Console Output

Started by user Julio Nunes Avelar
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/Risco-5@2
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf Risco-5
[Pipeline] sh
+ git clone --recursive https://github.com/JN513/Risco-5.git Risco-5
Cloning into 'Risco-5'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/Risco-5@2/Risco-5
[Pipeline] {
[Pipeline] sh
+ iverilog -o simulation.out -g2005 -s soc_tb src/core/alu.v src/core/alu_control.v src/core/control_unit.v src/core/core.v src/core/csr_unit.v src/core/immediate_generator.v src/core/mdu.v src/core/mux.v src/core/pc.v src/core/registers.v tests/soc_test.v src/peripheral/bus.v src/peripheral/fifo.v src/peripheral/gpios.v src/peripheral/gpio.v src/peripheral/leds.v src/peripheral/memory.v src/peripheral/pwm.v src/peripheral/soc.v src/peripheral/uart_rx.v src/peripheral/uart_tx.v src/peripheral/uart.v
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
[Pipeline] lock
Trying to acquire lock on [Resource: colorlight_i9]
The resource [colorlight_i9] is locked by build Risco 5 #386 #386 since Oct 8, 2024, 8:48 PM.
[Resource: colorlight_i9] is not free, waiting for execution ...
[Required resources: [colorlight_i9]] added into queue at position 0
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_nexys4_ddr]
The resource [digilent_nexys4_ddr] is locked by build Risco 5 #386 #386 since Oct 8, 2024, 8:48 PM.
[Resource: digilent_nexys4_ddr] is not free, waiting for execution ...
[Required resources: [digilent_nexys4_ddr]] added into queue at position 1
Lock acquired on [Resource: colorlight_i9]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/Risco-5@2/Risco-5
[Pipeline] {
[Pipeline] echo
Iniciando síntese para FPGA colorlight_i9.
[Pipeline] sh
+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Risco-5 -b colorlight_i9
Lock acquired on [Resource: digilent_nexys4_ddr]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/Risco-5@2/Risco-5
[Pipeline] {
[Pipeline] echo
Iniciando síntese para FPGA digilent_nexys4_ddr.
[Pipeline] sh
+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Risco-5 -b digilent_nexys4_ddr
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/Risco-5@2/Risco-5/build_colorlight_i9.tcl
Makefile executado com sucesso.
Sa��da do Makefile:
/eda/oss-cad-suite/bin/yosys -c /var/lib/jenkins/workspace/Risco-5@2/Risco-5/build_colorlight_i9.tcl -DID=0x6a6a6a6a -DCLOCK_FREQ=25000000 -DMEMORY_SIZE=4096

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.45+139 (git sha1 4d581a97d, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)

-- Running command `read -define ID=0x6a6a6a6a CLOCK_FREQ=25000000 MEMORY_SIZE=4096' --

1. Executing Verilog-2005 frontend: /eda/processor-ci/rtl/Risco-5.v
Parsing Verilog input from `/eda/processor-ci/rtl/Risco-5.v' to AST representation.
Generating RTLIL representation for module `\processorci_top'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v
Parsing Verilog input from `/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v' to AST representation.
Generating RTLIL representation for module `\Alu'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu_control.v
Parsing Verilog input from `/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu_control.v' to AST representation.
Generating RTLIL representation for module `\ALU_Control'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v
Parsing Verilog input from `/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v' to AST representation.
Generating RTLIL representation for module `\Control_Unit'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v
Parsing Verilog input from `/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v' to AST representation.
Generating RTLIL representation for module `\Core'.
/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v:187: Warning: Identifier `\pc_source' is implicitly declared.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v
Parsing Verilog input from `/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v' to AST representation.
Generating RTLIL representation for module `\CSR_Unit'.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/immediate_generator.v
Parsing Verilog input from `/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/immediate_generator.v' to AST representation.
Generating RTLIL representation for module `\Immediate_Generator'.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v
Parsing Verilog input from `/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v' to AST representation.
Generating RTLIL representation for module `\MDU'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mux.v
Parsing Verilog input from `/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mux.v' to AST representation.
Generating RTLIL representation for module `\MUX'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/pc.v
Parsing Verilog input from `/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/pc.v' to AST representation.
Generating RTLIL representation for module `\PC'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v
Parsing Verilog input from `/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v' to AST representation.
Generating RTLIL representation for module `\Registers'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/uart.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/uart.v' to AST representation.
Generating RTLIL representation for module `\UART'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_rx'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tx'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/fifo.v
Parsing Verilog input from `/eda/processor-ci-controller/src/fifo.v' to AST representation.
Generating RTLIL representation for module `\FIFO'.
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/reset.v
Parsing Verilog input from `/eda/processor-ci-controller/src/reset.v' to AST representation.
Generating RTLIL representation for module `\ResetBootSystem'.
Successfully finished Verilog frontend.

17. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/clk_divider.v
Parsing Verilog input from `/eda/processor-ci-controller/src/clk_divider.v' to AST representation.
Generating RTLIL representation for module `\ClkDivider'.
Successfully finished Verilog frontend.

18. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/memory.v
Parsing Verilog input from `/eda/processor-ci-controller/src/memory.v' to AST representation.
Generating RTLIL representation for module `\Memory'.
Successfully finished Verilog frontend.

19. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/interpreter.v
Parsing Verilog input from `/eda/processor-ci-controller/src/interpreter.v' to AST representation.
Generating RTLIL representation for module `\Interpreter'.
Successfully finished Verilog frontend.

20. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/controller.v
Parsing Verilog input from `/eda/processor-ci-controller/src/controller.v' to AST representation.
Generating RTLIL representation for module `\Controller'.
Successfully finished Verilog frontend.

21. Executing SYNTH_ECP5 pass.

21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.

21.3. Executing HIERARCHY pass (managing design hierarchy).

21.3.1. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     \ResetBootSystem
Used module:     \Core
Used module:         \CSR_Unit
Used module:         \Immediate_Generator
Used module:         \Alu
Used module:         \ALU_Control
Used module:         \Control_Unit
Used module:         \Registers
Used module:         \MUX
Used module:         \MDU
Used module:         \PC
Used module:     \Controller
Used module:         \Memory
Used module:         \UART
Used module:             \uart_tx
Used module:             \uart_rx
Used module:             \FIFO
Used module:         \Interpreter
Used module:         \ClkDivider
Parameter \CYCLES = 20

21.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'.
Parameter \CYCLES = 20
Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'.
Parameter \BOOT_ADDRESS = 0

21.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'.
Parameter \BOOT_ADDRESS = 0
Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.
/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v:187: Warning: Identifier `\pc_source' is implicitly declared.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \WORD_SIZE_BY = 4
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

21.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\Controller'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \WORD_SIZE_BY = 4
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

21.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4

21.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4
Generating RTLIL representation for module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 12
Parameter \BUS_WIDTH = 32
Parameter \ID = 1
Parameter \RESET_CLK_CYCLES = 20

21.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 12
Parameter \BUS_WIDTH = 32
Parameter \ID = 1
Parameter \RESET_CLK_CYCLES = 20
Generating RTLIL representation for module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 12

21.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 12
Generating RTLIL representation for module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

21.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

21.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8

21.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

21.3.12. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:         \CSR_Unit
Used module:         \Immediate_Generator
Used module:         \Alu
Used module:         \ALU_Control
Used module:         \Control_Unit
Used module:         \Registers
Used module:         \MUX
Used module:         \MDU
Used module:         \PC
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         \Memory
Used module:         \UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \Interpreter
Used module:         \ClkDivider
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4

21.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4
Generating RTLIL representation for module `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20

21.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Generating RTLIL representation for module `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 32

21.3.15. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 32
Generating RTLIL representation for module `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider'.

21.3.16. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:         \CSR_Unit
Used module:         \Immediate_Generator
Used module:         \Alu
Used module:         \ALU_Control
Used module:         \Control_Unit
Used module:         \Registers
Used module:         \MUX
Used module:         \MDU
Used module:         \PC
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             \uart_tx
Used module:             \uart_rx
Used module:             \FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

21.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

21.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

21.3.19. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:         \CSR_Unit
Used module:         \Immediate_Generator
Used module:         \Alu
Used module:         \ALU_Control
Used module:         \Control_Unit
Used module:         \Registers
Used module:         \MUX
Used module:         \MDU
Used module:         \PC
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider

21.3.20. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:         \CSR_Unit
Used module:         \Immediate_Generator
Used module:         \Alu
Used module:         \ALU_Control
Used module:         \Control_Unit
Used module:         \Registers
Used module:         \MUX
Used module:         \MDU
Used module:         \PC
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'.
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'.
Removing unused module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'.
Removing unused module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'.
Removing unused module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'.
Removing unused module `\Controller'.
Removing unused module `\Interpreter'.
Removing unused module `\Memory'.
Removing unused module `\ClkDivider'.
Removing unused module `\ResetBootSystem'.
Removing unused module `\FIFO'.
Removing unused module `\uart_tx'.
Removing unused module `\uart_rx'.
Removing unused module `\UART'.
Removing unused module `\Core'.
Removed 15 unused modules.

21.4. Executing PROC pass (convert processes to netlists).

21.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$587'.
Found and cleaned up 1 empty switch in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$791'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$791'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:130$106'.
Cleaned up 3 empty switches.

21.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$694 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$646 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$588 in module TRELLIS_DPR16X4.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:36$971 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:25$963 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1164 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1162 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1154 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1151 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1145 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1140 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1135 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1126 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1113 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1111 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1103 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1089 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1083 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1078 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:57$1065 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:36$1056 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Marked 15 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/interpreter.v:116$1020 in module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
Removed 1 dead cases from process $proc$/eda/processor-ci-controller/modules/uart.v:203$1012 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:203$1012 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:187$1007 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:132$1002 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:74$997 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/memory.v:36$780 in module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/controller.v:113$769 in module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v:305$723 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Marked 2 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:33$170 in module Registers.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/pc.v:15$159 in module PC.
Removed 1 dead cases from process $proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mux.v:14$158 in module MUX.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mux.v:14$158 in module MUX.
Marked 5 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:88$121 in module MDU.
Marked 4 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:50$113 in module MDU.
Marked 2 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/immediate_generator.v:18$112 in module Immediate_Generator.
Marked 2 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:130$106 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:106$104 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:78$103 in module CSR_Unit.
Marked 5 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/reset.v:25$697 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:703$79 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:693$78 in module Control_Unit.
Marked 21 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:157$32 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:149$31 in module Control_Unit.
Removed 1 dead cases from process $proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu_control.v:9$23 in module ALU_Control.
Marked 4 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu_control.v:9$23 in module ALU_Control.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:26$3 in module Alu.
Removed a total of 3 dead cases.

21.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 17 redundant assignments.
Promoted 141 assignments to connections.

21.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$695'.
  Set init value: \Q = 1'0
Found init rule in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$996'.
  Set init value: \read_ptr = 6'000000
  Set init value: \write_ptr = 6'000000
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1166'.
  Set init value: \i = 0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1119'.
  Set init value: \i = 0
Found init rule in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1071'.
  Set init value: \clk_o_auto = 1'0
  Set init value: \clk_counter = 0
  Set init value: \pulse_counter = 0
Found init rule in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1049'.
  Set init value: \state = 8'00000000
  Set init value: \counter = 8'00000000
  Set init value: \read_buffer = 0
  Set init value: \timeout = 0
  Set init value: \accumulator = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1019'.
  Set init value: \read_data = 0
  Set init value: \read_response = 1'0
  Set init value: \write_response = 1'0
  Set init value: \uart_tx_en = 1'0
  Set init value: \tx_fifo_read = 1'0
  Set init value: \tx_fifo_write = 1'0
  Set init value: \rx_fifo_read = 1'0
  Set init value: \rx_fifo_write = 1'0
  Set init value: \uart_tx_data = 8'00000000
  Set init value: \tx_fifo_write_data = 8'00000000
  Set init value: \rx_fifo_write_data = 8'00000000
  Set init value: \counter_write = 3'000
  Set init value: \counter_read = 3'000
  Set init value: \state_read = 4'0000
  Set init value: \state_write = 4'0000
Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v:0$726'.
  Set init value: \instruction_register = 0
  Set init value: \memory_register = 0
  Set init value: \alu_out_register = 0
  Set init value: \register_data_1 = 0
  Set init value: \register_data_2 = 0
  Set init value: \pc_old = 0
Found init rule in `\PC.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/pc.v:0$162'.
  Set init value: \Output = 0
Found init rule in `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:0$157'.
  Set init value: \state_mul = 2'00
  Set init value: \state_div = 2'00
  Set init value: \Data_X = 0
  Set init value: \Data_Y = 0
  Set init value: \MUL_RD = 0
  Set init value: \acumulador = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:0$111'.
  Set init value: \mepc = 0
  Set init value: \mscratch = 0
  Set init value: \mcause = 0
  Set init value: \mtval = 0
  Set init value: \mtvec = 0
  Set init value: \mcycle = 64'0000000000000000000000000000000000000000000000000000000000000000
  Set init value: \minstret = 64'0000000000000000000000000000000000000000000000000000000000000000
  Set init value: \utime = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$704'.
  Set init value: \reset_o = 1'0
  Set init value: \state = 2'01
  Set init value: \counter = 6'000000
Found init rule in `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:0$80'.
  Set init value: \memory_read = 1'0
  Set init value: \memory_write = 1'0
  Set init value: \is_immediate = 1'0
  Set init value: \pc_write = 1'0
  Set init value: \ir_write = 1'0
  Set init value: \pc_source = 1'0
  Set init value: \reg_write = 1'0
  Set init value: \pc_write_cond = 1'0
  Set init value: \csr_write_enable = 1'0
  Set init value: \alu_input_selector = 1'0
  Set init value: \save_address = 1'0
  Set init value: \save_value = 1'0
  Set init value: \save_value_2 = 1'0
  Set init value: \save_write_value = 1'0
  Set init value: \control_memory_op = 1'0
  Set init value: \write_data_in = 1'0
  Set init value: \mdu_start = 1'0
  Set init value: \lorD = 2'00
  Set init value: \aluop = 2'00
  Set init value: \alu_src_a = 3'000
  Set init value: \alu_src_b = 3'000
  Set init value: \memory_to_reg = 3'000
  Set init value: \control_unit_memory_op = 3'010
  Set init value: \control_unit_aluop = 4'0000
  Set init value: \state = 6'000000
  Set init value: \nextstate = 6'000000

21.4.5. Executing PROC_ARST pass (detect async resets in processes).

21.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~151 debug messages>

21.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$695'.
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$694'.
     1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$646'.
     1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$645_EN[3:0]$652
     2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$645_DATA[3:0]$651
     3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$645_ADDR[3:0]$650
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$588'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$586_EN[3:0]$594
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$586_DATA[3:0]$593
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$586_ADDR[3:0]$592
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$587'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$996'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$971'.
     1/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$983
     2/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_DATA[7:0]$982
     3/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_ADDR[5:0]$981
     4/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$977
     5/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_DATA[7:0]$976
     6/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_ADDR[5:0]$975
     7/7: $0\write_ptr[5:0]
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$963'.
     1/2: $0\read_ptr[5:0]
     2/2: $0\read_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1166'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1164'.
     1/2: $0\rxd_reg_0[0:0]
     2/2: $0\rxd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1162'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1154'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1151'.
     1/1: $0\bit_sample[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1145'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1140'.
     1/11: $3\i[31:0]
     2/11: $0\recieved_data[7:0] [1]
     3/11: $0\recieved_data[7:0] [0]
     4/11: $0\recieved_data[7:0] [2]
     5/11: $0\recieved_data[7:0] [3]
     6/11: $0\recieved_data[7:0] [4]
     7/11: $0\recieved_data[7:0] [5]
     8/11: $0\recieved_data[7:0] [6]
     9/11: $0\recieved_data[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1135'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1126'.
     1/1: $0\uart_rx_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1119'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1113'.
     1/1: $0\txd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1111'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1103'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1089'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1083'.
     1/11: $3\i[31:0]
     2/11: $0\data_to_send[7:0] [1]
     3/11: $0\data_to_send[7:0] [0]
     4/11: $0\data_to_send[7:0] [2]
     5/11: $0\data_to_send[7:0] [3]
     6/11: $0\data_to_send[7:0] [4]
     7/11: $0\data_to_send[7:0] [5]
     8/11: $0\data_to_send[7:0] [6]
     9/11: $0\data_to_send[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1078'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1071'.
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1065'.
     1/1: $0\pulse_counter[31:0]
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1056'.
     1/2: $0\clk_counter[31:0]
     2/2: $0\clk_o_auto[0:0]
Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1049'.
Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
     1/28: $0\state[7:0]
     2/28: $0\reset_bus[0:0]
     3/28: $0\memory_write[0:0]
     4/28: $0\memory_read[0:0]
     5/28: $0\write_pulse[0:0]
     6/28: $0\core_reset[0:0]
     7/28: $0\communication_write[0:0]
     8/28: $0\communication_read[0:0]
     9/28: $0\temp_buffer[63:0]
    10/28: $0\accumulator[63:0]
    11/28: $0\timeout_counter[31:0]
    12/28: $0\timeout[31:0]
    13/28: $0\read_buffer[31:0]
    14/28: $0\communication_buffer[31:0]
    15/28: $0\num_of_positions[23:0]
    16/28: $0\num_of_pages[23:0]
    17/28: $0\return_state[7:0]
    18/28: $0\memory_page_number[23:0]
    19/28: $0\memory_mux_selector[0:0]
    20/28: $0\end_position[31:0]
    21/28: $0\memory_page_size[23:0]
    22/28: $0\bus_mode[0:0]
    23/28: $0\num_of_cycles_to_pulse[31:0]
    24/28: $0\core_clk_enable[0:0]
    25/28: $0\communication_write_data[31:0]
    26/28: $0\counter[7:0]
    27/28: $0\write_data[31:0]
    28/28: $0\address[31:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1019'.
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1012'.
     1/4: $0\tx_fifo_read[0:0]
     2/4: $0\uart_tx_en[0:0]
     3/4: $0\tx_fifo_read_state[1:0]
     4/4: $0\uart_tx_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1007'.
     1/2: $0\rx_fifo_write[0:0]
     2/2: $0\rx_fifo_write_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1002'.
     1/6: $0\tx_fifo_write[0:0]
     2/6: $0\write_response[0:0]
     3/6: $0\state_write[3:0]
     4/6: $0\counter_write[2:0]
     5/6: $0\write_data_buffer[31:0]
     6/6: $0\tx_fifo_write_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$997'.
     1/5: $0\read_response[0:0]
     2/5: $0\rx_fifo_read[0:0]
     3/5: $0\state_read[3:0]
     4/5: $0\counter_read[2:0]
     5/5: $0\read_data[31:0]
Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$790'.
Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$780'.
     1/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$789
     2/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_DATA[31:0]$788
     3/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_ADDR[31:0]$787
     4/4: $0\read_sync[31:0]
Creating decoders for process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$769'.
     1/1: $0\finish_execution[0:0]
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v:0$726'.
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v:305$723'.
     1/7: $0\alu_out_register[31:0]
     2/7: $0\register_data_2[31:0]
     3/7: $0\register_data_1[31:0]
     4/7: $0\memory_register[31:0]
     5/7: $0\mdu_out_reg[31:0]
     6/7: $0\pc_old[31:0]
     7/7: $0\instruction_register[31:0]
Creating decoders for process `\Registers.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:0$188'.
Creating decoders for process `\Registers.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:33$170'.
     1/9: $2$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$185
     2/9: $2$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_DATA[31:0]$184
     3/9: $2$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_ADDR[4:0]$183
     4/9: $2$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$186
     5/9: $1$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$177
     6/9: $1$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$181
     7/9: $1$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$180
     8/9: $1$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_DATA[31:0]$179
     9/9: $1$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_ADDR[4:0]$178
Creating decoders for process `\PC.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/pc.v:0$162'.
Creating decoders for process `\PC.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/pc.v:15$159'.
     1/1: $0\Output[31:0]
Creating decoders for process `\MUX.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mux.v:14$158'.
     1/1: $1\S[31:0]
Creating decoders for process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:0$157'.
Creating decoders for process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:88$121'.
     1/8: $0\state_div[1:0]
     2/8: $0\div_done[0:0]
     3/8: $0\divisor[63:0]
     4/8: $0\DIV_RD[31:0]
     5/8: $0\quociente_msk[31:0]
     6/8: $0\quociente[31:0]
     7/8: $0\dividendo[31:0]
     8/8: $0\negativo[0:0]
Creating decoders for process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:50$113'.
     1/6: $0\state_mul[1:0]
     2/6: $0\mul_done[0:0]
     3/6: $0\acumulador[63:0]
     4/6: $0\MUL_RD[31:0]
     5/6: $0\Data_Y[31:0]
     6/6: $0\Data_X[31:0]
Creating decoders for process `\Immediate_Generator.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/immediate_generator.v:18$112'.
     1/2: $2\immediate[31:0]
     2/2: $1\immediate[31:0]
Creating decoders for process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:0$111'.
Creating decoders for process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:130$106'.
     1/1: $0\minstret[63:0]
Creating decoders for process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:106$104'.
     1/7: $0\mcycle[63:0]
     2/7: $0\utime[63:0]
     3/7: $0\mtvec[31:0]
     4/7: $0\mtval[31:0]
     5/7: $0\mcause[31:0]
     6/7: $0\mscratch[31:0]
     7/7: $0\mepc[31:0]
Creating decoders for process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:78$103'.
     1/1: $0\csr_data_out[31:0]
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$704'.
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$697'.
     1/3: $0\counter[5:0]
     2/3: $0\state[1:0]
     3/3: $0\reset_o[0:0]
Creating decoders for process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:0$80'.
Creating decoders for process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:703$79'.
     1/2: $0\clear_hal_byte_one_block_option_2[2:0]
     2/2: $0\clear_hal_byte_one_block_option[2:0]
Creating decoders for process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:693$78'.
     1/1: $0\wb_filter[2:0]
Creating decoders for process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
     1/23: $0\mdu_start[0:0]
     2/23: $0\save_write_value[0:0]
     3/23: $0\write_data_in[0:0]
     4/23: $0\save_value_2[0:0]
     5/23: $0\save_value[0:0]
     6/23: $0\control_memory_op[0:0]
     7/23: $0\save_address[0:0]
     8/23: $0\control_unit_aluop[3:0]
     9/23: $0\alu_input_selector[0:0]
    10/23: $0\csr_write_enable[0:0]
    11/23: $0\is_immediate[0:0]
    12/23: $0\reg_write[0:0]
    13/23: $0\alu_src_a[2:0]
    14/23: $0\alu_src_b[2:0]
    15/23: $0\aluop[1:0]
    16/23: $0\pc_source[0:0]
    17/23: $0\memory_to_reg[2:0]
    18/23: $0\memory_write[0:0]
    19/23: $0\memory_read[0:0]
    20/23: $0\lorD[1:0]
    21/23: $0\ir_write[0:0]
    22/23: $0\pc_write[0:0]
    23/23: $0\pc_write_cond[0:0]
Creating decoders for process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:157$32'.
     1/21: $21\nextstate[5:0]
     2/21: $20\nextstate[5:0]
     3/21: $19\nextstate[5:0]
     4/21: $18\nextstate[5:0]
     5/21: $17\nextstate[5:0]
     6/21: $16\nextstate[5:0]
     7/21: $15\nextstate[5:0]
     8/21: $14\nextstate[5:0]
     9/21: $13\nextstate[5:0]
    10/21: $12\nextstate[5:0]
    11/21: $11\nextstate[5:0]
    12/21: $10\nextstate[5:0]
    13/21: $9\nextstate[5:0]
    14/21: $8\nextstate[5:0]
    15/21: $7\nextstate[5:0]
    16/21: $6\nextstate[5:0]
    17/21: $5\nextstate[5:0]
    18/21: $4\nextstate[5:0]
    19/21: $3\nextstate[5:0]
    20/21: $2\nextstate[5:0]
    21/21: $1\nextstate[5:0]
Creating decoders for process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:149$31'.
     1/1: $0\state[5:0]
Creating decoders for process `\ALU_Control.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu_control.v:9$23'.
     1/1: $0\aluop_out[3:0]
Creating decoders for process `\Alu.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:26$3'.
     1/1: $0\ALU_out_S[31:0]

21.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1135'.
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1078'.
No latch inferred for signal `\Registers.$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:22$163_EN' from process `\Registers.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:0$188'.
No latch inferred for signal `\MUX.\S' from process `\MUX.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mux.v:14$158'.
No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/immediate_generator.v:18$112'.
No latch inferred for signal `\CSR_Unit.\csr_data_out' from process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:78$103'.
No latch inferred for signal `\Control_Unit.\clear_hal_byte_one_block_option' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:703$79'.
No latch inferred for signal `\Control_Unit.\clear_hal_byte_one_block_option_2' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:703$79'.
No latch inferred for signal `\Control_Unit.\wb_filter' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:693$78'.
No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\is_immediate' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\is_immediate` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\csr_write_enable' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\csr_write_enable` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\alu_input_selector' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_input_selector` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\save_address' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_address` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\save_value' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\save_value_2' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value_2` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\save_write_value' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_write_value` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\control_memory_op' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_memory_op` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\write_data_in' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\write_data_in` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\mdu_start' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\mdu_start` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [0]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [1]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [2]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [2]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [0]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [1]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [2]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\control_unit_memory_op' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [0]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'1 for non-memory siginal `\Control_Unit.\control_unit_memory_op [1]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [2]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\control_unit_aluop' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [0]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [1]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [2]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [3]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:157$32'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [0]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:157$32`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [1]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:157$32`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [2]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:157$32`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [3]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:157$32`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [4]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:157$32`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [5]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:157$32`.
No latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu_control.v:9$23'.
No latch inferred for signal `\Alu.\ALU_out_S' from process `\Alu.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:26$3'.

21.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$694'.
  created $dff cell `$procdff$4122' with positive edge clock.
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$630_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$631_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$632_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$633_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$634_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$635_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$636_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$637_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$638_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$639_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$640_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$641_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$642_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$643_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$644_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$645_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$646'.
  created $dff cell `$procdff$4123' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$645_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$646'.
  created $dff cell `$procdff$4124' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$645_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$646'.
  created $dff cell `$procdff$4125' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$570_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$571_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$572_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$573_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$574_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$575_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$576_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$577_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$578_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$579_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$580_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$581_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$582_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$583_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$584_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$585_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$586_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$588'.
  created $dff cell `$procdff$4126' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$586_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$588'.
  created $dff cell `$procdff$4127' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$586_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$588'.
  created $dff cell `$procdff$4128' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$587'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$971'.
  created $dff cell `$procdff$4129' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$971'.
  created $dff cell `$procdff$4130' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$971'.
  created $dff cell `$procdff$4131' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$971'.
  created $dff cell `$procdff$4132' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_data' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$963'.
  created $dff cell `$procdff$4133' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$963'.
  created $dff cell `$procdff$4134' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1164'.
  created $dff cell `$procdff$4135' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1164'.
  created $dff cell `$procdff$4136' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1162'.
  created $dff cell `$procdff$4137' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1154'.
  created $dff cell `$procdff$4138' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1151'.
  created $dff cell `$procdff$4139' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1145'.
  created $dff cell `$procdff$4140' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1140'.
  created $dff cell `$procdff$4141' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1140'.
  created $dff cell `$procdff$4142' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1126'.
  created $dff cell `$procdff$4143' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1113'.
  created $dff cell `$procdff$4144' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1111'.
  created $dff cell `$procdff$4145' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1103'.
  created $dff cell `$procdff$4146' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1089'.
  created $dff cell `$procdff$4147' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1083'.
  created $dff cell `$procdff$4148' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1083'.
  created $dff cell `$procdff$4149' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\pulse_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1065'.
  created $dff cell `$procdff$4150' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_o_auto' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1056'.
  created $dff cell `$procdff$4151' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1056'.
  created $dff cell `$procdff$4152' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4153' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4154' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\address' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4155' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4156' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4157' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4158' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4159' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4160' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4161' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4162' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_clk_enable' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4163' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_reset' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4164' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_cycles_to_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4165' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\reset_bus' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4166' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\bus_mode' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4167' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_size' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4168' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\end_position' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4169' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_mux_selector' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4170' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_number' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4171' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\return_state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4172' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_pages' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4173' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_positions' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4174' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4175' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\read_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4176' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4177' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout_counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4178' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\accumulator' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4179' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\temp_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4180' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_en' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1012'.
  created $dff cell `$procdff$4181' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1012'.
  created $dff cell `$procdff$4182' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1012'.
  created $dff cell `$procdff$4183' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read_state' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1012'.
  created $dff cell `$procdff$4184' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1007'.
  created $dff cell `$procdff$4185' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1007'.
  created $dff cell `$procdff$4186' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1002'.
  created $dff cell `$procdff$4187' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1002'.
  created $dff cell `$procdff$4188' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1002'.
  created $dff cell `$procdff$4189' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_data_buffer' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1002'.
  created $dff cell `$procdff$4190' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1002'.
  created $dff cell `$procdff$4191' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1002'.
  created $dff cell `$procdff$4192' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$997'.
  created $dff cell `$procdff$4193' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$997'.
  created $dff cell `$procdff$4194' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$997'.
  created $dff cell `$procdff$4195' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$997'.
  created $dff cell `$procdff$4196' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$997'.
  created $dff cell `$procdff$4197' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_write_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$790'.
  created $dff cell `$procdff$4198' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_read_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$790'.
  created $dff cell `$procdff$4199' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\read_sync' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$780'.
  created $dff cell `$procdff$4200' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_ADDR' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$780'.
  created $dff cell `$procdff$4201' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_DATA' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$780'.
  created $dff cell `$procdff$4202' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$780'.
  created $dff cell `$procdff$4203' with positive edge clock.
Creating register for signal `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.\finish_execution' using process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$769'.
  created $dff cell `$procdff$4204' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v:305$723'.
  created $dff cell `$procdff$4205' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v:305$723'.
  created $dff cell `$procdff$4206' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v:305$723'.
  created $dff cell `$procdff$4207' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v:305$723'.
  created $dff cell `$procdff$4208' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v:305$723'.
  created $dff cell `$procdff$4209' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\pc_old' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v:305$723'.
  created $dff cell `$procdff$4210' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\mdu_out_reg' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v:305$723'.
  created $dff cell `$procdff$4211' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN' using process `\Registers.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:33$170'.
  created $dff cell `$procdff$4212' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_ADDR' using process `\Registers.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:33$170'.
  created $dff cell `$procdff$4213' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_DATA' using process `\Registers.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:33$170'.
  created $dff cell `$procdff$4214' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN' using process `\Registers.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:33$170'.
  created $dff cell `$procdff$4215' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN' using process `\Registers.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:33$170'.
  created $dff cell `$procdff$4216' with positive edge clock.
Creating register for signal `\PC.\Output' using process `\PC.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/pc.v:15$159'.
  created $dff cell `$procdff$4217' with positive edge clock.
Creating register for signal `\MDU.\div_done' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:88$121'.
  created $dff cell `$procdff$4218' with positive edge clock.
Creating register for signal `\MDU.\state_div' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:88$121'.
  created $dff cell `$procdff$4219' with positive edge clock.
Creating register for signal `\MDU.\negativo' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:88$121'.
  created $dff cell `$procdff$4220' with positive edge clock.
Creating register for signal `\MDU.\dividendo' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:88$121'.
  created $dff cell `$procdff$4221' with positive edge clock.
Creating register for signal `\MDU.\quociente' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:88$121'.
  created $dff cell `$procdff$4222' with positive edge clock.
Creating register for signal `\MDU.\quociente_msk' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:88$121'.
  created $dff cell `$procdff$4223' with positive edge clock.
Creating register for signal `\MDU.\DIV_RD' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:88$121'.
  created $dff cell `$procdff$4224' with positive edge clock.
Creating register for signal `\MDU.\divisor' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:88$121'.
  created $dff cell `$procdff$4225' with positive edge clock.
Creating register for signal `\MDU.\mul_done' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:50$113'.
  created $dff cell `$procdff$4226' with positive edge clock.
Creating register for signal `\MDU.\state_mul' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:50$113'.
  created $dff cell `$procdff$4227' with positive edge clock.
Creating register for signal `\MDU.\Data_X' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:50$113'.
  created $dff cell `$procdff$4228' with positive edge clock.
Creating register for signal `\MDU.\Data_Y' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:50$113'.
  created $dff cell `$procdff$4229' with positive edge clock.
Creating register for signal `\MDU.\MUL_RD' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:50$113'.
  created $dff cell `$procdff$4230' with positive edge clock.
Creating register for signal `\MDU.\acumulador' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:50$113'.
  created $dff cell `$procdff$4231' with positive edge clock.
Creating register for signal `\CSR_Unit.\minstret' using process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:130$106'.
  created $dff cell `$procdff$4232' with positive edge clock.
Creating register for signal `\CSR_Unit.\mepc' using process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:106$104'.
  created $dff cell `$procdff$4233' with positive edge clock.
Creating register for signal `\CSR_Unit.\mscratch' using process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:106$104'.
  created $dff cell `$procdff$4234' with positive edge clock.
Creating register for signal `\CSR_Unit.\mcause' using process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:106$104'.
  created $dff cell `$procdff$4235' with positive edge clock.
Creating register for signal `\CSR_Unit.\mtval' using process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:106$104'.
  created $dff cell `$procdff$4236' with positive edge clock.
Creating register for signal `\CSR_Unit.\mtvec' using process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:106$104'.
  created $dff cell `$procdff$4237' with positive edge clock.
Creating register for signal `\CSR_Unit.\mcycle' using process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:106$104'.
  created $dff cell `$procdff$4238' with positive edge clock.
Creating register for signal `\CSR_Unit.\utime' using process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:106$104'.
  created $dff cell `$procdff$4239' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$697'.
  created $dff cell `$procdff$4240' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$697'.
  created $dff cell `$procdff$4241' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$697'.
  created $dff cell `$procdff$4242' with positive edge clock.
Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:149$31'.
  created $dff cell `$procdff$4243' with positive edge clock.

21.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$695'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$694'.
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$694'.
Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$646'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$588'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$587'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$996'.
Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$971'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$971'.
Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$963'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$963'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1166'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1164'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1164'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1162'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1162'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1154'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1154'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1151'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1151'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1145'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1145'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1140'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1140'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1135'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1135'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1126'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1126'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1119'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1113'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1113'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1111'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1111'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1103'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1103'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1089'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1089'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1083'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1083'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1078'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1078'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1071'.
Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1065'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1065'.
Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1056'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1056'.
Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1049'.
Found and cleaned up 15 empty switches in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1019'.
Found and cleaned up 3 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1012'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1012'.
Found and cleaned up 2 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1007'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1007'.
Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1002'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1002'.
Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$997'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$997'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$790'.
Found and cleaned up 2 empty switches in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$780'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$780'.
Found and cleaned up 4 empty switches in `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$769'.
Removing empty process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$769'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v:0$726'.
Found and cleaned up 2 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v:305$723'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v:305$723'.
Removing empty process `Registers.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:0$188'.
Found and cleaned up 2 empty switches in `\Registers.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:33$170'.
Removing empty process `Registers.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:33$170'.
Removing empty process `PC.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/pc.v:0$162'.
Found and cleaned up 2 empty switches in `\PC.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/pc.v:15$159'.
Removing empty process `PC.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/pc.v:15$159'.
Found and cleaned up 1 empty switch in `\MUX.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mux.v:14$158'.
Removing empty process `MUX.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mux.v:14$158'.
Removing empty process `MDU.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:0$157'.
Found and cleaned up 6 empty switches in `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:88$121'.
Removing empty process `MDU.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:88$121'.
Found and cleaned up 4 empty switches in `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:50$113'.
Removing empty process `MDU.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:50$113'.
Found and cleaned up 2 empty switches in `\Immediate_Generator.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/immediate_generator.v:18$112'.
Removing empty process `Immediate_Generator.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/immediate_generator.v:18$112'.
Removing empty process `CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:0$111'.
Found and cleaned up 4 empty switches in `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:130$106'.
Removing empty process `CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:130$106'.
Found and cleaned up 3 empty switches in `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:106$104'.
Removing empty process `CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:106$104'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:78$103'.
Removing empty process `CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:78$103'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$704'.
Found and cleaned up 6 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$697'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$697'.
Removing empty process `Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:0$80'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:703$79'.
Removing empty process `Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:703$79'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:693$78'.
Removing empty process `Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:693$78'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Removing empty process `Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:357$65'.
Found and cleaned up 21 empty switches in `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:157$32'.
Removing empty process `Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:157$32'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:149$31'.
Removing empty process `Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:149$31'.
Found and cleaned up 5 empty switches in `\ALU_Control.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu_control.v:9$23'.
Removing empty process `ALU_Control.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu_control.v:9$23'.
Found and cleaned up 1 empty switch in `\Alu.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:26$3'.
Removing empty process `Alu.$proc$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:26$3'.
Cleaned up 151 empty switches.

21.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
<suppressed ~5 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
<suppressed ~21 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
<suppressed ~19 debug messages>
Optimizing module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
<suppressed ~9 debug messages>
Optimizing module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
<suppressed ~15 debug messages>
Optimizing module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
<suppressed ~24 debug messages>
Optimizing module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
<suppressed ~3 debug messages>
Optimizing module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
<suppressed ~26 debug messages>
Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
<suppressed ~6 debug messages>
Optimizing module Registers.
<suppressed ~2 debug messages>
Optimizing module PC.
<suppressed ~2 debug messages>
Optimizing module MUX.
<suppressed ~1 debug messages>
Optimizing module MDU.
<suppressed ~17 debug messages>
Optimizing module Immediate_Generator.
Optimizing module CSR_Unit.
<suppressed ~1 debug messages>
Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~8 debug messages>
Optimizing module Control_Unit.
<suppressed ~25 debug messages>
Optimizing module ALU_Control.
<suppressed ~4 debug messages>
Optimizing module Alu.
<suppressed ~1 debug messages>
Optimizing module processorci_top.

21.5. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Deleting now unused module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Deleting now unused module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
Deleting now unused module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Deleting now unused module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
Deleting now unused module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Deleting now unused module Registers.
Deleting now unused module PC.
Deleting now unused module MUX.
Deleting now unused module MDU.
Deleting now unused module Immediate_Generator.
Deleting now unused module CSR_Unit.
Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Deleting now unused module Control_Unit.
Deleting now unused module ALU_Control.
Deleting now unused module Alu.
<suppressed ~25 debug messages>

21.6. Executing TRIBUF pass.

21.7. Executing DEMINOUT pass (demote inout ports to input or output).

21.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~50 debug messages>

21.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 119 unused cells and 977 unused wires.
<suppressed ~161 debug messages>

21.10. Executing CHECK pass (checking for obvious problems).
Checking module processorci_top...
Warning: Wire processorci_top.\miso is used but has no driver.
Warning: Wire processorci_top.\intr is used but has no driver.
Warning: Wire processorci_top.\ResetBootSystem.start is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [31] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [30] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [29] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [28] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [27] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [26] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [25] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [24] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [23] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [22] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [21] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [20] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [19] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [18] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [17] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [16] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [15] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [14] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [13] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [12] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [11] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [10] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [9] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [8] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [7] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [6] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [5] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [4] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [3] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [2] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [1] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [0] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [31] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [30] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [29] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [28] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [27] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [26] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [25] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [24] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [23] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [22] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [21] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [20] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [19] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [18] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [17] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [16] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [15] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [14] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [13] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [12] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [11] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [10] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [9] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [8] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [7] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [6] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [5] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [4] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [3] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [2] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [1] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [0] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [31] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [30] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [29] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [28] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [27] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [26] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [25] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [24] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [23] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [22] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [21] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [20] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [19] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [18] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [17] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [16] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [15] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [14] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [13] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [12] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [11] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [10] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [9] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [8] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [7] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [6] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [5] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [4] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [3] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [2] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [1] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [0] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [31] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [30] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [29] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [28] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [27] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [26] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [25] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [24] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [23] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [22] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [21] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [20] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [19] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [18] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [17] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [16] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [15] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [14] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [13] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [12] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [11] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [10] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [9] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [8] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [7] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [6] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [5] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [4] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [3] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [2] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [1] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [0] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [31] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [30] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [29] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [28] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [27] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [26] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [25] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [24] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [23] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [22] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [21] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [20] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [19] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [18] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [17] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [16] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [15] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [14] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [13] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [12] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [11] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [10] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [9] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [8] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [7] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [6] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [5] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [4] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [3] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [2] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [1] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [0] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [31] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [30] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [29] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [28] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [27] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [26] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [25] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [24] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [23] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [22] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [21] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [20] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [19] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [18] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [17] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [16] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [15] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [14] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [13] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [12] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [11] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [10] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [9] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [8] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [7] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [6] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [5] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [4] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [3] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [2] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [1] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [0] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [31] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [30] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [29] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [28] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [27] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [26] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [25] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [24] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [23] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [22] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [21] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [20] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [19] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [18] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [17] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [16] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [15] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [14] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [13] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [12] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [11] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [10] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [9] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [8] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [7] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [6] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [5] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [4] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [3] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [2] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [1] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [0] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [31] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [30] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [29] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [28] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [27] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [26] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [25] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [24] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [23] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [22] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [21] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [20] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [19] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [18] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [17] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [16] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [15] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [14] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [13] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [12] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [11] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [10] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [9] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [8] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [7] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [6] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [5] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [4] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [3] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [2] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [31] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [30] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [29] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [28] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [27] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [26] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [25] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [24] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [23] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [22] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [21] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [20] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [19] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [18] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [17] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [16] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [15] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [14] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [13] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [12] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [11] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [10] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [9] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [8] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [7] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [6] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [5] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [4] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [3] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [2] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [1] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [0] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [31] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [30] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [29] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [28] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [27] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [26] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [25] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [24] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [23] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [22] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [21] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [20] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [19] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [18] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [17] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [16] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [15] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [14] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [13] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [12] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [11] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [10] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [9] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [8] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [7] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [6] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [5] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [4] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [3] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [2] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [1] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [0] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [1] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [0] is used but has no driver.
Found and reported 323 problems.

21.11. Executing OPT pass (performing simple optimizations).

21.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~11 debug messages>

21.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~1065 debug messages>
Removed a total of 355 cells.

21.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1194.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1200.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1206.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1194.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1200.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1206.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3313.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3322.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3338.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3357.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3359.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3377.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3398.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3422.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3450.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3480.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3513.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3549.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3587.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3636.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3687.
    dead port 1/2 on $mux $flatten\Core.\Control_Unit.$procmux$3740.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3742.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3795.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3797.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3849.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3910.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3912.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3974.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$4029.
    dead port 2/2 on $mux $flatten\Core.\Immediate_Generator.$procmux$2692.
    dead port 1/9 on $pmux $flatten\Core.\MemoryAddressMUX.$procmux$2529.
    dead port 2/9 on $pmux $flatten\Core.\MemoryAddressMUX.$procmux$2529.
    dead port 3/9 on $pmux $flatten\Core.\MemoryAddressMUX.$procmux$2529.
    dead port 4/9 on $pmux $flatten\Core.\MemoryAddressMUX.$procmux$2529.
    dead port 1/9 on $pmux $flatten\Core.\PCSourceMUX.$procmux$2529.
    dead port 2/9 on $pmux $flatten\Core.\PCSourceMUX.$procmux$2529.
    dead port 3/9 on $pmux $flatten\Core.\PCSourceMUX.$procmux$2529.
    dead port 4/9 on $pmux $flatten\Core.\PCSourceMUX.$procmux$2529.
    dead port 5/9 on $pmux $flatten\Core.\PCSourceMUX.$procmux$2529.
    dead port 6/9 on $pmux $flatten\Core.\PCSourceMUX.$procmux$2529.
    dead port 1/2 on $mux $flatten\Core.\RegisterBank.$procmux$2489.
    dead port 1/2 on $mux $flatten\Core.\RegisterBank.$procmux$2495.
    dead port 1/2 on $mux $flatten\Core.\RegisterBank.$procmux$2501.
    dead port 1/2 on $mux $flatten\Core.\RegisterBank.$procmux$2507.
Removed 45 multiplexer ports.
<suppressed ~166 debug messages>

21.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2372: $auto$opt_reduce.cc:134:opt_pmux$4275
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1191:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1191_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1191_Y [0]
      New connections: $flatten\Controller.\Uart.\RX_FIFO.$procmux$1191_Y [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1191_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1191:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1191_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1191_Y [0]
      New connections: $flatten\Controller.\Uart.\TX_FIFO.$procmux$1191_Y [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1191_Y [0] }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1630: $auto$opt_reduce.cc:134:opt_pmux$4277
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1654: $auto$opt_reduce.cc:134:opt_pmux$4279
    New ctrl vector for $pmux cell $flatten\Core.\CSR_Unit.$procmux$2767: { $flatten\Core.\CSR_Unit.$procmux$2784_CMP $flatten\Core.\CSR_Unit.$procmux$2781_CMP $flatten\Core.\CSR_Unit.$procmux$2779_CMP $flatten\Core.\CSR_Unit.$procmux$2778_CMP $flatten\Core.\CSR_Unit.$procmux$2777_CMP $flatten\Core.\CSR_Unit.$procmux$2722_CMP $flatten\Core.\CSR_Unit.$procmux$2749_CMP $flatten\Core.\CSR_Unit.$procmux$2760_CMP $flatten\Core.\CSR_Unit.$procmux$2739_CMP $flatten\Core.\CSR_Unit.$procmux$2730_CMP $auto$opt_reduce.cc:134:opt_pmux$4287 $auto$opt_reduce.cc:134:opt_pmux$4285 $auto$opt_reduce.cc:134:opt_pmux$4283 $auto$opt_reduce.cc:134:opt_pmux$4281 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1676: $auto$opt_reduce.cc:134:opt_pmux$4289
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1687: $auto$opt_reduce.cc:134:opt_pmux$4291
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$2832: { $flatten\Core.\Control_Unit.$procmux$2829_CMP $auto$opt_reduce.cc:134:opt_pmux$4293 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1735: $auto$opt_reduce.cc:134:opt_pmux$4295
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$2878: $auto$opt_reduce.cc:134:opt_pmux$4297
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3003: { $auto$opt_reduce.cc:134:opt_pmux$4301 $auto$opt_reduce.cc:134:opt_pmux$4299 }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3034: $auto$opt_reduce.cc:134:opt_pmux$4303
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1777: $auto$opt_reduce.cc:134:opt_pmux$4305
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1802: { $flatten\Controller.\Interpreter.$procmux$1570_CMP $auto$opt_reduce.cc:134:opt_pmux$4307 $flatten\Controller.\Interpreter.$procmux$1560_CMP }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3060: $auto$opt_reduce.cc:134:opt_pmux$4309
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3063: $auto$opt_reduce.cc:134:opt_pmux$4311
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3071: { $flatten\Core.\Control_Unit.$procmux$3013_CMP $auto$opt_reduce.cc:134:opt_pmux$4323 $auto$opt_reduce.cc:134:opt_pmux$4321 $auto$opt_reduce.cc:134:opt_pmux$4319 $auto$opt_reduce.cc:134:opt_pmux$4317 $auto$opt_reduce.cc:134:opt_pmux$4315 $auto$opt_reduce.cc:134:opt_pmux$4313 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1855: { $auto$opt_reduce.cc:134:opt_pmux$4327 $auto$opt_reduce.cc:134:opt_pmux$4325 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Data_Memory.$procmux$2440:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0]
      New connections: $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [31:1] = { $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3110: { $flatten\Core.\Control_Unit.$procmux$3100_CMP $auto$opt_reduce.cc:134:opt_pmux$4341 $auto$opt_reduce.cc:134:opt_pmux$4339 $auto$opt_reduce.cc:134:opt_pmux$4337 $flatten\Core.\Control_Unit.$procmux$3010_CMP $auto$opt_reduce.cc:134:opt_pmux$4335 $flatten\Core.\Control_Unit.$procmux$3007_CMP $flatten\Core.\Control_Unit.$procmux$3006_CMP $flatten\Core.\Control_Unit.$procmux$3005_CMP $flatten\Core.\Control_Unit.$procmux$3004_CMP $auto$opt_reduce.cc:134:opt_pmux$4333 $auto$opt_reduce.cc:134:opt_pmux$4331 $auto$opt_reduce.cc:134:opt_pmux$4329 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1924: $auto$opt_reduce.cc:134:opt_pmux$4343
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1949: { $flatten\Controller.\Interpreter.$procmux$1570_CMP $auto$opt_reduce.cc:134:opt_pmux$4345 $flatten\Controller.\Interpreter.$procmux$1560_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1977: { $flatten\Controller.\Interpreter.$procmux$1556_CMP $flatten\Controller.\Interpreter.$procmux$1549_CMP $flatten\Controller.\Interpreter.$procmux$1538_CMP $flatten\Controller.\Interpreter.$procmux$1532_CMP $auto$opt_reduce.cc:134:opt_pmux$4347 }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3148: { $auto$opt_reduce.cc:134:opt_pmux$4349 $flatten\Core.\Control_Unit.$procmux$3078_CMP }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3158: $auto$opt_reduce.cc:134:opt_pmux$4351
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3162: { $flatten\Core.\Control_Unit.$procmux$3069_CMP $auto$opt_reduce.cc:134:opt_pmux$4353 $flatten\Core.\Control_Unit.$procmux$3053_CMP $flatten\Core.\Control_Unit.$procmux$3064_CMP }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3182: $auto$opt_reduce.cc:134:opt_pmux$4355
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2009: { $auto$opt_reduce.cc:134:opt_pmux$4359 $auto$opt_reduce.cc:134:opt_pmux$4357 }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3207: $auto$opt_reduce.cc:134:opt_pmux$4361
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3229: { $auto$opt_reduce.cc:134:opt_pmux$4365 $auto$opt_reduce.cc:134:opt_pmux$4363 }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3294: $auto$opt_reduce.cc:134:opt_pmux$4367
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2091: { $flatten\Controller.\Interpreter.$procmux$1550_CMP $auto$opt_reduce.cc:134:opt_pmux$4369 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2102: { $flatten\Controller.\Interpreter.$procmux$1691_CMP $flatten\Controller.\Interpreter.$procmux$1590_CMP $auto$opt_reduce.cc:134:opt_pmux$4371 }
    New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2308: $auto$opt_reduce.cc:134:opt_pmux$4373
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2112: { $flatten\Controller.\Interpreter.$procmux$1589_CMP $auto$opt_reduce.cc:134:opt_pmux$4377 $auto$opt_reduce.cc:134:opt_pmux$4375 }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3963: { $auto$opt_reduce.cc:134:opt_pmux$4379 $flatten\Core.\Control_Unit.$procmux$3911_CMP $flatten\Core.\Control_Unit.$procmux$3970_CMP $flatten\Core.\Control_Unit.$procmux$3969_CMP $flatten\Core.\Control_Unit.$procmux$3968_CMP $flatten\Core.\Control_Unit.$procmux$3967_CMP $flatten\Core.\Control_Unit.$procmux$3966_CMP $flatten\Core.\Control_Unit.$procmux$3965_CMP $flatten\Core.\Control_Unit.$procmux$3964_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1530: { $flatten\Controller.\Interpreter.$procmux$1624_CMP $flatten\Controller.\Interpreter.$procmux$1620_CMP $flatten\Controller.\Interpreter.$procmux$1616_CMP $flatten\Controller.\Interpreter.$procmux$1590_CMP $flatten\Controller.\Interpreter.$procmux$1589_CMP $flatten\Controller.\Interpreter.$procmux$1585_CMP $flatten\Controller.\Interpreter.$procmux$1584_CMP $flatten\Controller.\Interpreter.$procmux$1580_CMP $flatten\Controller.\Interpreter.$procmux$1570_CMP $flatten\Controller.\Interpreter.$procmux$1566_CMP $auto$opt_reduce.cc:134:opt_pmux$4387 $flatten\Controller.\Interpreter.$procmux$1561_CMP $flatten\Controller.\Interpreter.$procmux$1560_CMP $auto$opt_reduce.cc:134:opt_pmux$4385 $flatten\Controller.\Interpreter.$procmux$1555_CMP $flatten\Controller.\Interpreter.$procmux$1554_CMP $flatten\Controller.\Interpreter.$procmux$1549_CMP $flatten\Controller.\Interpreter.$procmux$1545_CMP $flatten\Controller.\Interpreter.$procmux$1544_CMP $auto$opt_reduce.cc:134:opt_pmux$4383 $flatten\Controller.\Interpreter.$procmux$1538_CMP $flatten\Controller.\Interpreter.$procmux$1537_CMP $flatten\Controller.\Interpreter.$procmux$1536_CMP $auto$opt_reduce.cc:134:opt_pmux$4381 }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$4033: { $flatten\Core.\Control_Unit.$procmux$3214_CMP $flatten\Core.\Control_Unit.$procmux$3139_CMP $flatten\Core.\Control_Unit.$procmux$3105_CMP $flatten\Core.\Control_Unit.$procmux$3104_CMP $flatten\Core.\Control_Unit.$procmux$3212_CMP $flatten\Core.\Control_Unit.$procmux$3185_CMP $flatten\Core.\Control_Unit.$procmux$3077_CMP $auto$opt_reduce.cc:134:opt_pmux$4391 $flatten\Core.\Control_Unit.$procmux$3211_CMP $flatten\Core.\Control_Unit.$procmux$3017_CMP $flatten\Core.\Control_Unit.$procmux$3068_CMP $flatten\Core.\Control_Unit.$procmux$3102_CMP $flatten\Core.\Control_Unit.$procmux$3210_CMP $flatten\Core.\Control_Unit.$procmux$3016_CMP $flatten\Core.\Control_Unit.$procmux$3100_CMP $flatten\Core.\Control_Unit.$procmux$3209_CMP $flatten\Core.\Control_Unit.$procmux$3015_CMP $flatten\Core.\Control_Unit.$procmux$3014_CMP $flatten\Core.\Control_Unit.$procmux$3013_CMP $flatten\Core.\Control_Unit.$procmux$3012_CMP $flatten\Core.\Control_Unit.$procmux$3095_CMP $flatten\Core.\Control_Unit.$procmux$3094_CMP $flatten\Core.\Control_Unit.$procmux$3010_CMP $flatten\Core.\Control_Unit.$procmux$3009_CMP $auto$opt_reduce.cc:134:opt_pmux$4389 $flatten\Core.\Control_Unit.$procmux$3089_CMP $flatten\Core.\Control_Unit.$procmux$2880_CMP $flatten\Core.\Control_Unit.$procmux$3088_CMP $flatten\Core.\Control_Unit.$procmux$3208_CMP $flatten\Core.\Control_Unit.$procmux$3007_CMP $flatten\Core.\Control_Unit.$procmux$3006_CMP $flatten\Core.\Control_Unit.$procmux$3085_CMP $flatten\Core.\Control_Unit.$procmux$3005_CMP $flatten\Core.\Control_Unit.$procmux$3004_CMP $flatten\Core.\Control_Unit.$procmux$3082_CMP $flatten\Core.\Control_Unit.$procmux$2879_CMP $flatten\Core.\Control_Unit.$procmux$2845_CMP $flatten\Core.\Control_Unit.$procmux$3072_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2188: { $auto$opt_reduce.cc:134:opt_pmux$4393 $flatten\Controller.\Interpreter.$procmux$1589_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2212: { $flatten\Controller.\Interpreter.$procmux$1657_CMP $flatten\Controller.\Interpreter.$procmux$1656_CMP $auto$opt_reduce.cc:134:opt_pmux$4395 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2238: { $auto$opt_reduce.cc:134:opt_pmux$4397 $flatten\Controller.\Interpreter.$procmux$1656_CMP $flatten\Controller.\Interpreter.$procmux$1575_CMP $flatten\Controller.\Interpreter.$procmux$1570_CMP $flatten\Controller.\Interpreter.$procmux$1560_CMP }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Memory.$procmux$2440:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0]
      New connections: $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [31:1] = { $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] }
    New ctrl vector for $pmux cell $flatten\Core.\Immediate_Generator.$procmux$2695: { $flatten\Core.\Control_Unit.$procmux$3968_CMP $flatten\Core.\Control_Unit.$procmux$3969_CMP $auto$opt_reduce.cc:134:opt_pmux$4401 $flatten\Core.\Control_Unit.$procmux$3970_CMP $auto$opt_reduce.cc:134:opt_pmux$4399 $flatten\Core.\Control_Unit.$procmux$3964_CMP $flatten\Core.\Control_Unit.$procmux$3972_CMP }
    Consolidated identical input bits for $mux cell $flatten\Core.\RegisterBank.$procmux$2486:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\RegisterBank.$procmux$2486_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Core.\RegisterBank.$procmux$2486_Y [0]
      New connections: $flatten\Core.\RegisterBank.$procmux$2486_Y [31:1] = { $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Core.\RegisterBank.$procmux$2504:
      Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\Core.\RegisterBank.$procmux$2504_Y
      New ports: A=1'1, B=1'0, Y=$flatten\Core.\RegisterBank.$procmux$2504_Y [0]
      New connections: $flatten\Core.\RegisterBank.$procmux$2504_Y [31:1] = { $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Core.\RegisterBank.$procmux$2510:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171
      New ports: A=1'0, B=1'1, Y=$flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0]
      New connections: $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [31:1] = { $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] }
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1209:
      Old ports: A=$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$983, B=8'00000000, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974
      New ports: A=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1191_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0]
      New connections: $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1209:
      Old ports: A=$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$983, B=8'00000000, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974
      New ports: A=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1191_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0]
      New connections: $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] }
    Consolidated identical input bits for $mux cell $flatten\Core.\RegisterBank.$procmux$2513:
      Old ports: A=$flatten\Core.\RegisterBank.$2$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$186, B=0, Y=$flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175
      New ports: A=$flatten\Core.\RegisterBank.$procmux$2504_Y [0], B=1'0, Y=$flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0]
      New connections: $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [31:1] = { $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] }
    Consolidated identical input bits for $mux cell $flatten\Core.\RegisterBank.$procmux$2516:
      Old ports: A=$flatten\Core.\RegisterBank.$2$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$185, B=0, Y=$flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174
      New ports: A=$flatten\Core.\RegisterBank.$procmux$2486_Y [0], B=1'0, Y=$flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0]
      New connections: $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [31:1] = { $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] }
  Optimizing cells in module \processorci_top.
Performed a total of 51 changes.

21.11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~30 debug messages>
Removed a total of 10 cells.

21.11.6. Executing OPT_DFF pass (perform DFF optimizations).

21.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 425 unused wires.
<suppressed ~15 debug messages>

21.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.11.9. Rerunning OPT passes. (Maybe there is more to do..)

21.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~166 debug messages>

21.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1802: { $auto$opt_reduce.cc:134:opt_pmux$4307 $auto$opt_reduce.cc:134:opt_pmux$4403 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1949: { $auto$opt_reduce.cc:134:opt_pmux$4307 $auto$opt_reduce.cc:134:opt_pmux$4405 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2238: { $auto$opt_reduce.cc:134:opt_pmux$4397 $flatten\Controller.\Interpreter.$procmux$1656_CMP $flatten\Controller.\Interpreter.$procmux$1575_CMP $auto$opt_reduce.cc:134:opt_pmux$4407 }
    New ctrl vector for $pmux cell $flatten\Core.\Alu.$procmux$4107: { $flatten\Core.\Alu.$procmux$4121_CMP $flatten\Core.\Alu.$procmux$4120_CMP $flatten\Core.\Alu.$procmux$4119_CMP $flatten\Core.\Alu.$procmux$4118_CMP $auto$opt_reduce.cc:134:opt_pmux$4411 $flatten\Core.\Alu.$procmux$4115_CMP $flatten\Core.\Alu.$procmux$4114_CMP $flatten\Core.\Alu.$procmux$4113_CMP $flatten\Core.\Alu.$procmux$4112_CMP $flatten\Core.\Alu.$procmux$4111_CMP $flatten\Core.\Alu.$procmux$4110_CMP $auto$opt_reduce.cc:134:opt_pmux$4409 }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3110: { $flatten\Core.\Control_Unit.$procmux$3100_CMP $auto$opt_reduce.cc:134:opt_pmux$4341 $auto$opt_reduce.cc:134:opt_pmux$4339 $auto$opt_reduce.cc:134:opt_pmux$4337 $flatten\Core.\Control_Unit.$procmux$3010_CMP $auto$opt_reduce.cc:134:opt_pmux$4335 $auto$opt_reduce.cc:134:opt_pmux$4415 $auto$opt_reduce.cc:134:opt_pmux$4413 $auto$opt_reduce.cc:134:opt_pmux$4333 $auto$opt_reduce.cc:134:opt_pmux$4331 $auto$opt_reduce.cc:134:opt_pmux$4329 }
  Optimizing cells in module \processorci_top.
Performed a total of 5 changes.

21.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

21.11.13. Executing OPT_DFF pass (perform DFF optimizations).

21.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 2 unused wires.
<suppressed ~1 debug messages>

21.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.11.16. Rerunning OPT passes. (Maybe there is more to do..)

21.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~166 debug messages>

21.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

21.11.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.11.20. Executing OPT_DFF pass (perform DFF optimizations).

21.11.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.11.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.11.23. Finished OPT passes. (There is nothing left to do.)

21.12. Executing FSM pass (extract and optimize FSM).

21.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking processorci_top.Controller.Interpreter.return_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Found FSM state register processorci_top.Controller.Uart.i_uart_rx.fsm_state.
Not marking processorci_top.Controller.Uart.i_uart_tx.fsm_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Not marking processorci_top.Controller.Uart.state_read as FSM state register:
    Register has an initialization value.
Not marking processorci_top.Controller.Uart.state_write as FSM state register:
    Register has an initialization value.
Found FSM state register processorci_top.Controller.Uart.tx_fifo_read_state.
Not marking processorci_top.Core.CSR_Unit.utime as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Not marking processorci_top.Core.Control_Unit.state as FSM state register:
    Register has an initialization value.
Not marking processorci_top.Core.Mdu.state_div as FSM state register:
    Register has an initialization value.
Not marking processorci_top.Core.Mdu.state_mul as FSM state register:
    Register has an initialization value.
Not marking processorci_top.ResetBootSystem.state as FSM state register:
    Register has an initialization value.
    Circuit seems to be self-resetting.

21.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\Controller.Uart.i_uart_rx.fsm_state' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Controller.\Uart.\i_uart_rx.$procdff$4137
  root of input selection tree: $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1130_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1143_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1156_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1142_Y
  found state code: 3'000
  found ctrl input: \Controller.Uart.i_uart_rx.next_bit
  found state code: 3'011
  found ctrl input: \Controller.Uart.i_uart_rx.payload_done
  found state code: 3'010
  found state code: 3'001
  found ctrl input: \Controller.Uart.i_uart_rx.rxd_reg
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1156_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1147_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1143_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1142_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1130_Y
  ctrl inputs: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.rxd_reg \Controller.Uart.i_uart_rx.next_bit \Controller.Uart.i_uart_rx.payload_done }
  ctrl outputs: { $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1130_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1142_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1143_Y $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1147_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1156_Y $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] }
  transition:      3'000 4'00-- ->      3'001 8'01010001
  transition:      3'000 4'01-- ->      3'000 8'01010000
  transition:      3'000 4'1--- ->      3'000 8'01010000
  transition:      3'010 4'0--0 ->      3'010 8'00100010
  transition:      3'010 4'0--1 ->      3'011 8'00100011
  transition:      3'010 4'1--- ->      3'000 8'00100000
  transition:      3'001 4'0-0- ->      3'001 8'00011001
  transition:      3'001 4'0-1- ->      3'010 8'00011010
  transition:      3'001 4'1--- ->      3'000 8'00011000
  transition:      3'011 4'0-0- ->      3'011 8'10010011
  transition:      3'011 4'0-1- ->      3'000 8'10010000
  transition:      3'011 4'1--- ->      3'000 8'10010000
Extracting FSM `\Controller.Uart.tx_fifo_read_state' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Controller.\Uart.$procdff$4184
  root of input selection tree: $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0]
  found reset state: 2'00 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\Controller.\Uart.$procmux$2269_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2264_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2271_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2258_CMP
  found state code: 2'00
  found state code: 2'11
  found state code: 2'10
  found ctrl input: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1016_Y
  found state code: 2'01
  found ctrl output: $flatten\Controller.\Uart.$procmux$2258_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2264_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2269_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2271_CMP
  ctrl inputs: { \ResetBootSystem.reset_o $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1016_Y }
  ctrl outputs: { $flatten\Controller.\Uart.$procmux$2271_CMP $flatten\Controller.\Uart.$procmux$2269_CMP $flatten\Controller.\Uart.$procmux$2264_CMP $flatten\Controller.\Uart.$procmux$2258_CMP $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] }
  transition:       2'00 2'00 ->       2'00 6'000100
  transition:       2'00 2'01 ->       2'01 6'000101
  transition:       2'00 2'1- ->       2'00 6'000100
  transition:       2'10 2'0- ->       2'11 6'001011
  transition:       2'10 2'1- ->       2'00 6'001000
  transition:       2'01 2'0- ->       2'10 6'100010
  transition:       2'01 2'1- ->       2'00 6'100000
  transition:       2'11 2'0- ->       2'00 6'010000
  transition:       2'11 2'1- ->       2'00 6'010000

21.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$4423' from module `\processorci_top'.
  Merging pattern 2'0- and 2'1- from group (3 0 6'010000).
  Merging pattern 2'1- and 2'0- from group (3 0 6'010000).
Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$4416' from module `\processorci_top'.

21.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 15 unused cells and 15 unused wires.
<suppressed ~16 debug messages>

21.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$4416' from module `\processorci_top'.
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2].
Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$4423' from module `\processorci_top'.
  Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [0].
  Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [1].
  Removing unused output signal $flatten\Controller.\Uart.$procmux$2269_CMP.
  Removing unused output signal $flatten\Controller.\Uart.$procmux$2271_CMP.

21.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$4416' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---
Recoding FSM `$fsm$\Controller.Uart.tx_fifo_read_state$4423' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00 -> ---1
  10 -> --1-
  01 -> -1--
  11 -> 1---

21.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$4416' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Controller.Uart.i_uart_rx.fsm_state$4416 (\Controller.Uart.i_uart_rx.fsm_state):

  Number of input signals:    4
  Number of output signals:   5
  Number of state bits:       4

  Input signals:
    0: \Controller.Uart.i_uart_rx.payload_done
    1: \Controller.Uart.i_uart_rx.next_bit
    2: \Controller.Uart.i_uart_rx.rxd_reg
    3: \ResetBootSystem.reset_o

  Output signals:
    0: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1156_Y
    1: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1147_Y
    2: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1143_Y
    3: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1142_Y
    4: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1130_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 4'01--   ->     0 5'01010
      1:     0 4'1---   ->     0 5'01010
      2:     0 4'00--   ->     2 5'01010
      3:     1 4'1---   ->     0 5'00100
      4:     1 4'0--0   ->     1 5'00100
      5:     1 4'0--1   ->     3 5'00100
      6:     2 4'1---   ->     0 5'00011
      7:     2 4'0-1-   ->     1 5'00011
      8:     2 4'0-0-   ->     2 5'00011
      9:     3 4'0-1-   ->     0 5'10010
     10:     3 4'1---   ->     0 5'10010
     11:     3 4'0-0-   ->     3 5'10010

-------------------------------------

FSM `$fsm$\Controller.Uart.tx_fifo_read_state$4423' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Controller.Uart.tx_fifo_read_state$4423 (\Controller.Uart.tx_fifo_read_state):

  Number of input signals:    2
  Number of output signals:   2
  Number of state bits:       4

  Input signals:
    0: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1016_Y
    1: \ResetBootSystem.reset_o

  Output signals:
    0: $flatten\Controller.\Uart.$procmux$2258_CMP
    1: $flatten\Controller.\Uart.$procmux$2264_CMP

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 2'00   ->     0 2'01
      1:     0 2'1-   ->     0 2'01
      2:     0 2'01   ->     2 2'01
      3:     1 2'1-   ->     0 2'10
      4:     1 2'0-   ->     3 2'10
      5:     2 2'1-   ->     0 2'00
      6:     2 2'0-   ->     1 2'00
      7:     3 2'--   ->     0 2'00

-------------------------------------

21.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$4416' from module `\processorci_top'.
Mapping FSM `$fsm$\Controller.Uart.tx_fifo_read_state$4423' from module `\processorci_top'.

21.13. Executing OPT pass (performing simple optimizations).

21.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~9 debug messages>

21.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.

21.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~164 debug messages>

21.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

21.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $flatten\ResetBootSystem.$procdff$4242 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$4240 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Adding SRST signal on $flatten\Core.\Pc.$procdff$4217 ($dff) from module processorci_top (D = $flatten\Core.\Pc.$procmux$2524_Y, Q = \Core.Pc.Output, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4511 ($sdff) from module processorci_top (D = \Core.Pc.Input, Q = \Core.Pc.Output).
Adding EN signal on $flatten\Core.\Mdu.$procdff$4231 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:74$118_Y, Q = \Core.Mdu.acumulador).
Adding SRST signal on $flatten\Core.\Mdu.$procdff$4230 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2651_Y, Q = \Core.Mdu.MUL_RD, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4518 ($sdff) from module processorci_top (D = $flatten\Core.\Mdu.$ternary$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:80$120_Y, Q = \Core.Mdu.MUL_RD).
Adding SRST signal on $flatten\Core.\Mdu.$procdff$4227 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2628_Y, Q = \Core.Mdu.state_mul, rval = 2'00).
Adding SRST signal on $flatten\Core.\Mdu.$procdff$4226 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2638_Y, Q = \Core.Mdu.mul_done, rval = 1'0).
Adding EN signal on $flatten\Core.\Mdu.$procdff$4225 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2560_Y, Q = \Core.Mdu.divisor).
Adding EN signal on $flatten\Core.\Mdu.$procdff$4224 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2571_Y, Q = \Core.Mdu.DIV_RD).
Adding EN signal on $flatten\Core.\Mdu.$procdff$4223 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2580_Y, Q = \Core.Mdu.quociente_msk).
Adding SRST signal on $flatten\Core.\Mdu.$procdff$4222 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2593_Y, Q = \Core.Mdu.quociente, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4545 ($sdff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2593_Y, Q = \Core.Mdu.quociente).
Adding EN signal on $flatten\Core.\Mdu.$procdff$4221 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2606_Y, Q = \Core.Mdu.dividendo).
Adding EN signal on $flatten\Core.\Mdu.$procdff$4220 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$or$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:99$141_Y, Q = \Core.Mdu.negativo).
Adding SRST signal on $flatten\Core.\Mdu.$procdff$4219 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2543_Y, Q = \Core.Mdu.state_div, rval = 2'00).
Adding SRST signal on $flatten\Core.\Mdu.$procdff$4218 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2553_Y, Q = \Core.Mdu.div_done, rval = 1'0).
Adding SRST signal on $flatten\Core.\Control_Unit.$procdff$4243 ($dff) from module processorci_top (D = \Core.Control_Unit.nextstate, Q = \Core.Control_Unit.state, rval = 6'000000).
Adding EN signal on $flatten\Core.\CSR_Unit.$procdff$4239 ($dff) from module processorci_top (D = 64'0000000000000000000000000000000000000000000000000000000000000000, Q = \Core.CSR_Unit.utime).
Adding SRST signal on $flatten\Core.\CSR_Unit.$procdff$4238 ($dff) from module processorci_top (D = $flatten\Core.\CSR_Unit.$add$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:116$105_Y, Q = \Core.CSR_Unit.mcycle, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding SRST signal on $flatten\Core.\CSR_Unit.$procdff$4237 ($dff) from module processorci_top (D = $flatten\Core.\CSR_Unit.$procmux$2723_Y, Q = \Core.CSR_Unit.mtvec, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4576 ($sdff) from module processorci_top (D = \Core.register_data_1, Q = \Core.CSR_Unit.mtvec).
Adding SRST signal on $flatten\Core.\CSR_Unit.$procdff$4236 ($dff) from module processorci_top (D = $flatten\Core.\CSR_Unit.$procmux$2731_Y, Q = \Core.CSR_Unit.mtval, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4580 ($sdff) from module processorci_top (D = \Core.register_data_1, Q = \Core.CSR_Unit.mtval).
Adding SRST signal on $flatten\Core.\CSR_Unit.$procdff$4235 ($dff) from module processorci_top (D = $flatten\Core.\CSR_Unit.$procmux$2740_Y, Q = \Core.CSR_Unit.mcause, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4584 ($sdff) from module processorci_top (D = \Core.register_data_1, Q = \Core.CSR_Unit.mcause).
Adding SRST signal on $flatten\Core.\CSR_Unit.$procdff$4234 ($dff) from module processorci_top (D = $flatten\Core.\CSR_Unit.$procmux$2750_Y, Q = \Core.CSR_Unit.mscratch, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4588 ($sdff) from module processorci_top (D = \Core.register_data_1, Q = \Core.CSR_Unit.mscratch).
Adding SRST signal on $flatten\Core.\CSR_Unit.$procdff$4233 ($dff) from module processorci_top (D = $flatten\Core.\CSR_Unit.$procmux$2761_Y, Q = \Core.CSR_Unit.mepc, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4592 ($sdff) from module processorci_top (D = { \Core.register_data_1 [31:2] 2'00 }, Q = \Core.CSR_Unit.mepc).
Adding SRST signal on $flatten\Core.\CSR_Unit.$procdff$4232 ($dff) from module processorci_top (D = $flatten\Core.\CSR_Unit.$procmux$2710_Y, Q = \Core.CSR_Unit.minstret, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4596 ($sdff) from module processorci_top (D = \Core.register_data_1, Q = \Core.CSR_Unit.minstret [63:32]).
Adding EN signal on $auto$ff.cc:266:slice$4596 ($sdff) from module processorci_top (D = $flatten\Core.\CSR_Unit.$procmux$2708_Y [31:0], Q = \Core.CSR_Unit.minstret [31:0]).
Adding EN signal on $flatten\Core.$procdff$4211 ($dff) from module processorci_top (D = \Core.mdu_out, Q = \Core.mdu_out_reg).
Adding SRST signal on $flatten\Core.$procdff$4210 ($dff) from module processorci_top (D = $flatten\Core.$procmux$2475_Y, Q = \Core.pc_old, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4610 ($sdff) from module processorci_top (D = \Core.Pc.Output, Q = \Core.pc_old).
Adding SRST signal on $flatten\Core.$procdff$4209 ($dff) from module processorci_top (D = \Core.register_data_2_out, Q = \Core.register_data_2, rval = 0).
Adding SRST signal on $flatten\Core.$procdff$4208 ($dff) from module processorci_top (D = \Core.register_data_1_out, Q = \Core.register_data_1, rval = 0).
Adding SRST signal on $flatten\Core.$procdff$4207 ($dff) from module processorci_top (D = \Core.Alu.ALU_out_S, Q = \Core.alu_out_register, rval = 0).
Adding SRST signal on $flatten\Core.$procdff$4206 ($dff) from module processorci_top (D = \Core.read_data, Q = \Core.memory_register, rval = 0).
Adding SRST signal on $flatten\Core.$procdff$4205 ($dff) from module processorci_top (D = $flatten\Core.$procmux$2480_Y, Q = \Core.instruction_register, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4616 ($sdff) from module processorci_top (D = \Core.read_data, Q = \Core.instruction_register).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$4149 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1480_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1474_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1465_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1456_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1447_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1438_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1420_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1429_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4618 ($sdff) from module processorci_top (D = \Controller.Uart.uart_tx_data [7], Q = \Controller.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$4618 ($sdff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1474_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1465_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1456_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1447_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1438_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1420_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1429_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$4147 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1396_Y, Q = \Controller.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$4623 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1396_Y, Q = \Controller.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$4146 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1385_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$4629 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1110_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$4145 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_tx.n_fsm_state, Q = \Controller.Uart.i_uart_tx.fsm_state, rval = 3'000).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$4144 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1374_Y, Q = \Controller.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$4634 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1374_Y, Q = \Controller.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$4143 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1363_Y, Q = \Controller.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4640 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.recieved_data, Q = \Controller.Uart.i_uart_rx.uart_rx_data).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$4141 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_rx.$procmux$1340_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1331_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1322_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1313_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1304_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1295_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1277_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1286_Y }, Q = \Controller.Uart.i_uart_rx.recieved_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4642 ($sdff) from module processorci_top (D = { \Controller.Uart.i_uart_rx.bit_sample \Controller.Uart.i_uart_rx.recieved_data [7:1] }, Q = \Controller.Uart.i_uart_rx.recieved_data).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$4140 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1259_Y, Q = \Controller.Uart.i_uart_rx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$4646 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1150_Y, Q = \Controller.Uart.i_uart_rx.bit_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$4139 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1254_Y, Q = \Controller.Uart.i_uart_rx.bit_sample, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4650 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg, Q = \Controller.Uart.i_uart_rx.bit_sample).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$4138 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1246_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$4652 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1161_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$4136 ($dff) from module processorci_top (D = \rx, Q = \Controller.Uart.i_uart_rx.rxd_reg_0, rval = 1'1).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$4135 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg_0, Q = \Controller.Uart.i_uart_rx.rxd_reg, rval = 1'1).
Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$4134 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1223_Y, Q = \Controller.Uart.TX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$4658 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$970_Y [5:0], Q = \Controller.Uart.TX_FIFO.read_ptr).
Adding EN signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$4133 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$967_DATA, Q = \Controller.Uart.TX_FIFO.read_data).
Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$4129 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1218_Y, Q = \Controller.Uart.TX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$4665 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$986_Y [5:0], Q = \Controller.Uart.TX_FIFO.write_ptr).
Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$4134 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1223_Y, Q = \Controller.Uart.RX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$4667 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$970_Y [5:0], Q = \Controller.Uart.RX_FIFO.read_ptr).
Adding EN signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$4133 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$967_DATA, Q = \Controller.Uart.RX_FIFO.read_data).
Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$4129 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1218_Y, Q = \Controller.Uart.RX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$4674 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$986_Y [5:0], Q = \Controller.Uart.RX_FIFO.write_ptr).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4197 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2394_Y, Q = \Controller.Uart.state_read, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$4676 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2394_Y, Q = \Controller.Uart.state_read).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4196 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2419_Y, Q = \Controller.Uart.counter_read, rval = 3'000).
Adding EN signal on $auto$ff.cc:266:slice$4680 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2419_Y, Q = \Controller.Uart.counter_read).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4195 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2383_Y, Q = \Controller.Uart.rx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4194 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2372_Y, Q = \Controller.Uart.read_response, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4193 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2434_Y, Q = \Controller.Uart.read_data, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4698 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2432_Y, Q = \Controller.Uart.read_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4192 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2316_Y, Q = \Controller.Uart.state_write, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$4704 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2316_Y, Q = \Controller.Uart.state_write).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4191 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2338_Y, Q = \Controller.Uart.counter_write, rval = 3'000).
Adding EN signal on $auto$ff.cc:266:slice$4708 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2338_Y, Q = \Controller.Uart.counter_write).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4190 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2352_Y, Q = \Controller.Uart.write_data_buffer, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4718 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2352_Y, Q = \Controller.Uart.write_data_buffer).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4189 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2366_Y, Q = \Controller.Uart.tx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4728 ($sdff) from module processorci_top (D = \Controller.Uart.write_data_buffer [31:24], Q = \Controller.Uart.tx_fifo_write_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4188 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2298_Y, Q = \Controller.Uart.tx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4187 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2308_Y, Q = \Controller.Uart.write_response, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4186 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2289_Y, Q = \Controller.Uart.rx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4742 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.uart_rx_data, Q = \Controller.Uart.rx_fifo_write_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4185 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2284_Y, Q = \Controller.Uart.rx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4183 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2279_Y, Q = \Controller.Uart.uart_tx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4745 ($sdff) from module processorci_top (D = \Controller.Uart.TX_FIFO.read_data, Q = \Controller.Uart.uart_tx_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4182 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2255_Y, Q = \Controller.Uart.tx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4181 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2263_Y, Q = \Controller.Uart.uart_tx_en, rval = 1'0).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4180 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1802_Y, Q = \Controller.Interpreter.temp_buffer).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4179 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1845_Y, Q = \Controller.Interpreter.accumulator, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4762 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1845_Y [63:8], Q = \Controller.Interpreter.accumulator [63:8]).
Adding EN signal on $auto$ff.cc:266:slice$4762 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1845_Y [7:0], Q = \Controller.Interpreter.accumulator [7:0]).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4178 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1855_Y, Q = \Controller.Interpreter.timeout_counter, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4777 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1855_Y, Q = \Controller.Interpreter.timeout_counter).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4177 ($dff) from module processorci_top (D = { 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, Q = \Controller.Interpreter.timeout).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4176 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1896_Y, Q = \Controller.Interpreter.read_buffer).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4175 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1924_Y, Q = \Controller.Interpreter.communication_buffer, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4793 ($sdff) from module processorci_top (D = \Controller.Uart.read_data, Q = \Controller.Interpreter.communication_buffer).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4174 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1949_Y, Q = \Controller.Interpreter.num_of_positions).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4173 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1971_Y, Q = \Controller.Interpreter.num_of_pages, rval = 24'000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4804 ($sdff) from module processorci_top (D = \Controller.Interpreter.communication_buffer [31:8], Q = \Controller.Interpreter.num_of_pages).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4172 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1977_Y, Q = \Controller.Interpreter.return_state, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4806 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1977_Y, Q = \Controller.Interpreter.return_state).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4171 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2001_Y, Q = \Controller.Interpreter.memory_page_number).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4170 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2009_Y, Q = \Controller.Interpreter.memory_mux_selector, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4821 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2009_Y, Q = \Controller.Interpreter.memory_mux_selector).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4169 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2049_Y, Q = \Controller.Interpreter.end_position, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4825 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2049_Y, Q = \Controller.Interpreter.end_position).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4167 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2091_Y, Q = \Controller.Interpreter.bus_mode, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4829 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2091_Y, Q = \Controller.Interpreter.bus_mode).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4166 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1630_Y, Q = \Controller.Interpreter.reset_bus, rval = 1'1).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4165 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2102_Y, Q = \Controller.Interpreter.num_of_cycles_to_pulse).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4164 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1735_Y, Q = \Controller.Interpreter.core_reset, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4163 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2112_Y, Q = \Controller.Interpreter.core_clk_enable, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4842 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2112_Y, Q = \Controller.Interpreter.core_clk_enable).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4162 ($dff) from module processorci_top (D = \Controller.Interpreter.read_buffer, Q = \Controller.Interpreter.communication_write_data).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4161 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1754_Y, Q = \Controller.Interpreter.communication_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4160 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1777_Y, Q = \Controller.Interpreter.communication_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4159 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1687_Y, Q = \Controller.Interpreter.write_pulse, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4158 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2188_Y, Q = \Controller.Interpreter.counter, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4858 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2188_Y, Q = \Controller.Interpreter.counter).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4157 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1530_Y, Q = \Controller.Interpreter.state, rval = 8'00000000).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4156 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2212_Y, Q = \Controller.Interpreter.write_data).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4155 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2238_Y, Q = \Controller.Interpreter.address).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4154 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1654_Y, Q = \Controller.Interpreter.memory_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4153 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1676_Y, Q = \Controller.Interpreter.memory_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\ClkDivider.$procdff$4150 ($dff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1504_Y, Q = \Controller.ClkDivider.pulse_counter, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4881 ($sdff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1504_Y, Q = \Controller.ClkDivider.pulse_counter).
Adding SRST signal on $flatten\Controller.$procdff$4204 ($dff) from module processorci_top (D = $flatten\Controller.$procmux$2455_Y, Q = \Controller.finish_execution, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4889 ($sdff) from module processorci_top (D = $flatten\Controller.$procmux$2455_Y, Q = \Controller.finish_execution).
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$4781 ($dffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$4781 ($dffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$4781 ($dffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$4781 ($dffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$4781 ($dffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$4781 ($dffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$4781 ($dffe) from module processorci_top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$4781 ($dffe) from module processorci_top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$4593 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$4593 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 33 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 34 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 35 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 36 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 37 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 38 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 39 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 40 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 41 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 42 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 43 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 44 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 45 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 46 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 47 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 48 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 49 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 50 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 51 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 52 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 53 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 54 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 55 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 56 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 57 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 58 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 59 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 60 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 61 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 62 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.
Setting constant 0-bit at position 63 on $auto$ff.cc:266:slice$4574 ($dffe) from module processorci_top.

21.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 174 unused cells and 179 unused wires.
<suppressed ~175 debug messages>

21.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~33 debug messages>

21.13.9. Rerunning OPT passes. (Maybe there is more to do..)

21.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~123 debug messages>

21.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$4648: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.fsm_state [3:2] \Controller.Uart.i_uart_rx.fsm_state [0] }
    New ctrl vector for $pmux cell $flatten\Core.\CSR_Unit.$procmux$2767: { $flatten\Core.\CSR_Unit.$procmux$2779_CMP $flatten\Core.\CSR_Unit.$procmux$2778_CMP $flatten\Core.\CSR_Unit.$procmux$2777_CMP $flatten\Core.\CSR_Unit.$procmux$2722_CMP $flatten\Core.\CSR_Unit.$procmux$2749_CMP $flatten\Core.\CSR_Unit.$procmux$2760_CMP $flatten\Core.\CSR_Unit.$procmux$2739_CMP $flatten\Core.\CSR_Unit.$procmux$2730_CMP $auto$opt_reduce.cc:134:opt_pmux$4287 $auto$opt_reduce.cc:134:opt_pmux$4285 $auto$opt_reduce.cc:134:opt_pmux$4283 $auto$opt_reduce.cc:134:opt_pmux$4281 }
  Optimizing cells in module \processorci_top.
Performed a total of 2 changes.

21.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~99 debug messages>
Removed a total of 33 cells.

21.13.13. Executing OPT_DFF pass (perform DFF optimizations).

21.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 3 unused cells and 36 unused wires.
<suppressed ~4 debug messages>

21.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.13.16. Rerunning OPT passes. (Maybe there is more to do..)

21.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~123 debug messages>

21.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

21.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.13.20. Executing OPT_DFF pass (perform DFF optimizations).

21.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.13.23. Finished OPT passes. (There is nothing left to do.)

21.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Data_Memory.$auto$proc_memwr.cc:45:proc_memwr$4245 (Controller.Data_Memory.memory).
Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$777 (Controller.Data_Memory.memory).
Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Memory.$auto$proc_memwr.cc:45:proc_memwr$4245 (Controller.Memory.memory).
Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$777 (Controller.Memory.memory).
Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$4244 (Controller.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$967 (Controller.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$4244 (Controller.Uart.TX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$967 (Controller.Uart.TX_FIFO.memory).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$4246 (Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$4248 (Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Core.\RegisterBank.$meminit$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:22$187 (Core.RegisterBank.registers).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$4463 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$4488 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$4501 ($ne).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$4438 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1068 ($gt).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:219$1025 ($eq).
Removed top 6 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1029 ($add).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1032 ($add).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1041 ($lt).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1046 ($eq).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1048 ($ge).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1531_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1532_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1534 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1536_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1537_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1538_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1539_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1540_CMP0 ($eq).
Removed top 5 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1542 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1544_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1545_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1547 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1549_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1550_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1554_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1555_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1556_CMP0 ($eq).
Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1558 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1560_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1561_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1562_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1564 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1566_CMP0 ($eq).
Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1568 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1570_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1571_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1572_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1573_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1574_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1575_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1576_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1578 ($mux).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1580_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1582 ($mux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1584_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1585_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1587 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1589_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1590_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1593_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1592 ($pmux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1594_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1595_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1596_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1597_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1598_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1599_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1600_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1601_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1602_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1603_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1604_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1605_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1606_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1607_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1608_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1609_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1610_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1611_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1612_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1613_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1614_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1615_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1616_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1618 ($mux).
Removed top 7 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1620_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1622 ($mux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1656_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1657_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1658_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1691_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1846_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1847_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1848_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1891_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2017_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2050_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2051_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2124_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2125_CMP0 ($eq).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:95$999 ($lt).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:159$1004 ($lt).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2303_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2309_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2310_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2322_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2324 ($mux).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2373_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2374_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2388_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2396_CMP0 ($eq).
Removed top 3 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2404 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1215 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1203 ($mux).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$987 ($sub).
Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$987 ($sub).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$986 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$985 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$984 ($eq).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$970 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$969 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$968 ($eq).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1215 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1203 ($mux).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$987 ($sub).
Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$987 ($sub).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$986 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$985 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$984 ($eq).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$970 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$969 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$968 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$4449 ($eq).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1139 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1138 ($mux).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1137 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1136 ($mux).
Removed top 2 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:110$1131 ($eq).
Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:108$1129 ($eq).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:152$1105 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:137$1097 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:135$1095 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1092 ($ne).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1091 ($ne).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:120$1087 ($eq).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1082 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1081 ($mux).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1080 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1079 ($mux).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:94$1075 ($eq).
Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:92$1073 ($eq).
Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Memory.$procmux$2446 ($mux).
Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Data_Memory.$procmux$2446 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:96$754 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$738 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$737 ($mux).
Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$4884 ($ne).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$4894 ($ne).
Removed top 32 bits (of 64) from mux cell processorci_top.$flatten\Core.\CSR_Unit.$procmux$2708 ($mux).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Core.\CSR_Unit.$procmux$2722_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Core.\CSR_Unit.$procmux$2730_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Core.\CSR_Unit.$procmux$2739_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Core.\CSR_Unit.$procmux$2749_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Core.\CSR_Unit.$procmux$2760_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Core.\CSR_Unit.$procmux$2777_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Core.\Alu.$ternary$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:37$9 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Core.\Alu.$ternary$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:53$20 ($mux).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Core.\Alu.$procmux$4110_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Core.\Alu.$procmux$4117_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Core.\Alu.$procmux$4118_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Core.\Alu.$procmux$4119_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Core.\Alu.$procmux$4120_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Core.\ALU_Control.$procmux$4105_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.\ALU_Control.$procmux$4089_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.\ALU_Control.$procmux$4090_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Core.\ALU_Control.$procmux$4091_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell processorci_top.$flatten\Core.\ALU_Control.$procmux$4093 ($mux).
Removed top 1 bits (of 3) from mux cell processorci_top.$flatten\Core.\Control_Unit.$ternary$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:114$30 ($mux).
Removed top 5 bits (of 7) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$eq$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:197$34 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$eq$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:282$47 ($eq).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Core.\Control_Unit.$ternary$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:566$68 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Core.\Control_Unit.$ternary$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:586$74 ($mux).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$2829_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$2830_CMP0 ($eq).
Removed top 1 bits (of 3) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$2832 ($pmux).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3011_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3012_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3013_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3014_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3015_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3016_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3017_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3053_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3061_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3062_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3066_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3067_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3068_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3069_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3074_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3075_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3077_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3078_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3079_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3081_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3094_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3095_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3100_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3102_CMP0 ($eq).
Removed top 4 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3104_CMP0 ($eq).
Removed top 5 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3105_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3185_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3209_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3210_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3211_CMP0 ($eq).
Removed top 4 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3212_CMP0 ($eq).
Removed top 5 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3311 ($mux).
Removed top 5 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3336 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3396 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3448 ($mux).
Removed top 5 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3478 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3511 ($mux).
Removed top 1 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3547 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3585 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3634 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3685 ($mux).
Removed top 1 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3737 ($mux).
Removed top 1 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3793 ($mux).
Removed top 1 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3847 ($mux).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3911_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3966_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3967_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3970_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3972_CMP0 ($eq).
Removed top 32 bits (of 64) from port A of cell processorci_top.$flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:74$118 ($mul).
Removed top 32 bits (of 64) from port B of cell processorci_top.$flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:74$118 ($mul).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Core.\Mdu.$eq$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:109$142 ($eq).
Removed top 32 bits (of 64) from port Y of cell processorci_top.$flatten\Core.\Mdu.$sub$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:116$144 ($sub).
Removed top 32 bits (of 64) from port B of cell processorci_top.$flatten\Core.\Mdu.$sub$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:116$144 ($sub).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Core.\Mdu.$procmux$2544_CMP0 ($eq).
Removed top 1 bits (of 2) from mux cell processorci_top.$flatten\Core.\Mdu.$procmux$2546 ($mux).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Core.\Mdu.$procmux$2629_CMP0 ($eq).
Removed top 1 bits (of 2) from mux cell processorci_top.$flatten\Core.\Mdu.$procmux$2631 ($mux).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.\AluInputBMUX.$procmux$2534_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.\AluInputBMUX.$procmux$2535_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Core.\AluInputBMUX.$procmux$2536_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.\AluInputAMUX.$procmux$2534_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.\AluInputAMUX.$procmux$2535_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Core.\AluInputAMUX.$procmux$2536_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.\MemoryDataMUX.$procmux$2534_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.\MemoryDataMUX.$procmux$2535_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Core.\MemoryDataMUX.$procmux$2536_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Core.\MemoryAddressMUX.$procmux$2536_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Core.\CSR_Unit.$add$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:116$105 ($add).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\ResetBootSystem.$procmux$2798_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$702 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$701 ($add).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$701 ($add).
Removed top 27 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$700 ($lt).
Removed cell processorci_top.$flatten\Core.\CSR_Unit.$procmux$2705 ($mux).
Removed top 20 bits (of 32) from wire processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$737_Y.
Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_ADDR[31:0]$781.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1534_Y.
Removed top 5 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1542_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1547_Y.
Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1558_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1564_Y.
Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1568_Y.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1578_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1582_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1587_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1592_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1618_Y.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1622_Y.
Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_ADDR[31:0]$781.
Removed top 1 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2324_Y.
Removed top 3 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2404_Y.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_ADDR[5:0]$972.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_ADDR[5:0]$981.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$969_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$985_Y.
Removed top 28 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$970_Y.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_ADDR[5:0]$972.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_ADDR[5:0]$981.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$969_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$985_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$970_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$986_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1136_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1137_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1138_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1139_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1079_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1080_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1081_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1082_Y.
Removed top 1 bits (of 4) from wire processorci_top.$flatten\Core.\ALU_Control.$procmux$4093_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Core.\Alu.$eq$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:45$15_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Core.\Alu.$ternary$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:37$9_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Core.\Alu.$ternary$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:53$20_Y.
Removed top 32 bits (of 64) from wire processorci_top.$flatten\Core.\CSR_Unit.$procmux$2708_Y.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Core.\Control_Unit.$10\nextstate[5:0].
Removed top 1 bits (of 6) from wire processorci_top.$flatten\Core.\Control_Unit.$11\nextstate[5:0].
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Core.\Control_Unit.$12\nextstate[5:0].
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Core.\Control_Unit.$14\nextstate[5:0].
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Core.\Control_Unit.$16\nextstate[5:0].
Removed top 5 bits (of 6) from wire processorci_top.$flatten\Core.\Control_Unit.$19\nextstate[5:0].
Removed top 5 bits (of 6) from wire processorci_top.$flatten\Core.\Control_Unit.$21\nextstate[5:0].
Removed top 1 bits (of 6) from wire processorci_top.$flatten\Core.\Control_Unit.$5\nextstate[5:0].
Removed top 1 bits (of 6) from wire processorci_top.$flatten\Core.\Control_Unit.$6\nextstate[5:0].
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Core.\Control_Unit.$8\nextstate[5:0].
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Core.\Control_Unit.$ternary$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:586$74_Y.
Removed top 1 bits (of 2) from wire processorci_top.$flatten\Core.\Mdu.$procmux$2546_Y.
Removed top 1 bits (of 2) from wire processorci_top.$flatten\Core.\Mdu.$procmux$2631_Y.
Removed top 32 bits (of 64) from wire processorci_top.$flatten\Core.\Mdu.$sub$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:116$144_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$701_Y.

21.15. Executing PEEPOPT pass (run peephole optimizers).

21.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 57 unused wires.
<suppressed ~1 debug messages>

21.17. Executing SHARE pass (SAT-based resource sharing).
Found 6 cells in module processorci_top that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\Core.\RegisterBank.$memrd$\registers$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/registers.v:28$169 ($memrd):
    Found 12 activation_patterns using ctrl signal { $auto$opt_reduce.cc:134:opt_pmux$4409 $flatten\Core.\AluInputBMUX.$procmux$2534_CMP $flatten\Core.\Alu.$procmux$4121_CMP $flatten\Core.\Alu.$procmux$4120_CMP $flatten\Core.\Alu.$procmux$4119_CMP $flatten\Core.\Alu.$procmux$4118_CMP $flatten\Core.\Alu.$procmux$4115_CMP $flatten\Core.\Alu.$procmux$4114_CMP $flatten\Core.\Alu.$procmux$4113_CMP $flatten\Core.\Alu.$procmux$4112_CMP $flatten\Core.\Alu.$procmux$4111_CMP $flatten\Core.\Alu.$procmux$4110_CMP $auto$opt_reduce.cc:134:opt_pmux$4411 }.
    No candidates found.
  Analyzing resource sharing options for $flatten\Core.\Alu.$sshr$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:51$18 ($sshr):
    Found 1 activation_patterns using ctrl signal $flatten\Core.\Alu.$procmux$4110_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\Core.\Alu.$shr$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:49$17 ($shr):
    Found 1 activation_patterns using ctrl signal $flatten\Core.\Alu.$procmux$4111_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\Core.\Alu.$shl$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:47$16 ($shl):
    Found 1 activation_patterns using ctrl signal $flatten\Core.\Alu.$procmux$4112_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$777 ($memrd):
    Found 2 activation_patterns using ctrl signal { \Controller.Memory.memory_read $flatten\Controller.\Interpreter.$procmux$1574_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }.
    No candidates found.
  Analyzing resource sharing options for $flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$777 ($memrd):
    Found 1 activation_patterns using ctrl signal { \Controller.Data_Memory.memory_read $flatten\Controller.\Interpreter.$procmux$1574_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }.
    No candidates found.

21.18. Executing TECHMAP pass (map to technology primitives).

21.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

21.18.2. Continuing TECHMAP pass.
Using template $paramod$141b0f41d8ab4b936f42c52ead39f1f9a7c93200\_90_lut_cmp_ for cells of type $lt.
No more expansions possible.
<suppressed ~223 debug messages>

21.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 6 unused wires.
<suppressed ~1 debug messages>

21.21. Executing TECHMAP pass (map to technology primitives).

21.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

21.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.

21.21.3. Continuing TECHMAP pass.
Using template $paramod$e88c2150f27e199b5b4c38f191932e407250eaa3\_80_mul for cells of type $mul.
Using template $paramod$de927ffa49f2a1327665483e9418148a52f3d36b\_80_mul for cells of type $__mul.
Using template $paramod$fac210dc6e441ade6153a47dcf32d681f9d41bee\_80_mul for cells of type $__mul.
Using template $paramod$ba1b36458f074a6329f9cad9c8b71be8774bccea\_80_mul for cells of type $__mul.
Using template $paramod$f84b7e774a64cf6bd61391522b3eee9d216e6e7e\_80_mul for cells of type $__mul.
Using template $paramod$84e4af21b083f56ce59bb3210f4da5751fbe9bb3\_80_mul for cells of type $__mul.
Using template $paramod$0c59eac522c8fc6cf582c390b8c4bd5bae1bb887\_80_mul for cells of type $__mul.
Using template $paramod$7c1afd677c664a6f211892c24ab4c74153b5be67\$__MUL18X18 for cells of type $__MUL18X18.
Using template $paramod$bef2a6330e4e8c17c10f220fb2d17af741212f04\$__MUL18X18 for cells of type $__MUL18X18.
Using template $paramod$e5ade21dea2c4d51df0cdca72b2a93a08fd8e7d1\$__MUL18X18 for cells of type $__MUL18X18.
Using template $paramod$ab0a030b3329c9db46a487d220064a2a8467942a\$__MUL18X18 for cells of type $__MUL18X18.
No more expansions possible.
<suppressed ~670 debug messages>

21.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module processorci_top:
  creating $macc model for $techmap$flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:74$118.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4967 ($add).
  creating $macc model for $techmap$flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:74$118.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4964 ($add).
  creating $macc model for $techmap$flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:74$118.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$4961 ($add).
  creating $macc model for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1069 ($sub).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1024 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1028 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1029 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1032 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1039 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1043 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1031 ($sub).
  creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1006 ($add).
  creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1001 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$969 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$985 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$987 ($sub).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$969 ($add).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$985 ($add).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$987 ($sub).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1150 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1161 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1099 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1110 ($add).
  creating $macc model for $flatten\Core.$add$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v:167$712 ($add).
  creating $macc model for $flatten\Core.$sub$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v:165$711 ($sub).
  creating $macc model for $flatten\Core.\Alu.$add$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:33$6 ($add).
  creating $macc model for $flatten\Core.\Alu.$sub$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:35$7 ($sub).
  creating $macc model for $flatten\Core.\CSR_Unit.$add$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:116$105 ($add).
  creating $macc model for $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:127$150 ($neg).
  creating $macc model for $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:129$152 ($neg).
  creating $macc model for $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:97$126 ($neg).
  creating $macc model for $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:98$130 ($neg).
  creating $macc model for $flatten\Core.\Mdu.$sub$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:116$144 ($sub).
  creating $macc model for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$701 ($add).
  creating $alu model for $macc $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$701.
  creating $alu model for $macc $flatten\Core.\Mdu.$sub$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:116$144.
  creating $alu model for $macc $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:98$130.
  creating $alu model for $macc $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:97$126.
  creating $alu model for $macc $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:129$152.
  creating $alu model for $macc $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:127$150.
  creating $alu model for $macc $flatten\Core.\CSR_Unit.$add$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:116$105.
  creating $alu model for $macc $flatten\Core.\Alu.$sub$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:35$7.
  creating $alu model for $macc $flatten\Core.\Alu.$add$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:33$6.
  creating $alu model for $macc $flatten\Core.$sub$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v:165$711.
  creating $alu model for $macc $flatten\Core.$add$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v:167$712.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1110.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1099.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1161.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1150.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$987.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$985.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$969.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$987.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$985.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$969.
  creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1001.
  creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1006.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1031.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1043.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1039.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1032.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1029.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1028.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1024.
  creating $alu model for $macc $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1069.
  creating $alu model for $macc $techmap$flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:74$118.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$4961.
  creating $alu model for $macc $techmap$flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:74$118.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4964.
  creating $alu model for $macc $techmap$flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:74$118.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4967.
  creating $alu model for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1068 ($gt): new $alu
  creating $alu model for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1048 ($ge): new $alu
  creating $alu model for $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1041 ($lt): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1048.
  creating $alu model for $flatten\Core.\Alu.$ge$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:53$19 ($ge): merged with $flatten\Core.\Alu.$sub$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:35$7.
  creating $alu model for $flatten\Core.\Alu.$lt$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:37$8 ($lt): merged with $flatten\Core.\Alu.$sub$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:35$7.
  creating $alu model for $flatten\Core.\Mdu.$le$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:115$143 ($le): new $alu
  creating $alu model for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$700 ($lt): new $alu
  creating $alu model for $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1046 ($eq): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1048.
  creating $alu model for $flatten\Core.\Alu.$eq$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:45$15 ($eq): merged with $flatten\Core.\Alu.$sub$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:35$7.
  creating $alu model for $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$702 ($eq): merged with $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$700.
  creating $alu cell for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$700, $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$702: $auto$alumacc.cc:485:replace_alu$4980
  creating $alu cell for $flatten\Core.\Mdu.$le$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:115$143: $auto$alumacc.cc:485:replace_alu$4991
  creating $alu cell for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1048, $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1041, $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1046: $auto$alumacc.cc:485:replace_alu$5004
  creating $alu cell for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1068: $auto$alumacc.cc:485:replace_alu$5017
  creating $alu cell for $techmap$flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:74$118.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4967: $auto$alumacc.cc:485:replace_alu$5022
  creating $alu cell for $techmap$flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:74$118.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4964: $auto$alumacc.cc:485:replace_alu$5025
  creating $alu cell for $techmap$flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:74$118.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$4961: $auto$alumacc.cc:485:replace_alu$5028
  creating $alu cell for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1069: $auto$alumacc.cc:485:replace_alu$5031
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1024: $auto$alumacc.cc:485:replace_alu$5034
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1028: $auto$alumacc.cc:485:replace_alu$5037
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1029: $auto$alumacc.cc:485:replace_alu$5040
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1032: $auto$alumacc.cc:485:replace_alu$5043
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1039: $auto$alumacc.cc:485:replace_alu$5046
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1043: $auto$alumacc.cc:485:replace_alu$5049
  creating $alu cell for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1031: $auto$alumacc.cc:485:replace_alu$5052
  creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1006: $auto$alumacc.cc:485:replace_alu$5055
  creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1001: $auto$alumacc.cc:485:replace_alu$5058
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$969: $auto$alumacc.cc:485:replace_alu$5061
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$985: $auto$alumacc.cc:485:replace_alu$5064
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$987: $auto$alumacc.cc:485:replace_alu$5067
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$969: $auto$alumacc.cc:485:replace_alu$5070
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$985: $auto$alumacc.cc:485:replace_alu$5073
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$987: $auto$alumacc.cc:485:replace_alu$5076
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1150: $auto$alumacc.cc:485:replace_alu$5079
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1161: $auto$alumacc.cc:485:replace_alu$5082
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1099: $auto$alumacc.cc:485:replace_alu$5085
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1110: $auto$alumacc.cc:485:replace_alu$5088
  creating $alu cell for $flatten\Core.$add$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v:167$712: $auto$alumacc.cc:485:replace_alu$5091
  creating $alu cell for $flatten\Core.$sub$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/core.v:165$711: $auto$alumacc.cc:485:replace_alu$5094
  creating $alu cell for $flatten\Core.\Alu.$add$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:33$6: $auto$alumacc.cc:485:replace_alu$5097
  creating $alu cell for $flatten\Core.\Alu.$sub$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:35$7, $flatten\Core.\Alu.$ge$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:53$19, $flatten\Core.\Alu.$lt$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:37$8, $flatten\Core.\Alu.$eq$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/alu.v:45$15: $auto$alumacc.cc:485:replace_alu$5100
  creating $alu cell for $flatten\Core.\CSR_Unit.$add$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/csr_unit.v:116$105: $auto$alumacc.cc:485:replace_alu$5113
  creating $alu cell for $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:127$150: $auto$alumacc.cc:485:replace_alu$5116
  creating $alu cell for $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:129$152: $auto$alumacc.cc:485:replace_alu$5119
  creating $alu cell for $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:97$126: $auto$alumacc.cc:485:replace_alu$5122
  creating $alu cell for $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:98$130: $auto$alumacc.cc:485:replace_alu$5125
  creating $alu cell for $flatten\Core.\Mdu.$sub$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/mdu.v:116$144: $auto$alumacc.cc:485:replace_alu$5128
  creating $alu cell for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$701: $auto$alumacc.cc:485:replace_alu$5131
  created 38 $alu and 0 $macc cells.

21.23. Executing OPT pass (performing simple optimizations).

21.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~4 debug messages>

21.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~123 debug messages>

21.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

21.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~12 debug messages>
Removed a total of 4 cells.

21.23.6. Executing OPT_DFF pass (perform DFF optimizations).

21.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 65 unused wires.
<suppressed ~1 debug messages>

21.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.23.9. Rerunning OPT passes. (Maybe there is more to do..)

21.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~123 debug messages>

21.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

21.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.23.13. Executing OPT_DFF pass (perform DFF optimizations).

21.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.23.16. Finished OPT passes. (There is nothing left to do.)

21.24. Executing MEMORY pass.

21.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

21.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

21.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing processorci_top.Controller.Data_Memory.memory write port 0.
  Analyzing processorci_top.Controller.Memory.memory write port 0.
  Analyzing processorci_top.Controller.Uart.RX_FIFO.memory write port 0.
  Analyzing processorci_top.Controller.Uart.TX_FIFO.memory write port 0.
  Analyzing processorci_top.Core.RegisterBank.registers write port 0.
  Analyzing processorci_top.Core.RegisterBank.registers write port 1.
  Analyzing processorci_top.Core.RegisterBank.registers write port 2.

21.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

21.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no output FF found.
Checking read port `\Controller.Memory.memory'[0] in module `\processorci_top': no output FF found.
Checking read port `\Controller.Uart.RX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\Controller.Uart.TX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\Core.RegisterBank.registers'[0] in module `\processorci_top': no output FF found.
Checking read port `\Core.RegisterBank.registers'[1] in module `\processorci_top': merging output FF to cell.
    Write port 0: don't care on collision.
    Write port 1: non-transparent.
    Write port 2: non-transparent.
Checking read port `\Core.RegisterBank.registers'[2] in module `\processorci_top': merging output FF to cell.
    Write port 0: don't care on collision.
    Write port 1: non-transparent.
    Write port 2: non-transparent.
Checking read port address `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no address FF found.
Checking read port address `\Controller.Memory.memory'[0] in module `\processorci_top': no address FF found.
Checking read port address `\Core.RegisterBank.registers'[0] in module `\processorci_top': address FF has fully-defined init value, not supported.

21.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 4 unused cells and 86 unused wires.
<suppressed ~9 debug messages>

21.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating read ports of memory processorci_top.Core.RegisterBank.registers by address:
Consolidating write ports of memory processorci_top.Core.RegisterBank.registers by address:
  Merging ports 0, 2 (address 5'00000).
Consolidating write ports of memory processorci_top.Core.RegisterBank.registers by address:
Consolidating write ports of memory processorci_top.Core.RegisterBank.registers using sat-based resource sharing:
  Checking group clocked with posedge \Core.CSR_Unit.clk, width 32: ports 0, 1.
  Common input cone for all EN signals: 14 cells.
  Size of unconstrained SAT problem: 110 variables, 305 clauses
  Merging port 1 into port 0.

21.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

21.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).

21.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory processorci_top.Controller.Data_Memory.memory via $__TRELLIS_DPR16X4_
mapping memory processorci_top.Controller.Memory.memory via $__TRELLIS_DPR16X4_
mapping memory processorci_top.Controller.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of processorci_top.Controller.Uart.RX_FIFO.memory: $\Controller.Uart.RX_FIFO.memory$rdreg[0]
mapping memory processorci_top.Controller.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of processorci_top.Controller.Uart.TX_FIFO.memory: $\Controller.Uart.TX_FIFO.memory$rdreg[0]
mapping memory processorci_top.Core.RegisterBank.registers via $__TRELLIS_DPR16X4_
Extracted data FF from read port 1 of processorci_top.Core.RegisterBank.registers: $\Core.RegisterBank.registers$rdreg[1]
Extracted data FF from read port 2 of processorci_top.Core.RegisterBank.registers: $\Core.RegisterBank.registers$rdreg[2]
<suppressed ~1178 debug messages>

21.27. Executing TECHMAP pass (map to technology primitives).

21.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

21.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.

21.27.3. Continuing TECHMAP pass.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$514fc941ac1ae997c717a8e6a1180ed8e0cf8fa9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~1107 debug messages>

21.28. Executing OPT pass (performing simple optimizations).

21.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~307 debug messages>

21.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

21.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $flatten\ResetBootSystem.$procdff$4241 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Adding SRST signal on $auto$ff.cc:266:slice$4814 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1043_Y, Q = \Controller.Interpreter.memory_page_number, rval = 24'000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4753 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1802_Y [1:0], Q = \Controller.Interpreter.temp_buffer [1:0]).
Adding SRST signal on $auto$ff.cc:266:slice$4536 ($dffe) from module processorci_top (D = \Core.Mdu.quociente_msk [31:1], Q = \Core.Mdu.quociente_msk [30:0], rval = 31'0000000000000000000000000000000).
Adding SRST signal on $auto$ff.cc:266:slice$4522 ($dffe) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2563_Y [63], Q = \Core.Mdu.divisor [63], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$4495 ($dffe) from module processorci_top (D = $flatten\ResetBootSystem.$procmux$2795_Y, Q = \ResetBootSystem.counter, rval = 6'000000).

21.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 9 unused cells and 7676 unused wires.
<suppressed ~10 debug messages>

21.28.5. Rerunning OPT passes. (Removed registers in this run.)

21.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~7 debug messages>

21.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$7691 ($sdffce) from module processorci_top (D = $auto$wreduce.cc:461:run$4954 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).
Adding SRST signal on $auto$ff.cc:266:slice$7690 ($dffe) from module processorci_top (D = \Core.Mdu.divisor [31:1], Q = \Core.Mdu.divisor [30:0], rval = 31'0000000000000000000000000000000).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$7689 ($sdffce) from module processorci_top.

21.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 7 unused cells and 10 unused wires.
<suppressed ~10 debug messages>

21.28.10. Rerunning OPT passes. (Removed registers in this run.)

21.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.28.13. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$7698 ($dffe) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2563_Y [62], Q = \Core.Mdu.divisor [62], rval = 1'0).

21.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.28.15. Rerunning OPT passes. (Removed registers in this run.)

21.28.16. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.28.17. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.28.18. Executing OPT_DFF pass (perform DFF optimizations).

21.28.19. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.28.20. Finished fast OPT passes.

21.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

21.30. Executing OPT pass (performing simple optimizations).

21.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $auto$memory_share.cc:453:consolidate_wr_using_sat$5235: $auto$rtlil.cc:2497:ReduceOr$5229 -> 1'1
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~81 debug messages>

21.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$7685: { $auto$opt_dff.cc:194:make_patterns_logic$7682 $auto$opt_dff.cc:194:make_patterns_logic$4756 $auto$opt_dff.cc:194:make_patterns_logic$4754 $auto$fsm_map.cc:74:implement_pattern_cache$4483 }
    Consolidated identical input bits for $mux cell $flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$737:
      Old ports: A=\Controller.core_address_memory [11:0], B={ \Controller.Interpreter.memory_page_number [5:0] \Controller.core_address_memory [5:0] }, Y=$auto$wreduce.cc:461:run$4899 [11:0]
      New ports: A=\Controller.core_address_memory [11:6], B=\Controller.Interpreter.memory_page_number [5:0], Y=$auto$wreduce.cc:461:run$4899 [11:6]
      New connections: $auto$wreduce.cc:461:run$4899 [5:0] = \Controller.core_address_memory [5:0]
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1542:
      Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$4902 [2:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$4902 [2] $auto$wreduce.cc:461:run$4902 [0] }
      New connections: $auto$wreduce.cc:461:run$4902 [1] = $auto$wreduce.cc:461:run$4902 [0]
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1547:
      Old ports: A=7'1010010, B=7'0010101, Y=$auto$wreduce.cc:461:run$4903 [6:0]
      New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$4903 [1:0]
      New connections: $auto$wreduce.cc:461:run$4903 [6:2] = { $auto$wreduce.cc:461:run$4903 [1] 3'010 $auto$wreduce.cc:461:run$4903 [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1558:
      Old ports: A=4'1100, B=4'0000, Y=$auto$wreduce.cc:461:run$4904 [3:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$4904 [2]
      New connections: { $auto$wreduce.cc:461:run$4904 [3] $auto$wreduce.cc:461:run$4904 [1:0] } = { $auto$wreduce.cc:461:run$4904 [2] 2'00 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1568:
      Old ports: A=4'1001, B=4'0000, Y=$auto$wreduce.cc:461:run$4906 [3:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$4906 [0]
      New connections: $auto$wreduce.cc:461:run$4906 [3:1] = { $auto$wreduce.cc:461:run$4906 [0] 2'00 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1582:
      Old ports: A=7'0000110, B=7'1010111, Y=$auto$wreduce.cc:461:run$4908 [6:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$4908 [0]
      New connections: $auto$wreduce.cc:461:run$4908 [6:1] = { $auto$wreduce.cc:461:run$4908 [0] 1'0 $auto$wreduce.cc:461:run$4908 [0] 3'011 }
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$1977:
      Old ports: A=8'00001011, B=302978816, Y=$flatten\Controller.\Interpreter.$procmux$1977_Y
      New ports: A=5'01011, B=20'10010011111011100000, Y=$flatten\Controller.\Interpreter.$procmux$1977_Y [4:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$1977_Y [7:5] = 3'000
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2102:
      Old ports: A={ 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, B={ 40'0000000000000000000000000001010000000000 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2102_Y
      New ports: A=\Controller.Interpreter.communication_buffer [31:8], B={ 24'000000000000000000010100 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2102_Y [23:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$2102_Y [31:24] = 8'00000000
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2112: $auto$opt_reduce.cc:134:opt_pmux$4377
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2316:
      Old ports: A=4'0000, B={ 1'0 $auto$wreduce.cc:461:run$4914 [2:0] 12'000100100011 }, Y=$flatten\Controller.\Uart.$procmux$2316_Y
      New ports: A=3'000, B={ $auto$wreduce.cc:461:run$4914 [2:0] 9'001010011 }, Y=$flatten\Controller.\Uart.$procmux$2316_Y [2:0]
      New connections: $flatten\Controller.\Uart.$procmux$2316_Y [3] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2324:
      Old ports: A=3'000, B=3'100, Y=$auto$wreduce.cc:461:run$4914 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$4914 [2]
      New connections: $auto$wreduce.cc:461:run$4914 [1:0] = 2'00
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2400:
      Old ports: A=4'0010, B=4'0100, Y=$flatten\Controller.\Uart.$procmux$2400_Y
      New ports: A=2'01, B=2'10, Y=$flatten\Controller.\Uart.$procmux$2400_Y [2:1]
      New connections: { $flatten\Controller.\Uart.$procmux$2400_Y [3] $flatten\Controller.\Uart.$procmux$2400_Y [0] } = 2'00
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_rx.$procmux$1358:
      Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$4927 [0] 1'0 $auto$wreduce.cc:461:run$4928 [1:0] 2'01 \Controller.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$4930 [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state
      New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$4927 [0] $auto$wreduce.cc:461:run$4928 [1:0] 1'1 \Controller.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$4930 [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state [1:0]
      New connections: \Controller.Uart.i_uart_rx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1139:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$4930 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$4930 [0]
      New connections: $auto$wreduce.cc:461:run$4930 [1] = $auto$wreduce.cc:461:run$4930 [0]
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_tx.$procmux$1495:
      Old ports: A=3'000, B={ 2'00 \Controller.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$4932 [1:0] 2'01 \Controller.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$4934 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state
      New ports: A=2'00, B={ 1'0 \Controller.Uart.uart_tx_en $auto$wreduce.cc:461:run$4932 [1:0] 1'1 \Controller.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$4934 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state [1:0]
      New connections: \Controller.Uart.i_uart_tx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1082:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$4934 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$4934 [0]
      New connections: $auto$wreduce.cc:461:run$4934 [1] = $auto$wreduce.cc:461:run$4934 [0]
    Consolidated identical input bits for $mux cell $flatten\Core.\ALU_Control.$procmux$4085:
      Old ports: A=4'1001, B=4'0011, Y=$flatten\Core.\ALU_Control.$procmux$4085_Y
      New ports: A=2'10, B=2'01, Y={ $flatten\Core.\ALU_Control.$procmux$4085_Y [3] $flatten\Core.\ALU_Control.$procmux$4085_Y [1] }
      New connections: { $flatten\Core.\ALU_Control.$procmux$4085_Y [2] $flatten\Core.\ALU_Control.$procmux$4085_Y [0] } = 2'01
    Consolidated identical input bits for $mux cell $flatten\Core.\ALU_Control.$procmux$4093:
      Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$4935 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$4935 [2]
      New connections: $auto$wreduce.cc:461:run$4935 [1:0] = 2'10
    Consolidated identical input bits for $pmux cell $flatten\Core.\Control_Unit.$procmux$3003:
      Old ports: A=4'0000, B=8'10001001, Y=\Core.control_unit_aluop
      New ports: A=2'00, B=4'1011, Y={ \Core.control_unit_aluop [3] \Core.control_unit_aluop [0] }
      New connections: \Core.control_unit_aluop [2:1] = 2'00
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3320:
      Old ports: A=6'101101, B=6'000000, Y=$flatten\Core.\Control_Unit.$20\nextstate[5:0]
      New ports: A=1'1, B=1'0, Y=$flatten\Core.\Control_Unit.$20\nextstate[5:0] [0]
      New connections: $flatten\Core.\Control_Unit.$20\nextstate[5:0] [5:1] = { $flatten\Core.\Control_Unit.$20\nextstate[5:0] [0] 1'0 $flatten\Core.\Control_Unit.$20\nextstate[5:0] [0] $flatten\Core.\Control_Unit.$20\nextstate[5:0] [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3355:
      Old ports: A=6'000000, B=6'100101, Y=$flatten\Core.\Control_Unit.$18\nextstate[5:0]
      New ports: A=1'0, B=1'1, Y=$flatten\Core.\Control_Unit.$18\nextstate[5:0] [0]
      New connections: $flatten\Core.\Control_Unit.$18\nextstate[5:0] [5:1] = { $flatten\Core.\Control_Unit.$18\nextstate[5:0] [0] 2'00 $flatten\Core.\Control_Unit.$18\nextstate[5:0] [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3511:
      Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$4942 [2:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$4942 [2] $auto$wreduce.cc:461:run$4942 [0] }
      New connections: $auto$wreduce.cc:461:run$4942 [1] = $auto$wreduce.cc:461:run$4942 [0]
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3547:
      Old ports: A=5'00000, B=5'10010, Y=$auto$wreduce.cc:461:run$4941 [4:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$4941 [1]
      New connections: { $auto$wreduce.cc:461:run$4941 [4:2] $auto$wreduce.cc:461:run$4941 [0] } = { $auto$wreduce.cc:461:run$4941 [1] 3'000 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3585:
      Old ports: A=3'110, B=3'000, Y=$auto$wreduce.cc:461:run$4940 [2:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$4940 [1]
      New connections: { $auto$wreduce.cc:461:run$4940 [2] $auto$wreduce.cc:461:run$4940 [0] } = { $auto$wreduce.cc:461:run$4940 [1] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3634:
      Old ports: A=3'101, B=3'000, Y=$flatten\Core.\Control_Unit.$9\nextstate[5:0] [2:0]
      New ports: A=1'1, B=1'0, Y=$flatten\Core.\Control_Unit.$9\nextstate[5:0] [0]
      New connections: $flatten\Core.\Control_Unit.$9\nextstate[5:0] [2:1] = { $flatten\Core.\Control_Unit.$9\nextstate[5:0] [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3737:
      Old ports: A=5'00101, B=5'11000, Y=$flatten\Core.\Control_Unit.$7\nextstate[5:0] [4:0]
      New ports: A=2'01, B=2'10, Y={ $flatten\Core.\Control_Unit.$7\nextstate[5:0] [3] $flatten\Core.\Control_Unit.$7\nextstate[5:0] [0] }
      New connections: { $flatten\Core.\Control_Unit.$7\nextstate[5:0] [4] $flatten\Core.\Control_Unit.$7\nextstate[5:0] [2:1] } = { $flatten\Core.\Control_Unit.$7\nextstate[5:0] [3] $flatten\Core.\Control_Unit.$7\nextstate[5:0] [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3793:
      Old ports: A=5'00011, B=5'10110, Y=$auto$wreduce.cc:461:run$4948 [4:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$4948 [2] $auto$wreduce.cc:461:run$4948 [0] }
      New connections: { $auto$wreduce.cc:461:run$4948 [4:3] $auto$wreduce.cc:461:run$4948 [1] } = { $auto$wreduce.cc:461:run$4948 [2] 2'01 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3908:
      Old ports: A=6'000110, B=6'101111, Y=$flatten\Core.\Control_Unit.$4\nextstate[5:0]
      New ports: A=1'0, B=1'1, Y=$flatten\Core.\Control_Unit.$4\nextstate[5:0] [0]
      New connections: $flatten\Core.\Control_Unit.$4\nextstate[5:0] [5:1] = { $flatten\Core.\Control_Unit.$4\nextstate[5:0] [0] 1'0 $flatten\Core.\Control_Unit.$4\nextstate[5:0] [0] 2'11 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$4027:
      Old ports: A=6'000000, B=6'101110, Y=$flatten\Core.\Control_Unit.$2\nextstate[5:0]
      New ports: A=1'0, B=1'1, Y=$flatten\Core.\Control_Unit.$2\nextstate[5:0] [1]
      New connections: { $flatten\Core.\Control_Unit.$2\nextstate[5:0] [5:2] $flatten\Core.\Control_Unit.$2\nextstate[5:0] [0] } = { $flatten\Core.\Control_Unit.$2\nextstate[5:0] [1] 1'0 $flatten\Core.\Control_Unit.$2\nextstate[5:0] [1] $flatten\Core.\Control_Unit.$2\nextstate[5:0] [1] 1'0 }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$4033: { $flatten\Core.\Control_Unit.$procmux$3214_CMP \Core.Control_Unit.ir_write $flatten\Core.\Control_Unit.$procmux$3105_CMP $flatten\Core.\Control_Unit.$procmux$3104_CMP $flatten\Core.\Control_Unit.$procmux$3212_CMP $flatten\Core.\Control_Unit.$procmux$3185_CMP $flatten\Core.\Control_Unit.$procmux$3077_CMP $auto$opt_reduce.cc:134:opt_pmux$4391 $flatten\Core.\Control_Unit.$procmux$3211_CMP $flatten\Core.\Control_Unit.$procmux$3017_CMP $flatten\Core.\Control_Unit.$procmux$3068_CMP $flatten\Core.\Control_Unit.$procmux$3102_CMP $flatten\Core.\Control_Unit.$procmux$3210_CMP $flatten\Core.\Control_Unit.$procmux$3016_CMP $flatten\Core.\Control_Unit.$procmux$3100_CMP $flatten\Core.\Control_Unit.$procmux$3209_CMP $flatten\Core.\Control_Unit.$procmux$3015_CMP $flatten\Core.\Control_Unit.$procmux$3013_CMP $flatten\Core.\Control_Unit.$procmux$3012_CMP $auto$opt_reduce.cc:134:opt_pmux$7704 $flatten\Core.\Control_Unit.$procmux$3094_CMP $flatten\Core.\Control_Unit.$procmux$3010_CMP $auto$opt_reduce.cc:134:opt_pmux$7702 $flatten\Core.\Control_Unit.$procmux$3089_CMP $flatten\Core.\Control_Unit.$procmux$2880_CMP $flatten\Core.\Control_Unit.$procmux$3088_CMP $flatten\Core.\Control_Unit.$procmux$3208_CMP $flatten\Core.\Control_Unit.$procmux$3007_CMP $flatten\Core.\Control_Unit.$procmux$3006_CMP $flatten\Core.\Control_Unit.$procmux$3085_CMP $flatten\Core.\Control_Unit.$procmux$3005_CMP $flatten\Core.\Control_Unit.$procmux$3004_CMP $flatten\Core.\Control_Unit.$procmux$3082_CMP $flatten\Core.\Control_Unit.$procmux$2879_CMP \Core.Mdu.start $flatten\Core.\Control_Unit.$procmux$3072_CMP }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$ternary$/var/lib/jenkins/workspace/Risco-5@2/Risco-5/src/core/control_unit.v:114$30:
      Old ports: A=2'11, B=2'01, Y=\Core.Control_Unit.second_block_write_src_b [1:0]
      New ports: A=1'1, B=1'0, Y=\Core.Control_Unit.second_block_write_src_b [1]
      New connections: \Core.Control_Unit.second_block_write_src_b [0] = 1'1
    Consolidated identical input bits for $pmux cell $flatten\Core.\Immediate_Generator.$procmux$2688:
      Old ports: A={ \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31:20] }, B={ \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24:20] 20'00000000000000000000 \Core.instruction_register [31:20] 27'000000000000000000000000000 \Core.instruction_register [24:20] }, Y=$flatten\Core.\Immediate_Generator.$2\immediate[31:0]
      New ports: A={ \Core.instruction_register [31] \Core.instruction_register [31:25] }, B={ \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] 1'0 \Core.instruction_register [31:25] 8'00000000 }, Y=$flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12:5]
      New connections: { $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [31:13] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [4:0] } = { $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] \Core.instruction_register [24:20] }
    Consolidated identical input bits for $mux cell $flatten\Core.\Mdu.$procmux$2560:
      Old ports: A={ 1'0 $flatten\Core.\Mdu.$procmux$2563_Y [62:31] 31'0000000000000000000000000000000 }, B={ 2'00 \Core.Mdu.divisor [62:1] }, Y=$flatten\Core.\Mdu.$procmux$2560_Y
      New ports: A={ $flatten\Core.\Mdu.$procmux$2563_Y [62:31] 31'0000000000000000000000000000000 }, B={ 1'0 \Core.Mdu.divisor [62:1] }, Y=$flatten\Core.\Mdu.$procmux$2560_Y [62:0]
      New connections: $flatten\Core.\Mdu.$procmux$2560_Y [63] = 1'0
    New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2806: { $flatten\ResetBootSystem.$procmux$2799_CMP $flatten\ResetBootSystem.$procmux$2798_CMP }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2809:
      Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2809_Y
      New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2809_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2809_Y [0] = 1'0
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$7701: { $flatten\Core.\Control_Unit.$procmux$3011_CMP $flatten\Core.\Control_Unit.$procmux$3009_CMP $flatten\Core.\Control_Unit.$procmux$3008_CMP }
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2394:
      Old ports: A=4'0000, B={ 3'000 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2400_Y 8'00010011 }, Y=$flatten\Controller.\Uart.$procmux$2394_Y
      New ports: A=3'000, B={ 2'00 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2400_Y [2:1] 7'0001011 }, Y=$flatten\Controller.\Uart.$procmux$2394_Y [2:0]
      New connections: $flatten\Controller.\Uart.$procmux$2394_Y [3] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3375:
      Old ports: A=6'100001, B=$flatten\Core.\Control_Unit.$18\nextstate[5:0], Y=$flatten\Core.\Control_Unit.$17\nextstate[5:0]
      New ports: A=2'01, B={ $flatten\Core.\Control_Unit.$18\nextstate[5:0] [0] $flatten\Core.\Control_Unit.$18\nextstate[5:0] [0] }, Y={ $flatten\Core.\Control_Unit.$17\nextstate[5:0] [2] $flatten\Core.\Control_Unit.$17\nextstate[5:0] [0] }
      New connections: { $flatten\Core.\Control_Unit.$17\nextstate[5:0] [5:3] $flatten\Core.\Control_Unit.$17\nextstate[5:0] [1] } = { $flatten\Core.\Control_Unit.$17\nextstate[5:0] [0] 3'000 }
    Consolidated identical input bits for $pmux cell $flatten\Core.\Control_Unit.$procmux$3963:
      Old ports: A=6'000000, B={ 6'000010 $flatten\Core.\Control_Unit.$4\nextstate[5:0] 42'001000001001001010001100001101001110001111 }, Y=$flatten\Core.\Control_Unit.$3\nextstate[5:0]
      New ports: A=5'00000, B={ 5'00010 $flatten\Core.\Control_Unit.$4\nextstate[5:0] [0] $flatten\Core.\Control_Unit.$4\nextstate[5:0] [0] 2'11 $flatten\Core.\Control_Unit.$4\nextstate[5:0] [0] 35'01000010010101001100011010111001111 }, Y={ $flatten\Core.\Control_Unit.$3\nextstate[5:0] [5] $flatten\Core.\Control_Unit.$3\nextstate[5:0] [3:0] }
      New connections: $flatten\Core.\Control_Unit.$3\nextstate[5:0] [4] = 1'0
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2815:
      Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2809_Y, Y=$flatten\ResetBootSystem.$procmux$2815_Y
      New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2809_Y [1], Y=$flatten\ResetBootSystem.$procmux$2815_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2815_Y [0] = 1'0
  Optimizing cells in module \processorci_top.
Performed a total of 44 changes.

21.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~12 debug messages>
Removed a total of 4 cells.

21.30.6. Executing OPT_DFF pass (perform DFF optimizations).

21.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1 unused cells and 5 unused wires.
<suppressed ~2 debug messages>

21.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~1 debug messages>

21.30.9. Rerunning OPT passes. (Maybe there is more to do..)

21.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~83 debug messages>

21.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3847:
      Old ports: A={ $auto$wreduce.cc:461:run$4948 [4] $auto$wreduce.cc:461:run$4948 [4] $auto$wreduce.cc:461:run$4948 [0] 1'0 $auto$wreduce.cc:461:run$4948 [0] }, B={ $auto$wreduce.cc:461:run$4948 [4] 1'0 $auto$wreduce.cc:461:run$4948 [4] 1'1 $auto$wreduce.cc:461:run$4948 [0] }, Y=$auto$wreduce.cc:461:run$4947 [4:0]
      New ports: A={ $auto$wreduce.cc:461:run$4948 [4] $auto$wreduce.cc:461:run$4948 [0] 1'0 }, B={ 1'0 $auto$wreduce.cc:461:run$4948 [4] 1'1 }, Y=$auto$wreduce.cc:461:run$4947 [3:1]
      New connections: { $auto$wreduce.cc:461:run$4947 [4] $auto$wreduce.cc:461:run$4947 [0] } = { $auto$wreduce.cc:461:run$4948 [4] $auto$wreduce.cc:461:run$4948 [0] }
  Optimizing cells in module \processorci_top.
Performed a total of 1 changes.

21.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.30.13. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$4633 ($sdff) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$4677 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$4705 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$4807 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$4807 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$4807 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$4834 ($dffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$4834 ($dffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$4834 ($dffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$4834 ($dffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$4834 ($dffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$4834 ($dffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$4834 ($dffe) from module processorci_top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$4834 ($dffe) from module processorci_top.

21.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

21.30.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~4 debug messages>

21.30.16. Rerunning OPT passes. (Maybe there is more to do..)

21.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~84 debug messages>

21.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1552:
      Old ports: A=8'00000100, B={ 3'000 \Controller.Interpreter.return_state [4:0] }, Y=$flatten\Controller.\Interpreter.$procmux$1552_Y
      New ports: A=5'00100, B=\Controller.Interpreter.return_state [4:0], Y=$flatten\Controller.\Interpreter.$procmux$1552_Y [4:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$1552_Y [7:5] = 3'000
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$1530:
      Old ports: A=8'00000000, B={ 7'0000000 $auto$wreduce.cc:461:run$4912 [0] 6'000000 $auto$wreduce.cc:461:run$4905 [1:0] 1'0 $auto$wreduce.cc:461:run$4910 [6:0] 14'00001101000011 $auto$wreduce.cc:461:run$4909 [1:0] 3'000 \Controller.Interpreter.return_state [4:0] 1'0 $auto$wreduce.cc:461:run$4908 [6] 1'0 $auto$wreduce.cc:461:run$4908 [6] 3'011 $auto$wreduce.cc:461:run$4908 [6] 7'0000011 \Controller.Uart.read_response 4'0000 $auto$wreduce.cc:461:run$4904 [3] 2'00 $auto$wreduce.cc:461:run$4904 [3] 6'000010 $auto$wreduce.cc:461:run$4905 [1:0] 20'00001000000010110000 $auto$wreduce.cc:461:run$4904 [3] $auto$wreduce.cc:461:run$4904 [3] 18'000000010100000100 $flatten\Controller.\Interpreter.$procmux$1552_Y 1'0 $auto$wreduce.cc:461:run$4903 [6] 3'010 $auto$wreduce.cc:461:run$4903 [2] $auto$wreduce.cc:461:run$4903 [6] $auto$wreduce.cc:461:run$4903 [2] 13'0001001100010 $auto$wreduce.cc:461:run$4902 [2:1] $auto$wreduce.cc:461:run$4902 [1] 31'0001011001010010000100000001000 $auto$wreduce.cc:461:run$4901 [0] 8'00000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1530_Y
      New ports: A=7'0000000, B={ 6'000000 $auto$wreduce.cc:461:run$4912 [0] 5'00000 $auto$wreduce.cc:461:run$4905 [1:0] $auto$wreduce.cc:461:run$4910 [6:0] 12'000110100011 $auto$wreduce.cc:461:run$4909 [1:0] 2'00 \Controller.Interpreter.return_state [4:0] $auto$wreduce.cc:461:run$4908 [6] 1'0 $auto$wreduce.cc:461:run$4908 [6] 3'011 $auto$wreduce.cc:461:run$4908 [6] 6'000011 \Controller.Uart.read_response 3'000 $auto$wreduce.cc:461:run$4904 [3] 2'00 $auto$wreduce.cc:461:run$4904 [3] 5'00010 $auto$wreduce.cc:461:run$4905 [1:0] 17'00010000001011000 $auto$wreduce.cc:461:run$4904 [3] $auto$wreduce.cc:461:run$4904 [3] 18'000000101000010000 $flatten\Controller.\Interpreter.$procmux$1552_Y [4:0] $auto$wreduce.cc:461:run$4903 [6] 3'010 $auto$wreduce.cc:461:run$4903 [2] $auto$wreduce.cc:461:run$4903 [6] $auto$wreduce.cc:461:run$4903 [2] 11'00100110010 $auto$wreduce.cc:461:run$4902 [2:1] $auto$wreduce.cc:461:run$4902 [1] 27'001011010100100010000001000 $auto$wreduce.cc:461:run$4901 [0] 7'0000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1530_Y [6:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$1530_Y [7] = 1'0
  Optimizing cells in module \processorci_top.
Performed a total of 2 changes.

21.30.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.30.20. Executing OPT_DFF pass (perform DFF optimizations).

21.30.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.30.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.30.23. Rerunning OPT passes. (Maybe there is more to do..)

21.30.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~84 debug messages>

21.30.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

21.30.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.30.27. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$4862 ($sdff) from module processorci_top.

21.30.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.30.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~1 debug messages>

21.30.30. Rerunning OPT passes. (Maybe there is more to do..)

21.30.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~84 debug messages>

21.30.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

21.30.33. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.30.34. Executing OPT_DFF pass (perform DFF optimizations).

21.30.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.30.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.30.37. Finished OPT passes. (There is nothing left to do.)

21.31. Executing TECHMAP pass (map to technology primitives).

21.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

21.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.

21.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $dffe.
Using template $paramod$824a2ca00d29d886599434cf8ea60471635f2955\_90_demux for cells of type $demux.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $bmux.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $reduce_or.
Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $logic_not.
Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_demux for cells of type $demux.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $lut.
Using extmapper simplemap for cells of type $or.
Using template $paramod$c04af8dbf0e5d1d69bbccb2c7bd8a93fc9ef54dc\_80_ecp5_alu for cells of type $alu.
Using template $paramod$8a99b868050f542c83270fc93de09787e35f2c64\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ecp5_alu for cells of type $alu.
Using template $paramod$039520c137afc9cd69dd56c3fb11a4e1fbe5f664\_80_ecp5_alu for cells of type $alu.
Using template $paramod$bdc78fe5225b43c64ccdf13e5eb67d9dcf228e8a\_80_ecp5_alu for cells of type $alu.
Using template $paramod$ff467a932a72bec5a93c27dba04bf3daba067451\_80_ecp5_alu for cells of type $alu.
Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu.
Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu.
Using template $paramod$79aa992f2eb7f354d4aaf651790713cf239111fa\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$c9511eeb847f2aa95252b1013477609463f67ee0\_80_ecp5_alu for cells of type $alu.
Using template $paramod$a7b312e4ba8fdc79d4c5e0789e4e6c41ea3896fb\_90_pmux for cells of type $pmux.
Using template $paramod$7a385d5b7a2e603dbc5beef838648775b433f248\_90_pmux for cells of type $pmux.
Using template $paramod$54a4503cc57b9df40b70c1899504d6aac2650719\_90_pmux for cells of type $pmux.
Using template $paramod$59b03ae2620a41577de8da5f5c97b2919e82362b\_90_pmux for cells of type $pmux.
Using template $paramod$24fb226dd75c9d3f6955ec2ad61d794776778cf6\_90_pmux for cells of type $pmux.
Using template $paramod$cc1e387d9d5ac1d3f6e6bed180038d9c0ac48d0c\_90_pmux for cells of type $pmux.
Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux.
Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $sdffce.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using template $paramod$ac45afa5bcd8e16ca475cce13f9d19bb109f1516\_80_ecp5_alu for cells of type $alu.
Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux.
Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu.
Using template $paramod$73d715d333263ca9cf422f13d07e21664e3ab775\_80_ecp5_alu for cells of type $alu.
Using template $paramod$ed6389a5938b09f91843a91d67becca5abedb1bd\_90_pmux for cells of type $pmux.
Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux.
Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux.
Using template $paramod$c96def1cdcef2eee3c62e5dfb7ba2dd09c9f74dd\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$cc80a4e89b0341cb117f5d28b0e7244620640141\_80_ecp5_alu for cells of type $alu.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$335cfd09f1afa8139c4aafcbbe5f361887b79c5e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$feecc7a0dbd012970970f2858f15e786e251f677\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$5180471e6f22625c8e3c4261cd538e11648586b5\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr.
Using template $paramod$33afdd83bf3811dac2de7a968d39eea5718691bc\_90_pmux for cells of type $pmux.
Using template $paramod$95ab7b964273918a033d1324366ecc612d202989\_90_pmux for cells of type $pmux.
Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux.
Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using template $paramod$a285b5a57fe61eabc57c91b8c412748ee1151a85\_90_pmux for cells of type $pmux.
Using template $paramod$e25898cce02b4d043ab08e065e45db8cf66c901c\_90_pmux for cells of type $pmux.
Using template $paramod$730057d8259da96d4776b15a47b747852ed4c479\_90_pmux for cells of type $pmux.
Using template $paramod$e13ed4cc4d636b3e93547ec233231d1aa3a8ac92\_90_pmux for cells of type $pmux.
Using template $paramod$c6baa65225090ac0a120feab1b920965244aa496\_80_ecp5_alu for cells of type $alu.
Using template $paramod$610911f8769324f781128d641f7fe2120143c328\_80_ecp5_alu for cells of type $alu.
Using template $paramod$2126a3039e9678f6a4bd73d35a1f58ee2616afb2\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux.
No more expansions possible.
<suppressed ~6441 debug messages>

21.32. Executing OPT pass (performing simple optimizations).

21.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~13018 debug messages>

21.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6312 debug messages>
Removed a total of 2104 cells.

21.32.3. Executing OPT_DFF pass (perform DFF optimizations).

21.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1913 unused cells and 6823 unused wires.
<suppressed ~1919 debug messages>

21.32.5. Finished fast OPT passes.

21.33. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

21.35. Executing TECHMAP pass (map to technology primitives).

21.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

21.35.2. Continuing TECHMAP pass.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
Using template $paramod\$_DFFE_PN_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PN_.
No more expansions possible.
<suppressed ~1636 debug messages>

21.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~90 debug messages>

21.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).

21.38. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in processorci_top.

21.39. Executing ATTRMVCP pass (move or copy attributes).

21.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 8395 unused wires.
<suppressed ~1 debug messages>

21.41. Executing TECHMAP pass (map to technology primitives).

21.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

21.41.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

21.42. Executing ABC9 pass.

21.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.3. Executing PROC pass (convert processes to netlists).

21.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$45791'.
Cleaned up 1 empty switch.

21.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$45792 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.3.4. Executing PROC_INIT pass (extract init attributes).

21.42.3.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45816'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$45792'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$45790_EN[3:0]$45798
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$45790_DATA[3:0]$45797
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$45790_ADDR[3:0]$45796
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$45791'.

21.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45816'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45774_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45816'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45775_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45816'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45779_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45816'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45780_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45816'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45784_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45816'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45776_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45816'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45785_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45816'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45789_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45816'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45781_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45816'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45777_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45816'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45786_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45816'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45782_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45816'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45787_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45816'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45788_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45816'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45783_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45816'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45778_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45816'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$45790_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$45792'.
  created $dff cell `$procdff$45842' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$45790_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$45792'.
  created $dff cell `$procdff$45843' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$45790_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$45792'.
  created $dff cell `$procdff$45844' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$45791'.
  created direct connection (no actual register cell created).

21.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45816'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$45792'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$45791'.
Cleaned up 1 empty switch.

21.42.3.12. Executing OPT_EXPR pass (perform const folding).

21.42.4. Executing PROC pass (convert processes to netlists).

21.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$45862'.
Cleaned up 1 empty switch.

21.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$45863 in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.4.4. Executing PROC_INIT pass (extract init attributes).

21.42.4.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45887'.
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$45863'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$45861_EN[3:0]$45868
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$45861_DATA[3:0]$45867
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$45861_ADDR[3:0]$45869
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$45862'.

21.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\i' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45887'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45845_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45887'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45847_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45887'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45848_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45887'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45852_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45887'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45853_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45887'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45857_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45887'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45849_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45887'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45858_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45887'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45854_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45887'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45850_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45887'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45859_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45887'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45855_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45887'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45860_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45887'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45856_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45887'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45851_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45887'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45846_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45887'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$45861_DATA' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$45863'.
  created $dff cell `$procdff$45913' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$45861_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$45863'.
  created $dff cell `$procdff$45914' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$45861_ADDR' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$45863'.
  created $dff cell `$procdff$45915' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$45862'.
  created direct connection (no actual register cell created).

21.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45887'.
Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$45863'.
Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$45862'.
Cleaned up 1 empty switch.

21.42.4.12. Executing OPT_EXPR pass (perform const folding).

21.42.5. Executing SCC pass (detecting logic loops).
Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$10036 $auto$simplemap.cc:126:simplemap_reduce$10303 $auto$simplemap.cc:126:simplemap_reduce$10301 $auto$simplemap.cc:126:simplemap_reduce$10039 $auto$simplemap.cc:126:simplemap_reduce$10037 $auto$simplemap.cc:38:simplemap_not$10007 $auto$simplemap.cc:38:simplemap_not$25512 $auto$ff.cc:266:slice$23969 $auto$ff.cc:479:convert_ce_over_srst$44158 $auto$ff.cc:266:slice$23972 $auto$ff.cc:479:convert_ce_over_srst$44164 $auto$ff.cc:266:slice$23973 $auto$ff.cc:479:convert_ce_over_srst$44166 $auto$ff.cc:266:slice$23970 $auto$ff.cc:479:convert_ce_over_srst$44160 $auto$simplemap.cc:126:simplemap_reduce$10042 $auto$simplemap.cc:38:simplemap_not$25514 $auto$ff.cc:266:slice$23971 $auto$ff.cc:479:convert_ce_over_srst$44162 $auto$simplemap.cc:126:simplemap_reduce$10045 $auto$simplemap.cc:126:simplemap_reduce$10041 $auto$simplemap.cc:38:simplemap_not$25511 $auto$simplemap.cc:38:simplemap_not$10002 $auto$alumacc.cc:485:replace_alu$4980.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$4980.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$4980.slice[0].ccu2c_i $auto$ff.cc:266:slice$23968 $auto$ff.cc:479:convert_ce_over_srst$44156 $auto$simplemap.cc:126:simplemap_reduce$21992 $auto$simplemap.cc:75:simplemap_bitop$17333 $auto$simplemap.cc:126:simplemap_reduce$10047 $auto$simplemap.cc:126:simplemap_reduce$10043 $auto$simplemap.cc:38:simplemap_not$38774
Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$43420 $auto$ff.cc:266:slice$16755 $auto$simplemap.cc:126:simplemap_reduce$16856 $auto$simplemap.cc:126:simplemap_reduce$16871 $auto$ff.cc:266:slice$16754 $auto$ff.cc:266:slice$16753 $auto$simplemap.cc:126:simplemap_reduce$30620 $auto$simplemap.cc:75:simplemap_bitop$30636 $auto$simplemap.cc:267:simplemap_mux$16842 $auto$simplemap.cc:225:simplemap_logbin$16845 $auto$simplemap.cc:196:simplemap_lognot$16860 $auto$simplemap.cc:126:simplemap_reduce$16858 $auto$simplemap.cc:126:simplemap_reduce$16855 $auto$opt_expr.cc:617:replace_const_cells$43792 $auto$opt_expr.cc:617:replace_const_cells$43426 $auto$simplemap.cc:267:simplemap_mux$30637 $auto$simplemap.cc:126:simplemap_reduce$30628 $auto$simplemap.cc:126:simplemap_reduce$30625 $auto$simplemap.cc:75:simplemap_bitop$30633 $auto$simplemap.cc:196:simplemap_lognot$16875 $auto$simplemap.cc:126:simplemap_reduce$16873 $auto$simplemap.cc:126:simplemap_reduce$16870 $auto$ff.cc:266:slice$16752 $auto$simplemap.cc:126:simplemap_reduce$10664 $auto$simplemap.cc:126:simplemap_reduce$10662 $auto$simplemap.cc:225:simplemap_logbin$16801 $auto$simplemap.cc:196:simplemap_lognot$16811 $auto$simplemap.cc:126:simplemap_reduce$16809 $auto$opt_expr.cc:617:replace_const_cells$43428 $auto$simplemap.cc:267:simplemap_mux$30638 $auto$simplemap.cc:126:simplemap_reduce$30623
Found an SCC: $auto$simplemap.cc:38:simplemap_not$30687 $auto$ff.cc:266:slice$16759 $auto$ff.cc:266:slice$16764 $auto$opt_expr.cc:617:replace_const_cells$42946 $auto$ff.cc:266:slice$16763 $auto$simplemap.cc:126:simplemap_reduce$16893 $auto$opt_expr.cc:617:replace_const_cells$42944 $auto$ff.cc:266:slice$16762 $auto$ff.cc:266:slice$16761 $auto$simplemap.cc:126:simplemap_reduce$16896 $auto$simplemap.cc:126:simplemap_reduce$16892 $auto$opt_expr.cc:617:replace_const_cells$42942 $auto$ff.cc:266:slice$16760 $auto$simplemap.cc:126:simplemap_reduce$16891 $auto$ff.cc:266:slice$16758 $auto$ff.cc:266:slice$16757 $auto$ff.cc:266:slice$16756 $auto$simplemap.cc:126:simplemap_reduce$10571 $auto$simplemap.cc:196:simplemap_lognot$16902 $auto$simplemap.cc:126:simplemap_reduce$16900 $auto$simplemap.cc:126:simplemap_reduce$16898 $auto$simplemap.cc:126:simplemap_reduce$16895 $auto$simplemap.cc:126:simplemap_reduce$16890 $auto$simplemap.cc:38:simplemap_not$30684
Found an SCC: $auto$ff.cc:266:slice$14593 $auto$opt_expr.cc:617:replace_const_cells$43454 $auto$ff.cc:266:slice$14592 $auto$simplemap.cc:126:simplemap_reduce$14684 $auto$simplemap.cc:126:simplemap_reduce$14715 $auto$opt_expr.cc:617:replace_const_cells$43452 $auto$ff.cc:266:slice$14591 $auto$simplemap.cc:38:simplemap_not$30614 $auto$ff.cc:266:slice$14590 $auto$simplemap.cc:126:simplemap_reduce$14687 $auto$simplemap.cc:126:simplemap_reduce$14683 $auto$simplemap.cc:126:simplemap_reduce$14718 $auto$simplemap.cc:126:simplemap_reduce$14714 $auto$simplemap.cc:38:simplemap_not$30613 $auto$ff.cc:266:slice$14589 $auto$simplemap.cc:38:simplemap_not$30612 $auto$ff.cc:266:slice$14588 $auto$simplemap.cc:126:simplemap_reduce$14713 $auto$simplemap.cc:126:simplemap_reduce$14682 $auto$simplemap.cc:38:simplemap_not$30611 $auto$ff.cc:266:slice$14587 $auto$ff.cc:266:slice$14586 $auto$simplemap.cc:196:simplemap_lognot$14724 $auto$simplemap.cc:126:simplemap_reduce$14722 $auto$simplemap.cc:126:simplemap_reduce$14720 $auto$simplemap.cc:126:simplemap_reduce$14717 $auto$simplemap.cc:126:simplemap_reduce$14712 $auto$opt_expr.cc:617:replace_const_cells$43794 $auto$simplemap.cc:126:simplemap_reduce$14691 $auto$simplemap.cc:126:simplemap_reduce$14689 $auto$simplemap.cc:126:simplemap_reduce$14686 $auto$simplemap.cc:126:simplemap_reduce$14681 $auto$ff.cc:266:slice$14585 $auto$simplemap.cc:167:logic_reduce$10262 $auto$simplemap.cc:225:simplemap_logbin$14665 $auto$simplemap.cc:225:simplemap_logbin$14666 $auto$simplemap.cc:196:simplemap_lognot$14693
Found 4 SCCs in module processorci_top.
Found 4 SCCs.

21.42.6. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.7. Executing PROC pass (convert processes to netlists).

21.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

21.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

21.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

21.42.7.4. Executing PROC_INIT pass (extract init attributes).

21.42.7.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.7.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

21.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

21.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs).

21.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

21.42.7.12. Executing OPT_EXPR pass (perform const folding).

21.42.8. Executing TECHMAP pass (map to technology primitives).

21.42.8.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

21.42.8.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~164 debug messages>

21.42.9. Executing OPT pass (performing simple optimizations).

21.42.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.

21.42.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

21.42.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.42.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Performed a total of 0 changes.

21.42.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

21.42.9.6. Executing OPT_DFF pass (perform DFF optimizations).

21.42.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..

21.42.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.

21.42.9.9. Finished OPT passes. (There is nothing left to do.)

21.42.10. Executing TECHMAP pass (map to technology primitives).

21.42.10.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

21.42.10.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~1080 debug messages>

21.42.11. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

21.42.12. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

21.42.13. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.14. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

21.42.15. Executing TECHMAP pass (map to technology primitives).

21.42.15.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

21.42.15.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~203 debug messages>

21.42.16. Executing OPT pass (performing simple optimizations).

21.42.16.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~18 debug messages>

21.42.16.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

21.42.16.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.42.16.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

21.42.16.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.42.16.6. Executing OPT_DFF pass (perform DFF optimizations).

21.42.16.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>

21.42.16.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.42.16.9. Rerunning OPT passes. (Maybe there is more to do..)

21.42.16.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.42.16.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

21.42.16.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.42.16.13. Executing OPT_DFF pass (perform DFF optimizations).

21.42.16.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.42.16.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.42.16.16. Finished OPT passes. (There is nothing left to do.)

21.42.17. Executing AIGMAP pass (map logic to AIG).
Module processorci_top: replaced 18 cells with 120 new cells, skipped 39 cells.
  replaced 3 cell types:
       2 $_OR_
       2 $_XOR_
      14 $_MUX_
  not replaced 3 cell types:
      31 $specify2
       4 $_NOT_
       4 $_AND_

21.42.18. Executing AIGMAP pass (map logic to AIG).
Module processorci_top: replaced 8634 cells with 52883 new cells, skipped 6506 cells.
  replaced 4 cell types:
    2517 $_OR_
     211 $_XOR_
       1 $_ORNOT_
    5905 $_MUX_
  not replaced 11 cell types:
      25 $scopeinfo
     554 $_NOT_
    1857 $_AND_
       1 $__ABC9_SCC_BREAKER
    1510 TRELLIS_FF
       4 MULT18X18D
     403 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
      24 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp
    1052 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
      24 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4
    1052 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4

21.42.18.1. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.18.2. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.18.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 22723 AND gates and 67969 wires from module `processorci_top' to a netlist network with 5953 inputs and 1719 outputs.

21.42.18.4. Executing ABC9_EXE pass (technology mapping using ABC9).

21.42.18.5. Executing ABC9.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   5953/   1719  and =   21070  lev =   44 (3.04)  mem = 0.63 MB  box = 1479  bb = 1076
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   5953/   1719  and =   29048  lev =   55 (2.11)  mem = 0.72 MB  ch = 2681  box = 1463  bb = 1076
ABC: + &if -W 300 -v 
ABC: K = 7. Memory (bytes): Truth =    0. Cut =   64. Obj =  148. Set =  672. CutMin = no
ABC: Node =   29048.  Ch =  2022.  Total mem =    8.49 MB. Peak cut mem =    0.23 MB.
ABC: P:  Del = 6068.00.  Ar =   24155.0.  Edge =    29266.  Cut =   383850.  T =     0.18 sec
ABC: P:  Del = 5768.00.  Ar =   24458.0.  Edge =    29110.  Cut =   380655.  T =     0.18 sec
ABC: P:  Del = 5768.00.  Ar =   13495.0.  Edge =    25363.  Cut =   830700.  T =     0.36 sec
ABC: F:  Del = 5768.00.  Ar =    9850.0.  Edge =    23740.  Cut =   650725.  T =     0.29 sec
ABC: A:  Del = 5768.00.  Ar =    9039.0.  Edge =    22173.  Cut =   567949.  T =     0.39 sec
ABC: A:  Del = 5768.00.  Ar =    8952.0.  Edge =    22076.  Cut =   603832.  T =     0.40 sec
ABC: Total time =     1.81 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: + &ps -l 
ABC: <abc-temp-dir>/input : i/o =   5953/   1719  and =   20474  lev =   31 (2.12)  mem = 0.62 MB  box = 1463  bb = 1076
ABC: Mapping (K=7)  :  lut =   5555  edge =   21873  lev =   12 (1.00)  Boxes are not in a topological order. Switching to level computation without boxes.
ABC: levB =   31  mem = 0.30 MB
ABC: LUT = 5555 : 2=686 12.3 %  3=1055 19.0 %  4=2407 43.3 %  5=962 17.3 %  6=217 3.9 %  7=228 4.1 %  Ave = 3.94
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + time 
ABC: elapse: 17.65 seconds, total: 17.65 seconds

21.42.18.6. Executing AIGER frontend.
<suppressed ~15372 debug messages>
Removed 28447 unused cells and 58849 unused wires.

21.42.18.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:     5568
ABC RESULTS:   $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells:      387
ABC RESULTS:   $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp cells:       24
ABC RESULTS:   $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells:     1052
ABC RESULTS:           input signals:     1166
ABC RESULTS:          output signals:      297
Removing temp directory.

21.42.19. Executing TECHMAP pass (map to technology primitives).

21.42.19.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

21.42.19.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000000110 for cells of type $__ABC9_SCC_BREAKER.
No more expansions possible.
<suppressed ~2561 debug messages>
Removed 439 unused cells and 84888 unused wires.

21.43. Executing TECHMAP pass (map to technology primitives).

21.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

21.43.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod$98dbdcd471ba0a28148297d600246e9d7dd9fa99\$lut for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod$c97bcad21440836b1df0dc8f4860bb61034e5b37\$lut for cells of type $lut.
Using template $paramod$8e1c82b304528085a78e4651c993ce9e1ef6b8a8\$lut for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod$2754a21a217ccdc1a0cbf27b2e8b19266cadc23f\$lut for cells of type $lut.
Using template $paramod$4860dafdc834533400ce38279a6df237a334bfd9\$lut for cells of type $lut.
Using template $paramod$527716fb767139921cc3a2a87fc898ef5b04a907\$lut for cells of type $lut.
Using template $paramod$c912d53617436148f085a2bea8d2ed5cbc082892\$lut for cells of type $lut.
Using template $paramod$f587be5dee6fb7e49a5d3ac9ec8f717822a31ea2\$lut for cells of type $lut.
Using template $paramod$97f3b6ab014042030ef7d90b63ad321dcdb251a4\$lut for cells of type $lut.
Using template $paramod$03d0edf20ed1469b09ef5ea8e93986bf65c1867c\$lut for cells of type $lut.
Using template $paramod$80fd3f90b6a7b38da9d25588666decbe3adaf5ec\$lut for cells of type $lut.
Using template $paramod$79c3d83d4871e26e96c90c891dc3096781d9df3e\$lut for cells of type $lut.
Using template $paramod$f0bef4a30c0ab8325e910c7b53ed5044c4e7d707\$lut for cells of type $lut.
Using template $paramod$3cf4b2556bdfa8eeb73797cb4dbe8ddadc6c93dc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod$c7017ce6f918370601990fdcd7ae7caf301de017\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod$fd3c6f7cd86ebd08275158b099051f4b085cb906\$lut for cells of type $lut.
Using template $paramod$fbda9ba53f7f57dd3cad1873a35a93bdf5d3a284\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100101 for cells of type $lut.
Using template $paramod$b46dece358ca27dba156a5b614caa6afaffa2ef3\$lut for cells of type $lut.
Using template $paramod$b2a4860cd839ff40d9dca4c3f237b2b534267028\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$0fa1c6e5d65a4e509c15b676a94b9aed076b9f4d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101100 for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod$2c2bac64448f77131b2d7cdc0cd192ca57c9eab7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$4237ec31543859d6444b0df9382030ab13f55b7e\$lut for cells of type $lut.
Using template $paramod$fccf32f2ce0297290591a5838f1fa2029876bdfc\$lut for cells of type $lut.
Using template $paramod$e90f70c39fe8c2a77ab6893b67a0d7eea0763c62\$lut for cells of type $lut.
Using template $paramod$a2f8c0f49f5179aa0ab5b87e4b39f0b9aaf82f5a\$lut for cells of type $lut.
Using template $paramod$6b9cd69b1e76a46d20d4fcfe7e78c87a68771565\$lut for cells of type $lut.
Using template $paramod$760cbd2b0865be4df85054ed8df8a4e88164e55a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod$25cf967f6f7a20c5f5225a9bf423f0bd7295a899\$lut for cells of type $lut.
Using template $paramod$384dd8fd176e9fb45aae56ef8f5af5a6b7507981\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod$796a976cd67711f2c509e1e9b3c47121c5427850\$lut for cells of type $lut.
Using template $paramod$6597485fc3b2961780e0943deca357e9af14cefd\$lut for cells of type $lut.
Using template $paramod$abb59c83b8ed9f89252ad5e5d1ca1d0e979fcd98\$lut for cells of type $lut.
Using template $paramod$d35161d1d7976dcc02e7c7d51172431be85143b4\$lut for cells of type $lut.
Using template $paramod$4813cacffce12ddd9116dd152a7f1591a368e881\$lut for cells of type $lut.
Using template $paramod$7b4e6fa1cdb2b42b19b33479c9fa66850e3a99de\$lut for cells of type $lut.
Using template $paramod$56c17e6b75008244fc881c7eb75e21c7a76da222\$lut for cells of type $lut.
Using template $paramod$323fbd8da0ac5986920f0496885d4acac13656a5\$lut for cells of type $lut.
Using template $paramod$a840cd94a0a32ebc7ae56637d85fd98be5f7a67c\$lut for cells of type $lut.
Using template $paramod$8c2f43e08c9cc2b49de93af951f385231789cba4\$lut for cells of type $lut.
Using template $paramod$7052bb73849c84c4a3e13a9f5c8c1cfa327a857f\$lut for cells of type $lut.
Using template $paramod$6d05ee5be4fbc817e6482b590e1831ddde15ffbe\$lut for cells of type $lut.
Using template $paramod$24fcf4939b48f5cd3175ac1b780a48b62517b4d6\$lut for cells of type $lut.
Using template $paramod$56e6d8a28a52006bb4e50e077743f0a2163235af\$lut for cells of type $lut.
Using template $paramod$0fcb06ed76df01e8d45bc2b9e6c8a9b43fa42cb4\$lut for cells of type $lut.
Using template $paramod$94e65f323749ab2f501acf5577af42456678fff9\$lut for cells of type $lut.
Using template $paramod$6e2b27a23561eba4d5d7a3612a01502854865858\$lut for cells of type $lut.
Using template $paramod$109987d365962408493bd7b1942d41daf77ce03a\$lut for cells of type $lut.
Using template $paramod$df5c8730c0a53792c3f54c2192a2221c27162fb5\$lut for cells of type $lut.
Using template $paramod$90dc599eed99da511e64ad217d69e7ff2c1e56cc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111011 for cells of type $lut.
Using template $paramod$95c50498433da1a7bcd81cd4bbcc14d8afa1d99f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut.
Using template $paramod$94507ca8ab4456c7f30b56936817430fef7e3798\$lut for cells of type $lut.
Using template $paramod$dd8f09456cc0557d76e7a209e6cf5c8b8adde891\$lut for cells of type $lut.
Using template $paramod$c9ee8c3cdffc10341c8cca5ef6f2d62a471dd9ea\$lut for cells of type $lut.
Using template $paramod$e8323f64b74b08cb8451d9188d080e5c4db6dec0\$lut for cells of type $lut.
Using template $paramod$2a9137b0bd391448ef4b5d31ebac76c273018562\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod$c9b437eae7cbae92bcce00de6505397a13545859\$lut for cells of type $lut.
Using template $paramod$5f496f7a17b34803c6c54860f8e4d6216cf793ef\$lut for cells of type $lut.
Using template $paramod$0481307368cf4a85ae92b0215b3a5fbde430998f\$lut for cells of type $lut.
Using template $paramod$e66ddd071de3be1d112de63078d882cb12c0fbe3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut.
Using template $paramod$63114da772fb28945ba24699e32f1e30ca7142f4\$lut for cells of type $lut.
Using template $paramod$6860d4b46cb57966be724dd044dc10f7935b0eed\$lut for cells of type $lut.
Using template $paramod$27428bd9dccd12f6c4856ed836022614aee41b9b\$lut for cells of type $lut.
Using template $paramod$751bcba42350c84efa14208eda5201a3c7d08f51\$lut for cells of type $lut.
Using template $paramod$6648c16856470047a915b30f34c7e1d81c145425\$lut for cells of type $lut.
Using template $paramod$20f3f4b8e32f8a8b038b0056872dc94926194798\$lut for cells of type $lut.
Using template $paramod$2844c7fef2a755a9af80c70990cd830291c4b71c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod$de81bb4f24bddd9c01fb4a8d2c0db4e04ac2517e\$lut for cells of type $lut.
Using template $paramod$bde6c96e44b0f8e6d9db97eafdf28d77ceaa9a96\$lut for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod$d21d214a5aa271f2d9da3f90f22432c0ecee130f\$lut for cells of type $lut.
Using template $paramod$d1e394e0c71f85fa25b7e43e2e31c5c51cd0e2f8\$lut for cells of type $lut.
Using template $paramod$5f1a82d5fe342005ef911d301582c4e4736a3d34\$lut for cells of type $lut.
Using template $paramod$12b93181fde40368887ce43b59fecaa09cb41fa7\$lut for cells of type $lut.
Using template $paramod$983adbc56c7400f95b406f02e82bd0da8b98fd00\$lut for cells of type $lut.
Using template $paramod$8c13ad014d500c3a349fa680995aa7f6f9eaaf87\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut.
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut.
Using template $paramod$a47d3f6fd9a7aebdb1b556bc977da3380a17c8cf\$lut for cells of type $lut.
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut.
Using template $paramod$2de23df76a24087ecc0fa38a78ecc970cd3f2492\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut.
Using template $paramod$0defb1586b24785b85905f661056d6b3d902c0c8\$lut for cells of type $lut.
Using template $paramod$ccd3e15dc00d71b9284dff48e88ccef5be7362c8\$lut for cells of type $lut.
Using template $paramod$fb7bbfbe62f17d1abd6f8eaee546f5a966c46c29\$lut for cells of type $lut.
Using template $paramod$d0aba71a7ea9c43ba4e04d936be46de775c59df0\$lut for cells of type $lut.
Using template $paramod$877859204cc06b766f4cb38f89dea559af1e3734\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut.
Using template $paramod$fd612331c30e9d253090fdb1f8a32e43d927e731\$lut for cells of type $lut.
Using template $paramod$c8f2b00a2feb859040935d06cafa51f6c4e20e0d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut.
Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod$3e63470ea7a06b3eefdfb990254dd83d20fa13a7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod$4834046533425f54583d6bd31e49deb63455e1a5\$lut for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut.
Using template $paramod$5076a5331d7c4e86743004be8ce491c208a9b0e4\$lut for cells of type $lut.
Using template $paramod$3331a91b4e24483a258fc0d47474cffbd93ab577\$lut for cells of type $lut.
Using template $paramod$7ee6c3286a349174c5e1aff5b6a17ba6deaea830\$lut for cells of type $lut.
Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut.
Using template $paramod$22fea57d7a456c098d9c97c3010141b9cce8b96f\$lut for cells of type $lut.
Using template $paramod$c3725c2b9a1759dee5fba5c3a3adebf5dbc443b8\$lut for cells of type $lut.
Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut.
Using template $paramod$9d3f1b7ccc10f44d7a470c921f48fc669223bc34\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod$17087967d5b06f73682a4be57fe09ecae078cdf7\$lut for cells of type $lut.
Using template $paramod$30ccc2d02d561628bd3e8ba21431cf11015685a5\$lut for cells of type $lut.
Using template $paramod$5b845d3335908b5c4976dbc63690b6cfc712e0cf\$lut for cells of type $lut.
Using template $paramod$717dae7a4b4d98fb824634d546043d165e3cf20a\$lut for cells of type $lut.
Using template $paramod$f5f41ee5d60dede31a2b59f58ec46b167939d713\$lut for cells of type $lut.
Using template $paramod$043949fc5694bcfbd43dabeae74108a81fa8d1bd\$lut for cells of type $lut.
Using template $paramod$060203c61072419c405137c8a93e1cbb22f89fe6\$lut for cells of type $lut.
Using template $paramod$b2153d8b4466d4a8f8649eafb88b32b9356a5968\$lut for cells of type $lut.
Using template $paramod$085cb83d0db09780ae5aa544a0f286ba9445143f\$lut for cells of type $lut.
Using template $paramod$f6e4b9df06807cac5789d4518648b5ffebae2abf\$lut for cells of type $lut.
Using template $paramod$af15d200e3605f2c4c42beab3430842bc93f1158\$lut for cells of type $lut.
Using template $paramod$bbf873f3df28e23f34e6c081b696f5dda6ad6952\$lut for cells of type $lut.
Using template $paramod$5b5755730b9a53f6c50cca29ba2f99d7e0bc0fe6\$lut for cells of type $lut.
Using template $paramod$8d64e576629e8d7c655e0c65958ea61e649cd93e\$lut for cells of type $lut.
Using template $paramod$ee3ba3939f6ccdb74bf420a252d58cdb86511937\$lut for cells of type $lut.
Using template $paramod$5e28eb89fe8218b3148e3be09ae377b977d434a9\$lut for cells of type $lut.
Using template $paramod$eb9a594c5d518ef570c200b24662e31de876a7be\$lut for cells of type $lut.
Using template $paramod$f25cfeb07793f4c9b87758158af8df76472138cf\$lut for cells of type $lut.
Using template $paramod$d211e97fd68a0a11bc667a37034e2f1e81fab7ad\$lut for cells of type $lut.
Using template $paramod$7dad2285b6a41fd718a0863efc009b14ae7d121a\$lut for cells of type $lut.
Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut.
Using template $paramod$9c6d68b4a4d547402e02df6c15cf2994f438168e\$lut for cells of type $lut.
Using template $paramod$deb9c04b2247e9028ddd7bdb0eb764bf0df817f1\$lut for cells of type $lut.
Using template $paramod$9acaef1f9cfe9a101af15c66764de7fa363dc84e\$lut for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut.
Using template $paramod$156da828c051948815c03a641e2104cbfe935333\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut.
Using template $paramod$df29fe9e6d6d694a9cc5697e4251bf7d8cd4d8e4\$lut for cells of type $lut.
Using template $paramod$f13784ede300b12a5285177c86c7721a54cf9e12\$lut for cells of type $lut.
Using template $paramod$8091f1055b08cf62a067eb9c712980d4ac8978e3\$lut for cells of type $lut.
Using template $paramod$fae488a30de1e466fec322ece7e4138825f6e723\$lut for cells of type $lut.
Using template $paramod$127d42c61791e2b6b8fd39133e126a67cbdb52bc\$lut for cells of type $lut.
Using template $paramod$64aff0e21068590cc879245516aab0f75ddd8a7c\$lut for cells of type $lut.
Using template $paramod$8e063d5fd16e3feac8d1520a7c034d0dbd089bde\$lut for cells of type $lut.
Using template $paramod$9b50316d837739e262cead619e8e06f06d816b8c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod$3f943b31daf852ed1ca222e5bb6488e4bbd6a0e6\$lut for cells of type $lut.
Using template $paramod$4cea13af862acc34b9fb468a6a60fa0db5fbd2e8\$lut for cells of type $lut.
Using template $paramod$15cd2baf528a4130f82a2cda907c597c2e928a8c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$fdb7d2f78b1b1d86177579c82e917e4e8af6f77d\$lut for cells of type $lut.
Using template $paramod$b419810ab1d51da1962917a1949cecc5f27935eb\$lut for cells of type $lut.
Using template $paramod$b1241bb2f9028a57b5d511f41eb42255eb327e39\$lut for cells of type $lut.
Using template $paramod$9e34c17c0d2b2f4707acecaf7c63b5063a9a4083\$lut for cells of type $lut.
Using template $paramod$aa92f7ccdceb11c598703c6ec6a4d2e77e7dc608\$lut for cells of type $lut.
Using template $paramod$eabde4761c91679426ef5401ae1b2c95bf56e107\$lut for cells of type $lut.
Using template $paramod$9270e724ed79ca5911f5d48ac2bd61e14d0f2639\$lut for cells of type $lut.
Using template $paramod$d71b174febd328244d15e5a4bbdf51181cbf5883\$lut for cells of type $lut.
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut.
Using template $paramod$8c511ecc39a73b7025cd36ecb3562498546aa7b3\$lut for cells of type $lut.
Using template $paramod$52b16e02f9802938606ca1b07736b1ecf69f6eb1\$lut for cells of type $lut.
Using template $paramod$33fa695ecdb9ecefe42c950b2f6bbc133885a055\$lut for cells of type $lut.
Using template $paramod$79b9e3b5b4d5055d8f7b4df884a3d9fa422809b9\$lut for cells of type $lut.
Using template $paramod$0817ba1bb76015d86d1f03b22a80e18f505980d8\$lut for cells of type $lut.
Using template $paramod$f87bcea8fd3d4d10784cf7549015f5cd3660785e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut.
Using template $paramod$900fba9ba62ae5f0e84a8ac2911c7bbf85560355\$lut for cells of type $lut.
Using template $paramod$5f0e94b9915830ab18fafa958a85f9ab3274acda\$lut for cells of type $lut.
Using template $paramod$08ca3949d0c7cfa1b64b981cab9cdbba3a9776a6\$lut for cells of type $lut.
Using template $paramod$ee700feb78d1f78a2275689013e0e783764ce7f3\$lut for cells of type $lut.
Using template $paramod$fde69dda40178470d7ad71867ad70621c2289f54\$lut for cells of type $lut.
Using template $paramod$1f8e4fcb18669db585d8f85bc4f8a45c7868e286\$lut for cells of type $lut.
Using template $paramod$17e73c622107a376b1917b25d6b319494548d143\$lut for cells of type $lut.
Using template $paramod$827968d270c9772a0a1498903c6e8cd5ccf08c0f\$lut for cells of type $lut.
Using template $paramod$3e895991b845b8c620b8c9e0068c52e372d1fbc1\$lut for cells of type $lut.
Using template $paramod$64f204687d6c23d4a4ada9e2207ddd6dcdab738e\$lut for cells of type $lut.
Using template $paramod$e0f3a9e651b58529d38c0d74095728cb30be2a31\$lut for cells of type $lut.
Using template $paramod$35059585e93e18989247e13034fd6a1ce4de9957\$lut for cells of type $lut.
Using template $paramod$20992234025039442418baf0b059929e088ee3db\$lut for cells of type $lut.
Using template $paramod$4b23d751b3e1d7cde9cd1766bf20ceee12e38a3d\$lut for cells of type $lut.
Using template $paramod$e6062a78edaf68ec0dbea59d4c8352dcb2ce0366\$lut for cells of type $lut.
Using template $paramod$be80b32a1a41df3594c2240cee4d1aae5002aa55\$lut for cells of type $lut.
Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut.
Using template $paramod$e08f26be522f3d4dfa64cc733049539df8b9c905\$lut for cells of type $lut.
Using template $paramod$7d12a59360fe750fab6cd6165277ca330c17affe\$lut for cells of type $lut.
Using template $paramod$62480b7bca8b711bceff201a7d41ed15a726259c\$lut for cells of type $lut.
Using template $paramod$ed2d3664ce2f0ca01a1782f50e1290a5fe9c5dfc\$lut for cells of type $lut.
Using template $paramod$b4d5f082f717432e6f8ece7d6b681bb560654b86\$lut for cells of type $lut.
Using template $paramod$d1112868f3c2119f6b3f85367550d338d78a7334\$lut for cells of type $lut.
Using template $paramod$973231071a94835b329fd27fffcae899cc292087\$lut for cells of type $lut.
Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut.
Using template $paramod$08a3d4c388856efc6fcf55a0e15d50cf1eb0d2d5\$lut for cells of type $lut.
Using template $paramod$77018f7168438de1e5cf566c71f19ae640d9d489\$lut for cells of type $lut.
Using template $paramod$166cf715efc1df7067d016845ac3b08a3b3bfe5f\$lut for cells of type $lut.
Using template $paramod$434563130e5565704ac6f845397506b51fb04af7\$lut for cells of type $lut.
Using template $paramod$c6f4f31b7625b7dda1379350a213e2061745453d\$lut for cells of type $lut.
Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5\$lut for cells of type $lut.
Using template $paramod$83c1b6108170249166239e09804c5f4542556524\$lut for cells of type $lut.
Using template $paramod$bf6de8dce6d7dd51475db454722c4388347732a0\$lut for cells of type $lut.
Using template $paramod$e3e4230bb990723642112b292aa705ee0cbad0d4\$lut for cells of type $lut.
Using template $paramod$13fa9273f1d4ad6050109d02dc87cffc90450a95\$lut for cells of type $lut.
Using template $paramod$6720635ab9307249b8ea0caf486aad8c353f2185\$lut for cells of type $lut.
Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut.
Using template $paramod$3681b2d3435960729195b0e19c518599e89fb0f5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod$e590b9fb2eeda322debdb6a1dd18102c5ff35ddb\$lut for cells of type $lut.
Using template $paramod$5bc4b34d04423f5c10a1f36d396093524460bd02\$lut for cells of type $lut.
Using template $paramod$8b170bed38bb84808b387a3554c5328e63aec095\$lut for cells of type $lut.
Using template $paramod$1092224f6029e53cfd0cc846bb5c4563eb8c60a3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut.
Using template $paramod$0c058dfc29825e1ea89fdfb7507eb91d68500897\$lut for cells of type $lut.
Using template $paramod$c6a0421f5b5114b68e9782f0585d571421cf8f01\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod$7666892acd23b8f07853aa04e4002c1e47b2cdd5\$lut for cells of type $lut.
Using template $paramod$311d67e4fe404298a69fbf7d5690fb437c7d558e\$lut for cells of type $lut.
Using template $paramod$ad2fbd8be3a819ebcd6b7ffdf7b499b345b7099d\$lut for cells of type $lut.
Using template $paramod$221832ea6a41a3208cd6f3411a952b5811695f4c\$lut for cells of type $lut.
Using template $paramod$d72b39aae547bf5473b4f5b33fc824040e0dc79c\$lut for cells of type $lut.
Using template $paramod$ea6128c270ef616511debeeff29f9b4270975f20\$lut for cells of type $lut.
Using template $paramod$c758cf8aee7c6f51f0f08a610e549e87b7c5efaf\$lut for cells of type $lut.
Using template $paramod$ce3fc22bfce5a632ce0c9661803f849e9311a539\$lut for cells of type $lut.
Using template $paramod$f782c0d9db8308022a9483df75860b2e163a6660\$lut for cells of type $lut.
Using template $paramod$965f8f2fa1a796a6c51222eabb50fbd26e97d98b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
Using template $paramod$6f7bad790fa6fec416a8c5c6e1d549dbf7aa8703\$lut for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut.
Using template $paramod$49a3ec53da697e2da42dc40ba801c84bd9727efa\$lut for cells of type $lut.
Using template $paramod$7874993450fc4241d829b5b8254852d8eff7cd07\$lut for cells of type $lut.
Using template $paramod$5289dac6f25369a9a495c69c724c25ee83ad0e78\$lut for cells of type $lut.
Using template $paramod$728e616c918eb05878d70b2bb240e381ea2847b9\$lut for cells of type $lut.
Using template $paramod$f984f1019c52174ba40ecbae4803a7dcfa09e5b1\$lut for cells of type $lut.
Using template $paramod$fbab7b4d89feb5bc60ba2e8a6fe0b73d7eff1c53\$lut for cells of type $lut.
Using template $paramod$b9e29340edc71fd770ad6d0656407f963f85b48f\$lut for cells of type $lut.
Using template $paramod$0ddd5d05cf91959469c9a2d972a98e3ec066e2bf\$lut for cells of type $lut.
Using template $paramod$0a19e0a5a779644c3142a486c7fd4839b760828c\$lut for cells of type $lut.
Using template $paramod$409279b79277055c92c645b01c2deb7a6d1a6a87\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut.
Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7\$lut for cells of type $lut.
Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a\$lut for cells of type $lut.
Using template $paramod$e54349d9a634ecff5f53629ed023a0262d334efb\$lut for cells of type $lut.
Using template $paramod$6e46ec5a196ba1a24b8e69ab094cadc07c13ac1f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut.
Using template $paramod$ee6944635a66b35a2c008244d1b98fdaec97fc5f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod$b8c12e9f20286ec99dd92b2fd58c920f7e7cec0f\$lut for cells of type $lut.
Using template $paramod$acb8c6253d65f5d7c38afa66fc3850a657bea507\$lut for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut.
Using template $paramod$047fa1aac617907e838f1b8f2df3ec2138c09566\$lut for cells of type $lut.
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut.
Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut.
Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut.
Using template $paramod$5afe21d6fdc7c33aeb338fdb508ea02813207bfd\$lut for cells of type $lut.
Using template $paramod$5292ee56af9b5b82806b8eda525aa33bb5ea38ac\$lut for cells of type $lut.
Using template $paramod$22641603d8fa727856e499ecf3ff9bfa826a5891\$lut for cells of type $lut.
Using template $paramod$c34bd785a67c473fb63ea0177b5ef15fccf52556\$lut for cells of type $lut.
Using template $paramod$d7856980c8e3df62f97c26ab34037f33a9e831b5\$lut for cells of type $lut.
Using template $paramod$060fe3a9a87c070316bade86e73c95c5eaa2139d\$lut for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut.
Using template $paramod$5b17484c2590736ad70267419f134a32681b2631\$lut for cells of type $lut.
Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut.
Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut.
Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut.
Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut.
Using template $paramod$f21b0041c50a00ee5548690150273548cd6916b5\$lut for cells of type $lut.
Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut.
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut.
Using template $paramod$6de442abe246ff8c0692702d40d84ce1c07479d9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut.
Using template $paramod$7a0b348a7069d0c8f44afe945e212fcf3f3fd64c\$lut for cells of type $lut.
Using template $paramod$8c14e6d85060218e346675600ae1194fdf5a803e\$lut for cells of type $lut.
Using template $paramod$1f313f85ef575d13bac75382f04905a8c8be8f57\$lut for cells of type $lut.
Using template $paramod$3c5eb16fa418cfbbe1710d24d17e7d0b5448c3c1\$lut for cells of type $lut.
Using template $paramod$d5c7dda3e544463bf43ed73dadb51262f5dcf2fe\$lut for cells of type $lut.
Using template $paramod$872def176acf0af46aee1a4df67a9291309e3c01\$lut for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
Using template $paramod$0a4d85497e20c50068555dd5ad9ad3a7952cab73\$lut for cells of type $lut.
Using template $paramod$c18316765b193c8fc68dacbcf73829d51ebe1631\$lut for cells of type $lut.
Using template $paramod$a5dd9ee10fc2202a29791f7d68d4afcce241aee5\$lut for cells of type $lut.
Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut.
Using template $paramod$fd3b589f355e989c0a46f46a1ab611b8e84c3267\$lut for cells of type $lut.
Using template $paramod$a670b08a47dd8a34f954c50cd06e9996d77e8467\$lut for cells of type $lut.
Using template $paramod$fbed19fb84ee7c8a884778d28a96daea96245184\$lut for cells of type $lut.
Using template $paramod$28f1f052daece0ac14809cddfcdfaa5151170630\$lut for cells of type $lut.
Using template $paramod$338ce46cf7ff44b9974887dd2adee6c4e0530bed\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut.
Using template $paramod$609ff53b8e25fddda2f58be8d19c2d47b81baf45\$lut for cells of type $lut.
Using template $paramod$a8b9523b256193b8ef4d76806da37359144a62fd\$lut for cells of type $lut.
Using template $paramod$5321e04f7ce32c091123c3570ab562efb1c81402\$lut for cells of type $lut.
Using template $paramod$f503ae6dd13af4ce255f26a38c5b2bb42d3444fc\$lut for cells of type $lut.
Using template $paramod$c11ee6bbb8d9fd9cf391261624c378fb45e86b84\$lut for cells of type $lut.
Using template $paramod$7ca4db46d3cd57dbe2541a389808e6d33af02319\$lut for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111001 for cells of type $lut.
Using template $paramod$59f2a3e232df3029c8bc36978b9bbe72a71dfb5a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut.
Using template $paramod$a2657580ee705348a33a1ee3bd7383820950f23b\$lut for cells of type $lut.
Using template $paramod$35d6d6bee07fbed4c99d77928117736fae8df929\$lut for cells of type $lut.
Using template $paramod$a5a9d48041af65bd5d7b6a1f6014e7ed22f6b87a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut.
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut.
Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut.
Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad\$lut for cells of type $lut.
Using template $paramod$9a383ca297ef012b6f33ce559547f89432250d88\$lut for cells of type $lut.
Using template $paramod$2382b0dd4cb27fd4312681c40a6dd179c2a7a26a\$lut for cells of type $lut.
Using template $paramod$231b756afd0fecf2005a2c074473038af42d34a0\$lut for cells of type $lut.
Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6\$lut for cells of type $lut.
Using template $paramod$181733d3e31dcdcea8c52d0a4fc252b3aa453564\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000110 for cells of type $lut.
Using template $paramod$4888f2121a1fba4d507203534ae54782bc81e02e\$lut for cells of type $lut.
Using template $paramod$f9d1c438f06419c3f069fb8ccb89c9102658adee\$lut for cells of type $lut.
Using template $paramod$ea2ed7b6000d8bc7d418a28d22dd562f94afdeff\$lut for cells of type $lut.
Using template $paramod$ebdfc07f371983eb68dd70ec63edee869ba600bd\$lut for cells of type $lut.
Using template $paramod$7e3d8ac009723e554811ad53385162c0e6a41625\$lut for cells of type $lut.
Using template $paramod$12fb017f90e7463fe74789d2ec23494cce2be24a\$lut for cells of type $lut.
Using template $paramod$0acc8d601702e9b60288baa3d5cf1d38d4f22457\$lut for cells of type $lut.
Using template $paramod$94d2f1f461ef911482e15efdba185521de732c99\$lut for cells of type $lut.
Using template $paramod$c50bf79556f7c35c37bbd3d892f752a0609f21ca\$lut for cells of type $lut.
Using template $paramod$1c8aea8d15a8caa53bcd106d813c48ea86657836\$lut for cells of type $lut.
Using template $paramod$90edad2b6a4dec5adef9ce6a532f7a1edb48db32\$lut for cells of type $lut.
Using template $paramod$80f75cefa2bef8403d80a2075d2d1e0a558f6cf5\$lut for cells of type $lut.
Using template $paramod$611e5863a30eeacc19b5015939188ef7be763eab\$lut for cells of type $lut.
Using template $paramod$ffbdf3001f0d2972a014e8e8948b59dcda97f633\$lut for cells of type $lut.
Using template $paramod$1241d759e3df4cac11dc7c99c36b0d1b07f7a673\$lut for cells of type $lut.
Using template $paramod$9640380942618015231dc80e07fe9e6281ac216a\$lut for cells of type $lut.
Using template $paramod$d7dad1939a8443490bea7b8024fc4daa153a48b3\$lut for cells of type $lut.
Using template $paramod$4bf8ce4ba3837f34813021ea7ba48081e9887a3e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000100 for cells of type $lut.
Using template $paramod$20235ca863361fbc253329cfc7eeea38c77404dc\$lut for cells of type $lut.
Using template $paramod$a5decf35c8e89d7ee0a60057106759110775301b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000101 for cells of type $lut.
Using template $paramod$f5df9595b57cb9a2ec12feaa3d15ab3d2be38725\$lut for cells of type $lut.
Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut.
Using template $paramod$f546bd96bcec6e3bf1b78bdea64b0f5bbbaff6df\$lut for cells of type $lut.
Using template $paramod$807041931e47c74b2cac2dfa0f075a4fcc09e1cb\$lut for cells of type $lut.
Using template $paramod$e134ec2a47a2462a591072e65d34fb15b81c90e0\$lut for cells of type $lut.
Using template $paramod$4832df48ba2043723334bbfa7a32d426d800dbae\$lut for cells of type $lut.
Using template $paramod$fe0ec6cf52a74b8e9115c7ff11adb77b1122b4e4\$lut for cells of type $lut.
Using template $paramod$2e9afba29670cc6475874639e7c1b3979c8ebde3\$lut for cells of type $lut.
Using template $paramod$1c96afdddebb58c8c8143438f1dc7e4cce73ee5e\$lut for cells of type $lut.
Using template $paramod$98f91c54c779da6d3b481a488cd9bf8593688dd5\$lut for cells of type $lut.
Using template $paramod$d26850d1fc6faaa4dbfd97c2008c9710ba39f07e\$lut for cells of type $lut.
Using template $paramod$f520d6a7821e132d6b75582f92717501082f3359\$lut for cells of type $lut.
Using template $paramod$bffbc92952163360ab46e89e211c634ca2e2cfb5\$lut for cells of type $lut.
Using template $paramod$beae4210b922fc9ba2fcc4008a7474b475e38c50\$lut for cells of type $lut.
Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut.
Using template $paramod$9cc13b78df4370dfb126255fad0d03d393a2cc28\$lut for cells of type $lut.
Using template $paramod$563acb1d1bf0bfccf04043ec6296c30447924991\$lut for cells of type $lut.
Using template $paramod$06e62c2045624c211a1abe4f2f36c8f22c688165\$lut for cells of type $lut.
Using template $paramod$6be53ab59e0a69757fc32adb071ddcb64e8c87b6\$lut for cells of type $lut.
Using template $paramod$8075729953f49b6cb1b4d863b2fb20da9818d304\$lut for cells of type $lut.
Using template $paramod$413d040dcd860cd74ca61a70644516a95d328ae7\$lut for cells of type $lut.
Using template $paramod$3d47aa1330a97b1ab60cf1eb70b8d4eb13966827\$lut for cells of type $lut.
Using template $paramod$12e9049d8709286a770fe60b59ec4d94c39ce3c9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010011 for cells of type $lut.
Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut.
Using template $paramod$adce9c89515a4e83641fc3471eb3c01ec7b082ff\$lut for cells of type $lut.
Using template $paramod$ede67ae6159d4864b11272c4fe0692c3419120cd\$lut for cells of type $lut.
Using template $paramod$97108e3cc0d0482a6e72e932e86430aa2177750b\$lut for cells of type $lut.
Using template $paramod$baa939b0bd5b3e0c8760492528669bd58f640542\$lut for cells of type $lut.
Using template $paramod$4133fe00eb18442862a284ccc67a95f8194d041c\$lut for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut.
Using template $paramod$f6205ea4d16154fcc0de4d21dff0bd55a57f1ba0\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011101 for cells of type $lut.
Using template $paramod$d25a0f1ed4a99ef8d1bf6a91b3015ece3e01714b\$lut for cells of type $lut.
Using template $paramod$f940b3836b816258cf0bf1afa7ea5d3b0e7a8025\$lut for cells of type $lut.
Using template $paramod$26918802e6ed329b7afdcbcae3efbad76693779f\$lut for cells of type $lut.
Using template $paramod$81cdc00d32c586d379feaa932cc25a9d9eb4f885\$lut for cells of type $lut.
Using template $paramod$74c0f3179b5cebe485563ea55e9b637e7ee5c0c3\$lut for cells of type $lut.
Using template $paramod$00ffcc628ccb870304683cac36ad3a16cc41b6a4\$lut for cells of type $lut.
Using template $paramod$c11fbe3ae77663a03f1ad210bc4d48c4d92df10a\$lut for cells of type $lut.
Using template $paramod$88af067e5d7a87415e359e1eb0f295b619d047cd\$lut for cells of type $lut.
Using template $paramod$3d7168c8134c4765b84a7b86d5ef7e1e65bbf4a0\$lut for cells of type $lut.
Using template $paramod$b75e8306635d621cb7e96e5d2ad1327ab1afa025\$lut for cells of type $lut.
Using template $paramod$ea0d8494b7855939e38ffe3f7b2f8f2d378d3ee0\$lut for cells of type $lut.
Using template $paramod$7b809938766c3068dc017c276033f224fcfb7189\$lut for cells of type $lut.
Using template $paramod$ef2e713cf94754a85372c7c4eece657b7521f115\$lut for cells of type $lut.
Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut.
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut.
Using template $paramod$57400e123f0147f905d2ec980ae5b64230fc0a43\$lut for cells of type $lut.
Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704\$lut for cells of type $lut.
Using template $paramod$461cadc1bd5a9a618782c453f75bb6c15ef2c050\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut.
Using template $paramod$e718d2f5eb562e6029d6a1b1e060511bf1c65df1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut.
Using template $paramod$fd8cbfbb0ad6945f17419290e86ae48a85480aca\$lut for cells of type $lut.
Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f\$lut for cells of type $lut.
Using template $paramod$305eb7dbb8b85462f2ab8d937e9d3604aaaac11b\$lut for cells of type $lut.
Using template $paramod$780628a1a77c105bc0915189ada6705ad9e623c4\$lut for cells of type $lut.
Using template $paramod$6d3ff2249b75859a5b3ab418eca6f7d98ed48047\$lut for cells of type $lut.
Using template $paramod$c35be096d33bbbe5e6f47290b6590ae1d8310544\$lut for cells of type $lut.
Using template $paramod$9d9345fea2bd22a862e4281d6754100e6f96d97b\$lut for cells of type $lut.
Using template $paramod$99c37408a6b9f982779887c9dcb981052d565cb1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut.
Using template $paramod$9cc51547ab44a72dd506ee5bb84a864365a103da\$lut for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod$c08a774c89ef1ea6ee2ef4d8c3b071eb141d4259\$lut for cells of type $lut.
Using template $paramod$7e8d331d1e06632d29fbdf6c3afc2de1856d3c67\$lut for cells of type $lut.
Using template $paramod$94ac66a11090dca84889e55fcf03297912a5b7ec\$lut for cells of type $lut.
Using template $paramod$eaea85d27cc0950ed001348e061727a194f5cf9c\$lut for cells of type $lut.
Using template $paramod$099af7f70fcc70b41da4ec1f8df6dd0abf473cb5\$lut for cells of type $lut.
Using template $paramod$707701b498a5cd123a043548b93e61e0b6bdc440\$lut for cells of type $lut.
Using template $paramod$e7dae0e75ef88f622f9268b2d0ebd23e42ebd640\$lut for cells of type $lut.
Using template $paramod$712505941a295086314c22735153725461a87f4a\$lut for cells of type $lut.
Using template $paramod$cba7d4f63aea5e4b3faf052f9f9805e0c6d202cb\$lut for cells of type $lut.
Using template $paramod$2a3aee6f1b16b87fae5ad552f211bb1ef99dfafe\$lut for cells of type $lut.
Using template $paramod$8c0d8c3650eb56f203c266c77aa390481fe8654a\$lut for cells of type $lut.
Using template $paramod$6fdf2fbb59d351968694f3a02f49f5a5f63ed7a1\$lut for cells of type $lut.
Using template $paramod$36e77cf68e95b3b8cccf1bb5b64409630f2c88d1\$lut for cells of type $lut.
Using template $paramod$fe4e24b614c63965c11dc88a1deafdb9e255213c\$lut for cells of type $lut.
Using template $paramod$51b138c6601401861f3f66aa30cc9212c6a6619a\$lut for cells of type $lut.
Using template $paramod$653ed1fca2cbea6092fc92115114dddd9158d22d\$lut for cells of type $lut.
Using template $paramod$58b33073d6510d6145ff01c28a604d07765b1342\$lut for cells of type $lut.
Using template $paramod$a511f425a16be7369933baa8c17a62ec61a7d7bf\$lut for cells of type $lut.
Using template $paramod$2649632427059f17a6997e51dd7f224fd1802b32\$lut for cells of type $lut.
Using template $paramod$c8f16510db975553c8b0be1064e8f5234175f8a8\$lut for cells of type $lut.
Using template $paramod$000fa2164e1f538c16460571efee2b6209a086cc\$lut for cells of type $lut.
Using template $paramod$faf4b69e2195a9ce52b7c3bce83fa5ea343bc378\$lut for cells of type $lut.
Using template $paramod$20b470574b222c8a8dc09c1422f61c706b7c8097\$lut for cells of type $lut.
Using template $paramod$a0f67318f1c24388c545d8c57553aed79a7a9a84\$lut for cells of type $lut.
Using template $paramod$9475acd65d515c2bd0824c8c2c81c37289c51bd4\$lut for cells of type $lut.
Using template $paramod$dc41a956c02896bb314b3585a99557a5e53688a4\$lut for cells of type $lut.
Using template $paramod$a6d1d3b993ab103c09440e675bfbbb8745de43c0\$lut for cells of type $lut.
Using template $paramod$93ffdc761f07962c601f2556f75c567b7a06c7f8\$lut for cells of type $lut.
Using template $paramod$9f7d0b11a500823b80d1564c55238b10068ae1cf\$lut for cells of type $lut.
Using template $paramod$059968be1ef12c596bb5d360a749040b6777bf4a\$lut for cells of type $lut.
Using template $paramod$20f82dd03802038bc013e5804609eaebb5d257db\$lut for cells of type $lut.
Using template $paramod$f4459bc2ab9d0bffb290e426e5e53be7edbcebe9\$lut for cells of type $lut.
Using template $paramod$672e798a02b8bcc43378b3bcf167b71b5747401f\$lut for cells of type $lut.
Using template $paramod$2357431a20f3891da5d1d21801bc815b057e2dac\$lut for cells of type $lut.
Using template $paramod$faba0cf60f1c89602d59ba2d491152c8f0d36384\$lut for cells of type $lut.
Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d\$lut for cells of type $lut.
Using template $paramod$7ebd053006fefd5a4368bea803813a6c7860a94a\$lut for cells of type $lut.
Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut.
Using template $paramod$aea1c03749b88ed34d454cc6e8153e829d5d62e7\$lut for cells of type $lut.
Using template $paramod$5e3dec618bc0fe16e630b3e41d31d22663795315\$lut for cells of type $lut.
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut.
Using template $paramod$7776c9f5ae2211fea85581af31384e8ba1fa501e\$lut for cells of type $lut.
Using template $paramod$01f4eaf801a9f3034d8a83a480bd2b0fb51b32ea\$lut for cells of type $lut.
Using template $paramod$3442977d9b8391b81788e752bf3ce2d366316fa7\$lut for cells of type $lut.
Using template $paramod$43d34d6b656dbbbd75e40492e45ffd77914a1a60\$lut for cells of type $lut.
Using template $paramod$f52df4b90f46c2ab9e801e1f39516c9cb1bb6ae7\$lut for cells of type $lut.
Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut.
Using template $paramod$d2a32b5705e5737b16886a119d437e51e14ee217\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110111 for cells of type $lut.
Using template $paramod$5c6d01824df27a97c3776b3694e8814e23c197cd\$lut for cells of type $lut.
Using template $paramod$c4fd8ed8a3f2fa4b44e4f56ed8c119b29df21157\$lut for cells of type $lut.
Using template $paramod$2a51abdeeb95860af27728b03974f0c67dd3cd99\$lut for cells of type $lut.
Using template $paramod$5f69790c19b5e35c1c6c7354854d5628ca59cfcc\$lut for cells of type $lut.
Using template $paramod$66658cbed86a8310f9b7ba1190d35eff90ee749b\$lut for cells of type $lut.
Using template $paramod$3e672ed4d74fb09d1bbc1e2b7e987d5fc7d32e5b\$lut for cells of type $lut.
Using template $paramod$18b66a2dc66be2a0d172c3d50ba03932f5924e22\$lut for cells of type $lut.
Using template $paramod$c0e395c2d0dfbafa147a6aae7cfc1897ce26affb\$lut for cells of type $lut.
Using template $paramod$f464e8ee635b255785618aa5657b4cb388e7c29e\$lut for cells of type $lut.
Using template $paramod$9dad3bd803a841860a42543fde7af3545545df64\$lut for cells of type $lut.
Using template $paramod$d1968255603f230ff6286a5a935a91f77276be12\$lut for cells of type $lut.
Using template $paramod$3e6521d392166179e4694ab4704ea33ea0d123ba\$lut for cells of type $lut.
Using template $paramod$2a4b250d89be3556c74aa0e719a4f6242369d42f\$lut for cells of type $lut.
Using template $paramod$76b69988499323c223a91b64a512926500d4c698\$lut for cells of type $lut.
Using template $paramod$b517d5becacef506fa9b592b09d13f7c0a2754bf\$lut for cells of type $lut.
Using template $paramod$3a0a392069bc969f34c65c546a8c56fbbb67e282\$lut for cells of type $lut.
Using template $paramod$baa9d2fb2d21010939721b85aa9f11effe0b53c4\$lut for cells of type $lut.
Using template $paramod$6f9324703e8fcc3b6df2bc2bec54ec19a446ae96\$lut for cells of type $lut.
Using template $paramod$0d710a2d1fb16e4de7d20bde66fd2cf26ada9670\$lut for cells of type $lut.
Using template $paramod$e1ac894a2723e96ae103a1941dc871fbb0ccd216\$lut for cells of type $lut.
Using template $paramod$81b99f0778f7854795e489d3acdff5b1c6c346a0\$lut for cells of type $lut.
Using template $paramod$aab54572d5ffecd31253b36e73e9cb718d05be34\$lut for cells of type $lut.
Using template $paramod$a743caf801766df40bcc22d49baa12a0bdc2f7fe\$lut for cells of type $lut.
Using template $paramod$5d5e0bd0963869548336b3a46c3170a573078c4b\$lut for cells of type $lut.
Using template $paramod$784f4711405f84982df518be1f8d295ab4d5b427\$lut for cells of type $lut.
Using template $paramod$b587e1dcd8f8a9800d395e4aeecac52c55d6f585\$lut for cells of type $lut.
Using template $paramod$ee01f8aaa86cdcd4b779fec0dec9c9062f5b2128\$lut for cells of type $lut.
Using template $paramod$58e67bd5de1d3445a99a48f225d91925f55bb75a\$lut for cells of type $lut.
Using template $paramod$10f5b35253585eaf1f702cede46624c7d0bd2909\$lut for cells of type $lut.
Using template $paramod$bc0944583eed5d4bcf41c3085aadb1498bcf79b6\$lut for cells of type $lut.
Using template $paramod$d80c9b99dacb354fa564a6fcc23ca30753bf6623\$lut for cells of type $lut.
Using template $paramod$f2982e149ddd9d4d086188b455b0c1a7c66a85cb\$lut for cells of type $lut.
Using template $paramod$7933cfc92cabda9fe594c5309ad3f6b3b7ed68e1\$lut for cells of type $lut.
Using template $paramod$24fc6b28d946c1050ce1af45194a82f30a626f44\$lut for cells of type $lut.
Using template $paramod$7ba701df361148e7453af382c90bbeab1fc4525c\$lut for cells of type $lut.
Using template $paramod$f43d7494969db0f2f564d9233d2873d73c25a1d4\$lut for cells of type $lut.
Using template $paramod$9f6bc32305fc769fa11e4327bee073e3fbe84018\$lut for cells of type $lut.
Using template $paramod$91a8c7207b2694b974cfe87bdb74cb70f78a6a1e\$lut for cells of type $lut.
Using template $paramod$e9b29726f16ceb294db8efb9135f326a530ee62e\$lut for cells of type $lut.
Using template $paramod$84c5cfa8d7481774250caab0fcdd6d249a376a31\$lut for cells of type $lut.
Using template $paramod$04a675b912ae1d3dbf320dc050bad2cb6bc647f0\$lut for cells of type $lut.
Using template $paramod$06c5e1fe9689bdc0008e38e009ddfdb9df508661\$lut for cells of type $lut.
Using template $paramod$0ae4b21b6e7aa4dc6bd422184956a70e4b79b8a1\$lut for cells of type $lut.
Using template $paramod$2d70e360329f2b83357618532825d0cf30a325f3\$lut for cells of type $lut.
Using template $paramod$8ccf61cbd280c99ab22986f0067fd91897da1e7f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001000 for cells of type $lut.
Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut.
Using template $paramod$e098d38d00670bf1f66f3fff32b3e8f0f799bc39\$lut for cells of type $lut.
Using template $paramod$e5ca65a4ef689621b3aeabada05c2009697d651c\$lut for cells of type $lut.
Using template $paramod$2b83444282692082c74e255f340b13f1700d73e9\$lut for cells of type $lut.
Using template $paramod$c7eaad6a588218ef0ba5a17502d003bdff2bbd3e\$lut for cells of type $lut.
Using template $paramod$e00b844c6aa23621b3a9b7fc8d116b356163b9f1\$lut for cells of type $lut.
Using template $paramod$071ef78ef050a8e3f1c7fc362b575932ee043820\$lut for cells of type $lut.
Using template $paramod$861b37ae0c614fe7ab6369f56475460abf5e689a\$lut for cells of type $lut.
Using template $paramod$9d773edcd81fdcf68e4ee0e14e645ee92d1552d0\$lut for cells of type $lut.
Using template $paramod$fd3ed3a223484aac184d1b7412ec4cfe4ca64c32\$lut for cells of type $lut.
Using template $paramod$332cafdcffc391074056b900e6dbc03ff48e6212\$lut for cells of type $lut.
Using template $paramod$96fa388e8affdab271f75641c2c3984e44361adb\$lut for cells of type $lut.
Using template $paramod$d4affc054d211b7a0176521ae286ff3e22af24b9\$lut for cells of type $lut.
Using template $paramod$d73f076f8a538c411c5655a085f8b77c30668c10\$lut for cells of type $lut.
Using template $paramod$6e3a03c79073e44642e8ed2dab4ee82dfd40dfba\$lut for cells of type $lut.
Using template $paramod$18368a3da11a7221c7fb674ec80ee0d0bd64b883\$lut for cells of type $lut.
Using template $paramod$bb2303c9c1bac3570d238d5307a22d4ecec2709e\$lut for cells of type $lut.
Using template $paramod$9ae0f136c9ed34a2deb323e9b2a3a520eea61514\$lut for cells of type $lut.
Using template $paramod$ca8e619db22b6f83f776947a8a3b98dd8a9709ea\$lut for cells of type $lut.
Using template $paramod$4fe8154203d178acdcc1b30d740210b7f434be76\$lut for cells of type $lut.
Using template $paramod$48c19eb209dd8ad2c18334e4df384d3b3b74d5ec\$lut for cells of type $lut.
Using template $paramod$d5f04d4004e34aa789af75492223cb07bf0c9b6d\$lut for cells of type $lut.
Using template $paramod$2f23ee9496edbb044d48f324aa9a472e448048c6\$lut for cells of type $lut.
Using template $paramod$37c9af120c85145419565a9ccf4ceb7397fbbe92\$lut for cells of type $lut.
Using template $paramod$da9e7bad4ef7c20a585d8061cb768f43237389cb\$lut for cells of type $lut.
Using template $paramod$0d4742cff20cb0e0e40b9af6c0257e3a276c0c2b\$lut for cells of type $lut.
Using template $paramod$8076fc1f69fb51c30fabbb736cdb4959ab6897ca\$lut for cells of type $lut.
Using template $paramod$52953750219effadf43093a566baf492fdd6b6c8\$lut for cells of type $lut.
Using template $paramod$42147db321d036372bf44f83ba93f840f06de5b7\$lut for cells of type $lut.
Using template $paramod$b7a0a32ef8f8e73ab8160d2399482c0c9d5a3edb\$lut for cells of type $lut.
Using template $paramod$bd57e9718a938c253993cb582d13218a9bcdcc54\$lut for cells of type $lut.
Using template $paramod$2096e0f45e8a23f1611337525706192d6571e3bb\$lut for cells of type $lut.
Using template $paramod$36da781c5c3f8e826f526c11e48feead47b01229\$lut for cells of type $lut.
Using template $paramod$92342ad98884d489d5b1aef3f19c66a00c80cefd\$lut for cells of type $lut.
Using template $paramod$5348912da867a611a8088b6b8b27a62d65f1de6e\$lut for cells of type $lut.
Using template $paramod$cbfab2d0518cca21cb26a503c5e0296523a16ef1\$lut for cells of type $lut.
Using template $paramod$160598ea436a2a1451e5eb1c313595be81162956\$lut for cells of type $lut.
Using template $paramod$05970b5bc5a175a1207f2da5f30cc12c945269a1\$lut for cells of type $lut.
Using template $paramod$a6c6d74a317a554ebd3a91775b8878b72ce961ec\$lut for cells of type $lut.
Using template $paramod$9bda742c69d513125ddabf1ba056578181c839e5\$lut for cells of type $lut.
Using template $paramod$1084ebe50e17fd68513975cf1cdcab6cdae2bbd2\$lut for cells of type $lut.
Using template $paramod$b56552b15644de250f928c7e882226531acd70c9\$lut for cells of type $lut.
Using template $paramod$bf8344c4eead49f5de1b64d00f36a560a632cff7\$lut for cells of type $lut.
Using template $paramod$831ca4a64340813833b25ea62fbeab6aa9d1a202\$lut for cells of type $lut.
Using template $paramod$010d9e7260a28ffa3b7871e475819281e7f16f47\$lut for cells of type $lut.
Using template $paramod$fb8490855044bc3451f83b6a3089a56a0d730f9d\$lut for cells of type $lut.
Using template $paramod$65f4f3efecd6cde7e71540097019def0fb665fcb\$lut for cells of type $lut.
Using template $paramod$f3ca9f7ec12524c75715879d74f2f9b7f83ddff0\$lut for cells of type $lut.
Using template $paramod$e2d4399e1e149b2bd3c04b32fc0d847bb8cdd6d6\$lut for cells of type $lut.
Using template $paramod$bf302e009b1e8dc7956cc27d825ec6a7ba8fbef8\$lut for cells of type $lut.
Using template $paramod$adc0b354bb960519a616db7423a6274fc380540e\$lut for cells of type $lut.
Using template $paramod$5e5c49d7e031b7a364445417d1bf7aca15c4d362\$lut for cells of type $lut.
Using template $paramod$7da7d7bde408365fd9edb48231a23e665dbb7ed8\$lut for cells of type $lut.
Using template $paramod$95521c1555247563d3d8466d2432bb6db43a5553\$lut for cells of type $lut.
Using template $paramod$4d0440a90e55befc55639569976d9facbb4a73c8\$lut for cells of type $lut.
Using template $paramod$1a12eba35eef39ee81e90971ea70fbae7d45f20a\$lut for cells of type $lut.
Using template $paramod$b1680225cc6a5792caa95f54b8b3218fae21705d\$lut for cells of type $lut.
Using template $paramod$cc173bb48f638125313eee2d9b59be0a55452992\$lut for cells of type $lut.
Using template $paramod$4b9b235bc4444ff899bef0c648e4109b26737f1a\$lut for cells of type $lut.
Using template $paramod$fcff9a7b1687e357a40264efcefe8443c8b2971a\$lut for cells of type $lut.
Using template $paramod$e2d96f36ef28053ecd27167cd95b944485ac3146\$lut for cells of type $lut.
Using template $paramod$f55f4b90ec8e3e648d5c29eab1fa5ddd64b3f973\$lut for cells of type $lut.
Using template $paramod$e197e162644f13ba3d6def1b385f7543969ee569\$lut for cells of type $lut.
Using template $paramod$0ee0167fb5dd83bdfe7197fff23e2c7146c57037\$lut for cells of type $lut.
Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut.
Using template $paramod$8d4215f192c2b44e6d2dab923066b63b90c77368\$lut for cells of type $lut.
Using template $paramod$df6b12cebabc3b2db650658c5e894d03a346e968\$lut for cells of type $lut.
Using template $paramod$16894c241be5ea1f024e9339dea788b4dbe184ae\$lut for cells of type $lut.
Using template $paramod$58df2c605746858c7e53492c8f57d6f1fafa12d2\$lut for cells of type $lut.
Using template $paramod$20ba583962918fa0136fc97b1558cc45cc91cc29\$lut for cells of type $lut.
Using template $paramod$6f1f52019f87cdf4da75cf900aaa58aecec1751f\$lut for cells of type $lut.
Using template $paramod$9fbefe93e659f4bccf12885400c6be58da08f9bc\$lut for cells of type $lut.
Using template $paramod$6be1c8f14b3d20f109fab904f0aa9f4d6a208357\$lut for cells of type $lut.
Using template $paramod$629aa9271019649fedae7825a12f30f1a19514c7\$lut for cells of type $lut.
Using template $paramod$345fd45d08372b78664700630f82ee6e3f3317d9\$lut for cells of type $lut.
Using template $paramod$d9a90adbcc3da1d5e7cc3ce04bb1ada828f244c7\$lut for cells of type $lut.
Using template $paramod$75d5c453cca75cc7a7ca320c4fb7be0932b6aaa7\$lut for cells of type $lut.
Using template $paramod$32abbd1d449a67fb913b4733374e345d4c17175b\$lut for cells of type $lut.
Using template $paramod$dbdbcb07b9994e498bb1324e5c006c6aa08a7a37\$lut for cells of type $lut.
Using template $paramod$e16c89da537f52281d818e305f3035f844b7438c\$lut for cells of type $lut.
Using template $paramod$77100ad16713c6ba9793c0afedf1db4e8752e2bb\$lut for cells of type $lut.
Using template $paramod$9891217114ca63a6e9d48073351d843bb1d46faf\$lut for cells of type $lut.
Using template $paramod$bf9d12be9e757c28b1374b63e168615e76b4b315\$lut for cells of type $lut.
Using template $paramod$9dd298ae76fb41ac94779a83c068607fbc09ce4f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut.
Using template $paramod$25944f8b03ec4601f8d9ff13d1154c562b90b79b\$lut for cells of type $lut.
Using template $paramod$8d31841c4841fc3b0c6bb48ca26698752f9e3c07\$lut for cells of type $lut.
Using template $paramod$5afad8f3a1b216100db639959be1d94dbeb119e5\$lut for cells of type $lut.
Using template $paramod$9c4004e0129dafbf742d448a55637017ac48d05a\$lut for cells of type $lut.
Using template $paramod$fe6703019056dabe94a3e064327e07c3371a5bcc\$lut for cells of type $lut.
Using template $paramod$e0b36666b2d163757ae8ae18af9ddd72d58f93ff\$lut for cells of type $lut.
Using template $paramod$18df3812bc12364e5ebcb6c3ed05c0294e4c26fc\$lut for cells of type $lut.
Using template $paramod$4677e5482886dccba9376e8611152076aa521ee4\$lut for cells of type $lut.
Using template $paramod$7c7a71fa5837027b1cccb613fecd982e836a2a37\$lut for cells of type $lut.
Using template $paramod$ba7f31f246a278c41fa0648a6e0512f63185dec0\$lut for cells of type $lut.
Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut.
Using template $paramod$8384e66d408d22ab39dfb451efb7879731befeb8\$lut for cells of type $lut.
Using template $paramod$1a95e0da14fff355d7b4438b7358c951bbb08ccd\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100111 for cells of type $lut.
Using template $paramod$39b0d201a18bed5573a88835da3f39d40814d360\$lut for cells of type $lut.
Using template $paramod$9e394303e290a474880b56f98766417009256d93\$lut for cells of type $lut.
Using template $paramod$02750f8d568bd99efbda01449a05e084a3143ca8\$lut for cells of type $lut.
Using template $paramod$24c18ddd85a46567fc912e79ea8ca93fad17580d\$lut for cells of type $lut.
Using template $paramod$8145d6636291fb05f5bc3110d09e539bc0c15ee7\$lut for cells of type $lut.
Using template $paramod$8abe21ee38ced38064203ce27d377b5c4dcd9cc2\$lut for cells of type $lut.
Using template $paramod$6961918e3564ac9ead822ba7e0287e436372f86a\$lut for cells of type $lut.
Using template $paramod$9cf976b4f3a576aa2cd6b51304cf5de7fc836fbd\$lut for cells of type $lut.
Using template $paramod$df009efd57e0360a9d9a6fba6fba9b2b381f2547\$lut for cells of type $lut.
Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072\$lut for cells of type $lut.
Using template $paramod$682dcf7a44e09cdf417bc55247ac658426f4c8e6\$lut for cells of type $lut.
Using template $paramod$b3f8492b654d6f4d7d1d31e0c18d0c5631447158\$lut for cells of type $lut.
Using template $paramod$01b636f2759ab594c2741266b3c22685988e291c\$lut for cells of type $lut.
Using template $paramod$f2972f00f781f1a033cecbb6cc420de13224764a\$lut for cells of type $lut.
Using template $paramod$63b3ffd6e543b0e90905ac46ac405617f2d419f0\$lut for cells of type $lut.
Using template $paramod$428d89f62acddb59efd2108232ae30869406491b\$lut for cells of type $lut.
Using template $paramod$06c50f3350aba33f5d4efc969d3a1f3880f8fb95\$lut for cells of type $lut.
Using template $paramod$c16f370ae7798b1bdf00bba0fa0d15e5edfce48d\$lut for cells of type $lut.
Using template $paramod$e5759512db67494ff77fbdfc66dff4006376568f\$lut for cells of type $lut.
Using template $paramod$d1dc785fc5b97e7bec2be30ee7302c8cf250ad22\$lut for cells of type $lut.
Using template $paramod$8f7210088a40da1859d27e900c288fd298d68bed\$lut for cells of type $lut.
Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut.
Using template $paramod$f24ba3ced4b870f8e829f5ac5a8af88573350e6f\$lut for cells of type $lut.
Using template $paramod$923e0ce3076e7e851bae1003470e22a3e229399e\$lut for cells of type $lut.
Using template $paramod$66bf2c1f0aa76f60f50d37e63c6fb3163b1ca684\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101110 for cells of type $lut.
Using template $paramod$c9d86860d7b8a94fe4e147db4941c14e73dd3281\$lut for cells of type $lut.
Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882\$lut for cells of type $lut.
Using template $paramod$176a6ceafa512d807921d7dfc76320dfbbfb5fe4\$lut for cells of type $lut.
Using template $paramod$1e9d7896e1dd3d2af9633eefc9c29afb478cef41\$lut for cells of type $lut.
Using template $paramod$e4723c78131b859cdb296cc7099a965ce6bf28d9\$lut for cells of type $lut.
Using template $paramod$8be603794459732f9a374f76041b510fc63b115b\$lut for cells of type $lut.
Using template $paramod$0bd570700cf8cad0539c515a93aa6679c2fc4116\$lut for cells of type $lut.
Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54\$lut for cells of type $lut.
Using template $paramod$47b2f5a9f58cb4be072657772748a1ab82d6819a\$lut for cells of type $lut.
Using template $paramod$223a1a0bfc3038108c8c5d096bc8fdc50fd540b0\$lut for cells of type $lut.
Using template $paramod$50ec6039d9de561a6d0a8dc470847f22a306b04f\$lut for cells of type $lut.
Using template $paramod$7295da7c5b19f528a428229f2570e0a23ad372af\$lut for cells of type $lut.
Using template $paramod$bdba345c854215b5827a3e814ead47dcf0fcc0fa\$lut for cells of type $lut.
Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut.
Using template $paramod$d4fae2c0d9ad2966369cd4e39b81c71bcd1327c9\$lut for cells of type $lut.
Using template $paramod$8e01d13e078e8177912f721c32dbabb20f78322d\$lut for cells of type $lut.
Using template $paramod$6e4a86e6f1a5dc8f826898a131e83cdba4a4fc9e\$lut for cells of type $lut.
Using template $paramod$18e50808df562b188523e13714b96fedec6427c1\$lut for cells of type $lut.
Using template $paramod$bb4fff1cc3b827238aa40993cafede1c5beecbe3\$lut for cells of type $lut.
Using template $paramod$50222e4d0527635d5cf211ed95d1ccfc839e99e8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut.
Using template $paramod$75020cdf7715bd4a5f7067d80cafc74eabba6a01\$lut for cells of type $lut.
Using template $paramod$6c543b558919ff57a92ac09985ad349c5934cfed\$lut for cells of type $lut.
Using template $paramod$bf8a2eb9c34204449ae734db198784b474646269\$lut for cells of type $lut.
Using template $paramod$034a69dd110db95ee917f313eafd6833fc6595f9\$lut for cells of type $lut.
Using template $paramod$3fcffbc2ddcfbfad442bbfe9c66883d5514b6202\$lut for cells of type $lut.
Using template $paramod$7fcc2f13195f27c397064377984d87a90c06749d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011100 for cells of type $lut.
Using template $paramod$f9b715fbf1040e81e900b2461c2390d17ed5e988\$lut for cells of type $lut.
Using template $paramod$ba6cdfbed6d3331b9479f31ee9a163b56164854e\$lut for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut.
Using template $paramod$a14a8c12a7d9be4302fd5be96e31aac1077e087b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110011 for cells of type $lut.
No more expansions possible.
<suppressed ~14651 debug messages>

21.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in processorci_top.
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153488.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153328.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153451.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153453.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153468.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153493.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153494.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153567.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153358.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153393.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$31332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$31332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$31332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$31332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$31332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$31332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$31332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$31323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$31323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$31317.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$31262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$31243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$31243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$31101.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$30882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$30860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$30844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$30786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$30761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30721.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$30543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$30543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$30516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$30516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30496.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$30473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$30473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$30455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30407.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$30097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$30097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$30086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30080.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30037.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$30031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$30010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$29990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$29990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$29979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$29979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$29681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$29681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$29664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$29655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$29618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$29608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$29608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$29599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$29599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$29593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29587.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29587.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29587.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29231.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$29231.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$29209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$29209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$29193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$29176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$29167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$29167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$29147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$29147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$28867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$28862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$28789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28755.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28755.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28755.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28755.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28755.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$28450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$28450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28444.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28444.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$28414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$28414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28394.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$28339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$28326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$28010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$28001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$27989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$27955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$27955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$27658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$27574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$27574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$27574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$27574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$27574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$27565.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$27200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$27186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$27168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$27163.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$27163.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$27163.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27163.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$27163.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27163.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27163.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27121.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27121.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$26754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$26754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$26744.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$26744.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$26492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$26475.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$26404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$26404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26382.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$26060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$26060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$26060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$26034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$26034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$26001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$26001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$25991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$25991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$25991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$25991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$25991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$25991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$25982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$25982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$25967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$25588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$25588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$25588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$25588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$25588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$25551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$25551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$25551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$25551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$25551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$25522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$25516.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$25207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$25195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$25189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$25170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$25170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$25163.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$flatten\Controller.\Interpreter.$procmux$1896.Y[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$24356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24350.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$24346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$24337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$24337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$24327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$24327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$24318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$24318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$24278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$24278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$24278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$24278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$24278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$24272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$24272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$23970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$23970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$23963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$23954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$23890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23582.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23582.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23582.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23582.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23582.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23191.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23191.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23191.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23191.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23191.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$23191.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$23182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$23182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$23173.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22988.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$22652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$22618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$22618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$22308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$22290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$22258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$22249.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$21922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21461.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$21074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$21064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$21055.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$20975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$20975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$20953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[5].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$20614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$20614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$20571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$20571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$20559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$20505.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20505.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20505.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20505.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20505.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20505.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20505.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$20483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$20468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$20184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$20139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20111.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20082.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19970.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$19811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$19811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$19811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$19763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$19672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$19652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$19652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$19652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$19652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[3].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$19199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$19186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$19186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$19186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$19186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$19186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$19106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$18635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$18619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$18619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$18619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$18619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$18619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$18610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$18610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$18602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$18602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$18591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$18591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$18591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$18533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$18533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$18510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$18510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$18510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$18510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17918.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$17184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$17170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16787.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16787.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16734.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$16675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$16544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$16497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$16497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$16482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153615.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$16361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$16294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$16280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16234.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153623.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153647.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16039.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$15994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$15994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15963.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$15949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$15949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$15916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$15916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$15906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$15906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15900.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$15886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$15839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153640.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153640.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$15774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153643.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$15709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$15702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$15702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$15696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$15630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$15601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$15513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$15410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$15361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15295.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$15232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$15129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$15129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$15129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$15112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$15112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153616.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11716.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11716.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11716.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11716.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$25049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13683.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13683.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13683.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13683.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13683.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13668.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153626.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153621.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153630.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153633.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13724.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13724.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$13717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153617.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13639.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13639.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13639.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13639.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13639.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13639.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153613.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153610.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13062.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13062.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13062.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13062.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12943.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$12901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$12875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12870.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$11683.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11683.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153645.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14503.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14503.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14503.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14503.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14485.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14485.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14485.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14485.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14485.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14485.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153634.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153654.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153658.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12210.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$11967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$11958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$11941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$11877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$11859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12754.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153663.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12807.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12807.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12807.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12807.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$12807.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$18070.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut\Controller.Memory.address[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153372.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11499.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$11604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$11610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$11625.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$11638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11683.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11705.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$11716.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11722.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$11728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$11751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$11842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153666.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$11967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153662.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12282.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12282.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153653.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$11809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12807.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$12861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$12875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12993.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$12993.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13062.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153605.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153609.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13683.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13724.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153638.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$13917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153642.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153637.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14266.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14266.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14503.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14645.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153649.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$14920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153622.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$14982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$15008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$13683.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$15112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$15281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15299.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$15361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$15377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153624.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$15513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15526.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153644.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$15584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$15584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$15601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15613.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153588.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$15702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$15731.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15787.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$15839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$15916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153648.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$15949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$15958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15975.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16011.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153651.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$16045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16072.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$16096.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153584.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$16193.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16301.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$16321.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16325.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$16361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16383.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$16445.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16645.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16706.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16720.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16787.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$16809.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$16832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$16893.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$16991.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17118.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$17134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17141.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17156.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$17163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$17184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$17198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$17205.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17252.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17277.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17353.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17436.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17541.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17644.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17700.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17710.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$17741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$17748.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$auto$opt_dff.cc:219:make_patterns_logic$4502.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$17883.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$17922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$17936.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18036.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18153.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$18162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18195.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$18521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$18533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$18533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$18556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$18563.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18573.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$18595.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$18602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$18602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$18610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18629.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$18672.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$18683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18875.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$18888.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$18962.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19062.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19071.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$19097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$19106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19110.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$19142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$19168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$19174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$19186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19217.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$19242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19318.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19351.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19547.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19561.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[3].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$19652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$19662.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$19682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19692.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19699.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19715.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$19763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19831.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19849.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$19865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$19900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$19933.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19949.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$19962.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$20077.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$20088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$20101.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$20128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$20147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$20163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$20225.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20273.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$20294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$20356.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20426.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$20436.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$20483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$20483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$20492.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20505.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20509.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20514.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$20534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20541.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20545.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20550.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$20571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$20582.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20591.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$20666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20680.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20698.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20714.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20732.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$20768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20823.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[5].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$20893.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$20903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$20963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$20975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20975.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21001.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21006.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21011.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$21026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$21205.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21215.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$21310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21363.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21370.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21378.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$21398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21408.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21456.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21477.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21523.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21560.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21567.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21592.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21608.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$21705.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$21715.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21788.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21811.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21837.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21848.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$21864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$21916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21922.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21929.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21945.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22011.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$22032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$22068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$22188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$22227.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22237.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$22281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$22290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$22308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$22340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22353.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$22390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22397.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22404.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22453.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$22480.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$22492.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22593.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$22606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22625.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$22652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$22652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$22659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$22706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22747.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22782.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22801.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22816.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22826.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$22833.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22852.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$22932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$22998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23036.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23093.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23157.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$23182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23191.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23191.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23198.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23205.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$23209.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23276.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23293.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23311.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23370.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23424.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23469.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23473.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23480.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23496.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23514.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23530.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23582.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23632.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23645.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23676.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23701.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23735.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23850.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23858.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$23908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23918.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$23925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23935.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23949.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$23963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$23970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$23980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$24014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24024.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$24052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24083.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$24119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$24185.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24242.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$24249.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24262.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$24278.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$24283.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24291.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24363.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24400.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24407.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24432.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24445.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$24466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24484.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$24502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24733.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24765.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24852.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24883.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24896.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$24918.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$24960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$24967.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$24980.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$25019.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$25092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$25102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$25112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$25116.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$25129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$25183.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$25195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$25195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$25207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$25217.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25253.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$25290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$25304.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$25392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25432.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25464.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$25481.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25486.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$25506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$25533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$25551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$25556.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25561.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$25588.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$25595.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$25632.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25639.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$25646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25664.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$25698.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$25722.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$25826.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25859.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25946.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$25975.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$25982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$26023.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$26041.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$26060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26073.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$26087.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26103.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$26138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26302.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26306.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26372.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26382.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26382.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$26392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26409.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$26429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26439.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$26492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26530.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$26537.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$26566.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$26576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26607.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$26679.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26690.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$26697.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26702.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26715.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26722.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$26733.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26737.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$26744.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$26767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$26774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26799.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$26804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$26804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$26811.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26824.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$26845.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26855.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$26862.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26896.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$27035.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27039.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$27103.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27113.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27121.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$27131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$27138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27163.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$27168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$27200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$27200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$27213.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$27220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27233.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$27240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$27317.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$27325.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27341.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$27371.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$27379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27473.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27536.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$27543.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27560.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$27596.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$27653.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$27658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27686.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27763.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$27779.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$27795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27811.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27845.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$27865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27927.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27943.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$27965.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27970.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27982.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$27989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$27989.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$27996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$28010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28019.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28059.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28092.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28139.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28183.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$28311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28343.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$28349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28370.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28387.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$28399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28404.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28421.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28433.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28444.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28516.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28537.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28547.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28572.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28588.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28624.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28664.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28668.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28726.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28733.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28738.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28755.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28755.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28765.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28843.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28848.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28862.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28867.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28871.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28878.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28915.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$28931.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$28947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28981.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$29005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$29059.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29101.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29115.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$29127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$29147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$29151.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29218.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29224.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29231.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29235.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$29276.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29293.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29311.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$29381.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29421.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$29469.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29530.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29551.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$29564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$29593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$29630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$29636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$29668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$29672.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$29681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29716.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$29927.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29972.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$29979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29983.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$29990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29994.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30015.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$30037.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30037.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30054.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30062.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30068.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30075.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30177.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30247.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30348.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30401.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30407.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30407.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30459.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$30473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$30501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30506.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$30543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$30558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30725.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30747.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30778.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30792.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30796.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30809.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30820.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30827.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30832.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30837.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30851.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30869.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30875.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$30940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30949.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$30953.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30968.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$31019.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$31046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$31070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$31105.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$31117.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$31192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$31243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$31248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$31256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$31262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$31262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$31273.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$31281.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$31313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$31323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$31332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$31336.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$31351.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$31355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$31365.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$31372.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$31398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$auto$fsm_map.cc:170:map_fsm$4429[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$fsm_map.cc:170:map_fsm$4429[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$opt_dff.cc:219:make_patterns_logic$4688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$opt_dff.cc:219:make_patterns_logic$4877.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[0].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[13].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[14].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[15].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[16].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[19].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[20].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[21].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[22].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[23].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[25].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[26].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[3].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[5].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[7].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut\Core.read_data[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153224$lut$flatten\Controller.\Interpreter.$procmux$1530.Y[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$18892.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19451.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23381.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$25734.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26950.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28642.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29017.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$29876.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$26643.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$auto$rtlil.cc:2628:Mux$5233[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut\Controller.Memory.address[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut$aiger153223$18445.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut\Controller.Memory.address[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut\Controller.Memory.address[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut\Controller.Memory.address[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut\Controller.Memory.address[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut\Controller.Memory.address[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153224$lut$auto$fsm_map.cc:170:map_fsm$4429[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153392.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153308.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$23582.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut\Core.read_data[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$26492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut\Core.read_data[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153224$lut$aiger153223$27658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$28065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$19199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$30886.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut\Core.read_data[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$19763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$20379.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$21074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153224$lut$aiger153223$21483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153310.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153307.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153307.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153311.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153344.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153323.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153323.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153328.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153337.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153344.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153366.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153354.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153370.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153400.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153370.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153402.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153380.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153385.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153416.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153393.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153380.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153385.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153416.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153417.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153423.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153423.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153439.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153437.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153439.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153434.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153444.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153462.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153467.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153472.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153476.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153488.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153492.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153493.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153507.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153521.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153511.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153513.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153533.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153224$lut\Controller.Memory.address[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153560.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153586.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153589.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153224$lut$aiger153223$15426.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153602.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153635.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153639.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153640.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Removed 0 unused cells and 16294 unused wires.

21.45. Executing AUTONAME pass.
Renamed 895905 objects in module processorci_top (309 iterations).
<suppressed ~25091 debug messages>

21.46. Executing HIERARCHY pass (managing design hierarchy).

21.46.1. Analyzing design hierarchy..
Top module:  \processorci_top

21.46.2. Analyzing design hierarchy..
Top module:  \processorci_top
Removed 0 unused modules.

21.47. Printing statistics.

=== processorci_top ===

   Number of wires:              11496
   Number of wire bits:          29545
   Number of public wires:       11496
   Number of public wire bits:   29545
   Number of ports:                 10
   Number of port bits:             10
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              14990
     $scopeinfo                     25
     CCU2C                         387
     L6MUX21                       901
     LUT4                         8779
     MULT18X18D                      4
     PFUMX                        2308
     TRELLIS_DPR16X4              1076
     TRELLIS_FF                   1510

21.48. Executing CHECK pass (checking for obvious problems).
Checking module processorci_top...
Found and reported 0 problems.

21.49. Executing JSON backend.

Warnings: 324 unique messages, 325 total
End of script. Logfile hash: fe284f1e4f, CPU: user 35.84s system 0.35s, MEM: 397.07 MB peak
Yosys 0.45+139 (git sha1 4d581a97d, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)
Time spent: 32% 1x abc9_exe (17 sec), 14% 1x autoname (7 sec), ...
/eda/oss-cad-suite/bin/nextpnr-ecp5 --json colorlight_i9.json --write colorlight_i9_pnr.json --45k \
	--lpf /eda/processor-ci/constraints/colorlight_i9.lpf --textcfg colorlight_i9.config --package CABGA381 \
	--speed 6 --lpf-allow-unconstrained --report report_timing.json \
	--detailed-timing-report  --ignore-loops
/eda/oss-cad-suite/bin/ecppack --compress --input colorlight_i9.config  --bit colorlight_i9.bit

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/Risco-5@2/Risco-5
[Pipeline] {
[Pipeline] echo
FPGA colorlight_i9 bloqueada para flash.
[Pipeline] sh
+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Risco-5 -b colorlight_i9 -l
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/Risco-5@2/Risco-5/build_colorlight_i9.tcl
Makefile executado com sucesso.
Sa��da do Makefile:
/eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 colorlight_i9.bit
empty
Found 1 compatible device:
	0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE

Loading: [====                                              ] 6.85%
Loading: [=======                                           ] 13.69%
Loading: [==========                                        ] 19.48%
Loading: [==============                                    ] 26.07%
Loading: [=================                                 ] 32.91%
Loading: [=====================                             ] 40.02%
Loading: [========================                          ] 47.13%
Loading: [===========================                       ] 53.97%
Loading: [===============================                   ] 61.08%
Loading: [=================================                 ] 65.30%
Loading: [====================================              ] 70.30%
Loading: [=======================================           ] 77.41%
Loading: [===========================================       ] 84.52%
Loading: [==============================================    ] 91.62%
Loading: [==================================================] 98.73%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste colorlight_i9)
[Pipeline] echo
Testando FPGA colorlight_i9.
[Pipeline] dir
Running in /var/lib/jenkins/workspace/Risco-5@2/Risco-5
[Pipeline] {
[Pipeline] sh
+ PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py

Running tests...
----------------------------------------------------------------------
..
----------------------------------------------------------------------
Ran 2 tests in 0.208s

OK

Generating XML reports...
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: colorlight_i9]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Sending interrupt signal to process
Aborted by Julio Nunes Avelar
Sending interrupt signal to process
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/Risco-5@2/Risco-5/build_digilent_nexys4_ddr.tcl
Erro ao executar o Makefile.
Terminated
make: *** [/eda/processor-ci/makefiles/digilent_nexys4_ddr.mk:12: digilent_nexys4_ddr.bit] Error 143

Traceback (most recent call last):
  File "/eda/processor-ci/main.py", line 79, in <module>
    main(
  File "/eda/processor-ci/main.py", line 26, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor-ci/core/fpga.py", line 113, in build
    raise subprocess.CalledProcessError(process.returncode, "make")
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
script returned exit code 1
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_nexys4_ddr)
Stage "Flash digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste digilent_nexys4_ddr)
Stage "Teste digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_nexys4_ddr]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch digilent_nexys4_ddr
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
Click here to forcibly terminate running steps
[Checks API] No suitable checks publisher found.
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: b3eee5c9-9ef2-45b3-82b1-2d796fc83d27
Finished: ABORTED