Console Output

Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/jenkins_home/workspace/Risco-5
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf Risco-5
[Pipeline] sh
+ git clone --recursive https://github.com/JN513/Risco-5.git Risco-5
Cloning into 'Risco-5'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Risco-5/Risco-5
[Pipeline] {
[Pipeline] sh
+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s soc_tb -I src/core/ -I src/peripheral/ src/core/alu.v src/core/alu_control.v src/core/control_unit.v src/core/core.v src/core/csr_unit.v src/core/immediate_generator.v src/core/mdu.v src/core/mux.v src/core/pc.v src/core/registers.v tests/soc_test.v src/peripheral/bus.v src/peripheral/fifo.v src/peripheral/gpios.v src/peripheral/gpio.v src/peripheral/leds.v src/peripheral/memory.v src/peripheral/pwm.v src/peripheral/soc.v src/peripheral/uart_rx.v src/peripheral/uart_tx.v src/peripheral/uart.v
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
[Pipeline] lock
Trying to acquire lock on [Resource: colorlight_i9]
Resource [colorlight_i9] did not exist. Created.
Lock acquired on [Resource: colorlight_i9]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_nexys4_ddr]
Resource [digilent_nexys4_ddr] did not exist. Created.
Lock acquired on [Resource: digilent_nexys4_ddr]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Risco-5/Risco-5
[Pipeline] {
[Pipeline] dir
Running in /var/jenkins_home/workspace/Risco-5/Risco-5
[Pipeline] {
[Pipeline] echo
Iniciando síntese para FPGA colorlight_i9.
[Pipeline] sh
[Pipeline] echo
Iniciando síntese para FPGA digilent_nexys4_ddr.
+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Risco-5 -b colorlight_i9
[Pipeline] sh
+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Risco-5 -b digilent_nexys4_ddr
Arquivo de configuração final gerado em /var/jenkins_home/workspace/Risco-5/Risco-5/build_colorlight_i9.tcl
Makefile executado com sucesso.
Saída do Makefile:
/eda/oss-cad-suite/bin/yosys -c /var/jenkins_home/workspace/Risco-5/Risco-5/build_colorlight_i9.tcl -DID=0x6a6a6a6a -DCLOCK_FREQ=25000000 -DMEMORY_SIZE=4096

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.45+139 (git sha1 4d581a97d, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)

-- Running command `read -define ID=0x6a6a6a6a CLOCK_FREQ=25000000 MEMORY_SIZE=4096' --

1. Executing Verilog-2005 frontend: /eda/processor-ci/rtl/Risco-5.v
Parsing Verilog input from `/eda/processor-ci/rtl/Risco-5.v' to AST representation.
Generating RTLIL representation for module `\processorci_top'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v
Parsing Verilog input from `/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v' to AST representation.
Generating RTLIL representation for module `\Alu'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu_control.v
Parsing Verilog input from `/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu_control.v' to AST representation.
Generating RTLIL representation for module `\ALU_Control'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v
Parsing Verilog input from `/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v' to AST representation.
Generating RTLIL representation for module `\Control_Unit'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v
Parsing Verilog input from `/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v' to AST representation.
Generating RTLIL representation for module `\Core'.
/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:197: Warning: Identifier `\pc_source' is implicitly declared.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v
Parsing Verilog input from `/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v' to AST representation.
Generating RTLIL representation for module `\CSR_Unit'.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/Risco-5/Risco-5/src/core/immediate_generator.v
Parsing Verilog input from `/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/immediate_generator.v' to AST representation.
Generating RTLIL representation for module `\Immediate_Generator'.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v
Parsing Verilog input from `/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v' to AST representation.
Generating RTLIL representation for module `\MDU'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mux.v
Parsing Verilog input from `/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mux.v' to AST representation.
Generating RTLIL representation for module `\MUX'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/Risco-5/Risco-5/src/core/pc.v
Parsing Verilog input from `/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/pc.v' to AST representation.
Generating RTLIL representation for module `\PC'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v
Parsing Verilog input from `/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v' to AST representation.
Generating RTLIL representation for module `\Registers'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/uart.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/uart.v' to AST representation.
Generating RTLIL representation for module `\UART'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_rx'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tx'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/fifo.v
Parsing Verilog input from `/eda/processor-ci-controller/src/fifo.v' to AST representation.
Generating RTLIL representation for module `\FIFO'.
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/reset.v
Parsing Verilog input from `/eda/processor-ci-controller/src/reset.v' to AST representation.
Generating RTLIL representation for module `\ResetBootSystem'.
Successfully finished Verilog frontend.

17. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/clk_divider.v
Parsing Verilog input from `/eda/processor-ci-controller/src/clk_divider.v' to AST representation.
Generating RTLIL representation for module `\ClkDivider'.
Successfully finished Verilog frontend.

18. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/memory.v
Parsing Verilog input from `/eda/processor-ci-controller/src/memory.v' to AST representation.
Generating RTLIL representation for module `\Memory'.
Successfully finished Verilog frontend.

19. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/interpreter.v
Parsing Verilog input from `/eda/processor-ci-controller/src/interpreter.v' to AST representation.
Generating RTLIL representation for module `\Interpreter'.
Successfully finished Verilog frontend.

20. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/controller.v
Parsing Verilog input from `/eda/processor-ci-controller/src/controller.v' to AST representation.
Generating RTLIL representation for module `\Controller'.
Successfully finished Verilog frontend.

21. Executing SYNTH_ECP5 pass.

21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.

21.3. Executing HIERARCHY pass (managing design hierarchy).

21.3.1. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     \ResetBootSystem
Used module:     \Core
Used module:         \CSR_Unit
Used module:         \Immediate_Generator
Used module:         \Alu
Used module:         \ALU_Control
Used module:         \Control_Unit
Used module:         \Registers
Used module:         \MDU
Used module:         \MUX
Used module:         \PC
Used module:     \Controller
Used module:         \Memory
Used module:         \UART
Used module:             \uart_tx
Used module:             \uart_rx
Used module:             \FIFO
Used module:         \Interpreter
Used module:         \ClkDivider
Parameter \CYCLES = 20

21.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'.
Parameter \CYCLES = 20
Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'.
Parameter \BOOT_ADDRESS = 0

21.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'.
Parameter \BOOT_ADDRESS = 0
Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.
/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:197: Warning: Identifier `\pc_source' is implicitly declared.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \WORD_SIZE_BY = 4
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

21.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\Controller'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \WORD_SIZE_BY = 4
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

21.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4

21.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4
Generating RTLIL representation for module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 12
Parameter \BUS_WIDTH = 32
Parameter \ID = 1
Parameter \RESET_CLK_CYCLES = 20

21.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 12
Parameter \BUS_WIDTH = 32
Parameter \ID = 1
Parameter \RESET_CLK_CYCLES = 20
Generating RTLIL representation for module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 12

21.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 12
Generating RTLIL representation for module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

21.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

21.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8

21.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

21.3.12. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:         \CSR_Unit
Used module:         \Immediate_Generator
Used module:         \Alu
Used module:         \ALU_Control
Used module:         \Control_Unit
Used module:         \Registers
Used module:         \MDU
Used module:         \MUX
Used module:         \PC
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         \Memory
Used module:         \UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \Interpreter
Used module:         \ClkDivider
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4

21.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4
Generating RTLIL representation for module `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20

21.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Generating RTLIL representation for module `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 32

21.3.15. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 32
Generating RTLIL representation for module `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider'.

21.3.16. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:         \CSR_Unit
Used module:         \Immediate_Generator
Used module:         \Alu
Used module:         \ALU_Control
Used module:         \Control_Unit
Used module:         \Registers
Used module:         \MDU
Used module:         \MUX
Used module:         \PC
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             \uart_tx
Used module:             \uart_rx
Used module:             \FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

21.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

21.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

21.3.19. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:         \CSR_Unit
Used module:         \Immediate_Generator
Used module:         \Alu
Used module:         \ALU_Control
Used module:         \Control_Unit
Used module:         \Registers
Used module:         \MDU
Used module:         \MUX
Used module:         \PC
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider

21.3.20. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:         \CSR_Unit
Used module:         \Immediate_Generator
Used module:         \Alu
Used module:         \ALU_Control
Used module:         \Control_Unit
Used module:         \Registers
Used module:         \MDU
Used module:         \MUX
Used module:         \PC
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'.
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'.
Removing unused module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'.
Removing unused module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'.
Removing unused module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'.
Removing unused module `\Controller'.
Removing unused module `\Interpreter'.
Removing unused module `\Memory'.
Removing unused module `\ClkDivider'.
Removing unused module `\ResetBootSystem'.
Removing unused module `\FIFO'.
Removing unused module `\uart_tx'.
Removing unused module `\uart_rx'.
Removing unused module `\UART'.
Removing unused module `\Core'.
Removed 15 unused modules.

21.4. Executing PROC pass (convert processes to netlists).

21.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$583'.
Found and cleaned up 1 empty switch in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$783'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$783'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:130$102'.
Cleaned up 3 empty switches.

21.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$690 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$642 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$584 in module TRELLIS_DPR16X4.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:36$963 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:25$955 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1156 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1154 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1146 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1143 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1137 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1132 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1127 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1118 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1105 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1103 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1095 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1081 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1075 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1070 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:57$1057 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:36$1048 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Marked 15 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/interpreter.v:116$1012 in module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
Removed 1 dead cases from process $proc$/eda/processor-ci-controller/modules/uart.v:203$1004 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:203$1004 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:187$999 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:132$994 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:74$989 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/memory.v:36$772 in module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/controller.v:113$761 in module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:269$715 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:33$166 in module Registers.
Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/pc.v:15$155 in module PC.
Removed 1 dead cases from process $proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mux.v:14$154 in module MUX.
Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mux.v:14$154 in module MUX.
Marked 5 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:88$117 in module MDU.
Marked 4 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:50$109 in module MDU.
Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/immediate_generator.v:18$108 in module Immediate_Generator.
Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:130$102 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:106$100 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:78$99 in module CSR_Unit.
Marked 5 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/reset.v:25$693 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:703$79 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:693$78 in module Control_Unit.
Marked 21 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:157$32 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:149$31 in module Control_Unit.
Removed 1 dead cases from process $proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu_control.v:9$23 in module ALU_Control.
Marked 4 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu_control.v:9$23 in module ALU_Control.
Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:26$3 in module Alu.
Removed a total of 3 dead cases.

21.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 17 redundant assignments.
Promoted 141 assignments to connections.

21.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$691'.
  Set init value: \Q = 1'0
Found init rule in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$988'.
  Set init value: \read_ptr = 6'000000
  Set init value: \write_ptr = 6'000000
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1158'.
  Set init value: \i = 0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1111'.
  Set init value: \i = 0
Found init rule in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1063'.
  Set init value: \clk_o_auto = 1'0
  Set init value: \clk_counter = 0
  Set init value: \pulse_counter = 0
Found init rule in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1041'.
  Set init value: \state = 8'00000000
  Set init value: \counter = 8'00000000
  Set init value: \read_buffer = 0
  Set init value: \timeout = 0
  Set init value: \accumulator = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1011'.
  Set init value: \read_data = 0
  Set init value: \read_response = 1'0
  Set init value: \write_response = 1'0
  Set init value: \uart_tx_en = 1'0
  Set init value: \tx_fifo_read = 1'0
  Set init value: \tx_fifo_write = 1'0
  Set init value: \rx_fifo_read = 1'0
  Set init value: \rx_fifo_write = 1'0
  Set init value: \uart_tx_data = 8'00000000
  Set init value: \tx_fifo_write_data = 8'00000000
  Set init value: \rx_fifo_write_data = 8'00000000
  Set init value: \counter_write = 3'000
  Set init value: \counter_read = 3'000
  Set init value: \state_read = 4'0000
  Set init value: \state_write = 4'0000
Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:0$718'.
  Set init value: \instruction_register = 0
  Set init value: \memory_register = 0
  Set init value: \alu_out_register = 0
  Set init value: \register_data_1 = 0
  Set init value: \register_data_2 = 0
  Set init value: \pc_old = 0
Found init rule in `\PC.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/pc.v:0$158'.
  Set init value: \Output = 0
Found init rule in `\MDU.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:0$153'.
  Set init value: \state_mul = 2'00
  Set init value: \state_div = 2'00
  Set init value: \Data_X = 0
  Set init value: \Data_Y = 0
  Set init value: \MUL_RD = 0
  Set init value: \acumulador = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `\CSR_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:0$107'.
  Set init value: \mepc = 0
  Set init value: \mscratch = 0
  Set init value: \mcause = 0
  Set init value: \mtval = 0
  Set init value: \mtvec = 0
  Set init value: \mcycle = 64'0000000000000000000000000000000000000000000000000000000000000000
  Set init value: \minstret = 64'0000000000000000000000000000000000000000000000000000000000000000
  Set init value: \utime = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$700'.
  Set init value: \reset_o = 1'0
  Set init value: \state = 2'01
  Set init value: \counter = 6'000000
Found init rule in `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:0$80'.
  Set init value: \memory_read = 1'0
  Set init value: \memory_write = 1'0
  Set init value: \is_immediate = 1'0
  Set init value: \pc_write = 1'0
  Set init value: \ir_write = 1'0
  Set init value: \pc_source = 1'0
  Set init value: \reg_write = 1'0
  Set init value: \pc_write_cond = 1'0
  Set init value: \csr_write_enable = 1'0
  Set init value: \alu_input_selector = 1'0
  Set init value: \save_address = 1'0
  Set init value: \save_value = 1'0
  Set init value: \save_value_2 = 1'0
  Set init value: \save_write_value = 1'0
  Set init value: \control_memory_op = 1'0
  Set init value: \write_data_in = 1'0
  Set init value: \mdu_start = 1'0
  Set init value: \lorD = 2'00
  Set init value: \aluop = 2'00
  Set init value: \alu_src_a = 3'000
  Set init value: \alu_src_b = 3'000
  Set init value: \memory_to_reg = 3'000
  Set init value: \control_unit_memory_op = 3'010
  Set init value: \control_unit_aluop = 4'0000
  Set init value: \state = 6'000000
  Set init value: \nextstate = 6'000000

21.4.5. Executing PROC_ARST pass (detect async resets in processes).

21.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~151 debug messages>

21.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$691'.
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$690'.
     1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$665'.
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$642'.
     1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$641_EN[3:0]$648
     2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$641_DATA[3:0]$647
     3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$641_ADDR[3:0]$646
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$608'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$584'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$582_EN[3:0]$590
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$582_DATA[3:0]$589
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$582_ADDR[3:0]$588
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$583'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$988'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$963'.
     1/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$975
     2/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_DATA[7:0]$974
     3/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_ADDR[5:0]$973
     4/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$969
     5/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_DATA[7:0]$968
     6/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_ADDR[5:0]$967
     7/7: $0\write_ptr[5:0]
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$955'.
     1/2: $0\read_ptr[5:0]
     2/2: $0\read_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1158'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1156'.
     1/2: $0\rxd_reg_0[0:0]
     2/2: $0\rxd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1154'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1146'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1143'.
     1/1: $0\bit_sample[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1137'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1132'.
     1/11: $3\i[31:0]
     2/11: $0\recieved_data[7:0] [1]
     3/11: $0\recieved_data[7:0] [0]
     4/11: $0\recieved_data[7:0] [2]
     5/11: $0\recieved_data[7:0] [3]
     6/11: $0\recieved_data[7:0] [4]
     7/11: $0\recieved_data[7:0] [5]
     8/11: $0\recieved_data[7:0] [6]
     9/11: $0\recieved_data[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1127'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1118'.
     1/1: $0\uart_rx_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1111'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1105'.
     1/1: $0\txd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1103'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1095'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1081'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1075'.
     1/11: $3\i[31:0]
     2/11: $0\data_to_send[7:0] [1]
     3/11: $0\data_to_send[7:0] [0]
     4/11: $0\data_to_send[7:0] [2]
     5/11: $0\data_to_send[7:0] [3]
     6/11: $0\data_to_send[7:0] [4]
     7/11: $0\data_to_send[7:0] [5]
     8/11: $0\data_to_send[7:0] [6]
     9/11: $0\data_to_send[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1070'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1063'.
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1057'.
     1/1: $0\pulse_counter[31:0]
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1048'.
     1/2: $0\clk_counter[31:0]
     2/2: $0\clk_o_auto[0:0]
Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1041'.
Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
     1/28: $0\state[7:0]
     2/28: $0\reset_bus[0:0]
     3/28: $0\memory_write[0:0]
     4/28: $0\memory_read[0:0]
     5/28: $0\write_pulse[0:0]
     6/28: $0\core_reset[0:0]
     7/28: $0\communication_write[0:0]
     8/28: $0\communication_read[0:0]
     9/28: $0\temp_buffer[63:0]
    10/28: $0\accumulator[63:0]
    11/28: $0\timeout_counter[31:0]
    12/28: $0\timeout[31:0]
    13/28: $0\read_buffer[31:0]
    14/28: $0\communication_buffer[31:0]
    15/28: $0\num_of_positions[23:0]
    16/28: $0\num_of_pages[23:0]
    17/28: $0\return_state[7:0]
    18/28: $0\memory_page_number[23:0]
    19/28: $0\memory_mux_selector[0:0]
    20/28: $0\end_position[31:0]
    21/28: $0\memory_page_size[23:0]
    22/28: $0\bus_mode[0:0]
    23/28: $0\num_of_cycles_to_pulse[31:0]
    24/28: $0\core_clk_enable[0:0]
    25/28: $0\communication_write_data[31:0]
    26/28: $0\counter[7:0]
    27/28: $0\write_data[31:0]
    28/28: $0\address[31:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1011'.
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1004'.
     1/4: $0\tx_fifo_read[0:0]
     2/4: $0\uart_tx_en[0:0]
     3/4: $0\tx_fifo_read_state[1:0]
     4/4: $0\uart_tx_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$999'.
     1/2: $0\rx_fifo_write[0:0]
     2/2: $0\rx_fifo_write_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$994'.
     1/6: $0\tx_fifo_write[0:0]
     2/6: $0\write_response[0:0]
     3/6: $0\state_write[3:0]
     4/6: $0\counter_write[2:0]
     5/6: $0\write_data_buffer[31:0]
     6/6: $0\tx_fifo_write_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$989'.
     1/5: $0\read_response[0:0]
     2/5: $0\rx_fifo_read[0:0]
     3/5: $0\state_read[3:0]
     4/5: $0\counter_read[2:0]
     5/5: $0\read_data[31:0]
Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$782'.
Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$772'.
     1/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$781
     2/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_DATA[31:0]$780
     3/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_ADDR[31:0]$779
     4/4: $0\read_sync[31:0]
Creating decoders for process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$761'.
     1/1: $0\finish_execution[0:0]
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:0$718'.
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:269$715'.
     1/7: $0\alu_out_register[31:0]
     2/7: $0\register_data_2[31:0]
     3/7: $0\register_data_1[31:0]
     4/7: $0\memory_register[31:0]
     5/7: $0\mdu_out_reg[31:0]
     6/7: $0\pc_old[31:0]
     7/7: $0\instruction_register[31:0]
Creating decoders for process `\Registers.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:0$184'.
Creating decoders for process `\Registers.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:33$166'.
     1/9: $2$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$181
     2/9: $2$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_DATA[31:0]$180
     3/9: $2$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_ADDR[4:0]$179
     4/9: $2$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$182
     5/9: $1$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$173
     6/9: $1$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$177
     7/9: $1$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$176
     8/9: $1$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_DATA[31:0]$175
     9/9: $1$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_ADDR[4:0]$174
Creating decoders for process `\PC.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/pc.v:0$158'.
Creating decoders for process `\PC.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/pc.v:15$155'.
     1/1: $0\Output[31:0]
Creating decoders for process `\MUX.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mux.v:14$154'.
     1/1: $1\S[31:0]
Creating decoders for process `\MDU.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:0$153'.
Creating decoders for process `\MDU.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:88$117'.
     1/8: $0\state_div[1:0]
     2/8: $0\div_done[0:0]
     3/8: $0\divisor[63:0]
     4/8: $0\DIV_RD[31:0]
     5/8: $0\quociente_msk[31:0]
     6/8: $0\quociente[31:0]
     7/8: $0\dividendo[31:0]
     8/8: $0\negativo[0:0]
Creating decoders for process `\MDU.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:50$109'.
     1/6: $0\state_mul[1:0]
     2/6: $0\mul_done[0:0]
     3/6: $0\acumulador[63:0]
     4/6: $0\MUL_RD[31:0]
     5/6: $0\Data_Y[31:0]
     6/6: $0\Data_X[31:0]
Creating decoders for process `\Immediate_Generator.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/immediate_generator.v:18$108'.
     1/2: $2\immediate[31:0]
     2/2: $1\immediate[31:0]
Creating decoders for process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:0$107'.
Creating decoders for process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:130$102'.
     1/1: $0\minstret[63:0]
Creating decoders for process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:106$100'.
     1/7: $0\mcycle[63:0]
     2/7: $0\utime[63:0]
     3/7: $0\mtvec[31:0]
     4/7: $0\mtval[31:0]
     5/7: $0\mcause[31:0]
     6/7: $0\mscratch[31:0]
     7/7: $0\mepc[31:0]
Creating decoders for process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:78$99'.
     1/1: $0\csr_data_out[31:0]
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$700'.
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$693'.
     1/3: $0\counter[5:0]
     2/3: $0\state[1:0]
     3/3: $0\reset_o[0:0]
Creating decoders for process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:0$80'.
Creating decoders for process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:703$79'.
     1/2: $0\clear_hal_byte_one_block_option_2[2:0]
     2/2: $0\clear_hal_byte_one_block_option[2:0]
Creating decoders for process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:693$78'.
     1/1: $0\wb_filter[2:0]
Creating decoders for process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
     1/23: $0\mdu_start[0:0]
     2/23: $0\save_write_value[0:0]
     3/23: $0\write_data_in[0:0]
     4/23: $0\save_value_2[0:0]
     5/23: $0\save_value[0:0]
     6/23: $0\control_memory_op[0:0]
     7/23: $0\save_address[0:0]
     8/23: $0\control_unit_aluop[3:0]
     9/23: $0\alu_input_selector[0:0]
    10/23: $0\csr_write_enable[0:0]
    11/23: $0\is_immediate[0:0]
    12/23: $0\reg_write[0:0]
    13/23: $0\alu_src_a[2:0]
    14/23: $0\alu_src_b[2:0]
    15/23: $0\aluop[1:0]
    16/23: $0\pc_source[0:0]
    17/23: $0\memory_to_reg[2:0]
    18/23: $0\memory_write[0:0]
    19/23: $0\memory_read[0:0]
    20/23: $0\lorD[1:0]
    21/23: $0\ir_write[0:0]
    22/23: $0\pc_write[0:0]
    23/23: $0\pc_write_cond[0:0]
Creating decoders for process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:157$32'.
     1/21: $21\nextstate[5:0]
     2/21: $20\nextstate[5:0]
     3/21: $19\nextstate[5:0]
     4/21: $18\nextstate[5:0]
     5/21: $17\nextstate[5:0]
     6/21: $16\nextstate[5:0]
     7/21: $15\nextstate[5:0]
     8/21: $14\nextstate[5:0]
     9/21: $13\nextstate[5:0]
    10/21: $12\nextstate[5:0]
    11/21: $11\nextstate[5:0]
    12/21: $10\nextstate[5:0]
    13/21: $9\nextstate[5:0]
    14/21: $8\nextstate[5:0]
    15/21: $7\nextstate[5:0]
    16/21: $6\nextstate[5:0]
    17/21: $5\nextstate[5:0]
    18/21: $4\nextstate[5:0]
    19/21: $3\nextstate[5:0]
    20/21: $2\nextstate[5:0]
    21/21: $1\nextstate[5:0]
Creating decoders for process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:149$31'.
     1/1: $0\state[5:0]
Creating decoders for process `\ALU_Control.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu_control.v:9$23'.
     1/1: $0\aluop_out[3:0]
Creating decoders for process `\Alu.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:26$3'.
     1/1: $0\ALU_out_S[31:0]

21.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1127'.
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1070'.
No latch inferred for signal `\Registers.$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:22$159_EN' from process `\Registers.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:0$184'.
No latch inferred for signal `\MUX.\S' from process `\MUX.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mux.v:14$154'.
No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/immediate_generator.v:18$108'.
No latch inferred for signal `\CSR_Unit.\csr_data_out' from process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:78$99'.
No latch inferred for signal `\Control_Unit.\clear_hal_byte_one_block_option' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:703$79'.
No latch inferred for signal `\Control_Unit.\clear_hal_byte_one_block_option_2' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:703$79'.
No latch inferred for signal `\Control_Unit.\wb_filter' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:693$78'.
No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\is_immediate' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\is_immediate` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\csr_write_enable' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\csr_write_enable` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\alu_input_selector' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_input_selector` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\save_address' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_address` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\save_value' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\save_value_2' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value_2` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\save_write_value' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_write_value` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\control_memory_op' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_memory_op` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\write_data_in' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\write_data_in` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\mdu_start' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\mdu_start` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [0]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [1]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [2]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [2]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [0]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [1]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [2]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\control_unit_memory_op' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [0]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'1 for non-memory siginal `\Control_Unit.\control_unit_memory_op [1]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [2]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\control_unit_aluop' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [0]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [1]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [2]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [3]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:157$32'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [0]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:157$32`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [1]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:157$32`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [2]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:157$32`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [3]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:157$32`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [4]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:157$32`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [5]` in process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:157$32`.
No latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu_control.v:9$23'.
No latch inferred for signal `\Alu.\ALU_out_S' from process `\Alu.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:26$3'.

21.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$690'.
  created $dff cell `$procdff$4114' with positive edge clock.
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$665'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$626_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$665'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$627_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$665'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$628_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$665'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$629_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$665'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$630_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$665'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$631_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$665'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$632_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$665'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$633_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$665'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$634_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$665'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$635_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$665'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$636_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$665'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$637_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$665'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$638_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$665'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$639_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$665'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$640_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$665'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$641_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$642'.
  created $dff cell `$procdff$4115' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$641_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$642'.
  created $dff cell `$procdff$4116' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$641_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$642'.
  created $dff cell `$procdff$4117' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$608'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$566_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$608'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$567_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$608'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$568_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$608'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$569_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$608'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$570_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$608'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$571_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$608'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$572_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$608'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$573_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$608'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$574_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$608'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$575_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$608'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$576_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$608'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$577_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$608'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$578_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$608'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$579_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$608'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$580_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$608'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$581_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$608'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$582_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$584'.
  created $dff cell `$procdff$4118' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$582_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$584'.
  created $dff cell `$procdff$4119' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$582_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$584'.
  created $dff cell `$procdff$4120' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$583'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$963'.
  created $dff cell `$procdff$4121' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$963'.
  created $dff cell `$procdff$4122' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$963'.
  created $dff cell `$procdff$4123' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$963'.
  created $dff cell `$procdff$4124' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_data' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$955'.
  created $dff cell `$procdff$4125' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$955'.
  created $dff cell `$procdff$4126' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1156'.
  created $dff cell `$procdff$4127' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1156'.
  created $dff cell `$procdff$4128' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1154'.
  created $dff cell `$procdff$4129' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1146'.
  created $dff cell `$procdff$4130' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1143'.
  created $dff cell `$procdff$4131' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1137'.
  created $dff cell `$procdff$4132' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1132'.
  created $dff cell `$procdff$4133' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1132'.
  created $dff cell `$procdff$4134' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1118'.
  created $dff cell `$procdff$4135' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1105'.
  created $dff cell `$procdff$4136' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1103'.
  created $dff cell `$procdff$4137' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1095'.
  created $dff cell `$procdff$4138' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1081'.
  created $dff cell `$procdff$4139' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1075'.
  created $dff cell `$procdff$4140' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1075'.
  created $dff cell `$procdff$4141' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\pulse_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1057'.
  created $dff cell `$procdff$4142' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_o_auto' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1048'.
  created $dff cell `$procdff$4143' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1048'.
  created $dff cell `$procdff$4144' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4145' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4146' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\address' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4147' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4148' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4149' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4150' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4151' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4152' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4153' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4154' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_clk_enable' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4155' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_reset' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4156' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_cycles_to_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4157' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\reset_bus' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4158' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\bus_mode' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4159' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_size' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4160' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\end_position' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4161' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_mux_selector' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4162' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_number' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4163' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\return_state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4164' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_pages' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4165' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_positions' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4166' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4167' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\read_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4168' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4169' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout_counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4170' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\accumulator' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4171' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\temp_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
  created $dff cell `$procdff$4172' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_en' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1004'.
  created $dff cell `$procdff$4173' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1004'.
  created $dff cell `$procdff$4174' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1004'.
  created $dff cell `$procdff$4175' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read_state' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1004'.
  created $dff cell `$procdff$4176' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$999'.
  created $dff cell `$procdff$4177' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$999'.
  created $dff cell `$procdff$4178' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$994'.
  created $dff cell `$procdff$4179' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$994'.
  created $dff cell `$procdff$4180' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$994'.
  created $dff cell `$procdff$4181' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_data_buffer' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$994'.
  created $dff cell `$procdff$4182' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$994'.
  created $dff cell `$procdff$4183' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$994'.
  created $dff cell `$procdff$4184' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$989'.
  created $dff cell `$procdff$4185' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$989'.
  created $dff cell `$procdff$4186' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$989'.
  created $dff cell `$procdff$4187' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$989'.
  created $dff cell `$procdff$4188' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$989'.
  created $dff cell `$procdff$4189' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_write_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$782'.
  created $dff cell `$procdff$4190' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_read_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$782'.
  created $dff cell `$procdff$4191' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\read_sync' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$772'.
  created $dff cell `$procdff$4192' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_ADDR' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$772'.
  created $dff cell `$procdff$4193' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_DATA' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$772'.
  created $dff cell `$procdff$4194' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$772'.
  created $dff cell `$procdff$4195' with positive edge clock.
Creating register for signal `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.\finish_execution' using process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$761'.
  created $dff cell `$procdff$4196' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:269$715'.
  created $dff cell `$procdff$4197' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:269$715'.
  created $dff cell `$procdff$4198' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:269$715'.
  created $dff cell `$procdff$4199' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:269$715'.
  created $dff cell `$procdff$4200' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:269$715'.
  created $dff cell `$procdff$4201' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\pc_old' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:269$715'.
  created $dff cell `$procdff$4202' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\mdu_out_reg' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:269$715'.
  created $dff cell `$procdff$4203' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN' using process `\Registers.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:33$166'.
  created $dff cell `$procdff$4204' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_ADDR' using process `\Registers.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:33$166'.
  created $dff cell `$procdff$4205' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_DATA' using process `\Registers.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:33$166'.
  created $dff cell `$procdff$4206' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN' using process `\Registers.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:33$166'.
  created $dff cell `$procdff$4207' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN' using process `\Registers.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:33$166'.
  created $dff cell `$procdff$4208' with positive edge clock.
Creating register for signal `\PC.\Output' using process `\PC.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/pc.v:15$155'.
  created $dff cell `$procdff$4209' with positive edge clock.
Creating register for signal `\MDU.\div_done' using process `\MDU.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:88$117'.
  created $dff cell `$procdff$4210' with positive edge clock.
Creating register for signal `\MDU.\state_div' using process `\MDU.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:88$117'.
  created $dff cell `$procdff$4211' with positive edge clock.
Creating register for signal `\MDU.\negativo' using process `\MDU.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:88$117'.
  created $dff cell `$procdff$4212' with positive edge clock.
Creating register for signal `\MDU.\dividendo' using process `\MDU.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:88$117'.
  created $dff cell `$procdff$4213' with positive edge clock.
Creating register for signal `\MDU.\quociente' using process `\MDU.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:88$117'.
  created $dff cell `$procdff$4214' with positive edge clock.
Creating register for signal `\MDU.\quociente_msk' using process `\MDU.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:88$117'.
  created $dff cell `$procdff$4215' with positive edge clock.
Creating register for signal `\MDU.\DIV_RD' using process `\MDU.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:88$117'.
  created $dff cell `$procdff$4216' with positive edge clock.
Creating register for signal `\MDU.\divisor' using process `\MDU.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:88$117'.
  created $dff cell `$procdff$4217' with positive edge clock.
Creating register for signal `\MDU.\mul_done' using process `\MDU.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:50$109'.
  created $dff cell `$procdff$4218' with positive edge clock.
Creating register for signal `\MDU.\state_mul' using process `\MDU.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:50$109'.
  created $dff cell `$procdff$4219' with positive edge clock.
Creating register for signal `\MDU.\Data_X' using process `\MDU.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:50$109'.
  created $dff cell `$procdff$4220' with positive edge clock.
Creating register for signal `\MDU.\Data_Y' using process `\MDU.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:50$109'.
  created $dff cell `$procdff$4221' with positive edge clock.
Creating register for signal `\MDU.\MUL_RD' using process `\MDU.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:50$109'.
  created $dff cell `$procdff$4222' with positive edge clock.
Creating register for signal `\MDU.\acumulador' using process `\MDU.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:50$109'.
  created $dff cell `$procdff$4223' with positive edge clock.
Creating register for signal `\CSR_Unit.\minstret' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:130$102'.
  created $dff cell `$procdff$4224' with positive edge clock.
Creating register for signal `\CSR_Unit.\mepc' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:106$100'.
  created $dff cell `$procdff$4225' with positive edge clock.
Creating register for signal `\CSR_Unit.\mscratch' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:106$100'.
  created $dff cell `$procdff$4226' with positive edge clock.
Creating register for signal `\CSR_Unit.\mcause' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:106$100'.
  created $dff cell `$procdff$4227' with positive edge clock.
Creating register for signal `\CSR_Unit.\mtval' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:106$100'.
  created $dff cell `$procdff$4228' with positive edge clock.
Creating register for signal `\CSR_Unit.\mtvec' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:106$100'.
  created $dff cell `$procdff$4229' with positive edge clock.
Creating register for signal `\CSR_Unit.\mcycle' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:106$100'.
  created $dff cell `$procdff$4230' with positive edge clock.
Creating register for signal `\CSR_Unit.\utime' using process `\CSR_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:106$100'.
  created $dff cell `$procdff$4231' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$693'.
  created $dff cell `$procdff$4232' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$693'.
  created $dff cell `$procdff$4233' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$693'.
  created $dff cell `$procdff$4234' with positive edge clock.
Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:149$31'.
  created $dff cell `$procdff$4235' with positive edge clock.

21.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$691'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$690'.
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$690'.
Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$665'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$642'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$608'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$584'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$583'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$988'.
Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$963'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$963'.
Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$955'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$955'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1158'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1156'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1156'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1154'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1154'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1146'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1146'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1143'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1143'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1137'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1137'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1132'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1132'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1127'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1127'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1118'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1118'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1111'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1105'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1105'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1103'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1103'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1095'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1095'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1081'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1081'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1075'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1075'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1070'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1070'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1063'.
Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1057'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1057'.
Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1048'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1048'.
Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1041'.
Found and cleaned up 15 empty switches in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1012'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1011'.
Found and cleaned up 3 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1004'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1004'.
Found and cleaned up 2 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$999'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$999'.
Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$994'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$994'.
Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$989'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$989'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$782'.
Found and cleaned up 2 empty switches in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$772'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$772'.
Found and cleaned up 4 empty switches in `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$761'.
Removing empty process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$761'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:0$718'.
Found and cleaned up 2 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:269$715'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:269$715'.
Removing empty process `Registers.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:0$184'.
Found and cleaned up 2 empty switches in `\Registers.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:33$166'.
Removing empty process `Registers.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:33$166'.
Removing empty process `PC.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/pc.v:0$158'.
Found and cleaned up 2 empty switches in `\PC.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/pc.v:15$155'.
Removing empty process `PC.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/pc.v:15$155'.
Found and cleaned up 1 empty switch in `\MUX.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mux.v:14$154'.
Removing empty process `MUX.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mux.v:14$154'.
Removing empty process `MDU.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:0$153'.
Found and cleaned up 6 empty switches in `\MDU.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:88$117'.
Removing empty process `MDU.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:88$117'.
Found and cleaned up 4 empty switches in `\MDU.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:50$109'.
Removing empty process `MDU.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:50$109'.
Found and cleaned up 2 empty switches in `\Immediate_Generator.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/immediate_generator.v:18$108'.
Removing empty process `Immediate_Generator.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/immediate_generator.v:18$108'.
Removing empty process `CSR_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:0$107'.
Found and cleaned up 4 empty switches in `\CSR_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:130$102'.
Removing empty process `CSR_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:130$102'.
Found and cleaned up 3 empty switches in `\CSR_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:106$100'.
Removing empty process `CSR_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:106$100'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:78$99'.
Removing empty process `CSR_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:78$99'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$700'.
Found and cleaned up 6 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$693'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$693'.
Removing empty process `Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:0$80'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:703$79'.
Removing empty process `Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:703$79'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:693$78'.
Removing empty process `Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:693$78'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing empty process `Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Found and cleaned up 21 empty switches in `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:157$32'.
Removing empty process `Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:157$32'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:149$31'.
Removing empty process `Control_Unit.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:149$31'.
Found and cleaned up 5 empty switches in `\ALU_Control.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu_control.v:9$23'.
Removing empty process `ALU_Control.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu_control.v:9$23'.
Found and cleaned up 1 empty switch in `\Alu.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:26$3'.
Removing empty process `Alu.$proc$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:26$3'.
Cleaned up 151 empty switches.

21.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
<suppressed ~5 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
<suppressed ~21 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
<suppressed ~19 debug messages>
Optimizing module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
<suppressed ~9 debug messages>
Optimizing module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
<suppressed ~15 debug messages>
Optimizing module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
<suppressed ~24 debug messages>
Optimizing module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
<suppressed ~3 debug messages>
Optimizing module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
<suppressed ~26 debug messages>
Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
<suppressed ~6 debug messages>
Optimizing module Registers.
<suppressed ~2 debug messages>
Optimizing module PC.
<suppressed ~2 debug messages>
Optimizing module MUX.
<suppressed ~1 debug messages>
Optimizing module MDU.
<suppressed ~17 debug messages>
Optimizing module Immediate_Generator.
Optimizing module CSR_Unit.
<suppressed ~1 debug messages>
Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~8 debug messages>
Optimizing module Control_Unit.
<suppressed ~25 debug messages>
Optimizing module ALU_Control.
<suppressed ~4 debug messages>
Optimizing module Alu.
<suppressed ~1 debug messages>
Optimizing module processorci_top.

21.5. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Deleting now unused module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Deleting now unused module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
Deleting now unused module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Deleting now unused module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
Deleting now unused module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Deleting now unused module Registers.
Deleting now unused module PC.
Deleting now unused module MUX.
Deleting now unused module MDU.
Deleting now unused module Immediate_Generator.
Deleting now unused module CSR_Unit.
Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Deleting now unused module Control_Unit.
Deleting now unused module ALU_Control.
Deleting now unused module Alu.
<suppressed ~24 debug messages>

21.6. Executing TRIBUF pass.

21.7. Executing DEMINOUT pass (demote inout ports to input or output).

21.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~50 debug messages>

21.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 113 unused cells and 964 unused wires.
<suppressed ~155 debug messages>

21.10. Executing CHECK pass (checking for obvious problems).
Checking module processorci_top...
Warning: Wire processorci_top.\miso is used but has no driver.
Warning: Wire processorci_top.\intr is used but has no driver.
Warning: Wire processorci_top.\ResetBootSystem.start is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [31] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [30] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [29] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [28] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [27] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [26] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [25] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [24] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [23] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [22] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [21] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [20] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [19] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [18] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [17] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [16] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [15] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [14] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [13] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [12] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [11] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [10] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [9] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [8] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [7] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [6] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [5] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [4] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [3] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [2] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [1] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.C [0] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [31] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [30] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [29] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [28] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [27] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [26] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [25] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [24] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [23] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [22] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [21] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [20] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [19] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [18] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [17] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [16] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [15] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [14] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [13] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [12] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [11] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [10] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [9] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [8] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [7] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [6] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [5] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [4] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [3] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [2] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [1] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.D [0] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [31] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [30] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [29] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [28] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [27] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [26] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [25] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [24] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [23] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [22] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [21] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [20] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [19] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [18] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [17] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [16] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [15] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [14] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [13] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [12] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [11] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [10] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [9] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [8] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [7] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [6] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [5] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [4] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [3] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [2] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [1] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.E [0] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [31] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [30] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [29] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [28] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [27] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [26] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [25] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [24] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [23] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [22] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [21] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [20] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [19] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [18] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [17] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [16] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [15] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [14] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [13] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [12] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [11] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [10] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [9] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [8] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [7] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [6] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [5] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [4] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [3] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [2] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [1] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.F [0] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [31] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [30] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [29] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [28] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [27] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [26] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [25] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [24] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [23] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [22] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [21] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [20] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [19] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [18] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [17] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [16] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [15] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [14] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [13] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [12] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [11] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [10] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [9] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [8] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [7] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [6] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [5] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [4] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [3] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [2] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [1] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.G [0] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [31] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [30] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [29] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [28] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [27] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [26] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [25] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [24] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [23] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [22] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [21] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [20] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [19] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [18] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [17] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [16] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [15] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [14] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [13] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [12] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [11] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [10] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [9] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [8] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [7] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [6] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [5] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [4] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [3] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [2] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [1] is used but has no driver.
Warning: Wire processorci_top.\Core.MemoryAddressMUX.H [0] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [31] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [30] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [29] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [28] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [27] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [26] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [25] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [24] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [23] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [22] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [21] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [20] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [19] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [18] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [17] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [16] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [15] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [14] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [13] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [12] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [11] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [10] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [9] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [8] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [7] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [6] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [5] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [4] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [3] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [2] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [1] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputBMUX.G [0] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [31] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [30] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [29] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [28] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [27] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [26] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [25] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [24] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [23] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [22] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [21] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [20] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [19] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [18] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [17] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [16] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [15] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [14] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [13] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [12] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [11] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [10] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [9] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [8] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [7] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [6] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [5] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [4] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [3] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [2] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [31] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [30] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [29] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [28] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [27] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [26] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [25] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [24] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [23] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [22] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [21] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [20] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [19] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [18] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [17] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [16] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [15] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [14] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [13] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [12] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [11] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [10] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [9] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [8] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [7] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [6] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [5] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [4] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [3] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [2] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [1] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.H [0] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [31] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [30] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [29] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [28] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [27] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [26] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [25] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [24] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [23] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [22] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [21] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [20] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [19] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [18] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [17] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [16] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [15] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [14] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [13] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [12] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [11] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [10] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [9] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [8] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [7] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [6] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [5] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [4] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [3] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [2] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [1] is used but has no driver.
Warning: Wire processorci_top.\Core.temp_write_value [0] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [1] is used but has no driver.
Warning: Wire processorci_top.\Core.AluInputAMUX.G [0] is used but has no driver.
Found and reported 323 problems.

21.11. Executing OPT pass (performing simple optimizations).

21.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~4 debug messages>

21.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~1062 debug messages>
Removed a total of 354 cells.

21.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1186.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1192.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1198.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1186.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1192.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1198.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3305.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3314.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3330.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3349.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3351.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3369.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3390.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3414.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3442.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3472.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3505.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3541.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3579.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3628.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3679.
    dead port 1/2 on $mux $flatten\Core.\Control_Unit.$procmux$3732.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3734.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3787.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3789.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3841.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3902.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3904.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3966.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$4021.
    dead port 2/2 on $mux $flatten\Core.\Immediate_Generator.$procmux$2684.
    dead port 1/9 on $pmux $flatten\Core.\MemoryAddressMUX.$procmux$2521.
    dead port 2/9 on $pmux $flatten\Core.\MemoryAddressMUX.$procmux$2521.
    dead port 3/9 on $pmux $flatten\Core.\MemoryAddressMUX.$procmux$2521.
    dead port 4/9 on $pmux $flatten\Core.\MemoryAddressMUX.$procmux$2521.
    dead port 1/2 on $mux $flatten\Core.\RegisterBank.$procmux$2481.
    dead port 1/2 on $mux $flatten\Core.\RegisterBank.$procmux$2487.
    dead port 1/2 on $mux $flatten\Core.\RegisterBank.$procmux$2493.
    dead port 1/2 on $mux $flatten\Core.\RegisterBank.$procmux$2499.
Removed 39 multiplexer ports.
<suppressed ~167 debug messages>

21.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2364: $auto$opt_reduce.cc:134:opt_pmux$4266
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1183:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1183_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1183_Y [0]
      New connections: $flatten\Controller.\Uart.\RX_FIFO.$procmux$1183_Y [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$procmux$1183_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1183_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1183_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1183_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1183_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1183_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1183_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1183:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1183_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1183_Y [0]
      New connections: $flatten\Controller.\Uart.\TX_FIFO.$procmux$1183_Y [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$procmux$1183_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1183_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1183_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1183_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1183_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1183_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1183_Y [0] }
    New ctrl vector for $pmux cell $flatten\Core.\CSR_Unit.$procmux$2759: { $flatten\Core.\CSR_Unit.$procmux$2776_CMP $flatten\Core.\CSR_Unit.$procmux$2773_CMP $flatten\Core.\CSR_Unit.$procmux$2771_CMP $flatten\Core.\CSR_Unit.$procmux$2770_CMP $flatten\Core.\CSR_Unit.$procmux$2769_CMP $flatten\Core.\CSR_Unit.$procmux$2714_CMP $flatten\Core.\CSR_Unit.$procmux$2741_CMP $flatten\Core.\CSR_Unit.$procmux$2752_CMP $flatten\Core.\CSR_Unit.$procmux$2731_CMP $flatten\Core.\CSR_Unit.$procmux$2722_CMP $auto$opt_reduce.cc:134:opt_pmux$4274 $auto$opt_reduce.cc:134:opt_pmux$4272 $auto$opt_reduce.cc:134:opt_pmux$4270 $auto$opt_reduce.cc:134:opt_pmux$4268 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1622: $auto$opt_reduce.cc:134:opt_pmux$4276
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1646: $auto$opt_reduce.cc:134:opt_pmux$4278
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$2824: { $flatten\Core.\Control_Unit.$procmux$2821_CMP $auto$opt_reduce.cc:134:opt_pmux$4280 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1668: $auto$opt_reduce.cc:134:opt_pmux$4282
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1679: $auto$opt_reduce.cc:134:opt_pmux$4284
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$2870: $auto$opt_reduce.cc:134:opt_pmux$4286
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$2995: { $auto$opt_reduce.cc:134:opt_pmux$4290 $auto$opt_reduce.cc:134:opt_pmux$4288 }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3026: $auto$opt_reduce.cc:134:opt_pmux$4292
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1727: $auto$opt_reduce.cc:134:opt_pmux$4294
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1769: $auto$opt_reduce.cc:134:opt_pmux$4296
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3052: $auto$opt_reduce.cc:134:opt_pmux$4298
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3055: $auto$opt_reduce.cc:134:opt_pmux$4300
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3063: { $flatten\Core.\Control_Unit.$procmux$3005_CMP $auto$opt_reduce.cc:134:opt_pmux$4312 $auto$opt_reduce.cc:134:opt_pmux$4310 $auto$opt_reduce.cc:134:opt_pmux$4308 $auto$opt_reduce.cc:134:opt_pmux$4306 $auto$opt_reduce.cc:134:opt_pmux$4304 $auto$opt_reduce.cc:134:opt_pmux$4302 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1794: { $flatten\Controller.\Interpreter.$procmux$1562_CMP $auto$opt_reduce.cc:134:opt_pmux$4314 $flatten\Controller.\Interpreter.$procmux$1552_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1847: { $auto$opt_reduce.cc:134:opt_pmux$4318 $auto$opt_reduce.cc:134:opt_pmux$4316 }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3102: { $flatten\Core.\Control_Unit.$procmux$3092_CMP $auto$opt_reduce.cc:134:opt_pmux$4332 $auto$opt_reduce.cc:134:opt_pmux$4330 $auto$opt_reduce.cc:134:opt_pmux$4328 $flatten\Core.\Control_Unit.$procmux$3002_CMP $auto$opt_reduce.cc:134:opt_pmux$4326 $flatten\Core.\Control_Unit.$procmux$2999_CMP $flatten\Core.\Control_Unit.$procmux$2998_CMP $flatten\Core.\Control_Unit.$procmux$2997_CMP $flatten\Core.\Control_Unit.$procmux$2996_CMP $auto$opt_reduce.cc:134:opt_pmux$4324 $auto$opt_reduce.cc:134:opt_pmux$4322 $auto$opt_reduce.cc:134:opt_pmux$4320 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1916: $auto$opt_reduce.cc:134:opt_pmux$4334
    Consolidated identical input bits for $mux cell $flatten\Controller.\Data_Memory.$procmux$2432:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0]
      New connections: $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [31:1] = { $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1941: { $flatten\Controller.\Interpreter.$procmux$1562_CMP $auto$opt_reduce.cc:134:opt_pmux$4336 $flatten\Controller.\Interpreter.$procmux$1552_CMP }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3140: { $auto$opt_reduce.cc:134:opt_pmux$4338 $flatten\Core.\Control_Unit.$procmux$3070_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1969: { $flatten\Controller.\Interpreter.$procmux$1548_CMP $flatten\Controller.\Interpreter.$procmux$1541_CMP $flatten\Controller.\Interpreter.$procmux$1530_CMP $flatten\Controller.\Interpreter.$procmux$1524_CMP $auto$opt_reduce.cc:134:opt_pmux$4340 }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3154: { $flatten\Core.\Control_Unit.$procmux$3061_CMP $auto$opt_reduce.cc:134:opt_pmux$4342 $flatten\Core.\Control_Unit.$procmux$3045_CMP $flatten\Core.\Control_Unit.$procmux$3056_CMP }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3174: $auto$opt_reduce.cc:134:opt_pmux$4344
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3199: $auto$opt_reduce.cc:134:opt_pmux$4346
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3221: { $auto$opt_reduce.cc:134:opt_pmux$4350 $auto$opt_reduce.cc:134:opt_pmux$4348 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2001: { $auto$opt_reduce.cc:134:opt_pmux$4354 $auto$opt_reduce.cc:134:opt_pmux$4352 }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3286: $auto$opt_reduce.cc:134:opt_pmux$4356
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2083: { $flatten\Controller.\Interpreter.$procmux$1542_CMP $auto$opt_reduce.cc:134:opt_pmux$4358 }
    New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2300: $auto$opt_reduce.cc:134:opt_pmux$4360
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3955: { $auto$opt_reduce.cc:134:opt_pmux$4362 $flatten\Core.\Control_Unit.$procmux$3903_CMP $flatten\Core.\Control_Unit.$procmux$3962_CMP $flatten\Core.\Control_Unit.$procmux$3961_CMP $flatten\Core.\Control_Unit.$procmux$3960_CMP $flatten\Core.\Control_Unit.$procmux$3959_CMP $flatten\Core.\Control_Unit.$procmux$3958_CMP $flatten\Core.\Control_Unit.$procmux$3957_CMP $flatten\Core.\Control_Unit.$procmux$3956_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2094: { $flatten\Controller.\Interpreter.$procmux$1683_CMP $flatten\Controller.\Interpreter.$procmux$1582_CMP $auto$opt_reduce.cc:134:opt_pmux$4364 }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$4025: { $flatten\Core.\Control_Unit.$procmux$3206_CMP $flatten\Core.\Control_Unit.$procmux$3131_CMP $flatten\Core.\Control_Unit.$procmux$3097_CMP $flatten\Core.\Control_Unit.$procmux$3096_CMP $flatten\Core.\Control_Unit.$procmux$3204_CMP $flatten\Core.\Control_Unit.$procmux$3177_CMP $flatten\Core.\Control_Unit.$procmux$3069_CMP $auto$opt_reduce.cc:134:opt_pmux$4368 $flatten\Core.\Control_Unit.$procmux$3203_CMP $flatten\Core.\Control_Unit.$procmux$3009_CMP $flatten\Core.\Control_Unit.$procmux$3060_CMP $flatten\Core.\Control_Unit.$procmux$3094_CMP $flatten\Core.\Control_Unit.$procmux$3202_CMP $flatten\Core.\Control_Unit.$procmux$3008_CMP $flatten\Core.\Control_Unit.$procmux$3092_CMP $flatten\Core.\Control_Unit.$procmux$3201_CMP $flatten\Core.\Control_Unit.$procmux$3007_CMP $flatten\Core.\Control_Unit.$procmux$3006_CMP $flatten\Core.\Control_Unit.$procmux$3005_CMP $flatten\Core.\Control_Unit.$procmux$3004_CMP $flatten\Core.\Control_Unit.$procmux$3087_CMP $flatten\Core.\Control_Unit.$procmux$3086_CMP $flatten\Core.\Control_Unit.$procmux$3002_CMP $flatten\Core.\Control_Unit.$procmux$3001_CMP $auto$opt_reduce.cc:134:opt_pmux$4366 $flatten\Core.\Control_Unit.$procmux$3081_CMP $flatten\Core.\Control_Unit.$procmux$2872_CMP $flatten\Core.\Control_Unit.$procmux$3080_CMP $flatten\Core.\Control_Unit.$procmux$3200_CMP $flatten\Core.\Control_Unit.$procmux$2999_CMP $flatten\Core.\Control_Unit.$procmux$2998_CMP $flatten\Core.\Control_Unit.$procmux$3077_CMP $flatten\Core.\Control_Unit.$procmux$2997_CMP $flatten\Core.\Control_Unit.$procmux$2996_CMP $flatten\Core.\Control_Unit.$procmux$3074_CMP $flatten\Core.\Control_Unit.$procmux$2871_CMP $flatten\Core.\Control_Unit.$procmux$2837_CMP $flatten\Core.\Control_Unit.$procmux$3064_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2104: { $flatten\Controller.\Interpreter.$procmux$1581_CMP $auto$opt_reduce.cc:134:opt_pmux$4372 $auto$opt_reduce.cc:134:opt_pmux$4370 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1522: { $flatten\Controller.\Interpreter.$procmux$1616_CMP $flatten\Controller.\Interpreter.$procmux$1612_CMP $flatten\Controller.\Interpreter.$procmux$1608_CMP $flatten\Controller.\Interpreter.$procmux$1582_CMP $flatten\Controller.\Interpreter.$procmux$1581_CMP $flatten\Controller.\Interpreter.$procmux$1577_CMP $flatten\Controller.\Interpreter.$procmux$1576_CMP $flatten\Controller.\Interpreter.$procmux$1572_CMP $flatten\Controller.\Interpreter.$procmux$1562_CMP $flatten\Controller.\Interpreter.$procmux$1558_CMP $auto$opt_reduce.cc:134:opt_pmux$4380 $flatten\Controller.\Interpreter.$procmux$1553_CMP $flatten\Controller.\Interpreter.$procmux$1552_CMP $auto$opt_reduce.cc:134:opt_pmux$4378 $flatten\Controller.\Interpreter.$procmux$1547_CMP $flatten\Controller.\Interpreter.$procmux$1546_CMP $flatten\Controller.\Interpreter.$procmux$1541_CMP $flatten\Controller.\Interpreter.$procmux$1537_CMP $flatten\Controller.\Interpreter.$procmux$1536_CMP $auto$opt_reduce.cc:134:opt_pmux$4376 $flatten\Controller.\Interpreter.$procmux$1530_CMP $flatten\Controller.\Interpreter.$procmux$1529_CMP $flatten\Controller.\Interpreter.$procmux$1528_CMP $auto$opt_reduce.cc:134:opt_pmux$4374 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2180: { $auto$opt_reduce.cc:134:opt_pmux$4382 $flatten\Controller.\Interpreter.$procmux$1581_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2204: { $flatten\Controller.\Interpreter.$procmux$1649_CMP $flatten\Controller.\Interpreter.$procmux$1648_CMP $auto$opt_reduce.cc:134:opt_pmux$4384 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2230: { $auto$opt_reduce.cc:134:opt_pmux$4386 $flatten\Controller.\Interpreter.$procmux$1648_CMP $flatten\Controller.\Interpreter.$procmux$1567_CMP $flatten\Controller.\Interpreter.$procmux$1562_CMP $flatten\Controller.\Interpreter.$procmux$1552_CMP }
    New ctrl vector for $pmux cell $flatten\Core.\Immediate_Generator.$procmux$2687: { $flatten\Core.\Control_Unit.$procmux$3960_CMP $flatten\Core.\Control_Unit.$procmux$3961_CMP $auto$opt_reduce.cc:134:opt_pmux$4390 $flatten\Core.\Control_Unit.$procmux$3962_CMP $auto$opt_reduce.cc:134:opt_pmux$4388 $flatten\Core.\Control_Unit.$procmux$3956_CMP $flatten\Core.\Control_Unit.$procmux$3964_CMP }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Memory.$procmux$2432:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0]
      New connections: $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [31:1] = { $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_EN[31:0]$775 [0] }
    Consolidated identical input bits for $mux cell $flatten\Core.\RegisterBank.$procmux$2478:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\RegisterBank.$procmux$2478_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Core.\RegisterBank.$procmux$2478_Y [0]
      New connections: $flatten\Core.\RegisterBank.$procmux$2478_Y [31:1] = { $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] $flatten\Core.\RegisterBank.$procmux$2478_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Core.\RegisterBank.$procmux$2496:
      Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\Core.\RegisterBank.$procmux$2496_Y
      New ports: A=1'1, B=1'0, Y=$flatten\Core.\RegisterBank.$procmux$2496_Y [0]
      New connections: $flatten\Core.\RegisterBank.$procmux$2496_Y [31:1] = { $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] $flatten\Core.\RegisterBank.$procmux$2496_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Core.\RegisterBank.$procmux$2502:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167
      New ports: A=1'0, B=1'1, Y=$flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0]
      New connections: $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [31:1] = { $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:35$160_EN[31:0]$167 [0] }
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1201:
      Old ports: A=$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$975, B=8'00000000, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$966
      New ports: A=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1183_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$966 [0]
      New connections: $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$966 [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$966 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$966 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$966 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$966 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$966 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$966 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$966 [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1201:
      Old ports: A=$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$975, B=8'00000000, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$966
      New ports: A=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1183_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$966 [0]
      New connections: $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$966 [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$966 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$966 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$966 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$966 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$966 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$966 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_EN[7:0]$966 [0] }
    Consolidated identical input bits for $mux cell $flatten\Core.\RegisterBank.$procmux$2505:
      Old ports: A=$flatten\Core.\RegisterBank.$2$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$182, B=0, Y=$flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171
      New ports: A=$flatten\Core.\RegisterBank.$procmux$2496_Y [0], B=1'0, Y=$flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0]
      New connections: $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [31:1] = { $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:39$162_EN[31:0]$171 [0] }
    Consolidated identical input bits for $mux cell $flatten\Core.\RegisterBank.$procmux$2508:
      Old ports: A=$flatten\Core.\RegisterBank.$2$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$181, B=0, Y=$flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170
      New ports: A=$flatten\Core.\RegisterBank.$procmux$2478_Y [0], B=1'0, Y=$flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0]
      New connections: $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [31:1] = { $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:37$161_EN[31:0]$170 [0] }
  Optimizing cells in module \processorci_top.
Performed a total of 50 changes.

21.11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~30 debug messages>
Removed a total of 10 cells.

21.11.6. Executing OPT_DFF pass (perform DFF optimizations).

21.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 417 unused wires.
<suppressed ~15 debug messages>

21.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.11.9. Rerunning OPT passes. (Maybe there is more to do..)

21.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~167 debug messages>

21.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1794: { $auto$opt_reduce.cc:134:opt_pmux$4314 $auto$opt_reduce.cc:134:opt_pmux$4392 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1941: { $auto$opt_reduce.cc:134:opt_pmux$4314 $auto$opt_reduce.cc:134:opt_pmux$4394 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2230: { $auto$opt_reduce.cc:134:opt_pmux$4386 $flatten\Controller.\Interpreter.$procmux$1648_CMP $flatten\Controller.\Interpreter.$procmux$1567_CMP $auto$opt_reduce.cc:134:opt_pmux$4396 }
    New ctrl vector for $pmux cell $flatten\Core.\Alu.$procmux$4099: { $flatten\Core.\Alu.$procmux$4113_CMP $flatten\Core.\Alu.$procmux$4112_CMP $flatten\Core.\Alu.$procmux$4111_CMP $flatten\Core.\Alu.$procmux$4110_CMP $auto$opt_reduce.cc:134:opt_pmux$4400 $flatten\Core.\Alu.$procmux$4107_CMP $flatten\Core.\Alu.$procmux$4106_CMP $flatten\Core.\Alu.$procmux$4105_CMP $flatten\Core.\Alu.$procmux$4104_CMP $flatten\Core.\Alu.$procmux$4103_CMP $flatten\Core.\Alu.$procmux$4102_CMP $auto$opt_reduce.cc:134:opt_pmux$4398 }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3102: { $flatten\Core.\Control_Unit.$procmux$3092_CMP $auto$opt_reduce.cc:134:opt_pmux$4332 $auto$opt_reduce.cc:134:opt_pmux$4330 $auto$opt_reduce.cc:134:opt_pmux$4328 $flatten\Core.\Control_Unit.$procmux$3002_CMP $auto$opt_reduce.cc:134:opt_pmux$4326 $auto$opt_reduce.cc:134:opt_pmux$4404 $auto$opt_reduce.cc:134:opt_pmux$4402 $auto$opt_reduce.cc:134:opt_pmux$4324 $auto$opt_reduce.cc:134:opt_pmux$4322 $auto$opt_reduce.cc:134:opt_pmux$4320 }
  Optimizing cells in module \processorci_top.
Performed a total of 5 changes.

21.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

21.11.13. Executing OPT_DFF pass (perform DFF optimizations).

21.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 2 unused wires.
<suppressed ~1 debug messages>

21.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.11.16. Rerunning OPT passes. (Maybe there is more to do..)

21.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~167 debug messages>

21.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

21.11.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.11.20. Executing OPT_DFF pass (perform DFF optimizations).

21.11.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.11.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.11.23. Finished OPT passes. (There is nothing left to do.)

21.12. Executing FSM pass (extract and optimize FSM).

21.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking processorci_top.Controller.Interpreter.return_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Found FSM state register processorci_top.Controller.Uart.i_uart_rx.fsm_state.
Not marking processorci_top.Controller.Uart.i_uart_tx.fsm_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Not marking processorci_top.Controller.Uart.state_read as FSM state register:
    Register has an initialization value.
Not marking processorci_top.Controller.Uart.state_write as FSM state register:
    Register has an initialization value.
Found FSM state register processorci_top.Controller.Uart.tx_fifo_read_state.
Not marking processorci_top.Core.CSR_Unit.utime as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Not marking processorci_top.Core.Control_Unit.state as FSM state register:
    Register has an initialization value.
Not marking processorci_top.Core.Mdu.state_div as FSM state register:
    Register has an initialization value.
Not marking processorci_top.Core.Mdu.state_mul as FSM state register:
    Register has an initialization value.
Not marking processorci_top.ResetBootSystem.state as FSM state register:
    Register has an initialization value.
    Circuit seems to be self-resetting.

21.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\Controller.Uart.i_uart_rx.fsm_state' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Controller.\Uart.\i_uart_rx.$procdff$4129
  root of input selection tree: $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1122_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1135_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1148_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1134_Y
  found state code: 3'000
  found ctrl input: \Controller.Uart.i_uart_rx.next_bit
  found state code: 3'011
  found ctrl input: \Controller.Uart.i_uart_rx.payload_done
  found state code: 3'010
  found state code: 3'001
  found ctrl input: \Controller.Uart.i_uart_rx.rxd_reg
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1148_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1139_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1135_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1134_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1122_Y
  ctrl inputs: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.rxd_reg \Controller.Uart.i_uart_rx.next_bit \Controller.Uart.i_uart_rx.payload_done }
  ctrl outputs: { $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1122_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1134_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1135_Y $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1139_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1148_Y $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] }
  transition:      3'000 4'00-- ->      3'001 8'01010001
  transition:      3'000 4'01-- ->      3'000 8'01010000
  transition:      3'000 4'1--- ->      3'000 8'01010000
  transition:      3'010 4'0--0 ->      3'010 8'00100010
  transition:      3'010 4'0--1 ->      3'011 8'00100011
  transition:      3'010 4'1--- ->      3'000 8'00100000
  transition:      3'001 4'0-0- ->      3'001 8'00011001
  transition:      3'001 4'0-1- ->      3'010 8'00011010
  transition:      3'001 4'1--- ->      3'000 8'00011000
  transition:      3'011 4'0-0- ->      3'011 8'10010011
  transition:      3'011 4'0-1- ->      3'000 8'10010000
  transition:      3'011 4'1--- ->      3'000 8'10010000
Extracting FSM `\Controller.Uart.tx_fifo_read_state' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Controller.\Uart.$procdff$4176
  root of input selection tree: $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0]
  found reset state: 2'00 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\Controller.\Uart.$procmux$2261_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2256_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2263_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2250_CMP
  found state code: 2'00
  found state code: 2'11
  found state code: 2'10
  found ctrl input: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1008_Y
  found state code: 2'01
  found ctrl output: $flatten\Controller.\Uart.$procmux$2250_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2256_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2261_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2263_CMP
  ctrl inputs: { \ResetBootSystem.reset_o $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1008_Y }
  ctrl outputs: { $flatten\Controller.\Uart.$procmux$2263_CMP $flatten\Controller.\Uart.$procmux$2261_CMP $flatten\Controller.\Uart.$procmux$2256_CMP $flatten\Controller.\Uart.$procmux$2250_CMP $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] }
  transition:       2'00 2'00 ->       2'00 6'000100
  transition:       2'00 2'01 ->       2'01 6'000101
  transition:       2'00 2'1- ->       2'00 6'000100
  transition:       2'10 2'0- ->       2'11 6'001011
  transition:       2'10 2'1- ->       2'00 6'001000
  transition:       2'01 2'0- ->       2'10 6'100010
  transition:       2'01 2'1- ->       2'00 6'100000
  transition:       2'11 2'0- ->       2'00 6'010000
  transition:       2'11 2'1- ->       2'00 6'010000

21.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$4412' from module `\processorci_top'.
  Merging pattern 2'0- and 2'1- from group (3 0 6'010000).
  Merging pattern 2'1- and 2'0- from group (3 0 6'010000).
Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$4405' from module `\processorci_top'.

21.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 15 unused cells and 15 unused wires.
<suppressed ~16 debug messages>

21.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$4405' from module `\processorci_top'.
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2].
Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$4412' from module `\processorci_top'.
  Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [0].
  Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [1].
  Removing unused output signal $flatten\Controller.\Uart.$procmux$2261_CMP.
  Removing unused output signal $flatten\Controller.\Uart.$procmux$2263_CMP.

21.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$4405' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---
Recoding FSM `$fsm$\Controller.Uart.tx_fifo_read_state$4412' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00 -> ---1
  10 -> --1-
  01 -> -1--
  11 -> 1---

21.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$4405' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Controller.Uart.i_uart_rx.fsm_state$4405 (\Controller.Uart.i_uart_rx.fsm_state):

  Number of input signals:    4
  Number of output signals:   5
  Number of state bits:       4

  Input signals:
    0: \Controller.Uart.i_uart_rx.payload_done
    1: \Controller.Uart.i_uart_rx.next_bit
    2: \Controller.Uart.i_uart_rx.rxd_reg
    3: \ResetBootSystem.reset_o

  Output signals:
    0: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1148_Y
    1: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1139_Y
    2: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1135_Y
    3: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1134_Y
    4: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1122_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 4'01--   ->     0 5'01010
      1:     0 4'1---   ->     0 5'01010
      2:     0 4'00--   ->     2 5'01010
      3:     1 4'1---   ->     0 5'00100
      4:     1 4'0--0   ->     1 5'00100
      5:     1 4'0--1   ->     3 5'00100
      6:     2 4'1---   ->     0 5'00011
      7:     2 4'0-1-   ->     1 5'00011
      8:     2 4'0-0-   ->     2 5'00011
      9:     3 4'0-1-   ->     0 5'10010
     10:     3 4'1---   ->     0 5'10010
     11:     3 4'0-0-   ->     3 5'10010

-------------------------------------

FSM `$fsm$\Controller.Uart.tx_fifo_read_state$4412' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Controller.Uart.tx_fifo_read_state$4412 (\Controller.Uart.tx_fifo_read_state):

  Number of input signals:    2
  Number of output signals:   2
  Number of state bits:       4

  Input signals:
    0: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1008_Y
    1: \ResetBootSystem.reset_o

  Output signals:
    0: $flatten\Controller.\Uart.$procmux$2250_CMP
    1: $flatten\Controller.\Uart.$procmux$2256_CMP

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 2'00   ->     0 2'01
      1:     0 2'1-   ->     0 2'01
      2:     0 2'01   ->     2 2'01
      3:     1 2'1-   ->     0 2'10
      4:     1 2'0-   ->     3 2'10
      5:     2 2'1-   ->     0 2'00
      6:     2 2'0-   ->     1 2'00
      7:     3 2'--   ->     0 2'00

-------------------------------------

21.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$4405' from module `\processorci_top'.
Mapping FSM `$fsm$\Controller.Uart.tx_fifo_read_state$4412' from module `\processorci_top'.

21.13. Executing OPT pass (performing simple optimizations).

21.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~9 debug messages>

21.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.

21.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~165 debug messages>

21.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

21.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $flatten\ResetBootSystem.$procdff$4234 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$4232 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Adding SRST signal on $flatten\Core.\Pc.$procdff$4209 ($dff) from module processorci_top (D = $flatten\Core.\Pc.$procmux$2516_Y, Q = \Core.Pc.Output, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4500 ($sdff) from module processorci_top (D = \Core.Pc.Input, Q = \Core.Pc.Output).
Adding EN signal on $flatten\Core.\Mdu.$procdff$4223 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$mul$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:74$114_Y, Q = \Core.Mdu.acumulador).
Adding SRST signal on $flatten\Core.\Mdu.$procdff$4222 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2643_Y, Q = \Core.Mdu.MUL_RD, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4507 ($sdff) from module processorci_top (D = $flatten\Core.\Mdu.$ternary$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:80$116_Y, Q = \Core.Mdu.MUL_RD).
Adding SRST signal on $flatten\Core.\Mdu.$procdff$4221 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2656_Y, Q = \Core.Mdu.Data_Y, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4509 ($sdff) from module processorci_top (D = \Core.register_data_2, Q = \Core.Mdu.Data_Y).
Adding SRST signal on $flatten\Core.\Mdu.$procdff$4220 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2670_Y, Q = \Core.Mdu.Data_X, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4513 ($sdff) from module processorci_top (D = \Core.register_data_1, Q = \Core.Mdu.Data_X).
Adding SRST signal on $flatten\Core.\Mdu.$procdff$4219 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2620_Y, Q = \Core.Mdu.state_mul, rval = 2'00).
Adding SRST signal on $flatten\Core.\Mdu.$procdff$4218 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2630_Y, Q = \Core.Mdu.mul_done, rval = 1'0).
Adding EN signal on $flatten\Core.\Mdu.$procdff$4217 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2552_Y, Q = \Core.Mdu.divisor).
Adding EN signal on $flatten\Core.\Mdu.$procdff$4216 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2563_Y, Q = \Core.Mdu.DIV_RD).
Adding EN signal on $flatten\Core.\Mdu.$procdff$4215 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2572_Y, Q = \Core.Mdu.quociente_msk).
Adding SRST signal on $flatten\Core.\Mdu.$procdff$4214 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2585_Y, Q = \Core.Mdu.quociente, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4542 ($sdff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2585_Y, Q = \Core.Mdu.quociente).
Adding EN signal on $flatten\Core.\Mdu.$procdff$4213 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2598_Y, Q = \Core.Mdu.dividendo).
Adding EN signal on $flatten\Core.\Mdu.$procdff$4212 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$or$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:99$137_Y, Q = \Core.Mdu.negativo).
Adding SRST signal on $flatten\Core.\Mdu.$procdff$4211 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2535_Y, Q = \Core.Mdu.state_div, rval = 2'00).
Adding SRST signal on $flatten\Core.\Mdu.$procdff$4210 ($dff) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2545_Y, Q = \Core.Mdu.div_done, rval = 1'0).
Adding SRST signal on $flatten\Core.\Control_Unit.$procdff$4235 ($dff) from module processorci_top (D = \Core.Control_Unit.nextstate, Q = \Core.Control_Unit.state, rval = 6'000000).
Adding EN signal on $flatten\Core.\CSR_Unit.$procdff$4231 ($dff) from module processorci_top (D = 64'0000000000000000000000000000000000000000000000000000000000000000, Q = \Core.CSR_Unit.utime).
Adding SRST signal on $flatten\Core.\CSR_Unit.$procdff$4230 ($dff) from module processorci_top (D = $flatten\Core.\CSR_Unit.$add$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:116$101_Y, Q = \Core.CSR_Unit.mcycle, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding SRST signal on $flatten\Core.\CSR_Unit.$procdff$4229 ($dff) from module processorci_top (D = $flatten\Core.\CSR_Unit.$procmux$2715_Y, Q = \Core.CSR_Unit.mtvec, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4573 ($sdff) from module processorci_top (D = \Core.register_data_1, Q = \Core.CSR_Unit.mtvec).
Adding SRST signal on $flatten\Core.\CSR_Unit.$procdff$4228 ($dff) from module processorci_top (D = $flatten\Core.\CSR_Unit.$procmux$2723_Y, Q = \Core.CSR_Unit.mtval, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4577 ($sdff) from module processorci_top (D = \Core.register_data_1, Q = \Core.CSR_Unit.mtval).
Adding SRST signal on $flatten\Core.\CSR_Unit.$procdff$4227 ($dff) from module processorci_top (D = $flatten\Core.\CSR_Unit.$procmux$2732_Y, Q = \Core.CSR_Unit.mcause, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4581 ($sdff) from module processorci_top (D = \Core.register_data_1, Q = \Core.CSR_Unit.mcause).
Adding SRST signal on $flatten\Core.\CSR_Unit.$procdff$4226 ($dff) from module processorci_top (D = $flatten\Core.\CSR_Unit.$procmux$2742_Y, Q = \Core.CSR_Unit.mscratch, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4585 ($sdff) from module processorci_top (D = \Core.register_data_1, Q = \Core.CSR_Unit.mscratch).
Adding SRST signal on $flatten\Core.\CSR_Unit.$procdff$4225 ($dff) from module processorci_top (D = $flatten\Core.\CSR_Unit.$procmux$2753_Y, Q = \Core.CSR_Unit.mepc, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4589 ($sdff) from module processorci_top (D = { \Core.register_data_1 [31:2] 2'00 }, Q = \Core.CSR_Unit.mepc).
Adding SRST signal on $flatten\Core.\CSR_Unit.$procdff$4224 ($dff) from module processorci_top (D = $flatten\Core.\CSR_Unit.$procmux$2702_Y, Q = \Core.CSR_Unit.minstret, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4593 ($sdff) from module processorci_top (D = \Core.register_data_1, Q = \Core.CSR_Unit.minstret [63:32]).
Adding EN signal on $auto$ff.cc:266:slice$4593 ($sdff) from module processorci_top (D = $flatten\Core.\CSR_Unit.$procmux$2700_Y [31:0], Q = \Core.CSR_Unit.minstret [31:0]).
Adding EN signal on $flatten\Core.$procdff$4203 ($dff) from module processorci_top (D = \Core.mdu_out, Q = \Core.mdu_out_reg).
Adding SRST signal on $flatten\Core.$procdff$4202 ($dff) from module processorci_top (D = $flatten\Core.$procmux$2467_Y, Q = \Core.pc_old, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4607 ($sdff) from module processorci_top (D = \Core.Pc.Output, Q = \Core.pc_old).
Adding SRST signal on $flatten\Core.$procdff$4201 ($dff) from module processorci_top (D = \Core.register_data_2_out, Q = \Core.register_data_2, rval = 0).
Adding SRST signal on $flatten\Core.$procdff$4200 ($dff) from module processorci_top (D = \Core.register_data_1_out, Q = \Core.register_data_1, rval = 0).
Adding SRST signal on $flatten\Core.$procdff$4199 ($dff) from module processorci_top (D = \Core.Alu.ALU_out_S, Q = \Core.alu_out_register, rval = 0).
Adding SRST signal on $flatten\Core.$procdff$4198 ($dff) from module processorci_top (D = \Core.read_data, Q = \Core.memory_register, rval = 0).
Adding SRST signal on $flatten\Core.$procdff$4197 ($dff) from module processorci_top (D = $flatten\Core.$procmux$2472_Y, Q = \Core.instruction_register, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4613 ($sdff) from module processorci_top (D = \Core.read_data, Q = \Core.instruction_register).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$4141 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1472_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1466_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1457_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1448_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1439_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1430_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1412_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1421_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4615 ($sdff) from module processorci_top (D = \Controller.Uart.uart_tx_data [7], Q = \Controller.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$4615 ($sdff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1466_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1457_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1448_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1439_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1430_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1412_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1421_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$4139 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1388_Y, Q = \Controller.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$4620 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1388_Y, Q = \Controller.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$4138 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1377_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$4626 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1102_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$4137 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_tx.n_fsm_state, Q = \Controller.Uart.i_uart_tx.fsm_state, rval = 3'000).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$4136 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1366_Y, Q = \Controller.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$4631 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1366_Y, Q = \Controller.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$4135 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1355_Y, Q = \Controller.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4637 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.recieved_data, Q = \Controller.Uart.i_uart_rx.uart_rx_data).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$4133 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_rx.$procmux$1332_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1323_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1314_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1305_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1296_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1287_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1269_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1278_Y }, Q = \Controller.Uart.i_uart_rx.recieved_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4639 ($sdff) from module processorci_top (D = { \Controller.Uart.i_uart_rx.bit_sample \Controller.Uart.i_uart_rx.recieved_data [7:1] }, Q = \Controller.Uart.i_uart_rx.recieved_data).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$4132 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1251_Y, Q = \Controller.Uart.i_uart_rx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$4643 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1142_Y, Q = \Controller.Uart.i_uart_rx.bit_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$4131 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1246_Y, Q = \Controller.Uart.i_uart_rx.bit_sample, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4647 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg, Q = \Controller.Uart.i_uart_rx.bit_sample).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$4130 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1238_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$4649 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1153_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$4128 ($dff) from module processorci_top (D = \rx, Q = \Controller.Uart.i_uart_rx.rxd_reg_0, rval = 1'1).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$4127 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg_0, Q = \Controller.Uart.i_uart_rx.rxd_reg, rval = 1'1).
Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$4126 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1215_Y, Q = \Controller.Uart.TX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$4655 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$962_Y [5:0], Q = \Controller.Uart.TX_FIFO.read_ptr).
Adding EN signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$4125 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$959_DATA, Q = \Controller.Uart.TX_FIFO.read_data).
Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$4121 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1210_Y, Q = \Controller.Uart.TX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$4662 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$978_Y [5:0], Q = \Controller.Uart.TX_FIFO.write_ptr).
Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$4126 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1215_Y, Q = \Controller.Uart.RX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$4664 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$962_Y [5:0], Q = \Controller.Uart.RX_FIFO.read_ptr).
Adding EN signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$4125 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$959_DATA, Q = \Controller.Uart.RX_FIFO.read_data).
Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$4121 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1210_Y, Q = \Controller.Uart.RX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$4671 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$978_Y [5:0], Q = \Controller.Uart.RX_FIFO.write_ptr).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4189 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2386_Y, Q = \Controller.Uart.state_read, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$4673 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2386_Y, Q = \Controller.Uart.state_read).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4188 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2411_Y, Q = \Controller.Uart.counter_read, rval = 3'000).
Adding EN signal on $auto$ff.cc:266:slice$4677 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2411_Y, Q = \Controller.Uart.counter_read).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4187 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2375_Y, Q = \Controller.Uart.rx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4186 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2364_Y, Q = \Controller.Uart.read_response, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4185 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2426_Y, Q = \Controller.Uart.read_data, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4695 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2424_Y, Q = \Controller.Uart.read_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4184 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2308_Y, Q = \Controller.Uart.state_write, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$4701 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2308_Y, Q = \Controller.Uart.state_write).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4183 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2330_Y, Q = \Controller.Uart.counter_write, rval = 3'000).
Adding EN signal on $auto$ff.cc:266:slice$4705 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2330_Y, Q = \Controller.Uart.counter_write).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4182 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2344_Y, Q = \Controller.Uart.write_data_buffer, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4715 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2344_Y, Q = \Controller.Uart.write_data_buffer).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4181 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2358_Y, Q = \Controller.Uart.tx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4725 ($sdff) from module processorci_top (D = \Controller.Uart.write_data_buffer [31:24], Q = \Controller.Uart.tx_fifo_write_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4180 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2290_Y, Q = \Controller.Uart.tx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4179 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2300_Y, Q = \Controller.Uart.write_response, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4178 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2281_Y, Q = \Controller.Uart.rx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4739 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.uart_rx_data, Q = \Controller.Uart.rx_fifo_write_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4177 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2276_Y, Q = \Controller.Uart.rx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4175 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2271_Y, Q = \Controller.Uart.uart_tx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4742 ($sdff) from module processorci_top (D = \Controller.Uart.TX_FIFO.read_data, Q = \Controller.Uart.uart_tx_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4174 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2247_Y, Q = \Controller.Uart.tx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4173 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2255_Y, Q = \Controller.Uart.uart_tx_en, rval = 1'0).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4172 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1794_Y, Q = \Controller.Interpreter.temp_buffer).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4171 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1837_Y, Q = \Controller.Interpreter.accumulator, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4759 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1837_Y [63:8], Q = \Controller.Interpreter.accumulator [63:8]).
Adding EN signal on $auto$ff.cc:266:slice$4759 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1837_Y [7:0], Q = \Controller.Interpreter.accumulator [7:0]).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4170 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1847_Y, Q = \Controller.Interpreter.timeout_counter, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4774 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1847_Y, Q = \Controller.Interpreter.timeout_counter).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4169 ($dff) from module processorci_top (D = { 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, Q = \Controller.Interpreter.timeout).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4168 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1888_Y, Q = \Controller.Interpreter.read_buffer).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4167 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1916_Y, Q = \Controller.Interpreter.communication_buffer, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4790 ($sdff) from module processorci_top (D = \Controller.Uart.read_data, Q = \Controller.Interpreter.communication_buffer).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4166 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1941_Y, Q = \Controller.Interpreter.num_of_positions).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4165 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1963_Y, Q = \Controller.Interpreter.num_of_pages, rval = 24'000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4801 ($sdff) from module processorci_top (D = \Controller.Interpreter.communication_buffer [31:8], Q = \Controller.Interpreter.num_of_pages).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4164 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1969_Y, Q = \Controller.Interpreter.return_state, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4803 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1969_Y, Q = \Controller.Interpreter.return_state).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4163 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1993_Y, Q = \Controller.Interpreter.memory_page_number).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4162 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2001_Y, Q = \Controller.Interpreter.memory_mux_selector, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4818 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2001_Y, Q = \Controller.Interpreter.memory_mux_selector).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4161 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2041_Y, Q = \Controller.Interpreter.end_position, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4822 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2041_Y, Q = \Controller.Interpreter.end_position).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4159 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2083_Y, Q = \Controller.Interpreter.bus_mode, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4826 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2083_Y, Q = \Controller.Interpreter.bus_mode).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4158 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1622_Y, Q = \Controller.Interpreter.reset_bus, rval = 1'1).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4157 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2094_Y, Q = \Controller.Interpreter.num_of_cycles_to_pulse).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4156 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1727_Y, Q = \Controller.Interpreter.core_reset, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4155 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2104_Y, Q = \Controller.Interpreter.core_clk_enable, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4839 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2104_Y, Q = \Controller.Interpreter.core_clk_enable).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4154 ($dff) from module processorci_top (D = \Controller.Interpreter.read_buffer, Q = \Controller.Interpreter.communication_write_data).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4153 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1746_Y, Q = \Controller.Interpreter.communication_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4152 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1769_Y, Q = \Controller.Interpreter.communication_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4151 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1679_Y, Q = \Controller.Interpreter.write_pulse, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4150 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2180_Y, Q = \Controller.Interpreter.counter, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4855 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2180_Y, Q = \Controller.Interpreter.counter).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4149 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1522_Y, Q = \Controller.Interpreter.state, rval = 8'00000000).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4148 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2204_Y, Q = \Controller.Interpreter.write_data).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4147 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2230_Y, Q = \Controller.Interpreter.address).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4146 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1646_Y, Q = \Controller.Interpreter.memory_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4145 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1668_Y, Q = \Controller.Interpreter.memory_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\ClkDivider.$procdff$4142 ($dff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1496_Y, Q = \Controller.ClkDivider.pulse_counter, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4878 ($sdff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1496_Y, Q = \Controller.ClkDivider.pulse_counter).
Adding SRST signal on $flatten\Controller.$procdff$4196 ($dff) from module processorci_top (D = $flatten\Controller.$procmux$2447_Y, Q = \Controller.finish_execution, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4886 ($sdff) from module processorci_top (D = $flatten\Controller.$procmux$2447_Y, Q = \Controller.finish_execution).
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$4778 ($dffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$4778 ($dffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$4778 ($dffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$4778 ($dffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$4778 ($dffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$4778 ($dffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$4778 ($dffe) from module processorci_top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$4778 ($dffe) from module processorci_top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$4590 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$4590 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 33 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 34 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 35 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 36 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 37 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 38 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 39 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 40 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 41 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 42 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 43 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 44 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 45 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 46 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 47 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 48 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 49 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 50 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 51 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 52 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 53 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 54 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 55 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 56 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 57 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 58 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 59 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 60 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 61 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 62 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.
Setting constant 0-bit at position 63 on $auto$ff.cc:266:slice$4571 ($dffe) from module processorci_top.

21.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 180 unused cells and 185 unused wires.
<suppressed ~181 debug messages>

21.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~33 debug messages>

21.13.9. Rerunning OPT passes. (Maybe there is more to do..)

21.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~122 debug messages>

21.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$4645: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.fsm_state [3:2] \Controller.Uart.i_uart_rx.fsm_state [0] }
    New ctrl vector for $pmux cell $flatten\Core.\CSR_Unit.$procmux$2759: { $flatten\Core.\CSR_Unit.$procmux$2771_CMP $flatten\Core.\CSR_Unit.$procmux$2770_CMP $flatten\Core.\CSR_Unit.$procmux$2769_CMP $flatten\Core.\CSR_Unit.$procmux$2714_CMP $flatten\Core.\CSR_Unit.$procmux$2741_CMP $flatten\Core.\CSR_Unit.$procmux$2752_CMP $flatten\Core.\CSR_Unit.$procmux$2731_CMP $flatten\Core.\CSR_Unit.$procmux$2722_CMP $auto$opt_reduce.cc:134:opt_pmux$4274 $auto$opt_reduce.cc:134:opt_pmux$4272 $auto$opt_reduce.cc:134:opt_pmux$4270 $auto$opt_reduce.cc:134:opt_pmux$4268 }
  Optimizing cells in module \processorci_top.
Performed a total of 2 changes.

21.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~102 debug messages>
Removed a total of 34 cells.

21.13.13. Executing OPT_DFF pass (perform DFF optimizations).

21.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 3 unused cells and 37 unused wires.
<suppressed ~4 debug messages>

21.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.13.16. Rerunning OPT passes. (Maybe there is more to do..)

21.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~122 debug messages>

21.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

21.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.13.20. Executing OPT_DFF pass (perform DFF optimizations).

21.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.13.23. Finished OPT passes. (There is nothing left to do.)

21.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Data_Memory.$auto$proc_memwr.cc:45:proc_memwr$4237 (Controller.Data_Memory.memory).
Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$769 (Controller.Data_Memory.memory).
Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Memory.$auto$proc_memwr.cc:45:proc_memwr$4237 (Controller.Memory.memory).
Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$769 (Controller.Memory.memory).
Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$4236 (Controller.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$959 (Controller.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$4236 (Controller.Uart.TX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$959 (Controller.Uart.TX_FIFO.memory).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$4238 (Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$4240 (Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Core.\RegisterBank.$meminit$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:22$183 (Core.RegisterBank.registers).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$4452 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$4477 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$4490 ($ne).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$4427 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1060 ($gt).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:219$1017 ($eq).
Removed top 6 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1021 ($add).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1024 ($add).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1033 ($lt).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1038 ($eq).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1040 ($ge).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1523_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1524_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1526 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1528_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1529_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1530_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1531_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1532_CMP0 ($eq).
Removed top 5 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1534 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1536_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1537_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1539 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1541_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1542_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1546_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1547_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1548_CMP0 ($eq).
Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1550 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1552_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1553_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1554_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1556 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1558_CMP0 ($eq).
Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1560 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1562_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1563_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1564_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1565_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1566_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1567_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1568_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1570 ($mux).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1572_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1574 ($mux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1576_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1577_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1579 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1581_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1582_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1585_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1584 ($pmux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1586_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1587_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1588_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1589_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1590_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1591_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1592_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1593_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1594_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1595_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1596_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1597_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1598_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1599_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1600_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1601_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1602_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1603_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1604_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1605_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1606_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1607_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1608_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1610 ($mux).
Removed top 7 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1612_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1614 ($mux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1648_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1649_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1650_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1683_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1838_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1839_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1840_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1883_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2009_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2042_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2043_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2116_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2117_CMP0 ($eq).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:95$991 ($lt).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:159$996 ($lt).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2295_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2301_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2302_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2314_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2316 ($mux).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2365_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2366_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2380_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2388_CMP0 ($eq).
Removed top 3 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2396 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1207 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1195 ($mux).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$979 ($sub).
Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$979 ($sub).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$978 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$977 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$976 ($eq).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$962 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$961 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$960 ($eq).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1207 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1195 ($mux).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$979 ($sub).
Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$979 ($sub).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$978 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$977 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$976 ($eq).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$962 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$961 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$960 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$4438 ($eq).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1131 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1130 ($mux).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1129 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1128 ($mux).
Removed top 2 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:110$1123 ($eq).
Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:108$1121 ($eq).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:152$1097 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:137$1089 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:135$1087 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1084 ($ne).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1083 ($ne).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:120$1079 ($eq).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1074 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1073 ($mux).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1072 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1071 ($mux).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:94$1067 ($eq).
Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:92$1065 ($eq).
Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Memory.$procmux$2438 ($mux).
Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Data_Memory.$procmux$2438 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:96$746 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$730 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$729 ($mux).
Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$4881 ($ne).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$4891 ($ne).
Removed top 32 bits (of 64) from mux cell processorci_top.$flatten\Core.\CSR_Unit.$procmux$2700 ($mux).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Core.\CSR_Unit.$procmux$2714_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Core.\CSR_Unit.$procmux$2722_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Core.\CSR_Unit.$procmux$2731_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Core.\CSR_Unit.$procmux$2741_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Core.\CSR_Unit.$procmux$2752_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\Core.\CSR_Unit.$procmux$2769_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Core.\Alu.$ternary$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:37$9 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Core.\Alu.$ternary$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:53$20 ($mux).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Core.\Alu.$procmux$4102_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Core.\Alu.$procmux$4109_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Core.\Alu.$procmux$4110_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Core.\Alu.$procmux$4111_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Core.\Alu.$procmux$4112_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Core.\ALU_Control.$procmux$4097_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.\ALU_Control.$procmux$4081_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.\ALU_Control.$procmux$4082_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Core.\ALU_Control.$procmux$4083_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell processorci_top.$flatten\Core.\ALU_Control.$procmux$4085 ($mux).
Removed top 1 bits (of 3) from mux cell processorci_top.$flatten\Core.\Control_Unit.$ternary$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:114$30 ($mux).
Removed top 5 bits (of 7) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$eq$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:197$34 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$eq$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:282$47 ($eq).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Core.\Control_Unit.$ternary$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:566$68 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Core.\Control_Unit.$ternary$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:586$74 ($mux).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$2821_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$2822_CMP0 ($eq).
Removed top 1 bits (of 3) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$2824 ($pmux).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3003_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3004_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3005_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3006_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3007_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3008_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3009_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3045_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3053_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3054_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3058_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3059_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3060_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3061_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3066_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3067_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3069_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3070_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3071_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3073_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3086_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3087_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3092_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3094_CMP0 ($eq).
Removed top 4 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3096_CMP0 ($eq).
Removed top 5 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3097_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3177_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3201_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3202_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3203_CMP0 ($eq).
Removed top 4 bits (of 6) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3204_CMP0 ($eq).
Removed top 5 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3303 ($mux).
Removed top 5 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3328 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3388 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3440 ($mux).
Removed top 5 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3470 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3503 ($mux).
Removed top 1 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3539 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3577 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3626 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3677 ($mux).
Removed top 1 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3729 ($mux).
Removed top 1 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3785 ($mux).
Removed top 1 bits (of 6) from mux cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3839 ($mux).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3903_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3958_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3959_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3962_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Core.\Control_Unit.$procmux$3964_CMP0 ($eq).
Removed top 32 bits (of 64) from port A of cell processorci_top.$flatten\Core.\Mdu.$mul$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:74$114 ($mul).
Removed top 32 bits (of 64) from port B of cell processorci_top.$flatten\Core.\Mdu.$mul$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:74$114 ($mul).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Core.\Mdu.$eq$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:109$138 ($eq).
Removed top 32 bits (of 64) from port Y of cell processorci_top.$flatten\Core.\Mdu.$sub$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:116$140 ($sub).
Removed top 32 bits (of 64) from port B of cell processorci_top.$flatten\Core.\Mdu.$sub$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:116$140 ($sub).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Core.\Mdu.$procmux$2536_CMP0 ($eq).
Removed top 1 bits (of 2) from mux cell processorci_top.$flatten\Core.\Mdu.$procmux$2538 ($mux).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Core.\Mdu.$procmux$2621_CMP0 ($eq).
Removed top 1 bits (of 2) from mux cell processorci_top.$flatten\Core.\Mdu.$procmux$2623 ($mux).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.\AluInputBMUX.$procmux$2526_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.\AluInputBMUX.$procmux$2527_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Core.\AluInputBMUX.$procmux$2528_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.\AluInputAMUX.$procmux$2526_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.\AluInputAMUX.$procmux$2527_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Core.\AluInputAMUX.$procmux$2528_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.\MemoryDataMUX.$procmux$2526_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Core.\MemoryDataMUX.$procmux$2527_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Core.\MemoryDataMUX.$procmux$2528_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Core.\MemoryAddressMUX.$procmux$2528_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Core.\CSR_Unit.$add$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:116$101 ($add).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\ResetBootSystem.$procmux$2790_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$698 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$697 ($add).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$697 ($add).
Removed top 27 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$696 ($lt).
Removed cell processorci_top.$flatten\Core.\CSR_Unit.$procmux$2697 ($mux).
Removed top 20 bits (of 32) from wire processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$729_Y.
Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_ADDR[31:0]$773.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1526_Y.
Removed top 5 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1534_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1539_Y.
Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1550_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1556_Y.
Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1560_Y.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1570_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1574_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1579_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1584_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1610_Y.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1614_Y.
Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$767_ADDR[31:0]$773.
Removed top 1 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2316_Y.
Removed top 3 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2396_Y.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_ADDR[5:0]$964.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_ADDR[5:0]$973.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$961_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$977_Y.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_ADDR[5:0]$964.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_ADDR[5:0]$973.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$954_DATA[7:0]$974.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$961_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$977_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$978_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1128_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1129_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1130_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1131_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1071_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1072_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1073_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1074_Y.
Removed top 1 bits (of 4) from wire processorci_top.$flatten\Core.\ALU_Control.$procmux$4085_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Core.\Alu.$eq$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:45$15_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Core.\Alu.$ternary$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:37$9_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Core.\Alu.$ternary$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:53$20_Y.
Removed top 32 bits (of 64) from wire processorci_top.$flatten\Core.\CSR_Unit.$procmux$2700_Y.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Core.\Control_Unit.$10\nextstate[5:0].
Removed top 1 bits (of 6) from wire processorci_top.$flatten\Core.\Control_Unit.$11\nextstate[5:0].
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Core.\Control_Unit.$12\nextstate[5:0].
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Core.\Control_Unit.$14\nextstate[5:0].
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Core.\Control_Unit.$16\nextstate[5:0].
Removed top 5 bits (of 6) from wire processorci_top.$flatten\Core.\Control_Unit.$19\nextstate[5:0].
Removed top 5 bits (of 6) from wire processorci_top.$flatten\Core.\Control_Unit.$21\nextstate[5:0].
Removed top 1 bits (of 6) from wire processorci_top.$flatten\Core.\Control_Unit.$5\nextstate[5:0].
Removed top 1 bits (of 6) from wire processorci_top.$flatten\Core.\Control_Unit.$6\nextstate[5:0].
Removed top 1 bits (of 6) from wire processorci_top.$flatten\Core.\Control_Unit.$7\nextstate[5:0].
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Core.\Control_Unit.$ternary$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:586$74_Y.
Removed top 1 bits (of 2) from wire processorci_top.$flatten\Core.\Mdu.$procmux$2538_Y.
Removed top 1 bits (of 2) from wire processorci_top.$flatten\Core.\Mdu.$procmux$2623_Y.
Removed top 32 bits (of 64) from wire processorci_top.$flatten\Core.\Mdu.$sub$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:116$140_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$697_Y.

21.15. Executing PEEPOPT pass (run peephole optimizers).

21.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 56 unused wires.
<suppressed ~1 debug messages>

21.17. Executing SHARE pass (SAT-based resource sharing).
Found 6 cells in module processorci_top that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\Core.\RegisterBank.$memrd$\registers$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/registers.v:28$165 ($memrd):
    Found 12 activation_patterns using ctrl signal { $auto$opt_reduce.cc:134:opt_pmux$4398 $flatten\Core.\AluInputBMUX.$procmux$2526_CMP $flatten\Core.\Alu.$procmux$4113_CMP $flatten\Core.\Alu.$procmux$4112_CMP $flatten\Core.\Alu.$procmux$4111_CMP $flatten\Core.\Alu.$procmux$4110_CMP $flatten\Core.\Alu.$procmux$4107_CMP $flatten\Core.\Alu.$procmux$4106_CMP $flatten\Core.\Alu.$procmux$4105_CMP $flatten\Core.\Alu.$procmux$4104_CMP $flatten\Core.\Alu.$procmux$4103_CMP $flatten\Core.\Alu.$procmux$4102_CMP $auto$opt_reduce.cc:134:opt_pmux$4400 }.
    No candidates found.
  Analyzing resource sharing options for $flatten\Core.\Alu.$sshr$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:51$18 ($sshr):
    Found 1 activation_patterns using ctrl signal $flatten\Core.\Alu.$procmux$4102_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\Core.\Alu.$shr$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:49$17 ($shr):
    Found 1 activation_patterns using ctrl signal $flatten\Core.\Alu.$procmux$4103_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\Core.\Alu.$shl$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:47$16 ($shl):
    Found 1 activation_patterns using ctrl signal $flatten\Core.\Alu.$procmux$4104_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$769 ($memrd):
    Found 2 activation_patterns using ctrl signal { \Controller.Memory.memory_read $flatten\Controller.\Interpreter.$procmux$1566_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }.
    No candidates found.
  Analyzing resource sharing options for $flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$769 ($memrd):
    Found 1 activation_patterns using ctrl signal { \Controller.Data_Memory.memory_read $flatten\Controller.\Interpreter.$procmux$1566_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }.
    No candidates found.

21.18. Executing TECHMAP pass (map to technology primitives).

21.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

21.18.2. Continuing TECHMAP pass.
Using template $paramod$141b0f41d8ab4b936f42c52ead39f1f9a7c93200\_90_lut_cmp_ for cells of type $lt.
No more expansions possible.
<suppressed ~223 debug messages>

21.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 6 unused wires.
<suppressed ~1 debug messages>

21.21. Executing TECHMAP pass (map to technology primitives).

21.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

21.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.

21.21.3. Continuing TECHMAP pass.
Using template $paramod$e88c2150f27e199b5b4c38f191932e407250eaa3\_80_mul for cells of type $mul.
Using template $paramod$fac210dc6e441ade6153a47dcf32d681f9d41bee\_80_mul for cells of type $__mul.
Using template $paramod$de927ffa49f2a1327665483e9418148a52f3d36b\_80_mul for cells of type $__mul.
Using template $paramod$f84b7e774a64cf6bd61391522b3eee9d216e6e7e\_80_mul for cells of type $__mul.
Using template $paramod$0c59eac522c8fc6cf582c390b8c4bd5bae1bb887\_80_mul for cells of type $__mul.
Using template $paramod$84e4af21b083f56ce59bb3210f4da5751fbe9bb3\_80_mul for cells of type $__mul.
Using template $paramod$ba1b36458f074a6329f9cad9c8b71be8774bccea\_80_mul for cells of type $__mul.
Using template $paramod$7c1afd677c664a6f211892c24ab4c74153b5be67\$__MUL18X18 for cells of type $__MUL18X18.
Using template $paramod$e5ade21dea2c4d51df0cdca72b2a93a08fd8e7d1\$__MUL18X18 for cells of type $__MUL18X18.
Using template $paramod$bef2a6330e4e8c17c10f220fb2d17af741212f04\$__MUL18X18 for cells of type $__MUL18X18.
Using template $paramod$ab0a030b3329c9db46a487d220064a2a8467942a\$__MUL18X18 for cells of type $__MUL18X18.
No more expansions possible.
<suppressed ~670 debug messages>

21.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module processorci_top:
  creating $macc model for $techmap$flatten\Core.\Mdu.$mul$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:74$114.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4963 ($add).
  creating $macc model for $techmap$flatten\Core.\Mdu.$mul$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:74$114.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4960 ($add).
  creating $macc model for $techmap$flatten\Core.\Mdu.$mul$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:74$114.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$4957 ($add).
  creating $macc model for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1061 ($sub).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1016 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1020 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1021 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1024 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1031 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1035 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1023 ($sub).
  creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$998 ($add).
  creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$993 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$961 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$977 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$979 ($sub).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$961 ($add).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$977 ($add).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$979 ($sub).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1142 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1153 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1091 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1102 ($add).
  creating $macc model for $flatten\Core.$add$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:142$708 ($add).
  creating $macc model for $flatten\Core.$sub$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:140$707 ($sub).
  creating $macc model for $flatten\Core.\Alu.$add$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:33$6 ($add).
  creating $macc model for $flatten\Core.\Alu.$sub$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:35$7 ($sub).
  creating $macc model for $flatten\Core.\CSR_Unit.$add$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:116$101 ($add).
  creating $macc model for $flatten\Core.\Mdu.$neg$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:127$146 ($neg).
  creating $macc model for $flatten\Core.\Mdu.$neg$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:129$148 ($neg).
  creating $macc model for $flatten\Core.\Mdu.$neg$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:97$122 ($neg).
  creating $macc model for $flatten\Core.\Mdu.$neg$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:98$126 ($neg).
  creating $macc model for $flatten\Core.\Mdu.$sub$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:116$140 ($sub).
  creating $macc model for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$697 ($add).
  creating $alu model for $macc $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$697.
  creating $alu model for $macc $flatten\Core.\Mdu.$sub$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:116$140.
  creating $alu model for $macc $flatten\Core.\Mdu.$neg$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:98$126.
  creating $alu model for $macc $flatten\Core.\Mdu.$neg$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:97$122.
  creating $alu model for $macc $flatten\Core.\Mdu.$neg$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:129$148.
  creating $alu model for $macc $flatten\Core.\Mdu.$neg$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:127$146.
  creating $alu model for $macc $flatten\Core.\CSR_Unit.$add$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:116$101.
  creating $alu model for $macc $flatten\Core.\Alu.$sub$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:35$7.
  creating $alu model for $macc $flatten\Core.\Alu.$add$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:33$6.
  creating $alu model for $macc $flatten\Core.$sub$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:140$707.
  creating $alu model for $macc $flatten\Core.$add$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:142$708.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1102.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1091.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1153.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1142.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$979.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$977.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$961.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$979.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$977.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$961.
  creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$993.
  creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$998.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1023.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1035.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1031.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1024.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1021.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1020.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1016.
  creating $alu model for $macc $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1061.
  creating $alu model for $macc $techmap$flatten\Core.\Mdu.$mul$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:74$114.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$4957.
  creating $alu model for $macc $techmap$flatten\Core.\Mdu.$mul$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:74$114.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4960.
  creating $alu model for $macc $techmap$flatten\Core.\Mdu.$mul$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:74$114.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4963.
  creating $alu model for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1060 ($gt): new $alu
  creating $alu model for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1040 ($ge): new $alu
  creating $alu model for $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1033 ($lt): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1040.
  creating $alu model for $flatten\Core.\Alu.$ge$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:53$19 ($ge): new $alu
  creating $alu model for $flatten\Core.\Alu.$lt$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:37$8 ($lt): merged with $flatten\Core.\Alu.$ge$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:53$19.
  creating $alu model for $flatten\Core.\Mdu.$le$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:115$139 ($le): new $alu
  creating $alu model for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$696 ($lt): new $alu
  creating $alu model for $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1038 ($eq): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1040.
  creating $alu model for $flatten\Core.\Alu.$eq$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:45$15 ($eq): merged with $flatten\Core.\Alu.$ge$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:53$19.
  creating $alu model for $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$698 ($eq): merged with $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$696.
  creating $alu cell for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$696, $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$698: $auto$alumacc.cc:485:replace_alu$4977
  creating $alu cell for $flatten\Core.\Mdu.$le$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:115$139: $auto$alumacc.cc:485:replace_alu$4988
  creating $alu cell for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1040, $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1033, $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1038: $auto$alumacc.cc:485:replace_alu$5001
  creating $alu cell for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1060: $auto$alumacc.cc:485:replace_alu$5014
  creating $alu cell for $techmap$flatten\Core.\Mdu.$mul$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:74$114.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4963: $auto$alumacc.cc:485:replace_alu$5019
  creating $alu cell for $techmap$flatten\Core.\Mdu.$mul$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:74$114.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4960: $auto$alumacc.cc:485:replace_alu$5022
  creating $alu cell for $techmap$flatten\Core.\Mdu.$mul$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:74$114.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$4957: $auto$alumacc.cc:485:replace_alu$5025
  creating $alu cell for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1061: $auto$alumacc.cc:485:replace_alu$5028
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1016: $auto$alumacc.cc:485:replace_alu$5031
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1020: $auto$alumacc.cc:485:replace_alu$5034
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1021: $auto$alumacc.cc:485:replace_alu$5037
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1024: $auto$alumacc.cc:485:replace_alu$5040
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1031: $auto$alumacc.cc:485:replace_alu$5043
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1035: $auto$alumacc.cc:485:replace_alu$5046
  creating $alu cell for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1023: $auto$alumacc.cc:485:replace_alu$5049
  creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$998: $auto$alumacc.cc:485:replace_alu$5052
  creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$993: $auto$alumacc.cc:485:replace_alu$5055
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$961: $auto$alumacc.cc:485:replace_alu$5058
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$977: $auto$alumacc.cc:485:replace_alu$5061
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$979: $auto$alumacc.cc:485:replace_alu$5064
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$961: $auto$alumacc.cc:485:replace_alu$5067
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$977: $auto$alumacc.cc:485:replace_alu$5070
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$979: $auto$alumacc.cc:485:replace_alu$5073
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1142: $auto$alumacc.cc:485:replace_alu$5076
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1153: $auto$alumacc.cc:485:replace_alu$5079
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1091: $auto$alumacc.cc:485:replace_alu$5082
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1102: $auto$alumacc.cc:485:replace_alu$5085
  creating $alu cell for $flatten\Core.$add$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:142$708: $auto$alumacc.cc:485:replace_alu$5088
  creating $alu cell for $flatten\Core.$sub$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/core.v:140$707: $auto$alumacc.cc:485:replace_alu$5091
  creating $alu cell for $flatten\Core.\Alu.$ge$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:53$19, $flatten\Core.\Alu.$lt$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:37$8, $flatten\Core.\Alu.$eq$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:45$15: $auto$alumacc.cc:485:replace_alu$5094
  creating $alu cell for $flatten\Core.\Alu.$add$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:33$6: $auto$alumacc.cc:485:replace_alu$5107
  creating $alu cell for $flatten\Core.\Alu.$sub$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/alu.v:35$7: $auto$alumacc.cc:485:replace_alu$5110
  creating $alu cell for $flatten\Core.\CSR_Unit.$add$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/csr_unit.v:116$101: $auto$alumacc.cc:485:replace_alu$5113
  creating $alu cell for $flatten\Core.\Mdu.$neg$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:127$146: $auto$alumacc.cc:485:replace_alu$5116
  creating $alu cell for $flatten\Core.\Mdu.$neg$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:129$148: $auto$alumacc.cc:485:replace_alu$5119
  creating $alu cell for $flatten\Core.\Mdu.$neg$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:97$122: $auto$alumacc.cc:485:replace_alu$5122
  creating $alu cell for $flatten\Core.\Mdu.$neg$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:98$126: $auto$alumacc.cc:485:replace_alu$5125
  creating $alu cell for $flatten\Core.\Mdu.$sub$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/mdu.v:116$140: $auto$alumacc.cc:485:replace_alu$5128
  creating $alu cell for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$697: $auto$alumacc.cc:485:replace_alu$5131
  created 39 $alu and 0 $macc cells.

21.23. Executing OPT pass (performing simple optimizations).

21.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~4 debug messages>

21.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~122 debug messages>

21.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

21.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~12 debug messages>
Removed a total of 4 cells.

21.23.6. Executing OPT_DFF pass (perform DFF optimizations).

21.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1 unused cells and 66 unused wires.
<suppressed ~2 debug messages>

21.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.23.9. Rerunning OPT passes. (Maybe there is more to do..)

21.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~122 debug messages>

21.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

21.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.23.13. Executing OPT_DFF pass (perform DFF optimizations).

21.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.23.16. Finished OPT passes. (There is nothing left to do.)

21.24. Executing MEMORY pass.

21.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

21.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

21.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing processorci_top.Controller.Data_Memory.memory write port 0.
  Analyzing processorci_top.Controller.Memory.memory write port 0.
  Analyzing processorci_top.Controller.Uart.RX_FIFO.memory write port 0.
  Analyzing processorci_top.Controller.Uart.TX_FIFO.memory write port 0.
  Analyzing processorci_top.Core.RegisterBank.registers write port 0.
  Analyzing processorci_top.Core.RegisterBank.registers write port 1.
  Analyzing processorci_top.Core.RegisterBank.registers write port 2.

21.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

21.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no output FF found.
Checking read port `\Controller.Memory.memory'[0] in module `\processorci_top': no output FF found.
Checking read port `\Controller.Uart.RX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\Controller.Uart.TX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\Core.RegisterBank.registers'[0] in module `\processorci_top': no output FF found.
Checking read port `\Core.RegisterBank.registers'[1] in module `\processorci_top': merging output FF to cell.
    Write port 0: don't care on collision.
    Write port 1: non-transparent.
    Write port 2: non-transparent.
Checking read port `\Core.RegisterBank.registers'[2] in module `\processorci_top': merging output FF to cell.
    Write port 0: don't care on collision.
    Write port 1: non-transparent.
    Write port 2: non-transparent.
Checking read port address `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no address FF found.
Checking read port address `\Controller.Memory.memory'[0] in module `\processorci_top': no address FF found.
Checking read port address `\Core.RegisterBank.registers'[0] in module `\processorci_top': address FF has fully-defined init value, not supported.

21.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 4 unused cells and 86 unused wires.
<suppressed ~9 debug messages>

21.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating read ports of memory processorci_top.Core.RegisterBank.registers by address:
Consolidating write ports of memory processorci_top.Core.RegisterBank.registers by address:
  Merging ports 0, 2 (address 5'00000).
Consolidating write ports of memory processorci_top.Core.RegisterBank.registers by address:
Consolidating write ports of memory processorci_top.Core.RegisterBank.registers using sat-based resource sharing:
  Checking group clocked with posedge \Core.CSR_Unit.clk, width 32: ports 0, 1.
  Common input cone for all EN signals: 14 cells.
  Size of unconstrained SAT problem: 110 variables, 305 clauses
  Merging port 1 into port 0.

21.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

21.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).

21.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory processorci_top.Controller.Data_Memory.memory via $__TRELLIS_DPR16X4_
mapping memory processorci_top.Controller.Memory.memory via $__TRELLIS_DPR16X4_
mapping memory processorci_top.Controller.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of processorci_top.Controller.Uart.RX_FIFO.memory: $\Controller.Uart.RX_FIFO.memory$rdreg[0]
mapping memory processorci_top.Controller.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of processorci_top.Controller.Uart.TX_FIFO.memory: $\Controller.Uart.TX_FIFO.memory$rdreg[0]
mapping memory processorci_top.Core.RegisterBank.registers via $__TRELLIS_DPR16X4_
Extracted data FF from read port 1 of processorci_top.Core.RegisterBank.registers: $\Core.RegisterBank.registers$rdreg[1]
Extracted data FF from read port 2 of processorci_top.Core.RegisterBank.registers: $\Core.RegisterBank.registers$rdreg[2]
<suppressed ~1178 debug messages>

21.27. Executing TECHMAP pass (map to technology primitives).

21.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

21.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.

21.27.3. Continuing TECHMAP pass.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$514fc941ac1ae997c717a8e6a1180ed8e0cf8fa9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~1107 debug messages>

21.28. Executing OPT pass (performing simple optimizations).

21.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~311 debug messages>

21.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

21.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $flatten\ResetBootSystem.$procdff$4233 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Adding SRST signal on $auto$ff.cc:266:slice$4811 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1035_Y, Q = \Controller.Interpreter.memory_page_number, rval = 24'000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4750 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1794_Y [1:0], Q = \Controller.Interpreter.temp_buffer [1:0]).
Adding SRST signal on $auto$ff.cc:266:slice$4533 ($dffe) from module processorci_top (D = \Core.Mdu.quociente_msk [31:1], Q = \Core.Mdu.quociente_msk [30:0], rval = 31'0000000000000000000000000000000).
Adding SRST signal on $auto$ff.cc:266:slice$4519 ($dffe) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2555_Y [63], Q = \Core.Mdu.divisor [63], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$4484 ($dffe) from module processorci_top (D = $flatten\ResetBootSystem.$procmux$2787_Y, Q = \ResetBootSystem.counter, rval = 6'000000).

21.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 8 unused cells and 7674 unused wires.
<suppressed ~9 debug messages>

21.28.5. Rerunning OPT passes. (Removed registers in this run.)

21.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~7 debug messages>

21.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$7691 ($sdffce) from module processorci_top (D = $auto$wreduce.cc:461:run$4950 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).
Adding SRST signal on $auto$ff.cc:266:slice$7690 ($dffe) from module processorci_top (D = \Core.Mdu.divisor [31:1], Q = \Core.Mdu.divisor [30:0], rval = 31'0000000000000000000000000000000).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$7689 ($sdffce) from module processorci_top.

21.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 7 unused cells and 10 unused wires.
<suppressed ~10 debug messages>

21.28.10. Rerunning OPT passes. (Removed registers in this run.)

21.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.28.13. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$7698 ($dffe) from module processorci_top (D = $flatten\Core.\Mdu.$procmux$2555_Y [62], Q = \Core.Mdu.divisor [62], rval = 1'0).

21.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.28.15. Rerunning OPT passes. (Removed registers in this run.)

21.28.16. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.28.17. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.28.18. Executing OPT_DFF pass (perform DFF optimizations).

21.28.19. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.28.20. Finished fast OPT passes.

21.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

21.30. Executing OPT pass (performing simple optimizations).

21.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $auto$memory_share.cc:453:consolidate_wr_using_sat$5235: $auto$rtlil.cc:2497:ReduceOr$5229 -> 1'1
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~81 debug messages>

21.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$7685: { $auto$opt_dff.cc:194:make_patterns_logic$7682 $auto$opt_dff.cc:194:make_patterns_logic$4753 $auto$opt_dff.cc:194:make_patterns_logic$4751 $auto$fsm_map.cc:74:implement_pattern_cache$4472 }
    Consolidated identical input bits for $mux cell $flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$729:
      Old ports: A=\Controller.core_address_memory [11:0], B={ \Controller.Interpreter.memory_page_number [5:0] \Controller.core_address_memory [5:0] }, Y=$auto$wreduce.cc:461:run$4896 [11:0]
      New ports: A=\Controller.core_address_memory [11:6], B=\Controller.Interpreter.memory_page_number [5:0], Y=$auto$wreduce.cc:461:run$4896 [11:6]
      New connections: $auto$wreduce.cc:461:run$4896 [5:0] = \Controller.core_address_memory [5:0]
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1534:
      Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$4899 [2:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$4899 [2] $auto$wreduce.cc:461:run$4899 [0] }
      New connections: $auto$wreduce.cc:461:run$4899 [1] = $auto$wreduce.cc:461:run$4899 [0]
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1539:
      Old ports: A=7'1010010, B=7'0010101, Y=$auto$wreduce.cc:461:run$4900 [6:0]
      New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$4900 [1:0]
      New connections: $auto$wreduce.cc:461:run$4900 [6:2] = { $auto$wreduce.cc:461:run$4900 [1] 3'010 $auto$wreduce.cc:461:run$4900 [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1550:
      Old ports: A=4'1100, B=4'0000, Y=$auto$wreduce.cc:461:run$4901 [3:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$4901 [2]
      New connections: { $auto$wreduce.cc:461:run$4901 [3] $auto$wreduce.cc:461:run$4901 [1:0] } = { $auto$wreduce.cc:461:run$4901 [2] 2'00 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1560:
      Old ports: A=4'1001, B=4'0000, Y=$auto$wreduce.cc:461:run$4903 [3:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$4903 [0]
      New connections: $auto$wreduce.cc:461:run$4903 [3:1] = { $auto$wreduce.cc:461:run$4903 [0] 2'00 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1574:
      Old ports: A=7'0000110, B=7'1010111, Y=$auto$wreduce.cc:461:run$4905 [6:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$4905 [0]
      New connections: $auto$wreduce.cc:461:run$4905 [6:1] = { $auto$wreduce.cc:461:run$4905 [0] 1'0 $auto$wreduce.cc:461:run$4905 [0] 3'011 }
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$1969:
      Old ports: A=8'00001011, B=302978816, Y=$flatten\Controller.\Interpreter.$procmux$1969_Y
      New ports: A=5'01011, B=20'10010011111011100000, Y=$flatten\Controller.\Interpreter.$procmux$1969_Y [4:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$1969_Y [7:5] = 3'000
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2094:
      Old ports: A={ 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, B={ 40'0000000000000000000000000001010000000000 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2094_Y
      New ports: A=\Controller.Interpreter.communication_buffer [31:8], B={ 24'000000000000000000010100 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2094_Y [23:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$2094_Y [31:24] = 8'00000000
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2104: $auto$opt_reduce.cc:134:opt_pmux$4372
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2308:
      Old ports: A=4'0000, B={ 1'0 $auto$wreduce.cc:461:run$4911 [2:0] 12'000100100011 }, Y=$flatten\Controller.\Uart.$procmux$2308_Y
      New ports: A=3'000, B={ $auto$wreduce.cc:461:run$4911 [2:0] 9'001010011 }, Y=$flatten\Controller.\Uart.$procmux$2308_Y [2:0]
      New connections: $flatten\Controller.\Uart.$procmux$2308_Y [3] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2316:
      Old ports: A=3'000, B=3'100, Y=$auto$wreduce.cc:461:run$4911 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$4911 [2]
      New connections: $auto$wreduce.cc:461:run$4911 [1:0] = 2'00
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2392:
      Old ports: A=4'0010, B=4'0100, Y=$flatten\Controller.\Uart.$procmux$2392_Y
      New ports: A=2'01, B=2'10, Y=$flatten\Controller.\Uart.$procmux$2392_Y [2:1]
      New connections: { $flatten\Controller.\Uart.$procmux$2392_Y [3] $flatten\Controller.\Uart.$procmux$2392_Y [0] } = 2'00
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_rx.$procmux$1350:
      Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$4923 [0] 1'0 $auto$wreduce.cc:461:run$4924 [1:0] 2'01 \Controller.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$4926 [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state
      New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$4923 [0] $auto$wreduce.cc:461:run$4924 [1:0] 1'1 \Controller.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$4926 [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state [1:0]
      New connections: \Controller.Uart.i_uart_rx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1131:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$4926 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$4926 [0]
      New connections: $auto$wreduce.cc:461:run$4926 [1] = $auto$wreduce.cc:461:run$4926 [0]
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_tx.$procmux$1487:
      Old ports: A=3'000, B={ 2'00 \Controller.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$4928 [1:0] 2'01 \Controller.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$4930 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state
      New ports: A=2'00, B={ 1'0 \Controller.Uart.uart_tx_en $auto$wreduce.cc:461:run$4928 [1:0] 1'1 \Controller.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$4930 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state [1:0]
      New connections: \Controller.Uart.i_uart_tx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1074:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$4930 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$4930 [0]
      New connections: $auto$wreduce.cc:461:run$4930 [1] = $auto$wreduce.cc:461:run$4930 [0]
    Consolidated identical input bits for $mux cell $flatten\Core.\ALU_Control.$procmux$4077:
      Old ports: A=4'1001, B=4'0011, Y=$flatten\Core.\ALU_Control.$procmux$4077_Y
      New ports: A=2'10, B=2'01, Y={ $flatten\Core.\ALU_Control.$procmux$4077_Y [3] $flatten\Core.\ALU_Control.$procmux$4077_Y [1] }
      New connections: { $flatten\Core.\ALU_Control.$procmux$4077_Y [2] $flatten\Core.\ALU_Control.$procmux$4077_Y [0] } = 2'01
    Consolidated identical input bits for $mux cell $flatten\Core.\ALU_Control.$procmux$4085:
      Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$4931 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$4931 [2]
      New connections: $auto$wreduce.cc:461:run$4931 [1:0] = 2'10
    Consolidated identical input bits for $pmux cell $flatten\Core.\Control_Unit.$procmux$2995:
      Old ports: A=4'0000, B=8'10001001, Y=\Core.control_unit_aluop
      New ports: A=2'00, B=4'1011, Y={ \Core.control_unit_aluop [3] \Core.control_unit_aluop [0] }
      New connections: \Core.control_unit_aluop [2:1] = 2'00
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3312:
      Old ports: A=6'101101, B=6'000000, Y=$flatten\Core.\Control_Unit.$20\nextstate[5:0]
      New ports: A=1'1, B=1'0, Y=$flatten\Core.\Control_Unit.$20\nextstate[5:0] [0]
      New connections: $flatten\Core.\Control_Unit.$20\nextstate[5:0] [5:1] = { $flatten\Core.\Control_Unit.$20\nextstate[5:0] [0] 1'0 $flatten\Core.\Control_Unit.$20\nextstate[5:0] [0] $flatten\Core.\Control_Unit.$20\nextstate[5:0] [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3347:
      Old ports: A=6'000000, B=6'100101, Y=$flatten\Core.\Control_Unit.$18\nextstate[5:0]
      New ports: A=1'0, B=1'1, Y=$flatten\Core.\Control_Unit.$18\nextstate[5:0] [0]
      New connections: $flatten\Core.\Control_Unit.$18\nextstate[5:0] [5:1] = { $flatten\Core.\Control_Unit.$18\nextstate[5:0] [0] 2'00 $flatten\Core.\Control_Unit.$18\nextstate[5:0] [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3503:
      Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$4938 [2:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$4938 [2] $auto$wreduce.cc:461:run$4938 [0] }
      New connections: $auto$wreduce.cc:461:run$4938 [1] = $auto$wreduce.cc:461:run$4938 [0]
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3539:
      Old ports: A=5'00000, B=5'10010, Y=$auto$wreduce.cc:461:run$4937 [4:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$4937 [1]
      New connections: { $auto$wreduce.cc:461:run$4937 [4:2] $auto$wreduce.cc:461:run$4937 [0] } = { $auto$wreduce.cc:461:run$4937 [1] 3'000 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3577:
      Old ports: A=3'110, B=3'000, Y=$auto$wreduce.cc:461:run$4936 [2:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$4936 [1]
      New connections: { $auto$wreduce.cc:461:run$4936 [2] $auto$wreduce.cc:461:run$4936 [0] } = { $auto$wreduce.cc:461:run$4936 [1] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3626:
      Old ports: A=3'101, B=3'000, Y=$flatten\Core.\Control_Unit.$9\nextstate[5:0] [2:0]
      New ports: A=1'1, B=1'0, Y=$flatten\Core.\Control_Unit.$9\nextstate[5:0] [0]
      New connections: $flatten\Core.\Control_Unit.$9\nextstate[5:0] [2:1] = { $flatten\Core.\Control_Unit.$9\nextstate[5:0] [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3729:
      Old ports: A=5'00101, B=5'11000, Y=$auto$wreduce.cc:461:run$4945 [4:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$4945 [3] $auto$wreduce.cc:461:run$4945 [0] }
      New connections: { $auto$wreduce.cc:461:run$4945 [4] $auto$wreduce.cc:461:run$4945 [2:1] } = { $auto$wreduce.cc:461:run$4945 [3] $auto$wreduce.cc:461:run$4945 [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3785:
      Old ports: A=5'00011, B=5'10110, Y=$auto$wreduce.cc:461:run$4944 [4:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$4944 [2] $auto$wreduce.cc:461:run$4944 [0] }
      New connections: { $auto$wreduce.cc:461:run$4944 [4:3] $auto$wreduce.cc:461:run$4944 [1] } = { $auto$wreduce.cc:461:run$4944 [2] 2'01 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3900:
      Old ports: A=6'000110, B=6'101111, Y=$flatten\Core.\Control_Unit.$4\nextstate[5:0]
      New ports: A=1'0, B=1'1, Y=$flatten\Core.\Control_Unit.$4\nextstate[5:0] [0]
      New connections: $flatten\Core.\Control_Unit.$4\nextstate[5:0] [5:1] = { $flatten\Core.\Control_Unit.$4\nextstate[5:0] [0] 1'0 $flatten\Core.\Control_Unit.$4\nextstate[5:0] [0] 2'11 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$4019:
      Old ports: A=6'000000, B=6'101110, Y=$flatten\Core.\Control_Unit.$2\nextstate[5:0]
      New ports: A=1'0, B=1'1, Y=$flatten\Core.\Control_Unit.$2\nextstate[5:0] [1]
      New connections: { $flatten\Core.\Control_Unit.$2\nextstate[5:0] [5:2] $flatten\Core.\Control_Unit.$2\nextstate[5:0] [0] } = { $flatten\Core.\Control_Unit.$2\nextstate[5:0] [1] 1'0 $flatten\Core.\Control_Unit.$2\nextstate[5:0] [1] $flatten\Core.\Control_Unit.$2\nextstate[5:0] [1] 1'0 }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$4025: { $flatten\Core.\Control_Unit.$procmux$3206_CMP \Core.Control_Unit.ir_write $flatten\Core.\Control_Unit.$procmux$3097_CMP $flatten\Core.\Control_Unit.$procmux$3096_CMP $flatten\Core.\Control_Unit.$procmux$3204_CMP $flatten\Core.\Control_Unit.$procmux$3177_CMP $flatten\Core.\Control_Unit.$procmux$3069_CMP $auto$opt_reduce.cc:134:opt_pmux$4368 $flatten\Core.\Control_Unit.$procmux$3203_CMP $flatten\Core.\Control_Unit.$procmux$3009_CMP $flatten\Core.\Control_Unit.$procmux$3060_CMP $flatten\Core.\Control_Unit.$procmux$3094_CMP $flatten\Core.\Control_Unit.$procmux$3202_CMP $flatten\Core.\Control_Unit.$procmux$3008_CMP $flatten\Core.\Control_Unit.$procmux$3092_CMP $flatten\Core.\Control_Unit.$procmux$3201_CMP $flatten\Core.\Control_Unit.$procmux$3007_CMP $flatten\Core.\Control_Unit.$procmux$3005_CMP $flatten\Core.\Control_Unit.$procmux$3004_CMP $auto$opt_reduce.cc:134:opt_pmux$7704 $flatten\Core.\Control_Unit.$procmux$3086_CMP $flatten\Core.\Control_Unit.$procmux$3002_CMP $auto$opt_reduce.cc:134:opt_pmux$7702 $flatten\Core.\Control_Unit.$procmux$3081_CMP $flatten\Core.\Control_Unit.$procmux$2872_CMP $flatten\Core.\Control_Unit.$procmux$3080_CMP $flatten\Core.\Control_Unit.$procmux$3200_CMP $flatten\Core.\Control_Unit.$procmux$2999_CMP $flatten\Core.\Control_Unit.$procmux$2998_CMP $flatten\Core.\Control_Unit.$procmux$3077_CMP $flatten\Core.\Control_Unit.$procmux$2997_CMP $flatten\Core.\Control_Unit.$procmux$2996_CMP $flatten\Core.\Control_Unit.$procmux$3074_CMP $flatten\Core.\Control_Unit.$procmux$2871_CMP \Core.Mdu.start $flatten\Core.\Control_Unit.$procmux$3064_CMP }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$ternary$/var/jenkins_home/workspace/Risco-5/Risco-5/src/core/control_unit.v:114$30:
      Old ports: A=2'11, B=2'01, Y=\Core.Control_Unit.second_block_write_src_b [1:0]
      New ports: A=1'1, B=1'0, Y=\Core.Control_Unit.second_block_write_src_b [1]
      New connections: \Core.Control_Unit.second_block_write_src_b [0] = 1'1
    Consolidated identical input bits for $pmux cell $flatten\Core.\Immediate_Generator.$procmux$2680:
      Old ports: A={ \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31:20] }, B={ \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24:20] 20'00000000000000000000 \Core.instruction_register [31:20] 27'000000000000000000000000000 \Core.instruction_register [24:20] }, Y=$flatten\Core.\Immediate_Generator.$2\immediate[31:0]
      New ports: A={ \Core.instruction_register [31] \Core.instruction_register [31:25] }, B={ \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] 1'0 \Core.instruction_register [31:25] 8'00000000 }, Y=$flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12:5]
      New connections: { $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [31:13] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [4:0] } = { $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] \Core.instruction_register [24:20] }
    Consolidated identical input bits for $mux cell $flatten\Core.\Mdu.$procmux$2552:
      Old ports: A={ 1'0 $flatten\Core.\Mdu.$procmux$2555_Y [62:31] 31'0000000000000000000000000000000 }, B={ 2'00 \Core.Mdu.divisor [62:1] }, Y=$flatten\Core.\Mdu.$procmux$2552_Y
      New ports: A={ $flatten\Core.\Mdu.$procmux$2555_Y [62:31] 31'0000000000000000000000000000000 }, B={ 1'0 \Core.Mdu.divisor [62:1] }, Y=$flatten\Core.\Mdu.$procmux$2552_Y [62:0]
      New connections: $flatten\Core.\Mdu.$procmux$2552_Y [63] = 1'0
    New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2798: { $flatten\ResetBootSystem.$procmux$2791_CMP $flatten\ResetBootSystem.$procmux$2790_CMP }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2801:
      Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2801_Y
      New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2801_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2801_Y [0] = 1'0
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$7701: { $flatten\Core.\Control_Unit.$procmux$3003_CMP $flatten\Core.\Control_Unit.$procmux$3001_CMP $flatten\Core.\Control_Unit.$procmux$3000_CMP }
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2386:
      Old ports: A=4'0000, B={ 3'000 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2392_Y 8'00010011 }, Y=$flatten\Controller.\Uart.$procmux$2386_Y
      New ports: A=3'000, B={ 2'00 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2392_Y [2:1] 7'0001011 }, Y=$flatten\Controller.\Uart.$procmux$2386_Y [2:0]
      New connections: $flatten\Controller.\Uart.$procmux$2386_Y [3] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3367:
      Old ports: A=6'100001, B=$flatten\Core.\Control_Unit.$18\nextstate[5:0], Y=$flatten\Core.\Control_Unit.$17\nextstate[5:0]
      New ports: A=2'01, B={ $flatten\Core.\Control_Unit.$18\nextstate[5:0] [0] $flatten\Core.\Control_Unit.$18\nextstate[5:0] [0] }, Y={ $flatten\Core.\Control_Unit.$17\nextstate[5:0] [2] $flatten\Core.\Control_Unit.$17\nextstate[5:0] [0] }
      New connections: { $flatten\Core.\Control_Unit.$17\nextstate[5:0] [5:3] $flatten\Core.\Control_Unit.$17\nextstate[5:0] [1] } = { $flatten\Core.\Control_Unit.$17\nextstate[5:0] [0] 3'000 }
    Consolidated identical input bits for $pmux cell $flatten\Core.\Control_Unit.$procmux$3955:
      Old ports: A=6'000000, B={ 6'000010 $flatten\Core.\Control_Unit.$4\nextstate[5:0] 42'001000001001001010001100001101001110001111 }, Y=$flatten\Core.\Control_Unit.$3\nextstate[5:0]
      New ports: A=5'00000, B={ 5'00010 $flatten\Core.\Control_Unit.$4\nextstate[5:0] [0] $flatten\Core.\Control_Unit.$4\nextstate[5:0] [0] 2'11 $flatten\Core.\Control_Unit.$4\nextstate[5:0] [0] 35'01000010010101001100011010111001111 }, Y={ $flatten\Core.\Control_Unit.$3\nextstate[5:0] [5] $flatten\Core.\Control_Unit.$3\nextstate[5:0] [3:0] }
      New connections: $flatten\Core.\Control_Unit.$3\nextstate[5:0] [4] = 1'0
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2807:
      Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2801_Y, Y=$flatten\ResetBootSystem.$procmux$2807_Y
      New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2801_Y [1], Y=$flatten\ResetBootSystem.$procmux$2807_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2807_Y [0] = 1'0
  Optimizing cells in module \processorci_top.
Performed a total of 44 changes.

21.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~12 debug messages>
Removed a total of 4 cells.

21.30.6. Executing OPT_DFF pass (perform DFF optimizations).

21.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1 unused cells and 5 unused wires.
<suppressed ~2 debug messages>

21.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~1 debug messages>

21.30.9. Rerunning OPT passes. (Maybe there is more to do..)

21.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~83 debug messages>

21.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3839:
      Old ports: A={ $auto$wreduce.cc:461:run$4944 [4] $auto$wreduce.cc:461:run$4944 [4] $auto$wreduce.cc:461:run$4944 [0] 1'0 $auto$wreduce.cc:461:run$4944 [0] }, B={ $auto$wreduce.cc:461:run$4944 [4] 1'0 $auto$wreduce.cc:461:run$4944 [4] 1'1 $auto$wreduce.cc:461:run$4944 [0] }, Y=$auto$wreduce.cc:461:run$4943 [4:0]
      New ports: A={ $auto$wreduce.cc:461:run$4944 [4] $auto$wreduce.cc:461:run$4944 [0] 1'0 }, B={ 1'0 $auto$wreduce.cc:461:run$4944 [4] 1'1 }, Y=$auto$wreduce.cc:461:run$4943 [3:1]
      New connections: { $auto$wreduce.cc:461:run$4943 [4] $auto$wreduce.cc:461:run$4943 [0] } = { $auto$wreduce.cc:461:run$4944 [4] $auto$wreduce.cc:461:run$4944 [0] }
  Optimizing cells in module \processorci_top.
Performed a total of 1 changes.

21.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.30.13. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$4630 ($sdff) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$4674 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$4702 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$4804 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$4804 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$4804 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$4831 ($dffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$4831 ($dffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$4831 ($dffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$4831 ($dffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$4831 ($dffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$4831 ($dffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$4831 ($dffe) from module processorci_top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$4831 ($dffe) from module processorci_top.

21.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

21.30.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~4 debug messages>

21.30.16. Rerunning OPT passes. (Maybe there is more to do..)

21.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~84 debug messages>

21.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1544:
      Old ports: A=8'00000100, B={ 3'000 \Controller.Interpreter.return_state [4:0] }, Y=$flatten\Controller.\Interpreter.$procmux$1544_Y
      New ports: A=5'00100, B=\Controller.Interpreter.return_state [4:0], Y=$flatten\Controller.\Interpreter.$procmux$1544_Y [4:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$1544_Y [7:5] = 3'000
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$1522:
      Old ports: A=8'00000000, B={ 7'0000000 $auto$wreduce.cc:461:run$4909 [0] 6'000000 $auto$wreduce.cc:461:run$4902 [1:0] 1'0 $auto$wreduce.cc:461:run$4907 [6:0] 14'00001101000011 $auto$wreduce.cc:461:run$4906 [1:0] 3'000 \Controller.Interpreter.return_state [4:0] 1'0 $auto$wreduce.cc:461:run$4905 [6] 1'0 $auto$wreduce.cc:461:run$4905 [6] 3'011 $auto$wreduce.cc:461:run$4905 [6] 7'0000011 \Controller.Uart.read_response 4'0000 $auto$wreduce.cc:461:run$4901 [3] 2'00 $auto$wreduce.cc:461:run$4901 [3] 6'000010 $auto$wreduce.cc:461:run$4902 [1:0] 20'00001000000010110000 $auto$wreduce.cc:461:run$4901 [3] $auto$wreduce.cc:461:run$4901 [3] 18'000000010100000100 $flatten\Controller.\Interpreter.$procmux$1544_Y 1'0 $auto$wreduce.cc:461:run$4900 [6] 3'010 $auto$wreduce.cc:461:run$4900 [2] $auto$wreduce.cc:461:run$4900 [6] $auto$wreduce.cc:461:run$4900 [2] 13'0001001100010 $auto$wreduce.cc:461:run$4899 [2:1] $auto$wreduce.cc:461:run$4899 [1] 31'0001011001010010000100000001000 $auto$wreduce.cc:461:run$4898 [0] 8'00000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1522_Y
      New ports: A=7'0000000, B={ 6'000000 $auto$wreduce.cc:461:run$4909 [0] 5'00000 $auto$wreduce.cc:461:run$4902 [1:0] $auto$wreduce.cc:461:run$4907 [6:0] 12'000110100011 $auto$wreduce.cc:461:run$4906 [1:0] 2'00 \Controller.Interpreter.return_state [4:0] $auto$wreduce.cc:461:run$4905 [6] 1'0 $auto$wreduce.cc:461:run$4905 [6] 3'011 $auto$wreduce.cc:461:run$4905 [6] 6'000011 \Controller.Uart.read_response 3'000 $auto$wreduce.cc:461:run$4901 [3] 2'00 $auto$wreduce.cc:461:run$4901 [3] 5'00010 $auto$wreduce.cc:461:run$4902 [1:0] 17'00010000001011000 $auto$wreduce.cc:461:run$4901 [3] $auto$wreduce.cc:461:run$4901 [3] 18'000000101000010000 $flatten\Controller.\Interpreter.$procmux$1544_Y [4:0] $auto$wreduce.cc:461:run$4900 [6] 3'010 $auto$wreduce.cc:461:run$4900 [2] $auto$wreduce.cc:461:run$4900 [6] $auto$wreduce.cc:461:run$4900 [2] 11'00100110010 $auto$wreduce.cc:461:run$4899 [2:1] $auto$wreduce.cc:461:run$4899 [1] 27'001011010100100010000001000 $auto$wreduce.cc:461:run$4898 [0] 7'0000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1522_Y [6:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$1522_Y [7] = 1'0
  Optimizing cells in module \processorci_top.
Performed a total of 2 changes.

21.30.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.30.20. Executing OPT_DFF pass (perform DFF optimizations).

21.30.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.30.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.30.23. Rerunning OPT passes. (Maybe there is more to do..)

21.30.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~84 debug messages>

21.30.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

21.30.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.30.27. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$4859 ($sdff) from module processorci_top.

21.30.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.30.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~1 debug messages>

21.30.30. Rerunning OPT passes. (Maybe there is more to do..)

21.30.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~84 debug messages>

21.30.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

21.30.33. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.30.34. Executing OPT_DFF pass (perform DFF optimizations).

21.30.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.30.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.30.37. Finished OPT passes. (There is nothing left to do.)

21.31. Executing TECHMAP pass (map to technology primitives).

21.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

21.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.

21.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $dffe.
Using template $paramod$824a2ca00d29d886599434cf8ea60471635f2955\_90_demux for cells of type $demux.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $not.
Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_or.
Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_demux for cells of type $demux.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $reduce_bool.
Using template $paramod$8a99b868050f542c83270fc93de09787e35f2c64\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $lut.
Using template $paramod$c04af8dbf0e5d1d69bbccb2c7bd8a93fc9ef54dc\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $or.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ecp5_alu for cells of type $alu.
Using template $paramod$039520c137afc9cd69dd56c3fb11a4e1fbe5f664\_80_ecp5_alu for cells of type $alu.
Using template $paramod$bdc78fe5225b43c64ccdf13e5eb67d9dcf228e8a\_80_ecp5_alu for cells of type $alu.
Using template $paramod$ff467a932a72bec5a93c27dba04bf3daba067451\_80_ecp5_alu for cells of type $alu.
Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu.
Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu.
Using template $paramod$79aa992f2eb7f354d4aaf651790713cf239111fa\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$c9511eeb847f2aa95252b1013477609463f67ee0\_80_ecp5_alu for cells of type $alu.
Using template $paramod$a7b312e4ba8fdc79d4c5e0789e4e6c41ea3896fb\_90_pmux for cells of type $pmux.
Using template $paramod$7a385d5b7a2e603dbc5beef838648775b433f248\_90_pmux for cells of type $pmux.
Using template $paramod$54a4503cc57b9df40b70c1899504d6aac2650719\_90_pmux for cells of type $pmux.
Using template $paramod$59b03ae2620a41577de8da5f5c97b2919e82362b\_90_pmux for cells of type $pmux.
Using template $paramod$24fb226dd75c9d3f6955ec2ad61d794776778cf6\_90_pmux for cells of type $pmux.
Using template $paramod$cc1e387d9d5ac1d3f6e6bed180038d9c0ac48d0c\_90_pmux for cells of type $pmux.
Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux.
Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $sdffce.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using template $paramod$ac45afa5bcd8e16ca475cce13f9d19bb109f1516\_80_ecp5_alu for cells of type $alu.
Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux.
Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $bmux.
Using template $paramod$73d715d333263ca9cf422f13d07e21664e3ab775\_80_ecp5_alu for cells of type $alu.
Using template $paramod$ed6389a5938b09f91843a91d67becca5abedb1bd\_90_pmux for cells of type $pmux.
Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux.
Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux.
Using template $paramod$c96def1cdcef2eee3c62e5dfb7ba2dd09c9f74dd\_90_pmux for cells of type $pmux.
Using template $paramod$cc80a4e89b0341cb117f5d28b0e7244620640141\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$335cfd09f1afa8139c4aafcbbe5f361887b79c5e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$feecc7a0dbd012970970f2858f15e786e251f677\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$5180471e6f22625c8e3c4261cd538e11648586b5\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr.
Using template $paramod$33afdd83bf3811dac2de7a968d39eea5718691bc\_90_pmux for cells of type $pmux.
Using template $paramod$95ab7b964273918a033d1324366ecc612d202989\_90_pmux for cells of type $pmux.
Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux.
Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using template $paramod$a285b5a57fe61eabc57c91b8c412748ee1151a85\_90_pmux for cells of type $pmux.
Using template $paramod$e25898cce02b4d043ab08e065e45db8cf66c901c\_90_pmux for cells of type $pmux.
Using template $paramod$730057d8259da96d4776b15a47b747852ed4c479\_90_pmux for cells of type $pmux.
Using template $paramod$e13ed4cc4d636b3e93547ec233231d1aa3a8ac92\_90_pmux for cells of type $pmux.
Using template $paramod$c6baa65225090ac0a120feab1b920965244aa496\_80_ecp5_alu for cells of type $alu.
Using template $paramod$610911f8769324f781128d641f7fe2120143c328\_80_ecp5_alu for cells of type $alu.
Using template $paramod$2126a3039e9678f6a4bd73d35a1f58ee2616afb2\_80_ecp5_alu for cells of type $alu.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux.
No more expansions possible.
<suppressed ~6513 debug messages>

21.32. Executing OPT pass (performing simple optimizations).

21.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~13115 debug messages>

21.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6315 debug messages>
Removed a total of 2105 cells.

21.32.3. Executing OPT_DFF pass (perform DFF optimizations).

21.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 2041 unused cells and 6905 unused wires.
<suppressed ~2047 debug messages>

21.32.5. Finished fast OPT passes.

21.33. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

21.35. Executing TECHMAP pass (map to technology primitives).

21.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

21.35.2. Continuing TECHMAP pass.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
Using template $paramod\$_DFFE_PN_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PN_.
No more expansions possible.
<suppressed ~1700 debug messages>

21.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~98 debug messages>

21.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).

21.38. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in processorci_top.

21.39. Executing ATTRMVCP pass (move or copy attributes).

21.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 8779 unused wires.
<suppressed ~1 debug messages>

21.41. Executing TECHMAP pass (map to technology primitives).

21.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

21.41.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

21.42. Executing ABC9 pass.

21.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.3. Executing PROC pass (convert processes to netlists).

21.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$46152'.
Cleaned up 1 empty switch.

21.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$46153 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.3.4. Executing PROC_INIT pass (extract init attributes).

21.42.3.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46177'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$46153'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$46151_EN[3:0]$46159
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$46151_DATA[3:0]$46158
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$46151_ADDR[3:0]$46157
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$46152'.

21.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46177'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46135_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46177'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46136_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46177'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46140_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46177'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46141_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46177'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46145_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46177'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46137_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46177'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46146_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46177'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46150_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46177'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46142_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46177'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46138_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46177'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46147_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46177'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46143_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46177'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46148_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46177'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46149_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46177'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46144_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46177'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46139_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46177'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$46151_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$46153'.
  created $dff cell `$procdff$46203' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$46151_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$46153'.
  created $dff cell `$procdff$46204' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$46151_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$46153'.
  created $dff cell `$procdff$46205' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$46152'.
  created direct connection (no actual register cell created).

21.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46177'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$46153'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$46152'.
Cleaned up 1 empty switch.

21.42.3.12. Executing OPT_EXPR pass (perform const folding).

21.42.4. Executing PROC pass (convert processes to netlists).

21.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$46223'.
Cleaned up 1 empty switch.

21.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$46224 in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.4.4. Executing PROC_INIT pass (extract init attributes).

21.42.4.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46248'.
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$46224'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$46222_EN[3:0]$46229
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$46222_DATA[3:0]$46228
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$46222_ADDR[3:0]$46230
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$46223'.

21.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\i' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46248'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46206_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46248'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46208_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46248'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46209_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46248'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46213_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46248'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46214_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46248'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46218_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46248'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46210_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46248'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46219_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46248'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46215_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46248'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46211_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46248'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46220_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46248'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46216_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46248'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46221_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46248'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46217_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46248'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46212_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46248'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46207_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46248'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$46222_DATA' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$46224'.
  created $dff cell `$procdff$46274' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$46222_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$46224'.
  created $dff cell `$procdff$46275' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$46222_ADDR' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$46224'.
  created $dff cell `$procdff$46276' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$46223'.
  created direct connection (no actual register cell created).

21.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46248'.
Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$46224'.
Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$46223'.
Cleaned up 1 empty switch.

21.42.4.12. Executing OPT_EXPR pass (perform const folding).

21.42.5. Executing SCC pass (detecting logic loops).
Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$8207 $auto$simplemap.cc:38:simplemap_not$15522 $auto$simplemap.cc:38:simplemap_not$26570 $auto$ff.cc:266:slice$22081 $auto$ff.cc:479:convert_ce_over_srst$44453 $auto$ff.cc:266:slice$22085 $auto$ff.cc:479:convert_ce_over_srst$44461 $auto$simplemap.cc:126:simplemap_reduce$8368 $auto$simplemap.cc:38:simplemap_not$38909 $auto$ff.cc:266:slice$22086 $auto$ff.cc:479:convert_ce_over_srst$44463 $auto$simplemap.cc:126:simplemap_reduce$8366 $auto$simplemap.cc:38:simplemap_not$26571 $auto$alumacc.cc:485:replace_alu$4977.slice[0].ccu2c_i $auto$ff.cc:266:slice$22082 $auto$ff.cc:479:convert_ce_over_srst$44455 $auto$alumacc.cc:485:replace_alu$4977.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$4977.slice[2].ccu2c_i $auto$ff.cc:266:slice$22083 $auto$ff.cc:479:convert_ce_over_srst$44457 $auto$simplemap.cc:126:simplemap_reduce$8273 $auto$simplemap.cc:126:simplemap_reduce$8271 $auto$simplemap.cc:126:simplemap_reduce$8209 $auto$simplemap.cc:126:simplemap_reduce$8206 $auto$simplemap.cc:126:simplemap_reduce$8372 $auto$simplemap.cc:126:simplemap_reduce$8370 $auto$simplemap.cc:126:simplemap_reduce$8367 $auto$simplemap.cc:38:simplemap_not$26573 $auto$ff.cc:266:slice$22084 $auto$ff.cc:479:convert_ce_over_srst$44459 $auto$simplemap.cc:126:simplemap_reduce$19982 $auto$simplemap.cc:75:simplemap_bitop$15419 $auto$simplemap.cc:38:simplemap_not$7980
Found an SCC: $auto$ff.cc:266:slice$12675 $auto$simplemap.cc:38:simplemap_not$30908 $auto$ff.cc:266:slice$12678 $auto$simplemap.cc:38:simplemap_not$30906 $auto$ff.cc:266:slice$12676 $auto$simplemap.cc:126:simplemap_reduce$14793 $auto$simplemap.cc:126:simplemap_reduce$14824 $auto$simplemap.cc:38:simplemap_not$30907 $auto$ff.cc:266:slice$12677 $auto$opt_expr.cc:617:replace_const_cells$43337 $auto$ff.cc:266:slice$12680 $auto$ff.cc:266:slice$12682 $auto$simplemap.cc:126:simplemap_reduce$14825 $auto$simplemap.cc:126:simplemap_reduce$14794 $auto$simplemap.cc:38:simplemap_not$30909 $auto$ff.cc:266:slice$12679 $auto$simplemap.cc:126:simplemap_reduce$14798 $auto$simplemap.cc:126:simplemap_reduce$14795 $auto$simplemap.cc:126:simplemap_reduce$14829 $auto$simplemap.cc:126:simplemap_reduce$14826 $auto$opt_expr.cc:617:replace_const_cells$43339 $auto$ff.cc:266:slice$12681 $auto$simplemap.cc:196:simplemap_lognot$14835 $auto$simplemap.cc:126:simplemap_reduce$14833 $auto$simplemap.cc:126:simplemap_reduce$14831 $auto$simplemap.cc:126:simplemap_reduce$14828 $auto$simplemap.cc:126:simplemap_reduce$14823 $auto$simplemap.cc:38:simplemap_not$30904 $auto$simplemap.cc:225:simplemap_logbin$14777 $auto$simplemap.cc:196:simplemap_lognot$14804 $auto$simplemap.cc:126:simplemap_reduce$14802 $auto$simplemap.cc:126:simplemap_reduce$14800 $auto$simplemap.cc:126:simplemap_reduce$14797 $auto$simplemap.cc:126:simplemap_reduce$14792 $auto$ff.cc:266:slice$12674 $auto$simplemap.cc:167:logic_reduce$8232 $auto$simplemap.cc:225:simplemap_logbin$14776
Found an SCC: $auto$ff.cc:266:slice$14843 $auto$ff.cc:266:slice$14842 $auto$simplemap.cc:126:simplemap_reduce$14945 $auto$simplemap.cc:126:simplemap_reduce$14960 $auto$opt_expr.cc:617:replace_const_cells$43823 $auto$ff.cc:266:slice$14844 $auto$simplemap.cc:126:simplemap_reduce$30915 $auto$simplemap.cc:75:simplemap_bitop$30930 $auto$simplemap.cc:267:simplemap_mux$14931 $auto$simplemap.cc:225:simplemap_logbin$14934 $auto$simplemap.cc:196:simplemap_lognot$14949 $auto$simplemap.cc:126:simplemap_reduce$14947 $auto$simplemap.cc:126:simplemap_reduce$14944 $auto$opt_expr.cc:617:replace_const_cells$44089 $auto$opt_expr.cc:617:replace_const_cells$43843 $auto$simplemap.cc:267:simplemap_mux$30932 $auto$simplemap.cc:126:simplemap_reduce$30923 $auto$simplemap.cc:126:simplemap_reduce$30920 $auto$simplemap.cc:75:simplemap_bitop$30928 $auto$simplemap.cc:196:simplemap_lognot$14964 $auto$simplemap.cc:126:simplemap_reduce$14962 $auto$simplemap.cc:126:simplemap_reduce$14959 $auto$ff.cc:266:slice$14841 $auto$simplemap.cc:126:simplemap_reduce$8676 $auto$simplemap.cc:126:simplemap_reduce$8674 $auto$simplemap.cc:225:simplemap_logbin$14890 $auto$simplemap.cc:196:simplemap_lognot$14900 $auto$simplemap.cc:126:simplemap_reduce$14898 $auto$opt_expr.cc:617:replace_const_cells$43845 $auto$simplemap.cc:267:simplemap_mux$30933 $auto$simplemap.cc:126:simplemap_reduce$30918
Found an SCC: $auto$ff.cc:266:slice$14850 $auto$opt_expr.cc:617:replace_const_cells$43837 $auto$ff.cc:266:slice$14851 $auto$simplemap.cc:126:simplemap_reduce$14982 $auto$opt_expr.cc:617:replace_const_cells$43839 $auto$ff.cc:266:slice$14852 $auto$ff.cc:266:slice$14846 $auto$ff.cc:266:slice$14847 $auto$simplemap.cc:126:simplemap_reduce$14980 $auto$opt_expr.cc:617:replace_const_cells$43833 $auto$ff.cc:266:slice$14848 $auto$ff.cc:266:slice$14853 $auto$simplemap.cc:126:simplemap_reduce$14985 $auto$simplemap.cc:126:simplemap_reduce$14981 $auto$simplemap.cc:38:simplemap_not$30983 $auto$ff.cc:266:slice$14849 $auto$simplemap.cc:126:simplemap_reduce$14989 $auto$simplemap.cc:126:simplemap_reduce$14987 $auto$simplemap.cc:126:simplemap_reduce$14984 $auto$simplemap.cc:126:simplemap_reduce$14979 $auto$simplemap.cc:38:simplemap_not$30979 $auto$ff.cc:266:slice$14845 $auto$simplemap.cc:126:simplemap_reduce$8765 $auto$simplemap.cc:196:simplemap_lognot$14991
Found 4 SCCs in module processorci_top.
Found 4 SCCs.

21.42.6. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.7. Executing PROC pass (convert processes to netlists).

21.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

21.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

21.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

21.42.7.4. Executing PROC_INIT pass (extract init attributes).

21.42.7.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.7.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

21.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

21.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs).

21.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

21.42.7.12. Executing OPT_EXPR pass (perform const folding).

21.42.8. Executing TECHMAP pass (map to technology primitives).

21.42.8.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

21.42.8.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~164 debug messages>

21.42.9. Executing OPT pass (performing simple optimizations).

21.42.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.

21.42.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

21.42.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.42.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Performed a total of 0 changes.

21.42.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

21.42.9.6. Executing OPT_DFF pass (perform DFF optimizations).

21.42.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..

21.42.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.

21.42.9.9. Finished OPT passes. (There is nothing left to do.)

21.42.10. Executing TECHMAP pass (map to technology primitives).

21.42.10.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

21.42.10.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~1080 debug messages>

21.42.11. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

21.42.12. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

21.42.13. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.14. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

21.42.15. Executing TECHMAP pass (map to technology primitives).

21.42.15.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

21.42.15.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~203 debug messages>

21.42.16. Executing OPT pass (performing simple optimizations).

21.42.16.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~18 debug messages>

21.42.16.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

21.42.16.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.42.16.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

21.42.16.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.42.16.6. Executing OPT_DFF pass (perform DFF optimizations).

21.42.16.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>

21.42.16.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.42.16.9. Rerunning OPT passes. (Maybe there is more to do..)

21.42.16.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.42.16.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

21.42.16.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

21.42.16.13. Executing OPT_DFF pass (perform DFF optimizations).

21.42.16.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

21.42.16.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

21.42.16.16. Finished OPT passes. (There is nothing left to do.)

21.42.17. Executing AIGMAP pass (map logic to AIG).
Module processorci_top: replaced 18 cells with 120 new cells, skipped 39 cells.
  replaced 3 cell types:
       2 $_OR_
       2 $_XOR_
      14 $_MUX_
  not replaced 3 cell types:
      31 $specify2
       4 $_NOT_
       4 $_AND_

21.42.18. Executing AIGMAP pass (map logic to AIG).
Module processorci_top: replaced 8662 cells with 52995 new cells, skipped 6586 cells.
  replaced 4 cell types:
    2545 $_OR_
     211 $_XOR_
       1 $_ORNOT_
    5905 $_MUX_
  not replaced 11 cell types:
      24 $scopeinfo
     555 $_NOT_
    1857 $_AND_
      24 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp
    1574 TRELLIS_FF
       4 MULT18X18D
     419 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
    1052 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
       1 $__ABC9_SCC_BREAKER
      24 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4
    1052 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4

21.42.18.1. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.18.2. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.18.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 22751 AND gates and 68194 wires from module `processorci_top' to a netlist network with 6017 inputs and 1784 outputs.

21.42.18.4. Executing ABC9_EXE pass (technology mapping using ABC9).

21.42.18.5. Executing ABC9.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   6017/   1784  and =   21098  lev =   44 (3.08)  mem = 0.64 MB  box = 1495  bb = 1076
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   6017/   1784  and =   28433  lev =   55 (2.14)  mem = 0.72 MB  ch = 2685  box = 1479  bb = 1076
ABC: + &if -W 300 -v 
ABC: K = 7. Memory (bytes): Truth =    0. Cut =   64. Obj =  148. Set =  672. CutMin = no
ABC: Node =   28433.  Ch =  2011.  Total mem =    8.44 MB. Peak cut mem =    0.27 MB.
ABC: P:  Del = 6075.00.  Ar =   39171.0.  Edge =    40190.  Cut =   349478.  T =     0.16 sec
ABC: P:  Del = 5820.00.  Ar =   38997.0.  Edge =    40144.  Cut =   346370.  T =     0.17 sec
ABC: P:  Del = 5820.00.  Ar =   11722.0.  Edge =    26155.  Cut =   841628.  T =     0.37 sec
ABC: F:  Del = 5820.00.  Ar =    9078.0.  Edge =    24359.  Cut =   643578.  T =     0.30 sec
ABC: A:  Del = 5819.00.  Ar =    8050.0.  Edge =    22454.  Cut =   563366.  T =     0.39 sec
ABC: A:  Del = 5819.00.  Ar =    7956.0.  Edge =    22362.  Cut =   596688.  T =     0.41 sec
ABC: Total time =     1.80 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: + &ps -l 
ABC: <abc-temp-dir>/input : i/o =   6017/   1784  and =   19752  lev =   32 (2.13)  mem = 0.62 MB  box = 1479  bb = 1076
ABC: Mapping (K=7)  :  lut =   5733  edge =   22152  lev =   12 (1.10)  Boxes are not in a topological order. Switching to level computation without boxes.
ABC: levB =   32  mem = 0.30 MB
ABC: LUT = 5733 : 2=620 10.8 %  3=972 17.0 %  4=3064 53.4 %  5=843 14.7 %  6=113 2.0 %  7=121 2.1 %  Ave = 3.86
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + time 
ABC: elapse: 19.98 seconds, total: 19.98 seconds

21.42.18.6. Executing AIGER frontend.
<suppressed ~15630 debug messages>
Removed 26680 unused cells and 57403 unused wires.

21.42.18.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:     5746
ABC RESULTS:   $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp cells:       24
ABC RESULTS:   $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells:      403
ABC RESULTS:   $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells:     1052
ABC RESULTS:           input signals:     1166
ABC RESULTS:          output signals:      300
Removing temp directory.

21.42.19. Executing TECHMAP pass (map to technology primitives).

21.42.19.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

21.42.19.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000000110 for cells of type $__ABC9_SCC_BREAKER.
No more expansions possible.
<suppressed ~2577 debug messages>
Removed 460 unused cells and 85289 unused wires.

21.43. Executing TECHMAP pass (map to technology primitives).

21.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

21.43.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod$baa939b0bd5b3e0c8760492528669bd58f640542\$lut for cells of type $lut.
Using template $paramod$44a31e5be59cd3ca0870eb8d89e5e32d8a2f2a5c\$lut for cells of type $lut.
Using template $paramod$a5dd9ee10fc2202a29791f7d68d4afcce241aee5\$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod$b009a26b33c3ca109c016cf968a774c0d66687bb\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod$f21b0041c50a00ee5548690150273548cd6916b5\$lut for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod$ee6944635a66b35a2c008244d1b98fdaec97fc5f\$lut for cells of type $lut.
Using template $paramod$acb8c6253d65f5d7c38afa66fc3850a657bea507\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut.
Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut.
Using template $paramod$903905cca899aab473483ca27c3db12d7108e3a5\$lut for cells of type $lut.
Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut.
Using template $paramod$00ffcc628ccb870304683cac36ad3a16cc41b6a4\$lut for cells of type $lut.
Using template $paramod$eaea85d27cc0950ed001348e061727a194f5cf9c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut.
Using template $paramod$3a0a392069bc969f34c65c546a8c56fbbb67e282\$lut for cells of type $lut.
Using template $paramod$9cc51547ab44a72dd506ee5bb84a864365a103da\$lut for cells of type $lut.
Using template $paramod$099af7f70fcc70b41da4ec1f8df6dd0abf473cb5\$lut for cells of type $lut.
Using template $paramod$6e46ec5a196ba1a24b8e69ab094cadc07c13ac1f\$lut for cells of type $lut.
Using template $paramod$c08a774c89ef1ea6ee2ef4d8c3b071eb141d4259\$lut for cells of type $lut.
Using template $paramod$7e8d331d1e06632d29fbdf6c3afc2de1856d3c67\$lut for cells of type $lut.
Using template $paramod$2d70e360329f2b83357618532825d0cf30a325f3\$lut for cells of type $lut.
Using template $paramod$653ed1fca2cbea6092fc92115114dddd9158d22d\$lut for cells of type $lut.
Using template $paramod$4270f290aff868c3cb2f9812632093bc3a3d9650\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod$176a6ceafa512d807921d7dfc76320dfbbfb5fe4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011101 for cells of type $lut.
Using template $paramod$c9d86860d7b8a94fe4e147db4941c14e73dd3281\$lut for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
Using template $paramod$0331e023d83b8009e60defb446ce9fa640b122c7\$lut for cells of type $lut.
Using template $paramod$b89c522b7f70adaee1a35d80e932f38159b6a445\$lut for cells of type $lut.
Using template $paramod$d25a0f1ed4a99ef8d1bf6a91b3015ece3e01714b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut.
Using template $paramod$6023c671e114c4eb0467aa8a0b08e183f33ec2fd\$lut for cells of type $lut.
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut.
Using template $paramod$a47d3f6fd9a7aebdb1b556bc977da3380a17c8cf\$lut for cells of type $lut.
Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut.
Using template $paramod$2de23df76a24087ecc0fa38a78ecc970cd3f2492\$lut for cells of type $lut.
Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut.
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut.
Using template $paramod$90edf8d4fe439b92725b09f66e94b5afc9f35376\$lut for cells of type $lut.
Using template $paramod$3c5eb16fa418cfbbe1710d24d17e7d0b5448c3c1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod$8c24dc0cdd336b7fb88bbf7eed45cec5cbae862b\$lut for cells of type $lut.
Using template $paramod$983adbc56c7400f95b406f02e82bd0da8b98fd00\$lut for cells of type $lut.
Using template $paramod$a8b9523b256193b8ef4d76806da37359144a62fd\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod$fe9a0158d0352193457c4f5b6282ac86d35fb3ee\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod$df5c8730c0a53792c3f54c2192a2221c27162fb5\$lut for cells of type $lut.
Using template $paramod$505ef859daf333cd3708b17e0847e5ec5b9043b5\$lut for cells of type $lut.
Using template $paramod$c97bcad21440836b1df0dc8f4860bb61034e5b37\$lut for cells of type $lut.
Using template $paramod$ccd3e15dc00d71b9284dff48e88ccef5be7362c8\$lut for cells of type $lut.
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut.
Using template $paramod$fb7bbfbe62f17d1abd6f8eaee546f5a966c46c29\$lut for cells of type $lut.
Using template $paramod$90dc599eed99da511e64ad217d69e7ff2c1e56cc\$lut for cells of type $lut.
Using template $paramod$2844c7fef2a755a9af80c70990cd830291c4b71c\$lut for cells of type $lut.
Using template $paramod$71112c23185f325d93f810329cb9d4a033178614\$lut for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut.
Using template $paramod$181733d3e31dcdcea8c52d0a4fc252b3aa453564\$lut for cells of type $lut.
Using template $paramod$d546db88fc169832512e499a9cdf9a41b89ab74e\$lut for cells of type $lut.
Using template $paramod$6c51c1ba6c39f0c09b896d52432b366f116bd3c1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod$234fd643079033ba0cbc98ff572df9b7b7a0dc86\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod$e0286d7bdebdb6346cb367bb1962e01892ba2e32\$lut for cells of type $lut.
Using template $paramod$609ff53b8e25fddda2f58be8d19c2d47b81baf45\$lut for cells of type $lut.
Using template $paramod$9c65fdfac74256c2eb67dd209b598e25d1f0a099\$lut for cells of type $lut.
Using template $paramod$fbda9ba53f7f57dd3cad1873a35a93bdf5d3a284\$lut for cells of type $lut.
Using template $paramod$4a9f20a18e16e687c50b1afb238d77d575a68f2d\$lut for cells of type $lut.
Using template $paramod$0d5e420ccfc2dddc13533c0817d1e17e68a2c136\$lut for cells of type $lut.
Using template $paramod$f0bef4a30c0ab8325e910c7b53ed5044c4e7d707\$lut for cells of type $lut.
Using template $paramod$d21d214a5aa271f2d9da3f90f22432c0ecee130f\$lut for cells of type $lut.
Using template $paramod$2883108cb47604e8d9f302b6fd523eca1a3ace81\$lut for cells of type $lut.
Using template $paramod$272a01c2714b204037ae625f971913a9414bd247\$lut for cells of type $lut.
Using template $paramod$8e1c82b304528085a78e4651c993ce9e1ef6b8a8\$lut for cells of type $lut.
Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut.
Using template $paramod$bce98cbc4c7663d9534fcdf870483176065e0cfd\$lut for cells of type $lut.
Using template $paramod$03d0edf20ed1469b09ef5ea8e93986bf65c1867c\$lut for cells of type $lut.
Using template $paramod$8c2f43e08c9cc2b49de93af951f385231789cba4\$lut for cells of type $lut.
Using template $paramod$323fbd8da0ac5986920f0496885d4acac13656a5\$lut for cells of type $lut.
Using template $paramod$384dd8fd176e9fb45aae56ef8f5af5a6b7507981\$lut for cells of type $lut.
Using template $paramod$8dc7036079d7be3e5b8905f947c0888c82aab734\$lut for cells of type $lut.
Using template $paramod$9dfcbe0e59b5276d61964ec6e59028bf2874daef\$lut for cells of type $lut.
Using template $paramod$80fd3f90b6a7b38da9d25588666decbe3adaf5ec\$lut for cells of type $lut.
Using template $paramod$6720635ab9307249b8ea0caf486aad8c353f2185\$lut for cells of type $lut.
Using template $paramod$83c1b6108170249166239e09804c5f4542556524\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001001 for cells of type $lut.
Using template $paramod$22fea57d7a456c098d9c97c3010141b9cce8b96f\$lut for cells of type $lut.
Using template $paramod$857512ea84a5fe5464efcd374b77666399ea78e1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$692c4ee85d95f8cc4959911841a85a43ebfd3f05\$lut for cells of type $lut.
Using template $paramod$6bf74d43098222579e639c5a64a5885252736467\$lut for cells of type $lut.
Using template $paramod$e800d193f17c895194d1649dde3e5037bf808d28\$lut for cells of type $lut.
Using template $paramod$cbd5aa65e685d8732fc12cc35263aabc5e682291\$lut for cells of type $lut.
Using template $paramod$6f26f546ad655ddf775808ebf2114763796f1896\$lut for cells of type $lut.
Using template $paramod$f5651ff2abca4d07e0dfb50ad5504abd96162cd4\$lut for cells of type $lut.
Using template $paramod$ee3ba3939f6ccdb74bf420a252d58cdb86511937\$lut for cells of type $lut.
Using template $paramod$5e28eb89fe8218b3148e3be09ae377b977d434a9\$lut for cells of type $lut.
Using template $paramod$88e557ff47f35512152dcd123e39a7dd2f3f82eb\$lut for cells of type $lut.
Using template $paramod$62ed4c3299b68c9865de35b2752762287f7bd37f\$lut for cells of type $lut.
Using template $paramod$d35161d1d7976dcc02e7c7d51172431be85143b4\$lut for cells of type $lut.
Using template $paramod$4d1486333717939e1eb6abd7280e827701773a1c\$lut for cells of type $lut.
Using template $paramod$60096d1cdb5f7f55fdf4ed3aab322b5c7375f61e\$lut for cells of type $lut.
Using template $paramod$0817ba1bb76015d86d1f03b22a80e18f505980d8\$lut for cells of type $lut.
Using template $paramod$8b170bed38bb84808b387a3554c5328e63aec095\$lut for cells of type $lut.
Using template $paramod$7052bb73849c84c4a3e13a9f5c8c1cfa327a857f\$lut for cells of type $lut.
Using template $paramod$108952590fe845e8e70a99827bbbccefd1a29568\$lut for cells of type $lut.
Using template $paramod$d73dfa3b88157603e114816c5374568d1760ceff\$lut for cells of type $lut.
Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5\$lut for cells of type $lut.
Using template $paramod$70e8623adea353a5ac0c4954be0d5b530a61494d\$lut for cells of type $lut.
Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut.
Using template $paramod$efd9db50f639c84b61057002b4119366b96c7abc\$lut for cells of type $lut.
Using template $paramod$77018f7168438de1e5cf566c71f19ae640d9d489\$lut for cells of type $lut.
Using template $paramod$8e3958c0721c76bb2ff944f8512e31568d71d6f3\$lut for cells of type $lut.
Using template $paramod$35d5cf238847996ccb5da25c65ad59a32e7c31aa\$lut for cells of type $lut.
Using template $paramod$352d59b2fa9424e5868b0bc90771ae14ae6ee8fc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut.
Using template $paramod$4237ec31543859d6444b0df9382030ab13f55b7e\$lut for cells of type $lut.
Using template $paramod$991f5fcb82fd10139056a359ffc4a67f44aea8ab\$lut for cells of type $lut.
Using template $paramod$86b3760cb96b770d612108cec5e7aac5497f3312\$lut for cells of type $lut.
Using template $paramod$388a5db45f2bfb8d18c6ba547cf0776f901eca7b\$lut for cells of type $lut.
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut.
Using template $paramod$9c20b6131270022a6b7ba9f36f0d66632266b00e\$lut for cells of type $lut.
Using template $paramod$c9ee8c3cdffc10341c8cca5ef6f2d62a471dd9ea\$lut for cells of type $lut.
Using template $paramod$70c7a29c0eecf1b0e2c5fe73ab7bdb3355f0e4f1\$lut for cells of type $lut.
Using template $paramod$dd8f09456cc0557d76e7a209e6cf5c8b8adde891\$lut for cells of type $lut.
Using template $paramod$2754a21a217ccdc1a0cbf27b2e8b19266cadc23f\$lut for cells of type $lut.
Using template $paramod$a2f8c0f49f5179aa0ab5b87e4b39f0b9aaf82f5a\$lut for cells of type $lut.
Using template $paramod$3fb98f54272d42cd2175fc350cb401c40d8fcb34\$lut for cells of type $lut.
Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5\$lut for cells of type $lut.
Using template $paramod$d1112868f3c2119f6b3f85367550d338d78a7334\$lut for cells of type $lut.
Using template $paramod$fd3c6f7cd86ebd08275158b099051f4b085cb906\$lut for cells of type $lut.
Using template $paramod$fccf32f2ce0297290591a5838f1fa2029876bdfc\$lut for cells of type $lut.
Using template $paramod$98dbdcd471ba0a28148297d600246e9d7dd9fa99\$lut for cells of type $lut.
Using template $paramod$4860dafdc834533400ce38279a6df237a334bfd9\$lut for cells of type $lut.
Using template $paramod$527716fb767139921cc3a2a87fc898ef5b04a907\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001001 for cells of type $lut.
Using template $paramod$796a976cd67711f2c509e1e9b3c47121c5427850\$lut for cells of type $lut.
Using template $paramod$a6cc35b73c1ffab209ee185e5047a4b26bf058d0\$lut for cells of type $lut.
Using template $paramod$09194da5f2c8e08bed8f609fd0e254d8629b24b3\$lut for cells of type $lut.
Using template $paramod$6e2b27a23561eba4d5d7a3612a01502854865858\$lut for cells of type $lut.
Using template $paramod$94e65f323749ab2f501acf5577af42456678fff9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut.
Using template $paramod$71393fb6c0bb927fba58a72a3f3c685a89eab477\$lut for cells of type $lut.
Using template $paramod$0fa1c6e5d65a4e509c15b676a94b9aed076b9f4d\$lut for cells of type $lut.
Using template $paramod$11f7a95762c5b4b70c087a0502121611638269c5\$lut for cells of type $lut.
Using template $paramod$7c5aa14800256439a9ba56caf12b6113f646b927\$lut for cells of type $lut.
Using template $paramod$85b779ce5ab505dbf25e5e046fb43ca2b76b878b\$lut for cells of type $lut.
Using template $paramod$b2a4860cd839ff40d9dca4c3f237b2b534267028\$lut for cells of type $lut.
Using template $paramod$66cba472e67a95d5f17de4e8967f34a9604e2c70\$lut for cells of type $lut.
Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut.
Using template $paramod$543b3bffa2bbcf34a8bf67a89ac93d5f88af7d7c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut.
Using template $paramod$7ffc04c088a4897014506d1e561a14b627924059\$lut for cells of type $lut.
Using template $paramod$7ac0d693e8b843c95e28e03fd4fd6964982c85ff\$lut for cells of type $lut.
Using template $paramod$f587be5dee6fb7e49a5d3ac9ec8f717822a31ea2\$lut for cells of type $lut.
Using template $paramod$a00adb5b37543b8dd0bae8bbe9f8146f98c8e8ec\$lut for cells of type $lut.
Using template $paramod$d3813b08e7bb29971c19859221b321b5494c6d5b\$lut for cells of type $lut.
Using template $paramod$41cf3e7f9a592734c11550fc575af1ecb816015d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut.
Using template $paramod$5502a85110dbca29ac631107f0b0635e7fade476\$lut for cells of type $lut.
Using template $paramod$e9fd60b305977ab6bf6eeca2f23beccee64ed3ee\$lut for cells of type $lut.
Using template $paramod$9d493a05bc89f65d5f5c1244f501c865445117f4\$lut for cells of type $lut.
Using template $paramod$187fffcabef93c35fdb224785631abfe158fc78e\$lut for cells of type $lut.
Using template $paramod$6d4cc4f82cbeec9f11ee20382d2e8cbca780ab4d\$lut for cells of type $lut.
Using template $paramod$c7eaad6a588218ef0ba5a17502d003bdff2bbd3e\$lut for cells of type $lut.
Using template $paramod$82687d3ad8130b5b49618b6a28f43c60b5130fe1\$lut for cells of type $lut.
Using template $paramod$44a6586fa21c1d277ba2728177750c6c473bb6e3\$lut for cells of type $lut.
Using template $paramod$bd3e77c5ae0c34ff2c9f3dae31b7c406cf14c40c\$lut for cells of type $lut.
Using template $paramod$6ae4b1e60c63ce9d50fe39399e50e2c0b298fef6\$lut for cells of type $lut.
Using template $paramod$b40080b643baa8bb528ec249e10d82b2d80dfed9\$lut for cells of type $lut.
Using template $paramod$3be30a5a9f993377f0c44a54aadf0fabaaafa2c9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut.
Using template $paramod$712505941a295086314c22735153725461a87f4a\$lut for cells of type $lut.
Using template $paramod$32f591d25bbccfbf6e8ff90ad0d6ecaf2ac6c218\$lut for cells of type $lut.
Using template $paramod$b4286900da1bbbce775d940132d12ee69163aa6e\$lut for cells of type $lut.
Using template $paramod$f3d649e8076d16e16e181b135cf4011cee04a458\$lut for cells of type $lut.
Using template $paramod$d2db04844030b686483eba8337be3f4070e22b77\$lut for cells of type $lut.
Using template $paramod$9c32fd119457e69e03a24d4d2698f238bf59d9d3\$lut for cells of type $lut.
Using template $paramod$9e0d5e3cbbbadb2b139aaae0b912cff38011856c\$lut for cells of type $lut.
Using template $paramod$da216d5db97812160cff47a7b1c65cd43181b2a8\$lut for cells of type $lut.
Using template $paramod$f99dc751189e8a1f9e12b58fac9a0e3f4559433d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut.
Using template $paramod$46d981b5eabc08c1691f743d7a017e4435316de4\$lut for cells of type $lut.
Using template $paramod$06e62c2045624c211a1abe4f2f36c8f22c688165\$lut for cells of type $lut.
Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut.
Using template $paramod$59601b4481617ef8784cc027d3c1241388c1c653\$lut for cells of type $lut.
Using template $paramod$d9740684ce6b7c5f0f4e8873d31f93e6ecc8cc80\$lut for cells of type $lut.
Using template $paramod$05c00c4a5c00725c4626deded1c7796a8bb02339\$lut for cells of type $lut.
Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut.
Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut.
Using template $paramod$0c31f8674d6b730afec588864e795ceca95d08fe\$lut for cells of type $lut.
Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75\$lut for cells of type $lut.
Using template $paramod$409279b79277055c92c645b01c2deb7a6d1a6a87\$lut for cells of type $lut.
Using template $paramod$4b23d751b3e1d7cde9cd1766bf20ceee12e38a3d\$lut for cells of type $lut.
Using template $paramod$62fc4ac57a0b73f1d95465f30f5df060addcd3ec\$lut for cells of type $lut.
Using template $paramod$84c5cfa8d7481774250caab0fcdd6d249a376a31\$lut for cells of type $lut.
Using template $paramod$b5ef04ad6f1419b140ac377ad9670f629913112e\$lut for cells of type $lut.
Using template $paramod$250e75f8c060e5dd4ba33397d5cbca1140bc869d\$lut for cells of type $lut.
Using template $paramod$b419810ab1d51da1962917a1949cecc5f27935eb\$lut for cells of type $lut.
Using template $paramod$9e776ec1b34d86f88d5c27558aea8207655d0a2b\$lut for cells of type $lut.
Using template $paramod$e6504163a6aac7eb100aad063fcf1dad8ffd4e1b\$lut for cells of type $lut.
Using template $paramod$19f568890ed784cb1efc3ce1b67eed20a6c54d9a\$lut for cells of type $lut.
Using template $paramod$814cde760aca38e0fefbe04cd31639b7754422f6\$lut for cells of type $lut.
Using template $paramod$9dfe2a25d99d8640a9f67a2438aaca85b684d257\$lut for cells of type $lut.
Using template $paramod$b6c45f8ba9d325a7b4ae042c8c22a8ae2a2f8a9b\$lut for cells of type $lut.
Using template $paramod$68ac0d64281403acc6a836bba5ccf2fc632d577a\$lut for cells of type $lut.
Using template $paramod$1b3394c4afda59b0cfa00f6debcd7cb2b39222dd\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod$3f943b31daf852ed1ca222e5bb6488e4bbd6a0e6\$lut for cells of type $lut.
Using template $paramod$32abbd1d449a67fb913b4733374e345d4c17175b\$lut for cells of type $lut.
Using template $paramod$4d4e8d3882a975246e1df0df643b6f2eb6d0336b\$lut for cells of type $lut.
Using template $paramod$2ec6422db00d358fc7469efce6208bffbc8521cd\$lut for cells of type $lut.
Using template $paramod$fdd4eded4016843be3b5f3b9144b104f298c2fc8\$lut for cells of type $lut.
Using template $paramod$1754f787ee39c132fd3133b2c8f1c9f0b87503a5\$lut for cells of type $lut.
Using template $paramod$f13784ede300b12a5285177c86c7721a54cf9e12\$lut for cells of type $lut.
Using template $paramod$5289dac6f25369a9a495c69c724c25ee83ad0e78\$lut for cells of type $lut.
Using template $paramod$3a30c503b366b8eb75a9939bd4232db3043a89f7\$lut for cells of type $lut.
Using template $paramod$c441dbd41fa7b52ce609b1fb3e8a706905598601\$lut for cells of type $lut.
Using template $paramod$cd616fa2bc6a825915cf712f7038cb57c9f8bac6\$lut for cells of type $lut.
Using template $paramod$8db9c2083114045f5acf6b27ead1ad1656813d6d\$lut for cells of type $lut.
Using template $paramod$f5f41ee5d60dede31a2b59f58ec46b167939d713\$lut for cells of type $lut.
Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f\$lut for cells of type $lut.
Using template $paramod$1f2df48b80e26a8e979abfdfd10b025373054649\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut.
Using template $paramod$12b93181fde40368887ce43b59fecaa09cb41fa7\$lut for cells of type $lut.
Using template $paramod$63c21a63caf7b85f1f888b02cf745b7d3944fb57\$lut for cells of type $lut.
Using template $paramod$3bb7b015790d2af03baf785d275cbd099cfe2c26\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001000 for cells of type $lut.
Using template $paramod$eabde4761c91679426ef5401ae1b2c95bf56e107\$lut for cells of type $lut.
Using template $paramod$7dad2285b6a41fd718a0863efc009b14ae7d121a\$lut for cells of type $lut.
Using template $paramod$28c616faf5f033f157ae11b466e19ab28d454f1e\$lut for cells of type $lut.
Using template $paramod$03d7da0d848b4f563fda6bc83a08135cc5ded340\$lut for cells of type $lut.
Using template $paramod$643ede1c292697fa3dbd09b401c673392cdf501e\$lut for cells of type $lut.
Using template $paramod$c0262e34631074b16c3f9acdc8998d6fc579f3a5\$lut for cells of type $lut.
Using template $paramod$ee8844629b8aee08469dc19b342bc2fa993f58a2\$lut for cells of type $lut.
Using template $paramod$31f0a66a4b242b524303bfb4ac95c05ad74158f8\$lut for cells of type $lut.
Using template $paramod$0c84c7d3848539be64b03a347705161b117bb0e7\$lut for cells of type $lut.
Using template $paramod$23ba03b3f106a8b0f20f18bfebd862b419996ddc\$lut for cells of type $lut.
Using template $paramod$4fc6efaec5bd8994232500ce8f8be9cb357522d5\$lut for cells of type $lut.
Using template $paramod$a6b2d4693fada6bebbe4480262641915d709d280\$lut for cells of type $lut.
Using template $paramod$1269bebbd9525c8f3550f48dd2e8320327f526b6\$lut for cells of type $lut.
Using template $paramod$d7ddd539c933104b4957261218ceb3ac1767bea5\$lut for cells of type $lut.
Using template $paramod$e6dfe5b1a1a5899545d0bf3f012990e128646c56\$lut for cells of type $lut.
Using template $paramod$9a844ff4fab313de5f6983da14e109424759ae5e\$lut for cells of type $lut.
Using template $paramod$9ae0f136c9ed34a2deb323e9b2a3a520eea61514\$lut for cells of type $lut.
Using template $paramod$6e64c13666511ae2ccc90ab6ddaf8be09bda5af2\$lut for cells of type $lut.
Using template $paramod$ebabab001c7635aaf665f1a0ecde2d42b3fb1e77\$lut for cells of type $lut.
Using template $paramod$5d39ffe7b7dd5841b0acdab60eccac9170dd317c\$lut for cells of type $lut.
Using template $paramod$09deb89cf77b6e37f6ed7fef8d797dc05c0b2eee\$lut for cells of type $lut.
Using template $paramod$02ec6771e6c104e763cf616cd331ad60c33e6d17\$lut for cells of type $lut.
Using template $paramod$2acc0c86fd7c89b049ee07b77315308f0b5543b4\$lut for cells of type $lut.
Using template $paramod$2a50fb8590ed0882f7469fc696f724f9bef90f55\$lut for cells of type $lut.
Using template $paramod$6145334fdf7d2d0acb076959a754832f46c06fe2\$lut for cells of type $lut.
Using template $paramod$3666188b96545248717c2ff7edce939f185fe6fd\$lut for cells of type $lut.
Using template $paramod$53564a2624f743596c6b6998e19fdd2ad9db459f\$lut for cells of type $lut.
Using template $paramod$afcb46a6d56ba82360e221df66fab2dbf63e96df\$lut for cells of type $lut.
Using template $paramod$1014d0fd5dfc0ee0d6761b10eb6b5fa1a028f373\$lut for cells of type $lut.
Using template $paramod$e5f53fb2cb3e702c9422ebddd3ba952e5a8f3401\$lut for cells of type $lut.
Using template $paramod$3a437ab042afe1dc11edf527b61ffeb19af46ae8\$lut for cells of type $lut.
Using template $paramod$e11fec9e222e25bc0d9d1def5e8b6effff98c489\$lut for cells of type $lut.
Using template $paramod$fd3ed3a223484aac184d1b7412ec4cfe4ca64c32\$lut for cells of type $lut.
Using template $paramod$1bb26330f94b9f62b6acb8cc6af86c50c7c3906f\$lut for cells of type $lut.
Using template $paramod$98c377328f303d3ed9039ca0db26b18f36e929b2\$lut for cells of type $lut.
Using template $paramod$a1522875362ebcc26f7effea4d2e5fdd80b2cc18\$lut for cells of type $lut.
Using template $paramod$ea79e410ad0f4fc3326666c891e1f3992816d636\$lut for cells of type $lut.
Using template $paramod$3ae9f1cda205b669870c653a21d45eee50078e98\$lut for cells of type $lut.
Using template $paramod$2fb7beda6555b34ccc4ac35589a1d71f2a1a9732\$lut for cells of type $lut.
Using template $paramod$6e424bd4a747f8421ac946af3d9bb3a47fd0b233\$lut for cells of type $lut.
Using template $paramod$92c3899764cd8074859d6a5a5b733cffe8a391b3\$lut for cells of type $lut.
Using template $paramod$79a5f4f6c85f6353a05008626bbb50a513afc30e\$lut for cells of type $lut.
Using template $paramod$08074372b958f9013985b1c2301ae914ff53b41e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod$b8bc93a50860defb026422e051b1b5c80f73638b\$lut for cells of type $lut.
Using template $paramod$058a3c6c4a5973a6fa96322456e9fa0d3a1a38f6\$lut for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut.
Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut.
Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7\$lut for cells of type $lut.
Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a\$lut for cells of type $lut.
Using template $paramod$8829675bb8c52553aed9f101ec0d5ef0c865e5c7\$lut for cells of type $lut.
Using template $paramod$4cf5305612d86489c1a6171729557670bf08582e\$lut for cells of type $lut.
Using template $paramod$e3e4230bb990723642112b292aa705ee0cbad0d4\$lut for cells of type $lut.
Using template $paramod$4834046533425f54583d6bd31e49deb63455e1a5\$lut for cells of type $lut.
Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut.
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut.
Using template $paramod$7e9df0afb32b76fe5fce0691b8752aca650057fa\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut.
Using template $paramod$b4ea8084232bb9dc08605562c95dabca15da1928\$lut for cells of type $lut.
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut.
Using template $paramod$2fa16d4c3d345074954635de91dde258ad9795ea\$lut for cells of type $lut.
Using template $paramod$2382b0dd4cb27fd4312681c40a6dd179c2a7a26a\$lut for cells of type $lut.
Using template $paramod$78b4324556f6321a85bd440441a5392f271ea218\$lut for cells of type $lut.
Using template $paramod$17f1b90a5c6d7e6613368c5e7d3f44dd634e59e2\$lut for cells of type $lut.
Using template $paramod$12fb017f90e7463fe74789d2ec23494cce2be24a\$lut for cells of type $lut.
Using template $paramod$efe8e6522858192ad208465f2cc042527dc2999a\$lut for cells of type $lut.
Using template $paramod$d750041ede21fd9873becb06293199fd1fbc9a7e\$lut for cells of type $lut.
Using template $paramod$80bc945f6d438f16387422ec284dc12b4bb4e68f\$lut for cells of type $lut.
Using template $paramod$4bf8ce4ba3837f34813021ea7ba48081e9887a3e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000100 for cells of type $lut.
Using template $paramod$4888f2121a1fba4d507203534ae54782bc81e02e\$lut for cells of type $lut.
Using template $paramod$0acc8d601702e9b60288baa3d5cf1d38d4f22457\$lut for cells of type $lut.
Using template $paramod$c50bf79556f7c35c37bbd3d892f752a0609f21ca\$lut for cells of type $lut.
Using template $paramod$ea2ed7b6000d8bc7d418a28d22dd562f94afdeff\$lut for cells of type $lut.
Using template $paramod$086937f2e69afb7c662e45e33f5a7616aa818da8\$lut for cells of type $lut.
Using template $paramod$7e3d8ac009723e554811ad53385162c0e6a41625\$lut for cells of type $lut.
Using template $paramod$2b6db8ab7ce32f609e32ceb713024ea3d104b1d8\$lut for cells of type $lut.
Using template $paramod$1c8aea8d15a8caa53bcd106d813c48ea86657836\$lut for cells of type $lut.
Using template $paramod$891d17c049ef97ffbed57a5d4edf3f9e83d4f776\$lut for cells of type $lut.
Using template $paramod$5a3b726670ce434c27ab6d39e16edfbe9baa03b2\$lut for cells of type $lut.
Using template $paramod$90edad2b6a4dec5adef9ce6a532f7a1edb48db32\$lut for cells of type $lut.
Using template $paramod$dcba541ad53a9873d71bfba6c13dc2a8e2a60a79\$lut for cells of type $lut.
Using template $paramod$e5c9ab9a76add278e3096395cd8bc49c38026588\$lut for cells of type $lut.
Using template $paramod$973818279bc95792902f3c09371fd2407d04a2a5\$lut for cells of type $lut.
Using template $paramod$1b21bfe3f0f701f19b91b9d9f4b2cb25c52e0379\$lut for cells of type $lut.
Using template $paramod$a5decf35c8e89d7ee0a60057106759110775301b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101101 for cells of type $lut.
Using template $paramod$47671b68495b53d6eea5a9dd67c114907e17980b\$lut for cells of type $lut.
Using template $paramod$c214b4f4a9031361a7ff4859158ca8c9d48de37d\$lut for cells of type $lut.
Using template $paramod$037be5c00d8a02858cdb1ab049b58a0133287ff1\$lut for cells of type $lut.
Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut.
Using template $paramod$07b1b12ce0305f55108770e958fd02caedfebdf8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut.
Using template $paramod$a03ef989f8f4e1878ce2f5c4e0e3d2dfb54307ef\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000101 for cells of type $lut.
Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut.
Using template $paramod$bb4fff1cc3b827238aa40993cafede1c5beecbe3\$lut for cells of type $lut.
Using template $paramod$91bdb23d9b60d1f7254461792a6db3468fa5ace0\$lut for cells of type $lut.
Using template $paramod$0defb1586b24785b85905f661056d6b3d902c0c8\$lut for cells of type $lut.
Using template $paramod$35d6d6bee07fbed4c99d77928117736fae8df929\$lut for cells of type $lut.
Using template $paramod$a5a9d48041af65bd5d7b6a1f6014e7ed22f6b87a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010001 for cells of type $lut.
Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut.
Using template $paramod$c0e395c2d0dfbafa147a6aae7cfc1897ce26affb\$lut for cells of type $lut.
Using template $paramod$63114da772fb28945ba24699e32f1e30ca7142f4\$lut for cells of type $lut.
Using template $paramod$b587e1dcd8f8a9800d395e4aeecac52c55d6f585\$lut for cells of type $lut.
Using template $paramod$f7a897257decedfb6cc642e53d65fef7fc0df390\$lut for cells of type $lut.
Using template $paramod$f6205ea4d16154fcc0de4d21dff0bd55a57f1ba0\$lut for cells of type $lut.
Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut.
Using template $paramod$ede67ae6159d4864b11272c4fe0692c3419120cd\$lut for cells of type $lut.
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut.
Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod$12e9049d8709286a770fe60b59ec4d94c39ce3c9\$lut for cells of type $lut.
Using template $paramod$2a4b250d89be3556c74aa0e719a4f6242369d42f\$lut for cells of type $lut.
Using template $paramod$e57bcb018bfe8170bc04f13a73befe2def28cdf3\$lut for cells of type $lut.
Using template $paramod$6d23198eb2b8f79a41c7626605a61009695893b1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010011 for cells of type $lut.
Using template $paramod$1b53a9695a0f80de7517b50863b438fd2b7f56da\$lut for cells of type $lut.
Using template $paramod$3fd3bba107ae74034eaf37dd17340d335c6579b1\$lut for cells of type $lut.
Using template $paramod$6be53ab59e0a69757fc32adb071ddcb64e8c87b6\$lut for cells of type $lut.
Using template $paramod$413d040dcd860cd74ca61a70644516a95d328ae7\$lut for cells of type $lut.
Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut.
Using template $paramod$3d7168c8134c4765b84a7b86d5ef7e1e65bbf4a0\$lut for cells of type $lut.
Using template $paramod$22a17f102d8eb29f9e3f67afc5da9acc7c1e8867\$lut for cells of type $lut.
Using template $paramod$18b66a2dc66be2a0d172c3d50ba03932f5924e22\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
Using template $paramod$2ae22ed255cc0f3746c71b5da2407ee38a2a66e6\$lut for cells of type $lut.
Using template $paramod$a5627e8ad36aa9b4fe2f6188097d151d45fefa8a\$lut for cells of type $lut.
Using template $paramod$a1cfe99817bd6d57a83efd5e1c3fc26a743b692f\$lut for cells of type $lut.
Using template $paramod$7ea2352f8f054781a715aeddf3e67f1db65f005a\$lut for cells of type $lut.
Using template $paramod$250e9ed6c15020113b6b30a5ef7c8f11f208ca8e\$lut for cells of type $lut.
Using template $paramod$4853050665c020c8d21fb1a749196950a09d9df8\$lut for cells of type $lut.
Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0\$lut for cells of type $lut.
Using template $paramod$37c9af120c85145419565a9ccf4ceb7397fbbe92\$lut for cells of type $lut.
Using template $paramod$707701b498a5cd123a043548b93e61e0b6bdc440\$lut for cells of type $lut.
Using template $paramod$f5c5b56521a6811444a94cf8aec11258bf0a108d\$lut for cells of type $lut.
Using template $paramod$284267df938459b9413fa2429dd65c56f230d038\$lut for cells of type $lut.
Using template $paramod$aaf2ef5cf75121bbc717334d538c8a2de3e26e03\$lut for cells of type $lut.
Using template $paramod$c52825d0b1a0cfc6362b36af6d13149a97d3e424\$lut for cells of type $lut.
Using template $paramod$f52df4b90f46c2ab9e801e1f39516c9cb1bb6ae7\$lut for cells of type $lut.
Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut.
Using template $paramod$a7d9b4ab0321c8125e5b895183ee6b84cdb4a31b\$lut for cells of type $lut.
Using template $paramod$98c396e6f215a5928f903721dfd7ad31ae8269ff\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut.
Using template $paramod$faba0cf60f1c89602d59ba2d491152c8f0d36384\$lut for cells of type $lut.
Using template $paramod$4e0dac06d9d9602cfb659e01e0850b77eec5b798\$lut for cells of type $lut.
Using template $paramod$a648edd7290dbdc60b4277769ac1653dae6fd74c\$lut for cells of type $lut.
Using template $paramod$7cca51110b6fee949c7a0c7918ee3db0ff20256e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011111 for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut.
Using template $paramod$18df3812bc12364e5ebcb6c3ed05c0294e4c26fc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut.
Using template $paramod$2955ab75367a3dc9d6f50d3655eebcd4f615031f\$lut for cells of type $lut.
Using template $paramod$18368a3da11a7221c7fb674ec80ee0d0bd64b883\$lut for cells of type $lut.
Using template $paramod$6f9324703e8fcc3b6df2bc2bec54ec19a446ae96\$lut for cells of type $lut.
Using template $paramod$c7017ce6f918370601990fdcd7ae7caf301de017\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut.
Using template $paramod$0d26e42822227428593a6f2ed183ae9b22d4b575\$lut for cells of type $lut.
Using template $paramod$c685a6e5e211287be351ac5f1078c1501564ce89\$lut for cells of type $lut.
Using template $paramod$1826e3aea176eca4e438cbfbcc6240c4b3fb0669\$lut for cells of type $lut.
Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut.
Using template $paramod$1e06da73d21c5736c1f943dd00fdcd4f80e36a2b\$lut for cells of type $lut.
Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut.
Using template $paramod$000fa2164e1f538c16460571efee2b6209a086cc\$lut for cells of type $lut.
Using template $paramod$88c7fa4cebf7dcb13ff45f839cb2ced3333f7369\$lut for cells of type $lut.
Using template $paramod$345fd45d08372b78664700630f82ee6e3f3317d9\$lut for cells of type $lut.
Using template $paramod$749a720f9ea286bd3d8f1aeede2e7b705292a16d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100111 for cells of type $lut.
Using template $paramod$8ccf61cbd280c99ab22986f0067fd91897da1e7f\$lut for cells of type $lut.
Using template $paramod$0ee0167fb5dd83bdfe7197fff23e2c7146c57037\$lut for cells of type $lut.
Using template $paramod$8f7210088a40da1859d27e900c288fd298d68bed\$lut for cells of type $lut.
Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut.
Using template $paramod$75d5c453cca75cc7a7ca320c4fb7be0932b6aaa7\$lut for cells of type $lut.
Using template $paramod$16894c241be5ea1f024e9339dea788b4dbe184ae\$lut for cells of type $lut.
Using template $paramod$c8f16510db975553c8b0be1064e8f5234175f8a8\$lut for cells of type $lut.
Using template $paramod$4b9b235bc4444ff899bef0c648e4109b26737f1a\$lut for cells of type $lut.
Using template $paramod$694c95659b447cef99dd4cdbd49b87dfd5f6c806\$lut for cells of type $lut.
Using template $paramod$e412821338883e25f2e0d1a1d7fada158db69807\$lut for cells of type $lut.
Using template $paramod$12879138d1e376f344e47ea40be66b776233be75\$lut for cells of type $lut.
Using template $paramod$fc31732417b7be9ad8ea4524b9939a4cc422dcee\$lut for cells of type $lut.
Using template $paramod$fcff9a7b1687e357a40264efcefe8443c8b2971a\$lut for cells of type $lut.
Using template $paramod$58df2c605746858c7e53492c8f57d6f1fafa12d2\$lut for cells of type $lut.
Using template $paramod$f921ab2c451d17e196d1dcad0b6d434881387fe3\$lut for cells of type $lut.
Using template $paramod$f68de29f78ad6d35b4f626a77ea0c5bcedd2fbbf\$lut for cells of type $lut.
Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b\$lut for cells of type $lut.
Using template $paramod$e019cb14313283ce60b57907d30cf3eefa00a93d\$lut for cells of type $lut.
Using template $paramod$4a8554d0a765102353ca9705f6a3cc329f4379e7\$lut for cells of type $lut.
Using template $paramod$dbdbcb07b9994e498bb1324e5c006c6aa08a7a37\$lut for cells of type $lut.
Using template $paramod$f24ba3ced4b870f8e829f5ac5a8af88573350e6f\$lut for cells of type $lut.
Using template $paramod$ea5280fce2698f0f291737e66fca69a1d9d058e1\$lut for cells of type $lut.
Using template $paramod$5073915fb3e3b6ee5612ea669fd7c36dbda7407c\$lut for cells of type $lut.
Using template $paramod$ba7f31f246a278c41fa0648a6e0512f63185dec0\$lut for cells of type $lut.
Using template $paramod$39b0d201a18bed5573a88835da3f39d40814d360\$lut for cells of type $lut.
Using template $paramod$a63014c5e66a56dc5e61848489c809a59ebe7c34\$lut for cells of type $lut.
Using template $paramod$325e90edf97670f9dea57833ae1f51a5e8bcddea\$lut for cells of type $lut.
Using template $paramod$c7754eeb17b54dfe53ea4a973db3714d78ced2f9\$lut for cells of type $lut.
Using template $paramod$eec22efc31481e6a2706a92743e67f4f90bad45a\$lut for cells of type $lut.
Using template $paramod$d2cb890d399dbdaa4981537b2f73f01e6cdb0947\$lut for cells of type $lut.
Using template $paramod$d08bd524390fbab3497855475f30a6ee4f3c1394\$lut for cells of type $lut.
Using template $paramod$09244871c4b5bfde1862f3870962d986eba7a18e\$lut for cells of type $lut.
Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad\$lut for cells of type $lut.
Using template $paramod$fdcae86fcfd036c1880a04306ae771a9d7579c31\$lut for cells of type $lut.
Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba\$lut for cells of type $lut.
Using template $paramod$7491e7206ae8c682d288373efe06a43b67c277cf\$lut for cells of type $lut.
Using template $paramod$e134ec2a47a2462a591072e65d34fb15b81c90e0\$lut for cells of type $lut.
Using template $paramod$38f9bf4dd2329347b8471f0a98443dd323386889\$lut for cells of type $lut.
Using template $paramod$b2192df6f90569fea4015d0a6658bdc192199f95\$lut for cells of type $lut.
Using template $paramod$64f43dc318f4c77b4186c3ebcba0aa7863e84359\$lut for cells of type $lut.
Using template $paramod$f1a1d9f676e9a8dfefb9d549b9b2c26a026e27e6\$lut for cells of type $lut.
Using template $paramod$f2972f00f781f1a033cecbb6cc420de13224764a\$lut for cells of type $lut.
Using template $paramod$e4723c78131b859cdb296cc7099a965ce6bf28d9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101110 for cells of type $lut.
Using template $paramod$9664b2f5fd61944d7798b30cde43b99ccda87303\$lut for cells of type $lut.
Using template $paramod$8c13ad014d500c3a349fa680995aa7f6f9eaaf87\$lut for cells of type $lut.
Using template $paramod$1e9d7896e1dd3d2af9633eefc9c29afb478cef41\$lut for cells of type $lut.
Using template $paramod$20aecb9a781743d0e93608b1c1e7d62ffc3a69a9\$lut for cells of type $lut.
Using template $paramod$f94cf08026d21db794b98b1a8efaec5f34ff8975\$lut for cells of type $lut.
Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882\$lut for cells of type $lut.
Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54\$lut for cells of type $lut.
Using template $paramod$127c0f065cbdbfc01465fd58161d13b20251be83\$lut for cells of type $lut.
Using template $paramod$5c0eb292ef891be47277bee5c25eaa71b34b43e2\$lut for cells of type $lut.
Using template $paramod$7295da7c5b19f528a428229f2570e0a23ad372af\$lut for cells of type $lut.
Using template $paramod$47b2f5a9f58cb4be072657772748a1ab82d6819a\$lut for cells of type $lut.
Using template $paramod$3e63470ea7a06b3eefdfb990254dd83d20fa13a7\$lut for cells of type $lut.
Using template $paramod$50222e4d0527635d5cf211ed95d1ccfc839e99e8\$lut for cells of type $lut.
Using template $paramod$e77dca5e1fc847f9005cbcedebcb6de355499010\$lut for cells of type $lut.
Using template $paramod$ab4188c7524eec831e9177bc675d62b21a3ccd8b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut.
Using template $paramod$bf8a2eb9c34204449ae734db198784b474646269\$lut for cells of type $lut.
Using template $paramod$1843b3c15f2447d117e2d5de9b00f791ef5f9fa3\$lut for cells of type $lut.
Using template $paramod$02b63907fb626de3e5f6572173cbabd407ece191\$lut for cells of type $lut.
Using template $paramod$01d6171b877f7655dc0d32e32900a6a207a75b44\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod$432e4e01d71b10f1550b48be5a824f4f5138a82c\$lut for cells of type $lut.
Using template $paramod$e1ac894a2723e96ae103a1941dc871fbb0ccd216\$lut for cells of type $lut.
Using template $paramod$34536926332939882b8ff52380fffc08ed1f405f\$lut for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut.
Using template $paramod$f9b715fbf1040e81e900b2461c2390d17ed5e988\$lut for cells of type $lut.
Using template $paramod$1b4dd6457d07f8f165ec99061b8d6c5023635c5b\$lut for cells of type $lut.
Using template $paramod$b18f60dfd13c21d3e472b89652353f3f5342b450\$lut for cells of type $lut.
Using template $paramod$d4fae2c0d9ad2966369cd4e39b81c71bcd1327c9\$lut for cells of type $lut.
Using template $paramod$50ec6039d9de561a6d0a8dc470847f22a306b04f\$lut for cells of type $lut.
No more expansions possible.
<suppressed ~12658 debug messages>

21.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in processorci_top.
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153876.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153889.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153903.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153995.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154052.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154076.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154089.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154101.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154119.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154161.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153987.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153845.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153926.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153918.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154018.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153974.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153975.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$30150.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$28739.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$27529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$27511.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$26643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$26643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$26643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$25175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24719.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$21212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$21212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$21206.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$21197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$21197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$21197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$20287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$20287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$20281.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$17963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$17963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$17079.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$17071.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$17048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$17048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$17042.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$17038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$17034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$17030.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154165.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154165.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154165.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154165.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154165.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154165.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16957.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16896.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16864.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16860.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16846.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16822.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154169.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16807.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16807.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16807.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16807.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16807.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16807.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16777.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16758.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16754.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16744.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16736.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16732.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16727.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16723.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16688.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16684.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16680.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16662.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16658.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16654.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16569.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154173.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16422.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16396.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16324.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16316.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16312.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16306.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16302.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16294.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16276.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16251.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16206.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16202.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16193.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16131.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16092.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16055.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16047.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16002.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15945.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$15929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$15929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$15859.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$15822.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$15813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15807.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$15603.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$15583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$15583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$15557.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15447.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15401.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15401.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$15392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15376.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15376.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15376.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15376.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$15376.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$15252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$15252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$15252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$15232.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$15153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$15153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$15073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$15073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$14951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154245.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14762.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154265.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$14517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$14496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14384.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14384.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14384.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$14331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154249.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14110.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154248.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154248.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13952.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154254.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154211.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154211.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154211.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154258.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154220.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13070.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154231.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154224.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154228.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154228.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154227.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154251.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154252.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12370.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12282.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12282.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12282.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12282.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12282.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12282.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$11852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$11852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$11852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$11819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$11803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$11803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$11803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$11790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$11790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$11790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$11790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$11765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153993.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$11575.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$11681.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$11689.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$11765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$11765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$11790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$11790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$11803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$11803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$11819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$11819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$11828.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$11833.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$11839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$11852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$11852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$11860.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$11865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$11871.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$11881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$11896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12094.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12370.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12402.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$12462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154232.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154223.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12639.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154255.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154264.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12801.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$12808.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$12971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13055.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13390.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$13627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154235.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13729.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154226.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154247.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14110.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154237.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14384.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154267.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$14552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14934.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15012.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154222.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15182.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$15259.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$15270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$15289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154270.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$15314.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15326.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15376.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15401.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154269.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15437.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15482.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15501.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15527.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$15593.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15607.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15633.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$15725.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15784.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15799.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$15827.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$15843.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15863.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$15884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15889.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$15893.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$15902.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15911.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15918.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$15929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$15937.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15949.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$15994.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16020.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16028.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16039.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16076.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16084.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16115.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16175.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16232.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16245.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16259.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16280.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154177.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16328.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16367.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16404.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16414.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16494.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16498.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16563.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16585.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16593.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$16781.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16807.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16826.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16832.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16842.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16923.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16931.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16939.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$16963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16978.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$16998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154165.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$17006.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$17022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$17048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$17083.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154163.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$17129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$17275.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$17339.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$17345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$17369.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$17386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$17390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$17408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$17567.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$17666.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$17720.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$17729.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$17810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$17820.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23604.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$17963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$17970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18024.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$18055.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$auto$opt_dff.cc:219:make_patterns_logic$4845.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$18165.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$18198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18276.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18292.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$18380.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18391.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18457.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18532.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$18539.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18572.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18585.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18592.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18608.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18624.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18640.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18710.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18725.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$18766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$18828.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$18979.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$19013.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$19038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$19098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$19114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$19148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$19164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$19180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$19199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$19215.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$19231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$19298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$19398.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$19412.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$19428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$19582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$19589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$19596.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$19609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$19643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$19653.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$19660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$19678.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$19694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$19709.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$19736.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$19748.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$19788.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$19886.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$19893.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$19912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$19928.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20037.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$20047.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20066.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20081.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$20098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20116.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$20150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20287.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$20361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20411.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20460.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20485.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$20489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20496.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20515.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20530.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20543.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$20565.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$20599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$20635.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$20723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20730.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20787.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20800.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$20807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$20833.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$20873.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20889.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20943.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$20978.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$20994.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$21012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$21025.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$21048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$21188.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$21197.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$21231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$21244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$21257.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$21264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$21286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$21290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$21392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$21429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$21436.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$21443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$21461.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$21477.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$21495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$21508.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$21621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$21664.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$21800.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$21816.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$21834.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$21847.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$21854.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$21869.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$21882.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$21903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$21916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$21939.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$22074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$22117.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$22224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$22258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$22274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$22293.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$22317.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$22325.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$22341.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$22355.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$22363.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$22472.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$22497.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$22555.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$22574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$22590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$22608.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$22621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$22628.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$22643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$22659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$22677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$22690.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$22713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$22813.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$22829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$22854.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$22873.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$22913.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$22929.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$23077.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$23165.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$23217.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23233.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23267.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23341.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$23345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23410.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$23429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23436.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$23443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23461.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$23495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23511.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$23561.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$23696.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23730.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23740.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$23747.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23765.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$23799.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23815.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$23835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23941.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23954.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23967.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$23974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$23996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$24000.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$24040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24056.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24069.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24125.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$24176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$24194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$24228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24241.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$24264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24493.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24527.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24537.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$24544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24562.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24575.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$24596.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$24737.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$24771.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24793.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$24826.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24921.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24954.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$24998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$25005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25023.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25057.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25073.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$25093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$25165.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$25175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25224.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25280.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$25377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$25414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25421.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$25428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$25480.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25493.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$25516.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$25564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25577.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$25597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25640.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25699.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25733.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$25750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25781.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$25802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25815.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$25838.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$25873.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26057.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$26117.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$26154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$26170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$26186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26233.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$26256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$26283.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26359.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26441.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$26461.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26508.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26515.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$26530.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26577.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$26600.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$26629.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26740.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26784.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26867.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$26896.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26917.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26933.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26961.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$26968.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26986.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$26999.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$27020.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$27056.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$27279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27293.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27349.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$27365.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$27381.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27397.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$27451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27519.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$27544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27558.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27614.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$27647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$27687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27706.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27722.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27740.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$27757.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$27809.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$27892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27905.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27918.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$27925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$27947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$27951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$27991.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28007.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28020.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28043.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$28061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28081.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$28096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$28166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$28196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28200.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28285.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$28411.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28424.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$28448.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28455.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$28462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28480.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28496.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28514.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28527.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$28550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$28596.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$28680.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$28718.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$28747.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28783.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28796.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$28817.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28827.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$28834.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28852.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$28886.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28939.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$28990.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$29047.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$29066.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$29082.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$29116.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$29138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$29142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$29182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$29221.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$29256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$29294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$29310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$29328.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$29341.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$29362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$29453.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$29480.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$29523.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$29620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$29700.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$29711.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$29766.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$29787.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$29812.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$29879.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$29903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$29950.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$30061.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$30098.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$30154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$30287.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$30360.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$30427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153809$lut$aiger153808$30444.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$30465.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$30489.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$30510.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$30521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$30563.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$30570.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$30574.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$30647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$30735.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$30751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$30777.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$30781.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$30801.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$30808.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$30835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$30847.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$30854.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$30946.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$auto$opt_dff.cc:219:make_patterns_logic$4566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$auto$opt_dff.cc:219:make_patterns_logic$4685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$auto$opt_dff.cc:219:make_patterns_logic$4874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$auto$rtlil.cc:2628:Mux$5233[14].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$auto$rtlil.cc:2628:Mux$5233[16].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$auto$rtlil.cc:2628:Mux$5233[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$auto$rtlil.cc:2628:Mux$5233[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$auto$rtlil.cc:2628:Mux$5233[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$auto$rtlil.cc:2628:Mux$5233[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$auto$rtlil.cc:2628:Mux$5233[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$auto$rtlil.cc:2628:Mux$5233[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut\Controller.Memory.address[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$auto$fsm_map.cc:170:map_fsm$4418[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut\Controller.Memory.address[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153850.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153855.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153859.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153867.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153881.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153895.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$27529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153897.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153902.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153912.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153918.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153916.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$26648.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153940.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153948.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153935.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154001.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153931.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153953.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153953.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153935.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153959.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153973.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153975.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153987.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153963.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153979.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154001.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154003.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154010.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154023.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154198.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153942.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154023.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154032.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154035.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154035.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154051.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154041.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$21212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154065.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154063.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154072.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154075.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154080.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154081.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154090.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154099.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154099.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154107.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154107.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154112.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154114.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154129.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154139.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154131.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154135.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153809$lut$aiger153808$18141.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154139.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153897.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154161.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154161.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154167.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$16532.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154187.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154190.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154219.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154253.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154228.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154025.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154239.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154243.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154248.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153809$lut$aiger153808$12639.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$13390.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153809$lut$aiger153808$14714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$154268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Removed 0 unused cells and 16742 unused wires.

21.45. Executing AUTONAME pass.
Renamed 659489 objects in module processorci_top (273 iterations).
<suppressed ~20764 debug messages>

21.46. Executing HIERARCHY pass (managing design hierarchy).

21.46.1. Analyzing design hierarchy..
Top module:  \processorci_top

21.46.2. Analyzing design hierarchy..
Top module:  \processorci_top
Removed 0 unused modules.

21.47. Printing statistics.

=== processorci_top ===

   Number of wires:               9263
   Number of wire bits:          27024
   Number of public wires:        9263
   Number of public wire bits:   27024
   Number of ports:                 10
   Number of port bits:             10
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              12887
     $scopeinfo                     24
     CCU2C                         403
     L6MUX21                       476
     LUT4                         7777
     MULT18X18D                      4
     PFUMX                        1553
     TRELLIS_DPR16X4              1076
     TRELLIS_FF                   1574

21.48. Executing CHECK pass (checking for obvious problems).
Checking module processorci_top...
Found and reported 0 problems.

21.49. Executing JSON backend.

Warnings: 324 unique messages, 325 total
End of script. Logfile hash: 7ba5bc6260, CPU: user 31.90s system 0.27s, MEM: 315.70 MB peak
Yosys 0.45+139 (git sha1 4d581a97d, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)
Time spent: 38% 1x abc9_exe (20 sec), 11% 11x techmap (6 sec), ...
/eda/oss-cad-suite/bin/nextpnr-ecp5 --json colorlight_i9.json --write colorlight_i9_pnr.json --45k \
	--lpf /eda/processor-ci/constraints/colorlight_i9.lpf --textcfg colorlight_i9.config --package CABGA381 \
	--speed 6 --lpf-allow-unconstrained  --ignore-loops
/eda/oss-cad-suite/bin/ecppack --compress --input colorlight_i9.config  --bit colorlight_i9.bit

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] dir
Running in /var/jenkins_home/workspace/Risco-5/Risco-5
[Pipeline] {
[Pipeline] echo
FPGA colorlight_i9 bloqueada para flash.
[Pipeline] sh
+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Risco-5 -b colorlight_i9 -l
Arquivo de configuração final gerado em /var/jenkins_home/workspace/Risco-5/Risco-5/build_colorlight_i9.tcl
Makefile executado com sucesso.
Saída do Makefile:
/eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 colorlight_i9.bit
empty
Found 1 compatible device:
	0x0d28 0x0204 0x3 (null)
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE

Loading: [====                                              ] 7.34%
Loading: [========                                          ] 14.41%
Loading: [===========                                       ] 21.75%
Loading: [===============                                   ] 29.09%
Loading: [===================                               ] 36.43%
Loading: [======================                            ] 43.77%
Loading: [==========================                        ] 51.11%
Loading: [==============================                    ] 58.45%
Loading: [=================================                 ] 65.80%
Loading: [=====================================             ] 72.59%
Loading: [=======================================           ] 76.40%
Loading: [==========================================        ] 82.38%
Loading: [=============================================     ] 89.45%
Loading: [===============================================   ] 93.53%
Loading: [==================================================] 98.15%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste colorlight_i9)
[Pipeline] echo
Testando FPGA colorlight_i9.
[Pipeline] dir
Running in /var/jenkins_home/workspace/Risco-5/Risco-5
[Pipeline] {
[Pipeline] sh
+ PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py

Running tests...
----------------------------------------------------------------------
..FFFFFFFFFFFFF
======================================================================
FAIL [0.107s]: test_jalr (test_00.TestTypeIBasic.test_jalr)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 112, in test_jalr
    self.assertEqual(int.from_bytes(retorno, "big"), 7)
AssertionError: 10 != 7

======================================================================
FAIL [0.108s]: test_jalr_2 (test_00.TestTypeIBasic.test_jalr_2)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 119, in test_jalr_2
    self.assertEqual(int.from_bytes(retorno, "big"), 7)
AssertionError: 10 != 7

======================================================================
FAIL [0.106s]: test_lb (test_00.TestTypeIBasic.test_lb)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 105, in test_lb
    self.assertEqual(int.from_bytes(retorno, "big"), 0xFF)
AssertionError: 10 != 255

======================================================================
FAIL [0.107s]: test_lh (test_00.TestTypeIBasic.test_lh)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 98, in test_lh
    self.assertEqual(int.from_bytes(retorno, "big"), 0xFFC0)
AssertionError: 10 != 65472

======================================================================
FAIL [0.110s]: test_lw (test_00.TestTypeIBasic.test_lw)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 91, in test_lw
    self.assertEqual(int.from_bytes(retorno, "big"), 0x809)
AssertionError: 10 != 2057

======================================================================
FAIL [0.108s]: test_ori (test_00.TestTypeIBasic.test_ori)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 35, in test_ori
    self.assertEqual(int.from_bytes(retorno, "big"), 7)
AssertionError: 10 != 7

======================================================================
FAIL [0.106s]: test_slli (test_00.TestTypeIBasic.test_slli)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 70, in test_slli
    self.assertEqual(int.from_bytes(retorno, "big"), 8)
AssertionError: 10 != 8

======================================================================
FAIL [0.107s]: test_slli_2 (test_00.TestTypeIBasic.test_slli_2)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 77, in test_slli_2
    self.assertEqual(int.from_bytes(retorno, "big"), 0x10)
AssertionError: 10 != 16

======================================================================
FAIL [0.110s]: test_slti (test_00.TestTypeIBasic.test_slti)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 49, in test_slti
    self.assertEqual(int.from_bytes(retorno, "big"), 0)
AssertionError: 10 != 0

======================================================================
FAIL [0.106s]: test_slti_2 (test_00.TestTypeIBasic.test_slti_2)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 56, in test_slti_2
    self.assertEqual(int.from_bytes(retorno, "big"), 1)
AssertionError: 10 != 1

======================================================================
FAIL [0.106s]: test_sltiu (test_00.TestTypeIBasic.test_sltiu)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 63, in test_sltiu
    self.assertEqual(int.from_bytes(retorno, "big"), 1)
AssertionError: 10 != 1

======================================================================
FAIL [0.112s]: test_srli (test_00.TestTypeIBasic.test_srli)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 84, in test_srli
    self.assertEqual(int.from_bytes(retorno, "big"), 2)
AssertionError: 10 != 2

======================================================================
FAIL [0.106s]: test_xori (test_00.TestTypeIBasic.test_xori)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 42, in test_xori
    self.assertEqual(int.from_bytes(retorno, "big"), 6)
AssertionError: 10 != 6

----------------------------------------------------------------------
Ran 15 tests in 2.036s

FAILED (failures=13)

Generating XML reports...
Traceback (most recent call last):
  File "/eda/processor-ci-communication/run_tests.py", line 27, in <module>
    xmlrunner.XMLTestRunner(output=output).run(test_case)
  File "/usr/lib/python3/dist-packages/xmlrunner/runner.py", line 113, in run
    result.generate_reports(self)
  File "/usr/lib/python3/dist-packages/xmlrunner/result.py", line 674, in generate_reports
    test_runner.output.write(xml_content)
TypeError: write() argument must be str, not bytes
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: colorlight_i9]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch colorlight_i9
Arquivo de configuração final gerado em /var/jenkins_home/workspace/Risco-5/Risco-5/build_digilent_nexys4_ddr.tcl
Erro ao executar o Makefile.
realloc(): invalid pointer
make: *** [/eda/processor-ci/makefiles/digilent_nexys4_ddr.mk:12: digilent_nexys4_ddr.bit] Error 134

Traceback (most recent call last):
  File "/eda/processor-ci/main.py", line 79, in <module>
    main(
  File "/eda/processor-ci/main.py", line 26, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor-ci/core/fpga.py", line 113, in build
    raise subprocess.CalledProcessError(process.returncode, "make")
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_nexys4_ddr)
Stage "Flash digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste digilent_nexys4_ddr)
Stage "Teste digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_nexys4_ddr]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch digilent_nexys4_ddr
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
[Checks API] No suitable checks publisher found.
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE