Console Output

Started by user Julio Nunes Avelar
[Pipeline] Start of Pipeline
[Pipeline] node
Still waiting to schedule task
Waiting for next available executor
Running on Jenkins in /var/lib/jenkins/workspace/Risco 5@2
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -Rf Risco-5/ build/
[Pipeline] sh
+ git clone https://github.com/JN513/Risco-5
Cloning into 'Risco-5'...
[Pipeline] sh
+ cd Risco-5
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (IVerilog)
[Pipeline] sh
+ mkdir -p build
[Pipeline] sh
+ cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex
[Pipeline] sh
+ /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb Risco-5/src/core/alu.v Risco-5/src/core/alu_control.v Risco-5/src/core/control_unit.v Risco-5/src/core/core.v Risco-5/src/core/immediate_generator.v Risco-5/src/core/mux.v Risco-5/src/core/pc.v Risco-5/src/core/registers.v Risco-5/src/peripheral/bus.v Risco-5/src/peripheral/gpio.v Risco-5/src/peripheral/gpios.v Risco-5/src/peripheral/leds.v Risco-5/src/peripheral/memory.v Risco-5/src/peripheral/soc.v Risco-5/src/peripheral/uart.v Risco-5/src/peripheral/uart_rx.v Risco-5/src/peripheral/uart_tx.v Risco-5/tests/soc_test.v
[Pipeline] sh
+ /eda/oss-cad-suite/bin/vvp build/soc_test.o
ERROR: Risco-5/src/peripheral/memory.v:27: $readmemh: Unable to open software/memory/generic.hex for reading.
VCD info: dumpfile build/soc.vcd opened for output.
Risco-5/tests/soc_test.v:32: $finish called at 566 (1s)
[Pipeline] sh
+ rm -f Risco5/software/memory/generic.hex
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Síntese)
[Pipeline] parallel
[Pipeline] { (Branch: OSS-Cad-Suite)
[Pipeline] { (Branch: Gowin)
[Pipeline] stage
[Pipeline] { (OSS-Cad-Suite)
[Pipeline] stage
[Pipeline] { (Gowin)
[Pipeline] stage
[Pipeline] { (Yosys)
[Pipeline] sh
[Pipeline] sh
+ echo 

[Pipeline] }
+ /eda/oss-cad-suite/bin/yosys -p                                          read_verilog Risco-5/fpga/ecp5/*.v;                                         read_verilog Risco-5/debug/clk_divider.v;                                         read_verilog Risco-5/src/core/*.v;                                         read_verilog Risco-5/src/peripheral/*.v;                                         synth_ecp5 -json ./build/out.json -abc9                                     

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.36+8 (git sha1 fb4cbfa73, clang 10.0.0-4ubuntu1 -fPIC -Os)


-- Running command `                                         read_verilog Risco-5/fpga/ecp5/*.v;                                         read_verilog Risco-5/debug/clk_divider.v;                                         read_verilog Risco-5/src/core/*.v;                                         read_verilog Risco-5/src/peripheral/*.v;                                         synth_ecp5 -json ./build/out.json -abc9                                     ' --

1. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/main.v
Parsing Verilog input from `Risco-5/fpga/ecp5/main.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/reset.v
Parsing Verilog input from `Risco-5/fpga/ecp5/reset.v' to AST representation.
Generating RTLIL representation for module `\ResetBootSystem'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: Risco-5/debug/clk_divider.v
Parsing Verilog input from `Risco-5/debug/clk_divider.v' to AST representation.
Generating RTLIL representation for module `\ClkDivider'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: Risco-5/src/core/alu.v
Parsing Verilog input from `Risco-5/src/core/alu.v' to AST representation.
Generating RTLIL representation for module `\ALU'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: Risco-5/src/core/alu_control.v
Parsing Verilog input from `Risco-5/src/core/alu_control.v' to AST representation.
Generating RTLIL representation for module `\ALU_Control'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: Risco-5/src/core/control_unit.v
Parsing Verilog input from `Risco-5/src/core/control_unit.v' to AST representation.
Generating RTLIL representation for module `\Control_Unit'.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: Risco-5/src/core/core.v
Parsing Verilog input from `Risco-5/src/core/core.v' to AST representation.
Generating RTLIL representation for module `\Core'.
Risco-5/src/core/core.v:76: Warning: Identifier `\pc_source' is implicitly declared.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: Risco-5/src/core/immediate_generator.v
Parsing Verilog input from `Risco-5/src/core/immediate_generator.v' to AST representation.
Generating RTLIL representation for module `\Immediate_Generator'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: Risco-5/src/core/mux.v
Parsing Verilog input from `Risco-5/src/core/mux.v' to AST representation.
Generating RTLIL representation for module `\MUX'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: Risco-5/src/core/pc.v
Parsing Verilog input from `Risco-5/src/core/pc.v' to AST representation.
Generating RTLIL representation for module `\PC'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: Risco-5/src/core/registers.v
Parsing Verilog input from `Risco-5/src/core/registers.v' to AST representation.
Generating RTLIL representation for module `\Registers'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: Risco-5/src/peripheral/bus.v
Parsing Verilog input from `Risco-5/src/peripheral/bus.v' to AST representation.
Generating RTLIL representation for module `\BUS'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpio.v
Parsing Verilog input from `Risco-5/src/peripheral/gpio.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (Risco-5/src/peripheral/gpio.v:9)
Generating RTLIL representation for module `\GPIO'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpios.v
Parsing Verilog input from `Risco-5/src/peripheral/gpios.v' to AST representation.
Generating RTLIL representation for module `\GPIOS'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend: Risco-5/src/peripheral/leds.v
Parsing Verilog input from `Risco-5/src/peripheral/leds.v' to AST representation.
Generating RTLIL representation for module `\LEDs'.
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend: Risco-5/src/peripheral/memory.v
Parsing Verilog input from `Risco-5/src/peripheral/memory.v' to AST representation.
Generating RTLIL representation for module `\Memory'.
Successfully finished Verilog frontend.

17. Executing Verilog-2005 frontend: Risco-5/src/peripheral/soc.v
Parsing Verilog input from `Risco-5/src/peripheral/soc.v' to AST representation.
Generating RTLIL representation for module `\Risco_5_SOC'.
Successfully finished Verilog frontend.

18. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart.v
Parsing Verilog input from `Risco-5/src/peripheral/uart.v' to AST representation.
Generating RTLIL representation for module `\UART'.
Successfully finished Verilog frontend.

19. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_rx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_rx'.
Successfully finished Verilog frontend.

20. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_tx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_tx'.
Successfully finished Verilog frontend.

21. Executing SYNTH_ECP5 pass.

21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.

21.3. Executing HIERARCHY pass (managing design hierarchy).

21.3.1. Finding top of design hierarchy..
root of   0 design levels: uart_tool_tx        
root of   0 design levels: uart_tool_rx        
root of   1 design levels: UART                
root of   2 design levels: Risco_5_SOC         
root of   0 design levels: Memory              
root of   0 design levels: LEDs                
root of   1 design levels: GPIOS               
root of   0 design levels: GPIO                
root of   0 design levels: BUS                 
root of   0 design levels: Registers           
root of   0 design levels: PC                  
root of   0 design levels: MUX                 
root of   0 design levels: Immediate_Generator 
root of   1 design levels: Core                
root of   0 design levels: Control_Unit        
root of   0 design levels: ALU_Control         
root of   0 design levels: ALU                 
root of   0 design levels: ClkDivider          
root of   0 design levels: ResetBootSystem     
root of   3 design levels: top                 
Automatically selected top as design top module.

21.3.2. Analyzing design hierarchy..
Top module:  \top
Used module:     \Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:         \UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     \ResetBootSystem
Used module:     \ClkDivider
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \MEMORY_SIZE = 4096
Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000
Parameter \GPIO_WIDHT = 5

21.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Risco_5_SOC'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \MEMORY_SIZE = 4096
Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000
Parameter \GPIO_WIDHT = 5
Generating RTLIL representation for module `$paramod$e03256ea8e7445dc30f095427a7bac59d40d5a9f\Risco_5_SOC'.
Parameter \CYCLES = 20

21.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'.
Parameter \CYCLES = 20
Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'.
Parameter \COUNTER_BITS = 32

21.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'.
Parameter \COUNTER_BITS = 32
Generating RTLIL representation for module `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000'.
Parameter \WIDHT = 5

21.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'.
Parameter \WIDHT = 5
Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600

21.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Generating RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

21.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \BOOT_ADDRESS = 0

21.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'.
Parameter \BOOT_ADDRESS = 0
Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.
Risco-5/src/core/core.v:76: Warning: Identifier `\pc_source' is implicitly declared.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

21.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

21.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.

21.3.12. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e03256ea8e7445dc30f095427a7bac59d40d5a9f\Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:         \UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000
Parameter \WIDHT = 5
Found cached RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Found cached RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 4096

21.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory'.
Parameter \BOOT_ADDRESS = 0
Found cached RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.

21.3.14. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e03256ea8e7445dc30f095427a7bac59d40d5a9f\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101
Used module:             \GPIO
Used module:         $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Found cached RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Found cached RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.

21.3.15. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e03256ea8e7445dc30f095427a7bac59d40d5a9f\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101
Used module:             \GPIO
Used module:         $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000

21.3.16. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e03256ea8e7445dc30f095427a7bac59d40d5a9f\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101
Used module:             \GPIO
Used module:         $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000
Removing unused module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Removing unused module `\uart_tool_tx'.
Removing unused module `\uart_tool_rx'.
Removing unused module `\UART'.
Removing unused module `\Risco_5_SOC'.
Removing unused module `\Memory'.
Removing unused module `\GPIOS'.
Removing unused module `\Core'.
Removing unused module `\ClkDivider'.
Removing unused module `\ResetBootSystem'.
Removed 10 unused modules.

21.4. Executing PROC pass (convert processes to netlists).

21.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$394'.
Found and cleaned up 1 empty switch in `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:0$662'.
Removing empty process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:0$662'.
Cleaned up 2 empty switches.

21.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$501 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$453 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$395 in module TRELLIS_DPR16X4.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:197$646 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:186$644 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:171$636 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:160$633 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:148$627 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:133$622 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:116$617 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:97$608 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:173$595 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:162$593 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:147$585 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:130$571 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:115$565 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:98$560 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/core.v:135$550 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:31$653 in module $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/leds.v:23$162 in module LEDs.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/gpios.v:29$531 in module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:155$68 in module Registers.
Removed 2 dead cases from process $proc$Risco-5/src/core/registers.v:81$67 in module Registers.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:81$67 in module Registers.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/pc.v:19$63 in module PC.
Removed 1 dead cases from process $proc$Risco-5/src/core/mux.v:10$62 in module MUX.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/mux.v:10$62 in module MUX.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/immediate_generator.v:7$59 in module Immediate_Generator.
Marked 3 switch rules as full_case in process $proc$Risco-5/debug/clk_divider.v:25$515 in module $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:109$50 in module Control_Unit.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:72$48 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:64$47 in module Control_Unit.
Removed 1 dead cases from process $proc$Risco-5/src/core/alu_control.v:8$45 in module ALU_Control.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/alu_control.v:8$45 in module ALU_Control.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/alu.v:11$30 in module ALU.
Marked 5 switch rules as full_case in process $proc$Risco-5/fpga/ecp5/reset.v:24$504 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Removed a total of 4 dead cases.

21.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 8 redundant assignments.
Promoted 130 assignments to connections.

21.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$502'.
  Set init value: \Q = 1'0
Found init rule in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$648'.
  Set init value: \i = 0
Found init rule in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$601'.
  Set init value: \i = 0
Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$553'.
  Set init value: \instruction_register = 0
  Set init value: \memory_register = 0
  Set init value: \alu_out_register = 0
  Set init value: \register_data_1 = 0
  Set init value: \register_data_2 = 0
Found init rule in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$165'.
  Set init value: \data = 33'000000000000000000000000000000000
Found init rule in `\Registers.$proc$Risco-5/src/core/registers.v:0$71'.
  Set init value: \register0 = 0
  Set init value: \register1 = 0
  Set init value: \register2 = 0
  Set init value: \register3 = 0
  Set init value: \register4 = 0
  Set init value: \register5 = 0
  Set init value: \register6 = 0
  Set init value: \register7 = 0
  Set init value: \register8 = 0
  Set init value: \register9 = 0
  Set init value: \register10 = 0
  Set init value: \register11 = 0
  Set init value: \register12 = 0
  Set init value: \register13 = 0
  Set init value: \register14 = 0
  Set init value: \register15 = 0
  Set init value: \register16 = 0
  Set init value: \register17 = 0
  Set init value: \register18 = 0
  Set init value: \register19 = 0
  Set init value: \register20 = 0
  Set init value: \register21 = 0
  Set init value: \register22 = 0
  Set init value: \register23 = 0
  Set init value: \register24 = 0
  Set init value: \register25 = 0
  Set init value: \register26 = 0
  Set init value: \register27 = 0
  Set init value: \register28 = 0
  Set init value: \register29 = 0
  Set init value: \register30 = 0
  Set init value: \register31 = 0
Found init rule in `\PC.$proc$Risco-5/src/core/pc.v:0$66'.
  Set init value: \PC_Register = 0
Found init rule in `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:0$527'.
  Set init value: \clk_o_pulse = 1'0
  Set init value: \clk_o_auto = 1'0
  Set init value: \clk_counter = 0
Found init rule in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$52'.
  Set init value: \state = 4'0000
  Set init value: \pc_write_cond = 1'0
  Set init value: \pc_write = 1'0
  Set init value: \lorD = 1'0
  Set init value: \memory_read = 1'0
  Set init value: \memory_write = 1'0
  Set init value: \memory_to_reg = 1'0
  Set init value: \ir_write = 1'0
  Set init value: \pc_source = 1'0
  Set init value: \aluop = 2'00
  Set init value: \alu_src_a = 2'00
  Set init value: \alu_src_b = 2'00
  Set init value: \reg_write = 1'0
Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:0$510'.
  Set init value: \reset_o = 1'0
  Set init value: \state = 2'01
  Set init value: \counter = 6'000000

21.4.5. Executing PROC_ARST pass (detect async resets in processes).

21.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~76 debug messages>

21.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$502'.
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$501'.
     1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$476'.
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$453'.
     1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$452_EN[3:0]$459
     2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$452_DATA[3:0]$458
     3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$452_ADDR[3:0]$457
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$419'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$395'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$393_EN[3:0]$401
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$393_DATA[3:0]$400
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$393_ADDR[3:0]$399
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$394'.
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$648'.
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$646'.
     1/2: $0\rxd_reg_0[0:0]
     2/2: $0\rxd_reg[0:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$644'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$636'.
     1/1: $0\cycle_counter[12:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$633'.
     1/1: $0\bit_sample[0:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$627'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$622'.
     1/11: $3\i[31:0]
     2/11: $0\recieved_data[7:0] [1]
     3/11: $0\recieved_data[7:0] [0]
     4/11: $0\recieved_data[7:0] [2]
     5/11: $0\recieved_data[7:0] [3]
     6/11: $0\recieved_data[7:0] [4]
     7/11: $0\recieved_data[7:0] [5]
     8/11: $0\recieved_data[7:0] [6]
     9/11: $0\recieved_data[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$617'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$608'.
     1/1: $0\uart_rx_data[7:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$601'.
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$595'.
     1/1: $0\txd_reg[0:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$593'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$585'.
     1/1: $0\cycle_counter[12:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$571'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$565'.
     1/11: $3\i[31:0]
     2/11: $0\data_to_send[7:0] [1]
     3/11: $0\data_to_send[7:0] [0]
     4/11: $0\data_to_send[7:0] [2]
     5/11: $0\data_to_send[7:0] [3]
     6/11: $0\data_to_send[7:0] [4]
     7/11: $0\data_to_send[7:0] [5]
     8/11: $0\data_to_send[7:0] [6]
     9/11: $0\data_to_send[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$560'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$553'.
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$550'.
     1/5: $0\alu_out_register[31:0]
     2/5: $0\register_data_2[31:0]
     3/5: $0\register_data_1[31:0]
     4/5: $0\memory_register[31:0]
     5/5: $0\instruction_register[31:0]
Creating decoders for process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$653'.
     1/3: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$660
     2/3: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_DATA[31:0]$659
     3/3: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_ADDR[31:0]$658
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$165'.
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$162'.
     1/1: $0\data[32:0]
Creating decoders for process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101.$proc$Risco-5/src/peripheral/gpios.v:29$531'.
     1/2: $0\gpio_value[4:0]
     2/2: $0\gpio_direction[4:0]
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:0$71'.
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
     1/32: $0\register31[31:0]
     2/32: $0\register30[31:0]
     3/32: $0\register29[31:0]
     4/32: $0\register28[31:0]
     5/32: $0\register27[31:0]
     6/32: $0\register26[31:0]
     7/32: $0\register25[31:0]
     8/32: $0\register24[31:0]
     9/32: $0\register23[31:0]
    10/32: $0\register22[31:0]
    11/32: $0\register21[31:0]
    12/32: $0\register20[31:0]
    13/32: $0\register19[31:0]
    14/32: $0\register18[31:0]
    15/32: $0\register17[31:0]
    16/32: $0\register16[31:0]
    17/32: $0\register15[31:0]
    18/32: $0\register14[31:0]
    19/32: $0\register13[31:0]
    20/32: $0\register12[31:0]
    21/32: $0\register11[31:0]
    22/32: $0\register10[31:0]
    23/32: $0\register9[31:0]
    24/32: $0\register8[31:0]
    25/32: $0\register7[31:0]
    26/32: $0\register6[31:0]
    27/32: $0\register5[31:0]
    28/32: $0\register4[31:0]
    29/32: $0\register3[31:0]
    30/32: $0\register2[31:0]
    31/32: $0\register1[31:0]
    32/32: $0\register0[31:0]
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:81$67'.
     1/2: $1\readData2[31:0]
     2/2: $1\readData1[31:0]
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:0$66'.
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:19$63'.
     1/1: $1\PC_Register[31:0]
Creating decoders for process `\MUX.$proc$Risco-5/src/core/mux.v:10$62'.
     1/1: $1\S[31:0]
Creating decoders for process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$59'.
     1/1: $1\immediate[31:0]
Creating decoders for process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:0$527'.
Creating decoders for process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:46$525'.
Creating decoders for process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$515'.
     1/2: $0\clk_counter[31:0]
     2/2: $0\clk_o_auto[0:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$52'.
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50'.
     1/13: $2\alu_src_a[1:0]
     2/13: $1\pc_write[0:0]
     3/13: $1\alu_src_b[1:0]
     4/13: $1\ir_write[0:0]
     5/13: $1\memory_read[0:0]
     6/13: $1\reg_write[0:0]
     7/13: $1\alu_src_a[1:0]
     8/13: $1\aluop[1:0]
     9/13: $1\pc_source[0:0]
    10/13: $1\memory_to_reg[0:0]
    11/13: $1\memory_write[0:0]
    12/13: $1\lorD[0:0]
    13/13: $1\pc_write_cond[0:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$48'.
     1/3: $3\nextstate[3:0]
     2/3: $2\nextstate[3:0]
     3/3: $1\nextstate[3:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:64$47'.
     1/1: $0\state[3:0]
Creating decoders for process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:8$45'.
     1/4: $4\aluop_out[3:0]
     2/4: $3\aluop_out[3:0]
     3/4: $2\aluop_out[3:0]
     4/4: $1\aluop_out[3:0]
Creating decoders for process `\ALU.$proc$Risco-5/src/core/alu.v:11$30'.
     1/1: $1\ALU_out_S[31:0]
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:0$510'.
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$504'.
     1/3: $0\counter[5:0]
     2/3: $0\state[1:0]
     3/3: $0\reset_o[0:0]

21.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\n_fsm_state' from process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$617'.
No latch inferred for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\n_fsm_state' from process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$560'.
No latch inferred for signal `\Registers.\readData1' from process `\Registers.$proc$Risco-5/src/core/registers.v:81$67'.
No latch inferred for signal `\Registers.\readData2' from process `\Registers.$proc$Risco-5/src/core/registers.v:81$67'.
No latch inferred for signal `\MUX.\S' from process `\MUX.$proc$Risco-5/src/core/mux.v:10$62'.
No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$59'.
No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50`.
No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50`.
No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50`.
No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50`.
No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50`.
No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50`.
No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50`.
No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50`.
No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50`.
No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50`.
No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50`.
No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50`.
Latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$48': $auto$proc_dlatch.cc:427:proc_dlatch$2149
Latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:8$45': $auto$proc_dlatch.cc:427:proc_dlatch$2220
No latch inferred for signal `\ALU.\ALU_out_S' from process `\ALU.$proc$Risco-5/src/core/alu.v:11$30'.

21.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$501'.
  created $dff cell `$procdff$2243' with positive edge clock.
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$476'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$437_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$476'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$438_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$476'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$439_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$476'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$440_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$476'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$441_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$476'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$442_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$476'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$443_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$476'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$444_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$476'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$445_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$476'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$446_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$476'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$447_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$476'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$448_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$476'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$449_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$476'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$450_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$476'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$451_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$476'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$452_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$453'.
  created $dff cell `$procdff$2244' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$452_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$453'.
  created $dff cell `$procdff$2245' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$452_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$453'.
  created $dff cell `$procdff$2246' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$419'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$377_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$419'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$378_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$419'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$379_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$419'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$380_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$419'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$381_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$419'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$382_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$419'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$383_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$419'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$384_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$419'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$385_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$419'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$386_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$419'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$387_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$419'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$388_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$419'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$389_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$419'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$390_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$419'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$391_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$419'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$392_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$419'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$393_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$395'.
  created $dff cell `$procdff$2247' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$393_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$395'.
  created $dff cell `$procdff$2248' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$393_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$395'.
  created $dff cell `$procdff$2249' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$394'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\rxd_reg' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$646'.
  created $dff cell `$procdff$2250' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\rxd_reg_0' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$646'.
  created $dff cell `$procdff$2251' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\fsm_state' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$644'.
  created $dff cell `$procdff$2252' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\cycle_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$636'.
  created $dff cell `$procdff$2253' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\bit_sample' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$633'.
  created $dff cell `$procdff$2254' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\bit_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$627'.
  created $dff cell `$procdff$2255' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\i' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$622'.
  created $dff cell `$procdff$2256' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\recieved_data' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$622'.
  created $dff cell `$procdff$2257' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\uart_rx_data' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$608'.
  created $dff cell `$procdff$2258' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\txd_reg' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$595'.
  created $dff cell `$procdff$2259' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\fsm_state' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$593'.
  created $dff cell `$procdff$2260' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\cycle_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$585'.
  created $dff cell `$procdff$2261' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\bit_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$571'.
  created $dff cell `$procdff$2262' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\i' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$565'.
  created $dff cell `$procdff$2263' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\data_to_send' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$565'.
  created $dff cell `$procdff$2264' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$550'.
  created $dff cell `$procdff$2265' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$550'.
  created $dff cell `$procdff$2266' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$550'.
  created $dff cell `$procdff$2267' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$550'.
  created $dff cell `$procdff$2268' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$550'.
  created $dff cell `$procdff$2269' with positive edge clock.
Creating register for signal `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_ADDR' using process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$653'.
  created $dff cell `$procdff$2270' with positive edge clock.
Creating register for signal `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_DATA' using process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$653'.
  created $dff cell `$procdff$2271' with positive edge clock.
Creating register for signal `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN' using process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$653'.
  created $dff cell `$procdff$2272' with positive edge clock.
Creating register for signal `\LEDs.\data' using process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$162'.
  created $dff cell `$procdff$2273' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101.\gpio_direction' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101.$proc$Risco-5/src/peripheral/gpios.v:29$531'.
  created $dff cell `$procdff$2274' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101.\gpio_value' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101.$proc$Risco-5/src/peripheral/gpios.v:29$531'.
  created $dff cell `$procdff$2275' with positive edge clock.
Creating register for signal `\Registers.\register0' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2276' with positive edge clock.
Creating register for signal `\Registers.\register1' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2277' with positive edge clock.
Creating register for signal `\Registers.\register2' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2278' with positive edge clock.
Creating register for signal `\Registers.\register3' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2279' with positive edge clock.
Creating register for signal `\Registers.\register4' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2280' with positive edge clock.
Creating register for signal `\Registers.\register5' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2281' with positive edge clock.
Creating register for signal `\Registers.\register6' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2282' with positive edge clock.
Creating register for signal `\Registers.\register7' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2283' with positive edge clock.
Creating register for signal `\Registers.\register8' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2284' with positive edge clock.
Creating register for signal `\Registers.\register9' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2285' with positive edge clock.
Creating register for signal `\Registers.\register10' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2286' with positive edge clock.
Creating register for signal `\Registers.\register11' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2287' with positive edge clock.
Creating register for signal `\Registers.\register12' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2288' with positive edge clock.
Creating register for signal `\Registers.\register13' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2289' with positive edge clock.
Creating register for signal `\Registers.\register14' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2290' with positive edge clock.
Creating register for signal `\Registers.\register15' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2291' with positive edge clock.
Creating register for signal `\Registers.\register16' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2292' with positive edge clock.
Creating register for signal `\Registers.\register17' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2293' with positive edge clock.
Creating register for signal `\Registers.\register18' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2294' with positive edge clock.
Creating register for signal `\Registers.\register19' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2295' with positive edge clock.
Creating register for signal `\Registers.\register20' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2296' with positive edge clock.
Creating register for signal `\Registers.\register21' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2297' with positive edge clock.
Creating register for signal `\Registers.\register22' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2298' with positive edge clock.
Creating register for signal `\Registers.\register23' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2299' with positive edge clock.
Creating register for signal `\Registers.\register24' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2300' with positive edge clock.
Creating register for signal `\Registers.\register25' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2301' with positive edge clock.
Creating register for signal `\Registers.\register26' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2302' with positive edge clock.
Creating register for signal `\Registers.\register27' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2303' with positive edge clock.
Creating register for signal `\Registers.\register28' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2304' with positive edge clock.
Creating register for signal `\Registers.\register29' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2305' with positive edge clock.
Creating register for signal `\Registers.\register30' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2306' with positive edge clock.
Creating register for signal `\Registers.\register31' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
  created $dff cell `$procdff$2307' with positive edge clock.
Creating register for signal `\PC.\PC_Register' using process `\PC.$proc$Risco-5/src/core/pc.v:19$63'.
  created $dff cell `$procdff$2308' with positive edge clock.
Creating register for signal `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.\clk_o_pulse' using process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:46$525'.
  created $dff cell `$procdff$2309' with positive edge clock.
Creating register for signal `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.\clk_o_auto' using process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$515'.
  created $dff cell `$procdff$2310' with positive edge clock.
Creating register for signal `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.\clk_counter' using process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$515'.
  created $dff cell `$procdff$2311' with positive edge clock.
Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:64$47'.
  created $dff cell `$procdff$2312' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$504'.
  created $dff cell `$procdff$2313' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$504'.
  created $dff cell `$procdff$2314' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$504'.
  created $dff cell `$procdff$2315' with positive edge clock.

21.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$502'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$501'.
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$501'.
Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$476'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$453'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$419'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$395'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$394'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$648'.
Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$646'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$646'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$644'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$644'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$636'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$636'.
Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$633'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$633'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$627'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$627'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$622'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$622'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$617'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$617'.
Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$608'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$608'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$601'.
Found and cleaned up 5 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$595'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$595'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$593'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$593'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$585'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$585'.
Found and cleaned up 5 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$571'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$571'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$565'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$565'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$560'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$560'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$553'.
Found and cleaned up 2 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$550'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$550'.
Found and cleaned up 1 empty switch in `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$653'.
Removing empty process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$653'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:0$165'.
Found and cleaned up 2 empty switches in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$162'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:23$162'.
Found and cleaned up 3 empty switches in `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101.$proc$Risco-5/src/peripheral/gpios.v:29$531'.
Removing empty process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101.$proc$Risco-5/src/peripheral/gpios.v:29$531'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:0$71'.
Found and cleaned up 3 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:155$68'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:155$68'.
Found and cleaned up 2 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:81$67'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:81$67'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:0$66'.
Found and cleaned up 2 empty switches in `\PC.$proc$Risco-5/src/core/pc.v:19$63'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:19$63'.
Found and cleaned up 1 empty switch in `\MUX.$proc$Risco-5/src/core/mux.v:10$62'.
Removing empty process `MUX.$proc$Risco-5/src/core/mux.v:10$62'.
Found and cleaned up 1 empty switch in `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$59'.
Removing empty process `Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$59'.
Removing empty process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:0$527'.
Removing empty process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:46$525'.
Found and cleaned up 4 empty switches in `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$515'.
Removing empty process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$515'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$52'.
Found and cleaned up 2 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:109$50'.
Found and cleaned up 3 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$48'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$48'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:64$47'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:64$47'.
Found and cleaned up 4 empty switches in `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:8$45'.
Removing empty process `ALU_Control.$proc$Risco-5/src/core/alu_control.v:8$45'.
Found and cleaned up 1 empty switch in `\ALU.$proc$Risco-5/src/core/alu.v:11$30'.
Removing empty process `ALU.$proc$Risco-5/src/core/alu.v:11$30'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:0$510'.
Found and cleaned up 5 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$504'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$504'.
Cleaned up 76 empty switches.

21.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
<suppressed ~21 debug messages>
Optimizing module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
<suppressed ~19 debug messages>
Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
<suppressed ~2 debug messages>
Optimizing module $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.
<suppressed ~2 debug messages>
Optimizing module $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.
Optimizing module LEDs.
<suppressed ~3 debug messages>
Optimizing module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101.
<suppressed ~4 debug messages>
Optimizing module GPIO.
<suppressed ~3 debug messages>
Optimizing module BUS.
Optimizing module Registers.
<suppressed ~4 debug messages>
Optimizing module PC.
<suppressed ~2 debug messages>
Optimizing module MUX.
<suppressed ~1 debug messages>
Optimizing module Immediate_Generator.
Optimizing module $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.
<suppressed ~5 debug messages>
Optimizing module Control_Unit.
<suppressed ~23 debug messages>
Optimizing module ALU_Control.
<suppressed ~13 debug messages>
Optimizing module ALU.
<suppressed ~1 debug messages>
Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~7 debug messages>
Optimizing module $paramod$e03256ea8e7445dc30f095427a7bac59d40d5a9f\Risco_5_SOC.
Optimizing module top.

21.5. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Deleting now unused module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Deleting now unused module $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.
Deleting now unused module $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.
Deleting now unused module LEDs.
Deleting now unused module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101.
Deleting now unused module GPIO.
Deleting now unused module BUS.
Deleting now unused module Registers.
Deleting now unused module PC.
Deleting now unused module MUX.
Deleting now unused module Immediate_Generator.
Deleting now unused module $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.
Deleting now unused module Control_Unit.
Deleting now unused module ALU_Control.
Deleting now unused module ALU.
Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Deleting now unused module $paramod$e03256ea8e7445dc30f095427a7bac59d40d5a9f\Risco_5_SOC.
<suppressed ~27 debug messages>

21.6. Executing TRIBUF pass.

21.7. Executing DEMINOUT pass (demote inout ports to input or output).

21.8. Executing OPT_EXPR pass (perform const folding).
[Pipeline] // stage
[Pipeline] }
Optimizing module top.
<suppressed ~52 debug messages>

21.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 134 unused cells and 680 unused wires.
<suppressed ~173 debug messages>

21.10. Executing CHECK pass (checking for obvious problems).
Checking module top...
Warning: Wire top.\SOC.Core.PCSourceMUX.C [31] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [30] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [29] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [28] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [27] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [26] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [25] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [24] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [23] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [22] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [21] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [20] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [19] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [18] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [17] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [16] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [15] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [14] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [13] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [12] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [11] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [10] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [9] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [8] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [7] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [6] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [5] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [4] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [3] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [2] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [1] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [0] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [31] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [30] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [29] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [28] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [27] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [26] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [25] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [24] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [23] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [22] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [21] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [20] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [19] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [18] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [17] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [16] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [15] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [14] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [13] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [12] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [11] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [10] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [9] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [8] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [7] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [6] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [5] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [4] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [3] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [2] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [1] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [0] is used but has no driver.
Found and reported 256 problems.

21.11. Executing OPT pass (performing simple optimizations).

21.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~9 debug messages>

21.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~396 debug messages>
Removed a total of 132 cells.

21.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1874.
    dead port 1/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1822.
    dead port 2/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1822.
    dead port 1/5 on $pmux $flatten\SOC.\Core.\MemoryDataMUX.$procmux$1822.
    dead port 2/5 on $pmux $flatten\SOC.\Core.\MemoryDataMUX.$procmux$1822.
    dead port 1/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1822.
    dead port 2/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1822.
Removed 7 multiplexer ports.
<suppressed ~94 debug messages>

21.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2094: { $flatten\SOC.\Core.\ALU_Control.$procmux$2096_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2095_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1879: $auto$opt_reduce.cc:134:opt_pmux$2328
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1884: { $auto$opt_reduce.cc:134:opt_pmux$2332 $auto$opt_reduce.cc:134:opt_pmux$2330 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1920: $auto$opt_reduce.cc:134:opt_pmux$2334
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1930: $auto$opt_reduce.cc:134:opt_pmux$2336
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1934: { $flatten\SOC.\Core.\Control_Unit.$procmux$1875_CMP $auto$opt_reduce.cc:134:opt_pmux$2338 $flatten\SOC.\Core.\Control_Unit.$procmux$1885_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1945: { $auto$opt_reduce.cc:134:opt_pmux$2340 $flatten\SOC.\Core.\Control_Unit.$procmux$1936_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1952: $auto$opt_reduce.cc:134:opt_pmux$2342
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1988: $auto$opt_reduce.cc:134:opt_pmux$2344
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2028: { $flatten\SOC.\Core.\Control_Unit.$procmux$2035_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2034_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2033_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2032_CMP $flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:131$51_Y $flatten\SOC.\Core.\Control_Unit.$procmux$2030_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2029_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2041: { $flatten\SOC.\Core.\Control_Unit.$procmux$1882_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1875_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1890_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1921_CMP $auto$opt_reduce.cc:134:opt_pmux$2346 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1828: { $flatten\SOC.\Core.\Control_Unit.$procmux$2032_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2033_CMP $auto$opt_reduce.cc:134:opt_pmux$2350 $flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:89$49_Y $auto$opt_reduce.cc:134:opt_pmux$2348 $flatten\SOC.\Core.\Control_Unit.$procmux$2036_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1714: $auto$opt_reduce.cc:134:opt_pmux$2352
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$971:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_EN[31:0]$656 [0] }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2071: { $flatten\SOC.\Core.\ALU_Control.$procmux$2078_CMP $auto$opt_reduce.cc:134:opt_pmux$2354 $flatten\SOC.\Core.\ALU_Control.$procmux$2075_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2074_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2073_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2072_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2085: { $auto$opt_reduce.cc:134:opt_pmux$2358 $auto$opt_reduce.cc:134:opt_pmux$2356 $flatten\SOC.\Core.\ALU_Control.$procmux$2078_CMP }
  Optimizing cells in module \top.
Performed a total of 18 changes.

21.11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

21.11.6. Executing OPT_DFF pass (perform DFF optimizations).

21.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 152 unused wires.
<suppressed ~8 debug messages>

21.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.11.9. Rerunning OPT passes. (Maybe there is more to do..)

21.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~94 debug messages>

21.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.11.13. Executing OPT_DFF pass (perform DFF optimizations).

21.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.11.16. Finished OPT passes. (There is nothing left to do.)

21.12. Executing FSM pass (extract and optimize FSM).

21.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking top.ResetBootSystem.state as FSM state register:
    Register has an initialization value.
    Circuit seems to be self-resetting.
Not marking top.SOC.Core.RegisterBank.register0 as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Found FSM state register top.SOC.Uart.i_uart_tx.fsm_state.

21.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\SOC.Uart.i_uart_tx.fsm_state' from module `\top'.
  found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_tx.$procdff$2260
  root of input selection tree: $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$579_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$569_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$587_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$567_Y
  found state code: 3'000
  found ctrl input: \SOC.Uart.i_uart_tx.stop_done
  found state code: 3'011
  found ctrl input: \SOC.Uart.i_uart_tx.payload_done
  found state code: 3'010
  found ctrl input: \SOC.Uart.i_uart_tx.next_bit
  found state code: 3'001
  found ctrl input: \SOC.Uart.i_uart_tx.uart_tx_en
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$587_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$579_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$574_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$573_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$569_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$567_Y
  ctrl inputs: { \SOC.Uart.i_uart_tx.uart_tx_en \SOC.Uart.i_uart_tx.next_bit \SOC.Uart.i_uart_tx.payload_done \SOC.Uart.i_uart_tx.stop_done \ResetBootSystem.reset_o }
  ctrl outputs: { $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$567_Y $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$569_Y $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$573_Y $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$574_Y $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$579_Y $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$587_Y $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] }
  transition:      3'000 5'0---0 ->      3'000 9'101100000
  transition:      3'000 5'1---0 ->      3'001 9'101100001
  transition:      3'000 5'----1 ->      3'000 9'101100000
  transition:      3'010 5'--0-0 ->      3'010 9'010100010
  transition:      3'010 5'--1-0 ->      3'011 9'010100011
  transition:      3'010 5'----1 ->      3'000 9'010100000
  transition:      3'001 5'-0--0 ->      3'001 9'001101001
  transition:      3'001 5'-1--0 ->      3'010 9'001101010
  transition:      3'001 5'----1 ->      3'000 9'001101000
  transition:      3'011 5'---00 ->      3'011 9'001010011
  transition:      3'011 5'---10 ->      3'000 9'001010000
  transition:      3'011 5'----1 ->      3'000 9'001010000

21.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2359' from module `\top'.

21.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 8 unused cells and 8 unused wires.
<suppressed ~9 debug messages>

21.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2359' from module `\top'.
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] [2].

21.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2359' from module `\top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---

21.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2359' from module `top':
-------------------------------------

  Information on FSM $fsm$\SOC.Uart.i_uart_tx.fsm_state$2359 (\SOC.Uart.i_uart_tx.fsm_state):

  Number of input signals:    5
  Number of output signals:   6
  Number of state bits:       4

  Input signals:
    0: \ResetBootSystem.reset_o
    1: \SOC.Uart.i_uart_tx.stop_done
    2: \SOC.Uart.i_uart_tx.payload_done
    3: \SOC.Uart.i_uart_tx.next_bit
    4: \SOC.Uart.i_uart_tx.uart_tx_en

  Output signals:
    0: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$587_Y
    1: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$579_Y
    2: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$574_Y
    3: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$573_Y
    4: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$569_Y
    5: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$567_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 5'0---0   ->     0 6'101100
      1:     0 5'----1   ->     0 6'101100
      2:     0 5'1---0   ->     2 6'101100
      3:     1 5'----1   ->     0 6'010100
      4:     1 5'--0-0   ->     1 6'010100
      5:     1 5'--1-0   ->     3 6'010100
      6:     2 5'----1   ->     0 6'001101
      7:     2 5'-1--0   ->     1 6'001101
      8:     2 5'-0--0   ->     2 6'001101
      9:     3 5'---10   ->     0 6'001010
     10:     3 5'----1   ->     0 6'001010
     11:     3 5'---00   ->     3 6'001010

-------------------------------------

21.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2359' from module `\top'.

21.13. Executing OPT pass (performing simple optimizations).

21.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>

21.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~93 debug messages>

21.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2264 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$933_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$927_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$918_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$909_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$900_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$891_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$873_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$882_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2411 ($sdff) from module top (D = \SOC.Bus.slave_2_write_data [7], Q = \SOC.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$2411 ($sdff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$927_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$918_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$909_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$900_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$891_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$873_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$882_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2262 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$849_Y, Q = \SOC.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$2416 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$849_Y, Q = \SOC.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2261 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$838_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter, rval = 13'0000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2422 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$592_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2259 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$827_Y, Q = \SOC.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$2426 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$827_Y, Q = \SOC.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\SOC.\Leds.$procdff$2273 ($dff) from module top (D = $flatten\SOC.\Leds.$procmux$979_Y, Q = \SOC.Leds.data, rval = 33'000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2432 ($sdff) from module top (D = { 1'0 \SOC.Leds.write_data }, Q = \SOC.Leds.data).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$2275 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$987_Y, Q = \SOC.GPIOS.gpio_value, rval = 5'00000).
Adding EN signal on $auto$ff.cc:266:slice$2434 ($sdff) from module top (D = \SOC.GPIOS.write_data [4:0], Q = \SOC.GPIOS.gpio_value).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$2274 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$995_Y, Q = \SOC.GPIOS.gpio_direction, rval = 5'00000).
Adding EN signal on $auto$ff.cc:266:slice$2438 ($sdff) from module top (D = \SOC.GPIOS.write_data [4:0], Q = \SOC.GPIOS.gpio_direction).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2307 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register31).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2306 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register30).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2305 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register29).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2304 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register28).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2303 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register27).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2302 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register26).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2301 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register25).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2300 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register24).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2299 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register23).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2298 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register22).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2297 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register21).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2296 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register20).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2295 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register19).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2294 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register18).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2293 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register17).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2292 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register16).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2291 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register15).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2290 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register14).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2289 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register13).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2288 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register12).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2287 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register11).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2286 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register10).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2285 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register9).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2284 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register8).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2283 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register7).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2282 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register6).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2281 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register5).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2280 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register4).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2279 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register3).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2278 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register2).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2277 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register1).
Adding SRST signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2276 ($dff) from module top (D = $flatten\SOC.\Core.\RegisterBank.$procmux$1746_Y, Q = \SOC.Core.RegisterBank.register0, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2599 ($sdff) from module top (D = 0, Q = \SOC.Core.RegisterBank.register0).
Adding SRST signal on $flatten\SOC.\Core.\Pc.$procdff$2308 ($dff) from module top (D = $flatten\SOC.\Core.\Pc.$procmux$1817_Y, Q = \SOC.Core.Pc.PC_Register, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2605 ($sdff) from module top (D = \SOC.Core.Pc.Input, Q = \SOC.Core.Pc.PC_Register).
Adding SRST signal on $flatten\SOC.\Core.\Control_Unit.$procdff$2312 ($dff) from module top (D = \SOC.Core.Control_Unit.nextstate, Q = \SOC.Core.Control_Unit.state, rval = 4'0000).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2269 ($dff) from module top (D = \SOC.Bus.write_data, Q = \SOC.Core.register_data_2, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2268 ($dff) from module top (D = \SOC.Core.register_data_1_out, Q = \SOC.Core.register_data_1, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2267 ($dff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.alu_out_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2266 ($dff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.memory_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2265 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$965_Y, Q = \SOC.Core.instruction_register, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2612 ($sdff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.instruction_register).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2315 ($dff) from module top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2314 ($dff) from module top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2313 ($dff) from module top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Adding SRST signal on $flatten\ClkDivider.$procdff$2311 ($dff) from module top (D = $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:32$518_Y, Q = \ClkDivider.clk_counter, rval = 0).
Adding SRST signal on $flatten\ClkDivider.$procdff$2310 ($dff) from module top (D = $flatten\ClkDivider.$procmux$1853_Y, Q = \ClkDivider.clk_o_auto, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2640 ($sdff) from module top (D = $flatten\ClkDivider.$procmux$1853_Y, Q = \ClkDivider.clk_o_auto).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$2600 ($sdffe) from module top.
Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$2433 ($sdffe) from module top.

21.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 136 unused cells and 137 unused wires.
<suppressed ~137 debug messages>

21.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~6 debug messages>

21.13.9. Rerunning OPT passes. (Maybe there is more to do..)

21.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~51 debug messages>

21.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~93 debug messages>
Removed a total of 31 cells.

21.13.13. Executing OPT_DFF pass (perform DFF optimizations).

21.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 31 unused wires.
<suppressed ~1 debug messages>

21.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.13.16. Rerunning OPT passes. (Maybe there is more to do..)

21.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~51 debug messages>

21.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.13.20. Executing OPT_DFF pass (perform DFF optimizations).

21.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.13.23. Finished OPT passes. (There is nothing left to do.)

21.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 22 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2316 (SOC.Memory.memory).
Removed top 22 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$meminit$\memory$Risco-5/src/peripheral/memory.v:0$661 (SOC.Memory.memory).
Removed top 22 address bits (of 32) from memory read port top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:17$651 (SOC.Memory.memory).
Removed top 9 bits (of 32) from port B of cell top.$flatten\ClkDivider.$ge$Risco-5/debug/clk_divider.v:40$524 ($ge).
Removed top 31 bits (of 32) from port B of cell top.$flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:37$522 ($add).
Removed top 10 bits (of 32) from port B of cell top.$flatten\ClkDivider.$eq$Risco-5/debug/clk_divider.v:33$520 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\ResetBootSystem.$procmux$2123_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\ResetBootSystem.$eq$Risco-5/fpga/ecp5/reset.v:38$508 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$507 ($add).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$507 ($add).
Removed top 27 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$lt$Risco-5/fpga/ecp5/reset.v:36$506 ($lt).
Removed top 27 bits (of 32) from mux cell top.$flatten\SOC.\GPIOS.$ternary$Risco-5/src/peripheral/gpios.v:20$530 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:135$577 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$564 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$563 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$562 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$561 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:94$557 ($eq).
Removed top 1 bits (of 13) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:92$555 ($eq).
Removed top 1 bits (of 33) from mux cell top.$flatten\SOC.\Leds.$ternary$Risco-5/src/peripheral/leds.v:21$161 ($mux).
Removed top 2 bits (of 8) from port Y of cell top.$flatten\SOC.\Leds.$not$Risco-5/src/peripheral/leds.v:31$164 ($not).
Removed top 2 bits (of 8) from port A of cell top.$flatten\SOC.\Leds.$not$Risco-5/src/peripheral/leds.v:31$164 ($not).
Removed top 20 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$73 ($le).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$76 ($ge).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$77 ($le).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$84 ($ge).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$85 ($le).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:66$96 ($ge).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:67$97 ($le).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:75$115 ($mux).
Removed top 22 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$977 ($mux).
Removed top 5 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:89$49 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$eq$Risco-5/src/core/alu_control.v:34$46 ($eq).
Removed top 29 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$60 ($sub).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1825_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1825_CMP0 ($eq).
Removed top 4 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1815_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1814_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1813_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1812_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1811_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1810_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1809_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1808_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1807_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1806_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1805_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1804_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1803_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1802_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1801_CMP0 ($eq).
Removed top 4 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1782_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1781_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1780_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1779_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1778_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1777_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1776_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1775_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1774_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1773_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1772_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1771_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1770_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1769_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1768_CMP0 ($eq).
Removed top 4 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1707_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1669_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1632_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1596_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1561_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1527_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1494_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1462_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1431_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1401_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1372_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1344_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1317_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1291_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1266_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2620 ($ne).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2625 ($ne).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2036_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2035_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2034_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2030_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2029_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2010 ($mux).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1978_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1938_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1932_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1931_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1921_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1890_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1875_CMP0 ($eq).
Removed top 1 bits (of 2) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1872 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2096_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2078_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2077_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2076_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2064 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2109_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2108_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2107_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2106_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$44 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:22$36 ($mux).
Removed top 29 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$61 ($sub).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$72 ($ge).
Removed top 20 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:80$123 ($mux).
Removed top 26 bits (of 32) from wire top.$flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$507_Y.
Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\ALU_Control.$4\aluop_out[3:0].
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:32$42_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:22$36_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$44_Y.
Removed top 1 bits (of 2) from wire top.$flatten\SOC.\Core.\Control_Unit.$2\alu_src_a[1:0].
Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\Control_Unit.$3\nextstate[3:0].
Removed top 22 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$649_ADDR[31:0]$654.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$561_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$562_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$563_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$564_Y.
Removed top 2 bits (of 8) from wire top.leds.

21.15. Executing PEEPOPT pass (run peephole optimizers).

21.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 14 unused wires.
<suppressed ~1 debug messages>

21.17. Executing SHARE pass (SAT-based resource sharing).
Found 3 cells in module top that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:17$651 ($memrd):
    Found 1 activation_patterns using ctrl signal { $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:53$74_Y \SOC.Bus.slave_0_read }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shr$Risco-5/src/core/alu.v:28$40 ($shr):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$2103_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shl$Risco-5/src/core/alu.v:26$39 ($shl):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$2104_CMP.
    No candidates found.

21.18. Executing TECHMAP pass (map to technology primitives).

21.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

21.18.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~322 debug messages>

21.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.21. Executing TECHMAP pass (map to technology primitives).

21.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

21.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.

21.21.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>

21.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
  creating $macc model for $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:37$522 ($add).
  creating $macc model for $flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$507 ($add).
  creating $macc model for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:18$33 ($add).
  creating $macc model for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34 ($sub).
  creating $macc model for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$60 ($sub).
  creating $macc model for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$61 ($sub).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$581 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$592 ($add).
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$592.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$581.
  creating $alu model for $macc $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$61.
  creating $alu model for $macc $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$60.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:18$33.
  creating $alu model for $macc $flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$507.
  creating $alu model for $macc $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:37$522.
  creating $alu model for $flatten\ClkDivider.$ge$Risco-5/debug/clk_divider.v:40$524 ($ge): new $alu
  creating $alu model for $flatten\ResetBootSystem.$lt$Risco-5/fpga/ecp5/reset.v:36$506 ($lt): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$72 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$76 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$84 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:66$96 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$73 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$77 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$85 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:67$97 ($le): new $alu
  creating $alu model for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:34$43 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:22$35 ($lt): merged with $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:34$43.
  creating $alu model for $flatten\ResetBootSystem.$eq$Risco-5/fpga/ecp5/reset.v:38$508 ($eq): merged with $flatten\ResetBootSystem.$lt$Risco-5/fpga/ecp5/reset.v:36$506.
  creating $alu model for $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:32$42 ($eq): merged with $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:34$43.
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:67$97: $auto$alumacc.cc:485:replace_alu$2670
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$85: $auto$alumacc.cc:485:replace_alu$2683
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$77: $auto$alumacc.cc:485:replace_alu$2696
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$73: $auto$alumacc.cc:485:replace_alu$2709
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:66$96: $auto$alumacc.cc:485:replace_alu$2722
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$84: $auto$alumacc.cc:485:replace_alu$2731
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$76: $auto$alumacc.cc:485:replace_alu$2740
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$72: $auto$alumacc.cc:485:replace_alu$2749
  creating $alu cell for $flatten\ResetBootSystem.$lt$Risco-5/fpga/ecp5/reset.v:36$506, $flatten\ResetBootSystem.$eq$Risco-5/fpga/ecp5/reset.v:38$508: $auto$alumacc.cc:485:replace_alu$2758
  creating $alu cell for $flatten\ClkDivider.$ge$Risco-5/debug/clk_divider.v:40$524: $auto$alumacc.cc:485:replace_alu$2769
  creating $alu cell for $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:37$522: $auto$alumacc.cc:485:replace_alu$2778
  creating $alu cell for $flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$507: $auto$alumacc.cc:485:replace_alu$2781
  creating $alu cell for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:34$43, $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:22$35, $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:32$42: $auto$alumacc.cc:485:replace_alu$2784
  creating $alu cell for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:18$33: $auto$alumacc.cc:485:replace_alu$2797
  creating $alu cell for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34: $auto$alumacc.cc:485:replace_alu$2800
  creating $alu cell for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$60: $auto$alumacc.cc:485:replace_alu$2803
  creating $alu cell for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$61: $auto$alumacc.cc:485:replace_alu$2806
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$581: $auto$alumacc.cc:485:replace_alu$2809
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$592: $auto$alumacc.cc:485:replace_alu$2812
  created 19 $alu and 0 $macc cells.

21.23. Executing OPT pass (performing simple optimizations).

21.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3 debug messages>

21.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~51 debug messages>

21.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$2639: { $auto$rtlil.cc:2464:ReduceAnd$2775 $auto$rtlil.cc:2461:Not$2773 \reset }
  Optimizing cells in module \top.
Performed a total of 1 changes.

21.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.23.6. Executing OPT_DFF pass (perform DFF optimizations).

21.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 2 unused cells and 16 unused wires.
<suppressed ~3 debug messages>

21.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.23.9. Rerunning OPT passes. (Maybe there is more to do..)

21.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~51 debug messages>

21.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.23.13. Executing OPT_DFF pass (perform DFF optimizations).

21.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.23.16. Finished OPT passes. (There is nothing left to do.)

21.24. Executing MEMORY pass.

21.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

21.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

21.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing top.SOC.Memory.memory write port 0.

21.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

21.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\SOC.Memory.memory'[0] in module `\top': no output FF found.
Checking read port address `\SOC.Memory.memory'[0] in module `\top': no address FF found.

21.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

21.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

21.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).

21.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory top.SOC.Memory.memory via $__TRELLIS_DPR16X4_
<suppressed ~68 debug messages>

21.27. Executing TECHMAP pass (map to technology primitives).

21.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

21.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.

21.27.3. Continuing TECHMAP pass.
Using template $paramod$0eb199c7b2cea9c358f23ffe94c4548bdd802747\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$b089c18cc881634130ec6d4716ef25d78c9d48c9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$731f2d82778baee6f78f5f3e0670a3ade61ac0d6\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$48358c22c7a8e5b48ddefb8e14a8bb1f81de841f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$5276274b86ff102139fbc8ae2dfc335d77b58a6a\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$c75b2ca41d3ff8a2b5ad26d6a6ec321bb6e56448\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$315d0c5245324146665fc1ab307bed98cfcb6adf\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$fb6ed8f936d3525780a052d218072c625795bc14\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~634 debug messages>

21.28. Executing OPT pass (performing simple optimizations).

21.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~109 debug messages>

21.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~12 debug messages>
Removed a total of 4 cells.

21.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$2614 ($dffe) from module top (D = $flatten\ResetBootSystem.$procmux$2120_Y, Q = \ResetBootSystem.counter, rval = 6'000000).

21.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 26 unused cells and 3648 unused wires.
<suppressed ~27 debug messages>

21.28.5. Rerunning OPT passes. (Removed registers in this run.)

21.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3 debug messages>

21.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$4086 ($sdffce) from module top (D = $auto$wreduce.cc:461:run$2645 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).

21.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 2 unused cells and 4 unused wires.
<suppressed ~3 debug messages>

21.28.10. Rerunning OPT passes. (Removed registers in this run.)

21.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.28.13. Executing OPT_DFF pass (perform DFF optimizations).

21.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.28.15. Finished fast OPT passes.

21.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

21.30. Executing OPT pass (performing simple optimizations).

21.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~37 debug messages>

21.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2129: { $flatten\ResetBootSystem.$procmux$2124_CMP $flatten\ResetBootSystem.$procmux$2123_CMP }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2132:
      Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2132_Y
      New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2132_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2132_Y [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2064:
      Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$2646 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$2646 [2]
      New connections: $auto$wreduce.cc:461:run$2646 [1:0] = 2'10
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2085:
      Old ports: A=4'0110, B=12'101101111110, Y=$flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0]
      New ports: A=3'010, B=9'101011110, Y={ $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [3:2] $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [0] }
      New connections: $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [1] = 1'1
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2010:
      Old ports: A=3'101, B=3'011, Y=$auto$wreduce.cc:461:run$2651 [2:0]
      New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$2651 [2:1]
      New connections: $auto$wreduce.cc:461:run$2651 [0] = 1'1
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_tx.$procmux$948:
      Old ports: A=3'000, B={ 2'00 \SOC.Uart.i_uart_tx.uart_tx_en 1'0 $auto$wreduce.cc:461:run$2654 [1:0] 2'01 \SOC.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$2656 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state
      New ports: A=2'00, B={ 1'0 \SOC.Uart.i_uart_tx.uart_tx_en $auto$wreduce.cc:461:run$2654 [1:0] 1'1 \SOC.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$2656 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state [1:0]
      New connections: \SOC.Uart.i_uart_tx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$564:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$2656 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$2656 [0]
      New connections: $auto$wreduce.cc:461:run$2656 [1] = $auto$wreduce.cc:461:run$2656 [0]
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2138:
      Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2132_Y, Y=$flatten\ResetBootSystem.$procmux$2138_Y
      New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2132_Y [1], Y=$flatten\ResetBootSystem.$procmux$2138_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2138_Y [0] = 1'0
  Optimizing cells in module \top.
Performed a total of 8 changes.

21.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.30.6. Executing OPT_DFF pass (perform DFF optimizations).

21.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.30.9. Rerunning OPT passes. (Maybe there is more to do..)

21.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~37 debug messages>

21.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.30.13. Executing OPT_DFF pass (perform DFF optimizations).

21.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.30.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.30.16. Finished OPT passes. (There is nothing left to do.)

21.31. Executing TECHMAP pass (map to technology primitives).

21.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

21.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.

21.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $reduce_and.
Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $mux.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $reduce_bool.
Using template $paramod$b469e176aa82369781227d524b4fecc3cede3e1d\_80_ecp5_alu for cells of type $alu.
Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux.
Using template $paramod$861f5302217787cd55fd1a501bc728125f176580\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c96def1cdcef2eee3c62e5dfb7ba2dd09c9f74dd\_90_pmux for cells of type $pmux.
Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu.
Using template $paramod$3111a1a8e90c88cc8c163ba5aed0203d96ddc46d\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $bmux.
Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_demux for cells of type $demux.
Using extmapper simplemap for cells of type $tribuf.
Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$215440792383f7884e57d9c95f84e9552d0bf4ac\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$41ef080258eed1ff8fcfbb7776f540ab469a3d7b\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c4ef20b21801b37ea2d65c32a05dfe56e84a870d\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $sdffce.
Using template $paramod$c83925f608704c3fa34790ddcfce9302bdcd7533\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $ne.
Using template $paramod$33afdd83bf3811dac2de7a968d39eea5718691bc\_90_pmux for cells of type $pmux.
Using template $paramod$95ab7b964273918a033d1324366ecc612d202989\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $dlatch.
Using template $paramod$97565c3687be688407d1272a293bd9d0ae6852dc\_90_pmux for cells of type $pmux.
Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux.
Using template $paramod$a13703aa027da371a1931fc542d213d7de559b19\_90_pmux for cells of type $pmux.
Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$56955d0f36f77738c952d3505dc563df3ee11b94\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$dce7c1188cb25d2520d170426d59301c3b73f9e7\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod$a5f0941832cc861549e29ccafffe20bfdf2e5528\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu.
Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux.
Using template $paramod$5d1d2614b24accd0f9d06c4779fd9ef771faf494\_90_demux for cells of type $demux.
No more expansions possible.
<suppressed ~3714 debug messages>

21.32. Executing OPT pass (performing simple optimizations).

21.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~6191 debug messages>

21.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~3864 debug messages>
Removed a total of 1288 cells.

21.32.3. Executing OPT_DFF pass (perform DFF optimizations).

21.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 454 unused cells and 3675 unused wires.
<suppressed ~455 debug messages>

21.32.5. Finished fast OPT passes.

21.33. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

21.35. Executing TECHMAP pass (map to technology primitives).

21.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

21.35.2. Continuing TECHMAP pass.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
No more expansions possible.
<suppressed ~1406 debug messages>

21.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~28 debug messages>

21.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).

21.38. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in top.

21.39. Executing ATTRMVCP pass (move or copy attributes).

21.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 6645 unused wires.
<suppressed ~1 debug messages>

21.41. Executing TECHMAP pass (map to technology primitives).

21.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

21.41.2. Continuing TECHMAP pass.

21.41.3. Executing SIMPLEMAP pass (map simple cells to gate primitives).
Mapping \$_DLATCH_N_.$ternary$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$28217 ($mux).
Mapping \$_DLATCH_N_.$logic_not$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$28216 ($logic_not).
<suppressed ~4 debug messages>

21.41.4. Executing OPT pass (performing simple optimizations).

21.41.4.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.
<suppressed ~1 debug messages>

21.41.4.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

21.41.4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.41.4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

21.41.4.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

21.41.4.6. Executing OPT_DFF pass (perform DFF optimizations).

21.41.4.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..
Removed 1 unused cells and 2 unused wires.
<suppressed ~2 debug messages>

21.41.4.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

21.41.4.9. Rerunning OPT passes. (Maybe there is more to do..)

21.41.4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.41.4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

21.41.4.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

21.41.4.13. Executing OPT_DFF pass (perform DFF optimizations).

21.41.4.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..

21.41.4.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

21.41.4.16. Finished OPT passes. (There is nothing left to do.)
Using template \$_DLATCH_N_ for cells of type $_DLATCH_N_.
No more expansions possible.
<suppressed ~8 debug messages>

21.42. Executing ABC9 pass.

21.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.3. Executing PROC pass (convert processes to netlists).

21.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28312'.
Cleaned up 1 empty switch.

21.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28313 in module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.3.4. Executing PROC_INIT pass (extract init attributes).

21.42.3.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28337'.
Creating decoders for process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28313'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28311_EN[3:0]$28319
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28311_DATA[3:0]$28318
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28311_ADDR[3:0]$28317
Creating decoders for process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28312'.

21.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.\i' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28337'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28305_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28337'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28299_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28337'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28295_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28337'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28296_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28337'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28300_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28337'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28301_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28337'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28302_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28337'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28306_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28337'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28307_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28337'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28297_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28337'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28308_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28337'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28298_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28337'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28303_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28337'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28304_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28337'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28309_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28337'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28310_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28337'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28311_ADDR' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28313'.
  created $dff cell `$procdff$28363' with positive edge clock.
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28311_DATA' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28313'.
  created $dff cell `$procdff$28364' with positive edge clock.
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28311_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28313'.
  created $dff cell `$procdff$28365' with positive edge clock.
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.\muxwre' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28312'.
  created direct connection (no actual register cell created).

21.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28337'.
Found and cleaned up 1 empty switch in `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28313'.
Removing empty process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28312'.
Cleaned up 1 empty switch.

21.42.3.12. Executing OPT_EXPR pass (perform const folding).

21.42.4. Executing PROC pass (convert processes to netlists).

21.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28383'.
Cleaned up 1 empty switch.

21.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28384 in module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.4.4. Executing PROC_INIT pass (extract init attributes).

21.42.4.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28408'.
Creating decoders for process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28384'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28382_EN[3:0]$28389
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28382_DATA[3:0]$28388
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28382_ADDR[3:0]$28390
Creating decoders for process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28383'.

21.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.\i' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28408'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28378_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28408'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28373_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28408'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28368_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28408'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28366_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28408'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28369_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28408'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28370_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28408'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28374_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28408'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28375_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28408'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28379_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28408'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28371_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28408'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28380_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28408'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28367_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28408'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28376_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28408'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28372_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28408'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28381_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28408'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28377_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28408'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28382_DATA' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28384'.
  created $dff cell `$procdff$28434' with positive edge clock.
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28382_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28384'.
  created $dff cell `$procdff$28435' with positive edge clock.
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28382_ADDR' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28384'.
  created $dff cell `$procdff$28436' with positive edge clock.
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28383'.
  created direct connection (no actual register cell created).

21.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28408'.
Found and cleaned up 1 empty switch in `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28384'.
Removing empty process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28383'.
Cleaned up 1 empty switch.

21.42.4.12. Executing OPT_EXPR pass (perform const folding).

21.42.5. Executing PROC pass (convert processes to netlists).

21.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28454'.
Cleaned up 1 empty switch.

21.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28455 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.5.4. Executing PROC_INIT pass (extract init attributes).

21.42.5.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.5.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28479'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28455'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28453_EN[3:0]$28461
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28453_DATA[3:0]$28460
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28453_ADDR[3:0]$28459
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28454'.

21.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28479'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28451_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28479'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28446_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28479'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28441_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28479'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28437_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28479'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28438_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28479'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28442_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28479'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28443_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28479'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28447_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28479'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28439_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28479'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28448_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28479'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28452_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28479'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28444_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28479'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28440_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28479'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28449_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28479'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28445_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28479'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28450_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28479'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28453_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28455'.
  created $dff cell `$procdff$28505' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28453_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28455'.
  created $dff cell `$procdff$28506' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28453_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28455'.
  created $dff cell `$procdff$28507' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28454'.
  created direct connection (no actual register cell created).

21.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28479'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28455'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28454'.
Cleaned up 1 empty switch.

21.42.5.12. Executing OPT_EXPR pass (perform const folding).

21.42.6. Executing PROC pass (convert processes to netlists).

21.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28525'.
Cleaned up 1 empty switch.

21.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28526 in module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.6.4. Executing PROC_INIT pass (extract init attributes).

21.42.6.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.6.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28550'.
Creating decoders for process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28526'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28524_EN[3:0]$28532
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28524_DATA[3:0]$28531
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28524_ADDR[3:0]$28530
Creating decoders for process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28525'.

21.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.\i' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28550'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28519_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28550'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28514_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28550'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28509_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28550'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28508_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28550'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28510_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28550'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28511_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28550'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28515_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28550'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28516_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28550'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28520_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28550'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28512_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28550'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28521_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28550'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28517_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28550'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28513_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28550'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28522_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28550'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28518_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28550'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28523_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28550'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28524_ADDR' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28526'.
  created $dff cell `$procdff$28576' with positive edge clock.
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28524_DATA' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28526'.
  created $dff cell `$procdff$28577' with positive edge clock.
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28524_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28526'.
  created $dff cell `$procdff$28578' with positive edge clock.
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28525'.
  created direct connection (no actual register cell created).

21.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28550'.
Found and cleaned up 1 empty switch in `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28526'.
Removing empty process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28525'.
Cleaned up 1 empty switch.

21.42.6.12. Executing OPT_EXPR pass (perform const folding).

21.42.7. Executing PROC pass (convert processes to netlists).

21.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28596'.
Cleaned up 1 empty switch.

21.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28597 in module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.7.4. Executing PROC_INIT pass (extract init attributes).

21.42.7.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.7.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28621'.
Creating decoders for process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28597'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28595_EN[3:0]$28601
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28595_DATA[3:0]$28603
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28595_ADDR[3:0]$28602
Creating decoders for process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28596'.

21.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.\i' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28621'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28592_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28621'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28587_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28621'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28582_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28621'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28579_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28621'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28583_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28621'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28584_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28621'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28588_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28621'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28580_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28621'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28589_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28621'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28593_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28621'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28585_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28621'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28594_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28621'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28581_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28621'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28590_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28621'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28586_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28621'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28591_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28621'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28595_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28597'.
  created $dff cell `$procdff$28647' with positive edge clock.
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28595_ADDR' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28597'.
  created $dff cell `$procdff$28648' with positive edge clock.
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28595_DATA' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28597'.
  created $dff cell `$procdff$28649' with positive edge clock.
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.\muxwre' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28596'.
  created direct connection (no actual register cell created).

21.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28621'.
Found and cleaned up 1 empty switch in `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28597'.
Removing empty process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28596'.
Cleaned up 1 empty switch.

21.42.7.12. Executing OPT_EXPR pass (perform const folding).

21.42.8. Executing PROC pass (convert processes to netlists).

21.42.8.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28667'.
Cleaned up 1 empty switch.

21.42.8.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28668 in module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.8.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.8.4. Executing PROC_INIT pass (extract init attributes).

21.42.8.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.8.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.8.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28692'.
Creating decoders for process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28668'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28666_EN[3:0]$28674
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28666_DATA[3:0]$28673
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28666_ADDR[3:0]$28672
Creating decoders for process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28667'.

21.42.8.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.8.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.\i' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28692'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28665_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28692'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28659_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28692'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28653_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28692'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28650_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28692'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28654_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28692'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28655_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28692'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28656_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28692'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28660_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28692'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28661_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28692'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28651_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28692'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28662_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28692'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28652_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28692'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28657_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28692'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28658_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28692'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28663_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28692'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28664_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28692'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28666_ADDR' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28668'.
  created $dff cell `$procdff$28718' with positive edge clock.
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28666_DATA' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28668'.
  created $dff cell `$procdff$28719' with positive edge clock.
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28666_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28668'.
  created $dff cell `$procdff$28720' with positive edge clock.
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.\muxwre' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28667'.
  created direct connection (no actual register cell created).

21.42.8.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.8.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28692'.
Found and cleaned up 1 empty switch in `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28668'.
Removing empty process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28667'.
Cleaned up 1 empty switch.

21.42.8.12. Executing OPT_EXPR pass (perform const folding).

21.42.9. Executing PROC pass (convert processes to netlists).

21.42.9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28738'.
Cleaned up 1 empty switch.

21.42.9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28739 in module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.9.4. Executing PROC_INIT pass (extract init attributes).

21.42.9.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.9.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.9.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28763'.
Creating decoders for process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28739'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28737_EN[3:0]$28745
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28737_DATA[3:0]$28744
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28737_ADDR[3:0]$28743
Creating decoders for process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28738'.

21.42.9.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.9.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.\i' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28763'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28735_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28763'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28729_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28763'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28723_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28763'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28721_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28763'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28724_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28763'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28725_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28763'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28726_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28763'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28730_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28763'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28731_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28763'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28732_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28763'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28736_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28763'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28722_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28763'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28727_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28763'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28728_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28763'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28733_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28763'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28734_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28763'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28737_ADDR' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28739'.
  created $dff cell `$procdff$28789' with positive edge clock.
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28737_DATA' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28739'.
  created $dff cell `$procdff$28790' with positive edge clock.
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28737_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28739'.
  created $dff cell `$procdff$28791' with positive edge clock.
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.\muxwre' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28738'.
  created direct connection (no actual register cell created).

21.42.9.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28763'.
Found and cleaned up 1 empty switch in `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28739'.
Removing empty process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28738'.
Cleaned up 1 empty switch.

21.42.9.12. Executing OPT_EXPR pass (perform const folding).

21.42.10. Executing PROC pass (convert processes to netlists).

21.42.10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28809'.
Cleaned up 1 empty switch.

21.42.10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28810 in module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.10.4. Executing PROC_INIT pass (extract init attributes).

21.42.10.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.10.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.10.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28834'.
Creating decoders for process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28810'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28808_EN[3:0]$28815
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28808_DATA[3:0]$28816
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28808_ADDR[3:0]$28814
Creating decoders for process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28809'.

21.42.10.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.10.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.\i' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28834'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28805_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28834'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28799_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28834'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28793_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28834'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28792_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28834'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28794_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28834'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28795_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28834'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28796_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28834'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28800_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28834'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28801_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28834'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28802_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28834'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28806_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28834'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28807_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28834'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28797_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28834'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28798_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28834'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28803_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28834'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28804_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28834'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28808_ADDR' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28810'.
  created $dff cell `$procdff$28860' with positive edge clock.
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28808_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28810'.
  created $dff cell `$procdff$28861' with positive edge clock.
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28808_DATA' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28810'.
  created $dff cell `$procdff$28862' with positive edge clock.
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.\muxwre' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28809'.
  created direct connection (no actual register cell created).

21.42.10.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28834'.
Found and cleaned up 1 empty switch in `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28810'.
Removing empty process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28809'.
Cleaned up 1 empty switch.

21.42.10.12. Executing OPT_EXPR pass (perform const folding).

21.42.11. Executing PROC pass (convert processes to netlists).

21.42.11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28880'.
Cleaned up 1 empty switch.

21.42.11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28881 in module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.11.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.11.4. Executing PROC_INIT pass (extract init attributes).

21.42.11.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.11.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.11.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28905'.
Creating decoders for process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28881'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28879_EN[3:0]$28886
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28879_DATA[3:0]$28885
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28879_ADDR[3:0]$28887
Creating decoders for process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28880'.

21.42.11.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.11.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.\i' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28905'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28875_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28905'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28870_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28905'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28865_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28905'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28863_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28905'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28866_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28905'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28867_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28905'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28871_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28905'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28872_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28905'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28876_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28905'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28868_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28905'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28877_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28905'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28864_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28905'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28873_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28905'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28869_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28905'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28878_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28905'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28874_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28905'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28879_DATA' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28881'.
  created $dff cell `$procdff$28931' with positive edge clock.
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28879_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28881'.
  created $dff cell `$procdff$28932' with positive edge clock.
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28879_ADDR' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28881'.
  created $dff cell `$procdff$28933' with positive edge clock.
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28880'.
  created direct connection (no actual register cell created).

21.42.11.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.11.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28905'.
Found and cleaned up 1 empty switch in `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28881'.
Removing empty process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28880'.
Cleaned up 1 empty switch.

21.42.11.12. Executing OPT_EXPR pass (perform const folding).

21.42.12. Executing SCC pass (detecting logic loops).
Found an SCC: $techmap$auto$ff.cc:266:slice$12043.$auto$simplemap.cc:267:simplemap_mux$28219
Found an SCC: $techmap$auto$ff.cc:266:slice$12042.$auto$simplemap.cc:267:simplemap_mux$28219
Found an SCC: $techmap$auto$ff.cc:266:slice$12041.$auto$simplemap.cc:267:simplemap_mux$28219
Found an SCC: $techmap$auto$ff.cc:266:slice$12040.$auto$simplemap.cc:267:simplemap_mux$28219
Found an SCC: $techmap$auto$ff.cc:266:slice$11438.$auto$simplemap.cc:267:simplemap_mux$28219
Found an SCC: $techmap$auto$ff.cc:266:slice$11437.$auto$simplemap.cc:267:simplemap_mux$28219
Found an SCC: $techmap$auto$ff.cc:266:slice$11436.$auto$simplemap.cc:267:simplemap_mux$28219
Found an SCC: $techmap$auto$ff.cc:266:slice$11435.$auto$simplemap.cc:267:simplemap_mux$28219
Found an SCC: $auto$simplemap.cc:38:simplemap_not$24693 $auto$ff.cc:266:slice$7597 $auto$simplemap.cc:126:simplemap_reduce$7785 $auto$simplemap.cc:126:simplemap_reduce$7770 $auto$ff.cc:266:slice$7598 $auto$ff.cc:266:slice$7599 $auto$simplemap.cc:75:simplemap_bitop$16291 $auto$simplemap.cc:196:simplemap_lognot$7790 $auto$simplemap.cc:126:simplemap_reduce$7788 $auto$simplemap.cc:126:simplemap_reduce$7786 $auto$opt_expr.cc:613:replace_const_cells$25984 $auto$simplemap.cc:126:simplemap_reduce$16298 $auto$opt_expr.cc:613:replace_const_cells$26220 $auto$simplemap.cc:267:simplemap_mux$16288 $auto$simplemap.cc:126:simplemap_reduce$16306 $auto$simplemap.cc:126:simplemap_reduce$16303 $auto$simplemap.cc:75:simplemap_bitop$16289 $auto$opt_expr.cc:613:replace_const_cells$26222 $auto$simplemap.cc:225:simplemap_logbin$7758 $auto$simplemap.cc:196:simplemap_lognot$7775 $auto$simplemap.cc:126:simplemap_reduce$7773 $auto$simplemap.cc:126:simplemap_reduce$7771 $auto$ff.cc:266:slice$7600 $auto$simplemap.cc:126:simplemap_reduce$4939 $auto$simplemap.cc:126:simplemap_reduce$4937 $auto$simplemap.cc:225:simplemap_logbin$7733 $auto$simplemap.cc:196:simplemap_lognot$7743 $auto$simplemap.cc:126:simplemap_reduce$7741 $auto$opt_expr.cc:613:replace_const_cells$26218 $auto$simplemap.cc:267:simplemap_mux$16287 $auto$simplemap.cc:126:simplemap_reduce$16301
Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$11397 $auto$simplemap.cc:38:simplemap_not$7429 $auto$simplemap.cc:38:simplemap_not$14493 $auto$ff.cc:266:slice$8099 $auto$ff.cc:479:convert_ce_over_srst$26902 $auto$alumacc.cc:485:replace_alu$2758.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7432 $auto$simplemap.cc:38:simplemap_not$24722 $auto$ff.cc:266:slice$8100 $auto$ff.cc:479:convert_ce_over_srst$26904 $auto$ff.cc:266:slice$8101 $auto$ff.cc:479:convert_ce_over_srst$26906 $auto$alumacc.cc:485:replace_alu$2758.slice[2].ccu2c_i $auto$ff.cc:266:slice$8102 $auto$ff.cc:479:convert_ce_over_srst$26908 $auto$ff.cc:266:slice$8103 $auto$ff.cc:479:convert_ce_over_srst$26910 $auto$simplemap.cc:126:simplemap_reduce$11641 $auto$simplemap.cc:75:simplemap_bitop$7430 $auto$simplemap.cc:38:simplemap_not$7439 $auto$alumacc.cc:485:replace_alu$2758.slice[4].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7434 $auto$simplemap.cc:38:simplemap_not$24726 $auto$ff.cc:266:slice$8104 $auto$ff.cc:479:convert_ce_over_srst$26912 $auto$simplemap.cc:126:simplemap_reduce$11434 $auto$simplemap.cc:126:simplemap_reduce$11432 $auto$simplemap.cc:126:simplemap_reduce$11399 $auto$simplemap.cc:126:simplemap_reduce$11396 $auto$simplemap.cc:126:simplemap_reduce$7438 $auto$simplemap.cc:126:simplemap_reduce$7436 $auto$simplemap.cc:126:simplemap_reduce$7433 $auto$simplemap.cc:38:simplemap_not$14496
Found an SCC: $auto$ff.cc:266:slice$7612 $auto$ff.cc:266:slice$7613 $auto$ff.cc:266:slice$7607 $auto$ff.cc:266:slice$7609 $auto$ff.cc:266:slice$7611 $auto$simplemap.cc:126:simplemap_reduce$7813 $auto$simplemap.cc:38:simplemap_not$15419 $auto$ff.cc:266:slice$7610 $auto$simplemap.cc:126:simplemap_reduce$7812 $auto$ff.cc:266:slice$7608 $auto$ff.cc:266:slice$7601 $auto$simplemap.cc:38:simplemap_not$15412 $auto$ff.cc:266:slice$7603 $auto$simplemap.cc:126:simplemap_reduce$7809 $auto$ff.cc:266:slice$7602 $auto$ff.cc:266:slice$7605 $auto$simplemap.cc:126:simplemap_reduce$7816 $auto$simplemap.cc:126:simplemap_reduce$7810 $auto$simplemap.cc:38:simplemap_not$15413 $auto$ff.cc:266:slice$7604 $auto$simplemap.cc:126:simplemap_reduce$7820 $auto$simplemap.cc:126:simplemap_reduce$7817 $auto$simplemap.cc:126:simplemap_reduce$7811 $auto$simplemap.cc:38:simplemap_not$15415 $auto$ff.cc:266:slice$7606 $auto$simplemap.cc:167:logic_reduce$4933 $auto$simplemap.cc:196:simplemap_lognot$7825 $auto$simplemap.cc:126:simplemap_reduce$7823 $auto$simplemap.cc:126:simplemap_reduce$7821 $auto$simplemap.cc:126:simplemap_reduce$7818 $auto$simplemap.cc:126:simplemap_reduce$7814 $auto$simplemap.cc:38:simplemap_not$15421
Found an SCC: $auto$ff.cc:266:slice$4423 $auto$ff.cc:266:slice$4414 $auto$ff.cc:266:slice$4411 $auto$ff.cc:266:slice$4415 $auto$simplemap.cc:126:simplemap_reduce$7400 $auto$simplemap.cc:38:simplemap_not$17180 $auto$ff.cc:266:slice$4416 $auto$simplemap.cc:38:simplemap_not$17172 $auto$ff.cc:266:slice$4408 $auto$simplemap.cc:38:simplemap_not$17174 $auto$ff.cc:266:slice$4410 $auto$ff.cc:266:slice$4404 $auto$ff.cc:266:slice$4425 $auto$simplemap.cc:126:simplemap_reduce$7397 $auto$simplemap.cc:38:simplemap_not$17173 $auto$ff.cc:266:slice$4409 $auto$ff.cc:266:slice$4405 $auto$ff.cc:266:slice$4419 $auto$simplemap.cc:126:simplemap_reduce$7399 $auto$ff.cc:266:slice$4413 $auto$simplemap.cc:38:simplemap_not$17195 $auto$ff.cc:266:slice$4431 $auto$simplemap.cc:38:simplemap_not$17193 $auto$ff.cc:266:slice$4429 $auto$simplemap.cc:38:simplemap_not$17197 $auto$ff.cc:266:slice$4433 $auto$simplemap.cc:126:simplemap_reduce$7402 $auto$ff.cc:266:slice$4420 $auto$simplemap.cc:126:simplemap_reduce$7405 $auto$simplemap.cc:38:simplemap_not$17190 $auto$ff.cc:266:slice$4426 $auto$simplemap.cc:126:simplemap_reduce$7408 $auto$simplemap.cc:38:simplemap_not$17196 $auto$ff.cc:266:slice$4432 $auto$simplemap.cc:126:simplemap_reduce$7418 $auto$simplemap.cc:126:simplemap_reduce$7409 $auto$simplemap.cc:38:simplemap_not$17198 $auto$ff.cc:266:slice$4434 $auto$alumacc.cc:485:replace_alu$2769.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$2769.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7412 $auto$simplemap.cc:126:simplemap_reduce$7396 $auto$simplemap.cc:38:simplemap_not$17171 $auto$ff.cc:266:slice$4407 $auto$ff.cc:266:slice$4422 $auto$ff.cc:266:slice$4417 $auto$simplemap.cc:126:simplemap_reduce$7415 $auto$simplemap.cc:126:simplemap_reduce$7403 $auto$ff.cc:266:slice$4421 $auto$simplemap.cc:38:simplemap_not$17191 $auto$ff.cc:266:slice$4427 $auto$simplemap.cc:126:simplemap_reduce$7406 $auto$simplemap.cc:38:simplemap_not$17192 $auto$ff.cc:266:slice$4428 $auto$simplemap.cc:126:simplemap_reduce$7395 $auto$ff.cc:266:slice$4406 $auto$alumacc.cc:485:replace_alu$2769.slice[8].ccu2c_i $auto$alumacc.cc:485:replace_alu$2769.slice[6].ccu2c_i $auto$alumacc.cc:485:replace_alu$2769.slice[4].ccu2c_i $auto$ff.cc:266:slice$4412 $auto$alumacc.cc:485:replace_alu$2769.slice[14].ccu2c_i $auto$alumacc.cc:485:replace_alu$2769.slice[12].ccu2c_i $auto$alumacc.cc:485:replace_alu$2769.slice[10].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7414 $auto$simplemap.cc:126:simplemap_reduce$7401 $auto$simplemap.cc:38:simplemap_not$17182 $auto$ff.cc:266:slice$4418 $auto$alumacc.cc:485:replace_alu$2769.slice[20].ccu2c_i $auto$alumacc.cc:485:replace_alu$2769.slice[18].ccu2c_i $auto$alumacc.cc:485:replace_alu$2769.slice[16].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7422 $auto$simplemap.cc:126:simplemap_reduce$7416 $auto$simplemap.cc:126:simplemap_reduce$7404 $auto$simplemap.cc:38:simplemap_not$17188 $auto$ff.cc:266:slice$4424 $auto$simplemap.cc:126:simplemap_reduce$11673 $auto$simplemap.cc:38:simplemap_not$7481 $auto$alumacc.cc:485:replace_alu$2769.slice[26].ccu2c_i $auto$alumacc.cc:485:replace_alu$2769.slice[24].ccu2c_i $auto$alumacc.cc:485:replace_alu$2769.slice[22].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7426 $auto$simplemap.cc:126:simplemap_reduce$7423 $auto$simplemap.cc:126:simplemap_reduce$7417 $auto$simplemap.cc:126:simplemap_reduce$7407 $auto$simplemap.cc:38:simplemap_not$17194 $auto$ff.cc:266:slice$4430 $auto$simplemap.cc:126:simplemap_reduce$7420 $auto$simplemap.cc:126:simplemap_reduce$7411 $auto$simplemap.cc:126:simplemap_reduce$7394 $auto$ff.cc:266:slice$4403 $auto$simplemap.cc:126:simplemap_reduce$11675 $auto$simplemap.cc:126:simplemap_reduce$7428 $auto$simplemap.cc:126:simplemap_reduce$7425 $auto$simplemap.cc:126:simplemap_reduce$7421 $auto$simplemap.cc:126:simplemap_reduce$7413 $auto$simplemap.cc:126:simplemap_reduce$7398 $auto$simplemap.cc:38:simplemap_not$17175
Found 12 SCCs in module top.
Found 12 SCCs.

21.42.13. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.14. Executing PROC pass (convert processes to netlists).

21.42.14.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

21.42.14.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

21.42.14.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

21.42.14.4. Executing PROC_INIT pass (extract init attributes).

21.42.14.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.14.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

21.42.14.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

21.42.14.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.14.9. Executing PROC_DFF pass (convert process syncs to FFs).

21.42.14.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.14.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

21.42.14.12. Executing OPT_EXPR pass (perform const folding).

21.42.15. Executing TECHMAP pass (map to technology primitives).

21.42.15.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

21.42.15.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~178 debug messages>

21.42.16. Executing OPT pass (performing simple optimizations).

21.42.16.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
Optimizing module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
Optimizing module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
Optimizing module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
Optimizing module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Optimizing module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Optimizing module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.

21.42.16.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

21.42.16.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.42.16.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Performed a total of 0 changes.

21.42.16.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

21.42.16.6. Executing OPT_DFF pass (perform DFF optimizations).

21.42.16.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4..

21.42.16.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
Optimizing module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
Optimizing module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Optimizing module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Optimizing module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
Optimizing module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
Optimizing module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Optimizing module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.

21.42.16.9. Finished OPT passes. (There is nothing left to do.)

21.42.17. Executing TECHMAP pass (map to technology primitives).

21.42.17.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

21.42.17.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4 for cells of type $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
Using template $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4 for cells of type $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
Using template $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4 for cells of type $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Using template $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4 for cells of type $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Using template $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4 for cells of type $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Using template $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4 for cells of type $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
Using template $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4 for cells of type $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
Using template $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4 for cells of type $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~523 debug messages>

21.42.18. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

21.42.19. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

21.42.20. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.21. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

21.42.22. Executing TECHMAP pass (map to technology primitives).

21.42.22.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

21.42.22.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $xor.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using extmapper simplemap for cells of type $or.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~217 debug messages>

21.42.23. Executing OPT pass (performing simple optimizations).

21.42.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~18 debug messages>

21.42.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

21.42.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.42.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.42.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.42.23.6. Executing OPT_DFF pass (perform DFF optimizations).

21.42.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>

21.42.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.42.23.9. Rerunning OPT passes. (Maybe there is more to do..)

21.42.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.42.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.42.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.42.23.13. Executing OPT_DFF pass (perform DFF optimizations).

21.42.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.42.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.42.23.16. Finished OPT passes. (There is nothing left to do.)

21.42.24. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 18 cells with 120 new cells, skipped 39 cells.
  replaced 3 cell types:
       2 $_OR_
       2 $_XOR_
      14 $_MUX_
  not replaced 3 cell types:
      31 $specify2
       4 $_NOT_
       4 $_AND_

21.42.25. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 6006 cells with 33402 new cells, skipped 5768 cells.
  replaced 3 cell types:
    2880 $_OR_
      67 $_XOR_
    3059 $_MUX_
  not replaced 24 cell types:
     377 $_NOT_
    2818 $_AND_
       5 $_TBUF_
    1302 TRELLIS_FF
       1 $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4
       1 $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4
       1 $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4_$abc9_byp
     241 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
       1 $__ABC9_SCC_BREAKER
       1 $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4_$abc9_byp
     504 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4
       1 $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4
     504 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
       1 $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4
       1 $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4
       1 $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4
       1 $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4

21.42.25.1. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.25.2. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.25.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 15076 AND gates and 43185 wires from module `top' to a netlist network with 3370 inputs and 497 outputs.

21.42.25.4. Executing ABC9_EXE pass (technology mapping using ABC9).

21.42.25.5. Executing ABC9.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   3370/    497  and =   13850  lev =   44 (5.78)  mem = 0.36 MB  box = 753  bb = 512
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   3370/    497  and =   19939  lev =   59 (3.24)  mem = 0.41 MB  ch = 1383  box = 677  bb = 512
ABC: + &if -W 300 -v 
ABC: K = 7. Memory (bytes): Truth =    0. Cut =   60. Obj =  140. Set =  636. CutMin = no
ABC: Node =   19939.  Ch =   980.  Total mem =    4.75 MB. Peak cut mem =    0.23 MB.
ABC: P:  Del = 6757.00.  Ar =   20798.0.  Edge =    23332.  Cut =   308705.  T =     0.07 sec
ABC: P:  Del = 6705.00.  Ar =   21825.0.  Edge =    23850.  Cut =   285776.  T =     0.07 sec
ABC: P:  Del = 6705.00.  Ar =    7976.0.  Edge =    18311.  Cut =   662301.  T =     0.14 sec
ABC: F:  Del = 6705.00.  Ar =    5757.0.  Edge =    16184.  Cut =   604984.  T =     0.14 sec
ABC: A:  Del = 6705.00.  Ar =    5339.0.  Edge =    15453.  Cut =   489105.  T =     0.20 sec
ABC: A:  Del = 6705.00.  Ar =    5291.0.  Edge =    15408.  Cut =   589781.  T =     0.24 sec
ABC: Total time =     0.86 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: + &ps -l 
ABC: <abc-temp-dir>/input : i/o =   3370/    497  and =   12635  lev =   36 (3.66)  mem = 0.33 MB  box = 677  bb = 512
ABC: Mapping (K=7)  :  lut =   3809  edge =   15366  lev =   14 (1.59)  levB =   25  mem = 0.18 MB
ABC: LUT = 3809 : 2=267 7.0 %  3=274 7.2 %  4=2623 68.9 %  5=466 12.2 %  6=65 1.7 %  7=114 3.0 %  Ave = 4.03
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + time 
ABC: elapse: 5.96 seconds, total: 5.96 seconds

21.42.25.6. Executing AIGER frontend.
<suppressed ~7822 debug messages>
Removed 16173 unused cells and 30327 unused wires.

21.42.25.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:     3828
ABC RESULTS:   $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells:      165
ABC RESULTS:   $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells:      504
ABC RESULTS:   $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:           input signals:      569
ABC RESULTS:          output signals:      111
Removing temp directory.

21.42.26. Executing TECHMAP pass (map to technology primitives).

21.42.26.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

21.42.26.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4 for cells of type $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
Using template $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4 for cells of type $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
Using template $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4 for cells of type $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Using template $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4 for cells of type $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Using template $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4 for cells of type $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Using template $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4 for cells of type $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
Using template $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4 for cells of type $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
Using template $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4 for cells of type $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
Using template $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000001100 for cells of type $__ABC9_SCC_BREAKER.
No more expansions possible.
<suppressed ~1225 debug messages>
Removed 212 unused cells and 49496 unused wires.

21.43. Executing TECHMAP pass (map to technology primitives).

21.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

21.43.2. Continuing TECHMAP pass.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod$c217e185eb8e6463ca272982ba8c5940fa90d81f\$lut for cells of type $lut.
Using template $paramod$5c36a508e8885449eeca65fa0c02b7154f6a3130\$lut for cells of type $lut.
Using template $paramod$a8b2b0f3a3fd7b01c99e8d61bb72f602bd41af54\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut.
Using template $paramod$8452243fb48b407833fccc268c2e858d8fb8a91b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod$cd4f4295f5084044560b62b49d805756222899b9\$lut for cells of type $lut.
Using template $paramod$ca4622dd5cce1ae747940c81feb34d462f1bb826\$lut for cells of type $lut.
Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5\$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod$f7bb8f06187392e20d67569087bc2fe4545f9329\$lut for cells of type $lut.
Using template $paramod$c24f8fdd416c42f1d58fb5343fd9f64c5a61ee3f\$lut for cells of type $lut.
Using template $paramod$803fb2e411cd759897bb32714c4cd91d7f11ca86\$lut for cells of type $lut.
Using template $paramod$acaffca83717f52a2fd861f73e9419e6c70cbc5d\$lut for cells of type $lut.
Using template $paramod$93e59f21d13b046d5960861a7ba127bbb388d6d1\$lut for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut.
Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut.
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut.
Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut.
Using template $paramod$59f2a3e232df3029c8bc36978b9bbe72a71dfb5a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod$df2c5671757930949ccad092458a7f705f78ea6a\$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$e85b6eba0dacefc5f73f8748159b8b9599212afc\$lut for cells of type $lut.
Using template $paramod$7ccb46ee9b56c39e0a7d82a185b08cb026e04fbc\$lut for cells of type $lut.
Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut.
Using template $paramod$0f9a5ffb15c1e481b6b1d423325ea99a60119726\$lut for cells of type $lut.
Using template $paramod$f546bd96bcec6e3bf1b78bdea64b0f5bbbaff6df\$lut for cells of type $lut.
Using template $paramod$344cc1d80011edd25f4e96042348a38c291be451\$lut for cells of type $lut.
Using template $paramod$e1623268c9003e962398ac4439a1e71823bfe84c\$lut for cells of type $lut.
Using template $paramod$cf53e4edf729275ad080a2bda0bf50af566f40f8\$lut for cells of type $lut.
Using template $paramod$4b13f036115ce1bfaedc0ace1c15ea7e612c6224\$lut for cells of type $lut.
Using template $paramod$d595f40cfc33e6fcedfc32971db56942d44597db\$lut for cells of type $lut.
Using template $paramod$17bd81b3d0b0f7b79dafb496bade494ba491a642\$lut for cells of type $lut.
Using template $paramod$ee19d45db61acb4c70d938b97483a4ed4b792645\$lut for cells of type $lut.
Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut.
Using template $paramod$67b1b761102ea2ed7f0f277d000c631a9072a22f\$lut for cells of type $lut.
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut.
Using template $paramod$40bf400bfab4b5cf32dcfe01e14f0900ac7f6b1b\$lut for cells of type $lut.
Using template $paramod$a237e3ba5a667f09416333271462f486601de1ad\$lut for cells of type $lut.
Using template $paramod$32d74efcaa3179123add72ab521dff5355eac8a0\$lut for cells of type $lut.
Using template $paramod$63114da772fb28945ba24699e32f1e30ca7142f4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut.
Using template $paramod$60d2f5cab8c1e6f41b4840ac141ed9152e14e949\$lut for cells of type $lut.
Using template $paramod$c4c53fc2069709859de2e7d395c61280d40a8432\$lut for cells of type $lut.
Using template $paramod$4eb848e991ac2a992be9b4be01f278b220c0efac\$lut for cells of type $lut.
Using template $paramod$718179c4766b4ea66e8ece9b944be5b997b67ba5\$lut for cells of type $lut.
Using template $paramod$7869265433e87c5986ebaf055d7288af743acd0c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut.
Using template $paramod$3ccc23db184ad4ca7ed34ebe2511de41d5d97e78\$lut for cells of type $lut.
Using template $paramod$7202672b7332febf25cdbe5424cf24593f5449be\$lut for cells of type $lut.
Using template $paramod$5400b6807adef39a9693b2fbff17f8c0ab116b66\$lut for cells of type $lut.
Using template $paramod$c20bb0ec9b7ffe048b440bc5b52865dca055e17d\$lut for cells of type $lut.
Using template $paramod$394086530b97e2ede4325cfef07483589916f736\$lut for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut.
Using template $paramod$de139c0078d9a308da97b8302bb1040535f13d7c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod$5b4b4ed558983d9f3ab4c896a7a011d129b0db9a\$lut for cells of type $lut.
Using template $paramod$6fab3e42679b868d1d9b15f2c058a9fdc99ca122\$lut for cells of type $lut.
Using template $paramod$874323b1b03bdf604ef39a47eba69b0b6ac78f25\$lut for cells of type $lut.
Using template $paramod$da49ead6f31a43bab2d6c107c254e628a16f3330\$lut for cells of type $lut.
Using template $paramod$176a6ceafa512d807921d7dfc76320dfbbfb5fe4\$lut for cells of type $lut.
Using template $paramod$41271b185c0299e54b5a93c3a0fde10b3867cc20\$lut for cells of type $lut.
Using template $paramod$11b6a2e0b5538d16dbffc5ea22a12a0e43c1e883\$lut for cells of type $lut.
Using template $paramod$4db3f0d067a6794efd5979ea33ffc0ce06e2e75c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001101 for cells of type $lut.
Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut.
Using template $paramod$be95f3a2132281eadd1adcfe6229e43dbc3353c9\$lut for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut.
Using template $paramod$2e42f4cdfa2b7be54cbecc74818d81b621a7793c\$lut for cells of type $lut.
Using template $paramod$6fc23ce09f2013cb9de2228dbcdda21841008f92\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod$302ba22a83dfb50189674147c5c2626b9e9dab7e\$lut for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut.
Using template $paramod$c039f15592dbb863a55cd28cd138649990f0aecd\$lut for cells of type $lut.
Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut.
Using template $paramod$8642dee22bfdb28bd84aa369e85fa9091862c0b2\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod$0f891ee84fac320f890afcf9c994c53a24cd31f9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
Using template $paramod$2a4b250d89be3556c74aa0e719a4f6242369d42f\$lut for cells of type $lut.
Using template $paramod$7d813eb49700f971f2635a434700eafdfa816bc3\$lut for cells of type $lut.
Using template $paramod$f6cb3fdab41e95c971e90994829351e95bc70e14\$lut for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut.
Using template $paramod$7cfe73664922da444301106f474e41d924726fae\$lut for cells of type $lut.
Using template $paramod$7ce7683c590e6b9a2ebd543a8f468551f1af24cf\$lut for cells of type $lut.
Using template $paramod$d9922e15eb5da1acc26e937540cc16b16c2ad42c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
Using template $paramod$a15fd389a2f54cb7b94707b25934d226e68d9e2e\$lut for cells of type $lut.
Using template $paramod$8696f458b0bc45d72f187617e991118b6ed26c4f\$lut for cells of type $lut.
Using template $paramod$3b374b0454c507d1efadee363d480c52c3b3f58f\$lut for cells of type $lut.
Using template $paramod$56c6fc98268f6966dd23dcb4af9b8f5298fa7ead\$lut for cells of type $lut.
Using template $paramod$b9cbb0f16a176e4b2e9dbca6aee127ce97922bd2\$lut for cells of type $lut.
Using template $paramod$247d41e6aae45287b99bdb9671745e7a6e92d532\$lut for cells of type $lut.
Using template $paramod$31b733cd55c680261b2f8eac8a3640c7194eebae\$lut for cells of type $lut.
Using template $paramod$27ec8a5745a5683119f8cb18ab7ba7fb9c14d17f\$lut for cells of type $lut.
Using template $paramod$968507d62d2af132f3fac8551304ecda97f656fb\$lut for cells of type $lut.
Using template $paramod$60e01561cadcff25188deca814511e4a10e72d35\$lut for cells of type $lut.
Using template $paramod$7bee76741eb51df66260977432d861248a5c6f1e\$lut for cells of type $lut.
Using template $paramod$47a326ee296feaca60c97add5a2f7670de259bd9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut.
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut.
Using template $paramod$74c0f3179b5cebe485563ea55e9b637e7ee5c0c3\$lut for cells of type $lut.
Using template $paramod$daac9b1e7bb2ac018f7132a3fbe0026ddd7b1a71\$lut for cells of type $lut.
Using template $paramod$aab54572d5ffecd31253b36e73e9cb718d05be34\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod$d546db88fc169832512e499a9cdf9a41b89ab74e\$lut for cells of type $lut.
Using template $paramod$d39daf56a31b2e8ce06533aad96ed54894dfed59\$lut for cells of type $lut.
Using template $paramod$a05170b3f2d3fcb0bf88d37e810984e864962880\$lut for cells of type $lut.
Using template $paramod$b482d305d17b85448f1eb6eb18c3d50230d62ecc\$lut for cells of type $lut.
Using template $paramod$60b758fd5679f6508bff32bea2afedb4f329e5f9\$lut for cells of type $lut.
Using template $paramod$e496e1ebaf8968b0448781d0c7b4fab8e5e7c961\$lut for cells of type $lut.
Using template $paramod$5dd5bdaac12c3e4b11850b45194b663734dd753b\$lut for cells of type $lut.
Using template $paramod$151773c161f403488b6d9962171babf39d88db5c\$lut for cells of type $lut.
Using template $paramod$c35ad3063d5038410210ddc72c1fd5fed46413b4\$lut for cells of type $lut.
Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$193d365ba3260f56de4ca734b1cedcf9dc72302b\$lut for cells of type $lut.
Using template $paramod$5275e9d6b0ff826f977bc54b20fbdf68c5bc0a89\$lut for cells of type $lut.
Using template $paramod$09deb89cf77b6e37f6ed7fef8d797dc05c0b2eee\$lut for cells of type $lut.
Using template $paramod$75ae9627805e0c99d176bdce0ae8ff0c02687aab\$lut for cells of type $lut.
Using template $paramod$1f575543d734f2d93dfcc8f91b30fb001334bb95\$lut for cells of type $lut.
Using template $paramod$9ff5810d0d4313c60ea05d2ef2f28b920dd1f8ee\$lut for cells of type $lut.
Using template $paramod$c5966e98773f1c185668bb7f5b6385d25e498be1\$lut for cells of type $lut.
Using template $paramod$2ab136f67b9bdf3935400ee9a8211bfbd673c833\$lut for cells of type $lut.
Using template $paramod$920c30c965b89e85bc6c38e2211cf7b09d4fb168\$lut for cells of type $lut.
Using template $paramod$b3a4a16458272670fe99d44d91de9d27aa7c14f3\$lut for cells of type $lut.
Using template $paramod$6023c671e114c4eb0467aa8a0b08e183f33ec2fd\$lut for cells of type $lut.
Using template $paramod$6f9324703e8fcc3b6df2bc2bec54ec19a446ae96\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$28a43eafd9c70d95e52b2418cf601e2e6b0411d3\$lut for cells of type $lut.
Using template $paramod$6df06577fab04385d46871e46644a696e22b7b2f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod$26d876869d6ab003366d0470e095daef2ccfcbd7\$lut for cells of type $lut.
Using template $paramod$d7372df0dc02a6c940130cc6e3dbb5dc0398486d\$lut for cells of type $lut.
Using template $paramod$f672f1e5ea7eaf40630014635549af40fc023a51\$lut for cells of type $lut.
Using template $paramod$0331e023d83b8009e60defb446ce9fa640b122c7\$lut for cells of type $lut.
Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut.
Using template $paramod$849d013d096d73269ca4beb768f8e399745d37f2\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod$2c959eb814502b813fb2b3a30c8dfa8d0f5741f3\$lut for cells of type $lut.
Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut.
Using template $paramod$55290dc5b2d325b1a51b6c31876bbb759b0b4b79\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut.
Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut.
Using template $paramod$caad58040116ab75470aaad37ed97fe8e10a8158\$lut for cells of type $lut.
Using template $paramod$98f8d17b25262d98d340140a4a5e512d234da40f\$lut for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut.
Using template $paramod$ee700feb78d1f78a2275689013e0e783764ce7f3\$lut for cells of type $lut.
Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f\$lut for cells of type $lut.
Using template $paramod$757c055b2d591f99a56beeb4bd1bdff266f67334\$lut for cells of type $lut.
Using template $paramod$5fa057242d435f2451c6bd198ef5ade6e3a77bb8\$lut for cells of type $lut.
Using template $paramod$6df45487b7ff542346e7f3201899fd223e81c5a0\$lut for cells of type $lut.
Using template $paramod$7fc325150916e09e21db63cc9672b99a89ef9301\$lut for cells of type $lut.
Using template $paramod$6d455d75bf172984ed004f7a5237b0ffe03e473b\$lut for cells of type $lut.
Using template $paramod$0f19b1c588a47c675d00132b243b5e3308ffab5d\$lut for cells of type $lut.
Using template $paramod$466db5b833deb153f39d807f4edbdf783486e131\$lut for cells of type $lut.
Using template $paramod$f13784ede300b12a5285177c86c7721a54cf9e12\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut.
Using template $paramod$1dbc005c3ca46176ed5f71d3318762a2498d170f\$lut for cells of type $lut.
Using template $paramod$332a399730bfc61adea04021a76b1c4e4030f37d\$lut for cells of type $lut.
Using template $paramod$95e3b069aff4a6adc0a3d90d66a109cc8ab110fa\$lut for cells of type $lut.
Using template $paramod$fffa155a219a46fb60e49c6660387f749cff3314\$lut for cells of type $lut.
Using template $paramod$e41077ee9a586289f18c67aae406c6a0c3d82cf3\$lut for cells of type $lut.
Using template $paramod$89ca3723ebb4dfdb3c4024f3f04b784a3e88f188\$lut for cells of type $lut.
Using template $paramod$a4640096cbef09c4ef8613155a589c40164ac034\$lut for cells of type $lut.
Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut.
Using template $paramod$cd77d5e7596a750e2c0ed130aacde2f323347f26\$lut for cells of type $lut.
Using template $paramod$a2329fe9c79054aad7c1fa172a19f1c9229b35e9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut.
Using template $paramod$f6e4b9df06807cac5789d4518648b5ffebae2abf\$lut for cells of type $lut.
Using template $paramod$57b0544f41a25c72a09d87f02afdb1a58250c2f7\$lut for cells of type $lut.
Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut.
Using template $paramod$dbdbcb07b9994e498bb1324e5c006c6aa08a7a37\$lut for cells of type $lut.
Using template $paramod$40b4a412b648ae3a239485526d56ceda18b420c9\$lut for cells of type $lut.
Using template $paramod$81ec8bd21cac2d39b7a042a8fd953a5cd3b7e6a1\$lut for cells of type $lut.
Using template $paramod$eabde4761c91679426ef5401ae1b2c95bf56e107\$lut for cells of type $lut.
Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut.
Using template $paramod$1f5c7b36d9ce2e112a0d4ef900f28d09aa656452\$lut for cells of type $lut.
Using template $paramod$83a094b6fe9fb738dfff353a8cb39fb4b34c4f40\$lut for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut.
Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut.
Using template $paramod$be890c21f2c4d30e642da2b8f1692f7983c02ea2\$lut for cells of type $lut.
Using template $paramod$05b5aa92f05138cd96904642c56a4188af97194f\$lut for cells of type $lut.
Using template $paramod$48c19eb209dd8ad2c18334e4df384d3b3b74d5ec\$lut for cells of type $lut.
Using template $paramod$8ae5e24171bca0b8d12d43741a6723f274290f92\$lut for cells of type $lut.
Using template $paramod$4133fe00eb18442862a284ccc67a95f8194d041c\$lut for cells of type $lut.
Using template $paramod$fda6887b37f599177ed9cb69271d882b63df7e66\$lut for cells of type $lut.
Using template $paramod$9a6965d4f53d69e345bd8d48283856520a30225e\$lut for cells of type $lut.
Using template $paramod$9f940528886e4436555e49aadfc3973afc89a325\$lut for cells of type $lut.
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut.
Using template $paramod$15ac410ea5b84c303864da98179081473b96983a\$lut for cells of type $lut.
Using template $paramod$0d4742cff20cb0e0e40b9af6c0257e3a276c0c2b\$lut for cells of type $lut.
Using template $paramod$b7d5a1d13a95755f80d49e78f7fe57dd63a6cfbe\$lut for cells of type $lut.
Using template $paramod$75d5c453cca75cc7a7ca320c4fb7be0932b6aaa7\$lut for cells of type $lut.
Using template $paramod$7bdeabbe4254f72e48d1c8836d2024b0c859eb93\$lut for cells of type $lut.
Using template $paramod$d330f39a497e29dd1c29fbd6c090f86e91f25241\$lut for cells of type $lut.
Using template $paramod$30ccc2d02d561628bd3e8ba21431cf11015685a5\$lut for cells of type $lut.
Using template $paramod$769bdbbde83614df0f4ab5f54e777ded51bb10ce\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod$20ae971f03a8aabd14bc9c90601f9bed8100c9da\$lut for cells of type $lut.
Using template $paramod$84c5cfa8d7481774250caab0fcdd6d249a376a31\$lut for cells of type $lut.
Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d\$lut for cells of type $lut.
Using template $paramod$37c9af120c85145419565a9ccf4ceb7397fbbe92\$lut for cells of type $lut.
Using template $paramod$f314abdbef3663f31659cf7a4e5e574a874f0912\$lut for cells of type $lut.
Using template $paramod$712505941a295086314c22735153725461a87f4a\$lut for cells of type $lut.
Using template $paramod$da48f07e3a6bb83a1cd493e7f686282a4bed64f5\$lut for cells of type $lut.
Using template $paramod$d08ae3e2fee668f1a68bd32fd012d46d229cb782\$lut for cells of type $lut.
Using template $paramod$068092ddede495d8462ffe530e6d91711913edbc\$lut for cells of type $lut.
Using template $paramod$5b4991ef8e215d9f18839630c2afa21273bf9421\$lut for cells of type $lut.
Using template $paramod$e019cb14313283ce60b57907d30cf3eefa00a93d\$lut for cells of type $lut.
Using template $paramod$baa9d2fb2d21010939721b85aa9f11effe0b53c4\$lut for cells of type $lut.
Using template $paramod$b97dea647725901eed851280e5a3889ea3e50a3d\$lut for cells of type $lut.
Using template $paramod$c5c49020910b92ff4373b705f131c82fdde71644\$lut for cells of type $lut.
Using template $paramod$ba7f31f246a278c41fa0648a6e0512f63185dec0\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod$7a9b7d7d96d5349b2a3f800b325795fd17e50692\$lut for cells of type $lut.
Using template $paramod$e332cff882edd417f410bab5fe07a0f88572cce3\$lut for cells of type $lut.
Using template $paramod$f58e0d90afc57a738914697b6a4a7319b30d7e7e\$lut for cells of type $lut.
Using template $paramod$a0b0cf1c522933f731e58459d7a7f9da9f8ee86e\$lut for cells of type $lut.
Using template $paramod$8b8eeaa4738ff9f1125c3e684237d568e8468405\$lut for cells of type $lut.
Using template $paramod$fce992df4978ad69e56d150579aa6ba47bc13a78\$lut for cells of type $lut.
Using template $paramod$538b4ae25dc35aacd84b6990112000e5c658b51e\$lut for cells of type $lut.
Using template $paramod$04fb975be6fe269049a4400755b287a00051a0db\$lut for cells of type $lut.
Using template $paramod$03d7da0d848b4f563fda6bc83a08135cc5ded340\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut.
Using template $paramod$8f7210088a40da1859d27e900c288fd298d68bed\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut.
Using template $paramod$138cb12c2aeb8bc72920026ffe90a83668621cff\$lut for cells of type $lut.
Using template $paramod$10352caa78a7d1fbb181ef6f61719dafe028589b\$lut for cells of type $lut.
Using template $paramod$44c1b28b1f6a49c9523219b444938c19061e33e0\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111011 for cells of type $lut.
Using template $paramod$205ad40b4230bad56308303cbfa3f349fcf03535\$lut for cells of type $lut.
Using template $paramod$1ec3fb8fd1fa98216cb96b4422de32c4ba5f6c9c\$lut for cells of type $lut.
Using template $paramod$694c95659b447cef99dd4cdbd49b87dfd5f6c806\$lut for cells of type $lut.
Using template $paramod$6eaff21d3c29251343ef497052cf2c77fea3c8e9\$lut for cells of type $lut.
Using template $paramod$baa939b0bd5b3e0c8760492528669bd58f640542\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut.
Using template $paramod$b9a230f0128644f43297bc33d870443914811095\$lut for cells of type $lut.
Using template $paramod$77b67ef20c955093353b18505577135db4a47988\$lut for cells of type $lut.
Using template $paramod$9cf976b4f3a576aa2cd6b51304cf5de7fc836fbd\$lut for cells of type $lut.
Using template $paramod$18df3812bc12364e5ebcb6c3ed05c0294e4c26fc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut.
Using template $paramod$cc2a095eb455a4b3d2a771dcc8d049b19888952d\$lut for cells of type $lut.
Using template $paramod$221832ea6a41a3208cd6f3411a952b5811695f4c\$lut for cells of type $lut.
Using template $paramod$10169eb8cbd20a3468845c89f3ff9e027786cf39\$lut for cells of type $lut.
Using template $paramod$39c23bd698f9b5a29dd4b1cc891d07462047f32e\$lut for cells of type $lut.
Using template $paramod$27d1fd562eca397af0bcf374fcecce96bb10480e\$lut for cells of type $lut.
Using template $paramod$137f74d8861423744b1783ae0260df331440aa44\$lut for cells of type $lut.
Using template $paramod$075a034cdb2527a542525df67052889c8173dcf2\$lut for cells of type $lut.
Using template $paramod$000fa2164e1f538c16460571efee2b6209a086cc\$lut for cells of type $lut.
Using template $paramod$deb9c04b2247e9028ddd7bdb0eb764bf0df817f1\$lut for cells of type $lut.
Using template $paramod$d41e4326feac1393586372ef3129c85e3d03343c\$lut for cells of type $lut.
Using template $paramod$0d26e42822227428593a6f2ed183ae9b22d4b575\$lut for cells of type $lut.
Using template $paramod$6382f7860648fdb6f8a8dc690c25a62882cc501b\$lut for cells of type $lut.
Using template $paramod$3bc39f3ad79c0cd33c289df8543dc6495ea876c1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod$1632c1c0242796acfc963a05742c4acd2f475c4e\$lut for cells of type $lut.
Using template $paramod$3b2fdfbff14ab5320509c9ec42fe20214a5bc8e3\$lut for cells of type $lut.
Using template $paramod$a7c07944e10969b2e1fd563a5b72f89493cb3705\$lut for cells of type $lut.
Using template $paramod$b600d182ae966d09f33a746441e104587fe7a58f\$lut for cells of type $lut.
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut.
Using template $paramod$a6597eda4608f36e684c1dd07ed552fcbec112b2\$lut for cells of type $lut.
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut.
Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut.
Using template $paramod$dcba541ad53a9873d71bfba6c13dc2a8e2a60a79\$lut for cells of type $lut.
Using template $paramod$2d52a1d6cf603c98ba7b908cd4e344a0536dbeca\$lut for cells of type $lut.
Using template $paramod$d728e7e6bb60bfda272c7f313a41a343d52152b5\$lut for cells of type $lut.
Using template $paramod$35059585e93e18989247e13034fd6a1ce4de9957\$lut for cells of type $lut.
Using template $paramod$c7275c2675e11ebc1d9539ebad7db386c9c59776\$lut for cells of type $lut.
Using template $paramod$36b7d8209200ca95c844934f9e4add2d5121b073\$lut for cells of type $lut.
Using template $paramod$1efd75a5296c2dbb94506897a28124d20c1063a2\$lut for cells of type $lut.
Using template $paramod$99414dafd78ee35fc62998e26b46b463039a743e\$lut for cells of type $lut.
Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0\$lut for cells of type $lut.
Using template $paramod$d315acbf930db7c20b3f4ac2dad3b7982b1f437c\$lut for cells of type $lut.
Using template $paramod$b2649106a625a0704077b7f703e411239478cf3e\$lut for cells of type $lut.
Using template $paramod$ab39b2ba6ccb452f80c67a2aef4d3a8d93226eda\$lut for cells of type $lut.
Using template $paramod$9cf044275e70b6dc34d2f815a6f8ffc23f9694a0\$lut for cells of type $lut.
Using template $paramod$31d0fe9872e147e32329f1888afc564130486200\$lut for cells of type $lut.
Using template $paramod$97472f517efe00e2e4bbd270b2ef0f8e6d9a1199\$lut for cells of type $lut.
Using template $paramod$63dfb5d507c3c0842cdb02014ffa50dbe5770b84\$lut for cells of type $lut.
Using template $paramod$72148f3545efac6f48701d6c21ae5eeb7a5f865b\$lut for cells of type $lut.
Using template $paramod$2b2b3565ec13859d2b24f2fa297fa46249270140\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
Using template $paramod$e934877433e628b9aa4b7cb2bee8957bca3e1db5\$lut for cells of type $lut.
Using template $paramod$651e836885d95717c36e69441422c3fe04ee5f4d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110011 for cells of type $lut.
Using template $paramod$9ea238b3c4036add2bd96e5aaac8768e1ad77c5a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$c5f3c57a6d466a2f42208bafb8985b96ce884440\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut.
Using template $paramod$0328e568d609989242dcb98a1c5328d4372a6e9c\$lut for cells of type $lut.
Using template $paramod$d198a35e390af0ebd4293772ba44e2470b1d193e\$lut for cells of type $lut.
Using template $paramod$70ebb6cf5bc7d63c5c1a98ccefefa2af79e8f2a9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod$18e50808df562b188523e13714b96fedec6427c1\$lut for cells of type $lut.
No more expansions possible.
<suppressed ~8216 debug messages>

21.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in top.
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$9750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8612.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$7483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$7483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$9816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$9816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$9816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9806.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$9194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$9194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9188.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9110.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9110.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9110.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9110.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9110.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9110.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8429.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8423.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8423.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8423.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8423.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8423.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8423.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8523.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$9363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$9231.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9231.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9231.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$9223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$9223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$8472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$9341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$9341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$9044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$9281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$11308.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$9760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$9760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$9760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$9760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$8900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$8632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8310.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8310.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8310.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$8799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$9057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$9057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$9057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$9057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$7978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$7978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$7978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$7968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$7968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$7968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$7968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$9527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96952.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96951.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96954.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$7509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96953.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$7921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96950.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$7577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96922.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$7650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$7650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$7650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$7650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96938.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96939.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96934.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96935.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$7616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$7616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$7616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$7616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96926.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96927.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96930.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96931.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$7540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96942.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96943.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96948.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96949.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96917.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$7365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$7341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$7124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$7069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$6951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$6951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$6971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$6971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$6971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96924.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$6930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$6930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$6930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$6909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$6909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$6909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$6893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96933.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$6793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$6793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$6793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$6831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$6831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$6831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$6881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6866.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$6859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$6859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$7320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$7300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$7276.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7276.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7276.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7276.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7276.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$7234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$6769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$7181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$7160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$10021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10042.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$10152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10543.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10577.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10620.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10627.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10661.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10735.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10783.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10851.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10979.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10995.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11011.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11063.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11181.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11197.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11213.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$11323.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11339.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11371.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11406.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11423.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11439.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11469.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11538.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11570.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11654.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11843.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11899.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11915.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$11947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12015.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12213.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12363.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12395.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12430.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12437.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12447.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12494.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12627.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12727.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12765.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12827.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12843.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12875.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12955.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$12966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13113.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13245.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13252.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13309.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13395.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13411.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13439.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13581.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13674.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13702.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13709.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13780.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13928.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13979.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$13995.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14011.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14387.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14453.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14619.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14653.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14703.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14724.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14858.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14959.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$14996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15267.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15363.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15431.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15447.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15539.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$15553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15584.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$15600.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$15607.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$15652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$15687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15753.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15845.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15886.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15906.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$15928.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15945.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15961.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$15990.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$16007.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$16023.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16157.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$16187.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$16223.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$16258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16285.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$16298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16372.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16385.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16395.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$16438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$16473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16500.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$16528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16715.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$16744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$16766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16777.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$16789.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16805.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16834.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$16859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16987.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$16994.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$17020.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$17033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$17061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$17093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$17106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$17151.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$17167.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$17197.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$17260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$17323.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$17361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$17374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$17393.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$17409.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$17434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$17446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$17491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$17507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$17549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$17581.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$17594.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$17613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$17635.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$17648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$17669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$17691.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$17819.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$17841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$17857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$17870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$17895.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$17911.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$17924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$17945.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$17969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$18032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$18099.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$18121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$18137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$18150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$18175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$18191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$18204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$18225.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$18247.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$18314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$18330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$18343.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$18359.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$18376.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$18382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$18420.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$18433.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$18477.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$18493.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$18506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$18513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$5935.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6203.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6252.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6456.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6472.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$10003.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96929.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$6769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$6893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$6909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96925.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$6930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$6951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$6971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96921.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$7005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96944.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$7027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96940.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$7048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96932.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$7092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7202.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7276.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7519.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$7483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$7931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7650.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96923.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$7687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7845.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$7990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8242.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8310.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8365.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8373.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8414.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8423.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$8429.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8501.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8531.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8594.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8655.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8702.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8775.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$8790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$8799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8807.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$8816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8862.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8882.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8910.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8957.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$8398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9035.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$9057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9087.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9006.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9110.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9159.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$9174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9200.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9231.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9265.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$9285.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9355.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9388.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9406.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$8472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9487.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9498.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9518.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9542.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9566.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9624.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9653.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9705.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9792.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$9829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9837.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9849.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$15669.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96753.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96749.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96759.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96799.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96813.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96743$lut$aiger96742$8190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$9363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96743$lut$aiger96742$9504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96889.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96743$lut$aiger96742$7901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96912.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$96743$lut$aiger96742$7911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96937.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96941.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96945.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Removed 0 unused cells and 11004 unused wires.

21.45. Executing AUTONAME pass.
Renamed 385185 objects in module top (277 iterations).
<suppressed ~13757 debug messages>

21.46. Executing HIERARCHY pass (managing design hierarchy).

21.46.1. Analyzing design hierarchy..
Top module:  \top

21.46.2. Analyzing design hierarchy..
Top module:  \top
Removed 0 unused modules.

21.47. Printing statistics.

=== top ===

   Number of wires:               5730
   Number of wire bits:          15992
   Number of public wires:        5730
   Number of public wire bits:   15992
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               8730
     $_TBUF_                         5
     CCU2C                         165
     L6MUX21                       407
     LUT4                         5287
     PFUMX                        1052
     TRELLIS_DPR16X4               512
     TRELLIS_FF                   1302

21.48. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

21.49. Executing JSON backend.

Warnings: 258 unique messages, 259 total
End of script. Logfile hash: f9cc3fd5f6, CPU: user 8.62s system 0.12s, MEM: 221.78 MB peak
Yosys 0.36+8 (git sha1 fb4cbfa73, clang 10.0.0-4ubuntu1 -fPIC -Os)
Time spent: 40% 1x abc9_exe (6 sec), 12% 11x techmap (1 sec), ...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (NextPNR)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --ignore-loops --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz
Warning: IO 'gpios[4]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[3]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[2]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[1]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[0]' is unconstrained in LPF and will be automatically placed

Info: Logic utilisation before packing:
Info:     Total LUT4s:      8689/43848    19%
Info:         logic LUTs:   5287/43848    12%
Info:         carry LUTs:    330/43848     0%
Info:           RAM LUTs:   2048/ 5481    37%
Info:          RAMW LUTs:   1024/10962     9%

Info:      Total DFFs:      1302/43848     2%

Info: Packing IOs..
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y.Y
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     298 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info:     promoting clock net clk_o to global network
Info:     promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0xcf017e8b

Info: Device utilisation:
Info: 	          TRELLIS_IO:    17/  245     6%
Info: 	                DCCA:     2/   56     3%
Info: 	              DP16KD:     0/  108     0%
Info: 	          MULT18X18D:     0/   72     0%
Info: 	              ALU54B:     0/   36     0%
Info: 	             EHXPLLL:     0/    4     0%
Info: 	             EXTREFB:     0/    2     0%
Info: 	                DCUA:     0/    2     0%
Info: 	           PCSCLKDIV:     0/    2     0%
Info: 	             IOLOGIC:     0/  160     0%
Info: 	            SIOLOGIC:     0/   85     0%
Info: 	                 GSR:     0/    1     0%
Info: 	               JTAGG:     0/    1     0%
Info: 	                OSCG:     0/    1     0%
Info: 	               SEDGA:     0/    1     0%
Info: 	                 DTR:     0/    1     0%
Info: 	             USRMCLK:     0/    1     0%
Info: 	             CLKDIVF:     0/    4     0%
Info: 	           ECLKSYNCB:     0/   10     0%
Info: 	             DLLDELD:     0/    8     0%
Info: 	              DDRDLL:     0/    4     0%
Info: 	             DQSBUFM:     0/   10     0%
Info: 	     TRELLIS_ECLKBUF:     0/    8     0%
Info: 	        ECLKBRIDGECS:     0/    2     0%
Info: 	                DCSC:     0/    2     0%
Info: 	          TRELLIS_FF:  1302/43848     2%
Info: 	        TRELLIS_COMB:  8752/43848    19%
Info: 	        TRELLIS_RAMW:   512/ 5481     9%

Info: Placed 12 cells based on constraints.
Info: Creating initial analytic placement for 5365 cells, random placement wirelen = 447552.
Info:     at initial placer iter 0, wirelen = 2449
Info:     at initial placer iter 1, wirelen = 2489
Info:     at initial placer iter 2, wirelen = 1965
Info:     at initial placer iter 3, wirelen = 2357
Info: Running main analytical placer, max placement attempts per cell = 14005278.
Info:     at iteration #1, type ALL: wirelen solved = 2085, spread = 65436, legal = 66229; time = 0.26s
Info:     at iteration #2, type ALL: wirelen solved = 6997, spread = 44414, legal = 45567; time = 0.26s
Info:     at iteration #3, type ALL: wirelen solved = 11712, spread = 42262, legal = 43587; time = 0.26s
Info:     at iteration #4, type ALL: wirelen solved = 15117, spread = 44584, legal = 45425; time = 0.25s
Info:     at iteration #5, type ALL: wirelen solved = 18077, spread = 42326, legal = 43150; time = 0.25s
Info:     at iteration #6, type ALL: wirelen solved = 19030, spread = 42412, legal = 43555; time = 0.24s
Info:     at iteration #7, type ALL: wirelen solved = 20185, spread = 37819, legal = 39424; time = 0.24s
Info:     at iteration #8, type ALL: wirelen solved = 20032, spread = 39799, legal = 40749; time = 0.24s
Info:     at iteration #9, type ALL: wirelen solved = 21754, spread = 38085, legal = 39166; time = 0.24s
Info:     at iteration #10, type ALL: wirelen solved = 22415, spread = 37200, legal = 38295; time = 0.24s
Info:     at iteration #11, type ALL: wirelen solved = 22642, spread = 39189, legal = 39958; time = 0.24s
Info:     at iteration #12, type ALL: wirelen solved = 23578, spread = 36552, legal = 37644; time = 0.24s
Info:     at iteration #13, type ALL: wirelen solved = 22758, spread = 36817, legal = 37906; time = 0.23s
Info:     at iteration #14, type ALL: wirelen solved = 23153, spread = 36896, legal = 37959; time = 0.23s
Info:     at iteration #15, type ALL: wirelen solved = 23882, spread = 37013, legal = 38017; time = 0.23s
Info:     at iteration #16, type ALL: wirelen solved = 25264, spread = 36423, legal = 37389; time = 0.23s
Info:     at iteration #17, type ALL: wirelen solved = 25419, spread = 36286, legal = 37407; time = 0.23s
Info:     at iteration #18, type ALL: wirelen solved = 25159, spread = 35327, legal = 36588; time = 0.23s
Info:     at iteration #19, type ALL: wirelen solved = 24823, spread = 35816, legal = 36688; time = 0.23s
Info:     at iteration #20, type ALL: wirelen solved = 25525, spread = 34377, legal = 35616; time = 0.23s
Info:     at iteration #21, type ALL: wirelen solved = 24876, spread = 35098, legal = 36287; time = 0.23s
Info:     at iteration #22, type ALL: wirelen solved = 25421, spread = 36401, legal = 37399; time = 0.23s
Info:     at iteration #23, type ALL: wirelen solved = 26180, spread = 35377, legal = 36482; time = 0.23s
Info:     at iteration #24, type ALL: wirelen solved = 25922, spread = 35438, legal = 36616; time = 0.23s
Info:     at iteration #25, type ALL: wirelen solved = 25764, spread = 34857, legal = 36085; time = 0.23s
Info: HeAP Placer Time: 9.23s
Info:   of which solving equations: 5.40s
Info:   of which spreading cells: 0.83s
Info:   of which strict legalisation: 0.25s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 9119, wirelen = 35616
Info:   at iteration #5: temp = 0.000000, timing cost = 12729, wirelen = 31186
Info:   at iteration #10: temp = 0.000000, timing cost = 13901, wirelen = 29881
Info:   at iteration #15: temp = 0.000000, timing cost = 12787, wirelen = 29374
Info:   at iteration #20: temp = 0.000000, timing cost = 13004, wirelen = 29157
Info:   at iteration #24: temp = 0.000000, timing cost = 12985, wirelen = 29058 
Info: SA placement time 22.50s

Info: Max frequency for clock             '$glbnet$clk_o': 29.56 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 146.33 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.90 ns
Info: Max delay <async>                           -> posedge $glbnet$clk_o            : 13.72 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 15.64 ns
Info: Max delay posedge $glbnet$clk_o             -> <async>                          : 12.16 ns

Info: Slack histogram:
Info:  legend: * represents 105 endpoint(s)
Info:          + represents [1,105) endpoint(s)
Info: [ 33166,  35637) |+
Info: [ 35637,  38108) |+
Info: [ 38108,  40579) |+
Info: [ 40579,  43050) | 
Info: [ 43050,  45521) | 
Info: [ 45521,  47992) | 
Info: [ 47992,  50463) |+
Info: [ 50463,  52934) |+
Info: [ 52934,  55405) |+
Info: [ 55405,  57876) |*****+
Info: [ 57876,  60347) |*************+
Info: [ 60347,  62818) |************************************************************ 
Info: [ 62818,  65289) |************************************+
Info: [ 65289,  67760) |***+
Info: [ 67760,  70231) |*+
Info: [ 70231,  72702) |******+
Info: [ 72702,  75173) |****+
Info: [ 75173,  77644) |********+
Info: [ 77644,  80115) |*+
Info: [ 80115,  82586) |+
Info: Checksum: 0xff348508
Info: Routing globals...
Info:     routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info:     routing clock net $glbnet$clk_o using global 1

Info: Routing..
Info: Setting up routing queue.
Info: Routing 42482 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:       1000 |      283        716 |  283   716 |     41934|       0.74       0.74|
Info:       2000 |      456       1543 |  173   827 |     41548|       0.16       0.90|
Info:       3000 |      644       2355 |  188   812 |     41142|       0.17       1.07|
Info:       4000 |      819       3180 |  175   825 |     40748|       0.16       1.23|
Info:       5000 |     1037       3962 |  218   782 |     40280|       0.16       1.39|
Info:       6000 |     1174       4825 |  137   863 |     40023|       0.15       1.54|
Info:       7000 |     1348       5651 |  174   826 |     39601|       0.17       1.72|
Info:       8000 |     1515       6484 |  167   833 |     39238|       0.19       1.90|
Info:       9000 |     1696       7303 |  181   819 |     39405|       0.19       2.09|
Info:      10000 |     1810       8189 |  114   886 |     39182|       0.17       2.26|
Info:      11000 |     1891       9108 |   81   919 |     39382|       0.20       2.46|
Info:      12000 |     2023       9976 |  132   868 |     39726|       0.18       2.64|
Info:      13000 |     2177      10822 |  154   846 |     39397|       0.19       2.83|
Info:      14000 |     2282      11717 |  105   895 |     39390|       0.18       3.01|
Info:      15000 |     2452      12547 |  170   830 |     38978|       0.21       3.22|
Info:      16000 |     2659      13340 |  207   793 |     38642|       0.19       3.40|
Info:      17000 |     2865      14134 |  206   794 |     38516|       0.19       3.59|
Info:      18000 |     3016      14983 |  151   849 |     38739|       0.16       3.75|
Info:      19000 |     3171      15828 |  155   845 |     38597|       0.16       3.92|
Info:      20000 |     3265      16734 |   94   906 |     38376|       0.17       4.08|
Info:      21000 |     3432      17567 |  167   833 |     38083|       0.17       4.25|
Info:      22000 |     3582      18417 |  150   850 |     37975|       0.16       4.41|
Info:      23000 |     3759      19240 |  177   823 |     37442|       0.18       4.59|
Info:      24000 |     3849      20150 |   90   910 |     38326|       0.18       4.77|
Info:      25000 |     3915      21084 |   66   934 |     38265|       0.17       4.94|
Info:      26000 |     4064      21935 |  149   851 |     38229|       0.19       5.13|
Info:      27000 |     4169      22830 |  105   895 |     37514|       0.17       5.30|
Info:      28000 |     4351      23648 |  182   818 |     37025|       0.18       5.47|
Info:      29000 |     4545      24454 |  194   806 |     36453|       0.19       5.66|
Info:      30000 |     4707      25292 |  162   838 |     36662|       0.19       5.85|
Info:      31000 |     4882      26117 |  175   825 |     36259|       0.17       6.03|
Info:      32000 |     5103      26896 |  221   779 |     35843|       0.18       6.21|
Info:      33000 |     5262      27737 |  159   841 |     35700|       0.18       6.38|
Info:      34000 |     5442      28557 |  180   820 |     35339|       0.16       6.55|
Info:      35000 |     5637      29362 |  195   805 |     35173|       0.20       6.74|
Info:      36000 |     5837      30162 |  200   800 |     35158|       0.19       6.94|
Info:      37000 |     6021      30978 |  184   816 |     34834|       0.20       7.14|
Info:      38000 |     6204      31795 |  183   817 |     34904|       0.18       7.32|
Info:      39000 |     6352      32647 |  148   852 |     34781|       0.18       7.51|
Info:      40000 |     6555      33444 |  203   797 |     34415|       0.18       7.69|
Info:      41000 |     6778      34221 |  223   777 |     34038|       0.19       7.88|
Info:      42000 |     6981      35018 |  203   797 |     33364|       0.18       8.06|
Info:      43000 |     7187      35812 |  206   794 |     32895|       0.17       8.23|
Info:      44000 |     7445      36554 |  258   742 |     32484|       0.20       8.44|
Info:      45000 |     7684      37315 |  239   761 |     32217|       0.20       8.64|
Info:      46000 |     7958      38041 |  274   726 |     31920|       0.19       8.83|
Info:      47000 |     8178      38821 |  220   780 |     31386|       0.21       9.03|
Info:      48000 |     8359      39640 |  181   819 |     31247|       0.19       9.22|
Info:      49000 |     8586      40413 |  227   773 |     31065|       0.20       9.42|
Info:      50000 |     8810      41189 |  224   776 |     30590|       0.19       9.61|
Info:      51000 |     9045      41954 |  235   765 |     30178|       0.19       9.80|
Info:      52000 |     9259      42740 |  214   786 |     29845|       0.20      10.00|
Info:      53000 |     9473      43526 |  214   786 |     29474|       0.20      10.20|
Info:      54000 |     9749      44250 |  276   724 |     29054|       0.22      10.42|
Info:      55000 |     9968      45031 |  219   781 |     28775|       0.21      10.63|
Info:      56000 |    10194      45805 |  226   774 |     28507|       0.22      10.85|
Info:      57000 |    10509      46490 |  315   685 |     28318|       0.22      11.07|
Info:      58000 |    10762      47237 |  253   747 |     27919|       0.20      11.27|
Info:      59000 |    11007      47992 |  245   755 |     27818|       0.22      11.48|
Info:      60000 |    11296      48703 |  289   711 |     27739|       0.22      11.70|
Info:      61000 |    11471      49528 |  175   825 |     27292|       0.21      11.91|
Info:      62000 |    11702      50297 |  231   769 |     26965|       0.25      12.16|
Info:      63000 |    11990      51009 |  288   712 |     26488|       0.22      12.39|
Info:      64000 |    12219      51780 |  229   771 |     26180|       0.22      12.60|
Info:      65000 |    12523      52476 |  304   696 |     25830|       0.24      12.84|
Info:      66000 |    12861      53138 |  338   662 |     25519|       0.26      13.10|
Info:      67000 |    13172      53827 |  311   689 |     25093|       0.24      13.34|
Info:      68000 |    13489      54510 |  317   683 |     24701|       0.22      13.56|
Info:      69000 |    13787      55212 |  298   702 |     24250|       0.22      13.78|
Info:      70000 |    14063      55936 |  276   724 |     24232|       0.19      13.97|
Info:      71000 |    14355      56644 |  292   708 |     23898|       0.25      14.22|
Info:      72000 |    14643      57356 |  288   712 |     23753|       0.25      14.47|
Info:      73000 |    14943      58056 |  300   700 |     23427|       0.28      14.75|
Info:      74000 |    15349      58650 |  406   594 |     23191|       0.31      15.06|
Info:      75000 |    15544      59455 |  195   805 |     23864|       0.21      15.27|
Info:      76000 |    15620      60379 |   76   924 |     23206|       0.17      15.44|
Info:      77000 |    15988      61011 |  368   632 |     22946|       0.25      15.69|
Info:      78000 |    16309      61690 |  321   679 |     22621|       0.23      15.92|
Info:      79000 |    16594      62405 |  285   715 |     22297|       0.24      16.17|
Info:      80000 |    16908      63091 |  314   686 |     22197|       0.23      16.40|
Info:      81000 |    17238      63761 |  330   670 |     21835|       0.23      16.63|
Info:      82000 |    17571      64428 |  333   667 |     21559|       0.24      16.87|
Info:      83000 |    17895      65104 |  324   676 |     21404|       0.25      17.11|
Info:      84000 |    18206      65793 |  311   689 |     21667|       0.23      17.34|
Info:      85000 |    18492      66507 |  286   714 |     21088|       0.25      17.59|
Info:      86000 |    18842      67157 |  350   650 |     21286|       0.22      17.81|
Info:      87000 |    19050      67949 |  208   792 |     21611|       0.24      18.05|
Info:      88000 |    19191      68808 |  141   859 |     21233|       0.21      18.26|
Info:      89000 |    19498      69501 |  307   693 |     20919|       0.26      18.52|
Info:      90000 |    19822      70177 |  324   676 |     20758|       0.24      18.76|
Info:      91000 |    20174      70825 |  352   648 |     20476|       0.26      19.01|
Info:      92000 |    20521      71478 |  347   653 |     20316|       0.28      19.30|
Info:      93000 |    20923      72076 |  402   598 |     20231|       0.25      19.55|
Info:      94000 |    21212      72787 |  289   711 |     20067|       0.25      19.80|
Info:      95000 |    21618      73381 |  406   594 |     19851|       0.27      20.07|
Info:      96000 |    22036      73963 |  418   582 |     19642|       0.24      20.31|
Info:      97000 |    22489      74510 |  453   547 |     19325|       0.25      20.56|
Info:      98000 |    22984      75015 |  495   505 |     19110|       0.25      20.81|
Info:      99000 |    23335      75664 |  351   649 |     19019|       0.25      21.06|
Info:     100000 |    23812      76187 |  477   523 |     18830|       0.27      21.33|
Info:     101000 |    24235      76764 |  423   577 |     18669|       0.27      21.59|
Info:     102000 |    24548      77451 |  313   687 |     18591|       0.24      21.83|
Info:     103000 |    24773      78226 |  225   775 |     18511|       0.22      22.05|
Info:     104000 |    25203      78796 |  430   570 |     18271|       0.27      22.32|
Info:     105000 |    25621      79378 |  418   582 |     17969|       0.27      22.59|
Info:     106000 |    26174      79825 |  553   447 |     17741|       0.27      22.86|
Info:     107000 |    26581      80418 |  407   593 |     17609|       0.25      23.11|
Info:     108000 |    27162      80837 |  581   419 |     17411|       0.25      23.36|
Info:     109000 |    27737      81262 |  575   425 |     17271|       0.27      23.63|
Info:     110000 |    28356      81643 |  619   381 |     17071|       0.26      23.89|
Info:     111000 |    29016      81983 |  660   340 |     16846|       0.25      24.13|
Info:     112000 |    29584      82415 |  568   432 |     16627|       0.28      24.41|
Info:     113000 |    30180      82819 |  596   404 |     16491|       0.26      24.68|
Info:     114000 |    30766      83233 |  586   414 |     16416|       0.26      24.93|
Info:     115000 |    31197      83802 |  431   569 |     16335|       0.28      25.21|
Info:     116000 |    31592      84407 |  395   605 |     16176|       0.25      25.46|
Info:     117000 |    31979      85020 |  387   613 |     16203|       0.27      25.73|
Info:     118000 |    32379      85620 |  400   600 |     16017|       0.28      26.01|
Info:     119000 |    32833      86166 |  454   546 |     16036|       0.26      26.27|
Info:     120000 |    33256      86743 |  423   577 |     15842|       0.29      26.56|
Info:     121000 |    33824      87175 |  568   432 |     15624|       0.26      26.82|
Info:     122000 |    34335      87664 |  511   489 |     15432|       0.26      27.08|
Info:     123000 |    34778      88197 |  443   533 |     15238|       0.29      27.38|
Info:     124000 |    35134      88824 |  356   627 |     16642|       0.26      27.63|
Info:     125000 |    35218      89740 |   84   916 |     15818|       0.21      27.84|
Info:     126000 |    35379      90579 |  161   839 |     15272|       0.23      28.07|
Info:     127000 |    35666      91292 |  287   713 |     16341|       0.27      28.34|
Info:     128000 |    35837      92121 |  171   829 |     15812|       0.24      28.58|
Info:     129000 |    36048      92910 |  211   789 |     15156|       0.24      28.81|
Info:     130000 |    36618      93282 |  570   372 |     14893|       0.24      29.06|
Info:     131000 |    37210      93658 |  592   376 |     14788|       0.28      29.34|
Info:     132000 |    37467      94365 |  257   707 |     14828|       0.29      29.63|
Info:     133000 |    37905      94909 |  438   544 |     14449|       0.26      29.88|
Info:     134000 |    38507      95238 |  602   329 |     14173|       0.24      30.12|
Info:     135000 |    39111      95572 |  604   334 |     13894|       0.26      30.38|
Info:     136000 |    39761      95861 |  650   289 |     13631|       0.25      30.64|
Info:     137000 |    40343      96248 |  582   387 |     13456|       0.31      30.95|
Info:     138000 |    40860      96677 |  517   429 |     13195|       0.25      31.20|
Info:     139000 |    41371      97102 |  511   425 |     12883|       0.27      31.46|
Info:     140000 |    41814      97617 |  443   515 |     12652|       0.25      31.72|
Info:     141000 |    42307      98067 |  493   450 |     12303|       0.31      32.02|
Info:     142000 |    42655      98633 |  348   566 |     11824|       0.21      32.23|
Info:     143000 |    42928      99255 |  273   622 |     11174|       0.21      32.44|
Info:     144000 |    43048     100119 |  120   864 |     10303|       0.13      32.57|
Info:     145000 |    43160     100997 |  112   878 |      9460|       0.14      32.70|
Info:     146000 |    43250     101904 |   90   907 |      8614|       0.17      32.87|
Info:     147000 |    43291     102859 |   41   955 |      7659|       0.09      32.97|
Info:     148000 |    43427     103718 |  136   859 |      6951|       0.18      33.14|
Info:     149000 |    43702     104442 |  275   724 |      6606|       0.29      33.44|
Info:     150000 |    44086     105058 |  384   616 |      6564|       0.29      33.73|
Info:     151000 |    44392     105752 |  306   694 |      6112|       0.25      33.98|
Info:     152000 |    44517     106621 |  125   869 |      5288|       0.17      34.15|
Info:     153000 |    44654     107461 |  137   840 |      4444|       0.14      34.30|
Info:     154000 |    44919     108191 |  265   730 |      3874|       0.25      34.54|
Info:     155000 |    45349     108761 |  430   570 |      3860|       0.37      34.92|
Info:     156000 |    45712     109394 |  363   633 |      3433|       0.35      35.26|
Info:     157000 |    46147     109940 |  435   546 |      3098|       0.35      35.61|
Info:     158000 |    46601     110481 |  454   541 |      3004|       0.43      36.04|
Info:     159000 |    46981     111097 |  380   616 |      2613|       0.29      36.34|
Info:     160000 |    47437     111638 |  456   541 |      2207|       0.28      36.62|
Info:     161000 |    47927     112140 |  490   502 |      1977|       0.41      37.03|
Info:     162000 |    48362     112705 |  435   565 |      1846|       0.47      37.50|
Info:     163000 |    48808     113255 |  446   550 |      1461|       0.34      37.83|
Info:     164000 |    49287     113776 |  479   521 |      1203|       0.41      38.24|
Info:     165000 |    49758     114304 |  471   528 |       871|       0.35      38.59|
Info:     166000 |    50299     114754 |  541   450 |       617|       0.37      38.96|
Info:     167000 |    50632     115200 |  333   446 |       156|       0.26      39.22|
Info:     167272 |    50710     115317 |   78   117 |         0|       0.15      39.38|
Info: Routing complete.
Info: Router1 time 39.38s
Info: Checksum: 0xb137b3bd

Info: Critical path report for clock '$glbnet$clk_o' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_1.Q
Info:  1.5  2.0    Net SOC.Core.Control_Unit.nextstate_LUT4_Z_2_B_LUT4_Z_A[0] (33,26) -> (34,18)
Info:                Sink SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.B
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/core/core.v:97.14-113.2
Info:                  Risco-5/src/core/control_unit.v:46.11-46.16
Info:                  Risco-5/src/peripheral/soc.v:28.3-36.2
Info:  0.2  2.3  Source SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.F
Info:  1.4  3.7    Net SOC.Memory.address_LUT4_Z_C_LUT4_Z_D[2] (34,18) -> (28,5)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  4.0  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_LUT4_Z.F
Info:  1.5  5.4    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0 (28,5) -> (31,8)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.B
Info:  0.4  5.9  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  5.9    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (31,8) -> (31,8)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  5.9  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  5.9    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (31,8) -> (31,8)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  5.9  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  5.9    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (31,8) -> (31,8)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  5.9  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  5.9    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (31,8) -> (31,8)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.0  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.0    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (31,8) -> (31,8)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.0  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.0    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (31,8) -> (32,8)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.1  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.1    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (32,8) -> (32,8)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.1  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.1    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (32,8) -> (32,8)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.2  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.2    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (32,8) -> (32,8)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.2  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.2    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (32,8) -> (32,8)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.2  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.2    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (32,8) -> (32,8)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.2  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.2    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (32,8) -> (32,8)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.3  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.3    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (32,8) -> (32,8)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.3  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.3    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (32,8) -> (33,8)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.4  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.4    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (33,8) -> (33,8)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.4  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.4    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (33,8) -> (33,8)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.4  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.4    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (33,8) -> (33,8)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.4  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.4    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (33,8) -> (33,8)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.5  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.5    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (33,8) -> (33,8)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.5  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_B_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.5    Net $nextpnr_CCU2C_1$CIN (33,8) -> (33,8)
Info:                Sink $nextpnr_CCU2C_1$CCU2_COMB0.FCI
Info:  0.4  7.0  Source $nextpnr_CCU2C_1$CCU2_COMB0.F
Info:  2.9  9.9    Net SOC.Memory.address_LUT4_Z_1_C[1] (33,8) -> (11,29)
Info:                Sink SOC.Memory.address_LUT4_Z_1.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 10.1  Source SOC.Memory.address_LUT4_Z_1.F
Info:  2.1 12.2    Net SOC.slave_address[4] (11,29) -> (13,40)
Info:                Sink SOC.Memory.memory.0.216$DPRAM_COMB1.C
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/soc.v:21.5-21.18
Info:  0.2 12.5  Source SOC.Memory.memory.0.216$DPRAM_COMB1.F
Info:  0.9 13.4    Net SOC.Memory.memory.0.216_DO_2[3] (13,40) -> (13,38)
Info:                Sink SOC.Memory.memory.0.208_DO_1_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 13.6  Source SOC.Memory.memory.0.208_DO_1_LUT4_Z.F
Info:  0.7 14.4    Net SOC.Memory.memory.0.208_DO_1[4] (13,38) -> (13,37)
Info:                Sink SOC.Memory.memory.0.200_DO_2_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 14.6  Source SOC.Memory.memory.0.200_DO_2_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  0.7 15.3    Net SOC.Memory.memory.0.200_DO_2_LUT4_C_Z[3] (13,37) -> (14,36)
Info:                Sink SOC.Memory.memory.0.200_DO_2_LUT4_C_Z_LUT4_B.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 15.5  Source SOC.Memory.memory.0.200_DO_2_LUT4_C_Z_LUT4_B.F
Info:  0.5 16.0    Net SOC.Memory.memory.0.264_DO_2_PFUMX_C0_Z[3] (14,36) -> (14,35)
Info:                Sink SOC.Memory.memory.0.0_DO_2_LUT4_C_Z_LUT4_A_Z_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 16.3  Source SOC.Memory.memory.0.0_DO_2_LUT4_C_Z_LUT4_A_Z_LUT4_Z.F
Info:  0.9 17.2    Net SOC.Memory.memory.0.0_DO_2_LUT4_C_Z_LUT4_A_Z[3] (14,35) -> (18,35)
Info:                Sink SOC.Core.read_data_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_B_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 17.4  Source SOC.Core.read_data_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_B_LUT4_Z.F
Info:  0.4 17.8    Net SOC.Core.read_data_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_B[2] (18,35) -> (18,35)
Info:                Sink SOC.Core.read_data_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 18.1  Source SOC.Core.read_data_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z.F
Info:  1.1 19.2    Net SOC.Core.read_data_LUT4_Z_1_D_LUT4_Z_D[3] (18,35) -> (18,29)
Info:                Sink SOC.Core.read_data_LUT4_Z_1_D_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 19.4  Source SOC.Core.read_data_LUT4_Z_1_D_LUT4_Z.F
Info:  1.3 20.7    Net SOC.Core.read_data_LUT4_Z_1_D[3] (18,29) -> (16,24)
Info:                Sink SOC.Core.read_data_LUT4_Z_1.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 20.9  Source SOC.Core.read_data_LUT4_Z_1.F
Info:  1.1 22.0    Net SOC.read_data[1] (16,24) -> (26,24)
Info:                Sink SOC.Core.instruction_register_TRELLIS_FF_Q_30.M
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/soc.v:20.34-20.43
Info:  0.0 22.0  Setup SOC.Core.instruction_register_TRELLIS_FF_Q_30.M
Info: 4.9 ns logic, 17.1 ns routing

Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source ClkDivider.clk_counter_TRELLIS_FF_Q_27.Q
Info:  1.2  1.7    Net ClkDivider.clk_counter[4] (3,3) -> (4,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.B
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:14.26-14.37
Info:  0.4  2.1  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.1    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (4,2) -> (4,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.1  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.1    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (4,2) -> (4,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.2  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.2    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (4,2) -> (4,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.2  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.2    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (4,2) -> (4,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.3  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.3    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (4,2) -> (4,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.3  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.3    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (4,2) -> (5,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.3  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.3    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (5,2) -> (5,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.3  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.3    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (5,2) -> (5,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.4  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.4    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (5,2) -> (5,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.4  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.4    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (5,2) -> (5,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.5  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.5    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (5,2) -> (5,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.5  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.5    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (5,2) -> (5,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.5  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.5    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (5,2) -> (5,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.5  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.5    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (5,2) -> (6,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.6  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.6    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (6,2) -> (6,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.6  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.6    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (6,2) -> (6,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.7  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.7    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (6,2) -> (6,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.7  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.7    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (6,2) -> (6,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.8  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.8    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (6,2) -> (6,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.8  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.8    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (6,2) -> (6,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.8  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.8    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (6,2) -> (6,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.8  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.8    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (6,2) -> (7,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.9  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.9    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (7,2) -> (7,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.9  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.9    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (7,2) -> (7,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  3.0  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  3.0    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (7,2) -> (7,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  3.0  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  3.0    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN (7,2) -> (7,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  3.0  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  3.0    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (7,2) -> (7,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  3.0  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  3.0    Net $nextpnr_CCU2C_7$CIN (7,2) -> (7,2)
Info:                Sink $nextpnr_CCU2C_7$CCU2_COMB0.FCI
Info:  0.4  3.5  Source $nextpnr_CCU2C_7$CCU2_COMB0.F
Info:  0.5  4.0    Net reset_LUT4_B_C_LUT4_Z_D (7,2) -> (7,4)
Info:                Sink reset_LUT4_B_C_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  4.2  Source reset_LUT4_B_C_LUT4_Z.F
Info:  0.7  4.9    Net reset_LUT4_B_C[1] (7,4) -> (5,4)
Info:                Sink reset_LUT4_B.C
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  5.1  Source reset_LUT4_B.F
Info:  0.7  5.8    Net reset_LUT4_B_Z (5,4) -> (6,3)
Info:                Sink ClkDivider.clk_counter_TRELLIS_FF_Q_9.LSR
Info:  0.4  6.2  Setup ClkDivider.clk_counter_TRELLIS_FF_Q_9.LSR
Info: 3.2 ns logic, 3.0 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info:  0.0  0.0  Source reset$tr_io.O
Info:  3.3  3.3    Net reset$TRELLIS_IO_IN (0,29) -> (5,4)
Info:                Sink reset_LUT4_B.B
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  3.5  Source reset_LUT4_B.F
Info:  0.7  4.2    Net reset_LUT4_B_Z (5,4) -> (6,3)
Info:                Sink ClkDivider.clk_counter_TRELLIS_FF_Q_9.LSR
Info:  0.4  4.6  Setup ClkDivider.clk_counter_TRELLIS_FF_Q_9.LSR
Info: 0.7 ns logic, 4.0 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk_o':
Info: curr total
Info:  0.0  0.0  Source gpios[0]$tr_io.O
Info:  4.1  4.1    Net gpios[0]$TRELLIS_IO_IN (90,35) -> (23,32)
Info:                Sink SOC.GPIOS.Gpios[0].direction_LUT4_C.A
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:7.16-7.21
Info:  0.2  4.3  Source SOC.GPIOS.Gpios[0].direction_LUT4_C.F
Info:  0.0  4.3    Net SOC.GPIOS.Gpios[0].direction_LUT4_C_Z (23,32) -> (23,32)
Info:                Sink SOC.GPIOS.Gpios[0].direction_LUT4_C_1.F1
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info:  0.2  4.5  Source SOC.GPIOS.Gpios[0].direction_LUT4_C_1.OFX
Info:  0.9  5.4    Net SOC.GPIOS.Gpios[0].direction_LUT4_C_Z_PFUMX_ALUT_Z[1] (23,32) -> (23,32)
Info:                Sink SOC.Core.read_data_LUT4_Z.B
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  5.6  Source SOC.Core.read_data_LUT4_Z.F
Info:  1.3  6.9    Net SOC.read_data[0] (23,32) -> (26,24)
Info:                Sink SOC.Core.instruction_register_TRELLIS_FF_Q_31.M
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/soc.v:20.34-20.43
Info:  0.0  6.9  Setup SOC.Core.instruction_register_TRELLIS_FF_Q_31.M
Info: 0.6 ns logic, 6.3 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source ClkDivider.clk_o_auto_TRELLIS_FF_Q.Q
Info:  4.2  4.7    Net clk_o (6,4) -> (63,17)
Info:                Sink led_LUT4_Z_3.D
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:10.6-10.11
Info:  0.2  5.0  Source led_LUT4_Z_3.F
Info:  2.0  7.0    Net led[7]$TRELLIS_IO_OUT (63,17) -> (90,20)
Info:                Sink led[7]$tr_io.I
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 6.2 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk_o' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source SOC.GPIOS.Gpios[0].direction_TRELLIS_FF_Q.Q
Info:  2.7  3.2    Net SOC.GPIOS.gpio_direction[0] (32,29) -> (68,35)
Info:                Sink gpios_$_TBUF__Y_4_E_LUT4_Z.D
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/gpios.v:14.19-14.33
Info:                  Risco-5/src/peripheral/soc.v:111.3-120.2
Info:  0.2  3.4  Source gpios_$_TBUF__Y_4_E_LUT4_Z.F
Info:  1.0  4.5    Net gpios_$_TBUF__Y_4_E (68,35) -> (74,35)
Info:                Sink gpios[0]$tr_io$invert_T.A
Info:  0.2  4.7  Source gpios[0]$tr_io$invert_T.F
Info:  1.6  6.2    Net gpios[0]$tr_io$invert_T$conn$Z (74,35) -> (90,35)
Info:                Sink gpios[0]$tr_io.T
Info: 1.0 ns logic, 5.3 ns routing

Info: Max frequency for clock             '$glbnet$clk_o': 45.48 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 161.50 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.62 ns
Info: Max delay <async>                           -> posedge $glbnet$clk_o            : 6.90 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 6.99 ns
Info: Max delay posedge $glbnet$clk_o             -> <async>                          : 6.25 ns

Info: Slack histogram:
Info:  legend: * represents 158 endpoint(s)
Info:          + represents [1,158) endpoint(s)
Info: [ 33808,  36229) |+
Info: [ 36229,  38650) |+
Info: [ 38650,  41071) |+
Info: [ 41071,  43492) | 
Info: [ 43492,  45913) | 
Info: [ 45913,  48334) | 
Info: [ 48334,  50755) | 
Info: [ 50755,  53176) | 
Info: [ 53176,  55597) | 
Info: [ 55597,  58018) | 
Info: [ 58018,  60439) | 
Info: [ 60439,  62860) |+
Info: [ 62860,  65281) |+
Info: [ 65281,  67702) |**+
Info: [ 67702,  70123) |****************+
Info: [ 70123,  72544) |************************************************************ 
Info: [ 72544,  74965) |+
Info: [ 74965,  77386) |******+
Info: [ 77386,  79807) |*******+
Info: [ 79807,  82228) |+

5 warnings, 0 errors

Info: Program finished normally.
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
[Pipeline] sh
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
Found 1 compatible device:
	0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
+ echo gravando na tang nano
gravando na tang nano
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }

Loading: [=====                                             ] 9.54%
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Loading: [====================                              ] 38.14%
Loading: [========================                          ] 47.68%
Loading: [=============================                     ] 57.21%
Loading: [==================================                ] 66.75%
Loading: [=======================================           ] 76.29%
Loading: [===========================================       ] 85.82%
Loading: [================================================  ] 95.36%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
[Pipeline] sh
+ echo testando na ecp5
testando na ecp5
[Pipeline] }
Lock released on resource [ecp5]
+ echo testando na tang nano
testando na tang nano
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // stage
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS