Console Output

Started by user Julio Nunes Avelar
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/Risco 5
[Pipeline] {
[Pipeline] stage
[Pipeline] { (git_clone)
[Pipeline] sh
+ rm -Rf Risco-5/ build/
[Pipeline] sh
+ git clone https://github.com/JN513/Risco-5
Cloning into 'Risco-5'...
[Pipeline] sh
+ cd Risco-5
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Yosys)
[Pipeline] sh
+ mkdir -p build
[Pipeline] sh
+ /eda/oss-cad-suite/bin/yosys -p                          read_verilog Risco-5/fpga/ecp5/*.v;                         read_verilog Risco-5/debug/clk_divider.v;                         read_verilog Risco-5/src/core/*.v;                         read_verilog Risco-5/src/peripheral/*.v;                         synth_ecp5 -json ./build/out.json -abc9                     

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.36+8 (git sha1 fb4cbfa73, clang 10.0.0-4ubuntu1 -fPIC -Os)


-- Running command `                         read_verilog Risco-5/fpga/ecp5/*.v;                         read_verilog Risco-5/debug/clk_divider.v;                         read_verilog Risco-5/src/core/*.v;                         read_verilog Risco-5/src/peripheral/*.v;                         synth_ecp5 -json ./build/out.json -abc9                     ' --

1. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/main.v
Parsing Verilog input from `Risco-5/fpga/ecp5/main.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/reset.v
Parsing Verilog input from `Risco-5/fpga/ecp5/reset.v' to AST representation.
Generating RTLIL representation for module `\ResetBootSystem'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: Risco-5/debug/clk_divider.v
Parsing Verilog input from `Risco-5/debug/clk_divider.v' to AST representation.
Generating RTLIL representation for module `\ClkDivider'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: Risco-5/src/core/alu.v
Parsing Verilog input from `Risco-5/src/core/alu.v' to AST representation.
Generating RTLIL representation for module `\ALU'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: Risco-5/src/core/alu_control.v
Parsing Verilog input from `Risco-5/src/core/alu_control.v' to AST representation.
Generating RTLIL representation for module `\ALU_Control'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: Risco-5/src/core/control_unit.v
Parsing Verilog input from `Risco-5/src/core/control_unit.v' to AST representation.
Generating RTLIL representation for module `\Control_Unit'.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: Risco-5/src/core/core.v
Parsing Verilog input from `Risco-5/src/core/core.v' to AST representation.
Generating RTLIL representation for module `\Core'.
Risco-5/src/core/core.v:76: Warning: Identifier `\pc_source' is implicitly declared.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: Risco-5/src/core/immediate_generator.v
Parsing Verilog input from `Risco-5/src/core/immediate_generator.v' to AST representation.
Generating RTLIL representation for module `\Immediate_Generator'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: Risco-5/src/core/mux.v
Parsing Verilog input from `Risco-5/src/core/mux.v' to AST representation.
Generating RTLIL representation for module `\MUX'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: Risco-5/src/core/pc.v
Parsing Verilog input from `Risco-5/src/core/pc.v' to AST representation.
Generating RTLIL representation for module `\PC'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: Risco-5/src/core/registers.v
Parsing Verilog input from `Risco-5/src/core/registers.v' to AST representation.
Generating RTLIL representation for module `\Registers'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: Risco-5/src/peripheral/bus.v
Parsing Verilog input from `Risco-5/src/peripheral/bus.v' to AST representation.
Generating RTLIL representation for module `\BUS'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpio.v
Parsing Verilog input from `Risco-5/src/peripheral/gpio.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (Risco-5/src/peripheral/gpio.v:9)
Generating RTLIL representation for module `\GPIO'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpios.v
Parsing Verilog input from `Risco-5/src/peripheral/gpios.v' to AST representation.
Generating RTLIL representation for module `\GPIOS'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend: Risco-5/src/peripheral/leds.v
Parsing Verilog input from `Risco-5/src/peripheral/leds.v' to AST representation.
Generating RTLIL representation for module `\LEDs'.
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend: Risco-5/src/peripheral/memory.v
Parsing Verilog input from `Risco-5/src/peripheral/memory.v' to AST representation.
Generating RTLIL representation for module `\Memory'.
Successfully finished Verilog frontend.

17. Executing Verilog-2005 frontend: Risco-5/src/peripheral/soc.v
Parsing Verilog input from `Risco-5/src/peripheral/soc.v' to AST representation.
Generating RTLIL representation for module `\Risco_5_SOC'.
Successfully finished Verilog frontend.

18. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart.v
Parsing Verilog input from `Risco-5/src/peripheral/uart.v' to AST representation.
Generating RTLIL representation for module `\UART'.
Successfully finished Verilog frontend.

19. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_rx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_rx'.
Successfully finished Verilog frontend.

20. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_tx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_tx'.
Successfully finished Verilog frontend.

21. Executing SYNTH_ECP5 pass.

21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.

21.3. Executing HIERARCHY pass (managing design hierarchy).

21.3.1. Finding top of design hierarchy..
root of   0 design levels: uart_tool_tx        
root of   0 design levels: uart_tool_rx        
root of   1 design levels: UART                
root of   2 design levels: Risco_5_SOC         
root of   0 design levels: Memory              
root of   0 design levels: LEDs                
root of   1 design levels: GPIOS               
root of   0 design levels: GPIO                
root of   0 design levels: BUS                 
root of   0 design levels: Registers           
root of   0 design levels: PC                  
root of   0 design levels: MUX                 
root of   0 design levels: Immediate_Generator 
root of   1 design levels: Core                
root of   0 design levels: Control_Unit        
root of   0 design levels: ALU_Control         
root of   0 design levels: ALU                 
root of   0 design levels: ClkDivider          
root of   0 design levels: ResetBootSystem     
root of   3 design levels: top                 
Automatically selected top as design top module.

21.3.2. Analyzing design hierarchy..
Top module:  \top
Used module:     \Risco_5_SOC
Used module:         \UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     \ResetBootSystem
Used module:     \ClkDivider
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \MEMORY_SIZE = 4096
Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000

21.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Risco_5_SOC'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \MEMORY_SIZE = 4096
Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000
Generating RTLIL representation for module `$paramod$f364a504a7e15f6f8a7a122a0a3044b25520ae7b\Risco_5_SOC'.
Parameter \CYCLES = 20

21.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'.
Parameter \CYCLES = 20
Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'.
Parameter \COUNTER_BITS = 32

21.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'.
Parameter \COUNTER_BITS = 32
Generating RTLIL representation for module `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600

21.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Generating RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

21.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \BOOT_ADDRESS = 0

21.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'.
Parameter \BOOT_ADDRESS = 0
Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.
Risco-5/src/core/core.v:76: Warning: Identifier `\pc_source' is implicitly declared.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

21.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

21.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.

21.3.11. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$f364a504a7e15f6f8a7a122a0a3044b25520ae7b\Risco_5_SOC
Used module:         \UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Found cached RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 4096

21.3.12. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory'.
Parameter \BOOT_ADDRESS = 0
Found cached RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.

21.3.13. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$f364a504a7e15f6f8a7a122a0a3044b25520ae7b\Risco_5_SOC
Used module:         $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Found cached RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Found cached RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.

21.3.14. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$f364a504a7e15f6f8a7a122a0a3044b25520ae7b\Risco_5_SOC
Used module:         $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000

21.3.15. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$f364a504a7e15f6f8a7a122a0a3044b25520ae7b\Risco_5_SOC
Used module:         $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000
Removing unused module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Removing unused module `\uart_tool_tx'.
Removing unused module `\uart_tool_rx'.
Removing unused module `\UART'.
Removing unused module `\Risco_5_SOC'.
Removing unused module `\Memory'.
Removing unused module `\GPIOS'.
Removing unused module `\GPIO'.
Removing unused module `\Core'.
Removing unused module `\ClkDivider'.
Removing unused module `\ResetBootSystem'.
Removed 11 unused modules.

21.4. Executing PROC pass (convert processes to netlists).

21.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$375'.
Found and cleaned up 1 empty switch in `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:0$638'.
Removing empty process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:0$638'.
Cleaned up 2 empty switches.

21.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$482 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$434 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$376 in module TRELLIS_DPR16X4.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:197$622 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:186$620 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:171$612 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:160$609 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:148$603 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:133$598 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:116$593 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:97$584 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:173$571 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:162$569 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:147$561 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:130$547 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:115$541 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:98$536 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/core.v:135$526 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:31$629 in module $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/leds.v:23$143 in module LEDs.
Marked 3 switch rules as full_case in process $proc$Risco-5/debug/clk_divider.v:25$496 in module $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.
Marked 5 switch rules as full_case in process $proc$Risco-5/fpga/ecp5/reset.v:24$485 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:155$69 in module Registers.
Removed 2 dead cases from process $proc$Risco-5/src/core/registers.v:81$68 in module Registers.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:81$68 in module Registers.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/pc.v:19$64 in module PC.
Removed 1 dead cases from process $proc$Risco-5/src/core/mux.v:10$63 in module MUX.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/mux.v:10$63 in module MUX.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/immediate_generator.v:7$60 in module Immediate_Generator.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:69$51 in module Control_Unit.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:52$48 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:44$47 in module Control_Unit.
Removed 1 dead cases from process $proc$Risco-5/src/core/alu_control.v:8$45 in module ALU_Control.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/alu_control.v:8$45 in module ALU_Control.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/alu.v:11$30 in module ALU.
Removed a total of 4 dead cases.

21.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 8 redundant assignments.
Promoted 131 assignments to connections.

21.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$483'.
  Set init value: \Q = 1'0
Found init rule in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$624'.
  Set init value: \i = 0
Found init rule in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$577'.
  Set init value: \i = 0
Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$529'.
  Set init value: \instruction_register = 0
  Set init value: \memory_register = 0
  Set init value: \alu_out_register = 0
  Set init value: \register_data_1 = 0
  Set init value: \register_data_2 = 0
Found init rule in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$146'.
  Set init value: \data = 33'000000000000000000000000000000000
Found init rule in `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:0$508'.
  Set init value: \clk_o_pulse = 1'0
  Set init value: \clk_o_auto = 1'0
  Set init value: \clk_counter = 0
Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:0$491'.
  Set init value: \reset_o = 1'0
  Set init value: \state = 2'01
  Set init value: \counter = 6'000000
Found init rule in `\Registers.$proc$Risco-5/src/core/registers.v:0$72'.
  Set init value: \register0 = 0
  Set init value: \register1 = 0
  Set init value: \register2 = 0
  Set init value: \register3 = 0
  Set init value: \register4 = 0
  Set init value: \register5 = 0
  Set init value: \register6 = 0
  Set init value: \register7 = 0
  Set init value: \register8 = 0
  Set init value: \register9 = 0
  Set init value: \register10 = 0
  Set init value: \register11 = 0
  Set init value: \register12 = 0
  Set init value: \register13 = 0
  Set init value: \register14 = 0
  Set init value: \register15 = 0
  Set init value: \register16 = 0
  Set init value: \register17 = 0
  Set init value: \register18 = 0
  Set init value: \register19 = 0
  Set init value: \register20 = 0
  Set init value: \register21 = 0
  Set init value: \register22 = 0
  Set init value: \register23 = 0
  Set init value: \register24 = 0
  Set init value: \register25 = 0
  Set init value: \register26 = 0
  Set init value: \register27 = 0
  Set init value: \register28 = 0
  Set init value: \register29 = 0
  Set init value: \register30 = 0
  Set init value: \register31 = 0
Found init rule in `\PC.$proc$Risco-5/src/core/pc.v:0$67'.
  Set init value: \PC_Register = 0
Found init rule in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$53'.
  Set init value: \state = 3'000
  Set init value: \pc_write_cond = 1'0
  Set init value: \pc_write = 1'0
  Set init value: \lorD = 1'0
  Set init value: \memory_read = 1'0
  Set init value: \memory_write = 1'0
  Set init value: \memory_to_reg = 1'0
  Set init value: \ir_write = 1'0
  Set init value: \pc_source = 1'0
  Set init value: \aluop = 2'00
  Set init value: \alu_src_a = 2'00
  Set init value: \alu_src_b = 2'00
  Set init value: \reg_write = 1'0
  Set init value: \nextstate = 3'000

21.4.5. Executing PROC_ARST pass (detect async resets in processes).

21.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~75 debug messages>

21.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$483'.
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$482'.
     1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$457'.
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$434'.
     1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$433_EN[3:0]$440
     2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$433_DATA[3:0]$439
     3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$433_ADDR[3:0]$438
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$400'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$376'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$374_EN[3:0]$382
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$374_DATA[3:0]$381
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$374_ADDR[3:0]$380
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$375'.
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$624'.
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$622'.
     1/2: $0\rxd_reg_0[0:0]
     2/2: $0\rxd_reg[0:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$620'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$612'.
     1/1: $0\cycle_counter[12:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$609'.
     1/1: $0\bit_sample[0:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$603'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$598'.
     1/11: $3\i[31:0]
     2/11: $0\recieved_data[7:0] [1]
     3/11: $0\recieved_data[7:0] [0]
     4/11: $0\recieved_data[7:0] [2]
     5/11: $0\recieved_data[7:0] [3]
     6/11: $0\recieved_data[7:0] [4]
     7/11: $0\recieved_data[7:0] [5]
     8/11: $0\recieved_data[7:0] [6]
     9/11: $0\recieved_data[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$593'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$584'.
     1/1: $0\uart_rx_data[7:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$577'.
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$571'.
     1/1: $0\txd_reg[0:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$569'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$561'.
     1/1: $0\cycle_counter[12:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$547'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$541'.
     1/11: $3\i[31:0]
     2/11: $0\data_to_send[7:0] [1]
     3/11: $0\data_to_send[7:0] [0]
     4/11: $0\data_to_send[7:0] [2]
     5/11: $0\data_to_send[7:0] [3]
     6/11: $0\data_to_send[7:0] [4]
     7/11: $0\data_to_send[7:0] [5]
     8/11: $0\data_to_send[7:0] [6]
     9/11: $0\data_to_send[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$536'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$529'.
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$526'.
     1/5: $0\alu_out_register[31:0]
     2/5: $0\register_data_2[31:0]
     3/5: $0\register_data_1[31:0]
     4/5: $0\memory_register[31:0]
     5/5: $0\instruction_register[31:0]
Creating decoders for process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$629'.
     1/3: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$636
     2/3: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_DATA[31:0]$635
     3/3: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_ADDR[31:0]$634
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$146'.
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$143'.
     1/1: $0\data[32:0]
Creating decoders for process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:0$508'.
Creating decoders for process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:46$506'.
Creating decoders for process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$496'.
     1/2: $0\clk_counter[31:0]
     2/2: $0\clk_o_auto[0:0]
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:0$491'.
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$485'.
     1/3: $0\counter[5:0]
     2/3: $0\state[1:0]
     3/3: $0\reset_o[0:0]
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:0$72'.
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
     1/32: $0\register31[31:0]
     2/32: $0\register30[31:0]
     3/32: $0\register29[31:0]
     4/32: $0\register28[31:0]
     5/32: $0\register27[31:0]
     6/32: $0\register26[31:0]
     7/32: $0\register25[31:0]
     8/32: $0\register24[31:0]
     9/32: $0\register23[31:0]
    10/32: $0\register22[31:0]
    11/32: $0\register21[31:0]
    12/32: $0\register20[31:0]
    13/32: $0\register19[31:0]
    14/32: $0\register18[31:0]
    15/32: $0\register17[31:0]
    16/32: $0\register16[31:0]
    17/32: $0\register15[31:0]
    18/32: $0\register14[31:0]
    19/32: $0\register13[31:0]
    20/32: $0\register12[31:0]
    21/32: $0\register11[31:0]
    22/32: $0\register10[31:0]
    23/32: $0\register9[31:0]
    24/32: $0\register8[31:0]
    25/32: $0\register7[31:0]
    26/32: $0\register6[31:0]
    27/32: $0\register5[31:0]
    28/32: $0\register4[31:0]
    29/32: $0\register3[31:0]
    30/32: $0\register2[31:0]
    31/32: $0\register1[31:0]
    32/32: $0\register0[31:0]
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:81$68'.
     1/2: $1\readData2[31:0]
     2/2: $1\readData1[31:0]
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:0$67'.
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:19$64'.
     1/1: $1\PC_Register[31:0]
Creating decoders for process `\MUX.$proc$Risco-5/src/core/mux.v:10$63'.
     1/1: $1\S[31:0]
Creating decoders for process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$60'.
     1/1: $1\immediate[31:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$53'.
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
     1/23: $2\reg_write[0:0]
     2/23: $2\memory_write[0:0]
     3/23: $2\memory_read[0:0]
     4/23: $2\lorD[0:0]
     5/23: $2\aluop[1:0]
     6/23: $3\alu_src_a[1:0]
     7/23: $2\alu_src_b[1:0]
     8/23: $2\pc_source[0:0]
     9/23: $2\pc_write[0:0]
    10/23: $2\pc_write_cond[0:0]
    11/23: $2\alu_src_a[1:0]
    12/23: $1\pc_write[0:0]
    13/23: $1\alu_src_b[1:0]
    14/23: $1\ir_write[0:0]
    15/23: $1\memory_read[0:0]
    16/23: $1\reg_write[0:0]
    17/23: $1\alu_src_a[1:0]
    18/23: $1\aluop[1:0]
    19/23: $1\pc_source[0:0]
    20/23: $1\memory_to_reg[0:0]
    21/23: $1\memory_write[0:0]
    22/23: $1\lorD[0:0]
    23/23: $1\pc_write_cond[0:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:52$48'.
     1/3: $3\nextstate[2:0]
     2/3: $2\nextstate[2:0]
     3/3: $1\nextstate[2:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:44$47'.
     1/1: $0\state[2:0]
Creating decoders for process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:8$45'.
     1/4: $4\aluop_out[3:0]
     2/4: $3\aluop_out[3:0]
     3/4: $2\aluop_out[3:0]
     4/4: $1\aluop_out[3:0]
Creating decoders for process `\ALU.$proc$Risco-5/src/core/alu.v:11$30'.
     1/1: $1\ALU_out_S[31:0]

21.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\n_fsm_state' from process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$593'.
No latch inferred for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\n_fsm_state' from process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$536'.
No latch inferred for signal `\Registers.\readData1' from process `\Registers.$proc$Risco-5/src/core/registers.v:81$68'.
No latch inferred for signal `\Registers.\readData2' from process `\Registers.$proc$Risco-5/src/core/registers.v:81$68'.
No latch inferred for signal `\MUX.\S' from process `\MUX.$proc$Risco-5/src/core/mux.v:10$63'.
No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$60'.
No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:52$48'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:52$48`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:52$48`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:52$48`.
Latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:8$45': $auto$proc_dlatch.cc:427:proc_dlatch$2108
No latch inferred for signal `\ALU.\ALU_out_S' from process `\ALU.$proc$Risco-5/src/core/alu.v:11$30'.

21.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$482'.
  created $dff cell `$procdff$2131' with positive edge clock.
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$457'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$418_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$457'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$419_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$457'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$420_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$457'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$421_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$457'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$422_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$457'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$423_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$457'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$424_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$457'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$425_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$457'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$426_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$457'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$427_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$457'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$428_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$457'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$429_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$457'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$430_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$457'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$431_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$457'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$432_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$457'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$433_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$434'.
  created $dff cell `$procdff$2132' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$433_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$434'.
  created $dff cell `$procdff$2133' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$433_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$434'.
  created $dff cell `$procdff$2134' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$400'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$358_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$400'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$359_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$400'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$360_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$400'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$361_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$400'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$362_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$400'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$363_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$400'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$364_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$400'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$365_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$400'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$366_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$400'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$367_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$400'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$368_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$400'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$369_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$400'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$370_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$400'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$371_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$400'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$372_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$400'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$373_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$400'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$374_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$376'.
  created $dff cell `$procdff$2135' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$374_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$376'.
  created $dff cell `$procdff$2136' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$374_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$376'.
  created $dff cell `$procdff$2137' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$375'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\rxd_reg' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$622'.
  created $dff cell `$procdff$2138' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\rxd_reg_0' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$622'.
  created $dff cell `$procdff$2139' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\fsm_state' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$620'.
  created $dff cell `$procdff$2140' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\cycle_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$612'.
  created $dff cell `$procdff$2141' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\bit_sample' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$609'.
  created $dff cell `$procdff$2142' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\bit_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$603'.
  created $dff cell `$procdff$2143' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\i' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$598'.
  created $dff cell `$procdff$2144' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\recieved_data' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$598'.
  created $dff cell `$procdff$2145' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\uart_rx_data' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$584'.
  created $dff cell `$procdff$2146' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\txd_reg' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$571'.
  created $dff cell `$procdff$2147' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\fsm_state' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$569'.
  created $dff cell `$procdff$2148' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\cycle_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$561'.
  created $dff cell `$procdff$2149' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\bit_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$547'.
  created $dff cell `$procdff$2150' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\i' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$541'.
  created $dff cell `$procdff$2151' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\data_to_send' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$541'.
  created $dff cell `$procdff$2152' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$526'.
  created $dff cell `$procdff$2153' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$526'.
  created $dff cell `$procdff$2154' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$526'.
  created $dff cell `$procdff$2155' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$526'.
  created $dff cell `$procdff$2156' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$526'.
  created $dff cell `$procdff$2157' with positive edge clock.
Creating register for signal `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_ADDR' using process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$629'.
  created $dff cell `$procdff$2158' with positive edge clock.
Creating register for signal `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_DATA' using process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$629'.
  created $dff cell `$procdff$2159' with positive edge clock.
Creating register for signal `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN' using process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$629'.
  created $dff cell `$procdff$2160' with positive edge clock.
Creating register for signal `\LEDs.\data' using process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$143'.
  created $dff cell `$procdff$2161' with positive edge clock.
Creating register for signal `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.\clk_o_pulse' using process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:46$506'.
  created $dff cell `$procdff$2162' with positive edge clock.
Creating register for signal `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.\clk_o_auto' using process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$496'.
  created $dff cell `$procdff$2163' with positive edge clock.
Creating register for signal `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.\clk_counter' using process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$496'.
  created $dff cell `$procdff$2164' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$485'.
  created $dff cell `$procdff$2165' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$485'.
  created $dff cell `$procdff$2166' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$485'.
  created $dff cell `$procdff$2167' with positive edge clock.
Creating register for signal `\Registers.\register0' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2168' with positive edge clock.
Creating register for signal `\Registers.\register1' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2169' with positive edge clock.
Creating register for signal `\Registers.\register2' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2170' with positive edge clock.
Creating register for signal `\Registers.\register3' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2171' with positive edge clock.
Creating register for signal `\Registers.\register4' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2172' with positive edge clock.
Creating register for signal `\Registers.\register5' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2173' with positive edge clock.
Creating register for signal `\Registers.\register6' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2174' with positive edge clock.
Creating register for signal `\Registers.\register7' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2175' with positive edge clock.
Creating register for signal `\Registers.\register8' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2176' with positive edge clock.
Creating register for signal `\Registers.\register9' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2177' with positive edge clock.
Creating register for signal `\Registers.\register10' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2178' with positive edge clock.
Creating register for signal `\Registers.\register11' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2179' with positive edge clock.
Creating register for signal `\Registers.\register12' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2180' with positive edge clock.
Creating register for signal `\Registers.\register13' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2181' with positive edge clock.
Creating register for signal `\Registers.\register14' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2182' with positive edge clock.
Creating register for signal `\Registers.\register15' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2183' with positive edge clock.
Creating register for signal `\Registers.\register16' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2184' with positive edge clock.
Creating register for signal `\Registers.\register17' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2185' with positive edge clock.
Creating register for signal `\Registers.\register18' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2186' with positive edge clock.
Creating register for signal `\Registers.\register19' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2187' with positive edge clock.
Creating register for signal `\Registers.\register20' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2188' with positive edge clock.
Creating register for signal `\Registers.\register21' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2189' with positive edge clock.
Creating register for signal `\Registers.\register22' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2190' with positive edge clock.
Creating register for signal `\Registers.\register23' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2191' with positive edge clock.
Creating register for signal `\Registers.\register24' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2192' with positive edge clock.
Creating register for signal `\Registers.\register25' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2193' with positive edge clock.
Creating register for signal `\Registers.\register26' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2194' with positive edge clock.
Creating register for signal `\Registers.\register27' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2195' with positive edge clock.
Creating register for signal `\Registers.\register28' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2196' with positive edge clock.
Creating register for signal `\Registers.\register29' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2197' with positive edge clock.
Creating register for signal `\Registers.\register30' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2198' with positive edge clock.
Creating register for signal `\Registers.\register31' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2199' with positive edge clock.
Creating register for signal `\PC.\PC_Register' using process `\PC.$proc$Risco-5/src/core/pc.v:19$64'.
  created $dff cell `$procdff$2200' with positive edge clock.
Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:44$47'.
  created $dff cell `$procdff$2201' with positive edge clock.

21.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$483'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$482'.
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$482'.
Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$457'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$434'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$400'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$376'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$375'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$624'.
Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$622'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$622'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$620'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$620'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$612'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$612'.
Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$609'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$609'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$603'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$603'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$598'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$598'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$593'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$593'.
Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$584'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$584'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$577'.
Found and cleaned up 5 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$571'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$571'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$569'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$569'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$561'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$561'.
Found and cleaned up 5 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$547'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$547'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$541'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$541'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$536'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$536'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$529'.
Found and cleaned up 2 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$526'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$526'.
Found and cleaned up 1 empty switch in `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$629'.
Removing empty process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$629'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:0$146'.
Found and cleaned up 2 empty switches in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$143'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:23$143'.
Removing empty process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:0$508'.
Removing empty process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:46$506'.
Found and cleaned up 4 empty switches in `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$496'.
Removing empty process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$496'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:0$491'.
Found and cleaned up 5 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$485'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$485'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:0$72'.
Found and cleaned up 3 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:155$69'.
Found and cleaned up 2 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:81$68'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:81$68'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:0$67'.
Found and cleaned up 2 empty switches in `\PC.$proc$Risco-5/src/core/pc.v:19$64'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:19$64'.
Found and cleaned up 1 empty switch in `\MUX.$proc$Risco-5/src/core/mux.v:10$63'.
Removing empty process `MUX.$proc$Risco-5/src/core/mux.v:10$63'.
Found and cleaned up 1 empty switch in `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$60'.
Removing empty process `Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$60'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$53'.
Found and cleaned up 4 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Found and cleaned up 3 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:52$48'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:52$48'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:44$47'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:44$47'.
Found and cleaned up 4 empty switches in `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:8$45'.
Removing empty process `ALU_Control.$proc$Risco-5/src/core/alu_control.v:8$45'.
Found and cleaned up 1 empty switch in `\ALU.$proc$Risco-5/src/core/alu.v:11$30'.
Removing empty process `ALU.$proc$Risco-5/src/core/alu.v:11$30'.
Cleaned up 75 empty switches.

21.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
<suppressed ~21 debug messages>
Optimizing module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
<suppressed ~19 debug messages>
Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
<suppressed ~2 debug messages>
Optimizing module $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.
<suppressed ~2 debug messages>
Optimizing module $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.
Optimizing module LEDs.
<suppressed ~3 debug messages>
Optimizing module $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.
<suppressed ~5 debug messages>
Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~7 debug messages>
Optimizing module BUS.
Optimizing module Registers.
<suppressed ~4 debug messages>
Optimizing module PC.
<suppressed ~2 debug messages>
Optimizing module MUX.
<suppressed ~1 debug messages>
Optimizing module Immediate_Generator.
Optimizing module $paramod$f364a504a7e15f6f8a7a122a0a3044b25520ae7b\Risco_5_SOC.
Optimizing module Control_Unit.
<suppressed ~5 debug messages>
Optimizing module ALU_Control.
<suppressed ~13 debug messages>
Optimizing module ALU.
<suppressed ~1 debug messages>
Optimizing module top.

21.5. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Deleting now unused module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Deleting now unused module $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.
Deleting now unused module $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.
Deleting now unused module LEDs.
Deleting now unused module $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.
Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Deleting now unused module BUS.
Deleting now unused module Registers.
Deleting now unused module PC.
Deleting now unused module MUX.
Deleting now unused module Immediate_Generator.
Deleting now unused module $paramod$f364a504a7e15f6f8a7a122a0a3044b25520ae7b\Risco_5_SOC.
Deleting now unused module Control_Unit.
Deleting now unused module ALU_Control.
Deleting now unused module ALU.
<suppressed ~21 debug messages>

21.6. Executing TRIBUF pass.

21.7. Executing DEMINOUT pass (demote inout ports to input or output).

21.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~52 debug messages>

21.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 122 unused cells and 623 unused wires.
<suppressed ~158 debug messages>

21.10. Executing CHECK pass (checking for obvious problems).
Checking module top...
Warning: Wire top.\SOC.Core.PCSourceMUX.C [31] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [30] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [29] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [28] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [27] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [26] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [25] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [24] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [23] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [22] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [21] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [20] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [19] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [18] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [17] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [16] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [15] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [14] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [13] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [12] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [11] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [10] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [9] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [8] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [7] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [6] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [5] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [4] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [3] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [2] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [1] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [0] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [31] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [30] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [29] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [28] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [27] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [26] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [25] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [24] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [23] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [22] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [21] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [20] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [19] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [18] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [17] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [16] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [15] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [14] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [13] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [12] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [11] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [10] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [9] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [8] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [7] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [6] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [5] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [4] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [3] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [2] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [1] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [0] is used but has no driver.
Found and reported 256 problems.

21.11. Executing OPT pass (performing simple optimizations).

21.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~9 debug messages>

21.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~438 debug messages>
Removed a total of 146 cells.

21.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1867.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1874.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1882.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1890.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1900.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1912.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1926.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1936.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1947.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1955.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1964.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2032.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2040.
    dead port 1/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1840.
    dead port 2/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1840.
    dead port 1/5 on $pmux $flatten\SOC.\Core.\MemoryDataMUX.$procmux$1840.
    dead port 2/5 on $pmux $flatten\SOC.\Core.\MemoryDataMUX.$procmux$1840.
    dead port 1/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1840.
    dead port 2/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1840.
Removed 19 multiplexer ports.
<suppressed ~88 debug messages>

21.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1887: $auto$opt_reduce.cc:134:opt_pmux$2204
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1896: { $auto$opt_reduce.cc:134:opt_pmux$2206 $flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:57$49_Y }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1906: { $flatten\SOC.\Core.\Control_Unit.$procmux$1863_CMP $auto$opt_reduce.cc:134:opt_pmux$2208 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1919: { $auto$opt_reduce.cc:134:opt_pmux$2212 $auto$opt_reduce.cc:134:opt_pmux$2210 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1932: $auto$opt_reduce.cc:134:opt_pmux$2214
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1944: $auto$opt_reduce.cc:134:opt_pmux$2216
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1861: $auto$opt_reduce.cc:134:opt_pmux$2218
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1846: { $flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:57$49_Y $flatten\SOC.\Core.\Control_Unit.$procmux$1862_CMP $auto$opt_reduce.cc:134:opt_pmux$2222 $flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:61$50_Y $auto$opt_reduce.cc:134:opt_pmux$2220 $flatten\SOC.\Core.\Control_Unit.$procmux$1873_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2068: { $flatten\SOC.\Core.\ALU_Control.$procmux$2075_CMP $auto$opt_reduce.cc:134:opt_pmux$2224 $flatten\SOC.\Core.\ALU_Control.$procmux$2072_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2071_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2070_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2069_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1732: $auto$opt_reduce.cc:134:opt_pmux$2226
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2082: { $auto$opt_reduce.cc:134:opt_pmux$2230 $auto$opt_reduce.cc:134:opt_pmux$2228 $flatten\SOC.\Core.\ALU_Control.$procmux$2075_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2091: { $flatten\SOC.\Core.\ALU_Control.$procmux$2093_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2092_CMP }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$947:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_EN[31:0]$632 [0] }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$2207: { $flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:57$49_Y $flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:61$50_Y $flatten\SOC.\Core.\Control_Unit.$procmux$1865_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1866_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1873_CMP }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$2209: { $flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:61$50_Y $flatten\SOC.\Core.\Control_Unit.$procmux$1863_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1864_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1865_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1873_CMP }
  Optimizing cells in module \top.
Performed a total of 17 changes.

21.11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

21.11.6. Executing OPT_DFF pass (perform DFF optimizations).

21.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 177 unused wires.
<suppressed ~8 debug messages>

21.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.11.9. Rerunning OPT passes. (Maybe there is more to do..)

21.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~88 debug messages>

21.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.11.13. Executing OPT_DFF pass (perform DFF optimizations).

21.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.11.16. Finished OPT passes. (There is nothing left to do.)

21.12. Executing FSM pass (extract and optimize FSM).

21.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking top.ResetBootSystem.state as FSM state register:
    Register has an initialization value.
    Circuit seems to be self-resetting.
Not marking top.SOC.Core.Control_Unit.state as FSM state register:
    Register has an initialization value.
Not marking top.SOC.Core.RegisterBank.register0 as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Found FSM state register top.SOC.Uart.i_uart_tx.fsm_state.

21.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\SOC.Uart.i_uart_tx.fsm_state' from module `\top'.
  found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_tx.$procdff$2148
  root of input selection tree: $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$555_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$545_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$563_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$543_Y
  found state code: 3'000
  found ctrl input: \SOC.Uart.i_uart_tx.stop_done
  found state code: 3'011
  found ctrl input: \SOC.Uart.i_uart_tx.payload_done
  found state code: 3'010
  found ctrl input: \SOC.Uart.i_uart_tx.next_bit
  found state code: 3'001
  found ctrl input: \SOC.Uart.i_uart_tx.uart_tx_en
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$563_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$555_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$550_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$549_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$545_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$543_Y
  ctrl inputs: { \SOC.Uart.i_uart_tx.uart_tx_en \SOC.Uart.i_uart_tx.next_bit \SOC.Uart.i_uart_tx.payload_done \SOC.Uart.i_uart_tx.stop_done \ResetBootSystem.reset_o }
  ctrl outputs: { $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$543_Y $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$545_Y $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$549_Y $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$550_Y $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$555_Y $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$563_Y $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] }
  transition:      3'000 5'0---0 ->      3'000 9'101100000
  transition:      3'000 5'1---0 ->      3'001 9'101100001
  transition:      3'000 5'----1 ->      3'000 9'101100000
  transition:      3'010 5'--0-0 ->      3'010 9'010100010
  transition:      3'010 5'--1-0 ->      3'011 9'010100011
  transition:      3'010 5'----1 ->      3'000 9'010100000
  transition:      3'001 5'-0--0 ->      3'001 9'001101001
  transition:      3'001 5'-1--0 ->      3'010 9'001101010
  transition:      3'001 5'----1 ->      3'000 9'001101000
  transition:      3'011 5'---00 ->      3'011 9'001010011
  transition:      3'011 5'---10 ->      3'000 9'001010000
  transition:      3'011 5'----1 ->      3'000 9'001010000

21.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2231' from module `\top'.

21.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 8 unused cells and 8 unused wires.
<suppressed ~9 debug messages>

21.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2231' from module `\top'.
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] [2].

21.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2231' from module `\top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---

21.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2231' from module `top':
-------------------------------------

  Information on FSM $fsm$\SOC.Uart.i_uart_tx.fsm_state$2231 (\SOC.Uart.i_uart_tx.fsm_state):

  Number of input signals:    5
  Number of output signals:   6
  Number of state bits:       4

  Input signals:
    0: \ResetBootSystem.reset_o
    1: \SOC.Uart.i_uart_tx.stop_done
    2: \SOC.Uart.i_uart_tx.payload_done
    3: \SOC.Uart.i_uart_tx.next_bit
    4: \SOC.Uart.i_uart_tx.uart_tx_en

  Output signals:
    0: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$563_Y
    1: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$555_Y
    2: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$550_Y
    3: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$549_Y
    4: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$545_Y
    5: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$543_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 5'0---0   ->     0 6'101100
      1:     0 5'----1   ->     0 6'101100
      2:     0 5'1---0   ->     2 6'101100
      3:     1 5'----1   ->     0 6'010100
      4:     1 5'--0-0   ->     1 6'010100
      5:     1 5'--1-0   ->     3 6'010100
      6:     2 5'----1   ->     0 6'001101
      7:     2 5'-1--0   ->     1 6'001101
      8:     2 5'-0--0   ->     2 6'001101
      9:     3 5'---10   ->     0 6'001010
     10:     3 5'----1   ->     0 6'001010
     11:     3 5'---00   ->     3 6'001010

-------------------------------------

21.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2231' from module `\top'.

21.13. Executing OPT pass (performing simple optimizations).

21.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>

21.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~87 debug messages>

21.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2152 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$909_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$903_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$894_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$885_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$876_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$867_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$849_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$858_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2283 ($sdff) from module top (D = \SOC.Bus.slave_2_write_data [7], Q = \SOC.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$2283 ($sdff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$903_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$894_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$885_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$876_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$867_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$849_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$858_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2150 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$825_Y, Q = \SOC.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$2288 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$825_Y, Q = \SOC.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2149 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$814_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter, rval = 13'0000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2294 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$568_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2147 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$803_Y, Q = \SOC.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$2298 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$803_Y, Q = \SOC.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\SOC.\Leds.$procdff$2161 ($dff) from module top (D = $flatten\SOC.\Leds.$procmux$955_Y, Q = \SOC.Leds.data, rval = 33'000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2304 ($sdff) from module top (D = { 1'0 \SOC.Leds.write_data }, Q = \SOC.Leds.data).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2199 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register31).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2198 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register30).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2197 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register29).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2196 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register28).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2195 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register27).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2194 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register26).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2193 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register25).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2192 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register24).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2191 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register23).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2190 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register22).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2189 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register21).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2188 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register20).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2187 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register19).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2186 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register18).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2185 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register17).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2184 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register16).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2183 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register15).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2182 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register14).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2181 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register13).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2180 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register12).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2179 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register11).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2178 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register10).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2177 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register9).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2176 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register8).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2175 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register7).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2174 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register6).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2173 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register5).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2172 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register4).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2171 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register3).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2170 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register2).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2169 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register1).
Adding SRST signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2168 ($dff) from module top (D = $flatten\SOC.\Core.\RegisterBank.$procmux$1764_Y, Q = \SOC.Core.RegisterBank.register0, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2461 ($sdff) from module top (D = 0, Q = \SOC.Core.RegisterBank.register0).
Adding SRST signal on $flatten\SOC.\Core.\Pc.$procdff$2200 ($dff) from module top (D = $flatten\SOC.\Core.\Pc.$procmux$1835_Y, Q = \SOC.Core.Pc.PC_Register, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2467 ($sdff) from module top (D = \SOC.Core.Pc.Input, Q = \SOC.Core.Pc.PC_Register).
Adding SRST signal on $flatten\SOC.\Core.\Control_Unit.$procdff$2201 ($dff) from module top (D = \SOC.Core.Control_Unit.nextstate, Q = \SOC.Core.Control_Unit.state, rval = 3'000).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2157 ($dff) from module top (D = \SOC.Bus.write_data, Q = \SOC.Core.register_data_2, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2156 ($dff) from module top (D = \SOC.Core.register_data_1_out, Q = \SOC.Core.register_data_1, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2155 ($dff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.alu_out_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2154 ($dff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.memory_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2153 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$941_Y, Q = \SOC.Core.instruction_register, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2474 ($sdff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.instruction_register).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2167 ($dff) from module top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2166 ($dff) from module top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2165 ($dff) from module top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Adding SRST signal on $flatten\ClkDivider.$procdff$2164 ($dff) from module top (D = $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:32$499_Y, Q = \ClkDivider.clk_counter, rval = 0).
Adding SRST signal on $flatten\ClkDivider.$procdff$2163 ($dff) from module top (D = $flatten\ClkDivider.$procmux$975_Y, Q = \ClkDivider.clk_o_auto, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2502 ($sdff) from module top (D = $flatten\ClkDivider.$procmux$975_Y, Q = \ClkDivider.clk_o_auto).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$2462 ($sdffe) from module top.
Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$2305 ($sdffe) from module top.

21.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 130 unused cells and 131 unused wires.
<suppressed ~131 debug messages>

21.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~6 debug messages>

21.13.9. Rerunning OPT passes. (Maybe there is more to do..)

21.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~48 debug messages>

21.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~93 debug messages>
Removed a total of 31 cells.

21.13.13. Executing OPT_DFF pass (perform DFF optimizations).

21.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 31 unused wires.
<suppressed ~1 debug messages>

21.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.13.16. Rerunning OPT passes. (Maybe there is more to do..)

21.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~48 debug messages>

21.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.13.20. Executing OPT_DFF pass (perform DFF optimizations).

21.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.13.23. Finished OPT passes. (There is nothing left to do.)

21.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 22 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2202 (SOC.Memory.memory).
Removed top 22 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$meminit$\memory$Risco-5/src/peripheral/memory.v:0$637 (SOC.Memory.memory).
Removed top 22 address bits (of 32) from memory read port top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:17$627 (SOC.Memory.memory).
Removed top 7 bits (of 32) from port B of cell top.$flatten\ClkDivider.$ge$Risco-5/debug/clk_divider.v:40$505 ($ge).
Removed top 8 bits (of 32) from port B of cell top.$flatten\ClkDivider.$eq$Risco-5/debug/clk_divider.v:33$501 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:32$499 ($add).
Removed top 1 bits (of 2) from port B of cell top.$flatten\ResetBootSystem.$procmux$1009_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\ResetBootSystem.$eq$Risco-5/fpga/ecp5/reset.v:38$489 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$488 ($add).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$488 ($add).
Removed top 27 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$lt$Risco-5/fpga/ecp5/reset.v:36$487 ($lt).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2482 ($ne).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:135$553 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$540 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$539 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$538 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$537 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:94$533 ($eq).
Removed top 1 bits (of 13) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:92$531 ($eq).
Removed top 1 bits (of 33) from mux cell top.$flatten\SOC.\Leds.$ternary$Risco-5/src/peripheral/leds.v:21$142 ($mux).
Removed top 2 bits (of 8) from port Y of cell top.$flatten\SOC.\Leds.$not$Risco-5/src/peripheral/leds.v:31$145 ($not).
Removed top 2 bits (of 8) from port A of cell top.$flatten\SOC.\Leds.$not$Risco-5/src/peripheral/leds.v:31$145 ($not).
Removed top 20 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:44$74 ($le).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:45$77 ($ge).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:46$78 ($le).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:54$93 ($ge).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:55$94 ($le).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:61$108 ($mux).
Removed top 22 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$953 ($mux).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$eq$Risco-5/src/core/alu_control.v:34$46 ($eq).
Removed top 29 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$61 ($sub).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1843_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1843_CMP0 ($eq).
Removed top 4 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1833_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1832_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1831_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1830_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1829_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1828_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1827_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1826_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1825_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1824_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1823_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1822_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1821_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1820_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1819_CMP0 ($eq).
Removed top 4 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1800_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1799_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1798_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1797_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1796_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1795_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1794_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1793_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1792_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1791_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1790_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1789_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1788_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1787_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1786_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2489 ($ne).
Removed top 4 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1725_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1687_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1650_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1614_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1579_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1545_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1512_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1480_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1449_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1419_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1390_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1362_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1335_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1309_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1284_CMP0 ($eq).
Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2038 ($mux).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1965_CMP0 ($eq).
Removed top 1 bits (of 2) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1962 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1901_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1873_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1868_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1866_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1865_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1864_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1863_CMP0 ($eq).
Removed top 5 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:61$50 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2093_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2075_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2074_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2073_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2061 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2106_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2105_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2104_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2103_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$44 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:22$36 ($mux).
Removed top 29 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$62 ($sub).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:43$73 ($ge).
Removed top 20 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:64$112 ($mux).
Removed top 26 bits (of 32) from wire top.$flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$488_Y.
Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\ALU_Control.$4\aluop_out[3:0].
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:32$42_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:22$36_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$44_Y.
Removed top 1 bits (of 2) from wire top.$flatten\SOC.\Core.\Control_Unit.$2\alu_src_a[1:0].
Removed top 1 bits (of 3) from wire top.$flatten\SOC.\Core.\Control_Unit.$2\nextstate[2:0].
Removed top 22 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$625_ADDR[31:0]$630.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$537_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$538_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$539_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$540_Y.
Removed top 2 bits (of 8) from wire top.leds.

21.15. Executing PEEPOPT pass (run peephole optimizers).

21.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 14 unused wires.
<suppressed ~1 debug messages>

21.17. Executing SHARE pass (SAT-based resource sharing).
Found 3 cells in module top that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:17$627 ($memrd):
    Found 1 activation_patterns using ctrl signal { $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:43$75_Y \SOC.Bus.slave_0_read }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shr$Risco-5/src/core/alu.v:28$40 ($shr):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$2100_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shl$Risco-5/src/core/alu.v:26$39 ($shl):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$2101_CMP.
    No candidates found.

21.18. Executing TECHMAP pass (map to technology primitives).

21.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

21.18.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~270 debug messages>

21.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.21. Executing TECHMAP pass (map to technology primitives).

21.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

21.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.

21.21.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>

21.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
  creating $macc model for $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:32$499 ($add).
  creating $macc model for $flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$488 ($add).
  creating $macc model for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:18$33 ($add).
  creating $macc model for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34 ($sub).
  creating $macc model for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$61 ($sub).
  creating $macc model for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$62 ($sub).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$557 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$568 ($add).
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$568.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$557.
  creating $alu model for $macc $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$62.
  creating $alu model for $macc $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$61.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:18$33.
  creating $alu model for $macc $flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$488.
  creating $alu model for $macc $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:32$499.
  creating $alu model for $flatten\ClkDivider.$ge$Risco-5/debug/clk_divider.v:40$505 ($ge): new $alu
  creating $alu model for $flatten\ResetBootSystem.$lt$Risco-5/fpga/ecp5/reset.v:36$487 ($lt): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:43$73 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:45$77 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:54$93 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:44$74 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:46$78 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:55$94 ($le): new $alu
  creating $alu model for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:34$43 ($ge): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34.
  creating $alu model for $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:22$35 ($lt): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34.
  creating $alu model for $flatten\ResetBootSystem.$eq$Risco-5/fpga/ecp5/reset.v:38$489 ($eq): merged with $flatten\ResetBootSystem.$lt$Risco-5/fpga/ecp5/reset.v:36$487.
  creating $alu model for $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:32$42 ($eq): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34.
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:55$94: $auto$alumacc.cc:485:replace_alu$2529
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:46$78: $auto$alumacc.cc:485:replace_alu$2542
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:44$74: $auto$alumacc.cc:485:replace_alu$2555
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:54$93: $auto$alumacc.cc:485:replace_alu$2568
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:45$77: $auto$alumacc.cc:485:replace_alu$2577
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:43$73: $auto$alumacc.cc:485:replace_alu$2586
  creating $alu cell for $flatten\ResetBootSystem.$lt$Risco-5/fpga/ecp5/reset.v:36$487, $flatten\ResetBootSystem.$eq$Risco-5/fpga/ecp5/reset.v:38$489: $auto$alumacc.cc:485:replace_alu$2595
  creating $alu cell for $flatten\ClkDivider.$ge$Risco-5/debug/clk_divider.v:40$505: $auto$alumacc.cc:485:replace_alu$2606
  creating $alu cell for $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:32$499: $auto$alumacc.cc:485:replace_alu$2615
  creating $alu cell for $flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$488: $auto$alumacc.cc:485:replace_alu$2618
  creating $alu cell for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:18$33: $auto$alumacc.cc:485:replace_alu$2621
  creating $alu cell for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34, $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:34$43, $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:22$35, $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:32$42: $auto$alumacc.cc:485:replace_alu$2624
  creating $alu cell for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$61: $auto$alumacc.cc:485:replace_alu$2637
  creating $alu cell for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$62: $auto$alumacc.cc:485:replace_alu$2640
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$557: $auto$alumacc.cc:485:replace_alu$2643
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$568: $auto$alumacc.cc:485:replace_alu$2646
  created 16 $alu and 0 $macc cells.

21.23. Executing OPT pass (performing simple optimizations).

21.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3 debug messages>

21.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~48 debug messages>

21.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$2501: { $auto$rtlil.cc:2461:Not$2610 $auto$rtlil.cc:2464:ReduceAnd$2612 \reset }
  Optimizing cells in module \top.
Performed a total of 1 changes.

21.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.23.6. Executing OPT_DFF pass (perform DFF optimizations).

21.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 13 unused wires.
<suppressed ~2 debug messages>

21.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.23.9. Rerunning OPT passes. (Maybe there is more to do..)

21.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~48 debug messages>

21.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.23.13. Executing OPT_DFF pass (perform DFF optimizations).

21.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.23.16. Finished OPT passes. (There is nothing left to do.)

21.24. Executing MEMORY pass.

21.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

21.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

21.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing top.SOC.Memory.memory write port 0.

21.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

21.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\SOC.Memory.memory'[0] in module `\top': no output FF found.
Checking read port address `\SOC.Memory.memory'[0] in module `\top': no address FF found.

21.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

21.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

21.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).

21.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory top.SOC.Memory.memory via $__TRELLIS_DPR16X4_
<suppressed ~68 debug messages>

21.27. Executing TECHMAP pass (map to technology primitives).

21.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

21.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.

21.27.3. Continuing TECHMAP pass.
Using template $paramod$fb6ed8f936d3525780a052d218072c625795bc14\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$0eb199c7b2cea9c358f23ffe94c4548bdd802747\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$b089c18cc881634130ec6d4716ef25d78c9d48c9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$731f2d82778baee6f78f5f3e0670a3ade61ac0d6\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$48358c22c7a8e5b48ddefb8e14a8bb1f81de841f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$5276274b86ff102139fbc8ae2dfc335d77b58a6a\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$c75b2ca41d3ff8a2b5ad26d6a6ec321bb6e56448\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$315d0c5245324146665fc1ab307bed98cfcb6adf\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~634 debug messages>

21.28. Executing OPT pass (performing simple optimizations).

21.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~108 debug messages>

21.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

21.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$2476 ($dffe) from module top (D = $flatten\ResetBootSystem.$procmux$989_Y, Q = \ResetBootSystem.counter, rval = 6'000000).

21.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 28 unused cells and 3648 unused wires.
<suppressed ~29 debug messages>

21.28.5. Rerunning OPT passes. (Removed registers in this run.)

21.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3 debug messages>

21.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$3920 ($sdffce) from module top (D = $auto$wreduce.cc:461:run$2507 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).

21.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 2 unused cells and 4 unused wires.
<suppressed ~3 debug messages>

21.28.10. Rerunning OPT passes. (Removed registers in this run.)

21.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.28.13. Executing OPT_DFF pass (perform DFF optimizations).

21.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.28.15. Finished fast OPT passes.

21.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

21.30. Executing OPT pass (performing simple optimizations).

21.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~41 debug messages>

21.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$1001:
      Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$1001_Y
      New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$1001_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$1001_Y [0] = 1'0
    New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$998: { $flatten\ResetBootSystem.$procmux$1010_CMP $flatten\ResetBootSystem.$procmux$1009_CMP }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2061:
      Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$2508 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$2508 [2]
      New connections: $auto$wreduce.cc:461:run$2508 [1:0] = 2'10
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2082:
      Old ports: A=4'0110, B=12'101101111110, Y=$flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0]
      New ports: A=3'010, B=9'101011110, Y={ $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [3:2] $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [0] }
      New connections: $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [1] = 1'1
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2030:
      Old ports: A=3'000, B=3'100, Y=$flatten\SOC.\Core.\Control_Unit.$3\nextstate[2:0]
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\Control_Unit.$3\nextstate[2:0] [2]
      New connections: $flatten\SOC.\Core.\Control_Unit.$3\nextstate[2:0] [1:0] = 2'00
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2038:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$2513 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$2513 [0]
      New connections: $auto$wreduce.cc:461:run$2513 [1] = $auto$wreduce.cc:461:run$2513 [0]
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_tx.$procmux$924:
      Old ports: A=3'000, B={ 2'00 \SOC.Uart.i_uart_tx.uart_tx_en 1'0 $auto$wreduce.cc:461:run$2516 [1:0] 2'01 \SOC.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$2518 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state
      New ports: A=2'00, B={ 1'0 \SOC.Uart.i_uart_tx.uart_tx_en $auto$wreduce.cc:461:run$2516 [1:0] 1'1 \SOC.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$2518 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state [1:0]
      New connections: \SOC.Uart.i_uart_tx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$540:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$2518 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$2518 [0]
      New connections: $auto$wreduce.cc:461:run$2518 [1] = $auto$wreduce.cc:461:run$2518 [0]
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$1007:
      Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$1001_Y, Y=$flatten\ResetBootSystem.$procmux$1007_Y
      New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$1001_Y [1], Y=$flatten\ResetBootSystem.$procmux$1007_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$1007_Y [0] = 1'0
  Optimizing cells in module \top.
Performed a total of 9 changes.

21.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.30.6. Executing OPT_DFF pass (perform DFF optimizations).

21.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.30.9. Rerunning OPT passes. (Maybe there is more to do..)

21.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~41 debug messages>

21.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.30.13. Executing OPT_DFF pass (perform DFF optimizations).

21.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.30.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.30.16. Finished OPT passes. (There is nothing left to do.)

21.31. Executing TECHMAP pass (map to technology primitives).

21.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

21.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.

21.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $ne.
Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $eq.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $mux.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $reduce_bool.
Using template $paramod$7c98249b977afe59aa75782d58a190a9577d92fe\_80_ecp5_alu for cells of type $alu.
Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux.
Using template $paramod$861f5302217787cd55fd1a501bc728125f176580\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c96def1cdcef2eee3c62e5dfb7ba2dd09c9f74dd\_90_pmux for cells of type $pmux.
Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $bmux.
Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_demux for cells of type $demux.
Using template $paramod$3111a1a8e90c88cc8c163ba5aed0203d96ddc46d\_80_ecp5_alu for cells of type $alu.
Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$215440792383f7884e57d9c95f84e9552d0bf4ac\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$41ef080258eed1ff8fcfbb7776f540ab469a3d7b\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c4ef20b21801b37ea2d65c32a05dfe56e84a870d\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $sdffce.
Using template $paramod$c83925f608704c3fa34790ddcfce9302bdcd7533\_90_pmux for cells of type $pmux.
Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux.
Using template $paramod$c5c783b17ab1d780abfad8cfe6563a0a7b47a3b0\_90_pmux for cells of type $pmux.
Using template $paramod$97565c3687be688407d1272a293bd9d0ae6852dc\_90_pmux for cells of type $pmux.
Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux.
Using template $paramod$a13703aa027da371a1931fc542d213d7de559b19\_90_pmux for cells of type $pmux.
Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $dlatch.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$56955d0f36f77738c952d3505dc563df3ee11b94\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$dce7c1188cb25d2520d170426d59301c3b73f9e7\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod$a5f0941832cc861549e29ccafffe20bfdf2e5528\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux.
Using template $paramod$5d1d2614b24accd0f9d06c4779fd9ef771faf494\_90_demux for cells of type $demux.
No more expansions possible.
<suppressed ~3462 debug messages>

21.32. Executing OPT pass (performing simple optimizations).

21.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5835 debug messages>

21.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~3375 debug messages>
Removed a total of 1125 cells.

21.32.3. Executing OPT_DFF pass (perform DFF optimizations).

21.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 273 unused cells and 3374 unused wires.
<suppressed ~274 debug messages>

21.32.5. Finished fast OPT passes.

21.33. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

21.35. Executing TECHMAP pass (map to technology primitives).

21.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

21.35.2. Continuing TECHMAP pass.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
No more expansions possible.
<suppressed ~1395 debug messages>

21.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~2 debug messages>

21.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).

21.38. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in top.

21.39. Executing ATTRMVCP pass (move or copy attributes).

21.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 6580 unused wires.
<suppressed ~1 debug messages>

21.41. Executing TECHMAP pass (map to technology primitives).

21.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

21.41.2. Continuing TECHMAP pass.

21.41.3. Executing SIMPLEMAP pass (map simple cells to gate primitives).
Mapping \$_DLATCH_N_.$ternary$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$27070 ($mux).
Mapping \$_DLATCH_N_.$logic_not$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$27069 ($logic_not).
<suppressed ~4 debug messages>

21.41.4. Executing OPT pass (performing simple optimizations).

21.41.4.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.
<suppressed ~1 debug messages>

21.41.4.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

21.41.4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.41.4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

21.41.4.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

21.41.4.6. Executing OPT_DFF pass (perform DFF optimizations).

21.41.4.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..
Removed 1 unused cells and 2 unused wires.
<suppressed ~2 debug messages>

21.41.4.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

21.41.4.9. Rerunning OPT passes. (Maybe there is more to do..)

21.41.4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.41.4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

21.41.4.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

21.41.4.13. Executing OPT_DFF pass (perform DFF optimizations).

21.41.4.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..

21.41.4.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

21.41.4.16. Finished OPT passes. (There is nothing left to do.)
Using template \$_DLATCH_N_ for cells of type $_DLATCH_N_.
No more expansions possible.
<suppressed ~4 debug messages>

21.42. Executing ABC9 pass.

21.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.3. Executing PROC pass (convert processes to netlists).

21.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27165'.
Cleaned up 1 empty switch.

21.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27166 in module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.3.4. Executing PROC_INIT pass (extract init attributes).

21.42.3.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27190'.
Creating decoders for process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27166'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27164_EN[3:0]$27172
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27164_DATA[3:0]$27171
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27164_ADDR[3:0]$27170
Creating decoders for process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27165'.

21.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.\i' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27190'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27162_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27190'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27156_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27190'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27150_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27190'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27151_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27190'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27152_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27190'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27153_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27190'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27157_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27190'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27158_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27190'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27148_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27190'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27159_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27190'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27163_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27190'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27149_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27190'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27154_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27190'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27155_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27190'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27160_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27190'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27161_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27190'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27164_ADDR' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27166'.
  created $dff cell `$procdff$27216' with positive edge clock.
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27164_DATA' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27166'.
  created $dff cell `$procdff$27217' with positive edge clock.
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27164_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27166'.
  created $dff cell `$procdff$27218' with positive edge clock.
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.\muxwre' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27165'.
  created direct connection (no actual register cell created).

21.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27190'.
Found and cleaned up 1 empty switch in `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27166'.
Removing empty process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27165'.
Cleaned up 1 empty switch.

21.42.3.12. Executing OPT_EXPR pass (perform const folding).

21.42.4. Executing PROC pass (convert processes to netlists).

21.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27236'.
Cleaned up 1 empty switch.

21.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27237 in module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.4.4. Executing PROC_INIT pass (extract init attributes).

21.42.4.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27261'.
Creating decoders for process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27237'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27235_EN[3:0]$27243
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27235_DATA[3:0]$27242
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27235_ADDR[3:0]$27241
Creating decoders for process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27236'.

21.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.\i' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27261'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27233_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27261'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27228_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27261'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27223_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27261'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27219_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27261'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27220_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27261'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27224_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27261'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27225_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27261'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27229_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27261'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27221_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27261'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27230_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27261'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27234_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27261'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27226_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27261'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27222_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27261'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27231_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27261'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27227_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27261'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27232_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27261'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27235_ADDR' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27237'.
  created $dff cell `$procdff$27287' with positive edge clock.
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27235_DATA' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27237'.
  created $dff cell `$procdff$27288' with positive edge clock.
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27235_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27237'.
  created $dff cell `$procdff$27289' with positive edge clock.
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27236'.
  created direct connection (no actual register cell created).

21.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27261'.
Found and cleaned up 1 empty switch in `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27237'.
Removing empty process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27236'.
Cleaned up 1 empty switch.

21.42.4.12. Executing OPT_EXPR pass (perform const folding).

21.42.5. Executing PROC pass (convert processes to netlists).

21.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27307'.
Cleaned up 1 empty switch.

21.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27308 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.5.4. Executing PROC_INIT pass (extract init attributes).

21.42.5.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.5.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27332'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27308'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27306_EN[3:0]$27314
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27306_DATA[3:0]$27313
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27306_ADDR[3:0]$27312
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27307'.

21.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27332'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27301_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27332'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27296_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27332'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27291_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27332'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27290_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27332'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27292_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27332'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27293_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27332'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27297_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27332'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27298_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27332'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27302_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27332'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27294_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27332'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27303_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27332'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27299_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27332'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27295_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27332'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27304_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27332'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27300_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27332'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27305_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27332'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27306_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27308'.
  created $dff cell `$procdff$27358' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27306_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27308'.
  created $dff cell `$procdff$27359' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27306_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27308'.
  created $dff cell `$procdff$27360' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27307'.
  created direct connection (no actual register cell created).

21.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27332'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27308'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27307'.
Cleaned up 1 empty switch.

21.42.5.12. Executing OPT_EXPR pass (perform const folding).

21.42.6. Executing PROC pass (convert processes to netlists).

21.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27378'.
Cleaned up 1 empty switch.

21.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27379 in module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.6.4. Executing PROC_INIT pass (extract init attributes).

21.42.6.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.6.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27403'.
Creating decoders for process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27379'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27377_EN[3:0]$27383
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27377_DATA[3:0]$27385
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27377_ADDR[3:0]$27384
Creating decoders for process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27378'.

21.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.\i' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27403'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27374_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27403'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27369_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27403'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27364_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27403'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27361_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27403'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27365_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27403'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27366_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27403'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27370_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27403'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27362_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27403'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27371_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27403'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27375_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27403'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27367_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27403'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27376_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27403'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27363_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27403'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27372_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27403'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27368_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27403'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27373_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27403'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27377_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27379'.
  created $dff cell `$procdff$27429' with positive edge clock.
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27377_ADDR' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27379'.
  created $dff cell `$procdff$27430' with positive edge clock.
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27377_DATA' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27379'.
  created $dff cell `$procdff$27431' with positive edge clock.
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27378'.
  created direct connection (no actual register cell created).

21.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27403'.
Found and cleaned up 1 empty switch in `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27379'.
Removing empty process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27378'.
Cleaned up 1 empty switch.

21.42.6.12. Executing OPT_EXPR pass (perform const folding).

21.42.7. Executing PROC pass (convert processes to netlists).

21.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27449'.
Cleaned up 1 empty switch.

21.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27450 in module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.7.4. Executing PROC_INIT pass (extract init attributes).

21.42.7.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.7.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27474'.
Creating decoders for process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27450'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27448_EN[3:0]$27456
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27448_DATA[3:0]$27455
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27448_ADDR[3:0]$27454
Creating decoders for process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27449'.

21.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.\i' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27474'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27447_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27474'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27442_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27474'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27437_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27474'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27432_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27474'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27433_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27474'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27434_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27474'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27438_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27474'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27439_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27474'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27443_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27474'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27435_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27474'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27444_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27474'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27440_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27474'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27436_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27474'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27445_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27474'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27441_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27474'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27446_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27474'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27448_ADDR' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27450'.
  created $dff cell `$procdff$27500' with positive edge clock.
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27448_DATA' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27450'.
  created $dff cell `$procdff$27501' with positive edge clock.
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27448_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27450'.
  created $dff cell `$procdff$27502' with positive edge clock.
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.\muxwre' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27449'.
  created direct connection (no actual register cell created).

21.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27474'.
Found and cleaned up 1 empty switch in `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27450'.
Removing empty process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27449'.
Cleaned up 1 empty switch.

21.42.7.12. Executing OPT_EXPR pass (perform const folding).

21.42.8. Executing PROC pass (convert processes to netlists).

21.42.8.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27520'.
Cleaned up 1 empty switch.

21.42.8.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27521 in module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.8.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.8.4. Executing PROC_INIT pass (extract init attributes).

21.42.8.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.8.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.8.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27545'.
Creating decoders for process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27521'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27519_EN[3:0]$27527
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27519_DATA[3:0]$27526
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27519_ADDR[3:0]$27525
Creating decoders for process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27520'.

21.42.8.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.8.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.\i' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27545'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27516_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27545'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27510_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27545'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27505_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27545'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27503_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27545'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27506_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27545'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27507_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27545'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27511_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27545'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27512_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27545'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27513_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27545'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27517_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27545'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27518_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27545'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27508_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27545'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27509_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27545'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27514_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27545'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27515_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27545'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27504_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27545'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27519_ADDR' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27521'.
  created $dff cell `$procdff$27571' with positive edge clock.
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27519_DATA' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27521'.
  created $dff cell `$procdff$27572' with positive edge clock.
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27519_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27521'.
  created $dff cell `$procdff$27573' with positive edge clock.
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.\muxwre' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27520'.
  created direct connection (no actual register cell created).

21.42.8.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.8.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27545'.
Found and cleaned up 1 empty switch in `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27521'.
Removing empty process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27520'.
Cleaned up 1 empty switch.

21.42.8.12. Executing OPT_EXPR pass (perform const folding).

21.42.9. Executing PROC pass (convert processes to netlists).

21.42.9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27591'.
Cleaned up 1 empty switch.

21.42.9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27592 in module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.9.4. Executing PROC_INIT pass (extract init attributes).

21.42.9.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.9.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.9.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27616'.
Creating decoders for process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27592'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27590_EN[3:0]$27596
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27590_DATA[3:0]$27598
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27590_ADDR[3:0]$27597
Creating decoders for process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27591'.

21.42.9.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.9.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.\i' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27616'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27586_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27616'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27580_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27616'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27574_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27616'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27575_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27616'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27576_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27616'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27577_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27616'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27581_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27616'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27582_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27616'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27583_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27616'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27587_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27616'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27588_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27616'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27578_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27616'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27589_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27616'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27579_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27616'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27584_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27616'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27585_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27616'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27590_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27592'.
  created $dff cell `$procdff$27642' with positive edge clock.
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27590_ADDR' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27592'.
  created $dff cell `$procdff$27643' with positive edge clock.
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27590_DATA' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27592'.
  created $dff cell `$procdff$27644' with positive edge clock.
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.\muxwre' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27591'.
  created direct connection (no actual register cell created).

21.42.9.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27616'.
Found and cleaned up 1 empty switch in `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27592'.
Removing empty process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27591'.
Cleaned up 1 empty switch.

21.42.9.12. Executing OPT_EXPR pass (perform const folding).

21.42.10. Executing PROC pass (convert processes to netlists).

21.42.10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27662'.
Cleaned up 1 empty switch.

21.42.10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27663 in module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.10.4. Executing PROC_INIT pass (extract init attributes).

21.42.10.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.10.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.10.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27687'.
Creating decoders for process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27663'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27661_EN[3:0]$27669
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27661_DATA[3:0]$27667
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27661_ADDR[3:0]$27668
Creating decoders for process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27662'.

21.42.10.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.10.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.\i' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27687'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27656_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27687'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27650_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27687'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27645_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27687'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27646_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27687'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27652_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27687'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27651_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27687'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27647_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27687'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27659_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27687'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27648_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27687'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27657_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27687'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27658_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27687'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27653_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27687'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27649_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27687'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27655_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27687'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27654_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27687'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27660_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27687'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27661_DATA' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27663'.
  created $dff cell `$procdff$27713' with positive edge clock.
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27661_ADDR' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27663'.
  created $dff cell `$procdff$27714' with positive edge clock.
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27661_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27663'.
  created $dff cell `$procdff$27715' with positive edge clock.
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.\muxwre' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27662'.
  created direct connection (no actual register cell created).

21.42.10.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27687'.
Found and cleaned up 1 empty switch in `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27663'.
Removing empty process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27662'.
Cleaned up 1 empty switch.

21.42.10.12. Executing OPT_EXPR pass (perform const folding).

21.42.11. Executing PROC pass (convert processes to netlists).

21.42.11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27733'.
Cleaned up 1 empty switch.

21.42.11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27734 in module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.11.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.11.4. Executing PROC_INIT pass (extract init attributes).

21.42.11.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.11.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.11.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27758'.
Creating decoders for process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27734'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27732_EN[3:0]$27740
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27732_DATA[3:0]$27739
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27732_ADDR[3:0]$27738
Creating decoders for process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27733'.

21.42.11.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.11.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.\i' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27758'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27730_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27758'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27725_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27758'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27720_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27758'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27716_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27758'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27717_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27758'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27721_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27758'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27722_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27758'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27726_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27758'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27718_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27758'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27727_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27758'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27731_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27758'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27723_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27758'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27719_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27758'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27728_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27758'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27724_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27758'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27729_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27758'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27732_ADDR' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27734'.
  created $dff cell `$procdff$27784' with positive edge clock.
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27732_DATA' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27734'.
  created $dff cell `$procdff$27785' with positive edge clock.
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27732_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27734'.
  created $dff cell `$procdff$27786' with positive edge clock.
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27733'.
  created direct connection (no actual register cell created).

21.42.11.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.11.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27758'.
Found and cleaned up 1 empty switch in `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27734'.
Removing empty process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27733'.
Cleaned up 1 empty switch.

21.42.11.12. Executing OPT_EXPR pass (perform const folding).

21.42.12. Executing SCC pass (detecting logic loops).
Found an SCC: $techmap$auto$ff.cc:266:slice$11564.$auto$simplemap.cc:267:simplemap_mux$27072
Found an SCC: $techmap$auto$ff.cc:266:slice$11563.$auto$simplemap.cc:267:simplemap_mux$27072
Found an SCC: $techmap$auto$ff.cc:266:slice$11562.$auto$simplemap.cc:267:simplemap_mux$27072
Found an SCC: $techmap$auto$ff.cc:266:slice$11561.$auto$simplemap.cc:267:simplemap_mux$27072
Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$25040 $auto$ff.cc:266:slice$7394 $auto$ff.cc:266:slice$7392 $auto$simplemap.cc:126:simplemap_reduce$7609 $auto$simplemap.cc:126:simplemap_reduce$7594 $auto$ff.cc:266:slice$7393 $auto$simplemap.cc:196:simplemap_lognot$7613 $auto$simplemap.cc:126:simplemap_reduce$7611 $auto$simplemap.cc:126:simplemap_reduce$7608 $auto$opt_expr.cc:613:replace_const_cells$25044 $auto$simplemap.cc:267:simplemap_mux$13230 $auto$simplemap.cc:126:simplemap_reduce$13215 $auto$simplemap.cc:126:simplemap_reduce$13212 $auto$simplemap.cc:75:simplemap_bitop$13227 $auto$opt_expr.cc:613:replace_const_cells$25254 $auto$simplemap.cc:225:simplemap_logbin$7583 $auto$simplemap.cc:196:simplemap_lognot$7598 $auto$simplemap.cc:126:simplemap_reduce$7596 $auto$simplemap.cc:126:simplemap_reduce$7593 $auto$opt_expr.cc:613:replace_const_cells$25042 $auto$ff.cc:266:slice$7391 $auto$simplemap.cc:126:simplemap_reduce$7364 $auto$simplemap.cc:126:simplemap_reduce$7362 $auto$simplemap.cc:225:simplemap_logbin$7562 $auto$simplemap.cc:196:simplemap_lognot$7572 $auto$simplemap.cc:126:simplemap_reduce$7570 $auto$opt_expr.cc:613:replace_const_cells$25064 $auto$simplemap.cc:267:simplemap_mux$13229 $auto$simplemap.cc:126:simplemap_reduce$13220 $auto$simplemap.cc:126:simplemap_reduce$13217 $auto$simplemap.cc:75:simplemap_bitop$13225
Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$4030 $auto$simplemap.cc:126:simplemap_reduce$10460 $auto$simplemap.cc:126:simplemap_reduce$10458 $auto$simplemap.cc:126:simplemap_reduce$4033 $auto$simplemap.cc:126:simplemap_reduce$4031 $auto$simplemap.cc:38:simplemap_not$4731 $auto$simplemap.cc:38:simplemap_not$23662 $auto$ff.cc:266:slice$7892 $auto$ff.cc:479:convert_ce_over_srst$25776 $auto$simplemap.cc:126:simplemap_reduce$4725 $auto$ff.cc:266:slice$7891 $auto$ff.cc:479:convert_ce_over_srst$25774 $auto$ff.cc:266:slice$7890 $auto$ff.cc:479:convert_ce_over_srst$25772 $auto$ff.cc:266:slice$7889 $auto$ff.cc:479:convert_ce_over_srst$25770 $auto$simplemap.cc:38:simplemap_not$16616 $auto$ff.cc:266:slice$7888 $auto$ff.cc:479:convert_ce_over_srst$25768 $auto$simplemap.cc:126:simplemap_reduce$4723 $auto$simplemap.cc:38:simplemap_not$16615 $auto$simplemap.cc:38:simplemap_not$4014 $auto$alumacc.cc:485:replace_alu$2595.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$2595.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$2595.slice[0].ccu2c_i $auto$ff.cc:266:slice$7887 $auto$ff.cc:479:convert_ce_over_srst$25766 $auto$simplemap.cc:126:simplemap_reduce$10468 $auto$simplemap.cc:75:simplemap_bitop$4730 $auto$simplemap.cc:126:simplemap_reduce$4729 $auto$simplemap.cc:126:simplemap_reduce$4727 $auto$simplemap.cc:126:simplemap_reduce$4724 $auto$simplemap.cc:38:simplemap_not$16618
Found an SCC: $auto$simplemap.cc:38:simplemap_not$13247 $auto$ff.cc:266:slice$7406 $auto$simplemap.cc:126:simplemap_reduce$7637 $auto$ff.cc:266:slice$7405 $auto$ff.cc:266:slice$7403 $auto$simplemap.cc:126:simplemap_reduce$7641 $auto$simplemap.cc:126:simplemap_reduce$7636 $auto$simplemap.cc:38:simplemap_not$13245 $auto$ff.cc:266:slice$7404 $auto$ff.cc:266:slice$7402 $auto$simplemap.cc:38:simplemap_not$13241 $auto$ff.cc:266:slice$7400 $auto$simplemap.cc:126:simplemap_reduce$7635 $auto$ff.cc:266:slice$7401 $auto$simplemap.cc:126:simplemap_reduce$7634 $auto$ff.cc:266:slice$7399 $auto$simplemap.cc:38:simplemap_not$13239 $auto$ff.cc:266:slice$7398 $auto$ff.cc:266:slice$7396 $auto$simplemap.cc:126:simplemap_reduce$7644 $auto$ff.cc:266:slice$7407 $auto$simplemap.cc:126:simplemap_reduce$7633 $auto$simplemap.cc:38:simplemap_not$13238 $auto$ff.cc:266:slice$7397 $auto$simplemap.cc:126:simplemap_reduce$7639 $auto$simplemap.cc:126:simplemap_reduce$7632 $auto$ff.cc:266:slice$7395 $auto$simplemap.cc:167:logic_reduce$4679 $auto$simplemap.cc:196:simplemap_lognot$7648 $auto$simplemap.cc:126:simplemap_reduce$7646 $auto$simplemap.cc:126:simplemap_reduce$7643 $auto$simplemap.cc:126:simplemap_reduce$7640
Found an SCC: $auto$ff.cc:266:slice$4253 $auto$simplemap.cc:38:simplemap_not$17212 $auto$ff.cc:266:slice$4243 $auto$simplemap.cc:38:simplemap_not$17229 $auto$ff.cc:266:slice$4260 $auto$ff.cc:266:slice$4245 $auto$simplemap.cc:38:simplemap_not$17226 $auto$ff.cc:266:slice$4257 $auto$simplemap.cc:38:simplemap_not$13410 $auto$ff.cc:266:slice$4263 $auto$simplemap.cc:126:simplemap_reduce$7125 $auto$ff.cc:266:slice$4256 $auto$ff.cc:266:slice$4255 $auto$simplemap.cc:126:simplemap_reduce$7136 $auto$simplemap.cc:126:simplemap_reduce$7124 $auto$ff.cc:266:slice$4254 $auto$ff.cc:266:slice$4235 $auto$ff.cc:266:slice$4236 $auto$simplemap.cc:38:simplemap_not$17218 $auto$ff.cc:266:slice$4249 $auto$simplemap.cc:126:simplemap_reduce$7115 $auto$ff.cc:266:slice$4237 $auto$ff.cc:266:slice$4238 $auto$simplemap.cc:126:simplemap_reduce$7118 $auto$simplemap.cc:38:simplemap_not$17211 $auto$ff.cc:266:slice$4242 $auto$simplemap.cc:126:simplemap_reduce$7116 $auto$ff.cc:266:slice$4239 $auto$simplemap.cc:38:simplemap_not$17220 $auto$ff.cc:266:slice$4251 $auto$simplemap.cc:38:simplemap_not$17210 $auto$ff.cc:266:slice$4241 $auto$simplemap.cc:126:simplemap_reduce$7133 $auto$simplemap.cc:126:simplemap_reduce$7119 $auto$simplemap.cc:38:simplemap_not$17213 $auto$ff.cc:266:slice$4244 $auto$simplemap.cc:126:simplemap_reduce$7122 $auto$ff.cc:266:slice$4250 $auto$simplemap.cc:126:simplemap_reduce$7121 $auto$ff.cc:266:slice$4248 $auto$ff.cc:266:slice$4247 $auto$simplemap.cc:126:simplemap_reduce$7131 $auto$simplemap.cc:126:simplemap_reduce$7114 $auto$ff.cc:266:slice$4234 $auto$simplemap.cc:38:simplemap_not$13411 $auto$ff.cc:266:slice$4264 $auto$ff.cc:266:slice$4258 $auto$simplemap.cc:126:simplemap_reduce$7142 $auto$simplemap.cc:126:simplemap_reduce$7135 $auto$simplemap.cc:126:simplemap_reduce$7123 $auto$ff.cc:266:slice$4252 $auto$simplemap.cc:126:simplemap_reduce$7128 $auto$simplemap.cc:38:simplemap_not$17231 $auto$ff.cc:266:slice$4262 $auto$simplemap.cc:126:simplemap_reduce$7141 $auto$simplemap.cc:126:simplemap_reduce$7134 $auto$simplemap.cc:126:simplemap_reduce$7120 $auto$ff.cc:266:slice$4246 $auto$simplemap.cc:126:simplemap_reduce$7138 $auto$simplemap.cc:126:simplemap_reduce$7129 $auto$simplemap.cc:38:simplemap_not$17234 $auto$ff.cc:266:slice$4265 $auto$alumacc.cc:485:replace_alu$2606.slice[16].ccu2c_i $auto$alumacc.cc:485:replace_alu$2606.slice[14].ccu2c_i $auto$alumacc.cc:485:replace_alu$2606.slice[12].ccu2c_i $auto$alumacc.cc:485:replace_alu$2606.slice[10].ccu2c_i $auto$alumacc.cc:485:replace_alu$2606.slice[8].ccu2c_i $auto$alumacc.cc:485:replace_alu$2606.slice[6].ccu2c_i $auto$alumacc.cc:485:replace_alu$2606.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$2606.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$2606.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7145 $auto$simplemap.cc:126:simplemap_reduce$7140 $auto$simplemap.cc:126:simplemap_reduce$7132 $auto$simplemap.cc:126:simplemap_reduce$7117 $auto$simplemap.cc:38:simplemap_not$17209 $auto$ff.cc:266:slice$4240 $auto$alumacc.cc:485:replace_alu$2606.slice[18].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7126 $auto$simplemap.cc:38:simplemap_not$17228 $auto$ff.cc:266:slice$4259 $auto$simplemap.cc:38:simplemap_not$4732 $auto$alumacc.cc:485:replace_alu$2606.slice[24].ccu2c_i $auto$alumacc.cc:485:replace_alu$2606.slice[22].ccu2c_i $auto$alumacc.cc:485:replace_alu$2606.slice[20].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7137 $auto$simplemap.cc:126:simplemap_reduce$7127 $auto$simplemap.cc:38:simplemap_not$17230 $auto$ff.cc:266:slice$4261 $auto$simplemap.cc:126:simplemap_reduce$10494 $auto$simplemap.cc:126:simplemap_reduce$10492 $auto$simplemap.cc:126:simplemap_reduce$7148 $auto$simplemap.cc:126:simplemap_reduce$7146 $auto$simplemap.cc:126:simplemap_reduce$7143
Found 8 SCCs in module top.
Found 8 SCCs.

21.42.13. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.14. Executing PROC pass (convert processes to netlists).

21.42.14.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

21.42.14.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

21.42.14.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

21.42.14.4. Executing PROC_INIT pass (extract init attributes).

21.42.14.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.14.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

21.42.14.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

21.42.14.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.14.9. Executing PROC_DFF pass (convert process syncs to FFs).

21.42.14.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.14.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

21.42.14.12. Executing OPT_EXPR pass (perform const folding).

21.42.15. Executing TECHMAP pass (map to technology primitives).

21.42.15.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

21.42.15.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~178 debug messages>

21.42.16. Executing OPT pass (performing simple optimizations).

21.42.16.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
Optimizing module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
Optimizing module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
Optimizing module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
Optimizing module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Optimizing module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Optimizing module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.

21.42.16.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

21.42.16.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.42.16.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Performed a total of 0 changes.

21.42.16.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

21.42.16.6. Executing OPT_DFF pass (perform DFF optimizations).

21.42.16.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4..

21.42.16.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
Optimizing module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
Optimizing module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Optimizing module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Optimizing module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
Optimizing module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
Optimizing module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Optimizing module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.

21.42.16.9. Finished OPT passes. (There is nothing left to do.)

21.42.17. Executing TECHMAP pass (map to technology primitives).

21.42.17.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

21.42.17.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4 for cells of type $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Using template $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4 for cells of type $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Using template $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4 for cells of type $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Using template $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4 for cells of type $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
Using template $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4 for cells of type $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
Using template $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4 for cells of type $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
Using template $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4 for cells of type $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
Using template $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4 for cells of type $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~523 debug messages>

21.42.18. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

21.42.19. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

21.42.20. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.21. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

21.42.22. Executing TECHMAP pass (map to technology primitives).

21.42.22.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

21.42.22.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $xor.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~217 debug messages>

21.42.23. Executing OPT pass (performing simple optimizations).

21.42.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~18 debug messages>

21.42.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

21.42.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.42.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.42.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.42.23.6. Executing OPT_DFF pass (perform DFF optimizations).

21.42.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>

21.42.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.42.23.9. Rerunning OPT passes. (Maybe there is more to do..)

21.42.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.42.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.42.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.42.23.13. Executing OPT_DFF pass (perform DFF optimizations).

21.42.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.42.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.42.23.16. Finished OPT passes. (There is nothing left to do.)

21.42.24. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 18 cells with 120 new cells, skipped 39 cells.
  replaced 3 cell types:
       2 $_OR_
       2 $_XOR_
      14 $_MUX_
  not replaced 3 cell types:
      31 $specify2
       4 $_NOT_
       4 $_AND_

21.42.25. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 5939 cells with 33011 new cells, skipped 5662 cells.
  replaced 3 cell types:
    2854 $_OR_
      67 $_XOR_
    3018 $_MUX_
  not replaced 23 cell types:
     356 $_NOT_
    2797 $_AND_
    1291 TRELLIS_FF
       1 $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4
     504 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
       1 $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4_$abc9_byp
     504 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
     193 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
       1 $__ABC9_SCC_BREAKER
       1 $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4
       1 $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4
       1 $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4
       1 $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4
       1 $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4
       1 $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4
       1 $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4

21.42.25.1. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.25.2. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.25.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 14906 AND gates and 42574 wires from module `top' to a netlist network with 3350 inputs and 470 outputs.

21.42.25.4. Executing ABC9_EXE pass (technology mapping using ABC9).

21.42.25.5. Executing ABC9.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   3350/    470  and =   13749  lev =   47 (6.91)  mem = 0.35 MB  box = 705  bb = 512
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   3350/    470  and =   19875  lev =   61 (4.51)  mem = 0.40 MB  ch = 1357  box = 644  bb = 512
ABC: + &if -W 300 -v 
ABC: K = 7. Memory (bytes): Truth =    0. Cut =   60. Obj =  140. Set =  636. CutMin = no
ABC: Node =   19875.  Ch =   959.  Total mem =    4.68 MB. Peak cut mem =    0.24 MB.
ABC: P:  Del = 7131.00.  Ar =   21128.0.  Edge =    23328.  Cut =   302139.  T =     0.07 sec
ABC: P:  Del = 6705.00.  Ar =   21585.0.  Edge =    23667.  Cut =   279162.  T =     0.07 sec
ABC: P:  Del = 6705.00.  Ar =    8785.0.  Edge =    18800.  Cut =   644814.  T =     0.14 sec
ABC: F:  Del = 6705.00.  Ar =    6170.0.  Edge =    16471.  Cut =   493279.  T =     0.12 sec
ABC: A:  Del = 6705.00.  Ar =    5624.0.  Edge =    15605.  Cut =   484688.  T =     0.20 sec
ABC: A:  Del = 6705.00.  Ar =    5578.0.  Edge =    15541.  Cut =   484403.  T =     0.21 sec
ABC: Total time =     0.81 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: + &ps -l 
ABC: <abc-temp-dir>/input : i/o =   3350/    470  and =   12594  lev =   38 (3.75)  mem = 0.32 MB  box = 644  bb = 512
ABC: Mapping (K=7)  :  lut =   3783  edge =   15483  lev =   13 (2.02)  levB =   25  mem = 0.18 MB
ABC: LUT = 3783 : 2=197 5.2 %  3=311 8.2 %  4=2588 68.4 %  5=473 12.5 %  6=59 1.6 %  7=155 4.1 %  Ave = 4.09
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + time 
ABC: elapse: 5.05 seconds, total: 5.05 seconds

21.42.25.6. Executing AIGER frontend.
<suppressed ~7713 debug messages>
Removed 16015 unused cells and 29731 unused wires.

21.42.25.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:     3797
ABC RESULTS:   $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells:      504
ABC RESULTS:   $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells:      132
ABC RESULTS:   $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:           input signals:      567
ABC RESULTS:          output signals:       93
Removing temp directory.

21.42.26. Executing TECHMAP pass (map to technology primitives).

21.42.26.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

21.42.26.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4 for cells of type $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Using template $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4 for cells of type $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Using template $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4 for cells of type $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4 for cells of type $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
Using template $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4 for cells of type $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
Using template $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4 for cells of type $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
Using template $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4 for cells of type $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
Using template $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4 for cells of type $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
Using template $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000001000 for cells of type $__ABC9_SCC_BREAKER.
Using template $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4_$abc9_byp.
No more expansions possible.
<suppressed ~1192 debug messages>
Removed 197 unused cells and 48572 unused wires.

21.43. Executing TECHMAP pass (map to technology primitives).

21.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

21.43.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod$5e2c4e05bbdd2eaa20212f01bb8e88597c0f6680\$lut for cells of type $lut.
Using template $paramod$a743caf801766df40bcc22d49baa12a0bdc2f7fe\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod$f4b04e57ed992cc7bc778356bca4a8fabeb6b83d\$lut for cells of type $lut.
Using template $paramod$2cc00fe796d5be3d04b653095ae074c81be83988\$lut for cells of type $lut.
Using template $paramod$5400b6807adef39a9693b2fbff17f8c0ab116b66\$lut for cells of type $lut.
Using template $paramod$6c8df34f38f3bb4fc8db8d09eb9f20a15c6ee32e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod$c20bb0ec9b7ffe048b440bc5b52865dca055e17d\$lut for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod$c1e03ad83f785f1cb08178836c284676a688a458\$lut for cells of type $lut.
Using template $paramod$874ccaa8ca7783774f35da6418d6fdb7651f35c0\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$01b24bf53ceb7fc66f9dc68d15f455f04b7f04c2\$lut for cells of type $lut.
Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5\$lut for cells of type $lut.
Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut.
Using template $paramod$a7dad16c080c08c1647c7e1b9706a59a123d8bcd\$lut for cells of type $lut.
Using template $paramod$872aae2e0d2b2ddb52ca07b1c6ce9b93ff747565\$lut for cells of type $lut.
Using template $paramod$21b45df4e65d7ac76e52853add208e7fdb8cd203\$lut for cells of type $lut.
Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut.
Using template $paramod$ecbb171d4c13c21e08940220a0c2b73302dc3cb8\$lut for cells of type $lut.
Using template $paramod$771fa20fb788c6f290888a2eefb1f56c651897b0\$lut for cells of type $lut.
Using template $paramod$e75993d8dc613209dd6f44bd8f9163232079f8e2\$lut for cells of type $lut.
Using template $paramod$ff13b8f3dd09d16132fb7c960a9829af8b6c8d82\$lut for cells of type $lut.
Using template $paramod$f054a7d7ab239e8c6ce022005b59678182897bfe\$lut for cells of type $lut.
Using template $paramod$cfe658add7b49bc6805d629e0a88423d427de396\$lut for cells of type $lut.
Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut.
Using template $paramod$08e0515b71182b69329467e1e009a2fd6b1d4c54\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
Using template $paramod$81f9efc172579af62278dd7f44759e3ea955ec1d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$cd4f4295f5084044560b62b49d805756222899b9\$lut for cells of type $lut.
Using template $paramod$529d29cadcf52f401c71e7551beb2bea2321ab7f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut.
Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut.
Using template $paramod$0b79fea9916f0c00f6899a0be9846668a1d4eae3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod$40bf400bfab4b5cf32dcfe01e14f0900ac7f6b1b\$lut for cells of type $lut.
Using template $paramod$1a441877fe507d6e3773ef1f291c342ba1351ff8\$lut for cells of type $lut.
Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod$7a02e05acb86bef14143e0e435fb2c7bb50c485b\$lut for cells of type $lut.
Using template $paramod$803fb2e411cd759897bb32714c4cd91d7f11ca86\$lut for cells of type $lut.
Using template $paramod$c0e395c2d0dfbafa147a6aae7cfc1897ce26affb\$lut for cells of type $lut.
Using template $paramod$0a6eee007c60fcc5aca728e0f4db043641f0ddb2\$lut for cells of type $lut.
Using template $paramod$4b23d751b3e1d7cde9cd1766bf20ceee12e38a3d\$lut for cells of type $lut.
Using template $paramod$6e84f1dafe1369dfbff5db75862cca344ec57f70\$lut for cells of type $lut.
Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut.
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut.
Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut.
Using template $paramod$59f2a3e232df3029c8bc36978b9bbe72a71dfb5a\$lut for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut.
Using template $paramod$0884d334dbac54c8581fffa4e59f1334bc9d59fb\$lut for cells of type $lut.
Using template $paramod$945973007634a6e187a1aa1ebd8842fe6cd9c9c8\$lut for cells of type $lut.
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut.
Using template $paramod$c217e185eb8e6463ca272982ba8c5940fa90d81f\$lut for cells of type $lut.
Using template $paramod$0f891ee84fac320f890afcf9c994c53a24cd31f9\$lut for cells of type $lut.
Using template $paramod$a15fd389a2f54cb7b94707b25934d226e68d9e2e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod$47d363ae7b1a0e81207e02fe31af85b6bf36a2ac\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod$b587e1dcd8f8a9800d395e4aeecac52c55d6f585\$lut for cells of type $lut.
Using template $paramod$78b4324556f6321a85bd440441a5392f271ea218\$lut for cells of type $lut.
Using template $paramod$130af793a2ec6ecceb3e0ef509cf6b180e856b6f\$lut for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut.
Using template $paramod$c5fc75a3c76ca4b62ba5ce67ff8eaffd884835f1\$lut for cells of type $lut.
Using template $paramod$03b7bc2c50b7bfbbc271e26fd94065a6746c84dd\$lut for cells of type $lut.
Using template $paramod$01033ac839e1447c668135b77fe512f0c54319ef\$lut for cells of type $lut.
Using template $paramod$e6c3d104d67ec1a7651dfbe0515c4d4a3e798b52\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut.
Using template $paramod$7bf38764e4de60965d0d6d9f1f8fc9b4ccc1d4e3\$lut for cells of type $lut.
Using template $paramod$18cc024e7e2627570c8376ddf2f176c662d8582b\$lut for cells of type $lut.
Using template $paramod$58e2f4e0710491e089ce4161fbd0f16ce71c019e\$lut for cells of type $lut.
Using template $paramod$a3f30630b3f97207e1a9a19eb2589290a870b590\$lut for cells of type $lut.
Using template $paramod$ab62a4a3d6aa81450d4a4cd3c80b9cb759758cd5\$lut for cells of type $lut.
Using template $paramod$18f7b4f1487f3d1f547644742ee00849da7cbfb9\$lut for cells of type $lut.
Using template $paramod$9ae0f136c9ed34a2deb323e9b2a3a520eea61514\$lut for cells of type $lut.
Using template $paramod$d86a18d460ecf2f1d1c5b055a9ec9447c00d8f45\$lut for cells of type $lut.
Using template $paramod$48a1aaadc16bd738e12f1633bf57ec0fa192dc95\$lut for cells of type $lut.
Using template $paramod$58318017d9bc6559295053db90fdf7a088b1fdc7\$lut for cells of type $lut.
Using template $paramod$29f786c76230f2c73a92703265831879ac13bf6e\$lut for cells of type $lut.
Using template $paramod$d39daf56a31b2e8ce06533aad96ed54894dfed59\$lut for cells of type $lut.
Using template $paramod$4dd4a9d54065b1696fc5e1c7ca18ff772310a315\$lut for cells of type $lut.
Using template $paramod$32abbd1d449a67fb913b4733374e345d4c17175b\$lut for cells of type $lut.
Using template $paramod$a88cbe275ca0f24a28b776a3819125328c2b6eb0\$lut for cells of type $lut.
Using template $paramod$b8113752b08bd47f69a1c8c2bca1cfb157e800c9\$lut for cells of type $lut.
Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut.
Using template $paramod$4a6b81c3909ae9ba555db882640e1727b94b143f\$lut for cells of type $lut.
Using template $paramod$b912903c5697c056ed832899a33f2105db006150\$lut for cells of type $lut.
Using template $paramod$04a3f7035a1cda67b0b5c75d77a6df4ed0460276\$lut for cells of type $lut.
Using template $paramod$1f575543d734f2d93dfcc8f91b30fb001334bb95\$lut for cells of type $lut.
Using template $paramod$45ee56e8502355090642d319eac1afef5aff9cc1\$lut for cells of type $lut.
Using template $paramod$9e394303e290a474880b56f98766417009256d93\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod$712505941a295086314c22735153725461a87f4a\$lut for cells of type $lut.
Using template $paramod$8e83c7ea20bd1b26ae726084c54862f46443f3f1\$lut for cells of type $lut.
Using template $paramod$0ee0167fb5dd83bdfe7197fff23e2c7146c57037\$lut for cells of type $lut.
Using template $paramod$04b76070d08337bc357baf9f0d16e1e6b20124d5\$lut for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut.
Using template $paramod$3b374b0454c507d1efadee363d480c52c3b3f58f\$lut for cells of type $lut.
Using template $paramod$6fc23ce09f2013cb9de2228dbcdda21841008f92\$lut for cells of type $lut.
Using template $paramod$2173de3b863bca56f7f65301b84bc178e6f2c71f\$lut for cells of type $lut.
Using template $paramod$a29dc9226a883358910d3758606f48686bda2689\$lut for cells of type $lut.
Using template $paramod$66658cbed86a8310f9b7ba1190d35eff90ee749b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$193d365ba3260f56de4ca734b1cedcf9dc72302b\$lut for cells of type $lut.
Using template $paramod$a4b35d3981c54981d8edaea95699043a59690a3d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod$aab54572d5ffecd31253b36e73e9cb718d05be34\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod$d546db88fc169832512e499a9cdf9a41b89ab74e\$lut for cells of type $lut.
Using template $paramod$e85b6eba0dacefc5f73f8748159b8b9599212afc\$lut for cells of type $lut.
Using template $paramod$4e0dac06d9d9602cfb659e01e0850b77eec5b798\$lut for cells of type $lut.
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut.
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut.
Using template $paramod$09deb89cf77b6e37f6ed7fef8d797dc05c0b2eee\$lut for cells of type $lut.
Using template $paramod$b97dea647725901eed851280e5a3889ea3e50a3d\$lut for cells of type $lut.
Using template $paramod$0c8ca179830091c5e617fa87fec5eda52bbb802e\$lut for cells of type $lut.
Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut.
Using template $paramod$71715b752f6c6222735147a74a785ff930effad3\$lut for cells of type $lut.
Using template $paramod$151773c161f403488b6d9962171babf39d88db5c\$lut for cells of type $lut.
Using template $paramod$81e300b0819553138d2ee25e9a978cf155f03dec\$lut for cells of type $lut.
Using template $paramod$dbd7752cebfffda2f7237bd51529740e7d59568b\$lut for cells of type $lut.
Using template $paramod$6adfc5a40becb3986d7ba7df5e42cf997a30ea81\$lut for cells of type $lut.
Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut.
Using template $paramod$221832ea6a41a3208cd6f3411a952b5811695f4c\$lut for cells of type $lut.
Using template $paramod$dd8b0f1e65e6a9c4ac0264bc14db2c5ffdac3453\$lut for cells of type $lut.
Using template $paramod$993a2044bae9e2f987bba692162e23bf80e406a7\$lut for cells of type $lut.
Using template $paramod$0d710a2d1fb16e4de7d20bde66fd2cf26ada9670\$lut for cells of type $lut.
Using template $paramod$cd6676b9de8abc9da5f33595fe44ac6b76edc0b8\$lut for cells of type $lut.
Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f\$lut for cells of type $lut.
Using template $paramod$6707bcca932d1a71b17c093e3bae516a22e5abc9\$lut for cells of type $lut.
Using template $paramod$c50a83e1ae6c2d4b7def7353a651bb8a906a6862\$lut for cells of type $lut.
Using template $paramod$2645ed3928f2726e8ccb403cb23252de43b617d7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod$be95f3a2132281eadd1adcfe6229e43dbc3353c9\$lut for cells of type $lut.
Using template $paramod$b98c5cad3e4b1575461e7c6b454efd7b9d35666f\$lut for cells of type $lut.
Using template $paramod$302ba22a83dfb50189674147c5c2626b9e9dab7e\$lut for cells of type $lut.
Using template $paramod$be7b9b4fe304f35e2a126a3893cf799cf6d216a8\$lut for cells of type $lut.
Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut.
Using template $paramod$e0dfb361569d0778518399d18b317c11a11fbf9d\$lut for cells of type $lut.
Using template $paramod$6fc6c0e34df58e53d27d3e65aff99e90593d25df\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101111 for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut.
Using template $paramod$4f2223f3a765685285ee28543b3f03abd179274a\$lut for cells of type $lut.
Using template $paramod$06158126b14a073c7846e31ae8eda5cc3837f960\$lut for cells of type $lut.
Using template $paramod$466db5b833deb153f39d807f4edbdf783486e131\$lut for cells of type $lut.
Using template $paramod$73bfab9a6a26309994bf03e2e1e427f44b9a29b0\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
Using template $paramod$01b636f2759ab594c2741266b3c22685988e291c\$lut for cells of type $lut.
Using template $paramod$384eac9ea43c5b0355fa175b42053a7b1c651c20\$lut for cells of type $lut.
Using template $paramod$5502a85110dbca29ac631107f0b0635e7fade476\$lut for cells of type $lut.
Using template $paramod$b582bd682328e778112e724cba2a0943360c779c\$lut for cells of type $lut.
Using template $paramod$a7d9b4ab0321c8125e5b895183ee6b84cdb4a31b\$lut for cells of type $lut.
Using template $paramod$a25bc3c841d39f1992f0b22dad9b5fd5677533ba\$lut for cells of type $lut.
Using template $paramod$62e962fc19a04a2b4e4e7ccfa8219434c241cbdd\$lut for cells of type $lut.
Using template $paramod$7b809938766c3068dc017c276033f224fcfb7189\$lut for cells of type $lut.
Using template $paramod$9e2b188711e0c12c2fe86e0510cd6df11f513c14\$lut for cells of type $lut.
Using template $paramod$312c8bab003b975d614e2bfaf49ff0fa7926f2d1\$lut for cells of type $lut.
Using template $paramod$1d976bc954653b91c2dfa54d38dd9f92125922d7\$lut for cells of type $lut.
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut.
Using template $paramod$d8119e7cf18bdd1d72e1822e569d9c40a2fc5848\$lut for cells of type $lut.
Using template $paramod$3873423a8ce80a55498b9126c04269c3d00fc043\$lut for cells of type $lut.
Using template $paramod$a2632e47f874d84a6659dbeafd119d5398c37569\$lut for cells of type $lut.
Using template $paramod$3e6ce97e9937f8d3bb19d63d60c1094359e14ced\$lut for cells of type $lut.
Using template $paramod$cc2a095eb455a4b3d2a771dcc8d049b19888952d\$lut for cells of type $lut.
Using template $paramod$82dd67738cc66e7305eddbbf1959188366d07b16\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod$238ce1c123ccd5620a61157a2c5350ee6fc4d4ff\$lut for cells of type $lut.
Using template $paramod$e874f38f398c5dce94e88799a16735741e938d58\$lut for cells of type $lut.
Using template $paramod$3f943b31daf852ed1ca222e5bb6488e4bbd6a0e6\$lut for cells of type $lut.
Using template $paramod$3fa7edc48a2239f30c327cf5858fbe695689954a\$lut for cells of type $lut.
Using template $paramod$dbaf931e1292c9aa3dc58e5cad9095c6c286b35d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut.
Using template $paramod$0331e023d83b8009e60defb446ce9fa640b122c7\$lut for cells of type $lut.
Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut.
Using template $paramod$f84480a2da752af131cb20293d03da96529d3313\$lut for cells of type $lut.
Using template $paramod$6e123cb71728cd1bd528e383150027dba800d6ac\$lut for cells of type $lut.
Using template $paramod$cc7b98ded7088f64dc88a04a7c54fe16eadf70f7\$lut for cells of type $lut.
Using template $paramod$40a3b80818a30ad59b093c50c50a47cfea27f867\$lut for cells of type $lut.
Using template $paramod$7a96d62884cccd5a8d3fffeab24306862b39f37c\$lut for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut.
Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut.
Using template $paramod$ecfc68783644d180c627ba80a5331c6671533dfe\$lut for cells of type $lut.
Using template $paramod$2778d17bfdb8ca32f3b6810bb49c9e3729186251\$lut for cells of type $lut.
Using template $paramod$3f7800f768bd1346fc60e2eb6d38a03dc5816f67\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut.
Using template $paramod$2e9afba29670cc6475874639e7c1b3979c8ebde3\$lut for cells of type $lut.
Using template $paramod$9a8142107e16b1af3b331cc683a28cc45dcf8f24\$lut for cells of type $lut.
Using template $paramod$d8084e36fc71627982d1cc3fcf939ccc2c722e4f\$lut for cells of type $lut.
Using template $paramod$e374f099c1946d555f0a6a12c0ce5d3ec931f9a3\$lut for cells of type $lut.
Using template $paramod$7fc325150916e09e21db63cc9672b99a89ef9301\$lut for cells of type $lut.
Using template $paramod$6023c671e114c4eb0467aa8a0b08e183f33ec2fd\$lut for cells of type $lut.
Using template $paramod$8c4aeabdc457046c83981d2a79379889a9ac8ba0\$lut for cells of type $lut.
Using template $paramod$426a98997b8ae70a480ce4b42a41d6f463a53b7d\$lut for cells of type $lut.
Using template $paramod$2265b733ea5bda69dba60508134323da5d5b62c4\$lut for cells of type $lut.
Using template $paramod$ec1ba13261471652a1600b57f1ebaf5eccb2b34a\$lut for cells of type $lut.
Using template $paramod$8ccf61cbd280c99ab22986f0067fd91897da1e7f\$lut for cells of type $lut.
Using template $paramod$36b7d8209200ca95c844934f9e4add2d5121b073\$lut for cells of type $lut.
Using template $paramod$6753094e1f5f10a493ec3c5a1ef65793b6f2ebc9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut.
Using template $paramod$3416dacc8eaab1f89b3d6b7398df3da766d29ef2\$lut for cells of type $lut.
Using template $paramod$49d70556b9b70b12cf0a704c8e1d63e33c5121ad\$lut for cells of type $lut.
Using template $paramod$024e95241da3cebf78e228447139a39694a29c0a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod$7562579f4b6cddaf6813bdaed7637a5cce67162c\$lut for cells of type $lut.
Using template $paramod$eabde4761c91679426ef5401ae1b2c95bf56e107\$lut for cells of type $lut.
Using template $paramod$83a094b6fe9fb738dfff353a8cb39fb4b34c4f40\$lut for cells of type $lut.
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod$c5e9409d868ac22b0d04fa66386bddf5c7c8858c\$lut for cells of type $lut.
Using template $paramod$430d9aae42a88b878b2a6ceac307a334dfa959c7\$lut for cells of type $lut.
Using template $paramod$093ee58b0520130b1d178e0c5806216acfab2d05\$lut for cells of type $lut.
Using template $paramod$9cf976b4f3a576aa2cd6b51304cf5de7fc836fbd\$lut for cells of type $lut.
Using template $paramod$9ef9c88bbf5a9c7658ec40b53df933881169b654\$lut for cells of type $lut.
Using template $paramod$6f9324703e8fcc3b6df2bc2bec54ec19a446ae96\$lut for cells of type $lut.
Using template $paramod$36c3f64fb67cfb5b68be929a6a8276da64fa4183\$lut for cells of type $lut.
Using template $paramod$c7b80ba430fcbff15d6bf260d454531db01b4698\$lut for cells of type $lut.
Using template $paramod$8b156142bc74ae9e700b3ef741666f2561ac80b2\$lut for cells of type $lut.
Using template $paramod$9b8ec3b2fbfe4d374226784040ad55afdda9d466\$lut for cells of type $lut.
Using template $paramod$000fa2164e1f538c16460571efee2b6209a086cc\$lut for cells of type $lut.
Using template $paramod$20ae971f03a8aabd14bc9c90601f9bed8100c9da\$lut for cells of type $lut.
Using template $paramod$d1dc785fc5b97e7bec2be30ee7302c8cf250ad22\$lut for cells of type $lut.
Using template $paramod$0d4742cff20cb0e0e40b9af6c0257e3a276c0c2b\$lut for cells of type $lut.
Using template $paramod$6be53ab59e0a69757fc32adb071ddcb64e8c87b6\$lut for cells of type $lut.
Using template $paramod$1578333f1a5078051b84dbcbad362e8087bf5284\$lut for cells of type $lut.
Using template $paramod$3787a3928b944fdb9c6a36ef50ee258f84082c1f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut.
Using template $paramod$1ec3fb8fd1fa98216cb96b4422de32c4ba5f6c9c\$lut for cells of type $lut.
Using template $paramod$8028399266c8ff6246df04ffbddf86cc2b8996bd\$lut for cells of type $lut.
Using template $paramod$694c95659b447cef99dd4cdbd49b87dfd5f6c806\$lut for cells of type $lut.
Using template $paramod$48c19eb209dd8ad2c18334e4df384d3b3b74d5ec\$lut for cells of type $lut.
Using template $paramod$8915f24fcc45a3744fe14e4ac7411030ea0a9166\$lut for cells of type $lut.
Using template $paramod$672e798a02b8bcc43378b3bcf167b71b5747401f\$lut for cells of type $lut.
Using template $paramod$15ac410ea5b84c303864da98179081473b96983a\$lut for cells of type $lut.
Using template $paramod$baa939b0bd5b3e0c8760492528669bd58f640542\$lut for cells of type $lut.
Using template $paramod$0b83932201bac77f28d8f183b38fa7402f2cda0d\$lut for cells of type $lut.
Using template $paramod$afa1b15c9b6d3b837cb91b2d9b8def648ff2c2e6\$lut for cells of type $lut.
Using template $paramod$c593ce43158c39bf45b040e3d3a4bf18087d62dd\$lut for cells of type $lut.
Using template $paramod$84c5cfa8d7481774250caab0fcdd6d249a376a31\$lut for cells of type $lut.
Using template $paramod$f24ba3ced4b870f8e829f5ac5a8af88573350e6f\$lut for cells of type $lut.
Using template $paramod$8f7210088a40da1859d27e900c288fd298d68bed\$lut for cells of type $lut.
Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut.
Using template $paramod$e5f7e0c689455dde2051e14b4496055df667a2c7\$lut for cells of type $lut.
Using template $paramod$37c9af120c85145419565a9ccf4ceb7397fbbe92\$lut for cells of type $lut.
Using template $paramod$4f8edd664328039cee7936fba43b73a91069e069\$lut for cells of type $lut.
Using template $paramod$49fb74fe3f799192a6d68795f37ecdda1614a472\$lut for cells of type $lut.
Using template $paramod$f314abdbef3663f31659cf7a4e5e574a874f0912\$lut for cells of type $lut.
Using template $paramod$27d1fd562eca397af0bcf374fcecce96bb10480e\$lut for cells of type $lut.
Using template $paramod$b9fc46df0204429c83a59a4dd0b563b17576dc7d\$lut for cells of type $lut.
Using template $paramod$9754422de62e5f46b1224496b225c68aeb5874c2\$lut for cells of type $lut.
Using template $paramod$f58e0d90afc57a738914697b6a4a7319b30d7e7e\$lut for cells of type $lut.
Using template $paramod$19f3b9d41115661044c8790d1ca6387e6cfb42d2\$lut for cells of type $lut.
Using template $paramod$e019cb14313283ce60b57907d30cf3eefa00a93d\$lut for cells of type $lut.
Using template $paramod$7e8fe64f22f1153a85bf31be98f3c990173d62ab\$lut for cells of type $lut.
Using template $paramod$8d64e576629e8d7c655e0c65958ea61e649cd93e\$lut for cells of type $lut.
Using template $paramod$833582361e14b3ee2e66ad676022ab35d7aa7e28\$lut for cells of type $lut.
Using template $paramod$420ce902a9839f934882da8e606c44145ccac490\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod$39825c5ed3d135e502be79829033166f1762d78b\$lut for cells of type $lut.
Using template $paramod$e332cff882edd417f410bab5fe07a0f88572cce3\$lut for cells of type $lut.
Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d\$lut for cells of type $lut.
Using template $paramod$017da96930567523820b9f9013b8815c31ef27f2\$lut for cells of type $lut.
Using template $paramod$b698dd2b885039c9e1d53e243fc4e0191632dfd9\$lut for cells of type $lut.
Using template $paramod$c4b1ceb2036c3437031eb9e6e68d02312cfa8a1d\$lut for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut.
Using template $paramod$2955ab75367a3dc9d6f50d3655eebcd4f615031f\$lut for cells of type $lut.
Using template $paramod$d9922e15eb5da1acc26e937540cc16b16c2ad42c\$lut for cells of type $lut.
Using template $paramod$5002424fb13e71fe3d63c5ae16358968d083bd9b\$lut for cells of type $lut.
Using template $paramod$f45da14e1df32d0b5705e5a7350e283f5a3e9906\$lut for cells of type $lut.
Using template $paramod$a1abe959e1b68100e005cf21562972e598f617aa\$lut for cells of type $lut.
Using template $paramod$72e7c2e5c33f89d6509e2f47d1e2807865fa0aff\$lut for cells of type $lut.
Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut.
Using template $paramod$bdc65f11200e9eefee8fbb35b2c23d18ffdf014a\$lut for cells of type $lut.
Using template $paramod$5e8f0d3e60e760ce741dff73f8973807ed47ce9c\$lut for cells of type $lut.
Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut.
Using template $paramod$6d4cc4f82cbeec9f11ee20382d2e8cbca780ab4d\$lut for cells of type $lut.
Using template $paramod$9a6965d4f53d69e345bd8d48283856520a30225e\$lut for cells of type $lut.
Using template $paramod$5e3164a14b8375764d1831e48df8bc11c8d249e0\$lut for cells of type $lut.
Using template $paramod$eca6cd13b01d19273758ba2ce345a18a5dc5dac2\$lut for cells of type $lut.
Using template $paramod$068092ddede495d8462ffe530e6d91711913edbc\$lut for cells of type $lut.
Using template $paramod$d2e2f2685ff9762a50614f8be430db927eaa4201\$lut for cells of type $lut.
Using template $paramod$77cc26d4b8b23897789fa347c0b85da89fb33105\$lut for cells of type $lut.
Using template $paramod$e01a027fedb28671a20c130493a89c7afd4e87d3\$lut for cells of type $lut.
Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut.
Using template $paramod$5dd97e3a189ac418135ada81e10c839f4725015c\$lut for cells of type $lut.
Using template $paramod$6eaff21d3c29251343ef497052cf2c77fea3c8e9\$lut for cells of type $lut.
Using template $paramod$75ae9627805e0c99d176bdce0ae8ff0c02687aab\$lut for cells of type $lut.
Using template $paramod$6cc3cdc82e584933f4fc6e1edfa8d72302b10c65\$lut for cells of type $lut.
Using template $paramod$90dc599eed99da511e64ad217d69e7ff2c1e56cc\$lut for cells of type $lut.
Using template $paramod$0d26e42822227428593a6f2ed183ae9b22d4b575\$lut for cells of type $lut.
Using template $paramod$de9aab33012da19ffeb182c5e4187804106ad9c4\$lut for cells of type $lut.
Using template $paramod$44fcc0d917d393367c0a4bcbd086949175b57371\$lut for cells of type $lut.
Using template $paramod$b7c672fcf7668105521fbf740fd805b77b15726e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod$f34232779a0569d5ac41d2d692536961128467b0\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut.
Using template $paramod$d1239dea58a04f3eb43994cd44236e98b306ac2c\$lut for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
Using template $paramod$2382b0dd4cb27fd4312681c40a6dd179c2a7a26a\$lut for cells of type $lut.
Using template $paramod$a6597eda4608f36e684c1dd07ed552fcbec112b2\$lut for cells of type $lut.
Using template $paramod$525425bfbe66d72ee88210d059d9a74f55ab8de8\$lut for cells of type $lut.
Using template $paramod$3548f6e93628807ae6cc989ec88fe8ae640cb47a\$lut for cells of type $lut.
Using template $paramod$fe6c0411314a3ff40b7d35a8993243255e828e70\$lut for cells of type $lut.
Using template $paramod$3017f9ac05e2435ae8bd5f9ac8eba230835a3f43\$lut for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod$90dde3ec335fc6daa3fb20f8db8c84b4ceeaa590\$lut for cells of type $lut.
Using template $paramod$978d8ad561686e3ed18a9d86996356057000c9eb\$lut for cells of type $lut.
Using template $paramod$25003f26a78bb2f583f23824f1e0b8cc16b88761\$lut for cells of type $lut.
Using template $paramod$451971c01773c1fb2ca2963b8d409b9c2a046a2b\$lut for cells of type $lut.
Using template $paramod$6069048ea7c45159713a0558424cdfb243a46dfe\$lut for cells of type $lut.
Using template $paramod$83d958c6befa4a0c0692b78c5ac23caf619907de\$lut for cells of type $lut.
Using template $paramod$1f70022fed369fe3df7654b51b678246bc46a882\$lut for cells of type $lut.
Using template $paramod$2293a3909a50b655337c678da06427a7c5c5e0cc\$lut for cells of type $lut.
Using template $paramod$b45308ffeb4031bc5d55ef31b149afd94d3d7565\$lut for cells of type $lut.
Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d\$lut for cells of type $lut.
Using template $paramod$ee34d6146deb1bda84ff4bc527e617d989dee372\$lut for cells of type $lut.
Using template $paramod$97ff70229dc156acd2b0f6b32f500e9ef768ae47\$lut for cells of type $lut.
Using template $paramod$fc4c231d1b8b034b24b5324d045443e2e9694ca3\$lut for cells of type $lut.
Using template $paramod$2926b16e717affb5d0a151eb884ab0739856a29e\$lut for cells of type $lut.
Using template $paramod$5b4b4ed558983d9f3ab4c896a7a011d129b0db9a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod$86a69f95bdbfc36792b7c7498d3544468c88bd9a\$lut for cells of type $lut.
Using template $paramod$18e50808df562b188523e13714b96fedec6427c1\$lut for cells of type $lut.
Using template $paramod$bb4fff1cc3b827238aa40993cafede1c5beecbe3\$lut for cells of type $lut.
Using template $paramod$e934877433e628b9aa4b7cb2bee8957bca3e1db5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$0328e568d609989242dcb98a1c5328d4372a6e9c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut.
Using template $paramod$d198a35e390af0ebd4293772ba44e2470b1d193e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
No more expansions possible.
<suppressed ~8550 debug messages>

21.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in top.
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94855.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$9454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$9318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$9116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9384.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9384.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$9371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$9371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$9412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$9404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17724.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17724.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17718.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$9363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$9672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$9672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9666.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16957.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$16920.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8870.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$8866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9129.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15749.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$8944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$9273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$9273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$9273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9048.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9794.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$8805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$8805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$8805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$8786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$8561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$8561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$8539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$8490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8515.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8515.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8515.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8515.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8515.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8515.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$8717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$8717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$8691.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$8763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$8743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$8743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$8297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$8297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$8297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$8288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$8403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$8403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$8351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$8281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$8162.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$8162.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$8162.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8162.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$8145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$8114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$8252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$8212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$9527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$9516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$9516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8429.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8429.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8429.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8429.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8429.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8429.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$7826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9469.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$8709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$9070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$7338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7211.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7211.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7211.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7211.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7211.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7211.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$8066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$95007.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$8052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94998.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$95001.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$8041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$95004.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$95006.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$8034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$7964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$7687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$7948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94976.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$7904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$7147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$7119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$7119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$7066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$6999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$6963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$6908.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$95000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$95000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$95000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$6854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$6802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$6802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$7134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$6796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$6993.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6993.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6993.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6993.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6993.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6993.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6993.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$6877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$95005.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$7352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$7352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$7352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$7495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$7495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94971.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$6835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$7113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$6923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$6978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$6815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$6904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94993.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$7159.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7159.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6753.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10063.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10405.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10520.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10536.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10676.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10692.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10761.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10777.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10796.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10845.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10927.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10937.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10953.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$10985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11004.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11037.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11147.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11195.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11365.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11381.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11397.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11439.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11596.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11674.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11780.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11905.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11921.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11937.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11953.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11972.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$11988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12004.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12020.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12049.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12183.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12215.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12336.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12405.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12421.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12437.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12456.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12472.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12488.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12527.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12739.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12771.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12790.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12806.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12838.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$12956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13089.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13105.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13265.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13348.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13358.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13365.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13381.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13540.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13572.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13588.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13607.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13639.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13808.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13824.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13840.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$13951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14110.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14117.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14223.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14304.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14336.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14388.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14404.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14444.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14460.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14645.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14661.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14689.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14696.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14719.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14783.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14799.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14815.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14834.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14850.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14866.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14882.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14895.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$14973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15053.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15141.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15223.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15261.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15277.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15304.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$15320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$15339.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$15355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$15377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15393.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15409.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15425.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15584.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15699.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$15724.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15737.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15753.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$15766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$15770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$15801.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15862.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$15884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15897.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$15919.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15938.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$15983.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$16009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$16175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$16207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$16229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16245.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$16284.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16416.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16505.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$16553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$16575.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16588.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$16610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16697.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16761.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16823.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$16852.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$16874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16885.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$16895.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$16937.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$16947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$16970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$17117.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17133.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$17159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$17172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17185.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17195.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17205.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17221.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17243.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$17265.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$17300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$17345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$17367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17378.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$17390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17541.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$17605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17685.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17705.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$17734.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17799.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17877.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17887.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17907.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$17933.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$17962.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$17984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$18005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$18130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$18141.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$18163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$18179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$18192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$18211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$18232.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$18245.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$18261.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$18277.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$18288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$5816.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$5974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6321.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6409.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6478.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6511.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6529.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6547.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6585.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6603.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6684.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6753.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6758.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$6766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$6815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6993.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$6999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$7008.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7437.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$7099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$7134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$6815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7037.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7159.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7211.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7241.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7253.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$7352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7373.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$7398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94847.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7437.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$7449.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7457.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7464.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$95003.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$7540.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94967.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$7568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$7637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$7655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7863.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$7904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7941.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8003.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8066.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8242.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8409.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8429.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8465.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$8490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8515.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8281.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8645.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$8763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$8831.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8916.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9800.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8999.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9007.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9024.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$9116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9133.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9202.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9234.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$9250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$9290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$9318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9340.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9348.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$9378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$9404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9417.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$9424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9520.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9563.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9588.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$9597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9611.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$9627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9538.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$9725.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$9762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$9762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9810.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$9821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9845.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9853.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9871.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$9999.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$94810$lut$auto$opt_dff.cc:219:make_patterns_logic$2483.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94857.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94819.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94827.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94828.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94878.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94889.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94867.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94874.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94881.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94888.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94891.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$9058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94919.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94929.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$94810$lut$aiger94809$8189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94953.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$94810$lut$aiger94809$7099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7078.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7392.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$7056.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$94984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$7687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$7996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6881.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$6927.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$7046.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$94810$lut$aiger94809$8013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$95000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$94810$lut$aiger94809$7637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Removed 0 unused cells and 10942 unused wires.

21.45. Executing AUTONAME pass.
Renamed 319361 objects in module top (272 iterations).
<suppressed ~14661 debug messages>

21.46. Executing HIERARCHY pass (managing design hierarchy).

21.46.1. Analyzing design hierarchy..
Top module:  \top

21.46.2. Analyzing design hierarchy..
Top module:  \top
Removed 0 unused modules.

21.47. Printing statistics.

=== top ===

   Number of wires:               6133
   Number of wire bits:          16295
   Number of public wires:        6133
   Number of public wire bits:   16295
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               9203
     CCU2C                         132
     L6MUX21                       524
     LUT4                         5533
     PFUMX                        1211
     TRELLIS_DPR16X4               512
     TRELLIS_FF                   1291

21.48. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

21.49. Executing JSON backend.

Warnings: 258 unique messages, 259 total
End of script. Logfile hash: 642a4f50dd, CPU: user 9.07s system 0.11s, MEM: 215.80 MB peak
Yosys 0.36+8 (git sha1 fb4cbfa73, clang 10.0.0-4ubuntu1 -fPIC -Os)
Time spent: 35% 1x abc9_exe (5 sec), 14% 11x techmap (2 sec), ...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (NextPNR)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6
Info: constraining clock net 'clk' to 25.00 MHz

Info: Logic utilisation before packing:
Info:     Total LUT4s:      8869/43848    20%
Info:         logic LUTs:   5533/43848    12%
Info:         carry LUTs:    264/43848     0%
Info:           RAM LUTs:   2048/ 5481    37%
Info:          RAMW LUTs:   1024/10962     9%

Info:      Total DFFs:      1291/43848     2%

Info: Packing IOs..
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     263 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info:     promoting clock net clk_o to global network
Info:     promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x0a832edc

Info: Device utilisation:
Info: 	          TRELLIS_IO:    12/  245     4%
Info: 	                DCCA:     2/   56     3%
Info: 	              DP16KD:     0/  108     0%
Info: 	          MULT18X18D:     0/   72     0%
Info: 	              ALU54B:     0/   36     0%
Info: 	             EHXPLLL:     0/    4     0%
Info: 	             EXTREFB:     0/    2     0%
Info: 	                DCUA:     0/    2     0%
Info: 	           PCSCLKDIV:     0/    2     0%
Info: 	             IOLOGIC:     0/  160     0%
Info: 	            SIOLOGIC:     0/   85     0%
Info: 	                 GSR:     0/    1     0%
Info: 	               JTAGG:     0/    1     0%
Info: 	                OSCG:     0/    1     0%
Info: 	               SEDGA:     0/    1     0%
Info: 	                 DTR:     0/    1     0%
Info: 	             USRMCLK:     0/    1     0%
Info: 	             CLKDIVF:     0/    4     0%
Info: 	           ECLKSYNCB:     0/   10     0%
Info: 	             DLLDELD:     0/    8     0%
Info: 	              DDRDLL:     0/    4     0%
Info: 	             DQSBUFM:     0/   10     0%
Info: 	     TRELLIS_ECLKBUF:     0/    8     0%
Info: 	        ECLKBRIDGECS:     0/    2     0%
Info: 	                DCSC:     0/    2     0%
Info: 	          TRELLIS_FF:  1291/43848     2%
Info: 	        TRELLIS_COMB:  8919/43848    20%
Info: 	        TRELLIS_RAMW:   512/ 5481     9%

Info: Placed 12 cells based on constraints.
Info: Creating initial analytic placement for 5352 cells, random placement wirelen = 448469.
Info:     at initial placer iter 0, wirelen = 1031
Info:     at initial placer iter 1, wirelen = 956
Info:     at initial placer iter 2, wirelen = 1112
Info:     at initial placer iter 3, wirelen = 1146
Info: Running main analytical placer, max placement attempts per cell = 14407712.
Info:     at iteration #1, type ALL: wirelen solved = 1183, spread = 69322, legal = 70040; time = 0.29s
Info:     at iteration #2, type ALL: wirelen solved = 4630, spread = 48043, legal = 49049; time = 0.30s
Info:     at iteration #3, type ALL: wirelen solved = 11069, spread = 43139, legal = 44150; time = 0.28s
Info:     at iteration #4, type ALL: wirelen solved = 13423, spread = 42676, legal = 43750; time = 0.28s
Info:     at iteration #5, type ALL: wirelen solved = 15549, spread = 39468, legal = 40469; time = 0.27s
Info:     at iteration #6, type ALL: wirelen solved = 16622, spread = 37283, legal = 38795; time = 0.27s
Info:     at iteration #7, type ALL: wirelen solved = 17886, spread = 39244, legal = 39982; time = 0.26s
Info:     at iteration #8, type ALL: wirelen solved = 19682, spread = 38584, legal = 39316; time = 0.28s
Info:     at iteration #9, type ALL: wirelen solved = 20648, spread = 40100, legal = 40776; time = 0.28s
Info:     at iteration #10, type ALL: wirelen solved = 21914, spread = 41036, legal = 41688; time = 0.28s
Info:     at iteration #11, type ALL: wirelen solved = 22606, spread = 42519, legal = 43094; time = 0.28s
Info: HeAP Placer Time: 5.21s
Info:   of which solving equations: 3.26s
Info:   of which spreading cells: 0.41s
Info:   of which strict legalisation: 0.12s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 10751, wirelen = 38795
Info:   at iteration #5: temp = 0.000000, timing cost = 12100, wirelen = 31492
Info:   at iteration #10: temp = 0.000000, timing cost = 10343, wirelen = 29857
Info:   at iteration #15: temp = 0.000000, timing cost = 10632, wirelen = 28992
Info:   at iteration #20: temp = 0.000000, timing cost = 10398, wirelen = 28303
Info:   at iteration #25: temp = 0.000000, timing cost = 10594, wirelen = 28064
Info:   at iteration #30: temp = 0.000000, timing cost = 9094, wirelen = 27940
Info:   at iteration #33: temp = 0.000000, timing cost = 9039, wirelen = 27911 
Info: SA placement time 35.86s

Info: Max frequency for clock             '$glbnet$clk_o': 27.82 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 143.78 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 11.51 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 9.52 ns
Info: Max delay posedge $glbnet$clk_o             -> <async>                          : 13.84 ns

Info: Slack histogram:
Info:  legend: * represents 88 endpoint(s)
Info:          + represents [1,88) endpoint(s)
Info: [ 33045,  35522) |+
Info: [ 35522,  37999) |+
Info: [ 37999,  40476) |+
Info: [ 40476,  42953) | 
Info: [ 42953,  45430) | 
Info: [ 45430,  47907) |+
Info: [ 47907,  50384) |+
Info: [ 50384,  52861) |+
Info: [ 52861,  55338) |+
Info: [ 55338,  57815) |******+
Info: [ 57815,  60292) |*************+
Info: [ 60292,  62769) |**********************************************************+
Info: [ 62769,  65246) |************************************************************ 
Info: [ 65246,  67723) |******+
Info: [ 67723,  70200) |*****+
Info: [ 70200,  72677) |**+
Info: [ 72677,  75154) |****+
Info: [ 75154,  77631) |*******+
Info: [ 77631,  80108) |**+
Info: [ 80108,  82585) |+
Info: Checksum: 0x2038011c
Info: Routing globals...
Info:     routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info:     routing clock net $glbnet$clk_o using global 1

Info: Routing..
Info: Setting up routing queue.
Info: Routing 43137 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:       1000 |      161        838 |  161   838 |     42812|       0.70       0.70|
Info:       2000 |      240       1759 |   79   921 |     42557|       0.15       0.85|
Info:       3000 |      409       2590 |  169   831 |     42461|       0.16       1.01|
Info:       4000 |      572       3427 |  163   837 |     42359|       0.16       1.17|
Info:       5000 |      736       4263 |  164   836 |     41827|       0.15       1.32|
Info:       6000 |      913       5086 |  177   823 |     41294|       0.17       1.49|
Info:       7000 |     1080       5919 |  167   833 |     41502|       0.17       1.67|
Info:       8000 |     1255       6744 |  175   825 |     40976|       0.21       1.88|
Info:       9000 |     1457       7542 |  202   798 |     40670|       0.18       2.06|
Info:      10000 |     1568       8431 |  111   889 |     40916|       0.18       2.24|
Info:      11000 |     1668       9331 |  100   900 |     40298|       0.20       2.44|
Info:      12000 |     1845      10154 |  177   823 |     39880|       0.19       2.63|
Info:      13000 |     2054      10945 |  209   791 |     39705|       0.18       2.81|
Info:      14000 |     2226      11773 |  172   828 |     39571|       0.18       2.99|
Info:      15000 |     2303      12696 |   77   923 |     39456|       0.17       3.16|
Info:      16000 |     2468      13531 |  165   835 |     39089|       0.18       3.34|
Info:      17000 |     2638      14361 |  170   830 |     38538|       0.19       3.53|
Info:      18000 |     2822      15177 |  184   816 |     38447|       0.21       3.74|
Info:      19000 |     3003      15996 |  181   819 |     38071|       0.19       3.93|
Info:      20000 |     3173      16826 |  170   830 |     37742|       0.19       4.12|
Info:      21000 |     3228      17771 |   55   945 |     37694|       0.17       4.29|
Info:      22000 |     3420      18579 |  192   808 |     37422|       0.20       4.49|
Info:      23000 |     3582      19417 |  162   838 |     37819|       0.20       4.69|
Info:      24000 |     3671      20328 |   89   911 |     38241|       0.17       4.87|
Info:      25000 |     3724      21275 |   53   947 |     37825|       0.16       5.02|
Info:      26000 |     3877      22122 |  153   847 |     37457|       0.18       5.20|
Info:      27000 |     4008      22991 |  131   869 |     37599|       0.18       5.38|
Info:      28000 |     4168      23831 |  160   840 |     37085|       0.19       5.57|
Info:      29000 |     4394      24605 |  226   774 |     36797|       0.22       5.79|
Info:      30000 |     4532      25467 |  138   862 |     36701|       0.22       6.01|
Info:      31000 |     4722      26277 |  190   810 |     36429|       0.17       6.18|
Info:      32000 |     4962      27037 |  240   760 |     35965|       0.21       6.39|
Info:      33000 |     5134      27865 |  172   828 |     35677|       0.20       6.59|
Info:      34000 |     5294      28705 |  160   840 |     35719|       0.22       6.81|
Info:      35000 |     5529      29470 |  235   765 |     35362|       0.22       7.03|
Info:      36000 |     5785      30214 |  256   744 |     35120|       0.21       7.24|
Info:      37000 |     6032      30967 |  247   753 |     34654|       0.22       7.46|
Info:      38000 |     6278      31721 |  246   754 |     34137|       0.23       7.69|
Info:      39000 |     6502      32497 |  224   776 |     33718|       0.22       7.90|
Info:      40000 |     6703      33296 |  201   799 |     33370|       0.23       8.13|
Info:      41000 |     6952      34047 |  249   751 |     33030|       0.23       8.36|
Info:      42000 |     7179      34820 |  227   773 |     32753|       0.21       8.57|
Info:      43000 |     7390      35609 |  211   789 |     32554|       0.23       8.80|
Info:      44000 |     7640      36359 |  250   750 |     32116|       0.22       9.02|
Info:      45000 |     7965      37034 |  325   675 |     32020|       0.23       9.25|
Info:      46000 |     8232      37767 |  267   733 |     31694|       0.24       9.49|
Info:      47000 |     8518      38481 |  286   714 |     31333|       0.24       9.73|
Info:      48000 |     8853      39146 |  335   665 |     31075|       0.24       9.97|
Info:      49000 |     9141      39858 |  288   712 |     30718|       0.24      10.21|
Info:      50000 |     9460      40539 |  319   681 |     30466|       0.27      10.48|
Info:      51000 |     9827      41172 |  367   633 |     30262|       0.28      10.76|
Info:      52000 |    10117      41882 |  290   710 |     29964|       0.27      11.04|
Info:      53000 |    10446      42553 |  329   671 |     29915|       0.27      11.31|
Info:      54000 |    10687      43312 |  241   759 |     29640|       0.23      11.53|
Info:      55000 |    10719      44280 |   32   968 |     30061|       0.17      11.70|
Info:      56000 |    10760      45239 |   41   959 |     29567|       0.17      11.88|
Info:      57000 |    11027      45972 |  267   733 |     29360|       0.25      12.13|
Info:      58000 |    11318      46681 |  291   709 |     29114|       0.24      12.37|
Info:      59000 |    11626      47373 |  308   692 |     28814|       0.26      12.63|
Info:      60000 |    11959      48040 |  333   667 |     28456|       0.29      12.92|
Info:      61000 |    12243      48756 |  284   716 |     28707|       0.28      13.20|
Info:      62000 |    12425      49574 |  182   818 |     28205|       0.22      13.42|
Info:      63000 |    12747      50252 |  322   678 |     27869|       0.26      13.68|
Info:      64000 |    12992      51007 |  245   755 |     27795|       0.25      13.93|
Info:      65000 |    13249      51750 |  257   743 |     27523|       0.25      14.18|
Info:      66000 |    13553      52446 |  304   696 |     27316|       0.31      14.49|
Info:      67000 |    13866      53133 |  313   687 |     27077|       0.29      14.78|
Info:      68000 |    14300      53699 |  434   566 |     27101|       0.37      15.15|
Info:      69000 |    14640      54359 |  340   660 |     26861|       0.29      15.45|
Info:      70000 |    14935      55064 |  295   705 |     26783|       0.33      15.78|
Info:      71000 |    15322      55677 |  387   613 |     26536|       0.36      16.13|
Info:      72000 |    15704      56295 |  382   618 |     26287|       0.32      16.46|
Info:      73000 |    16002      56997 |  298   702 |     25975|       0.27      16.73|
Info:      74000 |    16319      57680 |  317   683 |     25641|       0.29      17.02|
Info:      75000 |    16607      58392 |  288   712 |     25434|       0.30      17.31|
Info:      76000 |    16924      59075 |  317   683 |     25119|       0.30      17.61|
Info:      77000 |    17304      59695 |  380   620 |     24825|       0.31      17.92|
Info:      78000 |    17671      60328 |  367   633 |     24644|       0.35      18.26|
Info:      79000 |    18018      60981 |  347   653 |     24399|       0.34      18.61|
Info:      80000 |    18395      61604 |  377   623 |     24333|       0.39      19.00|
Info:      81000 |    18644      62355 |  249   751 |     24740|       0.28      19.27|
Info:      82000 |    18810      63189 |  166   834 |     24108|       0.26      19.53|
Info:      83000 |    19078      63921 |  268   732 |     23882|       0.27      19.80|
Info:      84000 |    19411      64588 |  333   667 |     23742|       0.32      20.12|
Info:      85000 |    19752      65247 |  341   659 |     23471|       0.36      20.47|
Info:      86000 |    20145      65854 |  393   607 |     23540|       0.31      20.78|
Info:      87000 |    20511      66488 |  366   634 |     23220|       0.32      21.11|
Info:      88000 |    20765      67234 |  254   746 |     23126|       0.30      21.41|
Info:      89000 |    21129      67870 |  364   636 |     23024|       0.36      21.77|
Info:      90000 |    21476      68523 |  347   653 |     22904|       0.30      22.07|
Info:      91000 |    21868      69131 |  392   608 |     22658|       0.33      22.40|
Info:      92000 |    22229      69770 |  361   639 |     22385|       0.33      22.73|
Info:      93000 |    22567      70432 |  338   662 |     22153|       0.29      23.02|
Info:      94000 |    22888      71111 |  321   679 |     21891|       0.29      23.31|
Info:      95000 |    23279      71720 |  391   609 |     21690|       0.41      23.72|
Info:      96000 |    23678      72321 |  399   601 |     21446|       0.37      24.09|
Info:      97000 |    24028      72971 |  350   650 |     21679|       0.34      24.43|
Info:      98000 |    24258      73741 |  230   770 |     21395|       0.28      24.71|
Info:      99000 |    24615      74384 |  357   643 |     21192|       0.34      25.05|
Info:     100000 |    24940      75059 |  325   675 |     20972|       0.31      25.37|
Info:     101000 |    25275      75724 |  335   665 |     20675|       0.31      25.68|
Info:     102000 |    25656      76343 |  381   619 |     20502|       0.32      26.00|
Info:     103000 |    25824      77175 |  168   832 |     20368|       0.28      26.28|
Info:     104000 |    26161      77838 |  337   663 |     20082|       0.30      26.58|
Info:     105000 |    26383      78616 |  222   778 |     21007|       0.26      26.84|
Info:     106000 |    26624      79375 |  241   759 |     20991|       0.28      27.12|
Info:     107000 |    26834      80165 |  210   790 |     20844|       0.26      27.39|
Info:     108000 |    27044      80955 |  210   790 |     20298|       0.28      27.67|
Info:     109000 |    27424      81575 |  380   620 |     19986|       0.36      28.03|
Info:     110000 |    27861      82138 |  437   563 |     19678|       0.30      28.32|
Info:     111000 |    28286      82713 |  425   575 |     19533|       0.36      28.68|
Info:     112000 |    28722      83277 |  436   564 |     19365|       0.31      28.99|
Info:     113000 |    29138      83861 |  416   584 |     19116|       0.30      29.29|
Info:     114000 |    29588      84411 |  450   550 |     19024|       0.36      29.65|
Info:     115000 |    29915      85084 |  327   673 |     18917|       0.32      29.97|
Info:     116000 |    30290      85709 |  375   625 |     18800|       0.33      30.30|
Info:     117000 |    30512      86487 |  222   778 |     18748|       0.30      30.60|
Info:     118000 |    30886      87113 |  374   626 |     18472|       0.29      30.88|
Info:     119000 |    31162      87837 |  276   724 |     18378|       0.29      31.18|
Info:     120000 |    31465      88534 |  303   697 |     18364|       0.32      31.50|
Info:     121000 |    31883      89116 |  418   582 |     18175|       0.34      31.84|
Info:     122000 |    32292      89707 |  409   591 |     17936|       0.30      32.14|
Info:     123000 |    32786      90213 |  494   506 |     17755|       0.33      32.47|
Info:     124000 |    33247      90752 |  461   539 |     17605|       0.29      32.76|
Info:     125000 |    33769      91230 |  522   478 |     17388|       0.33      33.09|
Info:     126000 |    34237      91762 |  468   532 |     17231|       0.35      33.43|
Info:     127000 |    34754      92245 |  517   483 |     17094|       0.32      33.76|
Info:     128000 |    35238      92761 |  484   516 |     16928|       0.36      34.11|
Info:     129000 |    35826      93173 |  588   412 |     16725|       0.29      34.40|
Info:     130000 |    36251      93748 |  425   575 |     16633|       0.34      34.74|
Info:     131000 |    36760      94239 |  509   491 |     16429|       0.28      35.02|
Info:     132000 |    37246      94753 |  486   514 |     16231|       0.33      35.35|
Info:     133000 |    37739      95260 |  493   507 |     16021|       0.29      35.65|
Info:     134000 |    38110      95889 |  371   629 |     16157|       0.29      35.93|
Info:     135000 |    38490      96509 |  380   620 |     15821|       0.33      36.26|
Info:     136000 |    38983      96994 |  493   485 |     15607|       0.32      36.58|
Info:     137000 |    39342      97635 |  359   641 |     15544|       0.33      36.91|
Info:     138000 |    39793      98171 |  451   536 |     15320|       0.35      37.26|
Info:     139000 |    40318      98599 |  525   428 |     15039|       0.32      37.59|
Info:     140000 |    40730      99180 |  412   581 |     15010|       0.46      38.05|
Info:     141000 |    41215      99641 |  485   461 |     14776|       0.34      38.39|
Info:     142000 |    41760     100072 |  545   431 |     14606|       0.33      38.72|
Info:     143000 |    42216     100564 |  456   492 |     14361|       0.32      39.04|
Info:     144000 |    42758     100942 |  542   378 |     13992|       0.31      39.35|
Info:     145000 |    43296     101346 |  538   404 |     13683|       0.26      39.61|
Info:     146000 |    43801     101764 |  505   418 |     13326|       0.27      39.88|
Info:     147000 |    44266     102226 |  465   462 |     12915|       0.25      40.13|
Info:     148000 |    44686     102720 |  420   494 |     12536|       0.28      40.41|
Info:     149000 |    45144     103198 |  458   478 |     12246|       0.29      40.70|
Info:     150000 |    45633     103657 |  489   459 |     12029|       0.29      40.99|
Info:     151000 |    46006     104275 |  373   618 |     11943|       0.43      41.42|
Info:     152000 |    46425     104841 |  419   566 |     11871|       0.46      41.88|
Info:     153000 |    46675     105533 |  250   692 |     12194|       0.31      42.18|
Info:     154000 |    46925     106283 |  250   750 |     11788|       0.36      42.54|
Info:     155000 |    47329     106851 |  404   568 |     11414|       0.32      42.86|
Info:     156000 |    47534     107601 |  205   750 |     10697|       0.20      43.06|
Info:     157000 |    47645     108479 |  111   878 |      9852|       0.13      43.20|
Info:     158000 |    47722     109394 |   77   915 |      8988|       0.14      43.34|
Info:     159000 |    47795     110315 |   73   921 |      8128|       0.15      43.49|
Info:     160000 |    47848     111259 |   53   944 |      7195|       0.11      43.60|
Info:     161000 |    47973     112129 |  125   870 |      6376|       0.16      43.76|
Info:     162000 |    48053     113048 |   80   919 |      5475|       0.15      43.91|
Info:     163000 |    48150     113946 |   97   898 |      4621|       0.16      44.07|
Info:     164000 |    48392     114683 |  242   737 |      4033|       0.28      44.36|
Info:     165000 |    48759     115312 |  367   629 |      3623|       0.40      44.76|
Info:     166000 |    49130     115939 |  371   627 |      3156|       0.40      45.16|
Info:     167000 |    49546     116510 |  416   571 |      2691|       0.37      45.53|
Info:     168000 |    50038     117005 |  492   495 |      2294|       0.42      45.95|
Info:     169000 |    50469     117560 |  431   555 |      1842|       0.36      46.32|
Info:     170000 |    50968     118054 |  499   494 |      1609|       0.50      46.81|
Info:     171000 |    51487     118535 |  519   481 |      1444|       0.50      47.31|
Info:     172000 |    51996     119025 |  509   490 |      1086|       0.44      47.75|
Info:     173000 |    52540     119481 |  544   456 |       869|       0.43      48.18|
Info:     174000 |    53113     119899 |  573   418 |       615|       0.47      48.65|
Info:     174943 |    53320     120256 |  207   357 |         0|       0.29      48.95|
Info: Routing complete.
Info: Router1 time 48.95s
Info: Checksum: 0x8f8648c6

Info: Critical path report for clock '$glbnet$clk_o' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q.Q
Info:  0.9  1.4    Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_PFUMX_Z_C0_LUT4_C_1_B_LUT4_D_C_LUT4_D_A[0] (28,39) -> (28,39)
Info:                Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_PFUMX_Z_C0_LUT4_C_1_B_LUT4_Z.B
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:40.3-46.2
Info:                  Risco-5/src/core/core.v:97.14-113.2
Info:                  Risco-5/src/core/control_unit.v:25.11-25.16
Info:                  Risco-5/src/peripheral/soc.v:25.3-33.2
Info:  0.2  1.6  Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_PFUMX_Z_C0_LUT4_C_1_B_LUT4_Z.F
Info:  1.0  2.7    Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_PFUMX_Z_C0_LUT4_C_1_B[3] (28,39) -> (30,36)
Info:                Sink SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_PFUMX_Z_C0_LUT4_C_1_B_LUT4_D.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  2.9  Source SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_PFUMX_Z_C0_LUT4_C_1_B_LUT4_D.F
Info:  2.3  5.2    Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_D_PFUMX_Z_C0_LUT4_C_1_B_LUT4_D_Z[2] (30,36) -> (40,21)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  5.4  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_LUT4_Z.F
Info:  2.1  7.5    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0 (40,21) -> (29,28)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.B
Info:  0.4  7.9  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  7.9    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (29,28) -> (29,28)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  7.9  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  7.9    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_CIN (29,28) -> (29,28)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:40.3-46.2
Info:                  Risco-5/src/peripheral/bus.v:44.5-44.37
Info:                  Risco-5/src/peripheral/soc.v:48.5-72.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  8.0  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  8.0    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (29,28) -> (29,28)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  8.0  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  8.0    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_CIN (29,28) -> (29,28)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:40.3-46.2
Info:                  Risco-5/src/peripheral/bus.v:44.5-44.37
Info:                  Risco-5/src/peripheral/soc.v:48.5-72.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  8.1  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  8.1    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (29,28) -> (29,28)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  8.1  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  8.1    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_CIN (29,28) -> (29,28)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:40.3-46.2
Info:                  Risco-5/src/peripheral/bus.v:44.5-44.37
Info:                  Risco-5/src/peripheral/soc.v:48.5-72.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  8.1  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  8.1    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (29,28) -> (29,28)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  8.1  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  8.1    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_CIN (29,28) -> (30,28)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:40.3-46.2
Info:                  Risco-5/src/peripheral/bus.v:44.5-44.37
Info:                  Risco-5/src/peripheral/soc.v:48.5-72.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  8.2  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  8.2    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (30,28) -> (30,28)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  8.2  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  8.2    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_CIN (30,28) -> (30,28)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:40.3-46.2
Info:                  Risco-5/src/peripheral/bus.v:44.5-44.37
Info:                  Risco-5/src/peripheral/soc.v:48.5-72.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  8.3  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  8.3    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (30,28) -> (30,28)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  8.3  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  8.3    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (30,28) -> (30,28)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:40.3-46.2
Info:                  Risco-5/src/peripheral/bus.v:44.5-44.37
Info:                  Risco-5/src/peripheral/soc.v:48.5-72.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  8.3  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  8.3    Net SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (30,28) -> (30,28)
Info:                Sink SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  8.3  Source SOC.Uart.i_uart_tx.uart_tx_data_LUT4_Z_C_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  8.3    Net $nextpnr_CCU2C_3$CIN (30,28) -> (30,28)
Info:                Sink $nextpnr_CCU2C_3$CCU2_COMB0.FCI
Info:  0.4  8.8  Source $nextpnr_CCU2C_3$CCU2_COMB0.F
Info:  1.8 10.6    Net SOC.Core.read_data_PFUMX_Z_8_C0_LUT4_Z_1_A[1] (30,28) -> (11,27)
Info:                Sink SOC.Memory.address_LUT4_Z_2.D
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:40.3-46.2
Info:                  Risco-5/src/peripheral/bus.v:44.5-44.37
Info:                  Risco-5/src/peripheral/soc.v:48.5-72.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.2 10.8  Source SOC.Memory.address_LUT4_Z_2.F
Info:  2.4 13.2    Net SOC.slave_address[3] (11,27) -> (9,12)
Info:                Sink SOC.Memory.memory.0.398$DPRAM_COMB1.B
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:40.3-46.2
Info:                  Risco-5/src/peripheral/soc.v:19.5-19.18
Info:  0.2 13.4  Source SOC.Memory.memory.0.398$DPRAM_COMB1.F
Info:  1.4 14.8    Net SOC.Memory.memory.0.398_DO_1[3] (9,12) -> (4,11)
Info:                Sink SOC.Memory.memory.0.422_DO_2_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 15.1  Source SOC.Memory.memory.0.422_DO_2_LUT4_Z.F
Info:  0.9 15.9    Net SOC.Memory.memory.0.422_DO_2[3] (4,11) -> (3,11)
Info:                Sink SOC.Memory.memory.0.390_DO_2_PFUMX_Z_ALUT_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 16.2  Source SOC.Memory.memory.0.390_DO_2_PFUMX_Z_ALUT_LUT4_Z.F
Info:  0.0 16.2    Net SOC.Memory.memory.0.390_DO_2_PFUMX_Z_ALUT (3,11) -> (3,11)
Info:                Sink SOC.Memory.memory.0.390_DO_2_PFUMX_Z_BLUT_LUT4_Z.F1
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info:  0.2 16.3  Source SOC.Memory.memory.0.390_DO_2_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  0.7 17.0    Net SOC.Memory.memory.0.390_DO_2[3] (3,11) -> (5,12)
Info:                Sink SOC.Memory.memory.0.390_DO_2_LUT4_B.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 17.3  Source SOC.Memory.memory.0.390_DO_2_LUT4_B.F
Info:  1.1 18.4    Net SOC.Memory.memory.0.462_DO_2_LUT4_B_Z[2] (5,12) -> (3,14)
Info:                Sink SOC.Core.read_data_PFUMX_Z_11_C0_LUT4_Z_1_B_LUT4_Z.C
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 18.7  Source SOC.Core.read_data_PFUMX_Z_11_C0_LUT4_Z_1_B_LUT4_Z.F
Info:  1.0 19.7    Net SOC.Core.read_data_PFUMX_Z_11_C0_LUT4_Z_1_B[3] (3,14) -> (3,18)
Info:                Sink SOC.Core.read_data_PFUMX_Z_11_C0_LUT4_Z_1.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 19.9  Source SOC.Core.read_data_PFUMX_Z_11_C0_LUT4_Z_1.F
Info:  1.3 21.2    Net SOC.Core.read_data_PFUMX_Z_11_C0[4] (3,18) -> (14,19)
Info:                Sink SOC.Core.read_data_PFUMX_Z_11_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 21.5  Source SOC.Core.read_data_PFUMX_Z_11_BLUT_LUT4_Z.OFX
Info:  2.1 23.6    Net SOC.read_data[25] (14,19) -> (28,32)
Info:                Sink SOC.Core.memory_register_TRELLIS_FF_Q_6.M
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:40.3-46.2
Info:                  Risco-5/src/peripheral/soc.v:18.34-18.43
Info:  0.0 23.6  Setup SOC.Core.memory_register_TRELLIS_FF_Q_6.M
Info: 4.6 ns logic, 19.0 ns routing

Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source ClkDivider.clk_counter_TRELLIS_FF_Q_19.Q
Info:  1.4  1.9    Net ClkDivider.clk_counter[12] (44,11) -> (45,13)
Info:                Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.B
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:14.3-22.2
Info:                  Risco-5/debug/clk_divider.v:14.26-14.37
Info:  0.4  2.3  Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.3    Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (45,13) -> (45,13)
Info:                Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.3  Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.3    Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (45,13) -> (45,13)
Info:                Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:14.3-22.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.4  Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.4    Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (45,13) -> (45,13)
Info:                Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.4  Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.4    Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (45,13) -> (45,13)
Info:                Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:14.3-22.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.5  Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.5    Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (45,13) -> (45,13)
Info:                Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.5  Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.5    Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (45,13) -> (45,13)
Info:                Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:14.3-22.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.5  Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.5    Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (45,13) -> (45,13)
Info:                Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.5  Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.5    Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (45,13) -> (46,13)
Info:                Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:14.3-22.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.6  Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.6    Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (46,13) -> (46,13)
Info:                Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.6  Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.6    Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (46,13) -> (46,13)
Info:                Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:14.3-22.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.7  Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.7    Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (46,13) -> (46,13)
Info:                Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.7  Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.7    Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (46,13) -> (46,13)
Info:                Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:14.3-22.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.8  Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.8    Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (46,13) -> (46,13)
Info:                Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.8  Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.8    Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (46,13) -> (46,13)
Info:                Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:14.3-22.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.8  Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.8    Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (46,13) -> (46,13)
Info:                Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.8  Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.8    Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (46,13) -> (47,13)
Info:                Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:14.3-22.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.9  Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.9    Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (47,13) -> (47,13)
Info:                Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.9  Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.9    Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT_CIN (47,13) -> (47,13)
Info:                Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:14.3-22.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  3.0  Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  3.0    Net reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (47,13) -> (47,13)
Info:                Sink reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  3.0  Source reset_LUT4_C_D_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  3.0    Net $nextpnr_CCU2C_7$CIN (47,13) -> (47,13)
Info:                Sink $nextpnr_CCU2C_7$CCU2_COMB0.FCI
Info:  0.4  3.4  Source $nextpnr_CCU2C_7$CCU2_COMB0.F
Info:  0.4  3.8    Net reset_LUT4_C_D_LUT4_Z_D (47,13) -> (47,13)
Info:                Sink reset_LUT4_C_D_LUT4_Z.D
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:14.3-22.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.2  4.1  Source reset_LUT4_C_D_LUT4_Z.F
Info:  1.1  5.2    Net reset_LUT4_C_D[1] (47,13) -> (45,12)
Info:                Sink reset_LUT4_A.B
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  5.4  Source reset_LUT4_A.F
Info:  0.0  5.4    Net reset_LUT4_A_Z (45,12) -> (45,12)
Info:                Sink reset_LUT4_C.F1
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info:  0.2  5.6  Source reset_LUT4_C.OFX
Info:  0.8  6.4    Net reset_LUT4_A_Z_PFUMX_ALUT_Z (45,12) -> (43,14)
Info:                Sink ClkDivider.clk_counter_TRELLIS_FF_Q_31.LSR
Info:  0.4  6.8  Setup ClkDivider.clk_counter_TRELLIS_FF_Q_31.LSR
Info: 3.1 ns logic, 3.7 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info:  0.0  0.0  Source reset$tr_io.O
Info:  4.1  4.1    Net reset$TRELLIS_IO_IN (0,29) -> (45,12)
Info:                Sink reset_LUT4_A.A
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  4.3  Source reset_LUT4_A.F
Info:  0.0  4.3    Net reset_LUT4_A_Z (45,12) -> (45,12)
Info:                Sink reset_LUT4_C.F1
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info:  0.2  4.5  Source reset_LUT4_C.OFX
Info:  0.8  5.3    Net reset_LUT4_A_Z_PFUMX_ALUT_Z (45,12) -> (43,14)
Info:                Sink ClkDivider.clk_counter_TRELLIS_FF_Q_31.LSR
Info:  0.4  5.7  Setup ClkDivider.clk_counter_TRELLIS_FF_Q_31.LSR
Info: 0.8 ns logic, 4.9 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source ClkDivider.clk_o_auto_TRELLIS_FF_Q.Q
Info:  3.0  3.5    Net clk_o (47,12) -> (85,19)
Info:                Sink led_LUT4_Z_6.D
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:9.6-9.11
Info:  0.2  3.7  Source led_LUT4_Z_6.F
Info:  1.4  5.1    Net led[7]$TRELLIS_IO_OUT (85,19) -> (90,20)
Info:                Sink led[7]$tr_io.I
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 4.3 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk_o' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source SOC.Leds.data_TRELLIS_FF_Q_29.Q
Info:  4.4  5.0    Net SOC.Core.read_data_LUT4_Z_D[0] (22,29) -> (78,37)
Info:                Sink led_LUT4_Z_7.D
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:40.3-46.2
Info:                  Risco-5/src/peripheral/leds.v:15.12-15.16
Info:                  Risco-5/src/peripheral/soc.v:74.6-83.2
Info:  0.2  5.2  Source led_LUT4_Z_7.F
Info:  2.1  7.3    Net led[2]$TRELLIS_IO_OUT (78,37) -> (90,44)
Info:                Sink led[2]$tr_io.I
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 6.5 ns routing

Info: Max frequency for clock             '$glbnet$clk_o': 42.31 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 146.24 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.69 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 5.10 ns
Info: Max delay posedge $glbnet$clk_o             -> <async>                          : 7.27 ns

Info: Slack histogram:
Info:  legend: * represents 144 endpoint(s)
Info:          + represents [1,144) endpoint(s)
Info: [ 33162,  35615) |+
Info: [ 35615,  38068) |+
Info: [ 38068,  40521) |+
Info: [ 40521,  42974) | 
Info: [ 42974,  45427) | 
Info: [ 45427,  47880) | 
Info: [ 47880,  50333) | 
Info: [ 50333,  52786) | 
Info: [ 52786,  55239) | 
Info: [ 55239,  57692) | 
Info: [ 57692,  60145) |+
Info: [ 60145,  62598) |+
Info: [ 62598,  65051) |+
Info: [ 65051,  67504) |****+
Info: [ 67504,  69957) |*********************+
Info: [ 69957,  72410) |************************************************************ 
Info: [ 72410,  74863) |*****+
Info: [ 74863,  77316) |*****+
Info: [ 77316,  79769) |*****+
Info: [ 79769,  82222) |+

Info: Program finished normally.
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/darksocv.cfg --bit ./build/darksocv.bit
Failed to open input file
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (openFPGAloader)
Stage "openFPGAloader" skipped due to earlier failure(s)
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE