*.fs
impl/
x.*
build/
rascunho.v
fpga/digilent_arty/vivado_131673.backup.jou
fpga/digilent_arty/vivado_131673.backup.log
fpga/digilent_arty/vivado.jou
fpga/digilent_arty/vivado.log
fpga/digilent_arty/digilent_arty_timing_synth.rpt
fpga/digilent_arty/digilent_arty_route.dcp
fpga/digilent_arty/clockInfo.txt
fpga/digilent_arty/digilent_arty_place.dcp
env/
fpga/digilent_arty/tight_setup_hold_pins.txt
fpga/nexys4_ddr/clockInfo.txt
fpga/nexys4_ddr/digilent_nexys4ddr_utilization_place.rpt
fpga/nexys4_ddr/digilent_nexys4ddr_utilization_hierarchical_place.rpt
fpga/nexys4_ddr/digilent_nexys4ddr_io.rpt
fpga/nexys4_ddr/digilent_nexys4ddr_control_sets.rpt
fpga/nexys4_ddr/digilent_nexys4ddr_clock_utilization.rpt
fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt
fpga/nexys4_ddr/digilent_nexys4ddr_power.rpt
fpga/nexys4_ddr/digilent_nexys4ddr_route_status.rpt
fpga/nexys4_ddr/digilent_nexys4ddr_timing.rpt
site/
fpga/xilinx_vc709/usage_statistics_webtalk.xml
fpga/xilinx_vc709/usage_statistics_webtalk.html
fpga/xilinx_vc709/tight_setup_hold_pins.txt
fpga/xilinx_vc709/webtalk.log
fpga/xilinx_vc709/webtalk.jou
*.backup.log
*.backup.jou
rascunho/
.vscode/settings.json
fpga/de1soc/c5_pin_model_dump.txt