<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
    <Template>FPGA</Template>
    <Version>5</Version>
    <Device name="GW2AR-18C" pn="GW2AR-LV18QN88PC8/I7">gw2ar18c-011</Device>
    <FileList>
        <File path="main.v" type="file.verilog" enable="1"/>
        <File path="../../debug/reset.v" type="file.verilog" enable="1"/>
        <File path="pinout.cst" type="file.cst" enable="1"/>
        <File path="../../src/core/alu_control.v" type="file.verilog" enable="1"/>
        <File path="../../src/core/alu.v" type="file.verilog" enable="1"/>
        <File path="../../src/core/control_unit.v" type="file.verilog" enable="1"/>
        <File path="../../src/core/core.v" type="file.verilog" enable="1"/>
        <File path="../../src/core/immediate_generator.v" type="file.verilog" enable="1"/>
        <File path="../../src/core/mux.v" type="file.verilog" enable="1"/>
        <File path="../../src/core/pc.v" type="file.verilog" enable="1"/>
        <File path="../../src/core/registers.v" type="file.verilog" enable="1"/>
        <File path="../../src/core/csr_unit.v" type="file.verilog" enable="1"/>
        <File path="../../src/peripheral/fifo.v" type="file.verilog" enable="1"/>
        <File path="../../src/peripheral/bus.v" type="file.verilog" enable="1"/>
        <File path="../../src/peripheral/gpio.v" type="file.verilog" enable="1"/>
        <File path="../../src/peripheral/gpios.v" type="file.verilog" enable="1"/>
        <File path="../../src/peripheral/leds.v" type="file.verilog" enable="1"/>
        <File path="../../src/peripheral/memory.v" type="file.verilog" enable="1"/>
        <File path="../../src/peripheral/soc.v" type="file.verilog" enable="1"/>
        <File path="../../src/peripheral/uart_rx.v" type="file.verilog" enable="1"/>
        <File path="../../src/peripheral/uart_tx.v" type="file.verilog" enable="1"/>
        <File path="../../src/peripheral/uart.v" type="file.verilog" enable="1"/>
    </FileList>
</Project>
