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# Your use of Intel Corporation's design tools, logic functions 
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# Quartus Prime
# Version 24.1.0 Build 115 03/21/2024 SC Pro Edition
# Date created = 11:07:47  June 18, 2024
#
# -------------------------------------------------------------------------- #
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 23.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:07:47  JUNE 18, 2024"
set_global_assignment -name LAST_QUARTUS_VERSION "23.1.0 Pro Edition"
set_global_assignment -name FAMILY "Cyclone 10 GX"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY build
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name DEVICE 10CX220YF780E5G
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name VERILOG_FILE main.v
set_global_assignment -name VERILOG_FILE ../../src/core/core.v
set_global_assignment -name VERILOG_FILE ../../src/core/alu_control.v
set_global_assignment -name VERILOG_FILE ../../src/core/alu.v
set_global_assignment -name VERILOG_FILE ../../src/core/control_unit.v
set_global_assignment -name VERILOG_FILE ../../src/core/csr_unit.v
set_global_assignment -name VERILOG_FILE ../../src/core/immediate_generator.v
set_global_assignment -name VERILOG_FILE ../../src/core/mdu.v
set_global_assignment -name VERILOG_FILE ../../src/core/mux.v
set_global_assignment -name VERILOG_FILE ../../src/core/pc.v
set_global_assignment -name VERILOG_FILE ../../src/core/registers.v
set_global_assignment -name VERILOG_FILE ../../src/peripheral/bus.v
set_global_assignment -name VERILOG_FILE ../../src/peripheral/fifo.v
set_global_assignment -name VERILOG_FILE ../../src/peripheral/gpio.v
set_global_assignment -name VERILOG_FILE ../../src/peripheral/gpios.v
set_global_assignment -name VERILOG_FILE ../../src/peripheral/leds.v
set_global_assignment -name VERILOG_FILE ../../src/peripheral/memory.v
set_global_assignment -name VERILOG_FILE ../../src/peripheral/soc.v
set_global_assignment -name VERILOG_FILE ../../src/peripheral/uart_rx.v
set_global_assignment -name VERILOG_FILE ../../src/peripheral/uart_tx.v
set_global_assignment -name VERILOG_FILE ../../src/peripheral/uart.v
set_global_assignment -name VERILOG_FILE ../../src/peripheral/pwm.v
set_global_assignment -name VERILOG_FILE ../../debug/reset.v
set_location_assignment PIN_J23 -to clk
set_location_assignment PIN_AF6 -to led
set_instance_assignment -name IO_STANDARD "1.8 V" -to led -entity top
set_instance_assignment -name IO_STANDARD "1.8 V" -to clk -entity top
set_global_assignment -name SDC_FILE pinout.sdc
