Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date         : Sat Jul 11 21:12:40 2026
| Host         : 685a421e500f running 64-bit unknown
| Command      : report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
| Design       : fpga_top
| Device       : xc7a100t
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |    99 |
|    Minimum number of control sets                        |    99 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |   103 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |    99 |
| >= 0 to < 4        |     4 |
| >= 4 to < 6        |     6 |
| >= 6 to < 8        |     1 |
| >= 8 to < 10       |     7 |
| >= 10 to < 12      |     4 |
| >= 12 to < 14      |     3 |
| >= 14 to < 16      |     0 |
| >= 16              |    74 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |               7 |            5 |
| No           | No                    | Yes                    |               0 |            0 |
| No           | Yes                   | No                     |             363 |          118 |
| Yes          | No                    | No                     |            1320 |          586 |
| Yes          | No                    | Yes                    |              32 |            8 |
| Yes          | Yes                   | No                     |             887 |          276 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+--------------------------------------+---------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+
|             Clock Signal             |                            Enable Signal                            |                       Set/Reset Signal                       | Slice Load Count | Bel Load Count | Bels / Slice |
+--------------------------------------+---------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+
|  clk_IBUF_BUFG                       |                                                                     |                                                              |                1 |              1 |         1.00 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                     |                                                              |                1 |              1 |         1.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                    | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_1_n_0             |                1 |              1 |         1.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/memory_page_number[23]_i_2_n_0        |                                                              |                1 |              1 |         1.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_2__0_n_0          | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_1__0_n_0   |                2 |              4 |         2.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/next_bit                           | ptop/u_Controller/Uart/i_uart_rx/bit_counter[3]_i_1_n_0      |                1 |              4 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/E[0]                                 |                                                              |                1 |              4 |         4.00 |
|  clk_o_BUFG                          |                                                                     |                                                              |                3 |              5 |         1.67 |
|  clk_o_BUFG                          | ResetBootSystem/counter                                             |                                                              |                2 |              5 |         2.50 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/return_state                          | ResetBootSystem/rst_o_reg_0                                  |                4 |              5 |         1.25 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/data_to_send[6]_i_1_n_0            | ResetBootSystem/rst_o_reg_0                                  |                2 |              7 |         3.50 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/counter                               | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/accumulator[7]_i_1_n_0                | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/uart_tx_en                                   | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/counter_write_reg[2][0]              | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/uart_rx_data[7]_i_1_n_0            | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/E[0]                               | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/recieved_data0                     | ptop/u_Controller/Uart/i_uart_rx/recieved_data[7]_i_1_n_0    |                2 |              8 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                    | ResetBootSystem/SR[0]                                        |                3 |             10 |         3.33 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/cycle_counter0                     | ptop/u_Controller/Uart/i_uart_rx/cycle_counter[9]_i_1__0_n_0 |                4 |             10 |         2.50 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/read_ptr[2]_i_1_n_0                  | ResetBootSystem/rst_o_reg_0                                  |                3 |             11 |         3.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/read_ptr0                            | ResetBootSystem/rst_o_reg_0                                  |                3 |             11 |         3.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/address[31]_i_1_n_0                   |                                                              |                6 |             12 |         2.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/memory_reg_0_7_0_5_i_1_n_0           |                                                              |                2 |             12 |         6.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/memory_reg_0_7_0_5_i_1__0_n_0        |                                                              |                2 |             12 |         6.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/memory_page_number[23]_i_2_n_0        | ptop/u_Controller/Interpreter/memory_page_number[23]_i_1_n_0 |                6 |             23 |         3.83 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_cycles_to_pulse[23]_i_1_n_0    |                                                              |                8 |             24 |         3.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_pages                          | ResetBootSystem/rst_o_reg_0                                  |                4 |             24 |         6.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/accumulator0                          | ResetBootSystem/rst_o_reg_0                                  |                6 |             24 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/timeout                               | ResetBootSystem/rst_o_reg_0                                  |                8 |             24 |         3.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/FSM_onehot_state_reg[49]_2[0]                | ptop/u_Controller/Interpreter/rst_core                       |               10 |             30 |         3.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Mdu/quociente                                             | ptop/u_Controller/Interpreter/rst_core                       |                7 |             32 |         4.57 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[8][0]               |                                                              |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[10][0]              |                                                              |               16 |             32 |         2.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[7]_1[0]             |                                                              |               18 |             32 |         1.78 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[10]_0[0]            |                                                              |               18 |             32 |         1.78 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[10]_2[0]            |                                                              |               21 |             32 |         1.52 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/FSM_onehot_state_reg[43]_2[0]                | ptop/u_Controller/Interpreter/rst_core                       |               15 |             32 |         2.13 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Mdu/DIV_RD                                                |                                                              |                9 |             32 |         3.56 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[10]_4[0]            |                                                              |               18 |             32 |         1.78 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Mdu/dividendo[31]_i_1_n_0                                 |                                                              |                9 |             32 |         3.56 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[9]_3[0]             |                                                              |               15 |             32 |         2.13 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[7]_3[0]             |                                                              |               15 |             32 |         2.13 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[8]_5[0]             |                                                              |               19 |             32 |         1.68 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[7]_5[0]             |                                                              |               14 |             32 |         2.29 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[8]_3[0]             |                                                              |               18 |             32 |         1.78 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[8]_4[0]             |                                                              |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[8]_2[0]             |                                                              |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[7]_2[0]             |                                                              |               22 |             32 |         1.45 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[9]_6[0]             | ptop/u_Controller/Interpreter/rst_core                       |               15 |             32 |         2.13 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[11][0]              |                                                              |               14 |             32 |         2.29 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[8]_0[0]             |                                                              |                9 |             32 |         3.56 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[9]_2[0]             |                                                              |               11 |             32 |         2.91 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[9]_5[0]             |                                                              |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[8]_1[0]             |                                                              |               11 |             32 |         2.91 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[10]_5[0]            |                                                              |               20 |             32 |         1.60 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[9]_1[0]             |                                                              |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[10]_3[0]            |                                                              |               22 |             32 |         1.45 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[11]_0[0]            |                                                              |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/E[0]                                         |                                                              |               10 |             32 |         3.20 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[9]_0[0]             |                                                              |                9 |             32 |         3.56 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[7][0]               |                                                              |               10 |             32 |         3.20 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[9][0]               |                                                              |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[10]_1[0]            |                                                              |               23 |             32 |         1.39 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/FSM_onehot_state_reg[49]_0[1]                | ptop/u_Controller/Interpreter/rst_core                       |               10 |             32 |         3.20 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/communication_write_data[31]_i_1_n_0  |                                                              |                9 |             32 |         3.56 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/write_data[31]_i_1_n_0                |                                                              |               14 |             32 |         2.29 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/end_position[31]_i_1_n_0              | ResetBootSystem/rst_o_reg_0                                  |                7 |             32 |         4.57 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/communication_buffer[31]_i_1_n_0      | ResetBootSystem/rst_o_reg_0                                  |                6 |             32 |         5.33 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/timeout_counter                       | ResetBootSystem/rst_o_reg_0                                  |                7 |             32 |         4.57 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/read_buffer                           | ResetBootSystem/rst_o_reg_0                                  |               15 |             32 |         2.13 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/FSM_sequential_state_write_reg[2][0] | ResetBootSystem/rst_o_reg_0                                  |                5 |             32 |         6.40 |
|  clk_o_BUFG                          | ptop/u_Controller/ClkDivider/pulse_counter[0]_i_1_n_0               | ResetBootSystem/rst_o_reg_0                                  |                8 |             32 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/E[0]                                 | ResetBootSystem/rst_o_reg_0                                  |                7 |             32 |         4.57 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/FSM_onehot_state_reg[49]_0[0]                | ptop/u_Controller/Interpreter/rst_core                       |               10 |             32 |         3.20 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/FSM_onehot_state_reg[49]_3[0]                | ptop/u_Controller/Interpreter/rst_core                       |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/FSM_onehot_state_reg[49]_1[0]                | ptop/u_Controller/Interpreter/rst_core                       |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/FSM_onehot_state_reg[49]_4[0]                | ptop/u_Controller/Interpreter/rst_core                       |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/FSM_onehot_state_reg[49]_5[0]                | ptop/u_Controller/Interpreter/rst_core                       |               13 |             32 |         2.46 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_Controller/Interpreter/E[0]                                  |                                                              |                7 |             32 |         4.57 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[7]_0[0]             |                                                              |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[7]_4[0]             |                                                              |               22 |             32 |         1.45 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Mdu/mul_done                                              | ptop/u_Controller/Interpreter/rst_core                       |                8 |             32 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/instruction_register_reg[9]_4[0]             |                                                              |               15 |             32 |         2.13 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Mdu/quociente_msk[31]_i_1_n_0                             |                                                              |                8 |             33 |         4.12 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Mdu/acumulador[16]_i_1_n_0                                |                                                              |                7 |             34 |         4.86 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_positions[23]_i_1_n_0          |                                                              |               14 |             55 |         3.93 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Mdu/quociente_msk[31]_i_1_n_0                             | ptop/Core/Mdu/quociente_msk[30]_i_1_n_0                      |               16 |             62 |         3.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/Core/Control_Unit/FSM_onehot_state_reg[39]_0[0]                | ptop/u_Controller/Interpreter/rst_core                       |               29 |             69 |         2.38 |
|  clk_o_BUFG                          |                                                                     | ResetBootSystem/rst_o_reg_0                                  |               43 |            117 |         2.72 |
|  clk_o_BUFG                          | ptop/Core/Control_Unit/FSM_onehot_state_reg[36]_0                   |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/Core/Control_Unit/FSM_onehot_state_reg[36]_6                   |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/Core/Control_Unit/FSM_onehot_state_reg[36]_3                   |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/Core/Control_Unit/FSM_onehot_state_reg[36]_1                   |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/Core/Control_Unit/FSM_onehot_state_reg[36]_2                   |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/Core/Control_Unit/FSM_onehot_state_reg[36]_5                   |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/Core/Control_Unit/FSM_onehot_state_reg[36]_4                   |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/Core/Control_Unit/FSM_onehot_state_reg[36]_7                   |                                                              |               32 |            128 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                     | ptop/u_Controller/Interpreter/rst_core                       |               75 |            246 |         3.28 |
+--------------------------------------+---------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+


