Started by timer [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/lib/jenkins/workspace/Risco 5 [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -Rf Risco-5/ build/ [Pipeline] sh + git clone https://github.com/JN513/Risco-5 Cloning into 'Risco-5'... [Pipeline] sh + cd Risco-5 [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (IVerilog) [Pipeline] sh + mkdir -p build [Pipeline] sh + cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex [Pipeline] sh + /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb Risco-5/src/core/alu.v Risco-5/src/core/alu_control.v Risco-5/src/core/control_unit.v Risco-5/src/core/core.v Risco-5/src/core/immediate_generator.v Risco-5/src/core/mux.v Risco-5/src/core/pc.v Risco-5/src/core/registers.v Risco-5/src/peripheral/bus.v Risco-5/src/peripheral/gpio.v Risco-5/src/peripheral/gpios.v Risco-5/src/peripheral/leds.v Risco-5/src/peripheral/memory.v Risco-5/src/peripheral/soc.v Risco-5/src/peripheral/uart.v Risco-5/src/peripheral/uart_rx.v Risco-5/src/peripheral/uart_tx.v Risco-5/tests/soc_test.v [Pipeline] sh + /eda/oss-cad-suite/bin/vvp build/soc_test.o ERROR: Risco-5/src/peripheral/memory.v:27: $readmemh: Unable to open software/memory/generic.hex for reading. VCD info: dumpfile build/soc.vcd opened for output. Risco-5/tests/soc_test.v:32: $finish called at 566 (1s) [Pipeline] sh + rm -f Risco-5/software/memory/generic.hex [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Síntese) [Pipeline] parallel [Pipeline] { (Branch: OSS-Cad-Suite) [Pipeline] { (Branch: Gowin) [Pipeline] stage [Pipeline] { (OSS-Cad-Suite) [Pipeline] stage [Pipeline] { (Gowin) [Pipeline] stage [Pipeline] { (Yosys) [Pipeline] sh [Pipeline] sh + rm -rf Risco-5/impl/pnr [Pipeline] sh + /eda/oss-cad-suite/bin/yosys -p read_verilog Risco-5/fpga/ecp5/main.v; read_verilog Risco-5/debug/clk_divider.v; read_verilog Risco-5/debug/reset.v; read_verilog Risco-5/src/core/*.v; read_verilog Risco-5/src/peripheral/*.v; synth_ecp5 -json ./build/out.json -abc9 /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com> | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.36+8 (git sha1 fb4cbfa73, clang 10.0.0-4ubuntu1 -fPIC -Os) -- Running command ` read_verilog Risco-5/fpga/ecp5/main.v; read_verilog Risco-5/debug/clk_divider.v; read_verilog Risco-5/debug/reset.v; read_verilog Risco-5/src/core/*.v; read_verilog Risco-5/src/peripheral/*.v; synth_ecp5 -json ./build/out.json -abc9 ' -- 1. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/main.v Parsing Verilog input from `Risco-5/fpga/ecp5/main.v' to AST representation. Generating RTLIL representation for module `\top'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: Risco-5/debug/clk_divider.v Parsing Verilog input from `Risco-5/debug/clk_divider.v' to AST representation. Generating RTLIL representation for module `\ClkDivider'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: Risco-5/debug/reset.v Parsing Verilog input from `Risco-5/debug/reset.v' to AST representation. Generating RTLIL representation for module `\ResetBootSystem'. Successfully finished Verilog frontend. 4. Executing Verilog-2005 frontend: Risco-5/src/core/alu.v Parsing Verilog input from `Risco-5/src/core/alu.v' to AST representation. Generating RTLIL representation for module `\ALU'. Successfully finished Verilog frontend. 5. Executing Verilog-2005 frontend: Risco-5/src/core/alu_control.v Parsing Verilog input from `Risco-5/src/core/alu_control.v' to AST representation. Generating RTLIL representation for module `\ALU_Control'. Successfully finished Verilog frontend. 6. Executing Verilog-2005 frontend: Risco-5/src/core/control_unit.v Parsing Verilog input from `Risco-5/src/core/control_unit.v' to AST representation. Generating RTLIL representation for module `\Control_Unit'. Successfully finished Verilog frontend. 7. Executing Verilog-2005 frontend: Risco-5/src/core/core.v Parsing Verilog input from `Risco-5/src/core/core.v' to AST representation. Generating RTLIL representation for module `\Core'. Risco-5/src/core/core.v:76: Warning: Identifier `\pc_source' is implicitly declared. Successfully finished Verilog frontend. 8. Executing Verilog-2005 frontend: Risco-5/src/core/immediate_generator.v Parsing Verilog input from `Risco-5/src/core/immediate_generator.v' to AST representation. Generating RTLIL representation for module `\Immediate_Generator'. Successfully finished Verilog frontend. 9. Executing Verilog-2005 frontend: Risco-5/src/core/mux.v Parsing Verilog input from `Risco-5/src/core/mux.v' to AST representation. Generating RTLIL representation for module `\MUX'. Successfully finished Verilog frontend. 10. Executing Verilog-2005 frontend: Risco-5/src/core/pc.v Parsing Verilog input from `Risco-5/src/core/pc.v' to AST representation. Generating RTLIL representation for module `\PC'. Successfully finished Verilog frontend. 11. Executing Verilog-2005 frontend: Risco-5/src/core/registers.v Parsing Verilog input from `Risco-5/src/core/registers.v' to AST representation. Generating RTLIL representation for module `\Registers'. Successfully finished Verilog frontend. 12. Executing Verilog-2005 frontend: Risco-5/src/peripheral/bus.v Parsing Verilog input from `Risco-5/src/peripheral/bus.v' to AST representation. Generating RTLIL representation for module `\BUS'. Successfully finished Verilog frontend. 13. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpio.v Parsing Verilog input from `Risco-5/src/peripheral/gpio.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (Risco-5/src/peripheral/gpio.v:9) Generating RTLIL representation for module `\GPIO'. Successfully finished Verilog frontend. 14. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpios.v Parsing Verilog input from `Risco-5/src/peripheral/gpios.v' to AST representation. Generating RTLIL representation for module `\GPIOS'. Successfully finished Verilog frontend. 15. Executing Verilog-2005 frontend: Risco-5/src/peripheral/leds.v Parsing Verilog input from `Risco-5/src/peripheral/leds.v' to AST representation. Generating RTLIL representation for module `\LEDs'. Successfully finished Verilog frontend. 16. Executing Verilog-2005 frontend: Risco-5/src/peripheral/memory.v Parsing Verilog input from `Risco-5/src/peripheral/memory.v' to AST representation. Generating RTLIL representation for module `\Memory'. Successfully finished Verilog frontend. 17. Executing Verilog-2005 frontend: Risco-5/src/peripheral/soc.v Parsing Verilog input from `Risco-5/src/peripheral/soc.v' to AST representation. Generating RTLIL representation for module `\Risco_5_SOC'. Successfully finished Verilog frontend. 18. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart.v Parsing Verilog input from `Risco-5/src/peripheral/uart.v' to AST representation. Generating RTLIL representation for module `\UART'. Successfully finished Verilog frontend. 19. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_rx.v Parsing Verilog input from `Risco-5/src/peripheral/uart_rx.v' to AST representation. Generating RTLIL representation for module `\uart_tool_rx'. Successfully finished Verilog frontend. 20. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_tx.v Parsing Verilog input from `Risco-5/src/peripheral/uart_tx.v' to AST representation. Generating RTLIL representation for module `\uart_tool_tx'. Successfully finished Verilog frontend. 21. Executing SYNTH_ECP5 pass. 21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\DP16KD'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCUA'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Successfully finished Verilog frontend. 21.3. Executing HIERARCHY pass (managing design hierarchy). 21.3.1. Finding top of design hierarchy.. root of 0 design levels: uart_tool_tx root of 0 design levels: uart_tool_rx root of 1 design levels: UART root of 2 design levels: Risco_5_SOC root of 0 design levels: Memory root of 0 design levels: LEDs root of 1 design levels: GPIOS root of 0 design levels: GPIO root of 0 design levels: BUS root of 0 design levels: Registers root of 0 design levels: PC root of 0 design levels: MUX root of 0 design levels: Immediate_Generator root of 1 design levels: Core root of 0 design levels: Control_Unit root of 0 design levels: ALU_Control root of 0 design levels: ALU root of 0 design levels: ResetBootSystem root of 0 design levels: ClkDivider root of 3 design levels: top Automatically selected top as design top module. 21.3.2. Analyzing design hierarchy.. Top module: \top Used module: \Risco_5_SOC Used module: \GPIOS Used module: \GPIO Used module: \UART Used module: \uart_tool_tx Used module: \uart_tool_rx Used module: \LEDs Used module: \BUS Used module: \Memory Used module: \Core Used module: \Immediate_Generator Used module: \ALU Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: \ResetBootSystem Used module: \ClkDivider Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \MEMORY_SIZE = 4096 Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000 Parameter \GPIO_WIDHT = 6 21.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Risco_5_SOC'. Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \MEMORY_SIZE = 4096 Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000 Parameter \GPIO_WIDHT = 6 Generating RTLIL representation for module `$paramod$3184ad0c07f8e5ef1997e235d9a61459f8c3c9b2\Risco_5_SOC'. Parameter \CYCLES = 20 21.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'. Parameter \CYCLES = 20 Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'. Parameter \COUNTER_BITS = 32 21.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'. Parameter \COUNTER_BITS = 32 Generating RTLIL representation for module `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000'. Parameter \WIDHT = 5 21.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'. Parameter \WIDHT = 5 Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'. Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 9600 21.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Generating RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 21.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \BOOT_ADDRESS = 0 21.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'. Parameter \BOOT_ADDRESS = 0 Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'. Risco-5/src/core/core.v:76: Warning: Identifier `\pc_source' is implicitly declared. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 21.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 21.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'. 21.3.12. Analyzing design hierarchy.. Top module: \top Used module: $paramod$3184ad0c07f8e5ef1997e235d9a61459f8c3c9b2\Risco_5_SOC Used module: \GPIOS Used module: \GPIO Used module: \UART Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx Used module: \LEDs Used module: \BUS Used module: \Memory Used module: \Core Used module: \Immediate_Generator Used module: \ALU Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000 Parameter \WIDHT = 6 21.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'. Parameter \WIDHT = 6 Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110'. Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Found cached RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'. Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000 Parameter \MEMORY_SIZE = 4096 21.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'. Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000 Parameter \MEMORY_SIZE = 4096 Generating RTLIL representation for module `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory'. Parameter \BOOT_ADDRESS = 0 Found cached RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'. 21.3.15. Analyzing design hierarchy.. Top module: \top Used module: $paramod$3184ad0c07f8e5ef1997e235d9a61459f8c3c9b2\Risco_5_SOC Used module: $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110 Used module: \GPIO Used module: $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART Used module: \uart_tool_tx Used module: \uart_tool_rx Used module: \LEDs Used module: \BUS Used module: $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \Immediate_Generator Used module: \ALU Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000 Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Found cached RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Found cached RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'. 21.3.16. Analyzing design hierarchy.. Top module: \top Used module: $paramod$3184ad0c07f8e5ef1997e235d9a61459f8c3c9b2\Risco_5_SOC Used module: $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110 Used module: \GPIO Used module: $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx Used module: \LEDs Used module: \BUS Used module: $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \Immediate_Generator Used module: \ALU Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000 21.3.17. Analyzing design hierarchy.. Top module: \top Used module: $paramod$3184ad0c07f8e5ef1997e235d9a61459f8c3c9b2\Risco_5_SOC Used module: $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110 Used module: \GPIO Used module: $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx Used module: \LEDs Used module: \BUS Used module: $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \Immediate_Generator Used module: \ALU Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000 Removing unused module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Removing unused module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'. Removing unused module `\uart_tool_tx'. Removing unused module `\uart_tool_rx'. Removing unused module `\UART'. Removing unused module `\Risco_5_SOC'. Removing unused module `\Memory'. Removing unused module `\GPIOS'. Removing unused module `\Core'. Removing unused module `\ResetBootSystem'. Removing unused module `\ClkDivider'. Removed 11 unused modules. 21.4. Executing PROC pass (convert processes to netlists). 21.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$426'. Found and cleaned up 1 empty switch in `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:0$708'. Removing empty process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:0$708'. Cleaned up 2 empty switches. 21.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$533 in module TRELLIS_FF. Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$485 in module DPR16X4C. Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$427 in module TRELLIS_DPR16X4. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:197$687 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:186$685 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:171$677 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:160$674 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:148$668 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:133$663 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:116$658 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:97$649 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx. Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:173$636 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:162$634 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:147$626 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx. Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:130$612 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:115$606 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:98$601 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/core.v:137$591 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:31$699 in module $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/leds.v:23$190 in module LEDs. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/gpios.v:29$693 in module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110. Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:22$80 in module Registers. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/pc.v:15$70 in module PC. Removed 1 dead cases from process $proc$Risco-5/src/core/mux.v:10$69 in module MUX. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/mux.v:10$69 in module MUX. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/immediate_generator.v:7$66 in module Immediate_Generator. Marked 1 switch rules as full_case in process $proc$Risco-5/debug/clk_divider.v:54$559 in module $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000. Marked 3 switch rules as full_case in process $proc$Risco-5/debug/clk_divider.v:33$549 in module $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:119$58 in module Control_Unit. Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:76$55 in module Control_Unit. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:68$54 in module Control_Unit. Removed 1 dead cases from process $proc$Risco-5/src/core/alu_control.v:9$50 in module ALU_Control. Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/alu_control.v:9$50 in module ALU_Control. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/alu.v:11$35 in module ALU. Marked 5 switch rules as full_case in process $proc$Risco-5/debug/reset.v:24$536 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Removed a total of 2 dead cases. 21.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 8 redundant assignments. Promoted 108 assignments to connections. 21.4.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$534'. Set init value: \Q = 1'0 Found init rule in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$689'. Set init value: \i = 0 Found init rule in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$642'. Set init value: \i = 0 Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$594'. Set init value: \instruction_register = 0 Set init value: \memory_register = 0 Set init value: \alu_out_register = 0 Set init value: \register_data_1 = 0 Set init value: \register_data_2 = 0 Found init rule in `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:0$575'. Set init value: \uart_tx_en = 1'0 Set init value: \uart_tx_data = 8'00000000 Found init rule in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$193'. Set init value: \data = 33'000000000000000000000000000000000 Found init rule in `\PC.$proc$Risco-5/src/core/pc.v:0$73'. Set init value: \Output = 0 Found init rule in `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:0$564'. Set init value: \clk_o_auto = 1'0 Set init value: \clk_counter = 0 Set init value: \pulse_counter = 0 Found init rule in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$59'. Set init value: \state = 4'0000 Set init value: \is_immediate = 1'0 Set init value: \pc_write_cond = 1'0 Set init value: \pc_write = 1'0 Set init value: \lorD = 1'0 Set init value: \memory_read = 1'0 Set init value: \memory_write = 1'0 Set init value: \memory_to_reg = 1'0 Set init value: \ir_write = 1'0 Set init value: \pc_source = 1'0 Set init value: \aluop = 2'00 Set init value: \alu_src_a = 2'00 Set init value: \alu_src_b = 2'00 Set init value: \reg_write = 1'0 Set init value: \nextstate = 4'0000 Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$542'. Set init value: \reset_o = 1'0 Set init value: \state = 2'01 Set init value: \counter = 6'000000 21.4.5. Executing PROC_ARST pass (detect async resets in processes). 21.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 1 switch. <suppressed ~75 debug messages> 21.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$534'. Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$533'. 1/1: $0\Q[0:0] Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$508'. Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$485'. 1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$484_EN[3:0]$491 2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$484_DATA[3:0]$490 3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$484_ADDR[3:0]$489 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$451'. Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$427'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$425_EN[3:0]$433 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$425_DATA[3:0]$432 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$425_ADDR[3:0]$431 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$426'. Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$689'. Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$687'. 1/2: $0\rxd_reg_0[0:0] 2/2: $0\rxd_reg[0:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$685'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$677'. 1/1: $0\cycle_counter[12:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$674'. 1/1: $0\bit_sample[0:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$668'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$663'. 1/11: $3\i[31:0] 2/11: $0\recieved_data[7:0] [1] 3/11: $0\recieved_data[7:0] [0] 4/11: $0\recieved_data[7:0] [2] 5/11: $0\recieved_data[7:0] [3] 6/11: $0\recieved_data[7:0] [4] 7/11: $0\recieved_data[7:0] [5] 8/11: $0\recieved_data[7:0] [6] 9/11: $0\recieved_data[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$658'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$649'. 1/1: $0\uart_rx_data[7:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$642'. Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$636'. 1/1: $0\txd_reg[0:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$634'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$626'. 1/1: $0\cycle_counter[12:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$612'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$606'. 1/11: $3\i[31:0] 2/11: $0\data_to_send[7:0] [1] 3/11: $0\data_to_send[7:0] [0] 4/11: $0\data_to_send[7:0] [2] 5/11: $0\data_to_send[7:0] [3] 6/11: $0\data_to_send[7:0] [4] 7/11: $0\data_to_send[7:0] [5] 8/11: $0\data_to_send[7:0] [6] 9/11: $0\data_to_send[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$601'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$594'. Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:137$591'. 1/5: $0\alu_out_register[31:0] 2/5: $0\register_data_2[31:0] 3/5: $0\register_data_1[31:0] 4/5: $0\memory_register[31:0] 5/5: $0\instruction_register[31:0] Creating decoders for process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$699'. 1/3: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$706 2/3: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_DATA[31:0]$705 3/3: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_ADDR[31:0]$704 Creating decoders for process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:0$575'. Creating decoders for process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:31$572'. Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$193'. Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$190'. 1/1: $0\data[32:0] Creating decoders for process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$693'. 1/2: $0\gpio_value[5:0] 2/2: $0\gpio_direction[5:0] Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:0$98'. Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:22$80'. 1/9: $2$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$95 2/9: $2$memwr$\registers$Risco-5/src/core/registers.v:26$76_DATA[31:0]$94 3/9: $2$memwr$\registers$Risco-5/src/core/registers.v:26$76_ADDR[4:0]$93 4/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$96 5/9: $1$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$87 6/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$91 7/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$90 8/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$76_DATA[31:0]$89 9/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$76_ADDR[4:0]$88 Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:0$73'. Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:15$70'. 1/1: $1\Output[31:0] Creating decoders for process `\MUX.$proc$Risco-5/src/core/mux.v:10$69'. 1/1: $1\S[31:0] Creating decoders for process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$66'. 1/1: $1\immediate[31:0] Creating decoders for process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:0$564'. Creating decoders for process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:54$559'. 1/1: $0\pulse_counter[31:0] Creating decoders for process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:33$549'. 1/2: $0\clk_counter[31:0] 2/2: $0\clk_o_auto[0:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$59'. Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58'. 1/1: { $1\pc_write[0:0] $1\alu_src_b[1:0] $1\ir_write[0:0] $1\memory_read[0:0] $1\reg_write[0:0] $1\alu_src_a[1:0] $1\aluop[1:0] $1\pc_source[0:0] $1\memory_to_reg[0:0] $1\memory_write[0:0] $1\lorD[0:0] $1\pc_write_cond[0:0] $1\is_immediate[0:0] } Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:76$55'. 1/4: $4\nextstate[3:0] 2/4: $3\nextstate[3:0] 3/4: $2\nextstate[3:0] 4/4: $1\nextstate[3:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:68$54'. 1/1: $0\state[3:0] Creating decoders for process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$50'. 1/4: $4\aluop_out[3:0] 2/4: $3\aluop_out[3:0] 3/4: $2\aluop_out[3:0] 4/4: $1\aluop_out[3:0] Creating decoders for process `\ALU.$proc$Risco-5/src/core/alu.v:11$35'. 1/1: $1\ALU_out_S[31:0] Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$542'. Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$536'. 1/3: $0\counter[5:0] 2/3: $0\state[1:0] 3/3: $0\reset_o[0:0] 21.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\n_fsm_state' from process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$658'. No latch inferred for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\n_fsm_state' from process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$601'. No latch inferred for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:16$74_EN' from process `\Registers.$proc$Risco-5/src/core/registers.v:0$98'. No latch inferred for signal `\MUX.\S' from process `\MUX.$proc$Risco-5/src/core/mux.v:10$69'. No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$66'. No latch inferred for signal `\Control_Unit.\is_immediate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\is_immediate` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58`. No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58`. No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58`. No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58`. No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58`. No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58`. No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58`. No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58`. No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58`. No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58`. No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58`. No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58`. No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58`. No latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:76$55'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:76$55`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:76$55`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:76$55`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:76$55`. Latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$50': $auto$proc_dlatch.cc:427:proc_dlatch$1310 No latch inferred for signal `\ALU.\ALU_out_S' from process `\ALU.$proc$Risco-5/src/core/alu.v:11$35'. 21.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$533'. created $dff cell `$procdff$1333' with positive edge clock. Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$508'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$469_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$508'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$470_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$508'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$471_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$508'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$472_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$508'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$473_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$508'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$474_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$508'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$475_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$508'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$476_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$508'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$477_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$508'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$478_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$508'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$479_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$508'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$480_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$508'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$481_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$508'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$482_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$508'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$483_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$508'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$484_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$485'. created $dff cell `$procdff$1334' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$484_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$485'. created $dff cell `$procdff$1335' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$484_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$485'. created $dff cell `$procdff$1336' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$451'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$409_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$451'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$410_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$451'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$411_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$451'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$412_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$451'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$413_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$451'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$414_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$451'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$415_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$451'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$416_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$451'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$417_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$451'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$418_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$451'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$419_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$451'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$420_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$451'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$421_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$451'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$422_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$451'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$423_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$451'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$424_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$451'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$425_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$427'. created $dff cell `$procdff$1337' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$425_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$427'. created $dff cell `$procdff$1338' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$425_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$427'. created $dff cell `$procdff$1339' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$426'. created direct connection (no actual register cell created). Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\rxd_reg' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$687'. created $dff cell `$procdff$1340' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\rxd_reg_0' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$687'. created $dff cell `$procdff$1341' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\fsm_state' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$685'. created $dff cell `$procdff$1342' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\cycle_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$677'. created $dff cell `$procdff$1343' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\bit_sample' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$674'. created $dff cell `$procdff$1344' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\bit_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$668'. created $dff cell `$procdff$1345' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\i' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$663'. created $dff cell `$procdff$1346' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\recieved_data' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$663'. created $dff cell `$procdff$1347' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\uart_rx_data' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$649'. created $dff cell `$procdff$1348' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\txd_reg' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$636'. created $dff cell `$procdff$1349' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\fsm_state' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$634'. created $dff cell `$procdff$1350' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\cycle_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$626'. created $dff cell `$procdff$1351' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\bit_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$612'. created $dff cell `$procdff$1352' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\i' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$606'. created $dff cell `$procdff$1353' with positive edge clock. Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\data_to_send' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$606'. created $dff cell `$procdff$1354' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:137$591'. created $dff cell `$procdff$1355' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:137$591'. created $dff cell `$procdff$1356' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:137$591'. created $dff cell `$procdff$1357' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:137$591'. created $dff cell `$procdff$1358' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:137$591'. created $dff cell `$procdff$1359' with positive edge clock. Creating register for signal `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_ADDR' using process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$699'. created $dff cell `$procdff$1360' with positive edge clock. Creating register for signal `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_DATA' using process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$699'. created $dff cell `$procdff$1361' with positive edge clock. Creating register for signal `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN' using process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$699'. created $dff cell `$procdff$1362' with positive edge clock. Creating register for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\uart_tx_en' using process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:31$572'. created $dff cell `$procdff$1363' with positive edge clock. Creating register for signal `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.\uart_tx_data' using process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:31$572'. created $dff cell `$procdff$1364' with positive edge clock. Creating register for signal `\LEDs.\data' using process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$190'. created $dff cell `$procdff$1365' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_direction' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$693'. created $dff cell `$procdff$1366' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_value' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$693'. created $dff cell `$procdff$1367' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$80'. created $dff cell `$procdff$1368' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$76_ADDR' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$80'. created $dff cell `$procdff$1369' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$76_DATA' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$80'. created $dff cell `$procdff$1370' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$80'. created $dff cell `$procdff$1371' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$80'. created $dff cell `$procdff$1372' with positive edge clock. Creating register for signal `\PC.\Output' using process `\PC.$proc$Risco-5/src/core/pc.v:15$70'. created $dff cell `$procdff$1373' with positive edge clock. Creating register for signal `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.\pulse_counter' using process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:54$559'. created $dff cell `$procdff$1374' with positive edge clock. Creating register for signal `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.\clk_o_auto' using process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:33$549'. created $dff cell `$procdff$1375' with positive edge clock. Creating register for signal `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.\clk_counter' using process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:33$549'. created $dff cell `$procdff$1376' with positive edge clock. Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:68$54'. created $dff cell `$procdff$1377' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$536'. created $dff cell `$procdff$1378' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$536'. created $dff cell `$procdff$1379' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$536'. created $dff cell `$procdff$1380' with positive edge clock. 21.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 21.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$534'. Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$533'. Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$533'. Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$508'. Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$485'. Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$451'. Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$427'. Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$426'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$689'. Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$687'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$687'. Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$685'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$685'. Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$677'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$677'. Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$674'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$674'. Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$668'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$668'. Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$663'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$663'. Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$658'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$658'. Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$649'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$649'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$642'. Found and cleaned up 5 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$636'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$636'. Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$634'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$634'. Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$626'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$626'. Found and cleaned up 5 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$612'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$612'. Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$606'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$606'. Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$601'. Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$601'. Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$594'. Found and cleaned up 2 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:137$591'. Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:137$591'. Found and cleaned up 1 empty switch in `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$699'. Removing empty process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$699'. Removing empty process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:0$575'. Removing empty process `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.$proc$Risco-5/src/peripheral/uart.v:31$572'. Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:0$193'. Found and cleaned up 2 empty switches in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$190'. Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:23$190'. Found and cleaned up 3 empty switches in `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$693'. Removing empty process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$693'. Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:0$98'. Found and cleaned up 2 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:22$80'. Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:22$80'. Removing empty process `PC.$proc$Risco-5/src/core/pc.v:0$73'. Found and cleaned up 2 empty switches in `\PC.$proc$Risco-5/src/core/pc.v:15$70'. Removing empty process `PC.$proc$Risco-5/src/core/pc.v:15$70'. Found and cleaned up 1 empty switch in `\MUX.$proc$Risco-5/src/core/mux.v:10$69'. Removing empty process `MUX.$proc$Risco-5/src/core/mux.v:10$69'. Found and cleaned up 1 empty switch in `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$66'. Removing empty process `Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$66'. Removing empty process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:0$564'. Found and cleaned up 3 empty switches in `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:54$559'. Removing empty process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:54$559'. Found and cleaned up 4 empty switches in `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:33$549'. Removing empty process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:33$549'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$59'. Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:119$58'. Found and cleaned up 4 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:76$55'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:76$55'. Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:68$54'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:68$54'. Found and cleaned up 4 empty switches in `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$50'. Removing empty process `ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$50'. Found and cleaned up 1 empty switch in `\ALU.$proc$Risco-5/src/core/alu.v:11$35'. Removing empty process `ALU.$proc$Risco-5/src/core/alu.v:11$35'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$542'. Found and cleaned up 5 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$536'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$536'. Cleaned up 76 empty switches. 21.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx. <suppressed ~21 debug messages> Optimizing module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx. <suppressed ~19 debug messages> Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. <suppressed ~2 debug messages> Optimizing module $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory. <suppressed ~2 debug messages> Optimizing module $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART. <suppressed ~1 debug messages> Optimizing module LEDs. <suppressed ~3 debug messages> Optimizing module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110. <suppressed ~4 debug messages> Optimizing module GPIO. <suppressed ~3 debug messages> Optimizing module BUS. Optimizing module Registers. <suppressed ~2 debug messages> Optimizing module PC. <suppressed ~2 debug messages> Optimizing module MUX. <suppressed ~1 debug messages> Optimizing module Immediate_Generator. Optimizing module $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000. <suppressed ~8 debug messages> Optimizing module Control_Unit. <suppressed ~2 debug messages> Optimizing module ALU_Control. <suppressed ~14 debug messages> Optimizing module ALU. <suppressed ~1 debug messages> Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. <suppressed ~7 debug messages> Optimizing module $paramod$3184ad0c07f8e5ef1997e235d9a61459f8c3c9b2\Risco_5_SOC. Optimizing module top. 21.5. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx. Deleting now unused module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx. Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. Deleting now unused module $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory. Deleting now unused module $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART. Deleting now unused module LEDs. Deleting now unused module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110. Deleting now unused module GPIO. Deleting now unused module BUS. Deleting now unused module Registers. Deleting now unused module PC. Deleting now unused module MUX. Deleting now unused module Immediate_Generator. Deleting now unused module $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000. Deleting now unused module Control_Unit. Deleting now unused module ALU_Control. Deleting now unused module ALU. Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Deleting now unused module $paramod$3184ad0c07f8e5ef1997e235d9a61459f8c3c9b2\Risco_5_SOC. <suppressed ~28 debug messages> 21.6. Executing TRIBUF pass. 21.7. Executing DEMINOUT pass (demote inout ports to input or output). 21.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~53 debug messages> 21.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 64 unused cells and 506 unused wires. <suppressed ~89 debug messages> 21.10. Executing CHECK pass (checking for obvious problems). + mkdir -p Risco-5/impl/pnr Checking module top... Warning: Wire top.\SOC.Core.PCSourceMUX.C [31] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [30] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [29] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [28] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [27] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [26] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [25] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [24] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [23] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [22] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [21] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [20] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [19] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [18] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [17] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [16] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [15] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [14] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [13] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [12] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [11] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [10] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [9] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [8] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [7] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [6] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [5] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [4] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [3] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [2] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [1] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [0] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [31] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [30] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [29] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [28] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [27] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [26] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [25] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [24] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [23] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [22] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [21] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [20] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [19] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [18] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [17] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [16] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [15] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [14] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [13] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [12] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [11] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [10] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [9] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [8] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [7] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [6] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [5] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [4] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [3] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [2] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [1] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [0] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [31] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [30] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [29] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [28] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [27] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [26] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [25] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [24] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [23] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [22] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [21] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [20] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [19] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [18] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [17] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [16] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [15] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [14] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [13] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [12] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [11] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [10] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [9] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [8] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [7] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [6] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [5] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [4] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [3] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [2] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [1] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.C [0] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [31] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [30] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [29] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [28] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [27] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [26] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [25] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [24] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [23] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [22] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [21] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [20] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [19] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [18] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [17] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [16] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [15] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [14] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [13] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [12] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [11] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [10] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [9] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [8] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [7] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [6] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [5] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [4] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [3] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [2] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [1] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [0] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [31] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [30] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [29] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [28] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [27] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [26] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [25] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [24] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [23] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [22] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [21] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [20] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [19] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [18] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [17] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [16] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [15] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [14] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [13] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [12] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [11] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [10] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [9] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [8] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [7] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [6] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [5] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [4] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [3] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [2] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [1] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [0] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [31] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [30] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [29] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [28] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [27] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [26] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [25] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [24] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [23] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [22] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [21] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [20] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [19] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [18] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [17] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [16] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [15] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [14] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [13] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [12] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [11] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [10] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [9] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [8] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [7] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [6] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [5] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [4] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [3] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [2] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [1] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [0] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [31] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [30] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [29] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [28] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [27] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [26] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [25] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [24] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [23] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [22] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [21] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [20] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [19] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [18] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [17] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [16] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [15] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [14] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [13] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [12] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [11] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [10] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [9] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [8] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [7] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [6] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [5] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [4] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [3] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [2] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [1] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputAMUX.D [0] is used but has no driver. Found and reported 224 problems. 21.11. Executing OPT pass (performing simple optimizations). 21.11.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~9 debug messages> 21.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~255 debug messages> Removed a total of 85 cells. 21.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1153. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1178. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1198. dead port 1/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1094. dead port 2/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1094. dead port 1/5 on $pmux $flatten\SOC.\Core.\MemoryDataMUX.$procmux$1094. dead port 2/5 on $pmux $flatten\SOC.\Core.\MemoryDataMUX.$procmux$1094. dead port 1/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1094. dead port 2/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1094. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1054. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1060. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1066. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1072. Removed 13 multiplexer ports. <suppressed ~68 debug messages> 21.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1232: { $flatten\SOC.\Core.\ALU_Control.$procmux$1239_CMP $auto$opt_reduce.cc:134:opt_pmux$1398 $flatten\SOC.\Core.\ALU_Control.$procmux$1236_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1235_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1234_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1233_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1246: { $auto$opt_reduce.cc:134:opt_pmux$1402 $auto$opt_reduce.cc:134:opt_pmux$1400 $flatten\SOC.\Core.\ALU_Control.$procmux$1239_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1255: { $flatten\SOC.\Core.\ALU_Control.$procmux$1257_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1256_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1169: { $auto$opt_reduce.cc:134:opt_pmux$1404 $flatten\SOC.\Core.\Control_Unit.$procmux$1175_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1174_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1173_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1172_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1171_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1170_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1201: { $flatten\SOC.\Core.\Control_Unit.$procmux$1199_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1211_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1179_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1154_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1208_CMP $auto$opt_reduce.cc:134:opt_pmux$1406 } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1100: { $flatten\SOC.\Core.\Control_Unit.$procmux$1172_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1173_CMP $auto$opt_reduce.cc:134:opt_pmux$1410 $flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:99$57_Y $auto$opt_reduce.cc:134:opt_pmux$1408 $flatten\SOC.\Core.\Control_Unit.$procmux$1176_CMP } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1051: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1069: Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1075: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$75_EN[31:0]$81 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1021: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_EN[31:0]$702 [0] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1078: Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$96, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1069_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$77_EN[31:0]$85 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1081: Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$95, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1051_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$76_EN[31:0]$84 [0] } Optimizing cells in module \top. Performed a total of 14 changes. 21.11.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 21.11.6. Executing OPT_DFF pass (perform DFF optimizations). 21.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 110 unused wires. <suppressed ~8 debug messages> 21.11.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 21.11.9. Rerunning OPT passes. (Maybe there is more to do..) 21.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~68 debug messages> 21.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 21.11.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 21.11.13. Executing OPT_DFF pass (perform DFF optimizations). 21.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 21.11.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 21.11.16. Finished OPT passes. (There is nothing left to do.) 21.12. Executing FSM pass (extract and optimize FSM). 21.12.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking top.ResetBootSystem.state as FSM state register: Register has an initialization value. Circuit seems to be self-resetting. Not marking top.SOC.Core.Control_Unit.state as FSM state register: Users of register don't seem to benefit from recoding. Register has an initialization value. Found FSM state register top.SOC.Uart.i_uart_rx.fsm_state. Found FSM state register top.SOC.Uart.i_uart_tx.fsm_state. 21.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). Extracting FSM `\SOC.Uart.i_uart_rx.fsm_state' from module `\top'. found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_rx.$procdff$1342 root of input selection tree: $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: \ResetBootSystem.reset_o found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$651_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$666_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$679_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$665_Y found state code: 3'000 found ctrl input: \SOC.Uart.i_uart_rx.next_bit found state code: 3'011 found ctrl input: \SOC.Uart.i_uart_rx.payload_done found state code: 3'010 found state code: 3'001 found ctrl input: \SOC.Uart.i_uart_rx.rxd_reg found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$679_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$670_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$666_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$665_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$651_Y ctrl inputs: { \SOC.Uart.i_uart_rx.rxd_reg \SOC.Uart.i_uart_rx.next_bit \SOC.Uart.i_uart_rx.payload_done \ResetBootSystem.reset_o } ctrl outputs: { $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$651_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$665_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$666_Y $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$670_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$679_Y $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] } transition: 3'000 4'0--0 -> 3'001 8'01010001 transition: 3'000 4'1--0 -> 3'000 8'01010000 transition: 3'000 4'---1 -> 3'000 8'01010000 transition: 3'010 4'--00 -> 3'010 8'00100010 transition: 3'010 4'--10 -> 3'011 8'00100011 transition: 3'010 4'---1 -> 3'000 8'00100000 transition: 3'001 4'-0-0 -> 3'001 8'00011001 transition: 3'001 4'-1-0 -> 3'010 8'00011010 transition: 3'001 4'---1 -> 3'000 8'00011000 transition: 3'011 4'-0-0 -> 3'011 8'10010011 transition: 3'011 4'-1-0 -> 3'000 8'10010000 transition: 3'011 4'---1 -> 3'000 8'10010000 Extracting FSM `\SOC.Uart.i_uart_tx.fsm_state' from module `\top'. found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_tx.$procdff$1350 root of input selection tree: $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: \ResetBootSystem.reset_o found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$620_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$610_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$628_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$608_Y found state code: 3'000 found ctrl input: \SOC.Uart.i_uart_tx.stop_done found state code: 3'011 found ctrl input: \SOC.Uart.i_uart_tx.payload_done found state code: 3'010 found ctrl input: \SOC.Uart.i_uart_tx.next_bit found state code: 3'001 found ctrl input: \SOC.Uart.uart_tx_en found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$628_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$620_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$615_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$614_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$610_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$608_Y ctrl inputs: { \SOC.Uart.i_uart_tx.next_bit \SOC.Uart.i_uart_tx.payload_done \SOC.Uart.i_uart_tx.stop_done \SOC.Uart.uart_tx_en \ResetBootSystem.reset_o } ctrl outputs: { $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$608_Y $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$610_Y $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$614_Y $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$615_Y $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$620_Y $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$628_Y $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] } transition: 3'000 5'---00 -> 3'000 9'101100000 transition: 3'000 5'---10 -> 3'001 9'101100001 transition: 3'000 5'----1 -> 3'000 9'101100000 transition: 3'010 5'-0--0 -> 3'010 9'010100010 transition: 3'010 5'-1--0 -> 3'011 9'010100011 transition: 3'010 5'----1 -> 3'000 9'010100000 transition: 3'001 5'0---0 -> 3'001 9'001101001 transition: 3'001 5'1---0 -> 3'010 9'001101010 transition: 3'001 5'----1 -> 3'000 9'001101000 transition: 3'011 5'--0-0 -> 3'011 9'001010011 transition: 3'011 5'--1-0 -> 3'000 9'001010000 transition: 3'011 5'----1 -> 3'000 9'001010000 21.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$1418' from module `\top'. Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$1411' from module `\top'. 21.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 20 unused cells and 20 unused wires. <suppressed ~22 debug messages> 21.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$1411' from module `\top'. Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2]. Optimizing FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$1418' from module `\top'. Removing unused output signal $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] [2]. 21.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$1411' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ---1 010 -> --1- 001 -> -1-- 011 -> 1--- Recoding FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$1418' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ---1 010 -> --1- 001 -> -1-- 011 -> 1--- 21.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$1411' from module `top': ------------------------------------- Information on FSM $fsm$\SOC.Uart.i_uart_rx.fsm_state$1411 (\SOC.Uart.i_uart_rx.fsm_state): Number of input signals: 4 Number of output signals: 5 Number of state bits: 4 Input signals: 0: \ResetBootSystem.reset_o 1: \SOC.Uart.i_uart_rx.payload_done 2: \SOC.Uart.i_uart_rx.next_bit 3: \SOC.Uart.i_uart_rx.rxd_reg Output signals: 0: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$679_Y 1: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$670_Y 2: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$666_Y 3: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$665_Y 4: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$651_Y State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 4'1--0 -> 0 5'01010 1: 0 4'---1 -> 0 5'01010 2: 0 4'0--0 -> 2 5'01010 3: 1 4'---1 -> 0 5'00100 4: 1 4'--00 -> 1 5'00100 5: 1 4'--10 -> 3 5'00100 6: 2 4'---1 -> 0 5'00011 7: 2 4'-1-0 -> 1 5'00011 8: 2 4'-0-0 -> 2 5'00011 9: 3 4'-1-0 -> 0 5'10010 10: 3 4'---1 -> 0 5'10010 11: 3 4'-0-0 -> 3 5'10010 ------------------------------------- FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$1418' from module `top': ------------------------------------- Information on FSM $fsm$\SOC.Uart.i_uart_tx.fsm_state$1418 (\SOC.Uart.i_uart_tx.fsm_state): Number of input signals: 5 Number of output signals: 6 Number of state bits: 4 Input signals: 0: \ResetBootSystem.reset_o 1: \SOC.Uart.uart_tx_en 2: \SOC.Uart.i_uart_tx.stop_done 3: \SOC.Uart.i_uart_tx.payload_done 4: \SOC.Uart.i_uart_tx.next_bit Output signals: 0: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$628_Y 1: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$620_Y 2: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$615_Y 3: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$614_Y 4: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$610_Y 5: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$608_Y State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 5'---00 -> 0 6'101100 1: 0 5'----1 -> 0 6'101100 2: 0 5'---10 -> 2 6'101100 3: 1 5'----1 -> 0 6'010100 4: 1 5'-0--0 -> 1 6'010100 5: 1 5'-1--0 -> 3 6'010100 6: 2 5'----1 -> 0 6'001101 7: 2 5'1---0 -> 1 6'001101 8: 2 5'0---0 -> 2 6'001101 9: 3 5'--1-0 -> 0 6'001010 10: 3 5'----1 -> 0 6'001010 11: 3 5'--0-0 -> 3 6'001010 ------------------------------------- 21.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Mapping FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$1411' from module `\top'. Mapping FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$1418' from module `\top'. 21.13. Executing OPT pass (performing simple optimizations). 21.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~10 debug messages> 21.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 21.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~66 debug messages> 21.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 21.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 21.13.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$1354 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$983_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$977_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$968_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$959_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$950_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$941_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$923_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$932_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$1513 ($sdff) from module top (D = \SOC.Uart.uart_tx_data [7], Q = \SOC.Uart.i_uart_tx.data_to_send [7]). Adding EN signal on $auto$ff.cc:266:slice$1513 ($sdff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$977_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$968_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$959_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$950_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$941_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$923_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$932_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send [6:0]). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$1352 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$899_Y, Q = \SOC.Uart.i_uart_tx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$1518 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$899_Y, Q = \SOC.Uart.i_uart_tx.bit_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$1351 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$888_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter, rval = 13'0000000000000). Adding EN signal on $auto$ff.cc:266:slice$1524 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$633_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$1349 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$877_Y, Q = \SOC.Uart.i_uart_tx.txd_reg, rval = 1'1). Adding EN signal on $auto$ff.cc:266:slice$1528 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$877_Y, Q = \SOC.Uart.i_uart_tx.txd_reg). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$1348 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$866_Y, Q = \SOC.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$1534 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.recieved_data, Q = \SOC.Uart.i_uart_rx.uart_rx_data). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$1347 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_rx.$procmux$843_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$834_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$825_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$816_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$807_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$798_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$780_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$789_Y }, Q = \SOC.Uart.i_uart_rx.recieved_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$1536 ($sdff) from module top (D = { \SOC.Uart.i_uart_rx.bit_sample \SOC.Uart.i_uart_rx.recieved_data [7:1] }, Q = \SOC.Uart.i_uart_rx.recieved_data). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$1345 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$762_Y, Q = \SOC.Uart.i_uart_rx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$1540 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$673_Y, Q = \SOC.Uart.i_uart_rx.bit_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$1344 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$757_Y, Q = \SOC.Uart.i_uart_rx.bit_sample, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$1544 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg, Q = \SOC.Uart.i_uart_rx.bit_sample). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$1343 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$749_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter, rval = 13'0000000000000). Adding EN signal on $auto$ff.cc:266:slice$1546 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$684_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$1341 ($dff) from module top (D = \rx, Q = \SOC.Uart.i_uart_rx.rxd_reg_0, rval = 1'1). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$1340 ($dff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg_0, Q = \SOC.Uart.i_uart_rx.rxd_reg, rval = 1'1). Adding SRST signal on $flatten\SOC.\Uart.$procdff$1364 ($dff) from module top (D = \SOC.Bus.write_data [7:0], Q = \SOC.Uart.uart_tx_data, rval = 8'00000000). Adding SRST signal on $flatten\SOC.\Uart.$procdff$1363 ($dff) from module top (D = \SOC.Bus.write, Q = \SOC.Uart.uart_tx_en, rval = 1'0). Adding SRST signal on $flatten\SOC.\Leds.$procdff$1365 ($dff) from module top (D = $flatten\SOC.\Leds.$procmux$1029_Y, Q = \SOC.Leds.data, rval = 33'000000000000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$1554 ($sdff) from module top (D = { 1'0 \SOC.Leds.write_data }, Q = \SOC.Leds.data). Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$1367 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1037_Y, Q = \SOC.GPIOS.gpio_value, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$1556 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_value). Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$1366 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1045_Y, Q = \SOC.GPIOS.gpio_direction, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$1560 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_direction). Adding SRST signal on $flatten\SOC.\Core.\Pc.$procdff$1373 ($dff) from module top (D = $flatten\SOC.\Core.\Pc.$procmux$1089_Y, Q = \SOC.Core.Pc.Output, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$1566 ($sdff) from module top (D = \SOC.Core.Pc.Input, Q = \SOC.Core.Pc.Output). Adding SRST signal on $flatten\SOC.\Core.\Control_Unit.$procdff$1377 ($dff) from module top (D = \SOC.Core.Control_Unit.nextstate, Q = \SOC.Core.Control_Unit.state, rval = 4'0000). Adding SRST signal on $flatten\SOC.\Core.$procdff$1359 ($dff) from module top (D = \SOC.Bus.write_data, Q = \SOC.Core.register_data_2, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$1358 ($dff) from module top (D = \SOC.Core.register_data_1_out, Q = \SOC.Core.register_data_1, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$1357 ($dff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.alu_out_register, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$1356 ($dff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.memory_register, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$1355 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1015_Y, Q = \SOC.Core.instruction_register, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$1573 ($sdff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.instruction_register). Adding EN signal on $flatten\ResetBootSystem.$procdff$1380 ($dff) from module top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter). Adding EN signal on $flatten\ResetBootSystem.$procdff$1379 ($dff) from module top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state). Adding EN signal on $flatten\ResetBootSystem.$procdff$1378 ($dff) from module top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o). Adding SRST signal on $flatten\ClkDivider.$procdff$1376 ($dff) from module top (D = $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:40$552_Y, Q = \ClkDivider.clk_counter, rval = 0). Adding SRST signal on $flatten\ClkDivider.$procdff$1375 ($dff) from module top (D = $flatten\ClkDivider.$procmux$1132_Y, Q = \ClkDivider.clk_o_auto, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$1601 ($sdff) from module top (D = $flatten\ClkDivider.$procmux$1132_Y, Q = \ClkDivider.clk_o_auto). Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$1555 ($sdffe) from module top. 21.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 75 unused cells and 83 unused wires. <suppressed ~82 debug messages> 21.13.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~6 debug messages> 21.13.9. Rerunning OPT passes. (Maybe there is more to do..) 21.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~40 debug messages> 21.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$1542: { \SOC.Uart.i_uart_rx.fsm_state [3:2] \SOC.Uart.i_uart_rx.fsm_state [0] \ResetBootSystem.reset_o } Optimizing cells in module \top. Performed a total of 1 changes. 21.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 21.13.13. Executing OPT_DFF pass (perform DFF optimizations). 21.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 1 unused wires. <suppressed ~2 debug messages> 21.13.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 21.13.16. Rerunning OPT passes. (Maybe there is more to do..) 21.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~40 debug messages> 21.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 21.13.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 21.13.20. Executing OPT_DFF pass (perform DFF optimizations). 21.13.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 21.13.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 21.13.23. Finished OPT passes. (There is nothing left to do.) 21.14. Executing WREDUCE pass (reducing word size of cells). Removed top 28 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\Control_Unit.$auto$mem.cc:328:emit$712 ($flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$1382 (SOC.Core.RegisterBank.registers). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$1384 (SOC.Core.RegisterBank.registers). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$meminit$\registers$Risco-5/src/core/registers.v:16$97 (SOC.Core.RegisterBank.registers). Removed top 22 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$1381 (SOC.Memory.memory). Removed top 22 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$meminit$\memory$Risco-5/src/peripheral/memory.v:0$707 (SOC.Memory.memory). Removed top 22 address bits (of 32) from memory read port top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:17$697 (SOC.Memory.memory). Removed top 9 bits (of 32) from port B of cell top.$flatten\ClkDivider.$ge$Risco-5/debug/clk_divider.v:48$558 ($ge). Removed top 10 bits (of 32) from port B of cell top.$flatten\ClkDivider.$eq$Risco-5/debug/clk_divider.v:41$554 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\ResetBootSystem.$procmux$1284_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$540 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$539 ($add). Removed top 26 bits (of 32) from port Y of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$539 ($add). Removed top 27 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$538 ($lt). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$1586 ($ne). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$1581 ($ne). Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\GPIOS.$ternary$Risco-5/src/peripheral/gpios.v:20$692 ($mux). Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Uart.$ternary$Risco-5/src/peripheral/uart.v:24$571 ($mux). Removed top 2 bits (of 13) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:111$654 ($eq). Removed top 1 bits (of 13) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:109$652 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:135$618 ($eq). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$605 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$604 ($mux). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$603 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$602 ($mux). Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:94$598 ($eq). Removed top 1 bits (of 13) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:92$596 ($eq). Removed top 1 bits (of 33) from mux cell top.$flatten\SOC.\Leds.$ternary$Risco-5/src/peripheral/leds.v:21$189 ($mux). Removed top 2 bits (of 8) from port Y of cell top.$flatten\SOC.\Leds.$not$Risco-5/src/peripheral/leds.v:31$192 ($not). Removed top 2 bits (of 8) from port A of cell top.$flatten\SOC.\Leds.$not$Risco-5/src/peripheral/leds.v:31$192 ($not). Removed top 20 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$101 ($le)[Pipeline] } [Pipeline] // stage [Pipeline] } . Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$104 ($ge). Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$105 ($le). Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$108 ($ge). Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$109 ($le). Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$112 ($ge). Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$113 ($le). Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$173 ($mux). Removed top 22 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1027 ($mux). Removed top 29 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$67 ($sub). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1097_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1097_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1208_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1207_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1179_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1176_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1175_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1174_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1171_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1170_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1154_CMP0 ($eq). Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1151 ($mux). Removed top 5 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:99$57 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1257_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1239_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1238_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1237_CMP0 ($eq). Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1225 ($mux). Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$eq$Risco-5/src/core/alu_control.v:35$52 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$1270_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$1269_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$1268_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$1267_CMP0 ($eq). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$49 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:22$41 ($mux). Removed top 29 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$68 ($sub). Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$100 ($ge). Removed top 20 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:80$151 ($mux). Removed top 26 bits (of 32) from wire top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$539_Y. Removed top 24 bits (of 32) from wire top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$173_Y. Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\ALU_Control.$4\aluop_out[3:0]. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:32$47_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:22$41_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$49_Y. Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\Control_Unit.$4\nextstate[3:0]. Removed top 22 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$695_ADDR[31:0]$700. Removed top 2 bits (of 32) from wire top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:17$697_DATA. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$602_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$603_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$604_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$605_Y. Removed top 2 bits (of 8) from wire top.leds. 21.15. Executing PEEPOPT pass (run peephole optimizers). 21.16. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 15 unused wires. <suppressed ~1 debug messages> 21.17. Executing SHARE pass (SAT-based resource sharing). Found 3 cells in module top that may be considered for resource sharing. Analyzing resource sharing options for $flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:17$697 ($memrd): Found 1 activation_patterns using ctrl signal { $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:53$102_Y \SOC.Bus.slave_0_read }. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shr$Risco-5/src/core/alu.v:28$45 ($shr): Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$1264_CMP. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shl$Risco-5/src/core/alu.v:26$44 ($shl): Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$1265_CMP. No candidates found. 21.18. Executing TECHMAP pass (map to technology primitives). 21.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 21.18.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~322 debug messages> 21.19. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 21.20. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 21.21. Executing TECHMAP pass (map to technology primitives). 21.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 21.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation. Generating RTLIL representation for module `\$__MUL18X18'. Successfully finished Verilog frontend. 21.21.3. Continuing TECHMAP pass. No more expansions possible. <suppressed ~5 debug messages> 21.22. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top: creating $macc model for $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:45$556 ($add). creating $macc model for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$539 ($add). creating $macc model for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:18$38 ($add). creating $macc model for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$39 ($sub). creating $macc model for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$67 ($sub). creating $macc model for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$68 ($sub). creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$673 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$684 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$622 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$633 ($add). creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$633. creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$622. creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$684. creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$673. creating $alu model for $macc $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$68. creating $alu model for $macc $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$67. creating $alu model for $macc $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$39. creating $alu model for $macc $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:18$38. creating $alu model for $macc $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$539. creating $alu model for $macc $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:45$556. creating $alu model for $flatten\ClkDivider.$ge$Risco-5/debug/clk_divider.v:48$558 ($ge): new $alu creating $alu model for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$538 ($lt): new $alu creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$100 ($ge): new $alu creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$104 ($ge): new $alu creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$108 ($ge): new $alu creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$112 ($ge): new $alu creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$101 ($le): new $alu creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$105 ($le): new $alu creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$109 ($le): new $alu creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$113 ($le): new $alu creating $alu model for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:34$48 ($ge): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$39. creating $alu model for $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:22$40 ($lt): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$39. creating $alu model for $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$540 ($eq): merged with $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$538. creating $alu model for $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:32$47 ($eq): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$39. creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$113: $auto$alumacc.cc:485:replace_alu$1631 creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$109: $auto$alumacc.cc:485:replace_alu$1644 creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$105: $auto$alumacc.cc:485:replace_alu$1657 creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$101: $auto$alumacc.cc:485:replace_alu$1670 creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$112: $auto$alumacc.cc:485:replace_alu$1683 creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$108: $auto$alumacc.cc:485:replace_alu$1692 creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$104: $auto$alumacc.cc:485:replace_alu$1701 creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$100: $auto$alumacc.cc:485:replace_alu$1710 creating $alu cell for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$538, $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$540: $auto$alumacc.cc:485:replace_alu$1719 creating $alu cell for $flatten\ClkDivider.$ge$Risco-5/debug/clk_divider.v:48$558: $auto$alumacc.cc:485:replace_alu$1730 creating $alu cell for $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:45$556: $auto$alumacc.cc:485:replace_alu$1739 creating $alu cell for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$539: $auto$alumacc.cc:485:replace_alu$1742 creating $alu cell for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:18$38: $auto$alumacc.cc:485:replace_alu$1745 creating $alu cell for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$39, $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:34$48, $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:22$40, $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:32$47: $auto$alumacc.cc:485:replace_alu$1748 creating $alu cell for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$67: $auto$alumacc.cc:485:replace_alu$1761 creating $alu cell for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$68: $auto$alumacc.cc:485:replace_alu$1764 creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$673: $auto$alumacc.cc:485:replace_alu$1767 creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$684: $auto$alumacc.cc:485:replace_alu$1770 creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$622: $auto$alumacc.cc:485:replace_alu$1773 creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$633: $auto$alumacc.cc:485:replace_alu$1776 created 20 $alu and 0 $macc cells. 21.23. Executing OPT pass (performing simple optimizations). 21.23.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~3 debug messages> 21.23.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 21.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~40 debug messages> 21.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$1600: { $auto$rtlil.cc:2461:Not$1734 $auto$rtlil.cc:2464:ReduceAnd$1736 \reset } Optimizing cells in module \top. Performed a total of 1 changes. 21.23.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 21.23.6. Executing OPT_DFF pass (perform DFF optimizations). 21.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 15 unused wires. <suppressed ~2 debug messages> 21.23.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 21.23.9. Rerunning OPT passes. (Maybe there is more to do..) 21.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~40 debug messages> 21.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 21.23.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 21.23.13. Executing OPT_DFF pass (perform DFF optimizations). 21.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 21.23.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 21.23.16. Finished OPT passes. (There is nothing left to do.) 21.24. Executing MEMORY pass. 21.24.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 21.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 21.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing top.SOC.Core.RegisterBank.registers write port 0. Analyzing top.SOC.Core.RegisterBank.registers write port 1. Analyzing top.SOC.Core.RegisterBank.registers write port 2. Analyzing top.SOC.Memory.memory write port 0. 21.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 21.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710'[0] in module `\top': no output FF found. Checking read port `\SOC.Core.RegisterBank.registers'[0] in module `\top': no output FF found. Checking read port `\SOC.Core.RegisterBank.registers'[1] in module `\top': merging output FF to cell. Write port 0: don't care on collision. Write port 1: non-transparent. Write port 2: non-transparent. Checking read port `\SOC.Memory.memory'[0] in module `\top': no output FF found. Checking read port address `$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710'[0] in module `\top': address FF has fully-defined init value, not supported. Checking read port address `\SOC.Core.RegisterBank.registers'[0] in module `\top': address FF has fully-defined init value, not supported. Checking read port address `\SOC.Memory.memory'[0] in module `\top': no address FF found. 21.24.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 34 unused wires. <suppressed ~4 debug messages> 21.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating read ports of memory top.SOC.Core.RegisterBank.registers by address: Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address: Merging ports 0, 2 (address 5'00000). Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address: Consolidating write ports of memory top.SOC.Core.RegisterBank.registers using sat-based resource sharing: Checking group clocked with posedge \ClkDivider.clk_o_auto, width 32: ports 0, 1. Common input cone for all EN signals: 6 cells. Size of unconstrained SAT problem: 40 variables, 98 clauses Merging port 1 into port 0. 21.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 21.24.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 21.24.10. Executing MEMORY_COLLECT pass (generating $mem cells). 21.25. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 21.26. Executing MEMORY_LIBMAP pass (mapping memories to cells). using FF mapping for memory top.$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710 mapping memory top.SOC.Core.RegisterBank.registers via $__TRELLIS_DPR16X4_ Extracted data FF from read port 1 of top.SOC.Core.RegisterBank.registers: $\SOC.Core.RegisterBank.registers$rdreg[1] mapping memory top.SOC.Memory.memory via $__TRELLIS_DPR16X4_ <suppressed ~162 debug messages> 21.27. Executing TECHMAP pass (map to technology primitives). 21.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation. Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 21.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ECP5_DP16KD_'. Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'. Successfully finished Verilog frontend. 21.27.3. Continuing TECHMAP pass. Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$514fc941ac1ae997c717a8e6a1180ed8e0cf8fa9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$5276274b86ff102139fbc8ae2dfc335d77b58a6a\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$48358c22c7a8e5b48ddefb8e14a8bb1f81de841f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$731f2d82778baee6f78f5f3e0670a3ade61ac0d6\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$b089c18cc881634130ec6d4716ef25d78c9d48c9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$0eb199c7b2cea9c358f23ffe94c4548bdd802747\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$c75b2ca41d3ff8a2b5ad26d6a6ec321bb6e56448\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$315d0c5245324146665fc1ab307bed98cfcb6adf\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$fb6ed8f936d3525780a052d218072c625795bc14\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. No more expansions possible. <suppressed ~679 debug messages> 21.28. Executing OPT pass (performing simple optimizations). 21.28.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~75 debug messages> 21.28.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~15 debug messages> Removed a total of 5 cells. 21.28.3. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$1575 ($dffe) from module top (D = $flatten\ResetBootSystem.$procmux$1281_Y, Q = \ResetBootSystem.counter, rval = 6'000000). 21.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 24 unused cells and 3869 unused wires. <suppressed ~25 debug messages> 21.28.5. Rerunning OPT passes. (Removed registers in this run.) 21.28.6. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~2 debug messages> 21.28.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 21.28.8. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$3173 ($sdffce) from module top (D = $auto$wreduce.cc:461:run$1606 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000). 21.28.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 3 unused wires. <suppressed ~3 debug messages> 21.28.10. Rerunning OPT passes. (Removed registers in this run.) 21.28.11. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 21.28.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 21.28.13. Executing OPT_DFF pass (perform DFF optimizations). 21.28.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 21.28.15. Finished fast OPT passes. 21.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). Mapping memory $flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710 in module \top: created 16 $dff cells and 0 static cells of width 16. read interface: 0 $dff and 15 $mux cells. write interface: 0 write mux blocks. 21.30. Executing OPT pass (performing simple optimizations). 21.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 21.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 21.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell $auto$memory_share.cc:453:consolidate_wr_using_sat$1829: $auto$rtlil.cc:2465:ReduceOr$1823 -> 1'1 Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~36 debug messages> 21.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][3][6]$3218: Old ports: A=16'0100000000000000, B=16'0100001000000000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][3]$a$3198 New ports: A=1'0, B=1'1, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][3]$a$3198 [9] New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][3]$a$3198 [15:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][3]$a$3198 [8:0] } = 15'010000000000000 Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][3][5]$3215: Old ports: A=16'0000000101100010, B=16'1010000000100001, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$b$3196 New ports: A=2'10, B=2'01, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$b$3196 [1:0] New connections: $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$b$3196 [15:2] = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$b$3196 [0] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$b$3196 [0] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$b$3196 [1] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$b$3196 [1] 4'1000 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][3][4]$3212: Old ports: A=16'0100000110000001, B=16'1010000000100000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$a$3195 New ports: A=2'01, B=2'10, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$a$3195 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$a$3195 [0] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$a$3195 [15:6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$a$3195 [4:1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$a$3195 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$a$3195 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$a$3195 [5] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$a$3195 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$a$3195 [0] 5'00000 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][3][3]$3209: Old ports: A=16'0000000110000000, B=16'0000010000000000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][1]$b$3193 New ports: A=2'01, B=2'10, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][1]$b$3193 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][1]$b$3193 [7] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][1]$b$3193 [15:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][1]$b$3193 [9:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][1]$b$3193 [6:0] } = { 6'000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][1]$b$3193 [7] 7'0000000 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][3][2]$3206: Old ports: A=16'0000010000010000, B=16'0000000000001100, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][1]$a$3192 New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][1]$a$3192 [4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][1]$a$3192 [2] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][1]$a$3192 [15:5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][1]$a$3192 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][1]$a$3192 [1:0] } = { 5'00000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][1]$a$3192 [4] 5'00000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][1]$a$3192 [2] 2'00 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][3][1]$3203: Old ports: A=16'0100000100000000, B=16'0000100000000100, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$b$3190 New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$b$3190 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$b$3190 [2] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$b$3190 [15:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$b$3190 [7:3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$b$3190 [1:0] } = { 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$b$3190 [8] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$b$3190 [2] 9'000000000 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][3][0]$3200: Old ports: A=16'1011100000000000, B=16'0100000000000000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$a$3189 New ports: A=2'01, B=2'10, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$a$3189 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$a$3189 [11] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$a$3189 [15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$a$3189 [13:12] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$a$3189 [10:0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$a$3189 [11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$a$3189 [11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$a$3189 [11] 11'00000000000 } New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$1290: { $flatten\ResetBootSystem.$procmux$1285_CMP $flatten\ResetBootSystem.$procmux$1284_CMP } Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$1293: Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$1293_Y New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$1293_Y [1] New connections: $flatten\ResetBootSystem.$procmux$1293_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1225: Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$1608 [2:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$1608 [2] New connections: $auto$wreduce.cc:461:run$1608 [1:0] = 2'10 Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1246: Old ports: A=4'0110, B=12'101101111110, Y=$flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] New ports: A=3'010, B=9'101011110, Y={ $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [3:2] $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [0] } New connections: $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [1] = 1'1 Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][3][7]$3221: Old ports: A=16'0100000100000000, B=16'0000000000000000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][3]$b$3199 New ports: A=1'1, B=1'0, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][3]$b$3199 [8] New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][3]$b$3199 [15:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][3]$b$3199 [7:0] } = { 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][3]$b$3199 [8] 13'0000000000000 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1151: Old ports: A=3'101, B=3'011, Y=$auto$wreduce.cc:461:run$1612 [2:0] New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$1612 [2:1] New connections: $auto$wreduce.cc:461:run$1612 [0] = 1'1 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1196: Old ports: A=4'0001, B=4'1110, Y=$flatten\SOC.\Core.\Control_Unit.$2\nextstate[3:0] New ports: A=2'01, B=2'10, Y=$flatten\SOC.\Core.\Control_Unit.$2\nextstate[3:0] [1:0] New connections: $flatten\SOC.\Core.\Control_Unit.$2\nextstate[3:0] [3:2] = { $flatten\SOC.\Core.\Control_Unit.$2\nextstate[3:0] [1] $flatten\SOC.\Core.\Control_Unit.$2\nextstate[3:0] [1] } Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_tx.$procmux$998: Old ports: A=3'000, B={ 2'00 \SOC.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$1616 [1:0] 2'01 \SOC.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$1618 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state New ports: A=2'00, B={ 1'0 \SOC.Uart.uart_tx_en $auto$wreduce.cc:461:run$1616 [1:0] 1'1 \SOC.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$1618 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state [1:0] New connections: \SOC.Uart.i_uart_tx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$605: Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$1618 [1:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$1618 [0] New connections: $auto$wreduce.cc:461:run$1618 [1] = $auto$wreduce.cc:461:run$1618 [0] Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][3]$3197: Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][3]$a$3198, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][3]$b$3199, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$b$3187 New ports: A={ 1'1 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][3]$a$3198 [9] 1'0 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][3]$b$3199 [8] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][3]$b$3199 [8] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$b$3187 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$b$3187 [9:8] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$b$3187 [15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$b$3187 [13:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$b$3187 [7:0] } = 13'0000000000000 Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$3194: Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$a$3195, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$b$3196, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$a$3186 New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$a$3195 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$a$3195 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$a$3195 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$a$3195 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$a$3195 [0] }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$b$3196 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$b$3196 [1] 2'01 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][2]$b$3196 [1:0] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$a$3186 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$a$3186 [8:7] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$a$3186 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$a$3186 [1:0] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$a$3186 [15:14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$a$3186 [12:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$a$3186 [6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$a$3186 [4:2] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$a$3186 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$a$3186 [7] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$a$3186 [1] 3'000 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][1]$3191: Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][1]$a$3192, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][1]$b$3193, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$b$3184 New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][1]$a$3192 [4] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][1]$a$3192 [4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][1]$a$3192 [2] }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][1]$b$3193 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][1]$b$3193 [7] 2'00 }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$b$3184 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$b$3184 [7] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$b$3184 [4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$b$3184 [2] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$b$3184 [15:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$b$3184 [9:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$b$3184 [6:5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$b$3184 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$b$3184 [1:0] } = { 6'000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$b$3184 [7] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$b$3184 [2] 2'00 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$3188: Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$a$3189, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$b$3190, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$a$3183 New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$a$3189 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$a$3189 [11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$a$3189 [11] 2'00 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$b$3190 [8] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$b$3190 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$b$3190 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][2][0]$b$3190 [2] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$a$3183 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$a$3183 [12:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$a$3183 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$a$3183 [2] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$a$3183 [15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$a$3183 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$a$3183 [10:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$a$3183 [7:3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$a$3183 [1:0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$a$3183 [12] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$a$3183 [12] 9'000000000 } Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$1299: Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$1293_Y, Y=$flatten\ResetBootSystem.$procmux$1299_Y New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$1293_Y [1], Y=$flatten\ResetBootSystem.$procmux$1299_Y [1] New connections: $flatten\ResetBootSystem.$procmux$1299_Y [0] = 1'0 Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$3185: Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$a$3186, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$b$3187, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$b$3181 New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$a$3186 [7] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$a$3186 [13] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$a$3186 [8:7] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$a$3186 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$a$3186 [1:0] }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$b$3187 [14] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][1]$b$3187 [9:8] 4'0000 }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$b$3181 [14:13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$b$3181 [9:7] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$b$3181 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$b$3181 [1:0] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$b$3181 [15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$b$3181 [12:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$b$3181 [6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$b$3181 [4:2] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$b$3181 [13] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$b$3181 [1] 3'000 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$3182: Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$a$3183, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$b$3184, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$a$3180 New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$a$3183 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$a$3183 [12:11] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$a$3183 [8] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$a$3183 [2] }, B={ 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$b$3184 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$b$3184 [7] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$b$3184 [7] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$b$3184 [4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$b$3184 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][1][0]$b$3184 [2] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$a$3180 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$a$3180 [12:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$a$3180 [8:7] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$a$3180 [4:2] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$a$3180 [15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$a$3180 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$a$3180 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$a$3180 [6:5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$a$3180 [1:0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$a$3180 [12] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$a$3180 [12] 5'00000 } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$3179: Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$a$3180, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$b$3181, Y={ \SOC.Core.pc_write \SOC.Core.AluInputBMUX.option \SOC.Core.Control_Unit.ir_write \SOC.Bus.read \SOC.Core.Control_Unit.reg_write \SOC.Core.AluInputAMUX.option \SOC.Core.ALU_Control.aluop_in \SOC.Core.PCSourceMUX.option [0] \SOC.Core.MemoryDataMUX.option [0] \SOC.Bus.write \SOC.Core.MemoryAddressMUX.option [0] \SOC.Core.pc_write_cond \SOC.Core.ALU_Control.is_immediate } New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$a$3180 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$a$3180 [12] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$a$3180 [12:10] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$a$3180 [8:7] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$a$3180 [4:2] 2'00 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$b$3181 [14:13] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$b$3181 [9:7] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$b$3181 [5] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:150:do_switch$710$rdmux[0][0][0]$b$3181 [1:0] }, Y={ \SOC.Core.AluInputBMUX.option \SOC.Core.Control_Unit.ir_write \SOC.Bus.read \SOC.Core.Control_Unit.reg_write \SOC.Core.AluInputAMUX.option \SOC.Core.ALU_Control.aluop_in [1] \SOC.Core.PCSourceMUX.option [0] \SOC.Core.MemoryDataMUX.option [0] \SOC.Bus.write \SOC.Core.MemoryAddressMUX.option [0] \SOC.Core.pc_write_cond \SOC.Core.ALU_Control.is_immediate } New connections: { \SOC.Core.pc_write \SOC.Core.ALU_Control.aluop_in [0] } = { \SOC.Core.AluInputBMUX.option [0] \SOC.Core.pc_write_cond } Optimizing cells in module \top. Performed a total of 26 changes. 21.30.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~12 debug messages> Removed a total of 4 cells. 21.30.6. Executing OPT_DFF pass (perform DFF optimizations). 21.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 20 unused wires. <suppressed ~1 debug messages> 21.30.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 21.30.9. Rerunning OPT passes. (Maybe there is more to do..) 21.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~40 debug messages> 21.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 21.30.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 21.30.13. Executing OPT_DFF pass (perform DFF optimizations). 21.30.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 21.30.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 21.30.16. Finished OPT passes. (There is nothing left to do.) 21.31. Executing TECHMAP pass (map to technology primitives). 21.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 21.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ecp5_alu'. Successfully finished Verilog frontend. 21.31.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $sdffce. Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu. Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $sdffe. Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_demux for cells of type $demux. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $sdff. Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $reduce_bool. Using template $paramod$b469e176aa82369781227d524b4fecc3cede3e1d\_80_ecp5_alu for cells of type $alu. Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux. Using template $paramod$861f5302217787cd55fd1a501bc728125f176580\_80_ecp5_alu for cells of type $alu. Using template $paramod$c96def1cdcef2eee3c62e5dfb7ba2dd09c9f74dd\_90_pmux for cells of type $pmux. Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux. Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $ne. Using template $paramod$3111a1a8e90c88cc8c163ba5aed0203d96ddc46d\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $tribuf. Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $logic_or. Using template $paramod$824a2ca00d29d886599434cf8ea60471635f2955\_90_demux for cells of type $demux. Using template $paramod$215440792383f7884e57d9c95f84e9552d0bf4ac\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $logic_and. Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux. Using template $paramod$41ef080258eed1ff8fcfbb7776f540ab469a3d7b\_80_ecp5_alu for cells of type $alu. Using template $paramod$c4ef20b21801b37ea2d65c32a05dfe56e84a870d\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $bmux. Using template $paramod$33afdd83bf3811dac2de7a968d39eea5718691bc\_90_pmux for cells of type $pmux. Using template $paramod$a13703aa027da371a1931fc542d213d7de559b19\_90_pmux for cells of type $pmux. Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux. Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $dlatch. Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$56955d0f36f77738c952d3505dc563df3ee11b94\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr. Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$dce7c1188cb25d2520d170426d59301c3b73f9e7\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod$a5f0941832cc861549e29ccafffe20bfdf2e5528\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $xor. Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $pos. Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux. Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux. No more expansions possible. <suppressed ~3395 debug messages> 21.32. Executing OPT pass (performing simple optimizations). 21.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~5767 debug messages> 21.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~2541 debug messages> Removed a total of 847 cells. 21.32.3. Executing OPT_DFF pass (perform DFF optimizations). 21.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 351 unused cells and 2734 unused wires. <suppressed ~352 debug messages> 21.32.5. Finished fast OPT passes. 21.33. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 21.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 21.35. Executing TECHMAP pass (map to technology primitives). 21.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 21.35.2. Continuing TECHMAP pass. Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_. Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_. Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_. Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_. No more expansions possible. <suppressed ~465 debug messages> 21.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~29 debug messages> 21.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 21.38. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in top. 21.39. Executing ATTRMVCP pass (move or copy attributes). 21.40. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 1972 unused wires. <suppressed ~1 debug messages> 21.41. Executing TECHMAP pass (map to technology primitives). 21.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 21.41.2. Continuing TECHMAP pass. 21.41.3. Executing SIMPLEMAP pass (map simple cells to gate primitives). Mapping \$_DLATCH_N_.$ternary$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$18999 ($mux). Mapping \$_DLATCH_N_.$logic_not$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$18998 ($logic_not). <suppressed ~4 debug messages> 21.41.4. Executing OPT pass (performing simple optimizations). 21.41.4.1. Executing OPT_EXPR pass (perform const folding). Optimizing module \$_DLATCH_N_. <suppressed ~1 debug messages> 21.41.4.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\$_DLATCH_N_'. Removed a total of 0 cells. 21.41.4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \$_DLATCH_N_.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 21.41.4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \$_DLATCH_N_. Performed a total of 0 changes. 21.41.4.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\$_DLATCH_N_'. Removed a total of 0 cells. 21.41.4.6. Executing OPT_DFF pass (perform DFF optimizations). 21.41.4.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \$_DLATCH_N_.. Removed 1 unused cells and 2 unused wires. <suppressed ~2 debug messages> 21.41.4.8. Executing OPT_EXPR pass (perform const folding). Optimizing module \$_DLATCH_N_. 21.41.4.9. Rerunning OPT passes. (Maybe there is more to do..) 21.41.4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \$_DLATCH_N_.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 21.41.4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \$_DLATCH_N_. Performed a total of 0 changes. 21.41.4.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\$_DLATCH_N_'. Removed a total of 0 cells. 21.41.4.13. Executing OPT_DFF pass (perform DFF optimizations). 21.41.4.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \$_DLATCH_N_.. 21.41.4.15. Executing OPT_EXPR pass (perform const folding). Optimizing module \$_DLATCH_N_. 21.41.4.16. Finished OPT passes. (There is nothing left to do.) Using template \$_DLATCH_N_ for cells of type $_DLATCH_N_. No more expansions possible. <suppressed ~4 debug messages> 21.42. Executing ABC9 pass. 21.42.1. Executing ABC9_OPS pass (helper functions for ABC9). 21.42.2. Executing ABC9_OPS pass (helper functions for ABC9). 21.42.3. Executing PROC pass (convert processes to netlists). 21.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19103'. Cleaned up 1 empty switch. 21.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19104 in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 21.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 21.42.3.4. Executing PROC_INIT pass (extract init attributes). 21.42.3.5. Executing PROC_ARST pass (detect async resets in processes). 21.42.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 21.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19128'. Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19104'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19102_EN[3:0]$19109 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19102_DATA[3:0]$19110 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19102_ADDR[3:0]$19108 Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19103'. 21.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 21.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19097_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19128'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\i' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19128'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19086_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19128'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19090_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19128'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19092_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19128'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19096_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19128'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19098_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19128'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19087_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19128'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19093_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19128'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19099_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19128'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19091_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19128'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19100_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19128'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19094_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19128'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19088_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19128'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19101_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19128'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19095_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19128'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19089_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19128'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19102_ADDR' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19104'. created $dff cell `$procdff$19154' with positive edge clock. Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19102_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19104'. created $dff cell `$procdff$19155' with positive edge clock. Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19102_DATA' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19104'. created $dff cell `$procdff$19156' with positive edge clock. Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19103'. created direct connection (no actual register cell created). 21.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 21.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19128'. Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19104'. Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19103'. Cleaned up 1 empty switch. 21.42.3.12. Executing OPT_EXPR pass (perform const folding). 21.42.4. Executing PROC pass (convert processes to netlists). 21.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19174'. Cleaned up 1 empty switch. 21.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19175 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 21.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 21.42.4.4. Executing PROC_INIT pass (extract init attributes). 21.42.4.5. Executing PROC_ARST pass (detect async resets in processes). 21.42.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 21.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19199'. Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19175'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19173_EN[3:0]$19180 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19173_DATA[3:0]$19181 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19173_ADDR[3:0]$19179 Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19174'. 21.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 21.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19199'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19170_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19199'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19171_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19199'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19167_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19199'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19163_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19199'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19168_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19199'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19160_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19199'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19161_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19199'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19165_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19199'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19166_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19199'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19162_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19199'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19158_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19199'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19172_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19199'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19169_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19199'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19164_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19199'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19159_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19199'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19157_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19199'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19173_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19175'. created $dff cell `$procdff$19225' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19173_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19175'. created $dff cell `$procdff$19226' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19173_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19175'. created $dff cell `$procdff$19227' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19174'. created direct connection (no actual register cell created). 21.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 21.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19199'. Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19175'. Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19174'. Cleaned up 1 empty switch. 21.42.4.12. Executing OPT_EXPR pass (perform const folding). 21.42.5. Executing PROC pass (convert processes to netlists). 21.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19245'. Cleaned up 1 empty switch. 21.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19246 in module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 21.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 21.42.5.4. Executing PROC_INIT pass (extract init attributes). 21.42.5.5. Executing PROC_ARST pass (detect async resets in processes). 21.42.5.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 21.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19270'. Creating decoders for process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19246'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19244_EN[3:0]$19250 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19244_DATA[3:0]$19252 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19244_ADDR[3:0]$19251 Creating decoders for process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19245'. 21.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). 21.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.\i' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19270'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19243_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19270'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19235_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19270'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19241_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19270'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19239_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19270'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19236_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19270'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19231_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19270'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19240_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19270'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19238_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19270'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19228_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19270'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19230_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19270'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19234_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19270'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19233_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19270'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19229_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19270'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19242_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19270'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19237_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19270'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19232_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19270'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19244_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19246'. created $dff cell `$procdff$19296' with positive edge clock. Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19244_ADDR' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19246'. created $dff cell `$procdff$19297' with positive edge clock. Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19244_DATA' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19246'. created $dff cell `$procdff$19298' with positive edge clock. Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.\muxwre' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19245'. created direct connection (no actual register cell created). 21.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 21.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19270'. Found and cleaned up 1 empty switch in `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19246'. Removing empty process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19245'. Cleaned up 1 empty switch. 21.42.5.12. Executing OPT_EXPR pass (perform const folding). 21.42.6. Executing PROC pass (convert processes to netlists). 21.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19316'. Cleaned up 1 empty switch. 21.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19317 in module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 21.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 21.42.6.4. Executing PROC_INIT pass (extract init attributes). 21.42.6.5. Executing PROC_ARST pass (detect async resets in processes). 21.42.6.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 21.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19341'. Creating decoders for process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19317'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19315_EN[3:0]$19322 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19315_DATA[3:0]$19321 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19315_ADDR[3:0]$19323 Creating decoders for process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19316'. 21.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches). 21.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.\i' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19341'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19302_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19341'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19301_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19341'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19299_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19341'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19306_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19341'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19307_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19341'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19311_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19341'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19303_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19341'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19312_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19341'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19308_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19341'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19304_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19341'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19313_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19341'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19309_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19341'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19314_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19341'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19310_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19341'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19305_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19341'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19300_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19341'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19315_DATA' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19317'. created $dff cell `$procdff$19367' with positive edge clock. Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19315_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19317'. created $dff cell `$procdff$19368' with positive edge clock. Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19315_ADDR' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19317'. created $dff cell `$procdff$19369' with positive edge clock. Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19316'. created direct connection (no actual register cell created). 21.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 21.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19341'. Found and cleaned up 1 empty switch in `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19317'. Removing empty process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19316'. Cleaned up 1 empty switch. 21.42.6.12. Executing OPT_EXPR pass (perform const folding). 21.42.7. Executing PROC pass (convert processes to netlists). 21.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19387'. Cleaned up 1 empty switch. 21.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19388 in module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 21.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 21.42.7.4. Executing PROC_INIT pass (extract init attributes). 21.42.7.5. Executing PROC_ARST pass (detect async resets in processes). 21.42.7.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 21.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19412'. Creating decoders for process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19388'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19386_EN[3:0]$19394 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19386_DATA[3:0]$19393 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19386_ADDR[3:0]$19392 Creating decoders for process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19387'. 21.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches). 21.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.\i' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19412'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19370_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19412'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19374_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19412'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19375_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19412'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19379_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19412'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19371_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19412'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19380_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19412'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19384_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19412'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19376_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19412'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19385_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19412'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19372_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19412'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19381_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19412'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19377_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19412'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19382_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19412'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19383_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19412'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19378_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19412'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19373_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19412'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19386_ADDR' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19388'. created $dff cell `$procdff$19438' with positive edge clock. Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19386_DATA' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19388'. created $dff cell `$procdff$19439' with positive edge clock. Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19386_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19388'. created $dff cell `$procdff$19440' with positive edge clock. Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19387'. created direct connection (no actual register cell created). 21.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 21.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19412'. Found and cleaned up 1 empty switch in `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19388'. Removing empty process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19387'. Cleaned up 1 empty switch. 21.42.7.12. Executing OPT_EXPR pass (perform const folding). 21.42.8. Executing PROC pass (convert processes to netlists). 21.42.8.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19458'. Cleaned up 1 empty switch. 21.42.8.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19459 in module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 21.42.8.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 21.42.8.4. Executing PROC_INIT pass (extract init attributes). 21.42.8.5. Executing PROC_ARST pass (detect async resets in processes). 21.42.8.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 21.42.8.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19483'. Creating decoders for process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19459'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19457_EN[3:0]$19465 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19457_DATA[3:0]$19464 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19457_ADDR[3:0]$19463 Creating decoders for process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19458'. 21.42.8.8. Executing PROC_DLATCH pass (convert process syncs to latches). 21.42.8.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.\i' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19483'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19441_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19483'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19442_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19483'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19443_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19483'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19447_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19483'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19448_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19483'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19452_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19483'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19444_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19483'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19453_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19483'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19449_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19483'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19445_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19483'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19454_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19483'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19450_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19483'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19455_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19483'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19456_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19483'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19451_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19483'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19446_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19483'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19457_ADDR' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19459'. created $dff cell `$procdff$19509' with positive edge clock. Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19457_DATA' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19459'. created $dff cell `$procdff$19510' with positive edge clock. Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19457_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19459'. created $dff cell `$procdff$19511' with positive edge clock. Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.\muxwre' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19458'. created direct connection (no actual register cell created). 21.42.8.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 21.42.8.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19483'. Found and cleaned up 1 empty switch in `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19459'. Removing empty process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19458'. Cleaned up 1 empty switch. 21.42.8.12. Executing OPT_EXPR pass (perform const folding). 21.42.9. Executing PROC pass (convert processes to netlists). 21.42.9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19529'. Cleaned up 1 empty switch. 21.42.9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19530 in module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 21.42.9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 21.42.9.4. Executing PROC_INIT pass (extract init attributes). 21.42.9.5. Executing PROC_ARST pass (detect async resets in processes). 21.42.9.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 21.42.9.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19554'. Creating decoders for process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19530'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19528_EN[3:0]$19534 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19528_DATA[3:0]$19536 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19528_ADDR[3:0]$19535 Creating decoders for process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19529'. 21.42.9.8. Executing PROC_DLATCH pass (convert process syncs to latches). 21.42.9.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.\i' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19554'. created direct connection (no actual register cell created). Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19515_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19554'. created direct connection (no actual register cell created). Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19516_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19554'. created direct connection (no actual register cell created). Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19520_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19554'. created direct connection (no actual register cell created). Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19521_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19554'. created direct connection (no actual register cell created). Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19525_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19554'. created direct connection (no actual register cell created). Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19517_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19554'. created direct connection (no actual register cell created). Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19526_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19554'. created direct connection (no actual register cell created). Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19513_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19554'. created direct connection (no actual register cell created). Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19522_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19554'. created direct connection (no actual register cell created). Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19518_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19554'. created direct connection (no actual register cell created). Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19527_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19554'. created direct connection (no actual register cell created). Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19523_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19554'. created direct connection (no actual register cell created). Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19524_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19554'. created direct connection (no actual register cell created). Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19519_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19554'. created direct connection (no actual register cell created). Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19514_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19554'. created direct connection (no actual register cell created). Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19512_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19554'. created direct connection (no actual register cell created). Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19528_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19530'. created $dff cell `$procdff$19580' with positive edge clock. Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19528_ADDR' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19530'. created $dff cell `$procdff$19581' with positive edge clock. Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19528_DATA' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19530'. created $dff cell `$procdff$19582' with positive edge clock. Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.\muxwre' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19529'. created direct connection (no actual register cell created). 21.42.9.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 21.42.9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19554'. Found and cleaned up 1 empty switch in `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19530'. Removing empty process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19529'. Cleaned up 1 empty switch. 21.42.9.12. Executing OPT_EXPR pass (perform const folding). 21.42.10. Executing PROC pass (convert processes to netlists). 21.42.10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19600'. Cleaned up 1 empty switch. 21.42.10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19601 in module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 21.42.10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 21.42.10.4. Executing PROC_INIT pass (extract init attributes). 21.42.10.5. Executing PROC_ARST pass (detect async resets in processes). 21.42.10.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 21.42.10.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19625'. Creating decoders for process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19601'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19599_EN[3:0]$19605 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19599_DATA[3:0]$19607 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19599_ADDR[3:0]$19606 Creating decoders for process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19600'. 21.42.10.8. Executing PROC_DLATCH pass (convert process syncs to latches). 21.42.10.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.\i' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19625'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19583_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19625'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19584_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19625'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19585_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19625'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19589_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19625'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19590_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19625'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19591_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19625'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19595_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19625'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19596_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19625'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19586_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19625'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19597_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19625'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19587_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19625'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19592_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19625'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19593_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19625'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19598_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19625'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19594_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19625'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19588_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19625'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19599_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19601'. created $dff cell `$procdff$19651' with positive edge clock. Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19599_ADDR' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19601'. created $dff cell `$procdff$19652' with positive edge clock. Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19599_DATA' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19601'. created $dff cell `$procdff$19653' with positive edge clock. Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.\muxwre' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19600'. created direct connection (no actual register cell created). 21.42.10.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 21.42.10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19625'. Found and cleaned up 1 empty switch in `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19601'. Removing empty process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19600'. Cleaned up 1 empty switch. 21.42.10.12. Executing OPT_EXPR pass (perform const folding). 21.42.11. Executing PROC pass (convert processes to netlists). 21.42.11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19671'. Cleaned up 1 empty switch. 21.42.11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19672 in module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 21.42.11.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 21.42.11.4. Executing PROC_INIT pass (extract init attributes). 21.42.11.5. Executing PROC_ARST pass (detect async resets in processes). 21.42.11.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 21.42.11.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19696'. Creating decoders for process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19672'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19670_EN[3:0]$19677 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19670_DATA[3:0]$19676 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19670_ADDR[3:0]$19678 Creating decoders for process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19671'. 21.42.11.8. Executing PROC_DLATCH pass (convert process syncs to latches). 21.42.11.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.\i' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19696'. created direct connection (no actual register cell created). Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19654_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19696'. created direct connection (no actual register cell created). Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19655_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19696'. created direct connection (no actual register cell created). Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19659_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19696'. created direct connection (no actual register cell created). Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19660_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19696'. created direct connection (no actual register cell created). Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19661_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19696'. created direct connection (no actual register cell created). Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19665_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19696'. created direct connection (no actual register cell created). Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19666_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19696'. created direct connection (no actual register cell created). Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19656_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19696'. created direct connection (no actual register cell created). Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19667_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19696'. created direct connection (no actual register cell created). Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19657_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19696'. created direct connection (no actual register cell created). Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19662_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19696'. created direct connection (no actual register cell created). Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19663_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19696'. created direct connection (no actual register cell created). Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19668_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19696'. created direct connection (no actual register cell created). Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19669_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19696'. created direct connection (no actual register cell created). Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19664_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19696'. created direct connection (no actual register cell created). Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19658_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19696'. created direct connection (no actual register cell created). Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19670_DATA' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19672'. created $dff cell `$procdff$19722' with positive edge clock. Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19670_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19672'. created $dff cell `$procdff$19723' with positive edge clock. Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19670_ADDR' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19672'. created $dff cell `$procdff$19724' with positive edge clock. Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.\muxwre' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19671'. created direct connection (no actual register cell created). 21.42.11.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 21.42.11.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19696'. Found and cleaned up 1 empty switch in `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19672'. Removing empty process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19671'. Cleaned up 1 empty switch. 21.42.11.12. Executing OPT_EXPR pass (perform const folding). 21.42.12. Executing PROC pass (convert processes to netlists). 21.42.12.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19742'. Cleaned up 1 empty switch. 21.42.12.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19743 in module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 21.42.12.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 21.42.12.4. Executing PROC_INIT pass (extract init attributes). 21.42.12.5. Executing PROC_ARST pass (detect async resets in processes). 21.42.12.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 21.42.12.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19767'. Creating decoders for process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19743'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19741_EN[3:0]$19749 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19741_DATA[3:0]$19748 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19741_ADDR[3:0]$19747 Creating decoders for process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19742'. 21.42.12.8. Executing PROC_DLATCH pass (convert process syncs to latches). 21.42.12.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.\i' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19767'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19725_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19767'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19729_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19767'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19730_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19767'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19731_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19767'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19735_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19767'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19736_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19767'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19726_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19767'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19737_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19767'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19727_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19767'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19732_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19767'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19733_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19767'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19738_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19767'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19739_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19767'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19740_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19767'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19734_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19767'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$19728_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19767'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19741_ADDR' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19743'. created $dff cell `$procdff$19793' with positive edge clock. Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19741_DATA' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19743'. created $dff cell `$procdff$19794' with positive edge clock. Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$19741_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19743'. created $dff cell `$procdff$19795' with positive edge clock. Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19742'. created direct connection (no actual register cell created). 21.42.12.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 21.42.12.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$19767'. Found and cleaned up 1 empty switch in `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$19743'. Removing empty process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$19742'. Cleaned up 1 empty switch. 21.42.12.12. Executing OPT_EXPR pass (perform const folding). 21.42.13. Executing SCC pass (detecting logic loops). Found an SCC: $techmap$auto$ff.cc:266:slice$8633.$auto$simplemap.cc:267:simplemap_mux$19001 Found an SCC: $techmap$auto$ff.cc:266:slice$8632.$auto$simplemap.cc:267:simplemap_mux$19001 Found an SCC: $techmap$auto$ff.cc:266:slice$8631.$auto$simplemap.cc:267:simplemap_mux$19001 Found an SCC: $techmap$auto$ff.cc:266:slice$8630.$auto$simplemap.cc:267:simplemap_mux$19001 Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$18249 $auto$ff.cc:266:slice$5120 $auto$ff.cc:266:slice$5118 $auto$simplemap.cc:126:simplemap_reduce$5246 $auto$opt_expr.cc:613:replace_const_cells$18247 $auto$simplemap.cc:126:simplemap_reduce$5261 $auto$ff.cc:266:slice$5117 $auto$simplemap.cc:126:simplemap_reduce$14429 $auto$simplemap.cc:75:simplemap_bitop$14444 $auto$opt_expr.cc:613:replace_const_cells$18325 $auto$simplemap.cc:225:simplemap_logbin$5236 $auto$simplemap.cc:196:simplemap_lognot$5251 $auto$simplemap.cc:126:simplemap_reduce$5249 $auto$simplemap.cc:126:simplemap_reduce$5247 $auto$opt_expr.cc:613:replace_const_cells$18267 $auto$simplemap.cc:267:simplemap_mux$14446 $auto$simplemap.cc:126:simplemap_reduce$14437 $auto$simplemap.cc:126:simplemap_reduce$14434 $auto$simplemap.cc:75:simplemap_bitop$14442 $auto$simplemap.cc:196:simplemap_lognot$5266 $auto$simplemap.cc:126:simplemap_reduce$5264 $auto$simplemap.cc:126:simplemap_reduce$5262 $auto$ff.cc:266:slice$5119 $auto$simplemap.cc:126:simplemap_reduce$4779 $auto$simplemap.cc:126:simplemap_reduce$4777 $auto$simplemap.cc:225:simplemap_logbin$5208 $auto$simplemap.cc:196:simplemap_lognot$5218 $auto$simplemap.cc:126:simplemap_reduce$5216 $auto$opt_expr.cc:613:replace_const_cells$18265 $auto$simplemap.cc:267:simplemap_mux$14447 $auto$simplemap.cc:126:simplemap_reduce$14432 Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$4491 $auto$simplemap.cc:38:simplemap_not$16882 $auto$ff.cc:266:slice$3375 $auto$ff.cc:479:convert_ce_over_srst$18619 $auto$simplemap.cc:126:simplemap_reduce$5527 $auto$ff.cc:266:slice$3374 $auto$ff.cc:479:convert_ce_over_srst$18617 $auto$simplemap.cc:38:simplemap_not$11661 $auto$ff.cc:266:slice$3373 $auto$ff.cc:479:convert_ce_over_srst$18615 $auto$simplemap.cc:126:simplemap_reduce$5526 $auto$ff.cc:266:slice$3372 $auto$ff.cc:479:convert_ce_over_srst$18613 $auto$simplemap.cc:38:simplemap_not$11659 $auto$ff.cc:266:slice$3371 $auto$ff.cc:479:convert_ce_over_srst$18611 $auto$alumacc.cc:485:replace_alu$1719.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$1719.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$1719.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$4293 $auto$simplemap.cc:126:simplemap_reduce$5531 $auto$simplemap.cc:126:simplemap_reduce$5529 $auto$simplemap.cc:126:simplemap_reduce$5525 $auto$simplemap.cc:38:simplemap_not$16877 $auto$ff.cc:266:slice$3370 $auto$ff.cc:479:convert_ce_over_srst$18609 $auto$simplemap.cc:126:simplemap_reduce$4516 $auto$simplemap.cc:126:simplemap_reduce$4514 $auto$simplemap.cc:126:simplemap_reduce$4296 $auto$simplemap.cc:126:simplemap_reduce$4294 $auto$simplemap.cc:38:simplemap_not$5200 $auto$simplemap.cc:75:simplemap_bitop$5334 $auto$simplemap.cc:38:simplemap_not$7814 Found an SCC: $auto$simplemap.cc:38:simplemap_not$14423 $auto$ff.cc:266:slice$4857 $auto$opt_expr.cc:613:replace_const_cells$18135 $auto$ff.cc:266:slice$4859 $auto$opt_expr.cc:613:replace_const_cells$18121 $auto$ff.cc:266:slice$4852 $auto$simplemap.cc:126:simplemap_reduce$5068 $auto$opt_expr.cc:613:replace_const_cells$18125 $auto$simplemap.cc:126:simplemap_reduce$5103 $auto$ff.cc:266:slice$4858 $auto$simplemap.cc:126:simplemap_reduce$5072 $auto$simplemap.cc:126:simplemap_reduce$5067 $auto$opt_expr.cc:613:replace_const_cells$18123 $auto$simplemap.cc:126:simplemap_reduce$5107 $auto$simplemap.cc:126:simplemap_reduce$5102 $auto$ff.cc:266:slice$4856 $auto$ff.cc:266:slice$4848 $auto$simplemap.cc:126:simplemap_reduce$5075 $auto$simplemap.cc:126:simplemap_reduce$5110 $auto$ff.cc:266:slice$4860 $auto$opt_expr.cc:613:replace_const_cells$18129 $auto$ff.cc:266:slice$4851 $auto$simplemap.cc:126:simplemap_reduce$5064 $auto$simplemap.cc:126:simplemap_reduce$5099 $auto$opt_expr.cc:613:replace_const_cells$18127 $auto$ff.cc:266:slice$4850 $auto$simplemap.cc:126:simplemap_reduce$5070 $auto$simplemap.cc:126:simplemap_reduce$5063 $auto$simplemap.cc:38:simplemap_not$14415 $auto$simplemap.cc:126:simplemap_reduce$5105 $auto$simplemap.cc:126:simplemap_reduce$5098 $auto$ff.cc:266:slice$4849 $auto$ff.cc:266:slice$4855 $auto$simplemap.cc:126:simplemap_reduce$5101 $auto$ff.cc:266:slice$4854 $auto$simplemap.cc:225:simplemap_logbin$5044 $auto$simplemap.cc:196:simplemap_lognot$5079 $auto$simplemap.cc:126:simplemap_reduce$5077 $auto$simplemap.cc:126:simplemap_reduce$5074 $auto$simplemap.cc:126:simplemap_reduce$5071 $auto$simplemap.cc:126:simplemap_reduce$5065 $auto$simplemap.cc:126:simplemap_reduce$5109 $auto$simplemap.cc:126:simplemap_reduce$5106 $auto$simplemap.cc:126:simplemap_reduce$5100 $auto$opt_expr.cc:613:replace_const_cells$18131 $auto$ff.cc:266:slice$4853 $auto$simplemap.cc:167:logic_reduce$4862 $auto$simplemap.cc:225:simplemap_logbin$5043 $auto$simplemap.cc:196:simplemap_lognot$5114 $auto$simplemap.cc:126:simplemap_reduce$5112 Found an SCC: $auto$ff.cc:266:slice$3843 $auto$ff.cc:266:slice$3850 $auto$simplemap.cc:126:simplemap_reduce$5165 $auto$ff.cc:266:slice$3851 $auto$simplemap.cc:38:simplemap_not$13210 $auto$ff.cc:266:slice$3839 $auto$ff.cc:266:slice$3846 $auto$ff.cc:266:slice$3844 $auto$simplemap.cc:126:simplemap_reduce$5162 $auto$ff.cc:266:slice$3845 $auto$ff.cc:266:slice$3835 $auto$simplemap.cc:38:simplemap_not$14300 $auto$ff.cc:266:slice$3841 $auto$simplemap.cc:126:simplemap_reduce$5163 $auto$simplemap.cc:38:simplemap_not$13218 $auto$ff.cc:266:slice$3847 $auto$ff.cc:266:slice$3853 $auto$simplemap.cc:38:simplemap_not$13230 $auto$ff.cc:266:slice$3859 $auto$simplemap.cc:38:simplemap_not$13236 $auto$ff.cc:266:slice$3865 $auto$simplemap.cc:126:simplemap_reduce$5157 $auto$ff.cc:266:slice$3834 $auto$ff.cc:266:slice$3836 $auto$simplemap.cc:38:simplemap_not$14319 $auto$ff.cc:266:slice$3860 $auto$ff.cc:266:slice$3854 $auto$simplemap.cc:126:simplemap_reduce$5160 $auto$simplemap.cc:38:simplemap_not$13211 $auto$ff.cc:266:slice$3840 $auto$simplemap.cc:126:simplemap_reduce$5174 $auto$simplemap.cc:126:simplemap_reduce$5158 $auto$ff.cc:266:slice$3837 $auto$alumacc.cc:485:replace_alu$1730.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$1730.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$5183 $auto$simplemap.cc:126:simplemap_reduce$5175 $auto$simplemap.cc:126:simplemap_reduce$5159 $auto$simplemap.cc:38:simplemap_not$14297 $auto$ff.cc:266:slice$3838 $auto$ff.cc:266:slice$3848 $auto$simplemap.cc:38:simplemap_not$13234 $auto$ff.cc:266:slice$3863 $auto$simplemap.cc:126:simplemap_reduce$5177 $auto$simplemap.cc:126:simplemap_reduce$5164 $auto$simplemap.cc:38:simplemap_not$13220 $auto$ff.cc:266:slice$3849 $auto$simplemap.cc:126:simplemap_reduce$5178 $auto$simplemap.cc:126:simplemap_reduce$5166 $auto$ff.cc:266:slice$3852 $auto$alumacc.cc:485:replace_alu$1730.slice[14].ccu2c_i $auto$alumacc.cc:485:replace_alu$1730.slice[12].ccu2c_i $auto$alumacc.cc:485:replace_alu$1730.slice[10].ccu2c_i $auto$alumacc.cc:485:replace_alu$1730.slice[8].ccu2c_i $auto$alumacc.cc:485:replace_alu$1730.slice[6].ccu2c_i $auto$alumacc.cc:485:replace_alu$1730.slice[4].ccu2c_i $auto$ff.cc:266:slice$3842 $auto$simplemap.cc:126:simplemap_reduce$5172 $auto$simplemap.cc:38:simplemap_not$13235 $auto$ff.cc:266:slice$3864 $auto$simplemap.cc:126:simplemap_reduce$5170 $auto$simplemap.cc:38:simplemap_not$13232 $auto$ff.cc:266:slice$3861 $auto$alumacc.cc:485:replace_alu$1730.slice[16].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$5167 $auto$simplemap.cc:38:simplemap_not$13226 $auto$ff.cc:266:slice$3855 $auto$simplemap.cc:126:simplemap_reduce$5181 $auto$simplemap.cc:126:simplemap_reduce$5171 $auto$simplemap.cc:38:simplemap_not$13233 $auto$ff.cc:266:slice$3862 $auto$simplemap.cc:126:simplemap_reduce$5186 $auto$simplemap.cc:126:simplemap_reduce$5180 $auto$simplemap.cc:126:simplemap_reduce$5169 $auto$simplemap.cc:38:simplemap_not$14317 $auto$ff.cc:266:slice$3858 $auto$simplemap.cc:38:simplemap_not$14316 $auto$ff.cc:266:slice$3857 $auto$simplemap.cc:38:simplemap_not$5192 $auto$alumacc.cc:485:replace_alu$1730.slice[26].ccu2c_i $auto$alumacc.cc:485:replace_alu$1730.slice[24].ccu2c_i $auto$alumacc.cc:485:replace_alu$1730.slice[22].ccu2c_i $auto$alumacc.cc:485:replace_alu$1730.slice[20].ccu2c_i $auto$alumacc.cc:485:replace_alu$1730.slice[18].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$5189 $auto$simplemap.cc:126:simplemap_reduce$5185 $auto$simplemap.cc:126:simplemap_reduce$5179 $auto$simplemap.cc:126:simplemap_reduce$5168 $auto$ff.cc:266:slice$3856 $auto$simplemap.cc:126:simplemap_reduce$4725 $auto$simplemap.cc:126:simplemap_reduce$4723 $auto$simplemap.cc:126:simplemap_reduce$5191 $auto$simplemap.cc:126:simplemap_reduce$5188 $auto$simplemap.cc:126:simplemap_reduce$5184 $auto$simplemap.cc:126:simplemap_reduce$5176 $auto$simplemap.cc:126:simplemap_reduce$5161 $auto$simplemap.cc:38:simplemap_not$14301 Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$18261 $auto$ff.cc:266:slice$5132 $auto$simplemap.cc:126:simplemap_reduce$5290 $auto$ff.cc:266:slice$5131 $auto$ff.cc:266:slice$5130 $auto$ff.cc:266:slice$5129 $auto$ff.cc:266:slice$5121 $auto$ff.cc:266:slice$5133 $auto$ff.cc:266:slice$5128 $auto$simplemap.cc:126:simplemap_reduce$5288 $auto$ff.cc:266:slice$5127 $auto$opt_expr.cc:613:replace_const_cells$18257 $auto$ff.cc:266:slice$5126 $auto$simplemap.cc:126:simplemap_reduce$5293 $auto$simplemap.cc:126:simplemap_reduce$5287 $auto$ff.cc:266:slice$5125 $auto$simplemap.cc:38:simplemap_not$14512 $auto$ff.cc:266:slice$5124 $auto$simplemap.cc:126:simplemap_reduce$5286 $auto$simplemap.cc:38:simplemap_not$14511 $auto$ff.cc:266:slice$5123 $auto$simplemap.cc:126:simplemap_reduce$5296 $auto$simplemap.cc:126:simplemap_reduce$5292 $auto$simplemap.cc:126:simplemap_reduce$5285 $auto$ff.cc:266:slice$5122 $auto$simplemap.cc:167:logic_reduce$4760 $auto$simplemap.cc:196:simplemap_lognot$5301 $auto$simplemap.cc:126:simplemap_reduce$5299 $auto$simplemap.cc:126:simplemap_reduce$5297 $auto$simplemap.cc:126:simplemap_reduce$5294 $auto$simplemap.cc:126:simplemap_reduce$5289 $auto$simplemap.cc:38:simplemap_not$14518 Found 9 SCCs in module top. Found 9 SCCs. 21.42.14. Executing ABC9_OPS pass (helper functions for ABC9). 21.42.15. Executing PROC pass (convert processes to netlists). 21.42.15.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 21.42.15.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 21.42.15.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 21.42.15.4. Executing PROC_INIT pass (extract init attributes). 21.42.15.5. Executing PROC_ARST pass (detect async resets in processes). 21.42.15.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 21.42.15.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 21.42.15.8. Executing PROC_DLATCH pass (convert process syncs to latches). 21.42.15.9. Executing PROC_DFF pass (convert process syncs to FFs). 21.42.15.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 21.42.15.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 21.42.15.12. Executing OPT_EXPR pass (perform const folding). 21.42.16. Executing TECHMAP pass (map to technology primitives). 21.42.16.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 21.42.16.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~180 debug messages> 21.42.17. Executing OPT pass (performing simple optimizations). 21.42.17.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4. Optimizing module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4. Optimizing module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4. Optimizing module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4. Optimizing module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4. Optimizing module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4. Optimizing module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4. Optimizing module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4. 21.42.17.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4'. Removed a total of 0 cells. 21.42.17.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 21.42.17.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing cells in module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4. Optimizing cells in module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4. Optimizing cells in module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4. Optimizing cells in module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4. Optimizing cells in module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4. Optimizing cells in module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4. Optimizing cells in module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4. Optimizing cells in module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4. Performed a total of 0 changes. 21.42.17.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4'. Removed a total of 0 cells. 21.42.17.6. Executing OPT_DFF pass (perform DFF optimizations). 21.42.17.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.. 21.42.17.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4. Optimizing module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4. Optimizing module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4. Optimizing module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4. Optimizing module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4. Optimizing module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4. Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Optimizing module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4. Optimizing module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4. 21.42.17.9. Finished OPT passes. (There is nothing left to do.) 21.42.18. Executing TECHMAP pass (map to technology primitives). 21.42.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 21.42.18.2. Continuing TECHMAP pass. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Using template $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4 for cells of type $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4. Using template $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4 for cells of type $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4. Using template $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4 for cells of type $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4. Using template $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4 for cells of type $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4. Using template $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4 for cells of type $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4. Using template $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4 for cells of type $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4. Using template $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4 for cells of type $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4. Using template $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4 for cells of type $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4. No more expansions possible. <suppressed ~556 debug messages> 21.42.19. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 21.42.20. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 21.42.21. Executing ABC9_OPS pass (helper functions for ABC9). 21.42.22. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 21.42.23. Executing TECHMAP pass (map to technology primitives). 21.42.23.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 21.42.23.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $mux. No more expansions possible. <suppressed ~219 debug messages> 21.42.24. Executing OPT pass (performing simple optimizations). 21.42.24.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~18 debug messages> 21.42.24.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 21.42.24.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 21.42.24.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 21.42.24.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 21.42.24.6. Executing OPT_DFF pass (perform DFF optimizations). 21.42.24.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 55 unused wires. <suppressed ~1 debug messages> 21.42.24.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 21.42.24.9. Rerunning OPT passes. (Maybe there is more to do..) 21.42.24.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 21.42.24.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 21.42.24.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 21.42.24.13. Executing OPT_DFF pass (perform DFF optimizations). 21.42.24.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 21.42.24.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 21.42.24.16. Finished OPT passes. (There is nothing left to do.) 21.42.25. Executing AIGMAP pass (map logic to AIG). Module top: replaced 18 cells with 120 new cells, skipped 39 cells. replaced 3 cell types: 2 $_OR_ 2 $_XOR_ 14 $_MUX_ not replaced 3 cell types: 31 $specify2 4 $_NOT_ 4 $_AND_ 21.42.26. Executing AIGMAP pass (map logic to AIG). Module top: replaced 3973 cells with 25510 new cells, skipped 2780 cells. replaced 3 cell types: 767 $_OR_ 70 $_XOR_ 3136 $_MUX_ not replaced 26 cell types: 300 $_NOT_ 792 $_AND_ 6 $_TBUF_ 1 $__ABC9_SCC_BREAKER 1 $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4_$abc9_byp 361 TRELLIS_FF 16 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp 16 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 520 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 232 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C 1 $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4 1 $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4 1 $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4 1 $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4 1 $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4 1 $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4 1 $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4 1 $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4 520 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4_$abc9_byp 21.42.26.1. Executing ABC9_OPS pass (helper functions for ABC9). 21.42.26.2. Executing ABC9_OPS pass (helper functions for ABC9). 21.42.26.3. Executing XAIGER backend. <suppressed ~11 debug messages> Extracted 11177 AND gates and 32524 wires from module `top' to a netlist network with 2555 inputs and 530 outputs. 21.42.26.4. Executing ABC9_EXE pass (technology mapping using ABC9). 21.42.26.5. Executing ABC9. Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1 ABC: ABC command line: "source <abc-temp-dir>/abc.script". ABC: ABC: + read_lut <abc-temp-dir>/input.lut ABC: + read_box <abc-temp-dir>/input.box ABC: + &read <abc-temp-dir>/input.xaig ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 2555/ 530 and = 9939 lev = 44 (5.76) mem = 0.30 MB box = 776 bb = 544 ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 2555/ 530 and = 13042 lev = 59 (2.84) mem = 0.33 MB ch = 1237 box = 700 bb = 544 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 60. Obj = 140. Set = 636. CutMin = no ABC: Node = 13042. Ch = 911. Total mem = 3.65 MB. Peak cut mem = 0.21 MB. ABC: P: Del = 6818.00. Ar = 12977.0. Edge = 14212. Cut = 195063. T = 0.04 sec ABC: P: Del = 6817.00. Ar = 13155.0. Edge = 14454. Cut = 175208. T = 0.04 sec ABC: P: Del = 6817.00. Ar = 5308.0. Edge = 12334. Cut = 453075. T = 0.10 sec ABC: F: Del = 6817.00. Ar = 4151.0. Edge = 10976. Cut = 392545. T = 0.09 sec ABC: A: Del = 6811.00. Ar = 3763.0. Edge = 10078. Cut = 257716. T = 0.11 sec ABC: A: Del = 6808.00. Ar = 3727.0. Edge = 10042. Cut = 388088. T = 0.15 sec ABC: Total time = 0.53 sec ABC: + &write -n <abc-temp-dir>/output.aig ABC: + &mfs ABC: + &ps -l ABC: <abc-temp-dir>/input : i/o = 2555/ 530 and = 8518 lev = 36 (3.23) mem = 0.27 MB box = 700 bb = 544 ABC: Mapping (K=7) : lut = 2529 edge = 10020 lev = 14 (1.37) levB = 25 mem = 0.13 MB ABC: LUT = 2529 : 2=272 10.8 % 3=315 12.5 % 4=1422 56.2 % 5=368 14.6 % 6=61 2.4 % 7=91 3.6 % Ave = 3.96 ABC: + &write -n <abc-temp-dir>/output.aig ABC: + time ABC: elapse: 4.05 seconds, total: 4.05 seconds 21.42.26.6. Executing AIGER frontend. <suppressed ~6258 debug messages> Removed 11539 unused cells and 25396 unused wires. 21.42.26.7. Executing ABC9_OPS pass (helper functions for ABC9). ABC RESULTS: $lut cells: 2552 ABC RESULTS: $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp cells: 16 ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 156 ABC RESULTS: $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 520 ABC RESULTS: $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: input signals: 574 ABC RESULTS: output signals: 107 Removing temp directory. 21.42.27. Executing TECHMAP pass (map to technology primitives). 21.42.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 21.42.27.2. Continuing TECHMAP pass. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4 for cells of type $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4. Using template $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4 for cells of type $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4. Using template $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4 for cells of type $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4. Using template $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4 for cells of type $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4. Using template $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4 for cells of type $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4. Using template $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4 for cells of type $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4. Using template $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4 for cells of type $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4. Using template $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4 for cells of type $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4. Using template $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000001001 for cells of type $__ABC9_SCC_BREAKER. Using template $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4_$abc9_byp. No more expansions possible. <suppressed ~1282 debug messages> Removed 161 unused cells and 40608 unused wires. 21.43. Executing TECHMAP pass (map to technology primitives). 21.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 21.43.2. Continuing TECHMAP pass. Using template $paramod$a8b2b0f3a3fd7b01c99e8d61bb72f602bd41af54\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut. Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut. Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut. Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut. Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut. Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut. Using template $paramod$59f2a3e232df3029c8bc36978b9bbe72a71dfb5a\$lut for cells of type $lut. Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut. Using template $paramod$75ae9627805e0c99d176bdce0ae8ff0c02687aab\$lut for cells of type $lut. Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut. Using template $paramod$0f891ee84fac320f890afcf9c994c53a24cd31f9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. Using template $paramod$c217e185eb8e6463ca272982ba8c5940fa90d81f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut. Using template $paramod$e85b6eba0dacefc5f73f8748159b8b9599212afc\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut. Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut. Using template $paramod$e9151b5894a7574ed1f3f44ed802f9cc6cf36fc1\$lut for cells of type $lut. Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut. Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut. Using template $paramod$7ccb46ee9b56c39e0a7d82a185b08cb026e04fbc\$lut for cells of type $lut. Using template $paramod$63114da772fb28945ba24699e32f1e30ca7142f4\$lut for cells of type $lut. Using template $paramod$394086530b97e2ede4325cfef07483589916f736\$lut for cells of type $lut. Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut. Using template $paramod$f28c2e49975958241d4d835ef97e799ed72256e5\$lut for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. Using template $paramod$3ccc23db184ad4ca7ed34ebe2511de41d5d97e78\$lut for cells of type $lut. Using template $paramod$7202672b7332febf25cdbe5424cf24593f5449be\$lut for cells of type $lut. Using template $paramod$2c1875de701f39453798b76f5b327fe456cc0991\$lut for cells of type $lut. Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. Using template $paramod$5e2c4e05bbdd2eaa20212f01bb8e88597c0f6680\$lut for cells of type $lut. Using template $paramod$f28a4401e00366386f5c9da01093cb438d2ef37a\$lut for cells of type $lut. Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5\$lut for cells of type $lut. Using template $paramod$fc41ed89496d8fea1bccabac6605f28217a9a3c1\$lut for cells of type $lut. Using template $paramod$08466811901d5e03ed77c75ae1ee4f324a7c22b7\$lut for cells of type $lut. Using template $paramod$f7bd536f0a874c7bb7aaa1ac909bf2d4656af121\$lut for cells of type $lut. Using template $paramod$40bf400bfab4b5cf32dcfe01e14f0900ac7f6b1b\$lut for cells of type $lut. Using template $paramod$3094262c264dea75d3d39a27858b110dbeb0338a\$lut for cells of type $lut. Using template $paramod$525425bfbe66d72ee88210d059d9a74f55ab8de8\$lut for cells of type $lut. Using template $paramod$ce44877a8aba311086973ef3ef648b154684306e\$lut for cells of type $lut. Using template $paramod$26086aa058c2908e5376930381a40ab08b4e5c29\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. Using template $paramod$ec4a21f896d8babdcea50998bb320a7741366e32\$lut for cells of type $lut. Using template $paramod$26ef535d2a282869f098e88441f9862263010468\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod$08e0515b71182b69329467e1e009a2fd6b1d4c54\$lut for cells of type $lut. Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut. Using template $paramod$136e57387592793f9592847d05ef6a1e5556813e\$lut for cells of type $lut. Using template $paramod$473fcd371d91799964bc73c98ad44aa026e26f19\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut. Using template $paramod$1780b599fad82e57d6459b81ca42390759dd97e1\$lut for cells of type $lut. Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut. Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut. Using template $paramod$466b72af80fcf88ce7333ff3b609da9423cb50a5\$lut for cells of type $lut. Using template $paramod$1084a32ba20e23d315f1f7012d89b04d9c51c87d\$lut for cells of type $lut. Using template $paramod$e18cd61c4880b32578539de46b5e9a7270be8167\$lut for cells of type $lut. Using template $paramod$373a6b2bfb72d8eb78c06f4cafb0bdd8a1118891\$lut for cells of type $lut. Using template $paramod$16773ebb5e5d8dbce266b8a86bb4af4574d61ffd\$lut for cells of type $lut. Using template $paramod$aa80fa079a227cf1e98cdb6bd2973d3412c30daf\$lut for cells of type $lut. Using template $paramod$75f5e4045ec954976867f86242b1a518d44bbe9d\$lut for cells of type $lut. Using template $paramod$803fb2e411cd759897bb32714c4cd91d7f11ca86\$lut for cells of type $lut. Using template $paramod$de04cb9fed08da92a34d101e5e82912c17d40d8e\$lut for cells of type $lut. Using template $paramod$f18573f960aa698bb5df0e9a5dc3a7659aca4c2e\$lut for cells of type $lut. Using template $paramod$c19ac226b2328a9dc00b76bc0a6d1e025c6f4fca\$lut for cells of type $lut. Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut. Using template $paramod$7aa8140c7d6de3160b21e7ff84e0f93f69f7fcc6\$lut for cells of type $lut. Using template $paramod$7172af407489522b2f646d9852a99086208a433b\$lut for cells of type $lut. Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882\$lut for cells of type $lut. Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54\$lut for cells of type $lut. Using template $paramod$3ec07761c84f2572ff2c69e2a76c619b913d3f08\$lut for cells of type $lut. Using template $paramod$8b92de0b0a7e05ded4e30fb9c0976d2e27fb3076\$lut for cells of type $lut. Using template $paramod$256f3f936b752cf569dca900ae92c3ac452c7e57\$lut for cells of type $lut. Using template $paramod$11d98a734fddb972e4bcf061987d6c0007a7bbfa\$lut for cells of type $lut. Using template $paramod$6e6d1d7d25c15e9e30053e6f5f7cf6f746739be7\$lut for cells of type $lut. Using template $paramod$3bcd6f633cdf31745ccb53511038b0b3fe05b606\$lut for cells of type $lut. Using template $paramod$30fd64b647b1ad124867d9d40acc2cf185e45687\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. Using template $paramod$b18a3edb490ff3a49fefc94182a05f36efbdbba2\$lut for cells of type $lut. Using template $paramod$713ee297d84b254aa0757bb9684ac410cdbbf43e\$lut for cells of type $lut. Using template $paramod$26d876869d6ab003366d0470e095daef2ccfcbd7\$lut for cells of type $lut. Using template $paramod$3dc8df1b07971bda7726ddf94f6377e60804ab64\$lut for cells of type $lut. Using template $paramod$fce992df4978ad69e56d150579aa6ba47bc13a78\$lut for cells of type $lut. Using template $paramod$f672f1e5ea7eaf40630014635549af40fc023a51\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. Using template $paramod$6fc23ce09f2013cb9de2228dbcdda21841008f92\$lut for cells of type $lut. Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut. Using template $paramod$12428c4217e00e6257ac0074a74f30fd71809836\$lut for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut. Using template $paramod$7fc325150916e09e21db63cc9672b99a89ef9301\$lut for cells of type $lut. Using template $paramod$7b809938766c3068dc017c276033f224fcfb7189\$lut for cells of type $lut. Using template $paramod$1a570f7c4fa84211cd76bb231e4a70d524ba2b35\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. Using template $paramod$2e9afba29670cc6475874639e7c1b3979c8ebde3\$lut for cells of type $lut. Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut. Using template $paramod$4442214c43c2efcac344587aca281a98e2997069\$lut for cells of type $lut. Using template $paramod$302ba22a83dfb50189674147c5c2626b9e9dab7e\$lut for cells of type $lut. Using template $paramod$a29dc9226a883358910d3758606f48686bda2689\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut. Using template $paramod$5be929872eb8345224eb6e1bba4cf7b750c635ce\$lut for cells of type $lut. Using template $paramod$664d4f6063c66290be5af3d205d1b83dcbdd49a3\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111011 for cells of type $lut. Using template $paramod$de07eb062963514b9c819aacc3e74a1253bffd53\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut. Using template $paramod$46969734f619307bdfb8ca4ad5af273b11115f8d\$lut for cells of type $lut. Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut. Using template $paramod$146d1e96dc4c9681b0c5558dc2dbbbbe4050c7ac\$lut for cells of type $lut. Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut. Using template $paramod$6f9324703e8fcc3b6df2bc2bec54ec19a446ae96\$lut for cells of type $lut. Using template $paramod$4db3f0d067a6794efd5979ea33ffc0ce06e2e75c\$lut for cells of type $lut. Using template $paramod$1f0c66e0f7ce7f846ca5a58367480fa489a7b432\$lut for cells of type $lut. Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut. Using template $paramod$aa2b6ee7fb649252ece267f6fdf05a9261ad10a7\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111101 for cells of type $lut. Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut. Using template $paramod$77b67ef20c955093353b18505577135db4a47988\$lut for cells of type $lut. Using template $paramod$0331e023d83b8009e60defb446ce9fa640b122c7\$lut for cells of type $lut. Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut. Using template $paramod$83a094b6fe9fb738dfff353a8cb39fb4b34c4f40\$lut for cells of type $lut. Using template $paramod$181d49f34bcb31fbb5a26e11f31af35e57e71eb0\$lut for cells of type $lut. Using template $paramod$a05170b3f2d3fcb0bf88d37e810984e864962880\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$8b24407096beec47292ddeb1567a058197a320b9\$lut for cells of type $lut. Using template $paramod$4853050665c020c8d21fb1a749196950a09d9df8\$lut for cells of type $lut. Using template $paramod$c96490ea53f143e0d338d5eb28ea3f028342a691\$lut for cells of type $lut. Using template $paramod$8c18f6892dc7029e886fb843b5b1d530720070e5\$lut for cells of type $lut. Using template $paramod$3416dacc8eaab1f89b3d6b7398df3da766d29ef2\$lut for cells of type $lut. Using template $paramod$9cf976b4f3a576aa2cd6b51304cf5de7fc836fbd\$lut for cells of type $lut. Using template $paramod$571895341b084d34c7674b4aaa647bcb4272d4c8\$lut for cells of type $lut. Using template $paramod$050221686252202c3dcb014324b7b753c760a3f5\$lut for cells of type $lut. Using template $paramod$332a399730bfc61adea04021a76b1c4e4030f37d\$lut for cells of type $lut. Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut. Using template $paramod$52e8ac6fbc5873870a62e236fe0a79280f986c96\$lut for cells of type $lut. Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut. Using template $paramod$47a326ee296feaca60c97add5a2f7670de259bd9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. Using template $paramod$dbdbcb07b9994e498bb1324e5c006c6aa08a7a37\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. Using template $paramod$78c19f250775f804c12bfc774db5542d496e7fb7\$lut for cells of type $lut. Using template $paramod$6382f7860648fdb6f8a8dc690c25a62882cc501b\$lut for cells of type $lut. Using template $paramod$f13784ede300b12a5285177c86c7721a54cf9e12\$lut for cells of type $lut. Using template $paramod$71443dd9ce6d822783b911babf9e9dab228ad54a\$lut for cells of type $lut. Using template $paramod$56e6d8a28a52006bb4e50e077743f0a2163235af\$lut for cells of type $lut. Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f\$lut for cells of type $lut. Using template $paramod$5afdc7428159757eedf89ce514f7efa32b31c8e7\$lut for cells of type $lut. Using template $paramod$193d365ba3260f56de4ca734b1cedcf9dc72302b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. Using template $paramod$fcd39626d04096d97f2b1c9f6aa5234130f8a230\$lut for cells of type $lut. Using template $paramod$55405c184723e0c981beae197deafc4b247b3004\$lut for cells of type $lut. Using template $paramod$5fa057242d435f2451c6bd198ef5ade6e3a77bb8\$lut for cells of type $lut. Using template $paramod$89ca3723ebb4dfdb3c4024f3f04b784a3e88f188\$lut for cells of type $lut. Using template $paramod$a4640096cbef09c4ef8613155a589c40164ac034\$lut for cells of type $lut. Using template $paramod$f52df4b90f46c2ab9e801e1f39516c9cb1bb6ae7\$lut for cells of type $lut. Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut. Using template $paramod$51b138c6601401861f3f66aa30cc9212c6a6619a\$lut for cells of type $lut. Using template $paramod$eaea85d27cc0950ed001348e061727a194f5cf9c\$lut for cells of type $lut. Using template $paramod$589d344cc5a28c53ff5f11cb0e9f352fbbe1ac17\$lut for cells of type $lut. Using template $paramod$068092ddede495d8462ffe530e6d91711913edbc\$lut for cells of type $lut. Using template $paramod$2d70e360329f2b83357618532825d0cf30a325f3\$lut for cells of type $lut. Using template $paramod$b7d5a1d13a95755f80d49e78f7fe57dd63a6cfbe\$lut for cells of type $lut. Using template $paramod$baa9d2fb2d21010939721b85aa9f11effe0b53c4\$lut for cells of type $lut. Using template $paramod$faba0cf60f1c89602d59ba2d491152c8f0d36384\$lut for cells of type $lut. Using template $paramod$9cc51547ab44a72dd506ee5bb84a864365a103da\$lut for cells of type $lut. Using template $paramod$cb0c458b1dc9855edd83a6a9e33b972cb7febd5e\$lut for cells of type $lut. Using template $paramod$03d7da0d848b4f563fda6bc83a08135cc5ded340\$lut for cells of type $lut. Using template $paramod$fb4ed309581bcd972f41afa8566ae8b9812c7f6c\$lut for cells of type $lut. Using template $paramod$793fc28cf61120083daef76d0ad6adfe307204e0\$lut for cells of type $lut. Using template $paramod$8696f458b0bc45d72f187617e991118b6ed26c4f\$lut for cells of type $lut. Using template $paramod$701ea6ba0841e6999295fed3aa14992b0c563e58\$lut for cells of type $lut. Using template $paramod$d08ae3e2fee668f1a68bd32fd012d46d229cb782\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut. Using template $paramod$70f68cc10fbeada9b6fa90c3bb75475e348ca467\$lut for cells of type $lut. Using template $paramod$caad58040116ab75470aaad37ed97fe8e10a8158\$lut for cells of type $lut. Using template $paramod$2c959eb814502b813fb2b3a30c8dfa8d0f5741f3\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut. Using template $paramod$6cafb465f31c34f6bb6b9412b7e75000e2a2081c\$lut for cells of type $lut. Using template $paramod$fc31732417b7be9ad8ea4524b9939a4cc422dcee\$lut for cells of type $lut. Using template $paramod$1754f787ee39c132fd3133b2c8f1c9f0b87503a5\$lut for cells of type $lut. Using template $paramod$150ee00bee81b2fcb159e621f4ef27bccb5ede20\$lut for cells of type $lut. Using template $paramod$c08a774c89ef1ea6ee2ef4d8c3b071eb141d4259\$lut for cells of type $lut. Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d\$lut for cells of type $lut. Using template $paramod$782961deb8dc512aef835b73aa3765da3ab3c15c\$lut for cells of type $lut. Using template $paramod$712505941a295086314c22735153725461a87f4a\$lut for cells of type $lut. Using template $paramod$e332cff882edd417f410bab5fe07a0f88572cce3\$lut for cells of type $lut. Using template $paramod$eabde4761c91679426ef5401ae1b2c95bf56e107\$lut for cells of type $lut. Using template $paramod$400af3cf9da48ed62bc6baa179f42f2eb1e25224\$lut for cells of type $lut. Using template $paramod$4c019fad677a6751d10c7683062ad8483ed51b71\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. Using template $paramod$150b1957dc408afc96e1c1804fffbfdfcb3383c7\$lut for cells of type $lut. Using template $paramod$707701b498a5cd123a043548b93e61e0b6bdc440\$lut for cells of type $lut. Using template $paramod$ba7f31f246a278c41fa0648a6e0512f63185dec0\$lut for cells of type $lut. Using template $paramod$7f7120086b74d2ad6501bbaa30925c183268a1c2\$lut for cells of type $lut. Using template $paramod$5506e3402bfb03b61e61d5a57a0a68d88d352dc9\$lut for cells of type $lut. Using template $paramod$920c30c965b89e85bc6c38e2211cf7b09d4fb168\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut. Using template $paramod$4385b611926e5c0509dba4de58311d325da0ff0d\$lut for cells of type $lut. Using template $paramod$1dbc005c3ca46176ed5f71d3318762a2498d170f\$lut for cells of type $lut. Using template $paramod$f7744fc299c4b6dc315f22eb6110994661b48d3f\$lut for cells of type $lut. Using template $paramod$1bbe3c71927a3b9b5aba8f3be2d11d68d98b1fa9\$lut for cells of type $lut. Using template $paramod$e684e947d725af21226ff9a9896770979345473f\$lut for cells of type $lut. Using template $paramod$27e7ae518734a6f179c4de51337b458b679b09a4\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. Using template $paramod$1f8d11827cfe27dfc297d495f53d8a969cf90bec\$lut for cells of type $lut. Using template $paramod$67d0c806b64ecae62b17b7861304f1258c6a2478\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. Using template $paramod$58df2c605746858c7e53492c8f57d6f1fafa12d2\$lut for cells of type $lut. Using template $paramod$af6bfc66edfa832be553173935a94fd15de7c168\$lut for cells of type $lut. Using template $paramod$c49993c8f2ff2fd8fd7a1dcc4704f7c8f0cdc57f\$lut for cells of type $lut. Using template $paramod$cbb3e819e791efb5f95432887001859d6b8027c2\$lut for cells of type $lut. Using template $paramod$07b1b12ce0305f55108770e958fd02caedfebdf8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut. Using template $paramod$a15fd389a2f54cb7b94707b25934d226e68d9e2e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut. Using template $paramod$adce9c89515a4e83641fc3471eb3c01ec7b082ff\$lut for cells of type $lut. Using template $paramod$a191129d10a368b82781b98ff31865427345b51c\$lut for cells of type $lut. Using template $paramod$7d813eb49700f971f2635a434700eafdfa816bc3\$lut for cells of type $lut. Using template $paramod$faace351d5336ef9147b65874a3ba6a2f4c9f8ee\$lut for cells of type $lut. Using template $paramod$c3b608ea633bffd787b9ead5aebc7111778f670e\$lut for cells of type $lut. Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut. Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut. Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut. Using template $paramod$9928e0d52d25df1c05471cbd9fa782a1bf94b80d\$lut for cells of type $lut. Using template $paramod$2d52a1d6cf603c98ba7b908cd4e344a0536dbeca\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut. Using template $paramod$2645ed3928f2726e8ccb403cb23252de43b617d7\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704\$lut for cells of type $lut. Using template $paramod$e6062a78edaf68ec0dbea59d4c8352dcb2ce0366\$lut for cells of type $lut. Using template $paramod$6df06577fab04385d46871e46644a696e22b7b2f\$lut for cells of type $lut. Using template $paramod$1dc04239bb241758f75df5b1118916486c63ca41\$lut for cells of type $lut. Using template $paramod$a6b2d4693fada6bebbe4480262641915d709d280\$lut for cells of type $lut. Using template $paramod$23d926f9f7f95656466c90957f3caa64701742cf\$lut for cells of type $lut. Using template $paramod$31d0fe9872e147e32329f1888afc564130486200\$lut for cells of type $lut. Using template $paramod$849d013d096d73269ca4beb768f8e399745d37f2\$lut for cells of type $lut. Using template $paramod$d30c4cc53d8a0d157b65f252aa337c124b365147\$lut for cells of type $lut. Using template $paramod$b9cbb0f16a176e4b2e9dbca6aee127ce97922bd2\$lut for cells of type $lut. Using template $paramod$66658cbed86a8310f9b7ba1190d35eff90ee749b\$lut for cells of type $lut. Using template $paramod$6023c671e114c4eb0467aa8a0b08e183f33ec2fd\$lut for cells of type $lut. Using template $paramod$085cb83d0db09780ae5aa544a0f286ba9445143f\$lut for cells of type $lut. Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut. Using template $paramod$e50f56a7028566ddce039783c185b3ecd3c5a571\$lut for cells of type $lut. Using template $paramod$b3a4a16458272670fe99d44d91de9d27aa7c14f3\$lut for cells of type $lut. Using template $paramod$da49ead6f31a43bab2d6c107c254e628a16f3330\$lut for cells of type $lut. Using template $paramod$2e0fd651ab536ddf2afd30af26b1a2532281e83a\$lut for cells of type $lut. Using template $paramod$66fa5f0091ddf0e95fc21f4cc02805ddf33c3024\$lut for cells of type $lut. Using template $paramod$b13a2cd0fbb9ebaeedad35383f0b23ffebc11d94\$lut for cells of type $lut. Using template $paramod$72148f3545efac6f48701d6c21ae5eeb7a5f865b\$lut for cells of type $lut. Using template $paramod$5c36a508e8885449eeca65fa0c02b7154f6a3130\$lut for cells of type $lut. Using template $paramod$57400e123f0147f905d2ec980ae5b64230fc0a43\$lut for cells of type $lut. Using template $paramod$f0de73e203daef8f8580918556298273e538cabc\$lut for cells of type $lut. Using template $paramod$f6cb3fdab41e95c971e90994829351e95bc70e14\$lut for cells of type $lut. Using template $paramod$beae4210b922fc9ba2fcc4008a7474b475e38c50\$lut for cells of type $lut. Using template $paramod$8075729953f49b6cb1b4d863b2fb20da9818d304\$lut for cells of type $lut. Using template $paramod$1180755756a7d9469e1ec1dcea4ba873f7818a53\$lut for cells of type $lut. Using template $paramod$df23d368a6ae8908771963811f5ab56f622887ca\$lut for cells of type $lut. Using template $paramod$5d465bcb0b72d0207b19ca10d090492e09d0263d\$lut for cells of type $lut. Using template $paramod$92c3899764cd8074859d6a5a5b733cffe8a391b3\$lut for cells of type $lut. Using template $paramod$da24d1fb17785734b91c6fc20677d0522f5909da\$lut for cells of type $lut. Using template $paramod$2a4b250d89be3556c74aa0e719a4f6242369d42f\$lut for cells of type $lut. Using template $paramod$57cf7fbf84518d9e7604ec42b59ba9511e1f3caf\$lut for cells of type $lut. Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut. Using template $paramod$ba4b1c9b57f942a38af35848615a2f06189d3bfe\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. Using template $paramod$176a6ceafa512d807921d7dfc76320dfbbfb5fe4\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. Using template $paramod$f94cf08026d21db794b98b1a8efaec5f34ff8975\$lut for cells of type $lut. Using template $paramod$e934877433e628b9aa4b7cb2bee8957bca3e1db5\$lut for cells of type $lut. Using template $paramod$2b2b3565ec13859d2b24f2fa297fa46249270140\$lut for cells of type $lut. Using template $paramod$769bdbbde83614df0f4ab5f54e777ded51bb10ce\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod$19be9597b788c07653b8e254f519518a1572fd5b\$lut for cells of type $lut. Using template $paramod$432f26b811c14bf54c5e87c8670ec65cbcaf38ac\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut. Using template $paramod$4af27add6cf39068c874707706b45040d7cc432b\$lut for cells of type $lut. Using template $paramod$bd6c69bc5b35ecaebc852c0e33740c86577e69c5\$lut for cells of type $lut. Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut. Using template $paramod$afddf753bc06379024ae15bcee2a9be2a1e56428\$lut for cells of type $lut. Using template $paramod$651e836885d95717c36e69441422c3fe04ee5f4d\$lut for cells of type $lut. Using template $paramod$60096d1cdb5f7f55fdf4ed3aab322b5c7375f61e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod$18e50808df562b188523e13714b96fedec6427c1\$lut for cells of type $lut. Using template $paramod$5b4b4ed558983d9f3ab4c896a7a011d129b0db9a\$lut for cells of type $lut. Using template $paramod$70ebb6cf5bc7d63c5c1a98ccefefa2af79e8f2a9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101100 for cells of type $lut. Using template $paramod$4d9437f28ee827cf4006287c53ecaa1266100fca\$lut for cells of type $lut. No more expansions possible. <suppressed ~6655 debug messages> 21.44. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in top. Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71902.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$8600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$8359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$8335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$8249.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8143.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$6884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$8196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$8157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$8157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$8157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$8157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$8151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$8151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$13417.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$7418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$7418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7288.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7401.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$7395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$7395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$7395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$8541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$8541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$8533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$8533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$8533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7765.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$8459.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7728.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$7447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$8001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7996.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$7308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$8088.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$7437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$8308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$7195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7370.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7370.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7370.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7370.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7370.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7370.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7370.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7155.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7155.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7155.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7155.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7155.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7155.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7155.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6874.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6874.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6874.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6874.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6874.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6874.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6988.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$6988.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$7586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$7028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$6947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$6947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$6947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$6917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$6261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$6255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$6255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$6596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71969.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71965.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71965.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$6001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$6001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$6001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$6001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$6047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$6047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$6047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$6047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$6029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$6029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$6029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$6029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$5979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71957.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71957.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$5921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$5921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$5921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$5921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71961.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$5967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$5949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$5949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$5949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$5899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$5884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$5884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$5884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$5884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71992.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$5844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$5844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$5844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$5844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$5804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$5757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72001.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$5640.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5640.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$6210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$6204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$5545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10007.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10023.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10069.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10085.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10095.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10185.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10253.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10442.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10449.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10498.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10704.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10720.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10748.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10788.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10923.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10939.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10958.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$10974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11007.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11023.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11067.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11107.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11123.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11165.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11181.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11232.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11376.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11411.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11465.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11481.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11491.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11498.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11565.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11581.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11625.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11692.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11708.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11784.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11800.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11834.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11943.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11964.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$11973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$11986.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12025.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12071.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12139.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12221.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12285.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12307.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12359.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12381.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12392.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12419.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12426.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12452.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12465.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12488.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12550.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12581.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12591.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12617.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12663.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12679.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12696.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12746.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12769.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12776.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12789.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12812.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12828.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12863.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12874.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12931.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$12943.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12959.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12976.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$12989.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$13005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$13027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$13038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$13070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$13077.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$13100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$13122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$13138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$13176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$13189.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$13214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$13224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$13247.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$13260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$13286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$13307.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$13316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$13329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$13394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$13404.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$13421.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$13443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$13460.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$13476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$13489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$13505.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$13522.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$13547.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$13557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$13580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$13593.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$13615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$13653.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$13666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$5310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5420.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5497.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$5525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71985.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$5545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5799.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72005.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$5583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$5640.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$5687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5725.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5757.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5853.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5888.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$5921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5953.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5971.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$5979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$6001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$6063.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$6146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$5545.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6199.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6359.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8232.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6505.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$6566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6735.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6874.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6884.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$6947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$6953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6988.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7004.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$7014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7155.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7223.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7370.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7386.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$7395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$7401.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7409.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$7418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$7422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$7437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7467.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$7520.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6988.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7671.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$6973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6874.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7696.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7736.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$7247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7773.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$7789.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7437.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7846.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$6953.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7891.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7895.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$7916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$7308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$7986.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$8001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$8046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$8092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8099.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$8151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$8157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$8179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8217.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8241.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$7205.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71994.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$8291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$8299.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$8308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$8314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$8323.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$8330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$8335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8400.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$8407.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8416.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$8430.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$8436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8467.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$8503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8533.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$8541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8577.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$8585.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$8594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8734.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8782.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8834.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8850.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8936.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8971.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9004.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9037.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$9119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9135.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9151.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9167.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$71853$lut$aiger71852$9252.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$9278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9344.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9372.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9395.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9411.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$9506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9541.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9573.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$9602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9684.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9703.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9719.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9873.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9907.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9923.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$9940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$71853$lut$auto$fsm_map.cc:170:map_fsm$1426[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$auto$fsm_map.cc:170:map_fsm$1469[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$9108.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71950.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71884.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71889.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71927.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71892.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71882.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71856.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71893.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71868.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71873.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71878.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71901.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$8245.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$71853$lut$aiger71852$8001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71957.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71965.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$6566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$6240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71981.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$6586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71989.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$71993.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$71853$lut$aiger71852$6146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$71853$lut$aiger71852$7068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Removed 0 unused cells and 7662 unused wires. 21.45. Executing AUTONAME pass. Renamed 153709 objects in module top (216 iterations). <suppressed ~10046 debug messages> 21.46. Executing HIERARCHY pass (managing design hierarchy). 21.46.1. Analyzing design hierarchy.. Top module: \top 21.46.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 21.47. Printing statistics. === top === Number of wires: 4765 Number of wire bits: 12684 Number of public wires: 4765 Number of public wire bits: 12684 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 5996 $_TBUF_ 6 CCU2C 156 L6MUX21 334 LUT4 3741 PFUMX 854 TRELLIS_DPR16X4 544 TRELLIS_FF 361 21.48. Executing CHECK pass (checking for obvious problems). Checking module top... Found and reported 0 problems. 21.49. Executing JSON backend. Warnings: 226 unique messages, 227 total End of script. Logfile hash: 1a06e2f51e, CPU: user 5.76s system 0.08s, MEM: 176.36 MB peak Yosys 0.36+8 (git sha1 fb4cbfa73, clang 10.0.0-4ubuntu1 -fPIC -Os) Time spent: 41% 1x abc9_exe (4 sec), 14% 11x techmap (1 sec), ... [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (NextPNR) [Pipeline] sh + /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --ignore-loops --lpf-allow-unconstrained Info: constraining clock net 'clk' to 25.00 MHz Info: Logic utilisation before packing: Info: Total LUT4s: 7317/43848 16% Info: logic LUTs: 3741/43848 8% Info: carry LUTs: 312/43848 0% Info: RAM LUTs: 2176/ 5481 39% Info: RAMW LUTs: 1088/10962 9% Info: Total DFFs: 361/43848 0% Info: Packing IOs.. Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y Info: pin 'gpios[5]$tr_io' constrained to Bel 'X0/Y23/PIOC'. Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y Info: pin 'gpios[4]$tr_io' constrained to Bel 'X0/Y44/PIOA'. Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y23/PIOA'. Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y Info: pin 'gpios[2]$tr_io' constrained to Bel 'X90/Y23/PIOD'. Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y Info: pin 'gpios[1]$tr_io' constrained to Bel 'X0/Y14/PIOD'. Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y Info: pin 'gpios[0]$tr_io' constrained to Bel 'X0/Y44/PIOB'. Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'. Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'. Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'. Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'. Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'. Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'. Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'. Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'. Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'. Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'. Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'. Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 280 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk_o to global network Info: promoting clock net clk$TRELLIS_IO_IN to global network Info: Checksum: 0x25e46968 Info: Device utilisation: Info: TRELLIS_IO: 18/ 245 7% Info: DCCA: 2/ 56 3% Info: DP16KD: 0/ 108 0% Info: MULT18X18D: 0/ 72 0% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 361/43848 0% Info: TRELLIS_COMB: 7381/43848 16% Info: TRELLIS_RAMW: 544/ 5481 9% Info: Placed 18 cells based on constraints. Info: Creating initial analytic placement for 3200 cells, random placement wirelen = 309861. Info: at initial placer iter 0, wirelen = 2158 Info: at initial placer iter 1, wirelen = 1733 Info: at initial placer iter 2, wirelen = 1694 Info: at initial placer iter 3, wirelen = 1749 Info: Running main analytical placer, max placement attempts per cell = 8623704. Info: at iteration #1, type ALL: wirelen solved = 1895, spread = 44234, legal = 44624; time = 0.21s Info: at iteration #2, type ALL: wirelen solved = 4963, spread = 35666, legal = 36295; time = 0.21s Info: at iteration #3, type ALL: wirelen solved = 6225, spread = 31703, legal = 32443; time = 0.20s Info: at iteration #4, type ALL: wirelen solved = 7856, spread = 29011, legal = 29750; time = 0.19s Info: at iteration #5, type ALL: wirelen solved = 8550, spread = 28366, legal = 29211; time = 0.19s Info: at iteration #6, type ALL: wirelen solved = 9744, spread = 29126, legal = 29803; time = 0.19s Info: at iteration #7, type ALL: wirelen solved = 10766, spread = 27646, legal = 28469; time = 0.19s Info: at iteration #8, type ALL: wirelen solved = 10975, spread = 27692, legal = 28678; time = 0.18s Info: at iteration #9, type ALL: wirelen solved = 12107, spread = 28198, legal = 28805; time = 0.18s Info: at iteration #10, type ALL: wirelen solved = 13114, spread = 26695, legal = 27462; time = 0.18s Info: at iteration #11, type ALL: wirelen solved = 13327, spread = 26262, legal = 27075; time = 0.18s Info: at iteration #12, type ALL: wirelen solved = 13358, spread = 26669, legal = 27445; time = 0.18s Info: at iteration #13, type ALL: wirelen solved = 13740, spread = 26658, legal = 27331; time = 0.18s Info: at iteration #14, type ALL: wirelen solved = 14284, spread = 26848, legal = 27425; time = 0.18s Info: at iteration #15, type ALL: wirelen solved = 14737, spread = 25928, legal = 26696; time = 0.18s Info: at iteration #16, type ALL: wirelen solved = 14551, spread = 25400, legal = 26173; time = 0.18s Info: at iteration #17, type ALL: wirelen solved = 14874, spread = 25681, legal = 26506; time = 0.18s Info: at iteration #18, type ALL: wirelen solved = 15237, spread = 24657, legal = 25639; time = 0.18s Info: at iteration #19, type ALL: wirelen solved = 15096, spread = 25098, legal = 25821; time = 0.17s Info: at iteration #20, type ALL: wirelen solved = 15432, spread = 24970, legal = 25807; time = 0.17s Info: at iteration #21, type ALL: wirelen solved = 15439, spread = 26081, legal = 26937; time = 0.18s Info: at iteration #22, type ALL: wirelen solved = 16162, spread = 25093, legal = 25846; time = 0.17s Info: at iteration #23, type ALL: wirelen solved = 15999, spread = 25057, legal = 25737; time = 0.17s Info: HeAP Placer Time: 6.80s Info: of which solving equations: 3.95s Info: of which spreading cells: 0.49s Info: of which strict legalisation: 0.16s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 14682, wirelen = 25639 Info: at iteration #5: temp = 0.000000, timing cost = 10765, wirelen = 21817 Info: at iteration #10: temp = 0.000000, timing cost = 13153, wirelen = 20868 Info: at iteration #15: temp = 0.000000, timing cost = 11445, wirelen = 20521 Info: at iteration #20: temp = 0.000000, timing cost = 10192, wirelen = 20412 Info: at iteration #23: temp = 0.000000, timing cost = 9952, wirelen = 20369 Info: SA placement time 17.65s Info: Max frequency for clock '$glbnet$clk_o': 31.34 MHz (PASS at 12.00 MHz) Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 146.33 MHz (PASS at 25.00 MHz) Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 12.18 ns Info: Max delay <async> -> posedge $glbnet$clk_o : 14.56 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 10.24 ns Info: Max delay posedge $glbnet$clk_o -> <async> : 16.24 ns Info: Slack histogram: Info: legend: * represents 89 endpoint(s) Info: + represents [1,89) endpoint(s) Info: [ 33166, 35637) |+ Info: [ 35637, 38108) |+ Info: [ 38108, 40579) |+ Info: [ 40579, 43050) | Info: [ 43050, 45521) | Info: [ 45521, 47992) | Info: [ 47992, 50463) | Info: [ 50463, 52934) |+ Info: [ 52934, 55405) |+ Info: [ 55405, 57876) |+ Info: [ 57876, 60347) |******+ Info: [ 60347, 62818) |******************+ Info: [ 62818, 65289) |************************************************+ Info: [ 65289, 67760) |************************************************************ Info: [ 67760, 70231) |*****+ Info: [ 70231, 72702) |**+ Info: [ 72702, 75173) |*****+ Info: [ 75173, 77644) |***+ Info: [ 77644, 80115) |**+ Info: [ 80115, 82586) |+ Info: Checksum: 0x017777a4 Info: Routing globals... Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 Info: routing clock net $glbnet$clk_o using global 1 Info: Routing.. Info: Setting up routing queue. Info: Routing 35544 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 84 915 | 84 915 | 34672| 0.60 0.60| Info: 2000 | 289 1710 | 205 795 | 34091| 0.18 0.79| Info: 3000 | 523 2476 | 234 766 | 33609| 0.19 0.98| Info: 4000 | 729 3270 | 206 794 | 33191| 0.18 1.16| Info: 5000 | 896 4103 | 167 833 | 32767| 0.19 1.34| Info: 6000 | 1117 4882 | 221 779 | 32414| 0.19 1.54| Info: 7000 | 1273 5726 | 156 844 | 31816| 0.19 1.73| Info: 8000 | 1500 6499 | 227 773 | 31384| 0.18 1.91| Info: 9000 | 1678 7321 | 178 822 | 30877| 0.21 2.12| Info: 10000 | 1859 8140 | 181 819 | 30561| 0.19 2.31| Info: 11000 | 2013 8986 | 154 846 | 30758| 0.18 2.49| Info: 12000 | 2211 9788 | 198 802 | 30617| 0.22 2.71| Info: 13000 | 2332 10667 | 121 879 | 30226| 0.18 2.89| Info: 14000 | 2483 11516 | 151 849 | 29922| 0.19 3.07| Info: 15000 | 2657 12342 | 174 826 | 29409| 0.17 3.24| Info: 16000 | 2847 13152 | 190 810 | 28853| 0.18 3.42| Info: 17000 | 2994 14005 | 147 853 | 28477| 0.18 3.60| Info: 18000 | 3197 14802 | 203 797 | 28278| 0.21 3.81| Info: 19000 | 3358 15641 | 161 839 | 27707| 0.17 3.98| Info: 20000 | 3461 16538 | 103 897 | 27382| 0.16 4.14| Info: 21000 | 3614 17385 | 153 847 | 27354| 0.17 4.32| Info: 22000 | 3823 18176 | 209 791 | 26889| 0.21 4.52| Info: 23000 | 4023 18976 | 200 800 | 26472| 0.20 4.72| Info: 24000 | 4222 19777 | 199 801 | 25924| 0.19 4.91| Info: 25000 | 4360 20639 | 138 862 | 25349| 0.17 5.08| Info: 26000 | 4608 21391 | 248 752 | 25018| 0.20 5.28| Info: 27000 | 4795 22204 | 187 813 | 24452| 0.18 5.46| Info: 28000 | 4962 23037 | 167 833 | 23966| 0.18 5.63| Info: 29000 | 5185 23814 | 223 777 | 23754| 0.20 5.84| Info: 30000 | 5405 24594 | 220 780 | 23400| 0.20 6.04| Info: 31000 | 5655 25344 | 250 750 | 23059| 0.20 6.25| Info: 32000 | 5882 26117 | 227 773 | 22731| 0.19 6.44| Info: 33000 | 6093 26906 | 211 789 | 22488| 0.21 6.65| Info: 34000 | 6314 27685 | 221 779 | 21930| 0.20 6.85| Info: 35000 | 6530 28469 | 216 784 | 21673| 0.20 7.06| Info: 36000 | 6805 29194 | 275 725 | 21216| 0.19 7.25| Info: 37000 | 6981 30018 | 176 824 | 21092| 0.20 7.45| Info: 38000 | 7116 30883 | 135 865 | 21009| 0.22 7.67| Info: 39000 | 7334 31665 | 218 782 | 20696| 0.22 7.89| Info: 40000 | 7613 32386 | 279 721 | 20223| 0.21 8.10| Info: 41000 | 7857 33142 | 244 756 | 19659| 0.20 8.30| Info: 42000 | 8148 33851 | 291 709 | 19626| 0.24 8.54| Info: 43000 | 8342 34657 | 194 806 | 19306| 0.22 8.76| Info: 44000 | 8574 35425 | 232 768 | 19192| 0.20 8.97| Info: 45000 | 8890 36109 | 316 684 | 18802| 0.21 9.18| Info: 46000 | 9149 36850 | 259 741 | 18335| 0.20 9.38| Info: 47000 | 9490 37509 | 341 659 | 18030| 0.23 9.61| Info: 48000 | 9772 38227 | 282 718 | 17766| 0.23 9.84| Info: 49000 | 10144 38855 | 372 628 | 17373| 0.23 10.07| Info: 50000 | 10560 39439 | 416 584 | 16951| 0.22 10.29| Info: 51000 | 10979 40020 | 419 581 | 16607| 0.23 10.52| Info: 52000 | 11389 40610 | 410 590 | 16188| 0.23 10.74| Info: 53000 | 11708 41291 | 319 681 | 15977| 0.23 10.98| Info: 54000 | 12156 41843 | 448 552 | 15675| 0.24 11.22| Info: 55000 | 12671 42328 | 515 485 | 15430| 0.25 11.47| Info: 56000 | 13069 42930 | 398 602 | 15220| 0.24 11.71| Info: 57000 | 13538 43461 | 469 531 | 14954| 0.25 11.96| Info: 58000 | 13917 44082 | 379 621 | 14620| 0.23 12.18| Info: 59000 | 14421 44578 | 504 496 | 14353| 0.25 12.43| Info: 60000 | 14895 45104 | 474 526 | 14104| 0.25 12.68| Info: 61000 | 15415 45584 | 520 480 | 13836| 0.25 12.93| Info: 62000 | 15946 46053 | 531 469 | 13636| 0.25 13.18| Info: 63000 | 16508 46491 | 562 438 | 13542| 0.25 13.42| Info: 64000 | 16841 47158 | 333 667 | 13336| 0.25 13.67| Info: 65000 | 17445 47554 | 604 396 | 13076| 0.24 13.91| Info: 66000 | 18038 47961 | 593 407 | 12898| 0.25 14.16| Info: 67000 | 18586 48413 | 548 452 | 12731| 0.26 14.42| Info: 68000 | 19135 48864 | 549 451 | 12548| 0.25 14.67| Info: 69000 | 19645 49354 | 510 490 | 12299| 0.24 14.91| Info: 70000 | 20160 49839 | 515 485 | 12114| 0.25 15.17| Info: 71000 | 20581 50394 | 421 555 | 11924| 0.24 15.41| Info: 72000 | 21042 50930 | 461 536 | 11670| 0.27 15.67| Info: 73000 | 21419 51544 | 377 614 | 11574| 0.24 15.91| Info: 74000 | 21965 51942 | 546 398 | 11270| 0.23 16.14| Info: 75000 | 22517 52304 | 552 362 | 10896| 0.22 16.36| Info: 76000 | 23031 52737 | 514 433 | 10711| 0.26 16.62| Info: 77000 | 23571 53160 | 540 423 | 10506| 0.26 16.88| Info: 78000 | 24078 53558 | 507 398 | 10298| 0.24 17.12| Info: 79000 | 24529 54070 | 451 512 | 9958| 0.23 17.35| Info: 80000 | 25106 54430 | 577 360 | 9633| 0.24 17.59| Info: 81000 | 25417 55113 | 311 683 | 9601| 0.29 17.88| Info: 82000 | 25868 55637 | 451 524 | 9408| 0.26 18.14| Info: 83000 | 26172 56316 | 304 679 | 9379| 0.25 18.39| Info: 84000 | 26583 56880 | 411 564 | 8983| 0.24 18.63| Info: 85000 | 27024 57403 | 441 523 | 8641| 0.23 18.86| Info: 86000 | 27267 58133 | 243 730 | 8539| 0.22 19.08| Info: 87000 | 27459 58868 | 192 735 | 7809| 0.13 19.21| Info: 88000 | 27522 59764 | 63 896 | 6903| 0.09 19.30| Info: 89000 | 27540 60729 | 18 965 | 5961| 0.08 19.38| Info: 90000 | 27551 61715 | 11 986 | 4984| 0.07 19.45| Info: 91000 | 27565 62695 | 14 980 | 3999| 0.07 19.52| Info: 92000 | 27570 63690 | 5 995 | 3006| 0.07 19.60| Info: 93000 | 27614 64646 | 44 956 | 2068| 0.09 19.69| Info: 94000 | 27770 65471 | 156 825 | 1336| 0.15 19.84| Info: 95000 | 27921 66293 | 151 822 | 539| 0.14 19.98| Info: 95781 | 28015 66728 | 94 435 | 0| 0.19 20.17| Info: Routing complete. Info: Router1 time 20.17s Info: Checksum: 0x93fef7e2 Info: Critical path report for clock '$glbnet$clk_o' (posedge -> posedge): Info: curr total Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q.Q Info: 1.4 2.0 Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_1_D_LUT4_Z_D_LUT4_Z_C[0] (9,9) -> (16,8) Info: Sink SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.A Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:43.3-50.2 Info: Risco-5/src/core/core.v:97.14-114.2 Info: Risco-5/src/core/control_unit.v:48.11-48.16 Info: Risco-5/src/peripheral/soc.v:28.3-36.2 Info: 0.2 2.2 Source SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.F Info: 1.6 3.8 Net SOC.Memory.address_LUT4_Z_C_LUT4_Z_D[2] (16,8) -> (21,13) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_LUT4_Z.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 4.0 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_LUT4_Z.F Info: 1.5 5.5 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0 (21,13) -> (19,6) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.B Info: 0.4 5.9 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO Info: 0.0 5.9 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (19,6) -> (19,6) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI Info: 0.0 5.9 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO Info: 0.0 5.9 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (19,6) -> (20,6) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:43.3-50.2 Info: Risco-5/src/peripheral/bus.v:54.5-54.37 Info: Risco-5/src/peripheral/soc.v:51.5-81.2 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 6.0 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO Info: 0.0 6.0 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (20,6) -> (20,6) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI Info: 0.0 6.0 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO Info: 0.0 6.0 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (20,6) -> (20,6) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:43.3-50.2 Info: Risco-5/src/peripheral/bus.v:54.5-54.37 Info: Risco-5/src/peripheral/soc.v:51.5-81.2 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 6.1 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO Info: 0.0 6.1 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (20,6) -> (20,6) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI Info: 0.0 6.1 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO Info: 0.0 6.1 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (20,6) -> (20,6) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:43.3-50.2 Info: Risco-5/src/peripheral/bus.v:54.5-54.37 Info: Risco-5/src/peripheral/soc.v:51.5-81.2 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 6.2 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO Info: 0.0 6.2 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (20,6) -> (20,6) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI Info: 0.0 6.2 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO Info: 0.0 6.2 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (20,6) -> (20,6) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:43.3-50.2 Info: Risco-5/src/peripheral/bus.v:54.5-54.37 Info: Risco-5/src/peripheral/soc.v:51.5-81.2 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 6.2 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO Info: 0.0 6.2 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (20,6) -> (20,6) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI Info: 0.0 6.2 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO Info: 0.0 6.2 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (20,6) -> (21,6) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:43.3-50.2 Info: Risco-5/src/peripheral/bus.v:54.5-54.37 Info: Risco-5/src/peripheral/soc.v:51.5-81.2 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 6.3 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO Info: 0.0 6.3 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (21,6) -> (21,6) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI Info: 0.0 6.3 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO Info: 0.0 6.3 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (21,6) -> (21,6) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:43.3-50.2 Info: Risco-5/src/peripheral/bus.v:54.5-54.37 Info: Risco-5/src/peripheral/soc.v:51.5-81.2 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 6.4 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO Info: 0.0 6.4 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (21,6) -> (21,6) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI Info: 0.0 6.4 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO Info: 0.0 6.4 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (21,6) -> (21,6) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:43.3-50.2 Info: Risco-5/src/peripheral/bus.v:54.5-54.37 Info: Risco-5/src/peripheral/soc.v:51.5-81.2 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 6.4 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO Info: 0.0 6.4 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (21,6) -> (21,6) Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI Info: 0.0 6.4 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO Info: 0.0 6.4 Net $nextpnr_CCU2C_17$CIN (21,6) -> (21,6) Info: Sink $nextpnr_CCU2C_17$CCU2_COMB0.FCI Info: 0.4 6.9 Source $nextpnr_CCU2C_17$CCU2_COMB0.F Info: 2.3 9.2 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B0_CCU2C_B0_COUT (21,6) -> (18,31) Info: Sink SOC.Memory.address_LUT4_Z_2.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 9.4 Source SOC.Memory.address_LUT4_Z_2.F Info: 3.1 12.5 Net SOC.slave_address[3] (18,31) -> (25,6) Info: Sink SOC.Memory.memory.0.119$DPRAM_COMB3.B Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:43.3-50.2 Info: Risco-5/src/peripheral/soc.v:21.5-21.18 Info: 0.2 12.7 Source SOC.Memory.memory.0.119$DPRAM_COMB3.F Info: 0.9 13.6 Net SOC.Memory.memory.0.79_DO_2[2] (25,6) -> (27,6) Info: Sink SOC.Memory.memory.0.71_DO_LUT4_Z.C Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 13.8 Source SOC.Memory.memory.0.71_DO_LUT4_Z.F Info: 0.7 14.5 Net SOC.Memory.memory.0.71_DO[4] (27,6) -> (27,7) Info: Sink SOC.Memory.memory.0.111_DO_PFUMX_Z_BLUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 14.7 Source SOC.Memory.memory.0.111_DO_PFUMX_Z_BLUT_LUT4_Z.OFX Info: 0.5 15.2 Net SOC.Memory.memory.0.111_DO[3] (27,7) -> (27,5) Info: Sink SOC.Memory.memory.0.111_DO_LUT4_C.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 15.5 Source SOC.Memory.memory.0.111_DO_LUT4_C.F Info: 1.2 16.6 Net SOC.Memory.memory.0.7_DO_LUT4_C_Z[3] (27,5) -> (29,4) Info: Sink SOC.Memory.memory.0.7_DO_LUT4_C_Z_LUT4_A.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 16.9 Source SOC.Memory.memory.0.7_DO_LUT4_C_Z_LUT4_A.F Info: 0.5 17.3 Net SOC.Core.read_data_LUT4_Z_23_C_LUT4_Z_1_D_LUT4_Z_B[3] (29,4) -> (29,6) Info: Sink SOC.Core.read_data_LUT4_Z_23_C_LUT4_Z_1_D_LUT4_Z.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 17.6 Source SOC.Core.read_data_LUT4_Z_23_C_LUT4_Z_1_D_LUT4_Z.F Info: 1.0 18.6 Net SOC.Core.read_data_LUT4_Z_23_C_LUT4_Z_1_D[2] (29,6) -> (27,12) Info: Sink SOC.Core.read_data_LUT4_Z_23_C_LUT4_Z_1.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 18.8 Source SOC.Core.read_data_LUT4_Z_23_C_LUT4_Z_1.F Info: 0.6 19.4 Net SOC.Core.read_data_LUT4_Z_23_C[3] (27,12) -> (27,12) Info: Sink SOC.Core.read_data_LUT4_Z_23.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 19.7 Source SOC.Core.read_data_LUT4_Z_23.F Info: 1.6 21.2 Net SOC.read_data[31] (27,12) -> (12,13) Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q.M Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:43.3-50.2 Info: Risco-5/src/peripheral/soc.v:20.34-20.43 Info: 0.0 21.2 Setup SOC.Core.instruction_register_TRELLIS_FF_Q.M Info: 4.5 ns logic, 16.7 ns routing Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): Info: curr total Info: 0.5 0.5 Source ClkDivider.clk_counter_TRELLIS_FF_Q_27.Q Info: 1.2 1.7 Net ClkDivider.clk_counter[4] (47,3) -> (48,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.B Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:15.3-24.2 Info: Risco-5/debug/clk_divider.v:17.26-17.37 Info: 0.4 2.1 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: 0.0 2.1 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (48,2) -> (48,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: 0.0 2.1 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: 0.0 2.1 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (48,2) -> (48,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:15.3-24.2 Info: Risco-5/debug/clk_divider.v:48.12-48.38 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 2.2 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: 0.0 2.2 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (48,2) -> (48,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: 0.0 2.2 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: 0.0 2.2 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (48,2) -> (48,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:15.3-24.2 Info: Risco-5/debug/clk_divider.v:48.12-48.38 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 2.3 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: 0.0 2.3 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (48,2) -> (48,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: 0.0 2.3 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: 0.0 2.3 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (48,2) -> (49,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:15.3-24.2 Info: Risco-5/debug/clk_divider.v:48.12-48.38 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 2.3 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: 0.0 2.3 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (49,2) -> (49,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: 0.0 2.3 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: 0.0 2.3 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (49,2) -> (49,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:15.3-24.2 Info: Risco-5/debug/clk_divider.v:48.12-48.38 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 2.4 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: 0.0 2.4 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (49,2) -> (49,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: 0.0 2.4 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: 0.0 2.4 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (49,2) -> (49,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:15.3-24.2 Info: Risco-5/debug/clk_divider.v:48.12-48.38 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 2.5 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: 0.0 2.5 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (49,2) -> (49,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: 0.0 2.5 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: 0.0 2.5 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (49,2) -> (49,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:15.3-24.2 Info: Risco-5/debug/clk_divider.v:48.12-48.38 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 2.5 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: 0.0 2.5 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (49,2) -> (49,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: 0.0 2.5 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: 0.0 2.5 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (49,2) -> (50,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:15.3-24.2 Info: Risco-5/debug/clk_divider.v:48.12-48.38 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 2.6 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: 0.0 2.6 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (50,2) -> (50,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: 0.0 2.6 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: 0.0 2.6 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (50,2) -> (50,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:15.3-24.2 Info: Risco-5/debug/clk_divider.v:48.12-48.38 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 2.7 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: 0.0 2.7 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (50,2) -> (50,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: 0.0 2.7 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: 0.0 2.7 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (50,2) -> (50,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:15.3-24.2 Info: Risco-5/debug/clk_divider.v:48.12-48.38 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (50,2) -> (50,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: 0.0 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (50,2) -> (50,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:15.3-24.2 Info: Risco-5/debug/clk_divider.v:48.12-48.38 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (50,2) -> (50,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: 0.0 2.8 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: 0.0 2.8 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (50,2) -> (51,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:15.3-24.2 Info: Risco-5/debug/clk_divider.v:48.12-48.38 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 2.9 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: 0.0 2.9 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (51,2) -> (51,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: 0.0 2.9 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: 0.0 2.9 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (51,2) -> (51,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:15.3-24.2 Info: Risco-5/debug/clk_divider.v:48.12-48.38 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 3.0 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO Info: 0.0 3.0 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (51,2) -> (51,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI Info: 0.0 3.0 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO Info: 0.0 3.0 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN (51,2) -> (51,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:15.3-24.2 Info: Risco-5/debug/clk_divider.v:48.12-48.38 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.1 3.0 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO Info: 0.0 3.0 Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (51,2) -> (51,2) Info: Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI Info: 0.0 3.0 Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO Info: 0.0 3.0 Net $nextpnr_CCU2C_11$CIN (51,2) -> (51,2) Info: Sink $nextpnr_CCU2C_11$CCU2_COMB0.FCI Info: 0.4 3.5 Source $nextpnr_CCU2C_11$CCU2_COMB0.F Info: 0.5 4.0 Net reset_LUT4_B_C_LUT4_Z_D (51,2) -> (51,4) Info: Sink reset_LUT4_B_C_LUT4_Z.D Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:15.3-24.2 Info: Risco-5/debug/clk_divider.v:48.12-48.38 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4 Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13 Info: 0.2 4.2 Source reset_LUT4_B_C_LUT4_Z.F Info: 0.7 4.9 Net reset_LUT4_B_C[1] (51,4) -> (49,4) Info: Sink reset_LUT4_B.C Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 5.1 Source reset_LUT4_B.F Info: 0.7 5.8 Net reset_LUT4_B_Z (49,4) -> (50,3) Info: Sink ClkDivider.clk_counter_TRELLIS_FF_Q_9.LSR Info: 0.4 6.2 Setup ClkDivider.clk_counter_TRELLIS_FF_Q_9.LSR Info: 3.2 ns logic, 3.0 ns routing Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': Info: curr total Info: 0.0 0.0 Source reset$tr_io.O Info: 4.0 4.0 Net reset$TRELLIS_IO_IN (0,29) -> (49,4) Info: Sink reset_LUT4_B.B Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 4.2 Source reset_LUT4_B.F Info: 0.7 4.9 Net reset_LUT4_B_Z (49,4) -> (50,3) Info: Sink ClkDivider.clk_counter_TRELLIS_FF_Q_9.LSR Info: 0.4 5.3 Setup ClkDivider.clk_counter_TRELLIS_FF_Q_9.LSR Info: 0.7 ns logic, 4.7 ns routing Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk_o': Info: curr total Info: 0.0 0.0 Source gpios[2]$tr_io.O Info: 5.0 5.0 Net gpios[2]$TRELLIS_IO_IN (90,23) -> (8,23) Info: Sink SOC.GPIOS.Gpios[2].direction_LUT4_B.A Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:7.16-7.21 Info: 0.2 5.2 Source SOC.GPIOS.Gpios[2].direction_LUT4_B.F Info: 0.0 5.2 Net SOC.GPIOS.Gpios[2].direction_LUT4_B_Z (8,23) -> (8,23) Info: Sink SOC.GPIOS.Gpios[2].direction_LUT4_B_Z_PFUMX_ALUT_BLUT_LUT4_Z.F1 Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24 Info: 0.2 5.4 Source SOC.GPIOS.Gpios[2].direction_LUT4_B_Z_PFUMX_ALUT_BLUT_LUT4_Z.OFX Info: 1.2 6.6 Net SOC.Core.read_data_LUT4_Z_26_C[2] (8,23) -> (7,15) Info: Sink SOC.Core.read_data_LUT4_Z_26.C Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 6.9 Source SOC.Core.read_data_LUT4_Z_26.F Info: 0.5 7.3 Net SOC.read_data[2] (7,15) -> (8,15) Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_29.M Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:43.3-50.2 Info: Risco-5/src/peripheral/soc.v:20.34-20.43 Info: 0.0 7.3 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_29.M Info: 0.6 ns logic, 6.7 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>': Info: curr total Info: 0.5 0.5 Source ClkDivider.clk_o_auto_TRELLIS_FF_Q.Q Info: 2.1 2.6 Net clk_o (48,4) -> (60,20) Info: Sink led_LUT4_Z_6.D Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:10.6-10.11 Info: 0.2 2.8 Source led_LUT4_Z_6.F Info: 2.3 5.2 Net led[7]$TRELLIS_IO_OUT (60,20) -> (90,20) Info: Sink led[7]$tr_io.I Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:6.22-6.25 Info: 0.8 ns logic, 4.4 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk_o' -> '<async>': Info: curr total Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_29.Q Info: 3.9 4.4 Net SOC.Leds.data[2] (8,23) -> (55,36) Info: Sink led_LUT4_Z_7.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 4.7 Source led_LUT4_Z_7.F Info: 3.2 7.9 Net led[2]$TRELLIS_IO_OUT (55,36) -> (90,44) Info: Sink led[2]$tr_io.I Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:6.22-6.25 Info: 0.8 ns logic, 7.1 ns routing Info: Max frequency for clock '$glbnet$clk_o': 47.12 MHz (PASS at 12.00 MHz) Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 161.29 MHz (PASS at 25.00 MHz) Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.31 ns Info: Max delay <async> -> posedge $glbnet$clk_o : 7.35 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 5.17 ns Info: Max delay posedge $glbnet$clk_o -> <async> : 7.90 ns Info: Slack histogram: Info: legend: * represents 153 endpoint(s) Info: + represents [1,153) endpoint(s) Info: [ 33800, 36230) |+ Info: [ 36230, 38660) |+ Info: [ 38660, 41090) |+ Info: [ 41090, 43520) | Info: [ 43520, 45950) | Info: [ 45950, 48380) | Info: [ 48380, 50810) | Info: [ 50810, 53240) | Info: [ 53240, 55670) | Info: [ 55670, 58100) | Info: [ 58100, 60530) | Info: [ 60530, 62960) |+ Info: [ 62960, 65390) |+ Info: [ 65390, 67820) |+ Info: [ 67820, 70250) |************+ Info: [ 70250, 72680) |************************************************************ Info: [ 72680, 75110) |********+ Info: [ 75110, 77540) |***+ Info: [ 77540, 79970) |***+ Info: [ 79970, 82400) |*+ Info: Program finished normally. [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (ECPPACK) [Pipeline] sh + /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Flash) [Pipeline] parallel [Pipeline] { (Branch: openFPGAloader ECP5) [Pipeline] { (Branch: openFPGAloader Tangnano 20k) [Pipeline] stage [Pipeline] { (openFPGAloader ECP5) [Pipeline] stage [Pipeline] { (openFPGAloader Tangnano 20k) [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] lock Trying to acquire lock on [ecp5] Resource [ecp5] did not exist. Created. Lock acquired on [ecp5] [Pipeline] { [Pipeline] lock Trying to acquire lock on [tangnano20k] Resource [tangnano20k] did not exist. Created. Lock acquired on [tangnano20k] [Pipeline] { [Pipeline] echo FPGA ECP5 Broqueada [Pipeline] sh [Pipeline] echo FPGA TangNano Broqueada [Pipeline] sh + /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit Found 1 compatible device: 0x0d28 0x0204 0x3 DAPLink CMSIS-DAP Open file: DONE Parse file: DONE Enable configuration: DONE SRAM erase: DONE + echo gravando na tang nano gravando na tang nano [Pipeline] } Lock released on resource [tangnano20k] [Pipeline] // lock [Pipeline] } [Pipeline] // script [Pipeline] } [Pipeline] // stage [Pipeline] } Loading: [====== ] 10.52% Loading: [=========== ] 21.04% Loading: [================ ] 31.56% Loading: [====================== ] 42.08% Loading: [=========================== ] 52.60% Loading: [================================ ] 63.12% Loading: [===================================== ] 73.63% Loading: [=========================================== ] 84.15% Loading: [================================================ ] 94.67% Loading: [==================================================] 100.00% Done Disable configuration: DONE [Pipeline] } Lock released on resource [ecp5] [Pipeline] // lock [Pipeline] } [Pipeline] // script [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Testes) [Pipeline] parallel [Pipeline] { (Branch: ECP5 - Testes) [Pipeline] { (Branch: TangNano - Testes) [Pipeline] stage [Pipeline] { (ECP5 - Testes) [Pipeline] stage [Pipeline] { (TangNano - Testes) [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] echo Rodando teste na ECP5 [Pipeline] lock Trying to acquire lock on [ecp5] Resource [ecp5] did not exist. Created. Lock acquired on [ecp5] [Pipeline] { [Pipeline] echo Rodando teste na tang nano [Pipeline] lock Trying to acquire lock on [tangnano20k] Resource [tangnano20k] did not exist. Created. Lock acquired on [tangnano20k] [Pipeline] { [Pipeline] echo FPGA ECP5 Broqueada [Pipeline] sh [Pipeline] echo FPGA TangNano Broqueada [Pipeline] sh + echo testando na ecp5 testando na ecp5 [Pipeline] } Lock released on resource [ecp5] + echo testando na tang nano testando na tang nano [Pipeline] // lock [Pipeline] echo ECP5 liberada [Pipeline] } [Pipeline] } Lock released on resource [tangnano20k] [Pipeline] // script [Pipeline] // lock [Pipeline] } [Pipeline] echo TangNano liberada [Pipeline] } [Pipeline] // stage [Pipeline] // script [Pipeline] } [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline Finished: SUCCESS