Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date         : Sat Jul  4 01:49:58 2026
| Host         : 685a421e500f running 64-bit unknown
| Command      : report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
| Design       : fpga_top
| Device       : xc7a100t
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |   106 |
|    Minimum number of control sets                        |   106 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |   115 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |   106 |
| >= 0 to < 4        |     2 |
| >= 4 to < 6        |    10 |
| >= 6 to < 8        |     2 |
| >= 8 to < 10       |     9 |
| >= 10 to < 12      |     4 |
| >= 12 to < 14      |     3 |
| >= 14 to < 16      |     0 |
| >= 16              |    76 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |              11 |            8 |
| No           | No                    | Yes                    |            3233 |         1942 |
| No           | Yes                   | No                     |             149 |           57 |
| Yes          | No                    | No                     |             199 |           69 |
| Yes          | No                    | Yes                    |            1818 |         1406 |
| Yes          | Yes                   | No                     |             539 |          196 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+----------------+---------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+
|  Clock Signal  |                            Enable Signal                            |                       Set/Reset Signal                       | Slice Load Count | Bel Load Count | Bels / Slice |
+----------------+---------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+
|  clk_IBUF_BUFG |                                                                     |                                                              |                1 |              1 |         1.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                    | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_1_n_0             |                1 |              1 |         1.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_tx/E[0]                               |                                                              |                1 |              4 |         4.00 |
|  clk_core      |                                                                     |                                                              |                4 |              4 |         1.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_rx/next_bit                           | ptop/u_Controller/Uart/i_uart_rx/bit_counter[3]_i_1_n_0      |                1 |              4 |         4.00 |
|  clk_o_BUFG    | ResetBootSystem/counter                                             | ResetBootSystem/counter[3]_i_1__0_n_0                        |                2 |              4 |         2.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_2__0_n_0          | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_1__0_n_0   |                1 |              4 |         4.00 |
|  clk_core      | ptop/u_ssrv_top/gen_mul[2].i_mul/calc_para0                         | ptop/rst                                                     |                5 |              5 |         1.00 |
|  clk_core      | ptop/u_ssrv_top/gen_mul[1].i_mul/calc_para0                         | ptop/rst                                                     |                5 |              5 |         1.00 |
|  clk_core      | ptop/u_ssrv_top/i_lsu/lsu_ready0                                    | ptop/rst                                                     |                3 |              5 |         1.67 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/return_state                          | ResetBootSystem/rst_o_reg_0                                  |                3 |              5 |         1.67 |
|  clk_core      | ptop/u_ssrv_top/gen_mul[0].i_mul/calc_para0                         | ptop/rst                                                     |                5 |              5 |         1.00 |
|  clk_o_BUFG    |                                                                     |                                                              |                3 |              6 |         2.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_tx/data_to_send[6]_i_1_n_0            | ResetBootSystem/rst_o_reg_0                                  |                2 |              7 |         3.50 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/tx_fifo/FSM_sequential_state_write_reg[2][0] | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/uart_tx_en                                   | ResetBootSystem/rst_o_reg_0                                  |                3 |              8 |         2.67 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_rx/recieved_data0                     | ptop/u_Controller/Uart/i_uart_rx/recieved_data[7]_i_1_n_0    |                3 |              8 |         2.67 |
|  clk_core      | ptop/u_ssrv_top/i_bits/req_sent_reg[0]                              | ptop/rst                                                     |                8 |              8 |         1.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_rx/E[0]                               | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_rx/uart_rx_data[7]_i_1_n_0            | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/accumulator[7]_i_1_n_0                | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/counter                               | ResetBootSystem/rst_o_reg_0                                  |                3 |              8 |         2.67 |
|  clk_core      | ptop/u_Controller/Interpreter/FSM_onehot_state_reg[7][0]            |                                                              |                2 |              9 |         4.50 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_rx/cycle_counter0                     | ptop/u_Controller/Uart/i_uart_rx/cycle_counter[9]_i_1__0_n_0 |                3 |             10 |         3.33 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                    | ResetBootSystem/SR[0]                                        |                3 |             10 |         3.33 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/tx_fifo/read_ptr[2]_i_1_n_0                  | ResetBootSystem/rst_o_reg_0                                  |                3 |             11 |         3.67 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/rx_fifo/read_ptr[2]_i_1__0_n_0               | ResetBootSystem/rst_o_reg_0                                  |                4 |             11 |         2.75 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/tx_fifo/memory_reg_0_7_0_5_i_1_n_0           |                                                              |                2 |             12 |         6.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address[31]_i_1_n_0                   |                                                              |                5 |             12 |         2.40 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/rx_fifo/memory_reg_0_7_0_5_i_1__0_n_0        |                                                              |                2 |             12 |         6.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/accumulator0                          | ResetBootSystem/rst_o_reg_0                                  |                4 |             24 |         6.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/memory_page_number[23]_i_2_n_0        | ptop/u_Controller/Interpreter/memory_page_number[23]_i_1_n_0 |                7 |             24 |         3.43 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/num_of_cycles_to_pulse[23]_i_1_n_0    |                                                              |                8 |             24 |         3.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/timeout                               | ResetBootSystem/rst_o_reg_0                                  |               11 |             24 |         2.18 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/num_of_pages                          | ResetBootSystem/rst_o_reg_0                                  |                4 |             24 |         6.00 |
|  clk_core      | ptop/u_Controller/Interpreter/core_reset_reg_2[0]                   |                                                              |                9 |             31 |         3.44 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[12].rbank[12][31]_i_1_n_0          | ptop/rst                                                     |               29 |             32 |         1.10 |
|  clk_core      | ptop/u_ssrv_top/i_bits/E[0]                                         | ptop/rst                                                     |               17 |             32 |         1.88 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[25].rbank[25][31]_i_1_n_0          | ptop/rst                                                     |               31 |             32 |         1.03 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[30].rbank[30][31]_i_1_n_0          | ptop/rst                                                     |               28 |             32 |         1.14 |
|  clk_core      | ptop/u_ssrv_top/i_bits/inbuf_bits_reg[22]_1[0]                      | ptop/rst                                                     |               18 |             32 |         1.78 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[31].rbank[31][31]_i_1_n_0          | ptop/rst                                                     |               27 |             32 |         1.19 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[26].rbank[26][31]_i_1_n_0          | ptop/rst                                                     |               26 |             32 |         1.23 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[10].rbank[10][31]_i_1_n_0          | ptop/rst                                                     |               31 |             32 |         1.03 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[2].rbank[2][31]_i_1_n_0            | ptop/rst                                                     |               31 |             32 |         1.03 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[22].rbank[22][31]_i_1_n_0          | ptop/rst                                                     |               30 |             32 |         1.07 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[4].rbank[4][31]_i_1_n_0            | ptop/rst                                                     |               32 |             32 |         1.00 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[11].rbank[11][31]_i_1_n_0          | ptop/rst                                                     |               31 |             32 |         1.03 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[23].rbank[23][31]_i_1_n_0          | ptop/rst                                                     |               29 |             32 |         1.10 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[15].rbank[15][31]_i_1_n_0          | ptop/rst                                                     |               28 |             32 |         1.14 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[29].rbank[29][31]_i_1_n_0          | ptop/rst                                                     |               30 |             32 |         1.07 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[13].rbank[13][31]_i_1_n_0          | ptop/rst                                                     |               30 |             32 |         1.07 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[17].rbank[17][31]_i_1_n_0          | ptop/rst                                                     |               32 |             32 |         1.00 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[9].rbank[9][31]_i_1_n_0            | ptop/rst                                                     |               29 |             32 |         1.10 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[19].rbank[19][31]_i_1_n_0          | ptop/rst                                                     |               32 |             32 |         1.00 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[5].rbank[5][31]_i_1_n_0            | ptop/rst                                                     |               32 |             32 |         1.00 |
|  clk_core      | ptop/u_ssrv_top/i_sys/mtime                                         | ptop/rst                                                     |                8 |             32 |         4.00 |
|  clk_core      | ptop/u_ssrv_top/gen_mul[0].i_mul/calc_y[31]_i_1__0_n_0              | ptop/rst                                                     |               12 |             32 |         2.67 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[21].rbank[21][31]_i_1_n_0          | ptop/rst                                                     |               32 |             32 |         1.00 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[24].rbank[24][31]_i_1_n_0          | ptop/rst                                                     |               31 |             32 |         1.03 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[28].rbank[28][31]_i_1_n_0          | ptop/rst                                                     |               31 |             32 |         1.03 |
|  clk_core      | ptop/u_Controller/Interpreter/E[2]                                  | ptop/u_Controller/Interpreter/core_reset_reg_0               |               19 |             32 |         1.68 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[20].rbank[20][31]_i_1_n_0          | ptop/rst                                                     |               30 |             32 |         1.07 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[8].rbank[8][31]_i_1_n_0            | ptop/rst                                                     |               32 |             32 |         1.00 |
|  clk_core      | ptop/u_ssrv_top/gen_mul[2].i_mul/calc_y[31]_i_1_n_0                 | ptop/rst                                                     |               12 |             32 |         2.67 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[16].rbank[16][31]_i_1_n_0          | ptop/rst                                                     |               32 |             32 |         1.00 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[27].rbank[27][31]_i_1_n_0          | ptop/rst                                                     |               26 |             32 |         1.23 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[18].rbank[18][31]_i_1_n_0          | ptop/rst                                                     |               27 |             32 |         1.19 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/communication_write_data[31]_i_1_n_0  |                                                              |               14 |             32 |         2.29 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/timeout_counter                       | ResetBootSystem/rst_o_reg_0                                  |                7 |             32 |         4.57 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/end_position[31]_i_1_n_0              | ResetBootSystem/rst_o_reg_0                                  |               10 |             32 |         3.20 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/communication_buffer[31]_i_1_n_0      | ResetBootSystem/rst_o_reg_0                                  |                6 |             32 |         5.33 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/read_buffer[31]_i_1_n_0               | ResetBootSystem/rst_o_reg_0                                  |               19 |             32 |         1.68 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/rx_fifo/E[0]                                 | ResetBootSystem/rst_o_reg_0                                  |                4 |             32 |         8.00 |
|  clk_o_BUFG    | ResetBootSystem/E[0]                                                |                                                              |               17 |             32 |         1.88 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/tx_fifo/E[0]                                 | ResetBootSystem/rst_o_reg_0                                  |                5 |             32 |         6.40 |
|  clk_core      |                                                                     | ptop/u_Controller/Interpreter/memory_mux_selector_reg_0      |               12 |             32 |         2.67 |
|  clk_o_BUFG    | ptop/u_Controller/ClkDivider/pulse_counter[0]_i_1_n_0               | ResetBootSystem/rst_o_reg_0                                  |                8 |             32 |         4.00 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[6].rbank[6][31]_i_1_n_0            | ptop/rst                                                     |               31 |             32 |         1.03 |
|  clk_core      | ptop/u_Controller/Interpreter/E[3]                                  | ptop/u_Controller/Interpreter/core_reset_reg_0               |               18 |             32 |         1.78 |
|  clk_core      | ptop/u_Controller/Interpreter/E[1]                                  | ptop/u_Controller/Interpreter/core_reset_reg_0               |               24 |             32 |         1.33 |
|  clk_core      | ptop/u_Controller/Interpreter/E[0]                                  | ptop/u_Controller/Interpreter/core_reset_reg_0               |               21 |             32 |         1.52 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[1].rbank[1][31]_i_1_n_0            | ptop/rst                                                     |               32 |             32 |         1.00 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[3].rbank[3][31]_i_1_n_0            | ptop/rst                                                     |               32 |             32 |         1.00 |
|  clk_core      | ptop/u_ssrv_top/gen_mul[1].i_mul/calc_y[31]_i_1__1_n_0              | ptop/rst                                                     |               14 |             32 |         2.29 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[7].rbank[7][31]_i_1_n_0            | ptop/rst                                                     |               31 |             32 |         1.03 |
|  clk_core      | ptop/u_ssrv_top/i_mprf/gen_rbank[14].rbank[14][31]_i_1_n_0          | ptop/rst                                                     |               32 |             32 |         1.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/num_of_positions[23]_i_1_n_0          |                                                              |               13 |             55 |         4.23 |
|  clk_core      | ptop/u_ssrv_top/gen_mul[1].i_mul/calc_b_pos                         | ptop/rst                                                     |               81 |            106 |         1.31 |
|  clk_core      | ptop/u_ssrv_top/gen_mul[0].i_mul/calc_b_pos                         | ptop/rst                                                     |               78 |            106 |         1.36 |
|  clk_core      | ptop/u_ssrv_top/gen_mul[2].i_mul/calc_b_pos                         | ptop/rst                                                     |               77 |            106 |         1.38 |
|  clk_o_BUFG    |                                                                     | ResetBootSystem/rst_o_reg_0                                  |               45 |            117 |         2.60 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/core_addr_reg[12]_0                   |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/memory_mux_selector_reg_3             |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address_reg[10]_0                     |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address_reg[11]_0                     |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/memory_mux_selector_reg_2             |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/core_addr_reg[12]                     |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/core_addr_reg[12]_1                   |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/core_addr_reg[12]_2                   |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/core_addr_reg[12]_3                   |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/core_addr_reg[12]_4                   |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/core_addr_reg[12]_5                   |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/core_addr_reg[12]_6                   |                                                              |               32 |            128 |         4.00 |
|  clk_core      | ptop/u_ssrv_top/i_bits/jcbuf_predict_reg[0]_0[0]                    | ptop/rst                                                     |              118 |            256 |         2.17 |
|  clk_core      |                                                                     | ptop/rst                                                     |             1942 |           3233 |         1.66 |
+----------------+---------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+


