# Group: HANRVivadoTranslator
rt::set_parameter sortTranslatorInputByName {false}
# Group: HARTCnf
rt::set_parameter CNFDebug {false}
# Group: HARTDFCnf
rt::set_parameter DFCnfDebug {true}
rt::set_parameter DFCnfSolverTimeOut {300}
# Group: HARTDFVerify
rt::set_parameter DFVerifyAssertOnNotEquiv {true}
rt::set_parameter DFVerifyCreateChangeGraphsOnly {false}
rt::set_parameter DFVerifyEliminateFalsePins {true}
rt::set_parameter DFVerifyGuidedFlow {false}
rt::set_parameter DFVerifyTerminateOnError {false}
rt::set_parameter DFVerifyTerminateOnNotEquiv {false}
rt::set_parameter DFVerifyVerifyChanges {true}
# Group: HARTFanoutOpt2
rt::set_parameter enableFanoutOpt2 {true}
rt::set_parameter fanoutOpt2SkipCarryInDriver {true}
rt::set_parameter fanoutOpt2assignLoadWeights {true}
rt::set_parameter fanoutOpt2considerTiming {false}
rt::set_parameter fanoutOpt2debug {0}
rt::set_parameter fanoutOpt2doTopoSort {true}
rt::set_parameter fanoutOpt2keepFeedbackLutsOnOneFlop {true}
rt::set_parameter fanoutOpt2lowerThreshold {192}
rt::set_parameter fanoutOpt2maxClusterSize {128}
rt::set_parameter fanoutOpt2maxHFNs {5000}
rt::set_parameter fanoutOpt2maxLoadLevels {5}
rt::set_parameter fanoutOpt2minClusterSize {64}
rt::set_parameter fanoutOpt2replicateControlNets {false}
rt::set_parameter fanoutOpt2upperThreshold {5000}
rt::set_parameter fanoutOpt2verySmallClusterSize {4}
# Group: HARTGLogicGen
rt::set_parameter GLogicGenCreateLogicPartitionPerNode {false}
rt::set_parameter GLogicGenCreateXilinxLogicPartitionPerNode {false}
rt::set_parameter GLogicGenDissolvePartition {true}
rt::set_parameter GLogicGenVerifyXilinxLogicPartition {false}
rt::set_parameter absorbInvInLogicGenerator {true}
rt::set_parameter disableOasysMuxGen {false}
rt::set_parameter dumpNetlistAfterNlopt {false}
rt::set_parameter extractMux1 {false}
rt::set_parameter extractXorAndXnor {true}
rt::set_parameter postponeOasysMuxGen {false}
rt::set_parameter supportConstantBSelOutOfBound {true}
rt::set_parameter useAndOrGenerator {true}
rt::set_parameter useNloptPerLogicPartition {false}
rt::set_parameter xilinxGLogicGenerator {true}
rt::set_parameter xilinxGLogicGeneratorForComparator {true}
rt::set_parameter xilinxGLogicGeneratorForConstantNode {false}
rt::set_parameter xilinxGLogicGeneratorForEqComparator {false}
rt::set_parameter xilinxGLogicGeneratorPerNode {true}
# Group: HARTGraph
rt::set_parameter noControlLatencyFromPort {false}
rt::set_parameter relaxRegSkew {1}
rt::set_parameter retAutoClock {0}
rt::set_parameter retBoundArea {100000}
rt::set_parameter retBoundedOneLevelSlack {8000}
rt::set_parameter retBoundedSlack {2600}
rt::set_parameter retBwrdCtrlPinDelay {200}
rt::set_parameter retBwrdIgnoreInitDebug {true}
rt::set_parameter retBwrdInputReg {false}
rt::set_parameter retBwrdRegsLooseCompatible {false}
rt::set_parameter retBwrdRelax {false}
rt::set_parameter retBwrdRelaxValue {0}
rt::set_parameter retCtrlBwrd {true}
rt::set_parameter retCtrlGateSlack {350}
rt::set_parameter retCtrlSize {4}
rt::set_parameter retDebugDsp {0}
rt::set_parameter retDebugLocal {0}
rt::set_parameter retDspFwrdJump {0}
rt::set_parameter retFwrdCritLimit {300}
rt::set_parameter retFwrdCtrlPinDelay {50}
rt::set_parameter retFwrdMinGain {20}
rt::set_parameter retFwrdRelax {false}
rt::set_parameter retFwrdRelaxValue {0}
rt::set_parameter retIoReg {1}
rt::set_parameter retLevelDelay {100}
rt::set_parameter retLocalFlag {true}
rt::set_parameter retLocalIncremental {1}
rt::set_parameter retLocalLevel {1}
rt::set_parameter retMinDelayForClk {false}
rt::set_parameter retMinTimerLutDelay {140}
rt::set_parameter retRelaxInitCondition {false}
rt::set_parameter retSkewWithEnable {true}
rt::set_parameter retURamRetNum {300}
rt::set_parameter retUpdateTiming {0}
rt::set_parameter retUseSlack {true}
rt::set_parameter retimingBackward {true}
rt::set_parameter retimingForward {true}
rt::set_parameter stopBwrdArea {2}
rt::set_parameter stopBwrdReachabeNumCarryReg {1}
rt::set_parameter stopBwrdReachableNumReg {200}
rt::set_parameter stopBwrdSlack {500}
# Group: HARTMLNlOptPrediction
rt::set_parameter nlOptSmartMLPredictionProbabilityThreshold {60}
# Group: HARTNNetDelayReader
rt::set_parameter delayReaderDbg {0}
rt::set_parameter useGetCellNameMapping_cached {true}
# Group: HARTPACellDelay
rt::set_parameter funnelEverestDsps {true}
rt::set_parameter funnelEverestRams {true}
rt::set_parameter funnelUserInstance {true}
rt::set_parameter speedupFunneling {true}
# Group: HARTPACellDelayVeam
rt::set_parameter maxLutDelay {true}
rt::set_parameter maxPercent {60}
rt::set_parameter useOriginalName {false}
rt::set_parameter versalCLK2CE {-140}
rt::set_parameter versalCLK2Q {120}
rt::set_parameter versalCLK2RS {100}
rt::set_parameter versalControlArc {12}
# Group: HARTPAMapping
rt::set_parameter versalRegTimingfix {true}
# Group: HARTPrepRetiming
rt::set_parameter backwardWNSRatio {20}
rt::set_parameter bwrdHighFF2FFDelta {150}
rt::set_parameter bwrdHighFF2FixedDelta {250}
rt::set_parameter bwrdHighFreqArr {800}
rt::set_parameter bwrdHighFreqDelta {120}
rt::set_parameter fixCarry2Group {true}
rt::set_parameter forwardWNSRatio {20}
rt::set_parameter fwrdHighFreqArr {400}
rt::set_parameter fwrdHighFreqDelta {120}
rt::set_parameter patternCR1144344 {false}
rt::set_parameter patternForwardMaxFanout {2}
rt::set_parameter patternForwardSlackBound {2000}
rt::set_parameter patternForwardSlackDelta {500}
rt::set_parameter patternMaxFanout {8}
rt::set_parameter patternNoCarry {0}
rt::set_parameter patternSlackBound {2000}
rt::set_parameter patternSlackDelta {550}
rt::set_parameter retFinalFwrdDelta {500}
rt::set_parameter retFinalWorstDelta {50}
rt::set_parameter retFwrdFanout {20}
rt::set_parameter retMoreURAMReg {true}
rt::set_parameter retimingFinalDebug {true}
rt::set_parameter retimingFinalLutDiff {100}
rt::set_parameter retimingFinalRelativeDiff {500}
rt::set_parameter retimingFinalSlack {400}
rt::set_parameter retimingFinalSlackDiff {100}
rt::set_parameter retimingFwrdCtrlFanout {-1}
rt::set_parameter worstSlackRatio {20}
# Group: HARTResynthHandleRtd
rt::set_parameter dumpPreservedModulesRtdsInTmpDir {true}
rt::set_parameter handleResynthRtdDebug {0}
rt::set_parameter rubikNamingConvention {true}
rt::set_parameter rubikReuseGlobalNames {true}
# Group: HARTResynthMgr
rt::set_parameter crcCollisionVerificationMode {false}
rt::set_parameter crcReuseVerificationMethod {1}
rt::set_parameter disableCrcFilter {false}
rt::set_parameter disableCrcReuse {false}
rt::set_parameter resynthMgrDebug {2}
rt::set_parameter resynthMgrDebugMsg {false}
rt::set_parameter resynthSynVerbose {0}
rt::set_parameter rubikEnableExtRamReg {false}
rt::set_parameter rubikEnableRamPipeline {false}
rt::set_parameter rubikMaxRamCascHeight {128}
rt::set_parameter rubikRecipeBRam2Uram {true}
rt::set_parameter rubikRecipeRamStyleToAuto {false}
rt::set_parameter rubikRecipeTDRam {true}
rt::set_parameter rubikRecipeURam2Uram {true}
rt::set_parameter rubikTestResynthFlow {false}
# Group: HARTRet
rt::set_parameter synNewIterations {1}
# Group: HARTRetUtil
rt::set_parameter lutMapDeltaThreshold {0.100000}
rt::set_parameter lutMapForRetiming {1}
rt::set_parameter lutMapLocalDeltaThreshold {200}
rt::set_parameter lutMapLocalThreshold {200}
rt::set_parameter lutMapWorstThreshold {100}
rt::set_parameter lutMapgBoundMax {-500}
rt::set_parameter prepLutmap {0}
rt::set_parameter prepLutmapDebug {0}
rt::set_parameter prepLutmapLevel {0}
rt::set_parameter retimingPattern {0}
# Group: HARTRetime
rt::set_parameter retBackwardLoop {true}
rt::set_parameter retCheckFlops {false}
rt::set_parameter retCheckSlack {false}
rt::set_parameter retCloneDriver {false}
rt::set_parameter retForwardOnly {true}
rt::set_parameter retPlaced {false}
rt::set_parameter retSkipCarry {true}
rt::set_parameter retSkipExceptions {false}
rt::set_parameter retimingForImrreg {0}
rt::set_parameter retimingIteration {10000}
# Group: HARTRetiming
rt::set_parameter BwrdCarry2Slack {0}
rt::set_parameter blockLeveRetimingThreshold {-1}
rt::set_parameter carryGroupFix {1}
rt::set_parameter enableOptIOFlops {false}
rt::set_parameter regBoundNum {0}
rt::set_parameter regBoundPercent {100}
rt::set_parameter regPatternNum {300}
rt::set_parameter regPatternPercent {5}
rt::set_parameter regPatternSlackBound {1000}
rt::set_parameter relaxBwrdWorstDelta {1000}
rt::set_parameter relaxFwrdWorstDelta {800}
rt::set_parameter relaxSlackBound {400}
rt::set_parameter retAdustCarryInReg {true}
rt::set_parameter retAsyncReg {true}
rt::set_parameter retAutoPipeline {false}
rt::set_parameter retBlockDelay {true}
rt::set_parameter retBlockNetDelay {350}
rt::set_parameter retBwrdFanout {100}
rt::set_parameter retBwrdIgnoreInitCondition {false}
rt::set_parameter retBwrdLocalDelta {1200}
rt::set_parameter retBwrdMapDelta {850}
rt::set_parameter retBwrdWorstDelta {700}
rt::set_parameter retBwrdWorstDelta2 {500}
rt::set_parameter retCSlowNumber {0}
rt::set_parameter retClkPeriod {-1}
rt::set_parameter retConstProp {false}
rt::set_parameter retControlSet {true}
rt::set_parameter retCpuTime {false}
rt::set_parameter retCritEdges {false}
rt::set_parameter retCritLevel {2}
rt::set_parameter retCtlTimingArc {true}
rt::set_parameter retCtrlDelta {800}
rt::set_parameter retCtrlFanoutLimit {8}
rt::set_parameter retCtrlPin {false}
rt::set_parameter retCtrlSlackDelta {10}
rt::set_parameter retDSP48E2ClkToOut {1050}
rt::set_parameter retDSP48E2Comb {1750}
rt::set_parameter retDSP48E2Setup {1050}
rt::set_parameter retDSP48E2Timing {true}
rt::set_parameter retDebugNetlist {false}
rt::set_parameter retDebugTiming {0}
rt::set_parameter retDesignSlackDelta {4000}
rt::set_parameter retDevDebug {false}
rt::set_parameter retDoParallel {true}
rt::set_parameter retDriverFanout {4}
rt::set_parameter retDspPackRegisters {false}
rt::set_parameter retEffort {20}
rt::set_parameter retEndPointLimit {1000000}
rt::set_parameter retFastClkPeriod {1000}
rt::set_parameter retFixSubInputReg {false}
rt::set_parameter retFixSubOutputReg {false}
rt::set_parameter retFixTopInputReg {true}
rt::set_parameter retFixTopOutputReg {true}
rt::set_parameter retFlattenInsideGenome {false}
rt::set_parameter retFlopSelfLoop {true}
rt::set_parameter retForURAM {true}
rt::set_parameter retForceTopOutReg {true}
rt::set_parameter retForwardOrBackward {0}
rt::set_parameter retFwrdLocalDelta {1000}
rt::set_parameter retFwrdMinDelta {30}
rt::set_parameter retFwrdWorstDelta {700}
rt::set_parameter retFwrdWorstDelta2 {500}
rt::set_parameter retGateFirstDelta {1800}
rt::set_parameter retGateSecondDelta {800}
rt::set_parameter retGateSlackBound {600}
rt::set_parameter retGatedClock {false}
rt::set_parameter retHighFanoutBound {1000}
rt::set_parameter retHighFanoutCombBound {200}
rt::set_parameter retHighFanoutFactor {200}
rt::set_parameter retHighFanoutFlag {false}
rt::set_parameter retIgnoreCtrlGateDelay {false}
rt::set_parameter retImprove {1}
rt::set_parameter retImproveRunTime {true}
rt::set_parameter retIncCarryDelay {true}
rt::set_parameter retIncMuxDelay {1}
rt::set_parameter retInsertPipeline {false}
rt::set_parameter retInsertPipelineBySlack {true}
rt::set_parameter retInsertPipelineForDsp {false}
rt::set_parameter retInsertPipelineForRam {false}
rt::set_parameter retKeepMod {true}
rt::set_parameter retLatencySlack {5000}
rt::set_parameter retLevel {3}
rt::set_parameter retLutCarryJump {true}
rt::set_parameter retLutDelay {350}
rt::set_parameter retMapControlPins {false}
rt::set_parameter retMaxDissolveSize {50000000}
rt::set_parameter retMinPipeDelay {350}
rt::set_parameter retModName {}
rt::set_parameter retModuleNetDelay {470}
rt::set_parameter retNewIterations {1}
rt::set_parameter retNewLutDelay {180}
rt::set_parameter retNewMoves {2}
rt::set_parameter retNewSlackDelta {140}
rt::set_parameter retNoCarry {false}
rt::set_parameter retNoModuleAcross {false}
rt::set_parameter retNoRegCtrlCheck {false}
rt::set_parameter retNoRegUserInstance {true}
rt::set_parameter retOneLevelDelay {-1}
rt::set_parameter retPatternMatch {true}
rt::set_parameter retPipelineByXdc {false}
rt::set_parameter retPipelineDebug {false}
rt::set_parameter retPipelineOneDomain {true}
rt::set_parameter retPortSameLatency {true}
rt::set_parameter retPostRetiming {true}
rt::set_parameter retRAM36E5ClkToOut {1050}
rt::set_parameter retRAM36E5Setup {1050}
rt::set_parameter retRemapLut {false}
rt::set_parameter retSeqSize {2000}
rt::set_parameter retSetDelta {150}
rt::set_parameter retSetPin {false}
rt::set_parameter retSlackBound {150}
rt::set_parameter retSlackBound2 {150}
rt::set_parameter retSlackDelta {525}
rt::set_parameter retSlackEffort {20}
rt::set_parameter retSweepRegisters {false}
rt::set_parameter retTopLevelOnly {true}
rt::set_parameter retTopModule {false}
rt::set_parameter retUseLatencyAttribute {true}
rt::set_parameter retUseWorstSlack {false}
rt::set_parameter retVersalCarry {false}
rt::set_parameter retVersalRAM {true}
rt::set_parameter retWorstSlackBound {20000}
rt::set_parameter retWorstSlackDelta {500}
rt::set_parameter retWriteGraph {false}
rt::set_parameter retimingHighFrequency {1}
rt::set_parameter retimingIOFlops {false}
rt::set_parameter retimingIgnoreFixed {false}
rt::set_parameter retimingLOOKAHEAD8 {true}
rt::set_parameter retimingSlackDebug {0}
rt::set_parameter retimingSlackLevel {1}
rt::set_parameter retimingVerbose {false}
rt::set_parameter retimingVersal {1}
rt::set_parameter synLocalRetiming {false}
rt::set_parameter synRetimingFast {true}
rt::set_parameter synRetimingLevel {1}
rt::set_parameter synRetimingTestFast {true}
# Group: HARTSlrOpt1
rt::set_parameter enableIoOpt1 {false}
rt::set_parameter enableSlrOpt1 {false}
rt::set_parameter slrOpt1assignLoadWeights {true}
rt::set_parameter slrOpt1considerTiming {false}
rt::set_parameter slrOpt1debug {0}
rt::set_parameter slrOpt1doTopoSort {true}
rt::set_parameter slrOpt1lowerThreshold {192}
rt::set_parameter slrOpt1maxClusterSize {128}
rt::set_parameter slrOpt1maxHFNs {5000}
rt::set_parameter slrOpt1maxLoadLevels {5}
rt::set_parameter slrOpt1minClusterSize {64}
rt::set_parameter slrOpt1replicateControlNets {false}
rt::set_parameter slrOpt1upperThreshold {5000}
rt::set_parameter slrOpt1verySmallClusterSize {4}
# Group: HARTTNetDelay
rt::set_parameter adjustGenomeDelay {1}
rt::set_parameter delayRow {0}
rt::set_parameter fastLookahead8Delay {0}
rt::set_parameter gate2Carry2Int {470}
rt::set_parameter interconnectDelayFactor {1.000000}
rt::set_parameter lookahead8Delay {0}
rt::set_parameter lumpCellTypeInWireLoadModel {false}
rt::set_parameter lut6cy2Carry2Int {470}
rt::set_parameter multiLoadDelay {470}
rt::set_parameter newNetDelayModel {false}
rt::set_parameter newNetDelayModelTestFlow {false}
rt::set_parameter oldNetDelayModel {false}
rt::set_parameter oneLoadDelay {470}
# Group: OptFSM
rt::set_parameter fsmAllowFanoutAtWireNode {true}
rt::set_parameter fsm_2018_1 {false}
# Group: TClock
rt::set_parameter storeMasterClock {true}
rt::set_parameter warnClockPeriod {false}
# Group: TDomain
rt::set_parameter warnClockBudget {false}
# Group: TNGenC
rt::set_parameter readAllArcss {true}
# Group: TReport
rt::set_parameter debugTimingReport {false}
rt::set_parameter reportModule {0}
rt::set_parameter timingDebugRetiming {false}
# Group: bitwiseLoopOptimization
rt::set_parameter bMergeThresholdForBitLoop {4}
rt::set_parameter copyPatternEdgeOrConstWithWire {false}
rt::set_parameter enableConstructXformForPropagatedVarExpr {true}
rt::set_parameter enableEdgeXformForLoopExitMuxes {true}
rt::set_parameter enableLoopExitMuxOptimization {true}
rt::set_parameter enableLoopExitXform1 {true}
rt::set_parameter maxVarFaninSize {1000}
rt::set_parameter optimizeMuxChain {false}
rt::set_parameter varBitAssignOptModuleGraph {false}
rt::set_parameter varInputAllowMux {false}
rt::set_parameter varInputAllowMuxForBmerge {true}
rt::set_parameter varInputAllowWire {true}
rt::set_parameter varNodeMaxTotalBitwidth {10}
# Group: condRangeOptimization
rt::set_parameter calcDomainInfo {true}
rt::set_parameter debugCondRangeOpti {false}
rt::set_parameter mergeControlFaninToCondRange {false}
rt::set_parameter pruneFanoutNodesFromControlFanin {false}
# Group: congestion
rt::set_parameter CellPlaceCongestionAnalysis {true}
rt::set_parameter CellPlaceCongestionDriven {false}
rt::set_parameter CongestionAllowOvercount {0}
rt::set_parameter CongestionCreateGraphWithClosedGenome {1}
rt::set_parameter CongestionDissolveUserModules {true}
rt::set_parameter CongestionGenBlockage {2}
rt::set_parameter CongestionGenUsageFactor {1.100000}
rt::set_parameter CongestionIncludeClockNets {false}
rt::set_parameter CongestionIncludePreRoutes {true}
rt::set_parameter CongestionLProbability {0.600000}
rt::set_parameter CongestionMapMaxGridSize {250}
rt::set_parameter CongestionMapPitch {5}
rt::set_parameter CongestionMaxNet {-1}
rt::set_parameter CongestionMinInput {10}
rt::set_parameter CongestionOptMaxInflationRatio {0.150000}
rt::set_parameter CongestionOptMaxOverflow {500}
rt::set_parameter CongestionOptMinInflationRatio {0.050000}
rt::set_parameter CongestionReportGranularity {1}
rt::set_parameter CongestionReservedLayers {2}
rt::set_parameter CongestionRoutingLayers {6}
rt::set_parameter CongestionSmoothingFactor {2}
rt::set_parameter CongestionType {1}
rt::set_parameter CongestionUseBinaryHeapPrim {1}
rt::set_parameter CongestionUseBinaryHeapPrimMinFanout {10}
rt::set_parameter CongestionVerbose {0}
rt::set_parameter CongestionWeightedGraph {5}
rt::set_parameter ECongestionDebug {0}
rt::set_parameter GenomeCongestionThreshold {0.000000}
rt::set_parameter NPlaceCongestionDrivenWSARatio {3.000000}
rt::set_parameter NPlaceCongestionOptInflation {0}
rt::set_parameter NPlaceCongestionOptMaxAllocation {0.050000}
rt::set_parameter PCongestionDebug {0}
rt::set_parameter reduceCongestionPostElaborate {false}
# Group: criticalSigOptAttr
rt::set_parameter criticalSigOptAttrThreshold {2}
rt::set_parameter criticalSigOptSkipAttrCheck {false}
rt::set_parameter critical_sig_opt_inDFG_depth_threshold {50}
rt::set_parameter debugCriticalSigOptAttr {0}
# Group: debug
rt::set_parameter dup3kw {false}
# Group: def
rt::set_parameter DefAllowGenomeInstancesIntoRegion {false}
rt::set_parameter DefDebug {0}
rt::set_parameter DefDefaultGuideSize {100}
rt::set_parameter DefExtractFixedInstances {true}
rt::set_parameter DefForceMSG {false}
rt::set_parameter DefIncludePreRoutes {true}
rt::set_parameter DefMatchEscapedComponent {false}
rt::set_parameter DefTreatPlacedUnknownComponentAsBlockage {true}
rt::set_parameter DefTreatUnknownComponentAsBlockage {true}
rt::set_parameter SdcFileName {}
rt::set_parameter SdcLineNum {}
rt::set_parameter WriteDefGCellGrids {1}
rt::set_parameter WriteDefGenomeExpansionFactor {3.000000}
rt::set_parameter WriteDefGenomeRegions {0}
rt::set_parameter WriteDefGroups {1}
rt::set_parameter WriteDefNets {1}
rt::set_parameter WriteDefPhyOnlyPins {true}
rt::set_parameter WriteDefRegions {1}
rt::set_parameter WriteDefRoutingBlockages {1}
rt::set_parameter WriteDefRows {1}
rt::set_parameter WriteDefSpecialNets {1}
rt::set_parameter WriteDefTracks {1}
rt::set_parameter WriteDefVias {1}
rt::set_parameter abcOptComplexCellBias {0.000000}
rt::set_parameter abcSkipDatapath {0}
rt::set_parameter abcUseLibGen {false}
rt::set_parameter acceptBetterSlackSameArea {false}
rt::set_parameter bucketizeAbcLibrary {false}
rt::set_parameter debugAbcCalls {false}
rt::set_parameter ignoreOneInstanceProblem {false}
rt::set_parameter lOptAlwaysAccept {false}
rt::set_parameter lOptAlwaysReject {false}
rt::set_parameter lOptDebugSDC {false}
rt::set_parameter lOptFanoutLimit {0}
rt::set_parameter lOptIgnoreCellIfInputsGT {10}
rt::set_parameter lOptRetry {false}
rt::set_parameter lOptUseArrival {true}
rt::set_parameter leakageAreaCostInAbcLib {true}
rt::set_parameter leakageAwareAbc {false}
rt::set_parameter rejectSameQorSolution {false}
rt::set_parameter rejectSameSlackWorseArea {false}
rt::set_parameter showAbcCalls {false}
rt::set_parameter skipBalanceInAmap {false}
rt::set_parameter useFullDeltaInEmove {false}
rt::set_parameter useInstCount {false}
rt::set_parameter useNewGenLibWriter {true}
rt::set_parameter useQorCheck {false}
# Group: dft
rt::set_parameter _checkDftAutoTestClocks {false}
rt::set_parameter _checkDftAutoTestPins {false}
rt::set_parameter _checkDftIgnoreClockGating {false}
rt::set_parameter _checkDftIgnoreScanMapStatus {false}
rt::set_parameter _checkDftViolationCount {0}
rt::set_parameter autoRunDft {false}
rt::set_parameter auto_define_derived_test_clocks {false}
rt::set_parameter checkDftFlatTrace {false}
rt::set_parameter checkDftForFailedRegs {false}
rt::set_parameter debugCheckDft {0}
rt::set_parameter debugConnectScanChains {0}
rt::set_parameter dftTspAlgorithm {2}
rt::set_parameter dftTspAnnealingWindowSize {20}
rt::set_parameter displayScanChainIOs {true}
rt::set_parameter scan_lockup_instance_prefix {lockup}
# Group: dp
rt::set_parameter datapathBoothInvPos {true}
rt::set_parameter datapathBoothProdTimingDriven {false}
rt::set_parameter datapathClaOA {true}
rt::set_parameter datapathDivideByConstThreshold {0}
rt::set_parameter datapathDividerOld {false}
rt::set_parameter datapathGenAsModules {false}
# Group: gen
rt::set_parameter MultiBitSelectToOneBit {true}
rt::set_parameter abcOpt {false}
rt::set_parameter aggressiveBalancing {0}
rt::set_parameter andOrGenGatesThreshold {17}
rt::set_parameter andOrImplForBigMux {false}
rt::set_parameter anotherPolarityChange {false}
rt::set_parameter areaForPrioMux {false}
rt::set_parameter balanceAndOr {2}
rt::set_parameter balanceBdd {false}
rt::set_parameter bddGenBucketSizeMult {0.300000}
rt::set_parameter bddGenBucketSizeReduction {0.800000}
rt::set_parameter bddGenRemoveUndriven {true}
rt::set_parameter bddGenSetUndrivenTo {-1}
rt::set_parameter bddGenUseTimingBuckets {true}
rt::set_parameter bddMinimize {0}
rt::set_parameter bigMuxThreshold {600}
rt::set_parameter collapseLateMuxesInAndOrBalancing {false}
rt::set_parameter convertConstSelMuxToPrioMux {true}
rt::set_parameter convertParallelMuxToPrioMux {false}
rt::set_parameter countLevelByTwoInputGates {true}
rt::set_parameter createDFPartitionForFFMuxes {false}
rt::set_parameter createVarSelectFromLsb {false}
rt::set_parameter datapathAdderGenMode {0}
rt::set_parameter datapathAlwaysUseTunedCSA {true}
rt::set_parameter datapathArrayMultiplier {false}
rt::set_parameter datapathBalancedDecoder {false}
rt::set_parameter datapathCSAEliminateSimpleCarry {true}
rt::set_parameter datapathCSAMergeArgs {true}
rt::set_parameter datapathCSAPostponeLateArrivingSignals {true}
rt::set_parameter datapathCSAPostponeLateArrivingSignalsFix {true}
rt::set_parameter datapathCSAScaleFADelay {0.900000}
rt::set_parameter datapathCSAShareSums {false}
rt::set_parameter datapathCSAShareSumsNonTD {false}
rt::set_parameter datapathCSAUseFACells {0}
rt::set_parameter datapathCheckPropCSA {false}
rt::set_parameter datapathClaThreshold {4}
rt::set_parameter datapathDecoderUseNAND {true}
rt::set_parameter datapathDetectGroupSize {2}
rt::set_parameter datapathDualPGTree {false}
rt::set_parameter datapathDualProductTerms {true}
rt::set_parameter datapathFCLA {true}
rt::set_parameter datapathFastestAdderArch {cla}
rt::set_parameter datapathForceFACells {false}
rt::set_parameter datapathGFuncCollapseCarry {true}
rt::set_parameter datapathGpGroupSize {4}
rt::set_parameter datapathInvertG {true}
rt::set_parameter datapathInvertP {false}
rt::set_parameter datapathMergeMultiplierInCSA {false}
rt::set_parameter datapathMultBooth {false}
rt::set_parameter datapathMultInvPrimProd {true}
rt::set_parameter datapathNewDecoder {true}
rt::set_parameter datapathNewInequality {false}
rt::set_parameter datapathNewMult {true}
rt::set_parameter datapathNewPGTree {false}
rt::set_parameter datapathNewUnaryMinus {true}
rt::set_parameter datapathPgConstx {true}
rt::set_parameter datapathPgDontCare {true}
rt::set_parameter datapathPgForCon {true}
rt::set_parameter datapathPgGroupSize {4}
rt::set_parameter datapathPgTuned {true}
rt::set_parameter datapathShareProductTerms {true}
rt::set_parameter datapathShifterConstFix {true}
rt::set_parameter datapathSmallestAdderArch {ripple}
rt::set_parameter datapathTunedCSA6to3Comp {false}
rt::set_parameter datapathTunedCSAFixTernaryPMM {true}
rt::set_parameter datapathUseGFuncManager {false}
rt::set_parameter datapathUseMapper {true}
rt::set_parameter debugFileNamePrefix {b2g}
rt::set_parameter debugHang {false}
rt::set_parameter debugHangThreshold {30}
rt::set_parameter debugMapLibrary {false}
rt::set_parameter debugMapper {false}
rt::set_parameter decompOnTopVar {false}
rt::set_parameter decompTryAllVar {true}
rt::set_parameter decompTryAllVarLimit {2147483647}
rt::set_parameter defaultInputLevel {-2147483648}
rt::set_parameter depthDiffToDistribute {3}
rt::set_parameter depthDiffToPushSignalForward {2}
rt::set_parameter depthOverCost {false}
rt::set_parameter donotBalanceMuxTreeGen {true}
rt::set_parameter dualRailInputs {false}
rt::set_parameter dualRailOutputs {false}
rt::set_parameter dynamicReorderBdd {true}
rt::set_parameter dynamicReorderBddForConstruct {true}
rt::set_parameter dynamicReorderForConstructBddToGates {true}
rt::set_parameter dynamicReorderingForBddToGates {true}
rt::set_parameter dynamicReorderingWith {6}
rt::set_parameter enableOnehotMux {false}
rt::set_parameter estimateCofactor {false}
rt::set_parameter flattenLogicAcrossBits {false}
rt::set_parameter forceNlOptMux {false}
rt::set_parameter fsmReencoding {true}
rt::set_parameter gFsmDebug {0}
rt::set_parameter goodFactorHeuristic {3}
rt::set_parameter groupPrioMux {true}
rt::set_parameter ignoreInputInverters {false}
rt::set_parameter implementOHDectorLogicInGates {false}
rt::set_parameter implementOHDectorUsingLutsAndGates {false}
rt::set_parameter implementPartialOHDectorLogicInGates {true}
rt::set_parameter implementPartialOHUsingOHDector {true}
rt::set_parameter implementPartialOHValidSelWidthThreshold {6}
rt::set_parameter improveRedundantGateRemoval {true}
rt::set_parameter inputDontCareValue {0}
rt::set_parameter logicDecompositionEffort {1}
rt::set_parameter logicGenCheckUserTime {0}
rt::set_parameter maxBddNodeCountIncrease {0.500000}
rt::set_parameter maxDepthDiffForMuxInputs {4}
rt::set_parameter maxInToDistribute {4}
rt::set_parameter maxSelectSizeForVarSelect {8}
rt::set_parameter minBddVarCount {20}
rt::set_parameter minimizeFunctionForVariableSorting {false}
rt::set_parameter minimizeMethod {restrict}
rt::set_parameter multipleFunctionGeneration {false}
rt::set_parameter muxVerbose {0}
rt::set_parameter nandForXorIgnoreInverterCost {false}
rt::set_parameter newCostFunctionForMuxPartGen {true}
rt::set_parameter nonTimingDrivenBalancing {true}
rt::set_parameter oldMuxGeneratorHeuristic {false}
rt::set_parameter optimizeReinfer {false}
rt::set_parameter powerPreferISOLOW {true}
rt::set_parameter powerRelaxPowerTypeRequirement {false}
rt::set_parameter precomputeSelect {true}
rt::set_parameter preselectDecompVar {0}
rt::set_parameter prioMuxNoCarryChain {true}
rt::set_parameter pushLateSignalForward {true}
rt::set_parameter pushLateSignalUsingDelays {false}
rt::set_parameter pushLateXorInputForward {true}
rt::set_parameter reduceBeforeGenerate {false}
rt::set_parameter reencodePrioMux {true}
rt::set_parameter regenBailImmediatelyOnBddError {true}
rt::set_parameter regenLogicWithinCritRange {-1}
rt::set_parameter releaseBddWhenDone {true}
rt::set_parameter reorderConstruct {1}
rt::set_parameter resetBddMgrVarCount {false}
rt::set_parameter restrictAndOrMuxForOHFsm {true}
rt::set_parameter reverseConnectOrder {false}
rt::set_parameter setDontCareValueTo {-1}
rt::set_parameter showMappingCosts {false}
rt::set_parameter sortAllVariables {false}
rt::set_parameter sortAndOrInputsByDepth {true}
rt::set_parameter sortBddVar {0}
rt::set_parameter sortXorInputs {false}
rt::set_parameter spdNlOpt {false}
rt::set_parameter spdNlOptDebug {false}
rt::set_parameter spdShannon {true}
rt::set_parameter supportBSelOutOfBound {true}
rt::set_parameter supportConstantDataInAndOrGenerator {false}
rt::set_parameter timdrBddGenDebug {0}
rt::set_parameter timingDrivenGateGeneration {true}
rt::set_parameter timingDrivenGateSkewing {true}
rt::set_parameter tryShare {false}
rt::set_parameter unbalancedMuxf {false}
rt::set_parameter useAndOr {true}
rt::set_parameter useArrivalForInputDelays {0}
rt::set_parameter useBestTree {false}
rt::set_parameter useBestTreeInAndPlane {false}
rt::set_parameter useBucketsInMapper {false}
rt::set_parameter useCachedStructures {true}
rt::set_parameter useDatapathForlogicDecoderOutSizeGr {1}
rt::set_parameter useDelayToBreakTiesInNonTDMode {true}
rt::set_parameter useDsd {false}
rt::set_parameter useFastDontCares {true}
rt::set_parameter useMapper {true}
rt::set_parameter useMapperInSynthesis {false}
rt::set_parameter useMux {true}
rt::set_parameter useNand {true}
rt::set_parameter useNor {true}
rt::set_parameter usePermsWhileMappingMuxes {true}
rt::set_parameter usePolarityInExpandMux {true}
rt::set_parameter useTwoLevelSpeedup {false}
rt::set_parameter useXor {true}
rt::set_parameter usingNloptInAndOr {false}
rt::set_parameter verifyMuxpartGenCnf {false}
rt::set_parameter xilinxMuxTreeGenerator {false}
# Group: gui
rt::set_parameter arrivalTimeToolTip {false}
rt::set_parameter congestionGuiDebug {0}
rt::set_parameter congestionThreshold {0.500000}
rt::set_parameter dutchZoom {false}
rt::set_parameter flightLinesBetweenSinks {false}
rt::set_parameter genericMuxSymbol {false}
rt::set_parameter jumpScroll {500}
rt::set_parameter markFixedInstances {true}
rt::set_parameter maxMessageCountPerGroup {1000}
rt::set_parameter maxWireCount {4000}
rt::set_parameter powerMapRange {5.000000}
rt::set_parameter powerPropertyShowDensity {false}
rt::set_parameter showClockNet {false}
rt::set_parameter showDetailedPins {false}
rt::set_parameter showDomainBrowserInMain {false}
rt::set_parameter showPinDensity {false}
rt::set_parameter showPowerTabWithDisabled {true}
rt::set_parameter timingHistogramBars {30}
rt::set_parameter timingHistogramUseDetailedEndpoints {true}
rt::set_parameter updateInstVisible {true}
rt::set_parameter warnIfBufferSizeMoreThan {10}
rt::set_parameter warnIfNetlistSizeMoreThan {50000}
# Group: hartcleanup
rt::set_parameter absorbDataInverter {false}
rt::set_parameter allowFanoutsForBddBasedCtrlExtraction {true}
rt::set_parameter byteWriteCleanupAfterAreaOpt {true}
rt::set_parameter cleanupInPreMap {false}
rt::set_parameter collapseLuts {true}
rt::set_parameter collapseLutsCheckCarryLoads {false}
rt::set_parameter collapseLutsPostInsertIO {true}
rt::set_parameter collapseLutsTiming {true}
rt::set_parameter collapseLutsVerbose {false}
rt::set_parameter collectOutMuxcyVersal {false}
rt::set_parameter ctrlSetDuplicateCompleteCone {false}
rt::set_parameter demoteMuxfRegUtilizationThreshold {30}
rt::set_parameter demoteMuxfThreshold {4}
rt::set_parameter demoteNonCriticalMuxF {false}
rt::set_parameter demoteNonCriticalMuxFForOlympus {false}
rt::set_parameter dontOptimizeConvertedMuxcy {false}
rt::set_parameter dontTouchOnInsertedAnchor {true}
rt::set_parameter extendCarryChainTop {true}
rt::set_parameter extendCarryChains {true}
rt::set_parameter extractSyncSetInNetlist {true}
rt::set_parameter logicLevelForBddBasedCtrlExtraction {6}
rt::set_parameter lookBOpt {true}
rt::set_parameter lutCascadeOpt {false}
rt::set_parameter lutCombineInstantiatedCarryChainFlow {false}
rt::set_parameter lutDupLimit {100}
rt::set_parameter lutFanoutThreshold {10000}
rt::set_parameter optimizeCtrlSetOverlapPostCollapseLut {true}
rt::set_parameter optimizeLutcy {false}
rt::set_parameter packLoadLutsOfCarryToCarryChain {false}
rt::set_parameter postMapNlOpt {false}
rt::set_parameter postMapTimingQuery {true}
rt::set_parameter postponeMuxCyConversion {true}
rt::set_parameter postponeXorCyConversion {false}
rt::set_parameter replicateRegister {false}
rt::set_parameter retimeCtrlForSrl {true}
rt::set_parameter retimeDeltaThreshold {1200}
rt::set_parameter retimeHighFanoutThreshold {100}
rt::set_parameter retimeHighFanoutVerbose {0}
rt::set_parameter retimeInputThreshold {1200}
rt::set_parameter retimeWorstThreshold {1000}
rt::set_parameter searchImmediateRegLoadLevel {3}
rt::set_parameter slackThreshold {1}
rt::set_parameter stopDemoteNonCriticalMuxF8DrivingF9 {true}
rt::set_parameter sweepRegisters {true}
rt::set_parameter updateDspTiming {true}
rt::set_parameter useCachedSlackInCleanup {true}
rt::set_parameter verboseCtrlExtraction {0}
rt::set_parameter xilinxBoolSwitch2 {false}
# Group: hartctrlsetopt
rt::set_parameter aggressiveControlSetOpt {false}
rt::set_parameter cloneInstanceForMultiFanOut {false}
rt::set_parameter controlSetOptCollapseControlLogic {true}
rt::set_parameter controlSetsFeedbackPathThreshold {1}
rt::set_parameter controlSetsOptFlow {premap}
rt::set_parameter controlSetsOptMaxFlops {-1}
rt::set_parameter controlSetsOptMaxFlopsLowerBound {20}
rt::set_parameter controlSetsOptMaxFlopsPercent {100}
rt::set_parameter controlSetsOptSkipBRAMAddr {true}
rt::set_parameter controlSetsOptSkipFlopChains {true}
rt::set_parameter controlSetsOptSkipUserInsts {true}
rt::set_parameter enableControlSetsOpt {true}
rt::set_parameter nlOptInPostMapCSO {false}
rt::set_parameter reduceControlSetForMultiFanOutNet {false}
# Group: hartgdatapathpipeline
rt::set_parameter retimingDataPathDebug {0}
rt::set_parameter retimingDataPathForce {false}
rt::set_parameter retimingDataPathIterations {1}
rt::set_parameter retimingLatencyDebug {false}
rt::set_parameter retimingPrepOnly {false}
# Group: hartgdp
rt::set_parameter compareZeroShortCut {true}
rt::set_parameter datapathAddDisjointTimingThreshold {35}
rt::set_parameter datapathComparatorConstOpt {false}
rt::set_parameter datapathEqMaxBitsPerStage {-1}
rt::set_parameter datapathLGTDisjointTimingThreshold {16}
rt::set_parameter eqConstOperandOpt {false}
rt::set_parameter eqKeepXor {false}
rt::set_parameter extendBinaryEq2Even {true}
rt::set_parameter implementMultInLogic {false}
rt::set_parameter removeConstInEqGen {0}
rt::set_parameter timingDrivenGeneratorEq {false}
rt::set_parameter useOriginalCSA {false}
rt::set_parameter useXilinxBoothMultiplier {false}
rt::set_parameter xilinxBoothAvoidMSBCarryMapping {false}
rt::set_parameter xilinxBoothSignedMaxThreshold {12}
rt::set_parameter xilinxBoothSignedMinThreshold {4}
rt::set_parameter xilinxBoothUnsignedMaxThreshold {13}
rt::set_parameter xilinxBoothUnsignedMinThreshold {5}
# Group: hartgsrlgen
rt::set_parameter disableTimingCheckInSRLGeneration {true}
rt::set_parameter retimingSRLEndMaxLength {30}
rt::set_parameter retimingSRLEndMinLength {4}
rt::set_parameter retimingSRLFunctionalFix {1}
rt::set_parameter retimingSRLRunTimeFix {1}
rt::set_parameter retimingSRLStartMinLength {4}
rt::set_parameter retimingSRLTotalMaxLength {34}
rt::set_parameter retimingSRLTotalMinLength {5}
# Group: harthoptpost
rt::set_parameter verifyPrio2BinaryConversion {false}
# Group: hartiomap
rt::set_parameter convertTristatesToLuts {false}
rt::set_parameter createOBUFTinLowerLevel {true}
rt::set_parameter enableAsyncFF {false}
rt::set_parameter enableIddrInfer {true}
rt::set_parameter enableOddrInfer {true}
rt::set_parameter enableTristateBubbleUp {true}
rt::set_parameter enableTristateToMux {true}
rt::set_parameter handlePreBufPins {true}
rt::set_parameter insertClkBufInOOC {false}
rt::set_parameter makeIOPortNetGroups {true}
rt::set_parameter splitDataWithCtrl {false}
rt::set_parameter unconnectedPinToZeroForOOCTop {true}
# Group: hartlutmap
rt::set_parameter areaOptHighRequiredAdjustFactor {3.500000}
rt::set_parameter areaOptLowRequiredAdjustFactor {2.000000}
rt::set_parameter areaOptMedRequiredAdjustFactor {3.000000}
rt::set_parameter requiredTimeAdjustFactor {1.000000}
rt::set_parameter requiredTimeAdjustInAreaOptimizedFlow {true}
rt::set_parameter restoreLut6cyForConstSPG {true}
rt::set_parameter restoreLut6cyForConstSPG2 {false}
rt::set_parameter restoreLut6cyForConstSPG_earlyTieOff {true}
rt::set_parameter retimingBasedAdjust {false}
rt::set_parameter tdMapperEndCompFactor1 {-1000}
rt::set_parameter tdMapperEndCompFactor2 {300}
rt::set_parameter tdMapperLevelFactor {1600}
rt::set_parameter tdMapperNewReqCompFactor {2}
rt::set_parameter tdMapperScaleFactor1 {2}
rt::set_parameter tdMapperScaleFactor2 {1}
rt::set_parameter tdMapperStartDelayFactor1 {14000}
rt::set_parameter tdMapperStartDelayFactor2 {4000}
rt::set_parameter tdMapperStartDelayFactor3 {12000}
rt::set_parameter tdMapperTimingException {false}
rt::set_parameter timingDrivenSetArrivalOnBoundary {true}
# Group: hartndb
rt::set_parameter block_nlopt {false}
rt::set_parameter callOasysConstPropInsideGenomes {true}
rt::set_parameter cleanUpAllShortedNets {true}
rt::set_parameter cleanUpShortedNetsInMergeUserInstances {false}
rt::set_parameter clock_gating_enable_hierarchical_flow {false}
rt::set_parameter compareNetlistCNF {false}
rt::set_parameter constPropRunTimeFix {true}
rt::set_parameter debug_changed_names {false}
rt::set_parameter deriveConstraints {false}
rt::set_parameter deriveConstraints2 {true}
rt::set_parameter dissolveEmptyInferredModules {true}
rt::set_parameter dissolveFsmModules {true}
rt::set_parameter fixIPRetiming {false}
rt::set_parameter fixTimingConstraints {false}
rt::set_parameter generateCnfForTopGraph {false}
rt::set_parameter inferMultiRatio {0.700000}
rt::set_parameter lutPairNewThreshold {false}
rt::set_parameter lutPairNewThreshold2 {false}
rt::set_parameter markGenomePinsConnectedToTopModule {true}
rt::set_parameter optimizeCleanupInMapToSRL {false}
rt::set_parameter optimizeReinfer2 {0}
rt::set_parameter optimizeReinfer2Debug {false}
rt::set_parameter preserveGenomesInsideSBlocks {false}
rt::set_parameter print_nlopt_checksum {false}
rt::set_parameter registerDebug {0}
rt::set_parameter reinferCaseFix {false}
rt::set_parameter reinferMultiInstsByName {true}
rt::set_parameter reinferPreserveUserInstances {false}
rt::set_parameter reinferPruneBitWidths {true}
rt::set_parameter reinferPruneRegisterWithEnable {true}
rt::set_parameter reinferReportEmptyAndUndriven {true}
rt::set_parameter reinferTimingDriven {true}
rt::set_parameter retRemoveKeepBuf {false}
rt::set_parameter retimingFinal {false}
rt::set_parameter retimingFinalIterations {1}
rt::set_parameter synthReportEmptyAndUndriven {true}
rt::set_parameter useAbcMapping {true}
rt::set_parameter verifyDFGToNetlistCnf {false}
# Group: hartnldivmodretiming
rt::set_parameter retimingDivMod {false}
rt::set_parameter retimingDivModDebug {false}
# Group: hartnlmacrocluster
rt::set_parameter addSoftMacroCoordinate {false}
rt::set_parameter clusterURAM {true}
rt::set_parameter macroClusterLevel0 {false}
rt::set_parameter macroClusterLevel1 {true}
# Group: hartnloptFX
rt::set_parameter nlOptCSEWeight {0}
rt::set_parameter nlOptFxDebug {0}
# Group: hartnloptframework
rt::set_parameter nlOptAig {0}
rt::set_parameter nlOptAreaSpeed {0}
rt::set_parameter nlOptAsis {none-0}
rt::set_parameter nlOptAutoCSS {0-7-2}
rt::set_parameter nlOptBDDOrdering {0}
rt::set_parameter nlOptBdd2PlaFlow {0}
rt::set_parameter nlOptCommon {0}
rt::set_parameter nlOptComplBdd {0}
rt::set_parameter nlOptCritcalSignal {}
rt::set_parameter nlOptCutMap {}
rt::set_parameter nlOptDebugCheckSum {0}
rt::set_parameter nlOptDisplayandSimulate {0}
rt::set_parameter nlOptDumpDataFromThisRunML {0}
rt::set_parameter nlOptEliminate {}
rt::set_parameter nlOptEndGame {0-1}
rt::set_parameter nlOptExpt {0}
rt::set_parameter nlOptFastFlow {0}
rt::set_parameter nlOptForwardCollapse {1}
rt::set_parameter nlOptGatedClockVerbose {0}
rt::set_parameter nlOptInPlaceReplace {1}
rt::set_parameter nlOptMaxLevelPerPartition {0}
rt::set_parameter nlOptMaxNodesPerPartition {0}
rt::set_parameter nlOptOptimizeCriticalPath {0}
rt::set_parameter nlOptOptimizeCriticalPathLevel {0}
rt::set_parameter nlOptPlatForm {0}
rt::set_parameter nlOptPrintHitML {0}
rt::set_parameter nlOptPrintNumAlg {0}
rt::set_parameter nlOptRedRemoval {0}
rt::set_parameter nlOptReduceDepth {1}
rt::set_parameter nlOptRewrite {1-1-4-8-10-100000}
rt::set_parameter nlOptRewriteMode {1}
rt::set_parameter nlOptRewriteNumConeOptimized {0}
rt::set_parameter nlOptRomOpt {1}
rt::set_parameter nlOptRomOptBddOrdering {1}
rt::set_parameter nlOptRomOptNin {16}
rt::set_parameter nlOptRomOptNout {10}
rt::set_parameter nlOptRunRewrite {0}
rt::set_parameter nlOptRunRewriteInStandAlone {0}
rt::set_parameter nlOptRunRewriteNumRun {3}
rt::set_parameter nlOptSelectiveCollapseBeforeRewrite {0}
rt::set_parameter nlOptSimulateBeforeInsert {7}
rt::set_parameter nlOptSingleOutputMinimization {0}
rt::set_parameter nlOptTinyDesign {0}
rt::set_parameter nlOptUseCache {1}
rt::set_parameter nlOptUseCacheML {1}
rt::set_parameter nlOptUseCoverinEstimate {0}
rt::set_parameter nlOptUseReadFileML {0}
rt::set_parameter nlOptUseSeparateBdd {0}
rt::set_parameter nlOptUseSeparateBddForStandalone {0}
rt::set_parameter nlOptUseSmartML {0}
rt::set_parameter nlOptVerilogNetlist {0}
rt::set_parameter nlOptVersalCascadeExtract {0}
rt::set_parameter nlOptWriteROM {0}
# Group: hartnloptimize
rt::set_parameter nlOptChecksum {0}
rt::set_parameter nlOptDebug {0}
rt::set_parameter nlOptEstimate {10000}
rt::set_parameter nlOptVerify {0}
# Group: hartnloptutil_cxx
rt::set_parameter nlOptInputPintoMove {-1}
rt::set_parameter nlOptOutputPintoMove {0}
# Group: hartnlstandalone
rt::set_parameter nlOptLutInit {}
rt::set_parameter nloptStandaloneOptDch {0}
# Group: hartnlutil
rt::set_parameter debugConnectPins {false}
rt::set_parameter ignoreTopMapbufs {false}
rt::set_parameter isClkInvertedAttr {true}
rt::set_parameter lutPairAdjustLimit {25000}
rt::set_parameter lutPairCluster {false}
rt::set_parameter lutPairDebug {false}
rt::set_parameter lutPairNewLevel {2}
rt::set_parameter lutPairThreshold {0}
rt::set_parameter lutPairThreshold1 {600}
rt::set_parameter lutPairThresholdPercent {5}
rt::set_parameter lutPairThresholdPercent2 {10}
rt::set_parameter lutPairWorstSlack {-100}
rt::set_parameter sweepAllRegisters {true}
# Group: hartoptimizeLookAhead
rt::set_parameter debugOptimizeLookAhead {1}
rt::set_parameter packLoadLutsToCarryChainThreshold {48}
# Group: hartoptoperator
rt::set_parameter checkBalanceForCascadeDsrlInference {false}
rt::set_parameter checkCEPinForExtrom {true}
rt::set_parameter checkLevelForRecoding {true}
rt::set_parameter conservativeTimingGuard {false}
rt::set_parameter convertUMinusToAdderMultiFanout {true}
rt::set_parameter convertUMinusToAdderSingleFanout {true}
rt::set_parameter extractResetForCounterFromMux {true}
rt::set_parameter inferBitBlastedDsrl {true}
rt::set_parameter laddToRegOnly {true}
rt::set_parameter muxSetParallel {true}
rt::set_parameter noCounterIfCmpDrivenMuxSel {false}
rt::set_parameter removePassThroughWireAtRamEnable {true}
rt::set_parameter skipMuxpartForOasysStyleMux {false}
rt::set_parameter xilinxCounterFix {true}
# Group: hartrommerge
rt::set_parameter mergeRoms {true}
# Group: hartsyn
rt::set_parameter CGDebug {false}
rt::set_parameter IncrSynMarkSkipCanPlace {false}
rt::set_parameter OptRoms {true}
rt::set_parameter PartId {xc7a100tcsg324-1}
rt::set_parameter SDCFile {}
rt::set_parameter XilinxArrayMult {true}
rt::set_parameter abcScriptForSpd {resyn2;map}
rt::set_parameter absorbAccumulatorInCascade {true}
rt::set_parameter absorbDspInputAdder {true}
rt::set_parameter absorbDspInputInvertor {true}
rt::set_parameter absorbDspInputMuxes {true}
rt::set_parameter absorbDspOutputCounter {false}
rt::set_parameter absorbDspPatternDetectNonConst {true}
rt::set_parameter absorbDspPatternbDetect {true}
rt::set_parameter absorbInvInConstProp {false}
rt::set_parameter absorbInvToRegister {false}
rt::set_parameter absorbTernaryAdderInCascade {true}
rt::set_parameter absorbTernaryAdderInCascadeCase2 {true}
rt::set_parameter addDummyAdderForDspSoloUminusAfterMult {true}
rt::set_parameter addMuxInNewPartitionForNlopt {false}
rt::set_parameter allBitSelectOrder {true}
rt::set_parameter allowMuxpartMerging {true}
rt::set_parameter allowSynkeep {false}
rt::set_parameter allowWidthMismatchInRamPipeline {true}
rt::set_parameter areaFlowFix2 {false}
rt::set_parameter areaPenaltyOnlyForMAPBUF3_1 {true}
rt::set_parameter areaStrategy {0}
rt::set_parameter areaTieThresholdInWireMap {20}
rt::set_parameter asymCascadeHeight {4}
rt::set_parameter asyncLoadPart {true}
rt::set_parameter autoSleepPipeLineAllowed {true}
rt::set_parameter autoSrlExtract {true}
rt::set_parameter balanceSelectOrder {false}
rt::set_parameter binaryMuxReuseControlLogic {true}
rt::set_parameter blockSynthRetiming {false}
rt::set_parameter bramAddrThreshold {6}
rt::set_parameter bramCascPowerPriority {false}
rt::set_parameter bramCascSpeedPriority {true}
rt::set_parameter bramCascadePipeStartPosition {128}
rt::set_parameter bramCascadePriority {min_power}
rt::set_parameter bramPowerAddrThreshold {0}
rt::set_parameter bramResource {-1}
rt::set_parameter bramResourceDebug {0}
rt::set_parameter bramRstPriorityOpt {false}
rt::set_parameter bramSizeThreshold2 {1024}
rt::set_parameter bramUtilHighThresh {90.000000}
rt::set_parameter bramUtilThresh {60.000000}
rt::set_parameter breakDspCascadeLoop {true}
rt::set_parameter breakupMacroClustersNetlist {true}
rt::set_parameter bromAddrThreshold {8}
rt::set_parameter bromSizeThreshold {1024}
rt::set_parameter cacheGenomeGateSlack {0}
rt::set_parameter carryBitSliceNonModFlow {false}
rt::set_parameter carryChainStrategy {0}
rt::set_parameter carryDrcFix {true}
rt::set_parameter carryLUTSizeThreshold {6}
rt::set_parameter ceMinFanout {2147483647}
rt::set_parameter cellToCollapse {NONE}
rt::set_parameter checkCompatibleLoopbackOnZMux {true}
rt::set_parameter checkForCarrySaveInPreAdderDSP {true}
rt::set_parameter checkForFullBinaryMux {false}
rt::set_parameter checkPullLastSrlRegister {true}
rt::set_parameter checkRemovableInstInSimplify {true}
rt::set_parameter checkSignMismatchInCounter {true}
rt::set_parameter cleanUpNetlistSpeedupFirstCall {true}
rt::set_parameter cleanupAfterRegenerate {false}
rt::set_parameter cleanupDanglingModules {true}
rt::set_parameter cleanupEquivalentRegRemovalByPrepRam {true}
rt::set_parameter cleanupInReinfer {false}
rt::set_parameter cleanupNetlistFOpt {true}
rt::set_parameter cleanupParallelRtdFiles {true}
rt::set_parameter clockGatingInsertBufg {true}
rt::set_parameter clockGatingInsertBufgForMinFanout {32}
rt::set_parameter clockGatingOptimizeCombinationalLoopDetection {true}
rt::set_parameter clock_gating_allow_nand_driving_latch {true}
rt::set_parameter clock_gating_allow_or_driving_latch {true}
rt::set_parameter clock_gating_allow_seq_cascade {true}
rt::set_parameter clock_gating_bdd_support_threshold {100}
rt::set_parameter clock_gating_check_for_inferred_clocks {false}
rt::set_parameter clock_gating_conversion_on_mapped_netlist {true}
rt::set_parameter clock_gating_debug {false}
rt::set_parameter clock_gating_debug_messaging_threshold {0}
rt::set_parameter clock_gating_enable_continue_with_comb_loop {false}
rt::set_parameter clock_gating_enable_div_by_2_xform {true}
rt::set_parameter clock_gating_enable_edge_detect_xform {true}
rt::set_parameter clock_gating_enable_stability_latch_removal {true}
rt::set_parameter clock_gating_enable_stability_latch_removal_before_gcc {true}
rt::set_parameter clock_gating_gating_patterns {band_bor_bnand_bnor}
rt::set_parameter clock_gating_handle_stability_latch_new {true}
rt::set_parameter clock_gating_merge_divBy2_retiming {true}
rt::set_parameter clock_gating_newCGExtraction {4}
rt::set_parameter clock_gating_new_flow {true}
rt::set_parameter clock_gating_olympus {true}
rt::set_parameter clock_gating_remove_user_inst_attribute {false}
rt::set_parameter clock_gating_retarget_old_primitives {true}
rt::set_parameter clock_gating_retiming_strategy {2}
rt::set_parameter clock_gating_sequential_types {ff_flop_latch_bram_srl_dsp_dmem_uram}
rt::set_parameter clock_gating_testcase_generation_mode {false}
rt::set_parameter clock_gating_true_forward_traversal {false}
rt::set_parameter clock_gating_use_nlopt {false}
rt::set_parameter clock_gating_use_slack {false}
rt::set_parameter clock_gating_work_on_structural_netlist {true}
rt::set_parameter clock_gating_work_with_multiple_clock_nets {false}
rt::set_parameter cltrlSetExtraction_2020_1 {true}
rt::set_parameter collapseAdderBconc {true}
rt::set_parameter collapseLutFanoutHeuristic {true}
rt::set_parameter collapseLutSlackThreshold {3}
rt::set_parameter collapseOperatorAtReinfer {false}
rt::set_parameter collapsePrioMux {true}
rt::set_parameter collapsePrioMuxDebug {false}
rt::set_parameter collapseThreshold {3000}
rt::set_parameter collectAllLoops {false}
rt::set_parameter columnOpt {true}
rt::set_parameter combineCyLuts {true}
rt::set_parameter combineLutInstPairThreshold {1000}
rt::set_parameter combineLuts {false}
rt::set_parameter combineLutsAggressiveMode {0}
rt::set_parameter combineLutsAggressively {false}
rt::set_parameter combineLutsCheckInputPort {true}
rt::set_parameter combineLutsCheckOutputPort {true}
rt::set_parameter combineLutsForBuses {false}
rt::set_parameter combineLutsForUserInst {false}
rt::set_parameter combineLutsLevelDiff {3}
rt::set_parameter combineLutsLutRegisterCheck {true}
rt::set_parameter combineLutsLutRegisterCheck2 {true}
rt::set_parameter combineLutsPostRebuildHierarchy {true}
rt::set_parameter combineLutsRuntimeFix {true}
rt::set_parameter combineLutsTimingCallRuntimeFix {true}
rt::set_parameter combineLutsUseLevel {false}
rt::set_parameter combineLutsVersalSixInputs {true}
rt::set_parameter combinedReinferAreaOptFlow {true}
rt::set_parameter complexDspPostInferenceFix {true}
rt::set_parameter considerOptRegForDelayEstInRamGen {true}
rt::set_parameter constPropBram {true}
rt::set_parameter constPropCarry {true}
rt::set_parameter constPropDram {true}
rt::set_parameter constPropDsp {true}
rt::set_parameter constPropLookahead8 {true}
rt::set_parameter constPropUram {true}
rt::set_parameter constantPropRamData {true}
rt::set_parameter controlSetOptPostMapReduceCtrlSets {false}
rt::set_parameter controlSetsOptSkipIOconnectedFlops {true}
rt::set_parameter convCmpToEq {false}
rt::set_parameter convGndToVcc {false}
rt::set_parameter convGndToVccBram {false}
rt::set_parameter convGndToVccDsp {false}
rt::set_parameter convGndToVccRegister {false}
rt::set_parameter convGndToVccUram {false}
rt::set_parameter convInvToLut1 {true}
rt::set_parameter convUMinusToAdder {true}
rt::set_parameter convertLoopToLatch {true}
rt::set_parameter convertMergeConstructToRom {true}
rt::set_parameter convertShortCarryChain {true}
rt::set_parameter copyRangeCarrySaveInGrouper {true}
rt::set_parameter copyUseDspAttrFromReg {true}
rt::set_parameter createDualPortRomPartition {true}
rt::set_parameter createGenomesForOutsideGenomeInsts {true}
rt::set_parameter createUndoSyncControlPartition {true}
rt::set_parameter criticalSigOpt {true}
rt::set_parameter criticalSigOptAttrInReinfer {true}
rt::set_parameter criticalSigOptInDFG {true}
rt::set_parameter crossClockDomainRetiming {true}
rt::set_parameter cutCostModifierForFirstMapbuf3_1 {false}
rt::set_parameter cutSelectStyle {0}
rt::set_parameter cvrtShrtCarryUltrascaleDiablo {false}
rt::set_parameter dSPCheckUminusByDriver {true}
rt::set_parameter datapathAddCarrySelThreshold {160}
rt::set_parameter datapathAddCheckRegLoad {false}
rt::set_parameter datapathAddTimingThresholdCLA {16}
rt::set_parameter datapathAddVersal {false}
rt::set_parameter datapathComparatorFanoutThreshold {-1}
rt::set_parameter datapathComparatorMaxBitsPerStage {5}
rt::set_parameter datapathComparatorThresholdHeuristicEverest {true}
rt::set_parameter datapathComparatorTimingThreshold {11}
rt::set_parameter datapathEqCarry4Height {12}
rt::set_parameter datapathEqOptimizeConstantBits {false}
rt::set_parameter datapathEqTimingThreshold {8}
rt::set_parameter datapathEqUpperThreshold {288}
rt::set_parameter datapathIncThreshold {40}
rt::set_parameter datapathIncThresholdCLA {11}
rt::set_parameter datapathInferThreshold {3}
rt::set_parameter debugCollapseAdderBconc {false}
rt::set_parameter debugDspComplexMult {0}
rt::set_parameter debugDspDotProduct {0}
rt::set_parameter debugDspTernaryInfer {0}
rt::set_parameter debugLAddInfer {false}
rt::set_parameter debugLoopDetect {false}
rt::set_parameter debugNetlistDiffer {false}
rt::set_parameter debugRomColumnOpt {false}
rt::set_parameter debugSrlGen {0}
rt::set_parameter debugUtilityCriticalSigOptInDFG {0}
rt::set_parameter decloneBrams {true}
rt::set_parameter decloneBramsV10 {true}
rt::set_parameter decloneBramsV10Debug {false}
rt::set_parameter decompLargeUnaryOp {true}
rt::set_parameter decompMult {true}
rt::set_parameter decompUramForMaxTiming {false}
rt::set_parameter decompUramForOptTiming {true}
rt::set_parameter decomposeAdderForDspDotProduct {true}
rt::set_parameter decomposeHighFaninLut6 {false}
rt::set_parameter deleteLoadlessLookAhead8 {false}
rt::set_parameter depthConstraintForExactArea {false}
rt::set_parameter depthDrivenCarryChain {false}
rt::set_parameter depthDrivenCarryChainLoad {false}
rt::set_parameter depthFirstMapbuf31Mapping {false}
rt::set_parameter depthFirstMapbuf31MappingFix {true}
rt::set_parameter dfgLevelThresholdRomAddressRegPacking {4}
rt::set_parameter disableConstProp {true}
rt::set_parameter disableControlSetsOptForKeepDontTouch {true}
rt::set_parameter disableDataPathWithLoopBackReinfer {true}
rt::set_parameter disableEnaOptForPowerOpt {true}
rt::set_parameter disableGatedClockPreCheck {false}
rt::set_parameter disableHighEffortMap {false}
rt::set_parameter disableOregPackingUram {false}
rt::set_parameter disconnectDanglingFlopWhenPackReg {true}
rt::set_parameter displayFullNameInRamMessage {true}
rt::set_parameter dissolveDSPPartition {false}
rt::set_parameter dissolveElabPartitions {false}
rt::set_parameter dissolveHlsDspModule {true}
rt::set_parameter dissolveSoftKeepHiers {false}
rt::set_parameter dissolveTimingDriven {false}
rt::set_parameter doAsymURamPipeline {true}
rt::set_parameter doBRAMResourceManagement {true}
rt::set_parameter doBramPowerOpt {true}
rt::set_parameter doDspResourceManagement {true}
rt::set_parameter doExtAsymBramAreaOpt {true}
rt::set_parameter doIncrementalTimingOpt {false}
rt::set_parameter doRamPipeLineAfterResourceManagement {false}
rt::set_parameter doRamPipeline {true}
rt::set_parameter doStructuralOpt {false}
rt::set_parameter doURAMResourceManagement {true}
rt::set_parameter dontOptimizeXorDrivingXorCy {false}
rt::set_parameter dontSetDontTouch {}
rt::set_parameter dsp48e2FixComplexMacc {true}
rt::set_parameter dspAbsorbDynamicControlRegs {false}
rt::set_parameter dspAbsorbInvOnCtrl {false}
rt::set_parameter dspActivateUseDSPDirective {true}
rt::set_parameter dspAdderDecompSplitOutReg {true}
rt::set_parameter dspAlignRegs {true}
rt::set_parameter dspAllowMultiFanoutForSumOfProduct {false}
rt::set_parameter dspAllowMuxAsSimpleSource {true}
rt::set_parameter dspAlwaysInferDynamic {false}
rt::set_parameter dspApplyUtilizationControl {true}
rt::set_parameter dspCascade {auto}
rt::set_parameter dspCascadeFix {true}
rt::set_parameter dspCascadeLengthFromSOP {100}
rt::set_parameter dspChainDecompNaryAdder {false}
rt::set_parameter dspCheckBeforeAlignRegs {true}
rt::set_parameter dspCheckDSPStartNodeMux {true}
rt::set_parameter dspCollapseConstMult {true}
rt::set_parameter dspComplexInferCascade {true}
rt::set_parameter dspConvertMult2DynDsp {true}
rt::set_parameter dspConvertMult2DynDspMethod {2}
rt::set_parameter dspCreateDummyAdderForMux {true}
rt::set_parameter dspCutFilterInDfg {true}
rt::set_parameter dspCutFilterInNetlist {false}
rt::set_parameter dspDebugLevel {1}
rt::set_parameter dspDecompAdderTernary {true}
rt::set_parameter dspDecompConstMultHeuristic {true}
rt::set_parameter dspDecompMultRevealSignedMult {false}
rt::set_parameter dspDecompMultWithConst {true}
rt::set_parameter dspDelayMultiplierMapWithUnknownLoad {false}
rt::set_parameter dspDisableAdderInputSizeCheck {false}
rt::set_parameter dspDisableDoubleDynamic {false}
rt::set_parameter dspDissolveNested {true}
rt::set_parameter dspDontAbsorbPRegOnAccumLoop {true}
rt::set_parameter dspFixAddSub {true}
rt::set_parameter dspFixInstantiated {false}
rt::set_parameter dspFixInvalidIter {2}
rt::set_parameter dspFixMuxOnAdderInput {true}
rt::set_parameter dspFixOperInputDriver {true}
rt::set_parameter dspFixSignedIssueInAbsorbReg {true}
rt::set_parameter dspFixSubOnAdderInput {2}
rt::set_parameter dspFixSystolicFilter {true}
rt::set_parameter dspFixTernaryAddInCascade {true}
rt::set_parameter dspFixTernaryWithRoundingConst {true}
rt::set_parameter dspFlattenBeforeReinfer {true}
rt::set_parameter dspFlattenDspHierarchy {false}
rt::set_parameter dspFloatUnusedDataPins {true}
rt::set_parameter dspFoldSTCFilters {true}
rt::set_parameter dspForceUnpackRegisters {false}
rt::set_parameter dspInferAdder {true}
rt::set_parameter dspInferDynamic {true}
rt::set_parameter dspInferDynamicInSynth {false}
rt::set_parameter dspInferPreAddPostAddInCascade {false}
rt::set_parameter dspInferPreaddSquare {1}
rt::set_parameter dspInferTernaryAccum {true}
rt::set_parameter dspMoveABtoMTimingDriven {true}
rt::set_parameter dspMoveMregToPregDynamicOpmode {true}
rt::set_parameter dspMoveMuxToOutput {2}
rt::set_parameter dspMoveMuxToPreAdderOutput {2}
rt::set_parameter dspMovePregToMreg {true}
rt::set_parameter dspMultDecompPrepInputs {true}
rt::set_parameter dspMultSizeUp {true}
rt::set_parameter dspNlDspDebug {false}
rt::set_parameter dspNormalizeInSize {true}
rt::set_parameter dspNormalizeTernaryAccumLoop {true}
rt::set_parameter dspNormalizeUMinus {true}
rt::set_parameter dspPackABReg2 {true}
rt::set_parameter dspPackCombinational {true}
rt::set_parameter dspPackCtrlRegAllowVdd {false}
rt::set_parameter dspPackInverters {true}
rt::set_parameter dspPackOpmode {true}
rt::set_parameter dspPackOpmodeRegForRegisteredInputs {true}
rt::set_parameter dspPackOverflow {false}
rt::set_parameter dspPackPtoCLoop {true}
rt::set_parameter dspPackRegisters {true}
rt::set_parameter dspPackRnd {true}
rt::set_parameter dspPostInferenceFix {true}
rt::set_parameter dspPostProcess {255}
rt::set_parameter dspPreInferRegister {false}
rt::set_parameter dspReconstructMux {false}
rt::set_parameter dspReconstructMuxSub {true}
rt::set_parameter dspReconstructSub {false}
rt::set_parameter dspRecoverPatternDetect {true}
rt::set_parameter dspRecoverUnsignedUMinus {true}
rt::set_parameter dspReduceDspRegSize {true}
rt::set_parameter dspReduceRegSize {true}
rt::set_parameter dspReduceUminusInputReg {true}
rt::set_parameter dspReinferTimingDriven {false}
rt::set_parameter dspRelocateABReg {true}
rt::set_parameter dspRelocateMRegToPReg {false}
rt::set_parameter dspRelocatePReg {true}
rt::set_parameter dspRelocateRegisters {true}
rt::set_parameter dspRelocateRegisters4Olympus {false}
rt::set_parameter dspReplicate4Reg {2}
rt::set_parameter dspReplicateOnlyIfFullyPipelined {false}
rt::set_parameter dspReportPacking {1}
rt::set_parameter dspResource {-1}
rt::set_parameter dspResourceSharing {false}
rt::set_parameter dspRestoreUnusedOps {3}
rt::set_parameter dspRetimeOverMult4DSP {true}
rt::set_parameter dspRetimeRegNearMultiplier {true}
rt::set_parameter dspRevealFakeTrim {true}
rt::set_parameter dspSimplifyConns {3}
rt::set_parameter dspSimplifyIOs {false}
rt::set_parameter dspSimplifyOutConn {true}
rt::set_parameter dspSimplifySignExtension {false}
rt::set_parameter dspSumOfProductInputThreshold {2}
rt::set_parameter dspSwapAdderInputsForSharedMult {true}
rt::set_parameter dspTrackUminusDecomp {false}
rt::set_parameter dspTreeDecompNaryAdder {false}
rt::set_parameter dspTrimDeadRegBits {true}
rt::set_parameter dspTrimSignBits {true}
rt::set_parameter dspUnpackRegisters {true}
rt::set_parameter dspUserCascLength {-1}
rt::set_parameter dspValidateOpmodeReg {true}
rt::set_parameter dspWireHourGlassFix {true}
rt::set_parameter dsppackRegistersBeforeInferSrl {false}
rt::set_parameter dumpOperatorReportIn {both}
rt::set_parameter dumpSrl2BramOnespin {false}
rt::set_parameter earlyMapForLUTCascBitslice {true}
rt::set_parameter edifCaseInsensitive {true}
rt::set_parameter edifCopyModule {false}
rt::set_parameter elaborateOnly {false}
rt::set_parameter elaborateRtlOnlyFlow {false}
rt::set_parameter enableBalancedMemoryInference {false}
rt::set_parameter enableBramPowerOpt {false}
rt::set_parameter enableContrlConversion {true}
rt::set_parameter enableCustomAttributeHandling {true}
rt::set_parameter enableDynamicCascadeHeight {true}
rt::set_parameter enableEnhancedRomInference {true}
rt::set_parameter enableEquivArrayDump {true}
rt::set_parameter enableExtractControlAttributes {true}
rt::set_parameter enableFlatMapping {false}
rt::set_parameter enableGenerateCore {false}
rt::set_parameter enableHlsRamPipeline {false}
rt::set_parameter enableIterativeIncrementalSynthesis {true}
rt::set_parameter enableKeepHierarchy {true}
rt::set_parameter enableLutMapping {false}
rt::set_parameter enableMergeClones {true}
rt::set_parameter enableMixedRamPipeline {true}
rt::set_parameter enableMuxf8Mapping {true}
rt::set_parameter enableMuxf9Mapping {false}
rt::set_parameter enableMuxfMapping {true}
rt::set_parameter enableNetNamesBasedOnInstanceNames {false}
rt::set_parameter enableNetlistDiffer {true}
rt::set_parameter enableParallelHelperSpawn {true}
rt::set_parameter enableRenamingGeneratedNetNames {true}
rt::set_parameter enableRenamingGeneratedPortNames {true}
rt::set_parameter enableRetimeMatching {false}
rt::set_parameter enableSmartLutramThreshold {true}
rt::set_parameter enableSynthDesignFanoutLimitSwitch {false}
rt::set_parameter enableSynthPlace {false}
rt::set_parameter enableUnchangedSiblingGenomeReuse {false}
rt::set_parameter enableUndoControlSetOverlap {false}
rt::set_parameter enableUndoSyncControlForAsyncReg {true}
rt::set_parameter enableUramInputPipe {true}
rt::set_parameter enableUramPipelineWithConstProp {true}
rt::set_parameter enableVersalTDRamGen {true}
rt::set_parameter enableXpmURamORegPackingForReadLatency2 {false}
rt::set_parameter enforcePullFirstSrlRegister {false}
rt::set_parameter estimationFlow {false}
rt::set_parameter everestImprove {true}
rt::set_parameter everestImprove2 {true}
rt::set_parameter extendCarryBottom {false}
rt::set_parameter extendLGt2Even {true}
rt::set_parameter extractLoadableAdd {false}
rt::set_parameter extractSyncControlThreshold {3}
rt::set_parameter extractSyncCtrl {true}
rt::set_parameter extractSyncCtrlThreshold {8}
rt::set_parameter fanInThresholdForLut6Decomposition {2147483647}
rt::set_parameter fanoutAsyncRetiming {true}
rt::set_parameter fanoutLimitBigBlockMaxFanout {4}
rt::set_parameter fanoutLimitBigBlockNoMaxFanout {10}
rt::set_parameter fanoutOptCriticalRange {25}
rt::set_parameter fanoutOptIterations {3}
rt::set_parameter fanoutStep {1000}
rt::set_parameter fanoutStepCritical {1000}
rt::set_parameter finalCleanupUndriven {true}
rt::set_parameter firFolding {false}
rt::set_parameter fixDspAdderWithTwoSingleBitInput {true}
rt::set_parameter fixDspAlignRegister {false}
rt::set_parameter fixDspCascadeDrcAcout {true}
rt::set_parameter fixDspCascadeDrcPcout {false}
rt::set_parameter fixEdifLongName {true}
rt::set_parameter fixEdifName {true}
rt::set_parameter fixSmallModDissolve {false}
rt::set_parameter fixVersalSRLs {true}
rt::set_parameter fixedLutPair {true}
rt::set_parameter flattenCheckCrcModule {false}
rt::set_parameter flattenHierarchyValue {4}
rt::set_parameter flattenInsideGenome {false}
rt::set_parameter flattenRemoveDfg {false}
rt::set_parameter foldDebugLevel {0}
rt::set_parameter foldDuplicates {0}
rt::set_parameter foldMinGateCount {100}
rt::set_parameter foptBigBlock {true}
rt::set_parameter foptSkipHFO {0}
rt::set_parameter forceArchitecture {-1}
rt::set_parameter forceBramPowerDecomp {false}
rt::set_parameter forceCinToOneForBufferCy {false}
rt::set_parameter forceDspMultThresholdCheck {false}
rt::set_parameter forceMuxPartForFsmOneHotMux {true}
rt::set_parameter forceRegenAllRams {true}
rt::set_parameter forcedParallelForSblock {false}
rt::set_parameter gatedClockConversion {0}
rt::set_parameter genXpmRamFromBlackbox {true}
rt::set_parameter genXpmRomWithNoOpt {false}
rt::set_parameter generateDsps {true}
rt::set_parameter generateMux41Cuts {true}
rt::set_parameter genomeToBeProcessedSequentially {}
rt::set_parameter getOperatorReport {false}
rt::set_parameter globalStrapsFilename {global_name.straps.rtd}
rt::set_parameter goAcrossFlopsInFoptToposort {false}
rt::set_parameter groupBigMux {true}
rt::set_parameter groupLargeShiftRegisters {false}
rt::set_parameter handleMaxFanoutChange {true}
rt::set_parameter handleRetimingChangeInIncrementalSynthesis {true}
rt::set_parameter helper_shm_key {LaunchHelperProcessKey_3622754_1783489524}
rt::set_parameter highEffortMap {false}
rt::set_parameter highEffortMapCriticalityCheck {true}
rt::set_parameter highEffortMapCriticalityCheck2 {false}
rt::set_parameter highEffortMapCriticalityCheck3 {false}
rt::set_parameter highEffortMapDampenFactor {0}
rt::set_parameter highFreqLimit {2}
rt::set_parameter honorAllSoftKeepHiers {true}
rt::set_parameter honorRamStyleInResourceBalancing {true}
rt::set_parameter hoptPostCollapseMuxChain {2}
rt::set_parameter ignoreMaxFanoutGlobally {false}
rt::set_parameter ignoreMaxFanoutOnTimingAssertInsts {false}
rt::set_parameter implementLGUsingLut4 {true}
rt::set_parameter inTimingModeInAreaOpt {0}
rt::set_parameter inactiveRamWriteEnableOpt {true}
rt::set_parameter incrementalGDGNew {true}
rt::set_parameter incrementalGDGTraverseNetlist {true}
rt::set_parameter inferAbs {false}
rt::set_parameter inferAddSub {true}
rt::set_parameter inferAddSubPattern3 {true}
rt::set_parameter inferAsymBramForMinArea {true}
rt::set_parameter inferAsymURam {true}
rt::set_parameter inferBDPreAdder {true}
rt::set_parameter inferBinaryMux {true}
rt::set_parameter inferBramForMaxTiming {false}
rt::set_parameter inferBramForMinArea {false}
rt::set_parameter inferBramWithParity {true}
rt::set_parameter inferClkBufForSynchronizers {false}
rt::set_parameter inferCounter {true}
rt::set_parameter inferCounterFix {true}
rt::set_parameter inferCounterGenQorFix {true}
rt::set_parameter inferDspComplexMult {true}
rt::set_parameter inferDspDynamicMultNegate {true}
rt::set_parameter inferDspFoldingAllowOnlyConstantControl {false}
rt::set_parameter inferDspFoldingAroundOutputAdder {true}
rt::set_parameter inferDspFoldingAutoGenerateClock {false}
rt::set_parameter inferDspSimd {true}
rt::set_parameter inferDspSimdCarryoutOpt {true}
rt::set_parameter inferDspSimdGroupCarryin {false}
rt::set_parameter inferDspSimdHandleMismatchedWidth {true}
rt::set_parameter inferDspSimdSkipCarryoutOptForOneSigned {false}
rt::set_parameter inferDspsSkipPass {0}
rt::set_parameter inferDynamicSrlGenericRegChain {true}
rt::set_parameter inferDynamicSrlPattern1AllowOtherFanout {true}
rt::set_parameter inferDynamicSrlPattern2AllowOtherFanout {true}
rt::set_parameter inferEverestExtendedAsymRam {true}
rt::set_parameter inferExtRamReg {true}
rt::set_parameter inferInputCascadePathDspCplx {true}
rt::set_parameter inferLoadableAdd {true}
rt::set_parameter inferLogicDsp {false}
rt::set_parameter inferLut6_2 {false}
rt::set_parameter inferMixedRam {true}
rt::set_parameter inferMixedRamXpm {false}
rt::set_parameter inferMultiPortRam {true}
rt::set_parameter inferMuxOpt {3}
rt::set_parameter inferMuxOptFromLoop {false}
rt::set_parameter inferMuxPart {true}
rt::set_parameter inferNActiveHighLowCircuit {false}
rt::set_parameter inferOutputCascadeForDspComplex {true}
rt::set_parameter inferOutputCascadeFromPtoCPath {true}
rt::set_parameter inferPipelineAwareURam {true}
rt::set_parameter inferPostSubInDspComplexMult {true}
rt::set_parameter inferRegPart {true}
rt::set_parameter inferRom {true}
rt::set_parameter inferSignInv {true}
rt::set_parameter inferStaticSrl {true}
rt::set_parameter inferStaticSrlAsBram {false}
rt::set_parameter inferStaticSrlAsBramMasterSwitch {true}
rt::set_parameter inferStaticSrlAsBramThreshold {1024}
rt::set_parameter inferStaticSrlAsBramUseOutReg {true}
rt::set_parameter inferStaticSrlUsingCascade {0}
rt::set_parameter inferTernaryAdd {true}
rt::set_parameter inferTernaryAddForced {false}
rt::set_parameter inferURam {true}
rt::set_parameter inferURamAuto {true}
rt::set_parameter inferWidegate {false}
rt::set_parameter insertLut1InPortWithMarkDebug {false}
rt::set_parameter insertLutForOutputKeep {false}
rt::set_parameter insertPassThroughLuts {false}
rt::set_parameter intelligentSeep {false}
rt::set_parameter internalClkBufThreshold {32}
rt::set_parameter ioVerbose {0}
rt::set_parameter isEfinix {false}
rt::set_parameter jitterSkipLoopElemCount {-1}
rt::set_parameter keepAutopipelineAttributes {true}
rt::set_parameter keepHierForMarkDebugOnPorts {true}
rt::set_parameter keepLastRegOutForLargeMultiplier {true}
rt::set_parameter keepRegPartitionToPreMap {false}
rt::set_parameter keepRegPartitionToRegenram {true}
rt::set_parameter lAddInferDetectUminus {true}
rt::set_parameter lAddInferSkipMultiLoadAdder {false}
rt::set_parameter lSFMonitorFrequency {60}
rt::set_parameter largeBRamThreshold {64}
rt::set_parameter leaveRamRegOutOfDSP {true}
rt::set_parameter levelDelayFactor {5000}
rt::set_parameter limitModuleNameLen {255}
rt::set_parameter limitURamColHeightToPowerOfTwo {false}
rt::set_parameter logRamAuxReport {false}
rt::set_parameter loopOptimize {false}
rt::set_parameter lsfLaunchTimeout {1200}
rt::set_parameter lut2LutCostOnlyInWireMap {false}
rt::set_parameter lutMapFreezeTimer {1}
rt::set_parameter lutPairBeforeUniquify {false}
rt::set_parameter lutPairFanoutThreshold {30}
rt::set_parameter lutPairSlackThreshold {0}
rt::set_parameter lutPairSlackThresholdRange {1}
rt::set_parameter lutPairSlackThresholdRange2 {2}
rt::set_parameter lutPairingFixForPositiveSlack {false}
rt::set_parameter lutSize {6}
rt::set_parameter lutSplittingFanoutLimit {50}
rt::set_parameter lutSplittingSizeLimit {3}
rt::set_parameter lutcyInternalFix {true}
rt::set_parameter lutmapF7rentThreshold {0.700000}
rt::set_parameter lutmapF8rentThreshold {0.600000}
rt::set_parameter lutmapUseRentParameter {false}
rt::set_parameter macroClusterIncludeMultiType {true}
rt::set_parameter macroClusterSizeLimit {50}
rt::set_parameter mapBlockRam {true}
rt::set_parameter mapBlockRamTimingDriven {true}
rt::set_parameter mapBlockRamTimingDrivenAddrSize {10}
rt::set_parameter mapBlockRamTimingDrivenAddrSize2 {12}
rt::set_parameter mapBlockRamTimingDrivenRamSize {32768}
rt::set_parameter mapBlockRamTimingDrivenRestricted {false}
rt::set_parameter mapBlockRamTimingDrivenTotalSize {163840}
rt::set_parameter mapBufAtConstInputGate {true}
rt::set_parameter mapFanoutThreshold {127}
rt::set_parameter mapFlowOption {18}
rt::set_parameter mapInRegenerate {false}
rt::set_parameter mapLutRam {true}
rt::set_parameter mapMapbuf31AreaCostReduction {0}
rt::set_parameter mapMarkDrivenByLut {true}
rt::set_parameter mapPruneCutsByRequiredTime {true}
rt::set_parameter mapRuntimeFix {1}
rt::set_parameter mapUseEstimatedTime {true}
rt::set_parameter mapUseEstimatedTimeForCarry {true}
rt::set_parameter mapUseEstimatedTimeForCarryLevel {2}
rt::set_parameter mapUseEstimatedTimeForSrl {false}
rt::set_parameter mapUseEstimatedTimeForSrlLevel {1}
rt::set_parameter mapperRunTimeFix {true}
rt::set_parameter markDebugPreservationLevel {enable}
rt::set_parameter markHighFanoutNetForRetime {false}
rt::set_parameter markInstKeepForMarkDebug {true}
rt::set_parameter markKeepHierarchyOnInsts {true}
rt::set_parameter maxAdaptFFPercent {-1}
rt::set_parameter maxBSelSelectRangeInXilinxLogicGen {16}
rt::set_parameter maxBramCascChainLength {8}
rt::set_parameter maxBramCascChainLengthTD {4}
rt::set_parameter maxBufgInsertForClockGating {4}
rt::set_parameter maxClockBufferCount {12}
rt::set_parameter maxDRamPrimAddrWidth {-1}
rt::set_parameter maxDissolveSize {1000}
rt::set_parameter maxDspLimitSeep {0}
rt::set_parameter maxFanOutForPartitionnedRegisters {100}
rt::set_parameter maxFanoutReplicateDriverOfLUT1 {true}
rt::set_parameter maxFanoutThroughInvBuf {true}
rt::set_parameter maxFlopLimitSeep {0}
rt::set_parameter maxLutLimitSeep {0}
rt::set_parameter maxLutramAddrSize {18}
rt::set_parameter maxLutramMemSize {262144}
rt::set_parameter maxNumCutsPerBucket {10000}
rt::set_parameter maxNumCutsPerNode {300}
rt::set_parameter maxRamAddrSize {32}
rt::set_parameter maxRamLimitSeep {0}
rt::set_parameter maxRomAddrWidth {25}
rt::set_parameter maxRomAddrWidthToReinfer {18}
rt::set_parameter maxRomTotalSizeToReinfer {1048576}
rt::set_parameter maxURamAddrSize {23}
rt::set_parameter maxURamCascChainLength {8}
rt::set_parameter mergeBramOutRegs {true}
rt::set_parameter mergeClonesInAllModules {false}
rt::set_parameter mergeClonesSkipUserInstances {true}
rt::set_parameter mergeLUTRAMConstChk {true}
rt::set_parameter mergeLutRam {6}
rt::set_parameter mergeMuxesWriteFirstRam {false}
rt::set_parameter mergeRtlRAMs {false}
rt::set_parameter mergeTernaryAdderInSingleDsp {true}
rt::set_parameter minClockBufferFanout {5}
rt::set_parameter minInstsInControlSet {4}
rt::set_parameter minInstsInControlSetPostMap {8}
rt::set_parameter minRomAddrWidth {5}
rt::set_parameter minURamAddrSize {11}
rt::set_parameter minURamTotalSize {147456}
rt::set_parameter minURamWidth {36}
rt::set_parameter minimizeCounterWidth {true}
rt::set_parameter multDfltUsePreg {true}
rt::set_parameter multFactorForLAddRegen {3}
rt::set_parameter muxFMacroMap {false}
rt::set_parameter muxFMacroMapLevel {2}
rt::set_parameter muxImplementationStyle {auto}
rt::set_parameter muxInputDfgLevelThresholdForCounter {4}
rt::set_parameter muxSameSelectOpt {false}
rt::set_parameter muxpartDebug {0}
rt::set_parameter newBypassKeepFlow {true}
rt::set_parameter newExtRamRegFlow {true}
rt::set_parameter newFoptBypassKeepFlow {true}
rt::set_parameter newLUT6CYRecover {true}
rt::set_parameter newLUT6CYRecoverBufferOnly {false}
rt::set_parameter newNetDelayModelForEverest {1}
rt::set_parameter nlOptMaxInstanceCount {1000000}
rt::set_parameter nlOptMaxSolnsUsingSmartML {2}
rt::set_parameter nlOptMuxpart {false}
rt::set_parameter nlOptRom {1}
rt::set_parameter nlOptSmartMLSupportedDevice {10}
rt::set_parameter nloptRunOnlyCommonAlgo {false}
rt::set_parameter nloptSmartMLPredictionDebug {0}
rt::set_parameter noPenaltyForMAPBUF3_1 {false}
rt::set_parameter noRecodeOutsideMuxpart {true}
rt::set_parameter noRemapForMapBuf31 {true}
rt::set_parameter nodeListTraversal {true}
rt::set_parameter olympusDistributedRamSupport {true}
rt::set_parameter oneHotMuxDuplicateInputThreshold {0.500000}
rt::set_parameter optAddCarryAdd {false}
rt::set_parameter optCarryDi {false}
rt::set_parameter optConstBMerge {false}
rt::set_parameter optInTryRecoverLUT6CY {false}
rt::set_parameter optMergeLut1s {true}
rt::set_parameter optMuxcyDiFix {true}
rt::set_parameter optNewCollapseMerge {1}
rt::set_parameter optNewCollapseMergeForComp {false}
rt::set_parameter optVerbose {0}
rt::set_parameter optimizeControlSetOverlap {true}
rt::set_parameter optimizeRamModuleWithDontTouch {true}
rt::set_parameter optimizeUramPipeLatency {false}
rt::set_parameter optimizeUserInstantiatedCarry {false}
rt::set_parameter packBramOutRegs {true}
rt::set_parameter packBramOutRegsAllowSet {true}
rt::set_parameter packCarry4 {true}
rt::set_parameter packCarrys {true}
rt::set_parameter packCarrysEverest {true}
rt::set_parameter packDspAsyncPRegs {true}
rt::set_parameter packDspRegs {false}
rt::set_parameter packEccRegInBram {true}
rt::set_parameter packLookaheadsEverest {true}
rt::set_parameter packOpAtAddress {true}
rt::set_parameter packOpAtDataOut {true}
rt::set_parameter packOpAtDataOutForMultiFanout {false}
rt::set_parameter packOregEccInUram {true}
rt::set_parameter packUramOutRegs {true}
rt::set_parameter packUserCarrys {false}
rt::set_parameter parallelFlowMaxMsgs {1000}
rt::set_parameter parallelHelperWaitForChild {true}
rt::set_parameter parallelHelperWaitingTime {10}
rt::set_parameter parallelInstCountThreshold {false}
rt::set_parameter parallelMinSize {10000}
rt::set_parameter parallelOOCTimingFlow {false}
rt::set_parameter parallelSortJobs {true}
rt::set_parameter parallelTimingMinSize {10000}
rt::set_parameter parallelTimingTest {false}
rt::set_parameter partCB {false}
rt::set_parameter partitionAllMuxesMinSel {3}
rt::set_parameter partitionAllMuxesMinWidth {4}
rt::set_parameter partitionMuxesMinSize {128}
rt::set_parameter partitionMuxesNew {true}
rt::set_parameter passMaxFanoutToBackendControlLoads {false}
rt::set_parameter perfStrategy {0}
rt::set_parameter pipeLineBram {true}
rt::set_parameter pipeLineDram {true}
rt::set_parameter pipeLineUram {true}
rt::set_parameter pipeLineUramWarningRatio {4}
rt::set_parameter populateRomReportData {true}
rt::set_parameter powerStrategy {0}
rt::set_parameter precomputeCuddLimit {200}
rt::set_parameter precomputeDebug {0}
rt::set_parameter precomputeInputCardinality {2}
rt::set_parameter precomputeMaxInputSize {30}
rt::set_parameter precomputeMaxOutputSize {10}
rt::set_parameter precomputeMinInputSize {2}
rt::set_parameter precomputeMinOutputSize {1}
rt::set_parameter precomputePathLimit {1000.000000}
rt::set_parameter preferMuxf8 {false}
rt::set_parameter preferPriorityMuxGenerator {true}
rt::set_parameter prepDspMultToShift {true}
rt::set_parameter prepDsps {true}
rt::set_parameter prepDspsSkipPass {0}
rt::set_parameter prepRams {true}
rt::set_parameter prepRoms {true}
rt::set_parameter preserveExtramPartition {false}
rt::set_parameter preserveRAMPartition {false}
rt::set_parameter preserveSelectedDp {false}
rt::set_parameter printIntelligentSeepInst {false}
rt::set_parameter prioMuxAndOrImpl {true}
rt::set_parameter prioMuxDuplicateInputThreshold {0.500000}
rt::set_parameter prioToBinaryMuxOpt {true}
rt::set_parameter prioToBinaryMuxOptTopo {true}
rt::set_parameter prioToBinaryMuxZeroAndOne {false}
rt::set_parameter processNonGenomeDependents {false}
rt::set_parameter propagateAllXpm {true}
rt::set_parameter propagateIntPortAttr {true}
rt::set_parameter propagateMuxcyFix {true}
rt::set_parameter pullFirstSrlRegister {true}
rt::set_parameter pullLastSrlRegister {true}
rt::set_parameter pullLossyPreAddInDsp {true}
rt::set_parameter pullOutLastRegFromSrlInFopt {true}
rt::set_parameter pushInvAcrossFlops {true}
rt::set_parameter pushInvAllowFanoutFromQ {true}
rt::set_parameter pushInvFanoutLimit {30}
rt::set_parameter pushInvForAllFlops {false}
rt::set_parameter pushInvForceINITOnFlop {true}
rt::set_parameter pushInvOnlyCEload {true}
rt::set_parameter pushInvOnlyForLutDrivenFlop {false}
rt::set_parameter putConstBMergeInRtlBox {false}
rt::set_parameter pwroptLUTRAMDepth {64}
rt::set_parameter pwroptLUTRAMSlack {100.000000}
rt::set_parameter ramPipeLineVerbosity {0}
rt::set_parameter ramPipelineDebug {false}
rt::set_parameter ramSynVerbose {0}
rt::set_parameter reSyncKeepFanOut {true}
rt::set_parameter readGenomeFromScheduler {true}
rt::set_parameter readLatencyCheckForXpmRomColumnOpt {true}
rt::set_parameter reasonToRevertToDefault {}
rt::set_parameter rebuildHierarchyBottomUp {false}
rt::set_parameter recodeMuxSelSizeThreshold {3}
rt::set_parameter recodeMuxes {2}
rt::set_parameter recognizeDsps {true}
rt::set_parameter reduceAminusA {false}
rt::set_parameter reduceCascadeLengthVariation {true}
rt::set_parameter reextractInGDG {false}
rt::set_parameter regenerateAsymRam {true}
rt::set_parameter regfile1DepthThreshold {2}
rt::set_parameter regfile1WidthThreshold {2}
rt::set_parameter regfile2DepthThreshold {4}
rt::set_parameter regfile2WidthThreshold {7}
rt::set_parameter regfile3DepthThreshold {8}
rt::set_parameter regfile3WidthThreshold {3}
rt::set_parameter reinferCascadeDspForMultiplier {false}
rt::set_parameter reinferMaxDissolveSize {2000}
rt::set_parameter reinferMuxLevel {3}
rt::set_parameter reinferMuxWidthThreshold {8}
rt::set_parameter removeAllRedundantSelBits {false}
rt::set_parameter removeBBoxDrivingMultiDrivenNets {false}
rt::set_parameter removeCarrySaveInfoFromEdges {true}
rt::set_parameter removeInternalLUTs {true}
rt::set_parameter removeInvalidSrlChainCand {true}
rt::set_parameter removeJitter {false}
rt::set_parameter removePassThruReg {false}
rt::set_parameter removeRedundantConnections {false}
rt::set_parameter removeRedundantOutsideRecode {true}
rt::set_parameter removeRedundantSelOfRom {true}
rt::set_parameter removeUnconnectedKeepHiers {true}
rt::set_parameter repFanoutThreshold {10000000}
rt::set_parameter replicateControlSignal {false}
rt::set_parameter replicateDriverRegWithLut {false}
rt::set_parameter replicateFaninLutInFopt {true}
rt::set_parameter replicateMuxSel {false}
rt::set_parameter reportDRamStats {false}
rt::set_parameter reportDspFinal {true}
rt::set_parameter reportDspNetlistDrc {true}
rt::set_parameter reportDspPreliminary {true}
rt::set_parameter reportInstantiatedPrimitives {false}
rt::set_parameter reportRTLAttributes {false}
rt::set_parameter reportURamCompatibility {false}
rt::set_parameter requiredTimeOffset {0}
rt::set_parameter resolveBramAddrCollision {false}
rt::set_parameter restrictMuxToBand {true}
rt::set_parameter restructureAdderComparator {true}
rt::set_parameter retargetFDCPE {false}
rt::set_parameter retimeConcatWithConstant {false}
rt::set_parameter retimeFromGateSlack {0}
rt::set_parameter retimeImprovement {2}
rt::set_parameter retimeLogicForRegisterInference {true}
rt::set_parameter romLutToGates {false}
rt::set_parameter routabilityStrategy {0}
rt::set_parameter rstSrlDepthThreshold {4}
rt::set_parameter rubikInMemoryFlow {false}
rt::set_parameter rubikPipelinedCE {false}
rt::set_parameter rubikPreservedModuleDontTouch {true}
rt::set_parameter rubikRebuildHierOptCommonAncestorSearch {true}
rt::set_parameter saveCarryGenThreshold {true}
rt::set_parameter scaleURAMPipeStageDelay {false}
rt::set_parameter sdxStrategy {0}
rt::set_parameter seepMode {}
rt::set_parameter selfCheckUtility {false}
rt::set_parameter setAuxNames {true}
rt::set_parameter setDontTouch {}
rt::set_parameter setRamGroupInfo {false}
rt::set_parameter setSRLBusName {true}
rt::set_parameter setZeroArrivalForInternalCarry {true}
rt::set_parameter sharedInputsThreshold {1}
rt::set_parameter shrinkOutRegInRomColumnOpt {true}
rt::set_parameter siblingModuleBindingBasedOnElabNameComparison {true}
rt::set_parameter simplifyAllEdgesInDspSimpConn {true}
rt::set_parameter simplifyShiftPatternMultiply {true}
rt::set_parameter simplifySignExtension {false}
rt::set_parameter simulateParallelSynthHelperForkError {false}
rt::set_parameter singleFanoutMuxfMapping {true}
rt::set_parameter skipConstPropDramForXpmMemory {true}
rt::set_parameter skipDspSEEP {false}
rt::set_parameter skipExtractSetResetForFBLoop {false}
rt::set_parameter skipRambSEEP {false}
rt::set_parameter skipRedundantTDRamGen {true}
rt::set_parameter skipReplFlopAndFaninLut {true}
rt::set_parameter skipReplicatingTimingAssertInsts {true}
rt::set_parameter slackThreshTDRamGen {50000}
rt::set_parameter smartResUtilSeep {0}
rt::set_parameter softKeepForMarkDebug {true}
rt::set_parameter sparseRomAddrDelta {3}
rt::set_parameter sparseRomMaxAddrSize {10}
rt::set_parameter sparseRomThreshold {0.250000}
rt::set_parameter spdAbc {false}
rt::set_parameter spdDupFree {true}
rt::set_parameter spdExcludeFailGate {true}
rt::set_parameter spdExcludeNewGate {false}
rt::set_parameter spdFF {true}
rt::set_parameter spdForTiming {false}
rt::set_parameter spdGate {true}
rt::set_parameter spdMux {false}
rt::set_parameter spdSimplifyCA4 {false}
rt::set_parameter spdUseTA {false}
rt::set_parameter speedupTechmapForNonTimingDrivenFlow {false}
rt::set_parameter splitCongestedLUT {false}
rt::set_parameter splitCongestedNonTimedLUT {false}
rt::set_parameter splitFlow {false}
rt::set_parameter splitLut6_2 {true}
rt::set_parameter srlCriticalityDistance {3}
rt::set_parameter srlDepthThreshold {3}
rt::set_parameter srlDrcFix {3}
rt::set_parameter srlHierSeparator {_}
rt::set_parameter srlRstChainFanoutThreshold {20000}
rt::set_parameter srlType {}
rt::set_parameter srlUseOnespinName {true}
rt::set_parameter structuralOptInputFile {top.v}
rt::set_parameter structuralOptOutputFile {final.v}
rt::set_parameter supportBWWE {true}
rt::set_parameter supportBramCascadePipeline {true}
rt::set_parameter supportCustomRamStyle {true}
rt::set_parameter supportEccErrorPipeline {true}
rt::set_parameter swapDspZYMux {true}
rt::set_parameter sweepRegistersInConstProp {false}
rt::set_parameter synPwroptLevel {0}
rt::set_parameter synPwroptVerbose {0}
rt::set_parameter synRetimingPattern {0}
rt::set_parameter syncControlMinFanout {1}
rt::set_parameter syncRstMinFanout {2147483647}
rt::set_parameter synthDesignFanoutLimitSwitchIsUsed {false}
rt::set_parameter tagCounterRegisters {false}
rt::set_parameter tdRamGenAreaPenaltyThresh {150.000000}
rt::set_parameter thresholdForAutoCMRom {10}
rt::set_parameter thresholdForParallelRun {3}
rt::set_parameter tieUnconnectedToZero {false}
rt::set_parameter timingDrivenControlSetsOpt {false}
rt::set_parameter timingDrivenMuxPartDecomp {false}
rt::set_parameter timingOptFlowCtrl {false}
rt::set_parameter traverseAllPinsOfChangedGenomes {false}
rt::set_parameter traverseAllPinsOfDependentGenomes {false}
rt::set_parameter trueFlatten {false}
rt::set_parameter tryFindingRegistersAcrossHierForDistRam {true}
rt::set_parameter tunedCascadeLUTArrival {false}
rt::set_parameter twoPassRamFlow {true}
rt::set_parameter unconnectedMuxfPinsToZero {true}
rt::set_parameter unconnectedPinsToZeroForBlackbox {false}
rt::set_parameter undrivenWireToDefault {false}
rt::set_parameter undrivenWireToX {false}
rt::set_parameter unmapMixedRamForTiming {false}
rt::set_parameter uram288e5DataWidth {72}
rt::set_parameter uramColumnLength {80}
rt::set_parameter uramGenPowerOptAttributes {true}
rt::set_parameter uramMinDepthThreshold {256}
rt::set_parameter uramMinDepthThresholdNew {1024}
rt::set_parameter uramMinUtilhreshold {51}
rt::set_parameter uramNoloadPortOpt {true}
rt::set_parameter uramResource {-1}
rt::set_parameter uramResourceDebug {0}
rt::set_parameter uramRetimeDebug {false}
rt::set_parameter uramUseHzCascadeChain {true}
rt::set_parameter uramUtilHighThresh {90.000000}
rt::set_parameter uramUtilThresh {60.000000}
rt::set_parameter uramVsBramUtilDiffThreshold {60}
rt::set_parameter useAsymCascade {true}
rt::set_parameter useAsymSDPMode {true}
rt::set_parameter useBWWECascade {true}
rt::set_parameter useBWWEWideDecomp {false}
rt::set_parameter useBramCascadeInTimingOpt {false}
rt::set_parameter useCarryoutInWideAdderDsp {true}
rt::set_parameter useGatesOnlyForSmallConstantInput {true}
rt::set_parameter useHARTLutMap2 {false}
rt::set_parameter useLogicGeneratorForInvalidOHMux {true}
rt::set_parameter useNewTDRamGen {true}
rt::set_parameter useNewUramSelection {true}
rt::set_parameter useParallelHelperForGenericLsf {true}
rt::set_parameter useParentCountForControlSet {true}
rt::set_parameter useUnchangedStitchPointsOnly {false}
rt::set_parameter useUniprims {true}
rt::set_parameter useXorForAllMultiPortRam {false}
rt::set_parameter userGivenChangedGenome {}
rt::set_parameter v8BramCascadeImplEnaDecoder {true}
rt::set_parameter v8CascChainStageDelay {2600}
rt::set_parameter v8CascadeUseFullBusWidth {false}
rt::set_parameter v8ForceBramCascade {false}
rt::set_parameter v8ShareBramGlueLogic {true}
rt::set_parameter validateCarryLutCheckCondition6 {true}
rt::set_parameter validateRetimedInputRegForExtrom {true}
rt::set_parameter verifyEarlyMaximalSharing {false}
rt::set_parameter versalAsyncRegInDsp {true}
rt::set_parameter versalBramDefaultWriteEnable {0}
rt::set_parameter versalBramWrenConnectActiveBytesOnly {false}
rt::set_parameter versalOptimizeShallowRam {true}
rt::set_parameter visitUnreachableILAorVIOinstances {true}
rt::set_parameter webTalkPath {./.Xil/Vivado-3622754-685a421e500f/wt}
rt::set_parameter wideGateThreshold {10}
rt::set_parameter wideXorToDsp {true}
rt::set_parameter wideXorToDspAuto {false}
rt::set_parameter wideXorToDspMixWidthMapping {true}
rt::set_parameter wideXorToDspResourceLimit {4}
rt::set_parameter wideXorToDspResourceLimitPerModule {35}
rt::set_parameter wideXorToDspThreshold {72}
rt::set_parameter widegateInCarrychain {false}
rt::set_parameter wireMapFlow {false}
rt::set_parameter writeChecksum {false}
rt::set_parameter writeForcedParallelTimingXdc {false}
rt::set_parameter writeParallelTimingXdc {false}
rt::set_parameter writeStatsToMetricDB {false}
rt::set_parameter writeUniquifiedBlackboxInterface {false}
rt::set_parameter writeWildcardsInMetricDBForRetimeAcrossOperatorsSuggestion {false}
rt::set_parameter xilinxAndOrMuxGenerator {false}
rt::set_parameter xilinxBoolSwitch1 {true}
rt::set_parameter xilinxConstMuxGenerator {false}
rt::set_parameter xilinxDecompMultAllowAsyncReg {true}
rt::set_parameter xilinxDecompMultFix {true}
rt::set_parameter xilinxDecompMultFix2 {true}
rt::set_parameter xilinxDecompMultFix3 {true}
rt::set_parameter xilinxDecompMultPipelineFix {true}
rt::set_parameter xilinxDecompMultTimingFix {false}
rt::set_parameter xilinxDelayDecompMultNew {true}
rt::set_parameter xilinxDelayDecompMultNew2 {true}
rt::set_parameter xilinxDelayDecompMultThreshold {29}
rt::set_parameter xilinxDontExtractGenomeForSmallDesign {true}
rt::set_parameter xilinxEvalMuxAreaFactorForOneLevel {80}
rt::set_parameter xilinxEvalMuxGenGenerators {true}
rt::set_parameter xilinxExtractGenomes {true}
rt::set_parameter xilinxGLogicGenGenerator {true}
rt::set_parameter xilinxGenLargeFsmOneHotMux {true}
rt::set_parameter xilinxGenerateInc {false}
rt::set_parameter xilinxMuxDecomp {false}
rt::set_parameter xilinxMuxDecompDecompseBuxMux {false}
rt::set_parameter xilinxMuxDecompExtractConstantInputs {false}
rt::set_parameter xilinxMuxDecompInputThreshold {4}
rt::set_parameter xilinxMuxDecompRemoveDuplicateInputs {false}
rt::set_parameter xilinxMuxDecompVerbose {false}
rt::set_parameter xilinxMuxGenGeneratorNew {true}
rt::set_parameter xilinxMuxLogicGenerator {true}
rt::set_parameter xilinxMuxPartSizeThreshold {6}
rt::set_parameter xilinxMuxStatistics {false}
rt::set_parameter xilinxNewSDPRam {6}
rt::set_parameter xilinxOneHotMuxGenGenerator {true}
rt::set_parameter xilinxOptAndOrMuxGenerator {false}
rt::set_parameter xilinxPrintMuxTable {0}
rt::set_parameter xilinxPrintMuxTableBeforePartition {0}
rt::set_parameter xilinxPrioMuxGenGenerator {true}
rt::set_parameter xilinxRemoveFalseDriver {false}
rt::set_parameter xilinxUseDatapathCLA {false}
rt::set_parameter xilinxUseTunedCSA {true}
rt::set_parameter xrefFilename {}
# Group: harttndelay
rt::set_parameter loadCellDelaysUsingVeamAPI {true}
rt::set_parameter pruneVersalTimingArc {true}
rt::set_parameter simplifyVersalFunnel {true}
rt::set_parameter skipLoadingArcsForCPM5 {true}
rt::set_parameter skipLoadingArcsForDCMAC {true}
rt::set_parameter skipLoadingArcsForPS9 {true}
# Group: hdl
rt::set_parameter adjustMemoryIndex {0}
rt::set_parameter allowClockAsData {true}
rt::set_parameter cellOverridesModule {true}
rt::set_parameter convertMultToShift {false}
rt::set_parameter createDFPinCacheThreshold {20}
rt::set_parameter diffPortNetNames {false}
rt::set_parameter displayConstants {false}
rt::set_parameter displayDisplay {true}
rt::set_parameter displayTypes {false}
rt::set_parameter dissolveChainedConstantBMerge {true}
rt::set_parameter dissolveModulesInElaborate {}
rt::set_parameter dissolveTemplateModulesInElaborate {false}
rt::set_parameter dissolveVerilogLogicGates {true}
rt::set_parameter dotAllignConstructAndMerge {false}
rt::set_parameter elabReportInstances {false}
rt::set_parameter elabRuntimes {false}
rt::set_parameter enableOtherTraces {true}
rt::set_parameter errorInUseClause {true}
rt::set_parameter forLoopSaveIterator {true}
rt::set_parameter ignoreConnectionError {false}
rt::set_parameter ignoreIllegalOutputConnection {true}
rt::set_parameter integerParameters {false}
rt::set_parameter iteratorInfersRegister {false}
rt::set_parameter linkParameterizedByName {false}
rt::set_parameter localVarIsStatic {true}
rt::set_parameter maxModuleNameLength {0}
rt::set_parameter multiFileCompilationUnit {true}
rt::set_parameter pruneIndexValues {false}
rt::set_parameter realNumberError {true}
rt::set_parameter reportOpeningRtlFiles {false}
rt::set_parameter resolveDefaultModportInout {true}
rt::set_parameter resolveItemInIntfPortTF {true}
rt::set_parameter shareAssignConstructs {0}
rt::set_parameter simWrapper {}
rt::set_parameter simplifyNegate {false}
rt::set_parameter simplifyOneBitComparison {true}
rt::set_parameter skipDfgOpt {false}
rt::set_parameter skipNetlist {false}
rt::set_parameter trimMerge {false}
rt::set_parameter uniquifyWhenNeeded {true}
rt::set_parameter upcaseVhdlRecordFields {false}
rt::set_parameter useSvElab {true}
rt::set_parameter vhdlCoerceSignedOperands {false}
rt::set_parameter vhdlConstantFunctions {true}
rt::set_parameter vhdlDeferReadUntilElab {true}
rt::set_parameter vhdlDowncase {false}
rt::set_parameter vhdlIntegerOp32 {false}
rt::set_parameter vhdlSortCommandLine {false}
rt::set_parameter vhdlSortDebug {}
rt::set_parameter vhdlTextio {false}
rt::set_parameter vlogConstantFunctions {true}
rt::set_parameter widthMismatchWarn {false}
# Group: hoptCluster
rt::set_parameter breakClusterInDfg {false}
rt::set_parameter calculateLCAForNonMacros {true}
rt::set_parameter clusterDebug {false}
rt::set_parameter hoptClusterEdgeWeightLimit {20}
rt::set_parameter maxClusterInsts {50}
rt::set_parameter minClusterSize {true}
rt::set_parameter skipNonMacros {false}
# Group: hoptConstruct
rt::set_parameter debugOptMuxSel {0}
rt::set_parameter doBasicConstructInputOpt {false}
rt::set_parameter doConstPropBasedConstructInputOpt {true}
rt::set_parameter maxBitWidthOfSelForConstPropBasedConstructInputOpt {16}
rt::set_parameter maxChangeInConstructSize {2}
rt::set_parameter maxNodesInFlowGraph {2500}
rt::set_parameter maxWideningAllowed {3}
rt::set_parameter maxWideningAllowedFactor {2}
rt::set_parameter onlyOptimizeDataOperators {false}
rt::set_parameter optimizeOnlyIfDataOperatorFound {true}
rt::set_parameter stopAtNodesWithOtherFanouts {false}
rt::set_parameter thresholdForAddSub {11}
rt::set_parameter thresholdForMult {8}
rt::set_parameter useMinCutInSelectingDrvVars {false}
# Group: hoptDataflow
rt::set_parameter DFVdontDissolveEmptyGraphs {false}
rt::set_parameter busViewFixBrokenConnections {false}
rt::set_parameter calculateGraphEdgeWeight {true}
rt::set_parameter createDFGBusGraph {true}
rt::set_parameter edgeBasedBusHighlighting {true}
rt::set_parameter ignoreConstPrimInputs {false}
rt::set_parameter ignoreConstPrimNode {true}
rt::set_parameter minPossibleBusWidth {2}
rt::set_parameter showCombineAndSplitNodes {true}
# Group: hoptGenControl
rt::set_parameter addDriverInPinsOnly {true}
rt::set_parameter checkRegForControlFeedback {false}
rt::set_parameter checkRegForControlFeedbackRecur {true}
rt::set_parameter checkResetInCaseMuxForReg {true}
rt::set_parameter extractAsyncTriStateSet {false}
rt::set_parameter fixBitExtensionForReg {true}
rt::set_parameter fixBitwisePattern1 {true}
rt::set_parameter fixBitwisePattern2 {true}
rt::set_parameter removeRedundantBmergeNodesForGenControl {true}
rt::set_parameter returnComboLoopError {true}
rt::set_parameter unShareClkDriverForGenControl {true}
# Group: hoptMerge
rt::set_parameter earlyCollapseMergeDebug {false}
rt::set_parameter earlyCollapseMergeLoop {true}
rt::set_parameter earlyCollapseMergeNestedLoop {true}
rt::set_parameter simplifyCascMergeOldConnect {true}
# Group: lef
rt::set_parameter lefCapUnit {ignore}
# Group: lib
rt::set_parameter ignoreSlewDerateFromLibrary {true}
rt::set_parameter libAllowMultiLibsForCell {true}
rt::set_parameter libertyLoadVerbosity {0}
rt::set_parameter markPadAsMacro {false}
rt::set_parameter readLibContinueOnError {true}
rt::set_parameter reportCombCellFunction {false}
rt::set_parameter reportMvCorner {false}
rt::set_parameter reportSeqInfoInRetention {false}
rt::set_parameter sortOutputPinsByIndex {true}
# Group: license
rt::set_parameter compareLiterally {false}
rt::set_parameter prefixModuleNameToMsgs {false}
# Group: lint
rt::set_parameter blockUnisimWarnings {true}
rt::set_parameter checkAdderMerge {true}
rt::set_parameter checkArithOverflow {true}
rt::set_parameter checkCaseEquality {true}
rt::set_parameter checkCombinationalLoop {true}
rt::set_parameter checkComparatorMismatch {true}
rt::set_parameter checkDualEdgeModule {true}
rt::set_parameter checkFullCase {true}
rt::set_parameter checkLatchInfer {true}
rt::set_parameter checkMissingAsyncReset {true}
rt::set_parameter checkMultiAssign {true}
rt::set_parameter checkMultiResetsBlock {true}
rt::set_parameter checkShiftOverflow {true}
rt::set_parameter checkSignednessResolution {true}
rt::set_parameter checkUnreadArrayBits {true}
rt::set_parameter checkUnreadSignal {true}
rt::set_parameter checkUnsetArrayBits {true}
rt::set_parameter lintBitsAssignScalar {true}
rt::set_parameter lintDbg {0}
rt::set_parameter lintEncryptedModule {false}
rt::set_parameter lintPassModPortDir {true}
rt::set_parameter lintXilinxIP {false}
rt::set_parameter lintXilinxIPIdentify2023 {true}
rt::set_parameter lint_ASSIGN1_precisionDelta {2}
rt::set_parameter lint_ASSIGN1_reducedPattern {false}
rt::set_parameter lint_ASSIGN2_reducedPattern {true}
rt::set_parameter lint_ASSIGN7_allowBMergeFanout {false}
rt::set_parameter lint_ASSIGN_maskTristateBufferMultiAssign {true}
rt::set_parameter lint_ASSIGN_reportBitWidthMismatch {true}
rt::set_parameter lint_ASSIGN_useLintBitsAssignInArrayNew {true}
rt::set_parameter lint_ASSIGN_variableInAlwaysBlock {false}
rt::set_parameter lint_MsgSortByFile {true}
# Group: loptabcverify
rt::set_parameter nlOptOneSpinVerify {0}
rt::set_parameter usePidBasedGenlib {true}
# Group: messages
rt::set_parameter messageAlwaysFlush {false}
rt::set_parameter message_suppress_limit {100}
# Group: naming
rt::set_parameter XDCskipInferredModule {false}
rt::set_parameter allowCaseAnalysis {true}
rt::set_parameter allowClass {true}
rt::set_parameter allowIndexedDefparam {true}
rt::set_parameter allowNestedModule {true}
rt::set_parameter allowNestedUnion {true}
rt::set_parameter allowOptWithKeepHier {true}
rt::set_parameter allowVirtualInterface {true}
rt::set_parameter architecture_naming_style {%s_%s}
rt::set_parameter array_instance_naming_style {%s[%d]}
rt::set_parameter array_naming_style {[%d]}
rt::set_parameter bddBasedCaseAnalysis {false}
rt::set_parameter block_naming_style {%s.}
rt::set_parameter changeNamesPreElab {false}
rt::set_parameter checkSensListUnsupported {true}
rt::set_parameter classElabSeparator {\.}
rt::set_parameter cleanupNameSpace {true}
rt::set_parameter compatibilityMode {false}
rt::set_parameter connectDefaultInputPort {true}
rt::set_parameter convertIfStmtToCase {false}
rt::set_parameter convertSynAttributes {false}
rt::set_parameter crcfyModuleSignature {false}
rt::set_parameter createNodeForModOperator {true}
rt::set_parameter createNodeForRemOperator {true}
rt::set_parameter createPortsForNullRecords {true}
rt::set_parameter defaultVhdlWorkLib {xil_defaultlib}
rt::set_parameter deferParseUntilElab {false}
rt::set_parameter deprecateUseDsp48Attr {true}
rt::set_parameter disableParamInitValuePrint {false}
rt::set_parameter displaySubprogram {false}
rt::set_parameter dissolveFunctionsInElab {false}
rt::set_parameter dotStarAOIConn {true}
rt::set_parameter elabConstPropForExpressions {true}
rt::set_parameter elabSvlgCleanupConstFuncBmerge {true}
rt::set_parameter elabSvlgCleanupConstFuncInternalItems {true}
rt::set_parameter elabSvlgCleanupConstNode {true}
rt::set_parameter elabSvlgCleanupInitialBlockBmerge {true}
rt::set_parameter elabSvlgExprEvalBasedSensitivityListCheck {true}
rt::set_parameter elabSvlgGenMapMemory {true}
rt::set_parameter elabSvlgInstantiateVhdlComplexGenericType {true}
rt::set_parameter elabSvlgInstantiateVhdlComplexPortType {true}
rt::set_parameter elabSvlgMoveInternalLoadsToWireOutput {true}
rt::set_parameter elabSvlgProceduralMapMemory {true}
rt::set_parameter elabSvlgPropagateAssignIdx {true}
rt::set_parameter elabSvlgReuseConstFuncPortDecl {true}
rt::set_parameter elabSvlgReuseEnableDeclInsideConstFunc {true}
rt::set_parameter elabSvlgReuseFuncGraph {true}
rt::set_parameter elabSvlgReuseFuncInstance {true}
rt::set_parameter elabSvlgSupportWandWor {true}
rt::set_parameter elabSvlgUseCachedRootExpr {true}
rt::set_parameter elabSvlgUseDirectConstOperator {true}
rt::set_parameter elabSvlgUseDirectIndexedExpr {true}
rt::set_parameter elabSvlgUseDirectMultiIdxExpr {true}
rt::set_parameter elabSvlgUseDirectSelectAssign {true}
rt::set_parameter elabSvlgUseDirectSliceExpr {true}
rt::set_parameter elabSvlgUseDirectStructMemberSelect {true}
rt::set_parameter elabSvlgUseLocalScopeConstNode {true}
rt::set_parameter elabVhdlCleanupConstFuncBmerg {false}
rt::set_parameter elabVhdlCleanupConstFuncBmerge {true}
rt::set_parameter elabVhdlCleanupConstFuncInternalItems {true}
rt::set_parameter elabVhdlCleanupConstNode {true}
rt::set_parameter elabVhdlFormalFunctionCall {true}
rt::set_parameter elabVhdlGenMapMemory {true}
rt::set_parameter elabVhdlInstantiateSvlgComplexGenericType {true}
rt::set_parameter elabVhdlInstantiateSvlgComplexPortType {true}
rt::set_parameter elabVhdlProceduralMapMemory {true}
rt::set_parameter elabVhdlPropagateAssignIdx {true}
rt::set_parameter elabVhdlReuseConstFuncPortDecl {true}
rt::set_parameter elabVhdlSeparateScopeForStmts {true}
rt::set_parameter elabVhdlUseCachedRootExpr {true}
rt::set_parameter elabVhdlUseDirectConstOperator {true}
rt::set_parameter elabVhdlUseDirectIndexedExpr {true}
rt::set_parameter elabVhdlUseDirectMultiIdxExpr {true}
rt::set_parameter elabVhdlUseDirectSelectAssign {true}
rt::set_parameter elabVhdlUseLocalScopeConstNode {true}
rt::set_parameter enableDollarRoot {false}
rt::set_parameter enableElabSystemTasks {true}
rt::set_parameter enableVhdlUseDSPFP32 {false}
rt::set_parameter enhancedGenericsVhdl2008 {true}
rt::set_parameter evalLocalparamAsModuleItem {true}
rt::set_parameter fanoutThreshold {}
rt::set_parameter fixInterfaceLookup {false}
rt::set_parameter genblkInterfacePortSupport {true}
rt::set_parameter generate_naming_style {%s[%d].}
rt::set_parameter genericSignatureWithType {true}
rt::set_parameter hierInterfacePortSupport {true}
rt::set_parameter if_generate_naming_style {%s.}
rt::set_parameter ignoreSvlgAssertStmts {false}
rt::set_parameter ignoreVhdlAssertStmts {true}
rt::set_parameter ignoreVhdlReportStmts {true}
rt::set_parameter incrementalElaboration {false}
rt::set_parameter instGenUserNamePrefix {rtSDC_}
rt::set_parameter instNameChangeProb {0.100000}
rt::set_parameter instNamePrefix {i_}
rt::set_parameter interfaceElabSeparator {\.}
rt::set_parameter library_naming_style {%s_%s}
rt::set_parameter loadMixedDialectVhdlPackages {false}
rt::set_parameter loadVhdl2008Libs {false}
rt::set_parameter loadVhdl2019Libs {false}
rt::set_parameter markAsynchBmerge {true}
rt::set_parameter markModRemOperatorNodes {false}
rt::set_parameter matchFlatNames {false}
rt::set_parameter nameChangeRandSeed {10000}
rt::set_parameter netNameChangeProb {0.100000}
rt::set_parameter netNamePrefix {n_}
rt::set_parameter paramOverrideAsAssign {true}
rt::set_parameter parameter_naming_style {_%s%d}
rt::set_parameter portConnAsAssign {true}
rt::set_parameter portNamePrefix {p_}
rt::set_parameter preElabScanRuntimes {false}
rt::set_parameter preElaborateScan {true}
rt::set_parameter preScanWithOasysEvaluate {false}
rt::set_parameter preScanWithVerificEvaluate {true}
rt::set_parameter printAllModules {false}
rt::set_parameter printAsLocalparam {false}
rt::set_parameter printDefaultValueParams {false}
rt::set_parameter printIPSubParams {false}
rt::set_parameter printModuleName {false}
rt::set_parameter processIntfPortsForParams {true}
rt::set_parameter record_naming_style {[%s]}
rt::set_parameter reg_naming_style {%s_reg}
rt::set_parameter relaxVhdlImpureCheck {false}
rt::set_parameter relaxedNetlistParsing {false}
rt::set_parameter resolveHierPath {true}
rt::set_parameter setMaxThresholdToInfinity {false}
rt::set_parameter setP1735DontTouch {true}
rt::set_parameter setPropertyMatchRtlRegToRegCell {false}
rt::set_parameter sortHdlCommandLine {false}
rt::set_parameter stdLogicVectorSeparateType {false}
rt::set_parameter svMarkModDivNodes {true}
rt::set_parameter unescapeVhdlName {true}
rt::set_parameter unpackedTypeAOIConn {true}
rt::set_parameter useLongGenericSignature {false}
rt::set_parameter useVhdlFpgaGenerateLabels {false}
rt::set_parameter vhdlCheckDynamicRangeMatch {false}
rt::set_parameter vhdlComplexDynamicRange {true}
rt::set_parameter vhdlDynamicRange {true}
rt::set_parameter vhdlDynamicRangeDiffSizes {true}
rt::set_parameter vhdlFixedVersion {true}
rt::set_parameter vhdlFunctionCacheing {true}
rt::set_parameter vhdlFunctionRuntimeDebug {false}
rt::set_parameter vhdlGraphFunctionCaching {true}
rt::set_parameter vhdlGraphProcedureCaching {true}
rt::set_parameter vhdlMarkModRemNodes {true}
rt::set_parameter vhdlResizeDynamicRangeArg {true}
rt::set_parameter vhdlSkipSelectPragmaFunctions {true}
rt::set_parameter vhdlSupportInterfaceSubprogram {true}
rt::set_parameter vhdlSupportToStringFunction {true}
rt::set_parameter vhdlUnconstRecordAggr {true}
rt::set_parameter vhdlUseDSPFP32 {false}
rt::set_parameter vhdlVerificEvaluate {true}
rt::set_parameter vhdl_H_L_handling {false}
rt::set_parameter warnUnpackedUnion {false}
# Group: nl
rt::set_parameter applyCommandsOnAllInstances {true}
rt::set_parameter areaBasedSortingWithinBucket {false}
rt::set_parameter areaUnit {0.000100}
rt::set_parameter avoidAssigns {2}
rt::set_parameter bfsDepthForRenamingGeneratedPorts {3}
rt::set_parameter bucketAwareResizeSequential {true}
rt::set_parameter cellBindingBasedCostBucket {false}
rt::set_parameter cleanupRtdFiles {false}
rt::set_parameter collapseMuxTree {false}
rt::set_parameter collapseMuxTreePattern1Threshold {15}
rt::set_parameter collapsePrioMuxChainThreshold {4}
rt::set_parameter collapsePrioMuxHighEffort {false}
rt::set_parameter considerHierInstBestPortName {false}
rt::set_parameter costBucketStressTest {false}
rt::set_parameter createHierFindBestPortName {4}
rt::set_parameter debugCostBucket {0}
rt::set_parameter debugGenClock {false}
rt::set_parameter debugModuleName { }
rt::set_parameter debugRebuildHierarchy {false}
rt::set_parameter delayBasedBucketing {false}
rt::set_parameter delayBasedSortingWithinBucket {false}
rt::set_parameter dissolveDeleteOrphanGenomes {true}
rt::set_parameter dissolveKeepHierarchy {false}
rt::set_parameter dissolveMergeNames {true}
rt::set_parameter dissolveMergeNamesSeparator {/}
rt::set_parameter dissolveMergeNamesToDfg {true}
rt::set_parameter dissolveSmallVirtualModules {true}
rt::set_parameter dupGenomeStraps {false}
rt::set_parameter energyBasedBinning {true}
rt::set_parameter energyBinningMultiplier {2.000000}
rt::set_parameter estimateFastestCell {0.300000}
rt::set_parameter fastestCellLoadMultiplier {3.000000}
rt::set_parameter fastestUseFixLoad {0.000000}
rt::set_parameter findCacheAllGenomeInstances {true}
rt::set_parameter findInsideDfPartitions {true}
rt::set_parameter findInstTrustCache {false}
rt::set_parameter findInstUseCache {true}
rt::set_parameter findPostUniquifies {false}
rt::set_parameter findTransparentlyInsideDf {false}
rt::set_parameter findTransparentlyInsideGenomes {true}
rt::set_parameter findUniquifies {true}
rt::set_parameter findWildCardInGen {true}
rt::set_parameter genomeSlewSaved {true}
rt::set_parameter getSamePinByName {false}
rt::set_parameter groupBigMuxSizeThreshold {10}
rt::set_parameter hierMatchingUseStraps {true}
rt::set_parameter ignoreBidirForMultiDriven {true}
rt::set_parameter ignoreDirectives {false}
rt::set_parameter ignoreDontTouch {false}
rt::set_parameter ignoreUserFuncClassInFamily {false}
rt::set_parameter includeBBoxInReportCells {true}
rt::set_parameter incrementalSortBucket {false}
rt::set_parameter inoutPortPrefix {B}
rt::set_parameter inputPortPrefix {I}
rt::set_parameter largeFanout {10}
rt::set_parameter leakageBasedSortingWithinBucket {true}
rt::set_parameter leakagePriority {3}
rt::set_parameter maxBddNodes {500000}
rt::set_parameter maxCapLoadSensitiveDelaySlope {1.000000}
rt::set_parameter maxCapLoadSensitiveDlyKink {2.000000}
rt::set_parameter maxCapLoadSensitiveSlewKink {2.000000}
rt::set_parameter maxCapLoadSensitiveSlewSlope {10.000000}
rt::set_parameter maxMemoryUse {500}
rt::set_parameter maxSlewSensitiveDelaySlope {1.000000}
rt::set_parameter maxSlewSensitiveSlewSlope {1.000000}
rt::set_parameter maxStandardCellHeightMultiple {3}
rt::set_parameter mergeDfNames {false}
rt::set_parameter minGenomeCache {3}
rt::set_parameter minRequiredFamilySize {8}
rt::set_parameter minimumMacroSize {100.000000}
rt::set_parameter newMuxHeadCriteria {true}
rt::set_parameter newNetNameUniquification {false}
rt::set_parameter numSupportedHierSepInInstName {50}
rt::set_parameter outputPortPrefix {O}
rt::set_parameter powerMacroLeakageMultiplier {1.000000}
rt::set_parameter powerOrderBucketZero {false}
rt::set_parameter prioMuxSel {2}
rt::set_parameter rebuildHierarchyUseConnectivity {true}
rt::set_parameter releaseDesignStressTest {false}
rt::set_parameter releaseInstanceDesignsOnModify {true}
rt::set_parameter removeRedundantMuxSel {true}
rt::set_parameter reportClockGateRecurLevel {3}
rt::set_parameter resetCostBucketForceRebind {true}
rt::set_parameter skipRemoveRedundantMuxSelForSmallAndWideMux {false}
rt::set_parameter tieUndrivenGenomePins {true}
rt::set_parameter ungroupVirtualToo {true}
rt::set_parameter uniquifyGenomeForUserDirectives {false}
rt::set_parameter usePostFindUniquification {true}
rt::set_parameter warnOnDissolveGraph {false}
# Group: nlcnf
rt::set_parameter setPinConstants {true}
rt::set_parameter setPinEquivalencies {true}
# Group: nmod
rt::set_parameter fastSdcSearch {0}
rt::set_parameter fastSdcSteps {2}
rt::set_parameter findTimerName {false}
rt::set_parameter sdcCurrentInstance {true}
rt::set_parameter trustInstanceAddedInCache {true}
# Group: optimize
rt::set_parameter abcOptScript {resyn2;fpga -K %d; sweep;}
rt::set_parameter abcOptScriptCollapse {resyn2;dch -f;resyn2}
rt::set_parameter abcOptScriptGates {resyn2;map;}
rt::set_parameter abcOptScriptGatesArea {strash;dch -f;amap}
rt::set_parameter acceptInternalGMoves {false}
rt::set_parameter allowHillClimb {false}
rt::set_parameter alwaysOptimizeArea {true}
rt::set_parameter areaOptAllowUndrivenInputs {true}
rt::set_parameter areaOptCleanUpFirst {true}
rt::set_parameter areaOptDissolveIncremental {true}
rt::set_parameter areaOptDissolveUserModules {0}
rt::set_parameter areaOptExcludeDecodedMux {0}
rt::set_parameter areaOptFixRunTime {4}
rt::set_parameter areaOptIncrementalCritRange {200}
rt::set_parameter areaOptIncrementalMergePartitions {false}
rt::set_parameter areaOptMaxDatapathArea {2500}
rt::set_parameter areaOptMaxLogicArea {-1}
rt::set_parameter areaOptMaxPasses {2}
rt::set_parameter areaOptMergePartitions {true}
rt::set_parameter areaOptRepartitionGraph {false}
rt::set_parameter areaOptSetUndrivenInputTo {0}
rt::set_parameter areaPartitionSingleInstance {true}
rt::set_parameter bailOutOnSlackIncrease {false}
rt::set_parameter blindswapInG {false}
rt::set_parameter blindswapInGMinArrDiff {0.000000}
rt::set_parameter blocknlOpt {0}
rt::set_parameter characterizeDebugThreshold {50}
rt::set_parameter coarseResizeConsiderInternalEndpoints {true}
rt::set_parameter costMultiple {2}
rt::set_parameter critInstanceCount {1073741824}
rt::set_parameter critPercentageLvt {0.000000}
rt::set_parameter disableAbc {true}
rt::set_parameter dynamicResize {false}
rt::set_parameter dynamicResizeAreaLevels {0}
rt::set_parameter dynamicResizeArrivalTimePruneMargin {4}
rt::set_parameter dynamicResizeBindWithoutCallBacks {0}
rt::set_parameter dynamicResizeBuffering {1}
rt::set_parameter dynamicResizeCurrentWorstSlackAsTarget {0}
rt::set_parameter dynamicResizeDebug {0}
rt::set_parameter dynamicResizeEstimatedLoadCriticalityMargin {0}
rt::set_parameter dynamicResizeInputArrivalMarginFactor {4}
rt::set_parameter dynamicResizeNumInputChoices {4}
rt::set_parameter dynamicResizeSlackMargin {0}
rt::set_parameter dynamicResizeSlewMargin {2}
rt::set_parameter dynamicResizeUseSlewFactor {1}
rt::set_parameter flopRemapFile {}
rt::set_parameter genomeAdjustCutoffSlack {true}
rt::set_parameter getCommonEquivalenciesQuickFix {true}
rt::set_parameter inferDecoderForMinMuxDataSize {2147483647}
rt::set_parameter inferDecoderMinOutSize {32}
rt::set_parameter leakageFilterInferior {false}
rt::set_parameter leakageNewFlow {4}
rt::set_parameter maxPercentageLvt {100.000000}
rt::set_parameter nlOptCheckSum {0}
rt::set_parameter nlOptML {0}
rt::set_parameter optAlwaysIncrToolId {1}
rt::set_parameter optCloneModBeforeRegen {false}
rt::set_parameter optCritPinFix {false}
rt::set_parameter optCriticalRangeForCloning {50.000000}
rt::set_parameter optCriticalRangeModeForCloning {0}
rt::set_parameter optDissolveTopPostCloning {false}
rt::set_parameter optGenLoopCounter {-1}
rt::set_parameter optMinGenomeRatio {0}
rt::set_parameter optTryFamilyFix {false}
rt::set_parameter optTryFamilyLastOnly {false}
rt::set_parameter optimizeAllowBackOff {false}
rt::set_parameter optimizeAreaDontTouchClockNetwork {false}
rt::set_parameter optimizeAreaDumpAbcFor {}
rt::set_parameter optimizeAreaEffort {1}
rt::set_parameter optimizeAreaFirstSweepOnly {false}
rt::set_parameter optimizeAreaGeneratedModulesOnly {true}
rt::set_parameter optimizeAreaImprovementRatio {1.000000}
rt::set_parameter optimizeAreaRemapToFirstMember {false}
rt::set_parameter optimizeAreaSkipGeneratedModules {false}
rt::set_parameter optimizeAreaStopAtCount {9999999}
rt::set_parameter optimizeAreaTimingDriven {false}
rt::set_parameter optimizeBlindSwapDatapath {true}
rt::set_parameter optimizeBlindSwapDatapathSingle {false}
rt::set_parameter optimizeBucketGreedy {true}
rt::set_parameter optimizeCPAfterRegenerateLopt {false}
rt::set_parameter optimizeCheckConnections {3}
rt::set_parameter optimizeCheckCriticalPaths {0}
rt::set_parameter optimizeCheckGWS {false}
rt::set_parameter optimizeClearHistoryAfterIncPlacement {true}
rt::set_parameter optimizeCritRangeWhenNoRetry {true}
rt::set_parameter optimizeCritRangeWithDissolveUM {true}
rt::set_parameter optimizeCriticalPathGreedy {false}
rt::set_parameter optimizeCriticalRegion {false}
rt::set_parameter optimizeDebug {0}
rt::set_parameter optimizeDebugGivingUpFrom {0}
rt::set_parameter optimizeDebugGivingUpTo {0}
rt::set_parameter optimizeDebugLeakage {0}
rt::set_parameter optimizeDebugPlotArea {false}
rt::set_parameter optimizeDebugPlotInstanceInstead {false}
rt::set_parameter optimizeDebugSkewClocks {0}
rt::set_parameter optimizeDebugWriteStep { }
rt::set_parameter optimizeDefaultActions {1}
rt::set_parameter optimizeDeleteOrphanGenomes {true}
rt::set_parameter optimizeDissolveUserModules {0}
rt::set_parameter optimizeDynamicReorderingWith {6}
rt::set_parameter optimizeEnforceOrdering {false}
rt::set_parameter optimizeExclusiveSplit {false}
rt::set_parameter optimizeExtractAllCriticalInsts {1}
rt::set_parameter optimizeFilterCosts {2}
rt::set_parameter optimizeFixMultiPortNets {true}
rt::set_parameter optimizeFixMultiPortNetsInGenome {true}
rt::set_parameter optimizeFlow {2}
rt::set_parameter optimizeGenomeBindAllInstantiationTogether {true}
rt::set_parameter optimizeGenomeCriticalRatio {0.000000}
rt::set_parameter optimizeGenomeDupKeepToolId {true}
rt::set_parameter optimizeGenomeMarkerStep { }
rt::set_parameter optimizeGenomeTryFamily {true}
rt::set_parameter optimizeIgnoreLastWorkedGroup {true}
rt::set_parameter optimizeImplementPF {false}
rt::set_parameter optimizeLPWithinCritRange {1}
rt::set_parameter optimizeLeakageBailOnReachingMax {true}
rt::set_parameter optimizeLeakageByVthGroup {true}
rt::set_parameter optimizeLeakageCoarseResizeRange {50.000000}
rt::set_parameter optimizeLeakageCritWholePath {false}
rt::set_parameter optimizeLeakageEffort {0}
rt::set_parameter optimizeLeakagePathBased {true}
rt::set_parameter optimizeLeakagePathBasedEffortHigh {true}
rt::set_parameter optimizeLeakageRebindSequential {true}
rt::set_parameter optimizeLeakageResetCritRange {100.000000}
rt::set_parameter optimizeLeakageResetRatio {0.100000}
rt::set_parameter optimizeLeakageResetToolOnChange {true}
rt::set_parameter optimizeLeakageSkipAreaPart {true}
rt::set_parameter optimizeLeakageSkipDatapath {false}
rt::set_parameter optimizeLeakageWithPessimism {false}
rt::set_parameter optimizeLeftToRight {true}
rt::set_parameter optimizeLegalizeAfterBackOff {true}
rt::set_parameter optimizeMaxAreaRatio {0.990000}
rt::set_parameter optimizeMaxCutInSplit {1}
rt::set_parameter optimizeMaxEndOfLoopPlacement {3}
rt::set_parameter optimizeMaxSlackJump {1.000000}
rt::set_parameter optimizeMaxUnrecoveredJump {0}
rt::set_parameter optimizeMaxUphillSplits {1}
rt::set_parameter optimizeMergeCaseWithBigOR {16}
rt::set_parameter optimizeMergeCheckXors {1}
rt::set_parameter optimizeMergeKeepUndrivenPort {true}
rt::set_parameter optimizeMergeLPAndDecoderOutSizeLtEq {16}
rt::set_parameter optimizeMergeMaxInputCount {55}
rt::set_parameter optimizeMergePrempt {false}
rt::set_parameter optimizeMergeReconvergence {false}
rt::set_parameter optimizeMergeReductionWithCase {false}
rt::set_parameter optimizeMergeSplitExclusive {false}
rt::set_parameter optimizeMergeUMLCheckSize {2}
rt::set_parameter optimizeMergeVarBselMaxSelSize {4}
rt::set_parameter optimizeMergeWithDecoderOutSizeLtEq {32}
rt::set_parameter optimizeMergeWithReductionOpr {-1}
rt::set_parameter optimizeMinSlackJump {0.050000}
rt::set_parameter optimizeNoConstPropInsideGenome {false}
rt::set_parameter optimizeNoEquallyCriticalEPs {0}
rt::set_parameter optimizeNoRetryInsideGenome {false}
rt::set_parameter optimizeNonProgressTolerance {2}
rt::set_parameter optimizeNumCellCostBucket {2}
rt::set_parameter optimizeOffCriticalMargin {100.000000}
rt::set_parameter optimizePGChangeTopOnly {4}
rt::set_parameter optimizePGFixEquallyCrit {true}
rt::set_parameter optimizePathGroups {true}
rt::set_parameter optimizePathGroupsWeightedCutoff {true}
rt::set_parameter optimizePermuteGenomes {true}
rt::set_parameter optimizePhysical {true}
rt::set_parameter optimizePlaceCriticalPath {true}
rt::set_parameter optimizePlaceCriticalPathEffort {0}
rt::set_parameter optimizePostPlaceSubCritMaxStep {m}
rt::set_parameter optimizePostResize {false}
rt::set_parameter optimizeRedoDegradedGroups {1}
rt::set_parameter optimizeRegenHierWithMiniTopt { }
rt::set_parameter optimizeRegenTargetGenomeAreaMult {0.750000}
rt::set_parameter optimizeRegenUseAreaMultForDatapath {true}
rt::set_parameter optimizeRegenWriteModule {}
rt::set_parameter optimizeReleaseAllGenomes {true}
rt::set_parameter optimizeRemoveClockFromCritPins {true}
rt::set_parameter optimizeRepartitionBeforeSplitting {false}
rt::set_parameter optimizeRepartitionGenomes {1}
rt::set_parameter optimizeRepartitionGenomesOffCritical {false}
rt::set_parameter optimizeResizeSeqCritPathOnly {false}
rt::set_parameter optimizeResizeSeqCritcalRange {10}
rt::set_parameter optimizeResizeSeqFixBug {false}
rt::set_parameter optimizeResizeSeqSameSlack {true}
rt::set_parameter optimizeRestructDfgDebug {0}
rt::set_parameter optimizeRetrySlackMargin {0.200000}
rt::set_parameter optimizeRetryWithPlacement {true}
rt::set_parameter optimizeShannonCaseLogic {false}
rt::set_parameter optimizeShannonCheckTiming {g1}
rt::set_parameter optimizeShannonDPMinGateDelays {2.000000}
rt::set_parameter optimizeShannonDupCount {3}
rt::set_parameter optimizeShannonMinGateDelays {3.500000}
rt::set_parameter optimizeSidePathTolerance {1.500000}
rt::set_parameter optimizeSkewClocks {false}
rt::set_parameter optimizeSkewClocksIncrements {100.000000}
rt::set_parameter optimizeSkewClocksMax {700.000000}
rt::set_parameter optimizeSkewClocksMaxCount {0}
rt::set_parameter optimizeSkewClocksMaxSlack {-50.000000}
rt::set_parameter optimizeSkewClocksMin {0.000000}
rt::set_parameter optimizeSkewClocksMinSlack {50.000000}
rt::set_parameter optimizeSkewClocksOnClockGates {false}
rt::set_parameter optimizeSkewClocksOnGenomes {false}
rt::set_parameter optimizeSkewClocksOnLatches {false}
rt::set_parameter optimizeSkewClocksOnMacros {false}
rt::set_parameter optimizeSkewClocksOnRegisters {true}
rt::set_parameter optimizeSkewClocksSubCrit {false}
rt::set_parameter optimizeSkewClocksWholeBus {false}
rt::set_parameter optimizeSplitAcceptanceCriteria {1}
rt::set_parameter optimizeSplitGenomes {1}
rt::set_parameter optimizeStepVCutOffBucket {0}
rt::set_parameter optimizeSteps {G}
rt::set_parameter optimizeSubCritMaxStep {A}
rt::set_parameter optimizeSwapSelectedDatapath {false}
rt::set_parameter optimizeTargetMargin {100.000000}
rt::set_parameter optimizeTimingDriven {true}
rt::set_parameter optimizeTopCriticalPathGreedy {false}
rt::set_parameter optimizeTrackDesignSpace {false}
rt::set_parameter optimizeTrackDoneActions {true}
rt::set_parameter optimizeUnshareMinGateDelays {1.000000}
rt::set_parameter optimizeUphillSplitRelaxation {1.000000}
rt::set_parameter optimizeVthGroupOrder {}
rt::set_parameter parallelConstprop {0}
rt::set_parameter postOptimizeCongestionOpt {false}
rt::set_parameter postOptimizeIncLegalize {true}
rt::set_parameter postOptimizeIncPlaceEffort {1}
rt::set_parameter postOptimizeIncPlacement {true}
rt::set_parameter postOptimizeMaxIncPlacement {2}
rt::set_parameter postOptimizeOneMoreTry {true}
rt::set_parameter postOptimizePlaceSmallObjectsOnly {false}
rt::set_parameter propagateConstantsPostPlace {true}
rt::set_parameter resizeBudgetMode {0}
rt::set_parameter resizeCutOff {10000000}
rt::set_parameter resizeEffortHigh {}
rt::set_parameter resizeFreezeTimingModel {false}
rt::set_parameter resizeRemainingPass {0}
rt::set_parameter resizeSequentialToZeroSlack {false}
rt::set_parameter shieldCriticalRangeMultiplier {1.000000}
rt::set_parameter shieldingAlwaysRemoveBuffersfromCP {true}
rt::set_parameter shieldingDebug {false}
rt::set_parameter shieldingEffort {1}
rt::set_parameter shieldingFollowSubCriticalNets {false}
rt::set_parameter shieldingHierInstOutputs {false}
rt::set_parameter shieldingInstancePrefix {_shieldBuf}
rt::set_parameter shieldingPostMarginFactor {3.000000}
rt::set_parameter shieldingPreMarginFactor {6.000000}
rt::set_parameter shieldingSkipDFPartitions {false}
rt::set_parameter shieldingSkipMergedPartitions {true}
rt::set_parameter sizingAreaWeight {2.000000}
rt::set_parameter sizingCritLeakWeight {0.500000}
rt::set_parameter sizingCriticalityThreshold {0.500000}
rt::set_parameter sizingDampingFactor {0.500000}
rt::set_parameter sizingDebug {0}
rt::set_parameter sizingEffort {0}
rt::set_parameter sizingGenomeCount {-1}
rt::set_parameter sizingMode {1}
rt::set_parameter sizingMultiplier {1.200000}
rt::set_parameter sizingNegSlackCost {10.000000}
rt::set_parameter sizingNonCritLeakWeight {2.000000}
rt::set_parameter sizingPosSlackCost {0.250000}
rt::set_parameter sizingPreserveLvt {true}
rt::set_parameter sizingPresizeUpdateLoad {true}
rt::set_parameter sizingRange {1}
rt::set_parameter sizingRelaxLeakWeight {0.100000}
rt::set_parameter sizingRelaxNegSlackDecay {10000.000000}
rt::set_parameter sizingRelaxPosSlackDecay {100.000000}
rt::set_parameter sizingSkipTopLevel {false}
rt::set_parameter sizingSlewFactorMultiplier {2.000000}
rt::set_parameter sizingSortGenomes {0}
rt::set_parameter sizingTopLevelOnly {false}
rt::set_parameter sizingUseDeltaSlewEffect {false}
rt::set_parameter sizingUseFastestAtGenome {false}
rt::set_parameter sizingUseRelaxCosting {false}
rt::set_parameter skipTimingOptimization {false}
rt::set_parameter smallvUseCoarseResize {true}
rt::set_parameter stopAfterOptimizingGroups {0}
rt::set_parameter stopAfterRestartLeakage {false}
rt::set_parameter stopBeforeRestartLeakage {false}
rt::set_parameter stopOptimizingAtCount {9999999}
rt::set_parameter stopOptimizingAtSlack {0.000000}
rt::set_parameter stopSizingAtCount {-1}
rt::set_parameter tdHierRegenAll {true}
rt::set_parameter uniquifyOnDemandPercentage {100}
rt::set_parameter useAbcAreaScript {false}
# Group: optimizeOpt
rt::set_parameter optimizeSelPrePlace {101}
# Group: pcr
rt::set_parameter pcr3579 {true}
rt::set_parameter pcr3604 {true}
rt::set_parameter pcr3627 {true}
rt::set_parameter pcr3632 {false}
rt::set_parameter pcr3632b {false}
rt::set_parameter pcr3635 {true}
rt::set_parameter pcr3645 {true}
rt::set_parameter pcr3646 {true}
rt::set_parameter pcr3668 {true}
rt::set_parameter pcr3670 {true}
rt::set_parameter pcr3713 {true}
rt::set_parameter pcr3767 {false}
rt::set_parameter pcr4264 {true}
# Group: physical
rt::set_parameter AnchorPlaceCheckGenome {false}
rt::set_parameter AnchorPlaceConstraint {use_guide}
rt::set_parameter AnchorPlaceDebug {0}
rt::set_parameter AnchorPlaceDissolveNonUserModu {true}
rt::set_parameter AnchorPlaceExcludeNonUserModu {false}
rt::set_parameter BoundPartitionByCenterOfFixedObjs {true}
rt::set_parameter CellDPlace {1}
rt::set_parameter CellPlaceAtGenomeCenter {0}
rt::set_parameter CellPlaceDefaultUtil {75}
rt::set_parameter CellPlaceDetailed {true}
rt::set_parameter CellPlaceDivideCore {true}
rt::set_parameter CellPlaceEvenPlacement {1}
rt::set_parameter CellPlaceFGC {1}
rt::set_parameter CellPlaceFRInvalidOk {1}
rt::set_parameter CellPlaceFRUseChopper {0}
rt::set_parameter CellPlaceGenomeRegionRange {1.500000}
rt::set_parameter CellPlaceGenomeRegionSlackMargin {1000}
rt::set_parameter CellPlaceGlobal {true}
rt::set_parameter CellPlaceInflation {1}
rt::set_parameter CellPlaceInflationMultiplier {0.750000}
rt::set_parameter CellPlaceInitFromScratch {1}
rt::set_parameter CellPlaceLegal {true}
rt::set_parameter CellPlaceLegalizationShift {5}
rt::set_parameter CellPlaceLocalBinWidth {6}
rt::set_parameter CellPlaceMaxInflation {1.000000}
rt::set_parameter CellPlaceMaxPartitionWidth {1000}
rt::set_parameter CellPlaceMultiLevelTiming {2}
rt::set_parameter CellPlacePaddingCriteria {2147483647.000000}
rt::set_parameter CellPlacePaddingFactor {0.000000}
rt::set_parameter CellPlaceQueueConcurrent {1}
rt::set_parameter CellPlaceRespectGenomeRegion {1}
rt::set_parameter CellPlaceRespectGenomeRegionCriticalOnly {false}
rt::set_parameter CellPlaceRespectGenomes {1}
rt::set_parameter CellPlaceSemiTimingDriven {0}
rt::set_parameter CellPlaceThreads {1}
rt::set_parameter CellPlaceTimingDebug {0}
rt::set_parameter CellPlaceTimingDriven {0}
rt::set_parameter CellPlaceTimingEffort {1.500000}
rt::set_parameter CellPlaceWithQuickTiming {true}
rt::set_parameter ChopperCentralCut {0}
rt::set_parameter ChopperDebug {0}
rt::set_parameter ChopperDefaultDensity {90}
rt::set_parameter ChopperDominatorOverlapRemoval {1}
rt::set_parameter ChopperUseMacroCut {1}
rt::set_parameter ChopperVerbose {0}
rt::set_parameter DEFUnitsPerMicron {2000}
rt::set_parameter DPlaceDebug {0}
rt::set_parameter DPlaceDumpGSRC {0}
rt::set_parameter EdgeAnchorWt {2}
rt::set_parameter ExternalPlacementAdjustment {1}
rt::set_parameter FPlaceBinDivider {5}
rt::set_parameter FPlaceDebug {0}
rt::set_parameter FPlaceDebugFixedPoint {0}
rt::set_parameter FPlaceExpansionUseAveUnitForce {1}
rt::set_parameter FPlaceHotspotRemoval {0}
rt::set_parameter FPlaceHotspotThreshold {10}
rt::set_parameter FPlaceIterations {75}
rt::set_parameter FPlaceMacroTopOverlapRemoval {1}
rt::set_parameter FPlacePlot {25}
rt::set_parameter FPlaceRemoveOverlap {1}
rt::set_parameter FPlaceScale {4}
rt::set_parameter FPlaceScaleForce {0}
rt::set_parameter FPlaceTimingDriven {1}
rt::set_parameter FPlaceTimingDrivenDebug {0}
rt::set_parameter FPlaceTimingOptEffort {1}
rt::set_parameter FPlaceTimingOptWeightingDistExp {1.000000}
rt::set_parameter FPlaceTimingOptWeightingExp {3.000000}
rt::set_parameter FPlaceVerbose {0}
rt::set_parameter FPlaceWLOpt {0}
rt::set_parameter FPlaceWLOptMaxFanout {50}
rt::set_parameter FPlaceWLOptPct {5}
rt::set_parameter FPlaceWLOptTimingMargin {250}
rt::set_parameter FRAllowExpandOverBlockage {false}
rt::set_parameter FRAllowMacroOverlap {1}
rt::set_parameter FRExtensionSearchLen {0.250000}
rt::set_parameter FRNeighborhoodCheckMinPoints {6}
rt::set_parameter FRNeighborhoodCheckMinWhiteSpace {50}
rt::set_parameter FRRelocateSmallGenome {false}
rt::set_parameter FRSmallGenomeMaxSize {14}
rt::set_parameter FRSmallGenomeNoOverlap {false}
rt::set_parameter FRUseChopperOnly {0}
rt::set_parameter FloorplanAlignRegions {1}
rt::set_parameter FloorplanAreaThreshold {1000000}
rt::set_parameter FloorplanBuildPhysicalPartition {1}
rt::set_parameter GenomeMinWidth {6}
rt::set_parameter GenomeWhiteSpace {10.000000}
rt::set_parameter GraphVerbose {0}
rt::set_parameter GridVerbose {0}
rt::set_parameter IgnoreLFOWireLength {false}
rt::set_parameter InitialPartition {use_priority_queue}
rt::set_parameter LegalizerAll {1}
rt::set_parameter LegalizerBinSize {1}
rt::set_parameter LegalizerDebug {0}
rt::set_parameter LegalizerGlobalOpt {0}
rt::set_parameter LegalizerOptRange {500}
rt::set_parameter LegalizerSizeThreshold {4}
rt::set_parameter LegalizerVerbose {0}
rt::set_parameter MLPartDebug {0}
rt::set_parameter MLPartMaxClusterLevel {0}
rt::set_parameter MacroLegalizerAllowReshape {false}
rt::set_parameter MacroLegalizerDebug {0}
rt::set_parameter MacroLegalizerShapeAR {3.000000}
rt::set_parameter MacroLegalizerShapePct {70}
rt::set_parameter MacroLegalizerVerbose {0}
rt::set_parameter MacroPlanMaxModuleSize {20}
rt::set_parameter MatrixVerbose {0}
rt::set_parameter MaxAreaRatio {4.000000}
rt::set_parameter MaxNegGain {10}
rt::set_parameter MaxPinNumScale {1.500000}
rt::set_parameter NGraphClusterDebug {0}
rt::set_parameter NGraphClusterMacroExclusive {0}
rt::set_parameter NGraphClusterStrictRegion {1}
rt::set_parameter NGraphDebug {0}
rt::set_parameter NGraphFanoutThreshold {2000}
rt::set_parameter NGraphFixedNodeWeight {0.000000}
rt::set_parameter NGraphUIDebug {0}
rt::set_parameter NGraphUIPinSize {1}
rt::set_parameter NGraphUIReduction {0}
rt::set_parameter NPlaceAbsorbSmallObjects {0}
rt::set_parameter NPlaceAll {0}
rt::set_parameter NPlaceAlwaysAdjustWhiteSpace {true}
rt::set_parameter NPlaceBlockCongestedArea {false}
rt::set_parameter NPlaceCellControllerIterations {10}
rt::set_parameter NPlaceCellControllerNum {1}
rt::set_parameter NPlaceCellControllerNumda {1.000000}
rt::set_parameter NPlaceCellControllerNumdaStepLength {2.000000}
rt::set_parameter NPlaceCellControllerOverflowTolerance {0.020000}
rt::set_parameter NPlaceCellControllerRadius {2}
rt::set_parameter NPlaceCellControllerStepLength {0.200000}
rt::set_parameter NPlaceCellMaxLevels {100}
rt::set_parameter NPlaceClusterExtDensity {0.500000}
rt::set_parameter NPlaceCompact {0}
rt::set_parameter NPlaceCompactSTD {0}
rt::set_parameter NPlaceConstraintDriven {1}
rt::set_parameter NPlaceConstraintOptExp {3.000000}
rt::set_parameter NPlaceDebug {0}
rt::set_parameter NPlaceDebug2 {0}
rt::set_parameter NPlaceDebugMV {0}
rt::set_parameter NPlaceDesignResize {0}
rt::set_parameter NPlaceDumpConstrConnections {0}
rt::set_parameter NPlaceFixGridNodeArea {0.000400}
rt::set_parameter NPlaceFixedMacroMargin {0.050000}
rt::set_parameter NPlaceFixedNodeWeightMultiplier {1.000000}
rt::set_parameter NPlaceGraphDebug {0}
rt::set_parameter NPlaceGroupFixedObjects {1}
rt::set_parameter NPlaceGuideRegionBarrier {0.500000}
rt::set_parameter NPlaceHierConstraintUpdateInterval {10}
rt::set_parameter NPlaceHierControllerBinSize {0.200000}
rt::set_parameter NPlaceHierControllerIterations {20}
rt::set_parameter NPlaceHierControllerNum {1}
rt::set_parameter NPlaceHierControllerNumda {1.250000}
rt::set_parameter NPlaceHierControllerNumdaStepLength {2.000000}
rt::set_parameter NPlaceHierControllerRadius {2}
rt::set_parameter NPlaceHierControllerStepLength {0.025000}
rt::set_parameter NPlaceIncConstraintDriven {2}
rt::set_parameter NPlaceIncConstraintMultiplier {20.000000}
rt::set_parameter NPlaceIncConstraintMultiplier2 {4.000000}
rt::set_parameter NPlaceIncConstraintUpdateInterval {1000000}
rt::set_parameter NPlaceIncControllerBinSize {0.200000}
rt::set_parameter NPlaceIncControllerIterations {10}
rt::set_parameter NPlaceIncControllerNum {1}
rt::set_parameter NPlaceIncControllerNumda {5.000000}
rt::set_parameter NPlaceIncControllerNumdaStepLength {2.000000}
rt::set_parameter NPlaceIncControllerRadius {2}
rt::set_parameter NPlaceIncControllerStepLength {0.025000}
rt::set_parameter NPlaceIncEffort {1}
rt::set_parameter NPlaceIncUseWL {false}
rt::set_parameter NPlaceIncrementalDensityScale {1.000000}
rt::set_parameter NPlaceIncrementalPostProcessSmallObjects {0}
rt::set_parameter NPlaceIncrementalSlackMargin {1.000000}
rt::set_parameter NPlaceIncrementalStoppingCriteria {0.000000}
rt::set_parameter NPlaceInflateSmall {1}
rt::set_parameter NPlaceInflateSmallEqual {1}
rt::set_parameter NPlaceInflateSmallMaxRatio {1.250000}
rt::set_parameter NPlaceInflateSmallWSRatio {0.200000}
rt::set_parameter NPlaceMaxFanout {250}
rt::set_parameter NPlaceMaxGrid {300}
rt::set_parameter NPlaceMaxLevels {1000}
rt::set_parameter NPlaceMinClusters {100}
rt::set_parameter NPlaceMinNodeArea {0.000010}
rt::set_parameter NPlaceMinWidthPerDegreeScale {0.500000}
rt::set_parameter NPlaceMultiLevel {1}
rt::set_parameter NPlaceMultiLevelTiming {2}
rt::set_parameter NPlaceMultiLevelWL {1}
rt::set_parameter NPlaceNodeExtDensity {1.000000}
rt::set_parameter NPlaceOpacity {1.000000}
rt::set_parameter NPlacePlaceSmallObjects {0}
rt::set_parameter NPlacePlotDegree {0}
rt::set_parameter NPlacePlotName {0}
rt::set_parameter NPlacePostProcessSmallObjects {2}
rt::set_parameter NPlacePostProcessSmallObjectsTimingDriven {0}
rt::set_parameter NPlacePreProcessSmallObjects {7}
rt::set_parameter NPlaceRadius {2}
rt::set_parameter NPlaceRegionBarrier {1.000000}
rt::set_parameter NPlaceResearch {}
rt::set_parameter NPlaceStartAtCenter {1}
rt::set_parameter NPlaceTestClusterPlacement {0}
rt::set_parameter NPlaceTestUnitArea {0}
rt::set_parameter NPlaceTimingCalibrationAdjust {1.000000}
rt::set_parameter NPlaceTimingDriven {0}
rt::set_parameter NPlaceTimingDrivenEffort {0}
rt::set_parameter NPlaceTimingOptSafeSlack {3000}
rt::set_parameter NPlaceTimingOptSlackMargin {500}
rt::set_parameter NPlaceTimingOptWeightingDistExp {1.000000}
rt::set_parameter NPlaceTimingOptWeightingExp {2.000000}
rt::set_parameter NPlaceTopConstraintUpdateInterval {8}
rt::set_parameter NPlaceTopController0BinSize {1.000000}
rt::set_parameter NPlaceTopController0Iterations {16}
rt::set_parameter NPlaceTopController0Numda {0.250000}
rt::set_parameter NPlaceTopController0NumdaStepLength {1.500000}
rt::set_parameter NPlaceTopController0Radius {2}
rt::set_parameter NPlaceTopController0StepLength {0.020000}
rt::set_parameter NPlaceTopController1BinSize {0.750000}
rt::set_parameter NPlaceTopController1Iterations {16}
rt::set_parameter NPlaceTopController1Numda {0.500000}
rt::set_parameter NPlaceTopController1NumdaStepLength {2.000000}
rt::set_parameter NPlaceTopController1Radius {2}
rt::set_parameter NPlaceTopController1StepLength {0.025000}
rt::set_parameter NPlaceTopController2BinSize {0.500000}
rt::set_parameter NPlaceTopController2Iterations {16}
rt::set_parameter NPlaceTopController2Numda {2.500000}
rt::set_parameter NPlaceTopController2NumdaStepLength {2.000000}
rt::set_parameter NPlaceTopController2Radius {2}
rt::set_parameter NPlaceTopController2StepLength {0.025000}
rt::set_parameter NPlaceTopControllerNum {3}
rt::set_parameter NPlaceUseFinalIncController {true}
rt::set_parameter NPlaceUseRegion {1}
rt::set_parameter NPlaceUseWeightedSlack {false}
rt::set_parameter NPlaceUserDensity {-1.000000}
rt::set_parameter NPlaceVerbose {0}
rt::set_parameter NPlaceWeightedGraph {1}
rt::set_parameter NPlaceWireLengthDriven {true}
rt::set_parameter OptimizeClockGatePlacement {false}
rt::set_parameter OrderLargePartition {first}
rt::set_parameter PartitionDebug {0}
rt::set_parameter PartitionIgnoreLocations {true}
rt::set_parameter PartitionPinsOnBBoxSides {true}
rt::set_parameter PartitionUseMaxSize {true}
rt::set_parameter PhysicalOpt {false}
rt::set_parameter PhysicalPartitionDebug {1}
rt::set_parameter PhysicalPartitionPinAssignment {true}
rt::set_parameter PinAssignDebug {0}
rt::set_parameter PlaceCongestionDriven {1}
rt::set_parameter PlaceStepThru {false}
rt::set_parameter PlaceUseMaxSize {true}
rt::set_parameter RationAvailableArea {true}
rt::set_parameter ScaleGSRCTest {1}
rt::set_parameter SkipPinAssignment {false}
rt::set_parameter TopLevelWhiteSpace {25.000000}
rt::set_parameter UseDefaultGenomeWhiteSpace {0}
rt::set_parameter UseScanLine {true}
rt::set_parameter WritePhysicalPartitionDebug {1}
rt::set_parameter WritePhysicalPartitionSkip {lib}
rt::set_parameter allowGrow {false}
rt::set_parameter assignMacroMaxModuleArea {3000000}
rt::set_parameter autoGroupMacros {0}
rt::set_parameter autoHaloMacros {1}
rt::set_parameter autoMacroOrientation {1}
rt::set_parameter autoMacroPlacement {1}
rt::set_parameter cutSlackFactor {5.000000}
rt::set_parameter debugTotalWL {0}
rt::set_parameter die_aspect_ratio {1.000000}
rt::set_parameter fastPlaceEffort {1}
rt::set_parameter fastPlaceIgnoreUnplaced {false}
rt::set_parameter fastPlacePostRepartition {true}
rt::set_parameter fastPlaceSlackMargin {0}
rt::set_parameter fastPlaceStopOnPositiveSlack {false}
rt::set_parameter flatAllWireLength {false}
rt::set_parameter flatWireLength {false}
rt::set_parameter floorplanNoMacroGrouping {0}
rt::set_parameter genomePlaceFillRatio {1.000000}
rt::set_parameter genomePlaceFullSpreading {0}
rt::set_parameter genomePlaceFullSpreadingFactor {1.000000}
rt::set_parameter groupMacroMaxModuleArea {1000000}
rt::set_parameter incrementalPlacementKeepTiming {false}
rt::set_parameter incrementalPlacementKeepTimingMargin {100}
rt::set_parameter incrementalPlacementMobility {10.000000}
rt::set_parameter incrementalPlacementRestrictTimer {false}
rt::set_parameter incrementalPlacementTimingOpt {1}
rt::set_parameter incrementalPlacementUseSimpleGraph {true}
rt::set_parameter keepAutoHalos {0}
rt::set_parameter macroPlanAllowRotate {1}
rt::set_parameter macroPlanBlockClosedRegion {0}
rt::set_parameter macroPlanBoundSize {0.500000}
rt::set_parameter macroPlanClosedRegionBlockageResolution {1000}
rt::set_parameter macroPlanClosedRegionMaxSize {10}
rt::set_parameter macroPlanIgnoreSmall {0}
rt::set_parameter macroPlanModulePlacementOnly {0}
rt::set_parameter macroPlanPartitionResolution {100}
rt::set_parameter macroPlanSpacing {2}
rt::set_parameter maxAllowedUtilization {85}
rt::set_parameter maxMacroHalo {50.000000}
rt::set_parameter maxUtilizationForRefine {80}
rt::set_parameter maximizeCutSlack {true}
rt::set_parameter minMacroHalo {5.000000}
rt::set_parameter newPartitioner {true}
rt::set_parameter newPartitionerDebug {0}
rt::set_parameter partitionFanoutThreshold {10000}
rt::set_parameter partitionOrderBasedOnSize {true}
rt::set_parameter partitionTimingDriven {false}
rt::set_parameter partitionToMax {true}
rt::set_parameter placeTimingDriven {true}
rt::set_parameter placedPinsAreFixed {false}
rt::set_parameter powerGuideWidthFactor {2}
rt::set_parameter refineBoundaryGenomesFirst {false}
rt::set_parameter removeOverlapInFRMap {true}
rt::set_parameter reportTimingAtPlacement {false}
rt::set_parameter slackMarginInPlace {0}
rt::set_parameter slackMultiplierInPlace {3.000000}
rt::set_parameter smallMacroMaxArea {15000}
rt::set_parameter unitMacroPinHalo {0.050000}
rt::set_parameter updateSlacksInPlace {false}
rt::set_parameter useFlatPinCountInPartitioner {false}
rt::set_parameter useMaxAreaRatioForAnchors {true}
rt::set_parameter weightAttractByEdgeDegree {false}
# Group: plib
rt::set_parameter capAdjust {1.000000}
rt::set_parameter ignoreEdgeCap {false}
rt::set_parameter rcProximityForLayerGrouping {90}
rt::set_parameter resAdjust {1.000000}
rt::set_parameter unitsPerMicron {20000}
# Group: pruneselectbits
rt::set_parameter enhancepruneSelectBits {false}
# Group: rangeOptimization
rt::set_parameter checkPowerOfTwoExpr {true}
rt::set_parameter computeAPConditionalRange {true}
rt::set_parameter computeAPRangeForDfgPatterns {true}
rt::set_parameter computeAPRangeForVariableMuxNodes {false}
rt::set_parameter computeConditionalRange {true}
rt::set_parameter computeConstantMod {true}
rt::set_parameter computeRangeForConcatNode {false}
rt::set_parameter conditionalRangeComputationThreshold {4096}
rt::set_parameter considerNegativeRangeForEquality {false}
rt::set_parameter debugAPRangeOptimization {false}
rt::set_parameter debugRangeOptimization {false}
rt::set_parameter forceModLibraryImplementation {false}
rt::set_parameter makeOutputConstantFromRange {true}
rt::set_parameter markAdderChainToSkipBitwidthOpti {true}
rt::set_parameter markShareableOpsToSkipBitwidthOpti {true}
rt::set_parameter maxLevelToFindDecisivePin {4}
rt::set_parameter muxChainLengthForConditionalMod {5}
rt::set_parameter optimizeBitwidthUsingWireNode {true}
rt::set_parameter optimizeBselUsingRangeset {true}
rt::set_parameter optimizeComparatorsUsingRangeset {true}
rt::set_parameter optimizeConditionalModWithMuxChain {true}
rt::set_parameter optimizeDfgSizing {true}
rt::set_parameter optimizeEqOperator {true}
rt::set_parameter optimizeFSMMuxUsingRangeSet {false}
rt::set_parameter optimizeMuxUsingRangeset {true}
rt::set_parameter optimizeNodeFromAPRangeSet {true}
rt::set_parameter optimizeNodeFromRangeSet {false}
rt::set_parameter optimizePowerOf2DivPattern {true}
rt::set_parameter optimizePowerOfTwoDiv {true}
rt::set_parameter optimizePowerOfTwoMod {true}
rt::set_parameter optimizeShiftUsingRangeset {true}
rt::set_parameter propagateConstantsForMod {true}
rt::set_parameter propagateRangeThroughRegNodes {false}
rt::set_parameter rangeBasedLogicOperatorOptimization {true}
rt::set_parameter rangeBasedOperatorOptimization {true}
rt::set_parameter rangeBasedRedundancyRemoval {true}
rt::set_parameter recomputeAPRangeSetForRegNodes {false}
rt::set_parameter recomputeRangeForRegWithFeedback {false}
rt::set_parameter transformOperators {true}
# Group: reports
rt::set_parameter reportModulesHideNonUserModules {true}
rt::set_parameter reportVirtualModulesAtLevel {0}
# Group: syn
rt::set_parameter AvgNeighbourDensity {10.000000}
rt::set_parameter DFDupWithHierarchy {true}
rt::set_parameter DFDupWithVirtualEdges {false}
rt::set_parameter DFVerifyDebug {false}
rt::set_parameter DFVerifyVerbose {true}
rt::set_parameter DebugExtractRuntime {0}
rt::set_parameter ExtractDebug {0}
rt::set_parameter ExtractKeepRealModuleWithGraph {1}
rt::set_parameter ExtractPhyFixedNeighborsOnly {false}
rt::set_parameter ExtractPhyMaxLevels {1}
rt::set_parameter ExtractUsePairwiseClustering {0}
rt::set_parameter ExtractVerbose {0}
rt::set_parameter PartitionAllowUnconnected {true}
rt::set_parameter PartitionConnectedCompsFirst {true}
rt::set_parameter PartitionMaxPinCount {1000000}
rt::set_parameter PartitionSpareCells {false}
rt::set_parameter ProhibitMultiCE4Block {true}
rt::set_parameter RepartitionCriticalRange {50}
rt::set_parameter RepartitionExcludeGenome {true}
rt::set_parameter RepartitionExcludeLeafCells {true}
rt::set_parameter RepartitionGroupRegistersWithLogic {0}
rt::set_parameter RepartitionKeepHistory {false}
rt::set_parameter RepartitionKeepRegistersInOriginalGenome {false}
rt::set_parameter RepartitionKeepRegistersInOriginalPlacedGenome {true}
rt::set_parameter RepartitionPlaceGenomesInOriginalLocations {1}
rt::set_parameter RepartitionPostProcessDisjointComponents {0}
rt::set_parameter UPFDefaultIsolationHandle {default_isolation}
rt::set_parameter UPFDefaultRetentionHandle {default_retention}
rt::set_parameter UPFDomainPrimaryHandle {primary}
rt::set_parameter UPFImplicitLevelShifter {true}
rt::set_parameter UPFIsolationPrefix {UPF_ISO}
rt::set_parameter UPFIsolationSuffix {}
rt::set_parameter UPFIsolationSupplyHandle {isolation_supply_set}
rt::set_parameter UPFLevelShiftPrefix {UPF_LS}
rt::set_parameter UPFRetentionSupplyHandle {retention_supply}
rt::set_parameter UPFSwitchSupplyHandle {supply}
rt::set_parameter __deliberateBadLogic {false}
rt::set_parameter absoluteTmpDirPath {/var/jenkins_home/workspace/SuperScalar-RISCV-CPU/SuperScalar-RISCV-CPU/.Xil/Vivado-3622754-685a421e500f}
rt::set_parameter absorbDspPatternDetect {true}
rt::set_parameter addAttributesToRamGraph {true}
rt::set_parameter addGenomesPostCleanup {true}
rt::set_parameter addPathInMacroDotCluster {false}
rt::set_parameter addToLogicThreshold {9}
rt::set_parameter addToLogicThresholdMax {31}
rt::set_parameter addXPinsInPushRW {true}
rt::set_parameter advancedConstPropAcrossHier {true}
rt::set_parameter advancedMemoryDissolve {true}
rt::set_parameter aggressiveAPRangeSetComputation {true}
rt::set_parameter aggressiveAdderCollapseForVersal {true}
rt::set_parameter aggressiveCollapseBMerges {true}
rt::set_parameter aggressiveCollapseLogicOperators {false}
rt::set_parameter aggressiveConditionalRangeSetOpt {true}
rt::set_parameter aggressiveFanoutMerging {1}
rt::set_parameter aggressiveOperatorSharing {false}
rt::set_parameter aggressiveRangeOpt {false}
rt::set_parameter aggressiveRangeSetComputation {true}
rt::set_parameter aggressiveSingleFanoutMerging {0}
rt::set_parameter allowAndOrForMux {true}
rt::set_parameter allowBMergeAsReconvergentSink {true}
rt::set_parameter allowCurrentInstanceInChildProc {true}
rt::set_parameter allowFsmMuxControlCollapse {false}
rt::set_parameter allowFsmWithInitVal {true}
rt::set_parameter allowFsmWithNoReset {false}
rt::set_parameter allowMismatchedAddressForBram {true}
rt::set_parameter allowNandForXor {false}
rt::set_parameter allowPotentialFsmMuxControlCollapse {false}
rt::set_parameter allowRepartitionOnMergedGenomes {false}
rt::set_parameter allowSignedInputForPruningRegisterWithEnable {false}
rt::set_parameter allowSyncRSFsm {true}
rt::set_parameter analyzeControlSetsAlwaysBlock {false}
rt::set_parameter applyKeepOnFsmRegister {false}
rt::set_parameter areaDiffPercentage {1.500000}
rt::set_parameter areaOptMergeMuxpart {true}
rt::set_parameter areaOptMergeXilinxInferred {true}
rt::set_parameter areaOptMergeXilinxInferred2 {true}
rt::set_parameter areaStrategyForFsm {false}
rt::set_parameter assignsForBusNetlist {0}
rt::set_parameter attributeOnFsmKeep {true}
rt::set_parameter autoSynRetiming {false}
rt::set_parameter avoidFsmEncoder {true}
rt::set_parameter avoidResetForRamSituations {false}
rt::set_parameter avoidSplitPartitionForBitNodesWithDonotCare {true}
rt::set_parameter bSelInSizeReductionThreshold {16384}
rt::set_parameter bddGenBucketSizeMultFpga {1.000000}
rt::set_parameter bddSupportForCtrlSetAttributes {true}
rt::set_parameter bitOperatorsInDFPartitionInput {false}
rt::set_parameter bitOperatorsInLogicPartition {true}
rt::set_parameter bitSliceDfgWordSize {2147483647}
rt::set_parameter bitSliceLogicNodes {false}
rt::set_parameter bitSliceNonRegMergeNodes {true}
rt::set_parameter bitwiseControl {true}
rt::set_parameter blackBoxForEmptyModule {true}
rt::set_parameter blackBoxForceInputPort {true}
rt::set_parameter breakLoopAtRegisters {true}
rt::set_parameter buildRamFromRecordsAnd3D {true}
rt::set_parameter bypassAritmeticCheckInMarkCarrySaveCandidates {false}
rt::set_parameter callNlOptRomBeforePartitioning {false}
rt::set_parameter cascade_height {-1}
rt::set_parameter changeInSBlockOnly {false}
rt::set_parameter checkAreaDuringRemap {true}
rt::set_parameter checkBufferForSynthesis {true}
rt::set_parameter checkConstPropRunTime {false}
rt::set_parameter checkFalseFanoutsAtPartitionInputs {1}
rt::set_parameter checkForMaxPrintGetPinsCount {false}
rt::set_parameter checkForStackOverflow {true}
rt::set_parameter checkForStructuralNetlist {false}
rt::set_parameter checkFsmEncodingNeeded {true}
rt::set_parameter checkFsmUserEncodingInRegen {false}
rt::set_parameter checkGraphInGenerate {true}
rt::set_parameter checkIBTForCGSynthesis {false}
rt::set_parameter checkIBTForSynthesis {false}
rt::set_parameter checkLicenseHoldSupport {true}
rt::set_parameter checkLogicDepthAtMuxSelect {within_module}
rt::set_parameter checkMuxInOutsForEquivalency {true}
rt::set_parameter checkMuxInputsForSignExtension {true}
rt::set_parameter checkPhysicalLibraryForSynthesis {false}
rt::set_parameter checkStackOverFlowConstProp {true}
rt::set_parameter checkUnsupported {true}
rt::set_parameter cleanUpAfterRetiming {true}
rt::set_parameter cleanupBitOperatorsInReinfer {true}
rt::set_parameter cleanupClockGatesInOptimize {true}
rt::set_parameter cleanupFsm {false}
rt::set_parameter cleanupInstantiatedClockGates {false}
rt::set_parameter cleanupUnreachableNets {true}
rt::set_parameter clearDotOnGraphRemoval {false}
rt::set_parameter clockGatingMinimumWidth {4}
rt::set_parameter clockGatingObservability {false}
rt::set_parameter cloneLatchDataLogic {true}
rt::set_parameter clonePartitionModuleBeforeMerging {false}
rt::set_parameter cloneRegisterDataLogic {false}
rt::set_parameter collapseAWMergeNodesInCollapseTwinAW {true}
rt::set_parameter collapseAddEquality {false}
rt::set_parameter collapseAwrite {true}
rt::set_parameter collapseBMerges {false}
rt::set_parameter collapseBMergesDuringOpt {true}
rt::set_parameter collapseFsmInputMux {false}
rt::set_parameter collapseFsmMux {false}
rt::set_parameter collapseFsmMuxThreshold {5}
rt::set_parameter collapseLogicOperators {true}
rt::set_parameter collapseMergeAfterValueNumberReg {true}
rt::set_parameter collapseMergeInSameGraph {false}
rt::set_parameter collapseMergeInSameGraphLookupDepth {30}
rt::set_parameter collapseMultiFanoutBinaryAdders {true}
rt::set_parameter collapseMuxChain {1}
rt::set_parameter collapseMuxChainCheckCarrySaveInput {true}
rt::set_parameter collapseMuxChainCheckConstantInput {false}
rt::set_parameter collapseMuxChainFsm {false}
rt::set_parameter collapseMuxFsm {true}
rt::set_parameter collapseOperators {true}
rt::set_parameter collapseOperatorsWithNonUnitFanout {1}
rt::set_parameter collapseReconvergentMerge {true}
rt::set_parameter commonSubexpressionElimination {true}
rt::set_parameter comparatorInLogicPartitionThreshold {64}
rt::set_parameter compileOnly {false}
rt::set_parameter computeAPConditionalRangeSet {true}
rt::set_parameter computeAPDomainAcrossBinaryLogic {true}
rt::set_parameter computeAPDomainAcrossConnectionNodes {true}
rt::set_parameter computeAPDomainForDefaultDataInMux {true}
rt::set_parameter computeAPDomainForGraphPins {true}
rt::set_parameter computeAPRangeForLogicNodes {true}
rt::set_parameter computeAPRangeSetForLogicNodes {true}
rt::set_parameter computeCondRangeForControlPinDrivers {true}
rt::set_parameter computeRangeSetForVarInputMux {true}
rt::set_parameter computeSetInDomainInfo {true}
rt::set_parameter conditionalConstProp {true}
rt::set_parameter congestionDrivenSplittingMode {1}
rt::set_parameter congestion_driven_extract {false}
rt::set_parameter connectConstantForGenomeUndrivenPin {false}
rt::set_parameter connectConstantPinsForNetlist {true}
rt::set_parameter connectTopModUndrivenPinToObuft {true}
rt::set_parameter connectUndrivenVHDL {true}
rt::set_parameter connectXToRedundantDataPins {false}
rt::set_parameter considerFsmAttrsInFirstInference {true}
rt::set_parameter considerReachableForFsmOutput {true}
rt::set_parameter considerSignOfMuxInEdges {true}
rt::set_parameter constPropBramV10 {true}
rt::set_parameter constPropCSA {false}
rt::set_parameter constPropClockGate {false}
rt::set_parameter constPropDspV10 {true}
rt::set_parameter constPropIgnoreDontTouchOnFunnel {true}
rt::set_parameter constPropIgnoreKeepHier {false}
rt::set_parameter constPropIgnoreKeepHierSoft {false}
rt::set_parameter constPropInsideDontTouch {true}
rt::set_parameter constPropIterations {1000}
rt::set_parameter constPropUramV10 {true}
rt::set_parameter constPropUseFFEnableDontCare {false}
rt::set_parameter constantMuxesWithSameSel {true}
rt::set_parameter constantShiftInLogicPartition {true}
rt::set_parameter constpropAfterUserModuleResyn {true}
rt::set_parameter constpropBDDforUndrivenNet {true}
rt::set_parameter constpropFix2018_3 {true}
rt::set_parameter constructSizeLimitForDfgVerilog {10000}
rt::set_parameter constructStgInGenerator {true}
rt::set_parameter contiguousRangeThresholdToEnableReduceBigSharedMux {10}
rt::set_parameter controlSetSwitch {false}
rt::set_parameter convertConstructInputsToRanges {true}
rt::set_parameter convertMux2WireWithSameAsDefault {false}
rt::set_parameter convertSubShiftAdd {true}
rt::set_parameter copyTopGraphOnceForGraphDiffer {true}
rt::set_parameter countDFPartitionArea {false}
rt::set_parameter countElabPrimitiveNodes {false}
rt::set_parameter createAreaOptMLInfo {false}
rt::set_parameter createClockGateControlPort {true}
rt::set_parameter createConnectionDfg {false}
rt::set_parameter createDetector {0}
rt::set_parameter createDfgPartConstrRecurLimit {50}
rt::set_parameter createDfgPartMergeRecurLimit {50}
rt::set_parameter createFsmGraphWithUniquifiedPorts {true}
rt::set_parameter createHierarchyForLoopBodies {false}
rt::set_parameter createHierarchyForLoopInsideConstFunc {false}
rt::set_parameter createLogicPartitionForWire {false}
rt::set_parameter createRegPartitionForNegEdgeClock {true}
rt::set_parameter createRegisterPartition {false}
rt::set_parameter createRtlPartitionForBitAssign {false}
rt::set_parameter createSmallGenomeForCongestion {0}
rt::set_parameter createWireForUnmatchedEdges {true}
rt::set_parameter criticalRegThreshold {5}
rt::set_parameter crossBoundaryOpt {true}
rt::set_parameter cseBmerge {false}
rt::set_parameter cseFunctions {true}
rt::set_parameter cseNonWiredBmerge {false}
rt::set_parameter cseRuntimeFix {true}
rt::set_parameter currentInstPath {}
rt::set_parameter customModulePatternText {customArchText}
rt::set_parameter dataFlowViewInElab {false}
rt::set_parameter dataflowBusHighlighting {false}
rt::set_parameter dataflowEnableDeadcodeRemoval {true}
rt::set_parameter dataflowGraphClustering {false}
rt::set_parameter dataflowGraphPass2Clustering {false}
rt::set_parameter dataflowHierBusHighlighting {true}
rt::set_parameter dataflowHighlighting {false}
rt::set_parameter dataflowMinBusWidth {4}
rt::set_parameter dataflowPass2BusHighlighting {false}
rt::set_parameter dataflowPathAllowMultifanouts {true}
rt::set_parameter dataflowPathWidthThreshold {16}
rt::set_parameter dataflowPruneDeadMuxes {true}
rt::set_parameter dataflowPruneNonWideBussedAdders {true}
rt::set_parameter dataflowTagging {false}
rt::set_parameter datapathAddThreshold {11}
rt::set_parameter datapathAddThresholdCarry8 {6}
rt::set_parameter datapathAddTimingThreshold {11}
rt::set_parameter datapathComparatorConstThreshold {30}
rt::set_parameter datapathComparatorThreshold {6}
rt::set_parameter datapathComparatorThresholdCarry8 {14}
rt::set_parameter datapathDensePacking {false}
rt::set_parameter datapathEqThreshold {8}
rt::set_parameter datapathEqThresholdCarry8 {36}
rt::set_parameter datapathMergeConstantIn {false}
rt::set_parameter datapathMultThresholdDensePack {11}
rt::set_parameter datapathShifterReduction {true}
rt::set_parameter datapathStartWithMinArea {false}
rt::set_parameter debugBusGraph {false}
rt::set_parameter debugConstProp {0}
rt::set_parameter debugCrossBoundaryCprop {0}
rt::set_parameter debugExtractRamWordEnable {false}
rt::set_parameter debugGenControl {0}
rt::set_parameter debugGenomeCP {false}
rt::set_parameter debugGenomeEquivalencies {false}
rt::set_parameter debugGraph {false}
rt::set_parameter debugIncrSynConnectivity {false}
rt::set_parameter debugIncrementalNlOpt {false}
rt::set_parameter debugLoopExitOpt {0}
rt::set_parameter debugLoopOpt {0}
rt::set_parameter debugMV {false}
rt::set_parameter debugMarkingCarrySave {false}
rt::set_parameter debugOptimizeComparators {false}
rt::set_parameter debugPreElabScanFlow {false}
rt::set_parameter debugRamFromRecordsAnd3D {0}
rt::set_parameter debugRamPruning {0}
rt::set_parameter debugRangeOpt {0}
rt::set_parameter debugRangeSetOptimization {false}
rt::set_parameter debugSBlocks {false}
rt::set_parameter debugSecureStepNetlistWriter {false}
rt::set_parameter debugSimplifyCM {0}
rt::set_parameter declone {true}
rt::set_parameter decloneComplements {true}
rt::set_parameter decloneDuringRemap {false}
rt::set_parameter decloneFunction {true}
rt::set_parameter decloneInstancesWithSimilarAssertions {true}
rt::set_parameter decloneMemoryRegs {true}
rt::set_parameter decloneMultiDriverRegisters {false}
rt::set_parameter declonePreferNegativeGates {false}
rt::set_parameter decloneScanFlops {true}
rt::set_parameter decomposeVariableBitSelect {true}
rt::set_parameter deepCopyDfgModule {true}
rt::set_parameter deepCopyDfgNodes {true}
rt::set_parameter deepakDebug {0}
rt::set_parameter delayFsmInference {true}
rt::set_parameter delayThreshold {0.500000}
rt::set_parameter designWorstSlack {-1000000}
rt::set_parameter detectPlusOneAsNonLossy {false}
rt::set_parameter detectorDebugLevel {0}
rt::set_parameter detectorOffsetting {true}
rt::set_parameter dfvSettings {}
rt::set_parameter diffNamingType {true}
rt::set_parameter disableGenomeDissolving {true}
rt::set_parameter disableGenomeUniquification {false}
rt::set_parameter disableIncrementalRTLOpt2 {false}
rt::set_parameter disableMuxOptForCasexCasez {true}
rt::set_parameter disableOneHotFsmMuxCollapse {true}
rt::set_parameter disableRSForMultiInputWire {true}
rt::set_parameter disableRSForSigned {true}
rt::set_parameter disableStichPointConnectivityFixing {false}
rt::set_parameter disableTDMapOnTException {true}
rt::set_parameter disconnectNonDrivingPorts {true}
rt::set_parameter disconnectPartitionPin {true}
rt::set_parameter disconnectRedundantBselLoad {true}
rt::set_parameter dissolveChildGenomesOfChangedModules {true}
rt::set_parameter dissolveFinalGraph {false}
rt::set_parameter dissolveFunctions {1}
rt::set_parameter dissolveLibcells {false}
rt::set_parameter dissolveMemory {1}
rt::set_parameter dissolveMemoryAwriteNewDecomp {false}
rt::set_parameter dissolveMemoryMaxWordSize {2147483647}
rt::set_parameter dissolveMemoryNumAddrBitsOnData {3}
rt::set_parameter dissolveMemoryRePartitionReg {true}
rt::set_parameter dissolveMemorySizeLimit {65536}
rt::set_parameter dissolveRealMaxPinCount {2000}
rt::set_parameter dissolveRealMaxPinDensity {10000.000000}
rt::set_parameter dissolveSBlockGenome {false}
rt::set_parameter doAPRangeOptimizationDfg {true}
rt::set_parameter doBramAddrRegResetTransform {false}
rt::set_parameter doComparatorShare {true}
rt::set_parameter doEitherPolarityForMult {true}
rt::set_parameter doIncremental {false}
rt::set_parameter doRangeBasedModNodeOptimization {true}
rt::set_parameter doRangeOptimizationDfg {true}
rt::set_parameter dontCollapseMuxChainInFsmPart {true}
rt::set_parameter dontCountMuxForLogicDepthInfer {true}
rt::set_parameter dontCseConsteqSizeub {false}
rt::set_parameter dontMarkEdgesDrivingPinAOfSub {true}
rt::set_parameter dontMarkEdgesDrivingPinBOfSub {true}
rt::set_parameter dontPartitionBlackBox {true}
rt::set_parameter dontPartitionCRCMod {false}
rt::set_parameter dont_synthesize {}
rt::set_parameter downgradeMessageList {8-3332 8-3936 8-3917 8-506 8-3919 8-3295}
rt::set_parameter dspColumnLength {-1}
rt::set_parameter dspMapWideAdder {true}
rt::set_parameter dspWeightage {100}
rt::set_parameter dumpAttrsInDot {false}
rt::set_parameter dumpDFGFearturesForNloptPrediction {false}
rt::set_parameter dumpGenomesToEnableIncremental {true}
rt::set_parameter dumpMergedRegOnespinHints {false}
rt::set_parameter dumpThroughBuffer {true}
rt::set_parameter duplicateAndMergeBitOperatorsIntoFanouts {false}
rt::set_parameter duplicateWhenMerging {false}
rt::set_parameter earlyCollapseMerge {true}
rt::set_parameter earlyIsolateRegSlice {false}
rt::set_parameter earlyMaximalSharing {true}
rt::set_parameter elabSvlgCreateHierarchyForGenStmt {false}
rt::set_parameter elabVhdlCreateHierarchyForGenStmt {false}
rt::set_parameter elaboratePrototype {false}
rt::set_parameter elaborateRtl {false}
rt::set_parameter eliminateConstRegWithMultLoad {false}
rt::set_parameter eliminateConstantReg {true}
rt::set_parameter eliminateRedundantBitOperator {true}
rt::set_parameter eliminateRedundantBitSelect {true}
rt::set_parameter eliminateRedundantConcatOperator {3}
rt::set_parameter eliminateRedundantMuxWithDiffConstants {true}
rt::set_parameter eliminateRedundantMuxWithFSMSafeDefaultStateAttribute {false}
rt::set_parameter eliminateRedundantReg {false}
rt::set_parameter eliminateRedundantWire {true}
rt::set_parameter eliminateRelativeConstantReg {false}
rt::set_parameter enableAsymRamAsyncReset {true}
rt::set_parameter enableBSelInSizeReduction {true}
rt::set_parameter enableBwweDatapathOpt {true}
rt::set_parameter enableChangeIndependentDissolvedReExtractedGenomesReuse {true}
rt::set_parameter enableEcc {true}
rt::set_parameter enableGenomeSBlockMapUpdate {true}
rt::set_parameter enableIncremental {true}
rt::set_parameter enableInvertedDataInOperatorPushing {false}
rt::set_parameter enableOlympus {false}
rt::set_parameter enablePinsWithNoLoadsCollector {true}
rt::set_parameter enableReportFeasibilityChecks {true}
rt::set_parameter enableRunTimeFixInGenControl {true}
rt::set_parameter enableRunTimeFixInMaxCluster {true}
rt::set_parameter enableShareBMergeCache {true}
rt::set_parameter enableShareBMergeCacheThreshold {65536}
rt::set_parameter enableSplitFlow {true}
rt::set_parameter enableSplitFlowPath {./.Xil/Vivado-3622754-685a421e500f/}
rt::set_parameter enableSplitFlowStep {2}
rt::set_parameter enableSplitFlowXDC {true}
rt::set_parameter encodeFsm {auto}
rt::set_parameter enhancepruneDeadBits {true}
rt::set_parameter equalitiesInLogicPartition {1}
rt::set_parameter error_on_blackbox {false}
rt::set_parameter error_on_cells_with_no_lefs {false}
rt::set_parameter estimateFastestLoadMultiplier {2.000000}
rt::set_parameter evaluateFsmEncoding {true}
rt::set_parameter evaluateFsmWithCollapsedMux {false}
rt::set_parameter exceptionOccuredInStitching {false}
rt::set_parameter excludeMuxPartFromFsm {true}
rt::set_parameter exitFsmAfterCollapse {false}
rt::set_parameter explicitFsmRegName {true}
rt::set_parameter exportSecureStepNetlists {false}
rt::set_parameter expose_empty_module {false}
rt::set_parameter extractBusSynchronousSetReset {true}
rt::set_parameter extractConstantIndexBits {false}
rt::set_parameter extractEnable {true}
rt::set_parameter extractEnableForFSMs {true}
rt::set_parameter extractEnableForOneHotFsm {true}
rt::set_parameter extractEnableFromAssign {true}
rt::set_parameter extractFirstResetOnly {false}
rt::set_parameter extractGenomes {false}
rt::set_parameter extractIgnoreVirtual {false}
rt::set_parameter extractLatchEnablesFirst {true}
rt::set_parameter extractPartialSynchronousSetReset {false}
rt::set_parameter extractRamWordEnable {true}
rt::set_parameter extractSyncControlInNetlist {true}
rt::set_parameter extractSynchronousSetReset {true}
rt::set_parameter extractWithPartition {true}
rt::set_parameter factorTrees {1}
rt::set_parameter factorTreesMaxInputs {2000}
rt::set_parameter fileName {}
rt::set_parameter fixCollapseMerge {false}
rt::set_parameter fixConnectionToOutPort {false}
rt::set_parameter fixDeepCopyDfg {true}
rt::set_parameter fixFsmFeedbackPaths {true}
rt::set_parameter fixFsmFeedbackPathsForOneHotFsm {true}
rt::set_parameter fixFsmFeedbackPathsWithReplication {true}
rt::set_parameter flipflopInitialState {0}
rt::set_parameter floorplanGuidedRepartitionCriteria {-1}
rt::set_parameter forceAsyncRstAsSync {false}
rt::set_parameter forceExtractBlackboxGenomes {true}
rt::set_parameter forceExtractGenerateGenomes {25000}
rt::set_parameter forceExtractParameterGenomes {false}
rt::set_parameter forceGlobalConstProp {false}
rt::set_parameter forceIncremental {false}
rt::set_parameter forcePackBramAddrReg {false}
rt::set_parameter forcedHierDissolve {false}
rt::set_parameter freeMemoryInElaborate {0}
rt::set_parameter fsmOnespinHint2014Format {true}
rt::set_parameter fsmOptimalRegResize {true}
rt::set_parameter fsmReachableOnlyStates {true}
rt::set_parameter fsmRecodeNewFlow {true}
rt::set_parameter fsmSafeState {none}
rt::set_parameter fullCaseMuxHandleDefault {true}
rt::set_parameter gateClock {false}
rt::set_parameter generateDataflowBusNetlist {false}
rt::set_parameter generateFsmSideFile {false}
rt::set_parameter generateNetlistCNF {false}
rt::set_parameter genericLossyDetectionForAdders {false}
rt::set_parameter genericLsfFlow {false}
rt::set_parameter genomeArea {25000}
rt::set_parameter genomeAreaScaleFactor {0.000000}
rt::set_parameter genomeAreaVariation {1.400000}
rt::set_parameter genomeBasedLogicConnection {true}
rt::set_parameter genomeInPartition {false}
rt::set_parameter genomeOpt {false}
rt::set_parameter globalNamesAlreadyRead {false}
rt::set_parameter globalNamesAlreadyWritten {false}
rt::set_parameter glogicGenSetError {true}
rt::set_parameter groupFirstLevelHierarchy {1}
rt::set_parameter groupFirstLevelHierarchyMaxInstanceCount {0}
rt::set_parameter groupFirstLevelHierarchyRegisterMaxInstanceCount {256}
rt::set_parameter handleFatalRtdReadWrite {false}
rt::set_parameter handleVariableByteWidth {true}
rt::set_parameter hdlAdvisor {true}
rt::set_parameter heuristicMarkBitSelected {false}
rt::set_parameter heuristicMarkUnbalanced {false}
rt::set_parameter hypersource_dollarroot_debug_messaging_threshold {0}
rt::set_parameter ignoreChecksumAttribPrint {}
rt::set_parameter ignoreDontTouchInPropagation {false}
rt::set_parameter ignoreFanoutCountDuringMerging {0}
rt::set_parameter ignoreFsmPowerOn {false}
rt::set_parameter ignoreLogicalOnlyCellsForSynthesis {false}
rt::set_parameter ignorePropagateSettingsInElaborate {false}
rt::set_parameter ignoreSetResetInConstantRegisters {false}
rt::set_parameter inParallelGenomes {true}
rt::set_parameter inProcessGenomesSequentially {false}
rt::set_parameter includeLogicConeThreshold {9}
rt::set_parameter includeUnmergedPaths {true}
rt::set_parameter incrementalBeforeExtractGenomes {false}
rt::set_parameter incrementalChangedModules {}
rt::set_parameter incrementalCompressElabRtd {true}
rt::set_parameter incrementalCongestionOpt {0}
rt::set_parameter incrementalDebug {false}
rt::set_parameter incrementalForcePrintGraphDifferChanges {false}
rt::set_parameter incrementalGraphDifferDebug {false}
rt::set_parameter incrementalNlOpt {true}
rt::set_parameter incrementalOnCache {}
rt::set_parameter incrementalSBlockModule {false}
rt::set_parameter indexOpDebug {0}
rt::set_parameter inequalitiesInLogicPartition {4}
rt::set_parameter inferAllRamVerilog {true}
rt::set_parameter inferAllRamVhdl {true}
rt::set_parameter inferBWWEFor2And3Bytes {true}
rt::set_parameter inferCarrySave {true}
rt::set_parameter inferCarrySaveCandidatesForMultiFanouts {false}
rt::set_parameter inferCarrySaveForBitOperators {false}
rt::set_parameter inferCarrySaveForComparator {false}
rt::set_parameter inferCarrySaveForMultiFanouts {false}
rt::set_parameter inferCarrySaveForMultiplier {false}
rt::set_parameter inferCarrySaveForUnaryMinus {true}
rt::set_parameter inferCarrySaveForWire {false}
rt::set_parameter inferCustomModule {false}
rt::set_parameter inferDecodedMux {false}
rt::set_parameter inferDecodedMuxMinFanouts {1}
rt::set_parameter inferDecodedMuxMinSelSize {2}
rt::set_parameter inferDecodedMuxWithCommonData {true}
rt::set_parameter inferDecoderFirst {false}
rt::set_parameter inferDecoderFromConstantEqOutSizeGr {3}
rt::set_parameter inferDecoderGroups {0}
rt::set_parameter inferDecoderWithEnable {true}
rt::set_parameter inferDspDotProduct {true}
rt::set_parameter inferDspMultNegate {false}
rt::set_parameter inferDynamicSrl {true}
rt::set_parameter inferDynamicSrlBigEndian {false}
rt::set_parameter inferDynamicSrlUb {true}
rt::set_parameter inferEnableForKeepFlops {true}
rt::set_parameter inferEqualityGroupMinSize {2}
rt::set_parameter inferEqualityGroups {false}
rt::set_parameter inferFsm {true}
rt::set_parameter inferGroupsDebug {false}
rt::set_parameter inferMemory {true}
rt::set_parameter inferMemoryAllowConstantIndex {false}
rt::set_parameter inferMemoryAssertForBadRam {false}
rt::set_parameter inferMemoryCheckCoreRam {true}
rt::set_parameter inferMemoryIfTotalBitsMoreThan {16383}
rt::set_parameter inferMemoryIfVariableIndexWritesLessThan {3}
rt::set_parameter inferMergeFromLogic {true}
rt::set_parameter inferPatternDetectForSub {true}
rt::set_parameter inferRamAcrossHier {1}
rt::set_parameter inferRamFromHierRecord {true}
rt::set_parameter inferShifterFromMerge {false}
rt::set_parameter insertAdderForNonCarrySaveEdges {true}
rt::set_parameter instCountDiff {20}
rt::set_parameter instCountDiffRatio {1}
rt::set_parameter installLutInBaseMod {true}
rt::set_parameter ipRuntime {true}
rt::set_parameter isolateRegSlice {true}
rt::set_parameter iterateMerging {true}
rt::set_parameter iterativeNetlistTraversing {true}
rt::set_parameter iterativeTraversingNew {false}
rt::set_parameter keepBselWithpartialNegIndexInPartition {true}
rt::set_parameter keepDFGUnchangedInConstProp {false}
rt::set_parameter keepEnableInRegister {true}
rt::set_parameter keepOneHotEncodedFsm {true}
rt::set_parameter keepRegisterClockEdge {true}
rt::set_parameter largeFanoutForDecloning {1000}
rt::set_parameter lightTimer {1}
rt::set_parameter linterFlow {false}
rt::set_parameter loadPartResult {1}
rt::set_parameter logicDepthAtMuxSelect {4}
rt::set_parameter logicGenDebug {0}
rt::set_parameter logicalOperatorsAreReductions {true}
rt::set_parameter makeCasePartitionsVirtual {false}
rt::set_parameter makeDatapathPartitionsVirtual {false}
rt::set_parameter makeEquivArrayChangeAfterDisconnect {1}
rt::set_parameter makeLogicPartitionsVirtual {false}
rt::set_parameter makeUserModulesVirtual {false}
rt::set_parameter makeVirtual {true}
rt::set_parameter makeVirtualIfInstanceCountLessThan {1}
rt::set_parameter mapInitialBitToLogic {true}
rt::set_parameter mapToScan {false}
rt::set_parameter mapUseTimer {false}
rt::set_parameter markCarrySaveForOnlyTwoInputAdder {false}
rt::set_parameter markCarrySaveInRangeOpt {true}
rt::set_parameter markCarrySaveInUminus {true}
rt::set_parameter markCriticalRegisters {false}
rt::set_parameter markDebugCores {ila;vio}
rt::set_parameter markDebugOutputIlaCore {true}
rt::set_parameter markDebugPinName {probe}
rt::set_parameter markDfgFsm {true}
rt::set_parameter markDisjointAdders {false}
rt::set_parameter markDisjointAdders2InputsOnly {true}
rt::set_parameter markDisjointAddersExpanded {false}
rt::set_parameter markDisjointAddersExpanded2 {false}
rt::set_parameter markDisjointAddersFirst {true}
rt::set_parameter markDisjointAddersLast {false}
rt::set_parameter markDisjointAddersPathLimit {10000}
rt::set_parameter markDisjointAddersPrev {false}
rt::set_parameter markDisjointDatapath {false}
rt::set_parameter markSiblingModulesUnchangedInDFG {false}
rt::set_parameter markSignedDataPath {true}
rt::set_parameter maxBddVarCount {100}
rt::set_parameter maxInputIncreaseToMerge {0}
rt::set_parameter maxIterationsInAreaOpt {4}
rt::set_parameter maxLoopAnalysisPathDepth {200}
rt::set_parameter maxNodeAreaSize {10000}
rt::set_parameter maxPartitionInputCount {50}
rt::set_parameter maxPathDepth {10}
rt::set_parameter maxPrintGetPinsCount {5000}
rt::set_parameter maxRegLevel {100000}
rt::set_parameter maxRegisterInGenome {2147483647}
rt::set_parameter maxReordering {10}
rt::set_parameter maxVariableIndexWrites {16}
rt::set_parameter max_call_depth {1000}
rt::set_parameter max_loop_limit {65536}
rt::set_parameter mem_init {}
rt::set_parameter mergeAcrossBlocks {1}
rt::set_parameter mergeAllInLoopBodies {true}
rt::set_parameter mergeAsyncInverters {true}
rt::set_parameter mergeCarryInOasysConstProp {false}
rt::set_parameter mergeCaseAndLogicPartitions {true}
rt::set_parameter mergeCasePartitions {2}
rt::set_parameter mergeConstantEqualities {1}
rt::set_parameter mergeFanoutLimit {1}
rt::set_parameter mergeIfwithcase {true}
rt::set_parameter mergeLogicIntoConstruct {false}
rt::set_parameter mergeMaxWidth {2147483647}
rt::set_parameter mergeMultiConstructFanout {true}
rt::set_parameter mergeMultiFanoutPartitionsInLoopBodies {true}
rt::set_parameter mergeNumNonConstantInputs {1}
rt::set_parameter mergeOrigEdgeEnableArray {true}
rt::set_parameter mergePartRuntimeFix2019_2 {true}
rt::set_parameter mergePartitionModulesInTimingOpt {true}
rt::set_parameter mergeReconvergentCasePartitions {true}
rt::set_parameter mergeReconvergentDebug {false}
rt::set_parameter mergeReconvergentLogicPartitions {true}
rt::set_parameter mergeReconvergentMaxGraphSize {1000}
rt::set_parameter mergeReconvergentPrintDebug {false}
rt::set_parameter mergeReconvergentRecurLimit {5}
rt::set_parameter mergeReconvergentSkipModules {}
rt::set_parameter mergeReductionOperators {false}
rt::set_parameter mergeSimplify {false}
rt::set_parameter mergeSingleFanoutDatapathPartitions {true}
rt::set_parameter mergeSingleFanoutPartitions {1}
rt::set_parameter mergeSingleFanoutXorPartitions {true}
rt::set_parameter mergeSmallDatapaths {0}
rt::set_parameter mergeThruPrimitives {true}
rt::set_parameter mergeUserInstances {true}
rt::set_parameter merge_flipflops {true}
rt::set_parameter merge_hierarchical_instances {0}
rt::set_parameter merge_latches {true}
rt::set_parameter merge_macros {false}
rt::set_parameter mif_reader {}
rt::set_parameter mimicAndStitchAgressively {false}
rt::set_parameter minDFPartitionAreaCount {100000}
rt::set_parameter minDFPartitionCount {10000}
rt::set_parameter minDetectorWidth {32}
rt::set_parameter minFsmStates {3}
rt::set_parameter minJobsForParallel {5}
rt::set_parameter minModuleWireCount {1000}
rt::set_parameter minNoOfPinsForMuxReductWithSameAsDefault {1000}
rt::set_parameter minReductRatioForMuxReductWithSameAsDefault {75}
rt::set_parameter moveIndexOpToConstruct {false}
rt::set_parameter moveIndexOpToConstructFill {false}
rt::set_parameter moveIndexOpToConstructNormalize {true}
rt::set_parameter moveOpsAcross2x1Mux {true}
rt::set_parameter moveOpsAcrossMux {false}
rt::set_parameter multToLogicThreshold {5}
rt::set_parameter multToLogicThreshold2 {10}
rt::set_parameter multToLogicThresholdMax {30}
rt::set_parameter multToLogicThresholdMin {4}
rt::set_parameter multiDriveConstAssgnCheck {true}
rt::set_parameter multiDriveError {false}
rt::set_parameter multiThread {false}
rt::set_parameter muxDecompCellsPerPartition {1200}
rt::set_parameter muxDecompFlatten {true}
rt::set_parameter muxDecompIgnoreUnate {false}
rt::set_parameter muxDecompInElaborate {false}
rt::set_parameter muxDecompPickTopBddVars {true}
rt::set_parameter muxDecompPortsPerPartition {16}
rt::set_parameter muxDecompRecursive {true}
rt::set_parameter muxDecompRestrictSifting {true}
rt::set_parameter muxDecompRtlHeuristic {3}
rt::set_parameter muxDecompUniqueBddManager {false}
rt::set_parameter muxDecompUniqueSources {false}
rt::set_parameter muxFanoutLimitForFsm {20}
rt::set_parameter muxMapLevel {1}
rt::set_parameter muxSelFanoutLimit {256}
rt::set_parameter muxSelReplicaLimit {10}
rt::set_parameter muxesWithDataEqualsSelect {true}
rt::set_parameter neverUniquifyGenomes {false}
rt::set_parameter newAttributeAPIs {true}
rt::set_parameter newCollapseMerge {true}
rt::set_parameter newConstProp {false}
rt::set_parameter newDefaultState {true}
rt::set_parameter newILAMarkDebug {true}
rt::set_parameter newMuxPartition {true}
rt::set_parameter newSetAttribute {true}
rt::set_parameter newUniquifyInstUserNames {false}
rt::set_parameter nlOptInAreaOpt {0}
rt::set_parameter noExtramRegenInOasys {true}
rt::set_parameter noPass2 {false}
rt::set_parameter noSynRetiming {false}
rt::set_parameter nodeDepthForVersal {true}
rt::set_parameter nonParallelRefRunReason {}
rt::set_parameter nonParallelSBlockGen {false}
rt::set_parameter nonconst_loop_limit {2000}
rt::set_parameter normRamAddress {true}
rt::set_parameter normalizeDatapath {true}
rt::set_parameter numBitMergeForPartition {1000}
rt::set_parameter numPartsForLargePinModule {8}
rt::set_parameter numberOfPinsToEnableOptimizingConstruct {10}
rt::set_parameter numberOfPinsToEnableReduceBigSharedDataMux {12288}
rt::set_parameter oasysConstPropMaxIters {1000}
rt::set_parameter offsetToShift {false}
rt::set_parameter offsetToShiftRecurse {true}
rt::set_parameter onlyOneHotConstructMerge {false}
rt::set_parameter oocMessageList {8-638 8-256}
rt::set_parameter operatorDirectiveCompatibility20_1 {true}
rt::set_parameter optimizeAfterRAMDissolve {false}
rt::set_parameter optimizeAndInferAsymRam {false}
rt::set_parameter optimizeClockGatingCell {false}
rt::set_parameter optimizeComparatorBasedOnRangeAlso {true}
rt::set_parameter optimizeComparators {true}
rt::set_parameter optimizeComparatorsCompatibleConstruct {true}
rt::set_parameter optimizeConditionalBitwiseAssign {false}
rt::set_parameter optimizeConstantComparisonLogic {true}
rt::set_parameter optimizeConstantEq {true}
rt::set_parameter optimizeConstruct {true}
rt::set_parameter optimizeConstructMaxEqSize {64}
rt::set_parameter optimizeDFGTopDownTraversal {true}
rt::set_parameter optimizeLoop {false}
rt::set_parameter optimizeLoopExit {true}
rt::set_parameter optimizeMemoryPorts {true}
rt::set_parameter optimizeMergeUsingAPRangeset {true}
rt::set_parameter optimizeMuxSelect1 {true}
rt::set_parameter optimizeMuxSelect2 {true}
rt::set_parameter optimizeParallelChainsOfComparators {true}
rt::set_parameter optimizeStructuralNetlist {true}
rt::set_parameter optimizeThreeComparisonLogic {true}
rt::set_parameter optimizeVarBitwiseAssign {true}
rt::set_parameter optimizedOneHotFsm {true}
rt::set_parameter parallelCaseMuxHandleDefault {true}
rt::set_parameter parallelChildUpdateCell {false}
rt::set_parameter parallelDFGDumpMode {false}
rt::set_parameter parallelDFGOptMinSize {5000}
rt::set_parameter parallelDFGOptPass1 {true}
rt::set_parameter parallelDebug {false}
rt::set_parameter parallelGenomeList {}
rt::set_parameter parallelStuckFFsRemoval {495}
rt::set_parameter parallelTimingMode {false}
rt::set_parameter parallelTimingModeRound {0}
rt::set_parameter partSeries {7}
rt::set_parameter partitionBitArrayAccess {false}
rt::set_parameter partitionSBlockModule {true}
rt::set_parameter partitionSkipPartialSequentialNet {false}
rt::set_parameter partitionSkipSequentialNet {true}
rt::set_parameter partitionUseGradualReorder {false}
rt::set_parameter phyExtractConsiderPinDensity {true}
rt::set_parameter phyExtractMinAreaFactor {10}
rt::set_parameter phyExtractPinDensityFactor {0.200000}
rt::set_parameter pickSequentialWhenTie {true}
rt::set_parameter pinsWithNoLoadsCollectorThreshold {100}
rt::set_parameter postCommitCPFGlobalPlace {false}
rt::set_parameter postGenControlCSE {false}
rt::set_parameter postPlacementRepartitionGenomes {false}
rt::set_parameter powerBoundaryCellOutsideGenome {true}
rt::set_parameter powerBoundaryCellsInSeparateHierarchy {true}
rt::set_parameter powerDontTouchLSNet {false}
rt::set_parameter powerElabDebug {false}
rt::set_parameter powerLevelShiftingThreshold {0.010000}
rt::set_parameter powerUseDomainInterface {true}
rt::set_parameter preScanHierMismatch {false}
rt::set_parameter preserveConstantAtGenomeBoundary {true}
rt::set_parameter preserveConstantAtModuleBoundary {true}
rt::set_parameter preserveDatapathBoundary {0}
rt::set_parameter preserveDirectiveInMaximalSharing {true}
rt::set_parameter preserveDontOptimizeCarryChains {true}
rt::set_parameter preserveFloatingRTL {false}
rt::set_parameter preserveFloatingRegisters {false}
rt::set_parameter preserveFloatingUserInstances {true}
rt::set_parameter preserveGenomeInstNames {false}
rt::set_parameter preserveInstanceWithDontTouch {true}
rt::set_parameter preserveMacros {false}
rt::set_parameter preserveNetNames {true}
rt::set_parameter preserveUserCarryChains {true}
rt::set_parameter preserveUserInstancesInElaborate {true}
rt::set_parameter preserveUserInstsInConstProp {false}
rt::set_parameter preserveZWires {true}
rt::set_parameter preserve_constant_flipflops {false}
rt::set_parameter preserve_constant_latches {false}
rt::set_parameter preserve_dangling_flipflops {false}
rt::set_parameter preserve_dangling_latches {false}
rt::set_parameter preserve_module_boundaries {none}
rt::set_parameter printFsmEncodingTable {true}
rt::set_parameter printFsmRegisters {false}
rt::set_parameter printGraphStructure {false}
rt::set_parameter printParallelStat {false}
rt::set_parameter procSeepAttr {false}
rt::set_parameter propagateAPRangeSetThroughWireNode {true}
rt::set_parameter propagateConditionalConstants {true}
rt::set_parameter propagateConstantEq {true}
rt::set_parameter propagateConstantsCleanupNetsInElaborate {false}
rt::set_parameter propagateConstantsIgnoreTimingAssertions {true}
rt::set_parameter propagateConstantsInCreateGenome {false}
rt::set_parameter propagateConstantsInElaborate {false}
rt::set_parameter propagateCustomAttribute {true}
rt::set_parameter propagateDontCareInXor {true}
rt::set_parameter propagateModuleLevelAttributes {true}
rt::set_parameter propagateModuleLevelAttributesRecursiveDown {true}
rt::set_parameter propagatePrunedConst {true}
rt::set_parameter propagateRangeSetThroughRegNodes {false}
rt::set_parameter propagateRangeSetThroughWireNode {false}
rt::set_parameter propagateRangeThroughMergeNodes {true}
rt::set_parameter propagateSoftKeepHierRecursiveDown {false}
rt::set_parameter propagateTransparentMux {true}
rt::set_parameter propagate_constants {true}
rt::set_parameter pruneAndRedundancyRemovalLoop {true}
rt::set_parameter pruneBitWidths {true}
rt::set_parameter pruneBitWidthsBeforeInferCSA {false}
rt::set_parameter pruneDeadBits {true}
rt::set_parameter pruneMemoryBitWidths {true}
rt::set_parameter pruneMemoryCheckBoundLogic {true}
rt::set_parameter pruneMemoryDepth {true}
rt::set_parameter pruneMerge {true}
rt::set_parameter pruneNodeIfBitSelLoadOnly {true}
rt::set_parameter prunePowerOfTwoConstModDiv {true}
rt::set_parameter pruneRegister {true}
rt::set_parameter pruneRegisterWithConstantInput {false}
rt::set_parameter pruneSignConversionWire {false}
rt::set_parameter pruneUnreachableReg {true}
rt::set_parameter pushAwThroughLastMerge {false}
rt::set_parameter pushBackRamEnable {false}
rt::set_parameter pushInvertersFromGenomes {false}
rt::set_parameter pushRamOps {true}
rt::set_parameter pushRamsSelectivelyToReinfer {false}
rt::set_parameter putAdderAcrossMuxAttributeOnCarrys {false}
rt::set_parameter qualifyInferredModNameDuringGenExtract {true}
rt::set_parameter ramFromADTThreshold {8192}
rt::set_parameter ramStyle {auto}
rt::set_parameter ramToRegistersVerbose {false}
rt::set_parameter ram_decomp {auto}
rt::set_parameter ram_style {auto}
rt::set_parameter rangeBasedBitwidthOptimization {true}
rt::set_parameter rangeBasedCSA {false}
rt::set_parameter rangeOptLevel {2}
rt::set_parameter rangesToValuesRatioToEnableOptimization {0.300000}
rt::set_parameter reExtractCongestionCriteria {75}
rt::set_parameter readDataflowRtdFlow {false}
rt::set_parameter readGenomeDependencyMap {true}
rt::set_parameter readLatencyFile {false}
rt::set_parameter realWareSupport {false}
rt::set_parameter recodeConstruct {false}
rt::set_parameter recodeFsmCtOutput {true}
rt::set_parameter recodeFsmOutput {true}
rt::set_parameter recodeNextStateFsmOutput {true}
rt::set_parameter reconnectLatch {true}
rt::set_parameter reduceBigSharedDataMuxToCascadeOfSmallMuxes {false}
rt::set_parameter reduceMuxHavingSameValueAsDefault {true}
rt::set_parameter reduceToplevelInverters {false}
rt::set_parameter reduceVariableBitSelect {true}
rt::set_parameter reducedRatioToEnableReduceBigSharedMux {0.750000}
rt::set_parameter registerBankWidthThreshold {12}
rt::set_parameter regroupDuringDecloning {true}
rt::set_parameter remapCellsDuringConstantPropagation {true}
rt::set_parameter remapDontTouchCells {false}
rt::set_parameter remapInstantiatedCells {false}
rt::set_parameter remapInstantiatedFlipFlops {true}
rt::set_parameter remapScanToNoScan {false}
rt::set_parameter remapTimingDriven {false}
rt::set_parameter remapUseComplement {false}
rt::set_parameter removeBBoxKeepHier {false}
rt::set_parameter removeDeadMux {true}
rt::set_parameter removeRedundancy {true}
rt::set_parameter removeRedundantBconcBselTreePattern {true}
rt::set_parameter removeRedundantMerge {true}
rt::set_parameter removeRedundantMux {true}
rt::set_parameter removeRedundantWireBeforePruning {false}
rt::set_parameter removeVModDuringDissolveSmallPartitions {false}
rt::set_parameter removeWireFromAreadOutput {true}
rt::set_parameter remove_flipflops_stuck_at_reset {2}
rt::set_parameter repartitionBeforeTimingOpt {2}
rt::set_parameter repartitionGenomeEffort {0}
rt::set_parameter repartitionGenomeSkipClustering {1}
rt::set_parameter replaceAfterCongestionDrivenRepartition {true}
rt::set_parameter replaceUndriven {0}
rt::set_parameter replaceUndrivenMacroPin {false}
rt::set_parameter replaceX {false}
rt::set_parameter replaceXBy {0}
rt::set_parameter replicateConcatThreshold {10000}
rt::set_parameter reportCommandRuntime {false}
rt::set_parameter reportSynth {true}
rt::set_parameter resizeStartLimitForCompWithConst {512}
rt::set_parameter resolveAdderLoops {true}
rt::set_parameter resolveCombLoops {true}
rt::set_parameter resolveMultiDriversInConstProp {false}
rt::set_parameter resourceShareForVersal {true}
rt::set_parameter restrictedCollapseMerge {true}
rt::set_parameter resynthesisGenomeRatioThresholdForIncrementalSynthesis {0.500000}
rt::set_parameter retainDontTouchFile {false}
rt::set_parameter retainUnconnectedPinsForPrimBBox {true}
rt::set_parameter retimeDfg {false}
rt::set_parameter retimingAdder {true}
rt::set_parameter retimingAdderInside {false}
rt::set_parameter retimingDataPath {2}
rt::set_parameter retimingDataPathMark {true}
rt::set_parameter retimingDebugLevel {0}
rt::set_parameter retimingDivider {true}
rt::set_parameter retimingMultiplier {true}
rt::set_parameter retimingOptLevel {1}
rt::set_parameter retimingSignedDataPath {true}
rt::set_parameter reuseChangeIndependentDissolvedReExtractedGenomes {false}
rt::set_parameter reuseGlobalNames {true}
rt::set_parameter rubikFlow {false}
rt::set_parameter rw_addr_collision {true}
rt::set_parameter sPinDontConnectToLoadLessInv {false}
rt::set_parameter sblockDetailReport {true}
rt::set_parameter searchFullNamePin {false}
rt::set_parameter secureStepNetlistsPrefix {OS_}
rt::set_parameter secureStepNetlistsSuffix {}
rt::set_parameter selectiveInvalidationInSetPowerState {true}
rt::set_parameter setDontTouchGenomes {false}
rt::set_parameter setEdgeToDestPinSize {true}
rt::set_parameter setRepresentativeToHighestBucket {false}
rt::set_parameter setStateEncodingAttributeOnFsmRegister {true}
rt::set_parameter shareBMerges {2}
rt::set_parameter shareCommonBitSelects {false}
rt::set_parameter shareDPInElabAllOrNone {true}
rt::set_parameter shareDPInElabCollapseMerge {2}
rt::set_parameter shareDPInElabDebug {false}
rt::set_parameter shareDPInElabExclude {}
rt::set_parameter shareDPInElabMinOprSize {4}
rt::set_parameter shareDatapath {1}
rt::set_parameter shareDatapathInElaborate {false}
rt::set_parameter shareDatapathUminus {true}
rt::set_parameter shareOperatorWithMinConstSize {16}
rt::set_parameter shiftAddSub {false}
rt::set_parameter signedRangeForConstructNode {false}
rt::set_parameter simpleGateMaxInput {4}
rt::set_parameter simplifyBmergeDrivenByBconcs {true}
rt::set_parameter simplifyCMforDefaultInput {true}
rt::set_parameter simplifyCascadedMerge {1}
rt::set_parameter simplifyDfgForMerging {false}
rt::set_parameter simplifyFlattenUnflattenVector {false}
rt::set_parameter simplifyLoopAsyncReset {true}
rt::set_parameter simplifyRamRead {true}
rt::set_parameter simplifyReset4BlockReg {true}
rt::set_parameter simplifyTiming {true}
rt::set_parameter simplifyXorWithConstant {true}
rt::set_parameter skipExtractLargeRegFile {false}
rt::set_parameter skipExtractModuleWithGraph {true}
rt::set_parameter skipFsmEvaluateForLargeMux {false}
rt::set_parameter skipFsmRegen {false}
rt::set_parameter skipGenomeReviveAndRevertToDefault {false}
rt::set_parameter skipGenomesWithAssertions {false}
rt::set_parameter skipModuleError {false}
rt::set_parameter skipUniquifyFullInstUserNames {true}
rt::set_parameter skipXformsForNetlist {true}
rt::set_parameter spdChainLength {100}
rt::set_parameter spdSimpleGate {false}
rt::set_parameter spdSimplifyUserChain {false}
rt::set_parameter splitFsmConcatFanout {true}
rt::set_parameter splitGenomeCriteria {-200}
rt::set_parameter splitGenomeMinSpan {100.000000}
rt::set_parameter splitGenomesUniquifyAll {false}
rt::set_parameter splitMergeMaxselectsize {1}
rt::set_parameter splitMultiFanoutMerge {false}
rt::set_parameter stackOverFlowLimit {7500}
rt::set_parameter stackOverflowAvailabeMemoryThreshold {5000000}
rt::set_parameter stackOverflowFuncCallThreshold {1000}
rt::set_parameter stackOverflowMinMemoryRequired {150000}
rt::set_parameter strictWireRemoval {true}
rt::set_parameter supportAsymRam {true}
rt::set_parameter supportAsymRamDebug {0}
rt::set_parameter supportBRAMAsyncOutReg {true}
rt::set_parameter supportDontCareInGenerator {false}
rt::set_parameter supportDontCareInLogicGen {false}
rt::set_parameter supportParalWrtRam {false}
rt::set_parameter suppressReport {true}
rt::set_parameter swapLutInputs {false}
rt::set_parameter synFlattenHierarchyValue {2}
rt::set_parameter synPartitionBottomUpLoopLimit {3}
rt::set_parameter synPartitionEnable {false}
rt::set_parameter synPartitionFPGAResourceString {}
rt::set_parameter synPartitionNumPartitions {3}
rt::set_parameter synPartitionStyle {topdown}
rt::set_parameter synRetiming {false}
rt::set_parameter synRetimingSwitch {false}
rt::set_parameter synRetimingTest {0}
rt::set_parameter synVerbose {0}
rt::set_parameter synopsysCompatible {true}
rt::set_parameter synthDebugLog {false}
rt::set_parameter synthesisMarkPartition {false}
rt::set_parameter synthesisMarkPartitionThreshold {50}
rt::set_parameter synthesisMarkTimingCriticalPartition {false}
rt::set_parameter synthesizePrintStats {0}
rt::set_parameter synthesizePrintStatsStart {0}
rt::set_parameter tieBackPositivePolarity {false}
rt::set_parameter tieBackScanOutToScanIn {true}
rt::set_parameter tieScanEnableToZero {true}
rt::set_parameter tieUndrivenWiresToZero {false}
rt::set_parameter toolUPFVersion {2.0}
rt::set_parameter topConeHeight {100000}
rt::set_parameter totalBlackboxInstancesCountForIncrementalSynthesis {0}
rt::set_parameter trackCrossBoundaryConstProp {true}
rt::set_parameter trackEquivArrayChange {false}
rt::set_parameter transferStructuralNetlistToChildren {true}
rt::set_parameter transformBnot {15}
rt::set_parameter transformComparison {true}
rt::set_parameter transformEq {true}
rt::set_parameter transformEqCmp {false}
rt::set_parameter transformFsm {true}
rt::set_parameter transformFsmOutput {true}
rt::set_parameter transformIfElseIfFsm {true}
rt::set_parameter transformInequality {false}
rt::set_parameter transformUminus {3}
rt::set_parameter transformUnaryOrNor {true}
rt::set_parameter transformVariableBitSelectToMux {true}
rt::set_parameter transformVariableBitSelectToMuxThreshold {12}
rt::set_parameter traverseDebug {0}
rt::set_parameter twoPassFsmFlow {true}
rt::set_parameter twoPassGenerateFlow {false}
rt::set_parameter unflattenRamResetLogic {true}
rt::set_parameter uniqueBddManagerForCSE {false}
rt::set_parameter uniquePartitionsInFanoutCount {false}
rt::set_parameter uniquify {false}
rt::set_parameter uniquifyInstUserNames {true}
rt::set_parameter unshareEq {true}
rt::set_parameter unshareOperators {true}
rt::set_parameter unshareOperatorsAggressive {false}
rt::set_parameter unshareOperatorsSelective {false}
rt::set_parameter updateCellArcDelays {true}
rt::set_parameter uramResetPriorityAutoSleepFix {true}
rt::set_parameter useAPSetForRangeOptimization {1024}
rt::set_parameter useGenomesAsChangedStitchPoint {true}
rt::set_parameter useNewStgConstructor {true}
rt::set_parameter useOldAsymRamFlow {false}
rt::set_parameter usePortDefaultValueForUndriven {true}
rt::set_parameter useSetForRangeOptimization {1000}
rt::set_parameter useTopoSortInVN {false}
rt::set_parameter v8SupportBramCascade {true}
rt::set_parameter varNodeOptimizationThreshold {0.500000}
rt::set_parameter var_size_limit {1000000}
rt::set_parameter verboseDot {false}
rt::set_parameter verifyResourceSharing {false}
rt::set_parameter versalAdderReplicateCollapseThreshold {5}
rt::set_parameter warnForLatch {true}
rt::set_parameter warnForStringValue {false}
rt::set_parameter wireInLogicPartition {true}
rt::set_parameter writeCustomModulePattern {false}
rt::set_parameter writeDataflowRtdFlow {false}
rt::set_parameter writeDfgStage {}
rt::set_parameter writeDfgText {0}
rt::set_parameter writeDfgVerilog {0}
rt::set_parameter writeDot {0}
rt::set_parameter writeDotDataRange {false}
rt::set_parameter writeDotPrettyRouteEdges {false}
rt::set_parameter writeGraphsInFile {}
rt::set_parameter writeNetlistModules {false}
rt::set_parameter writeRamInitInDot {true}
rt::set_parameter writeSeparateGlobalNames {true}
rt::set_parameter writeSimulatableAfterElabNetlist {false}
rt::set_parameter writeXdcUsingPinOffset {true}
rt::set_parameter writeXmsg {true}
rt::set_parameter writingXdcForParallelTiming {false}
rt::set_parameter xilinxConnectUndrivenRegWithInit {true}
rt::set_parameter xilinxConnectUndrivenWireWithInit {true}
rt::set_parameter xilinxHierName {true}
rt::set_parameter xilinxRemoveDeadCodeFix {false}
rt::set_parameter xilinxSyncRSFix {true}
# Group: timer
rt::set_parameter abstractGenomes {true}
rt::set_parameter abstractGenomesAssertInputSlew {false}
rt::set_parameter abstractGenomesOnDemand {true}
rt::set_parameter acceptGroupPaths {true}
rt::set_parameter accessEndpointHeapAlways {false}
rt::set_parameter accumulateClockLatencies {false}
rt::set_parameter addArcsToConstraints {true}
rt::set_parameter addBBoxPinAsInternalPin {true}
rt::set_parameter addConstantPinToInvalidQueue {true}
rt::set_parameter addDefaultExternalDelay {false}
rt::set_parameter addEndpointAtProcessEndpoint {true}
rt::set_parameter adjustBufNetDelay {false}
rt::set_parameter adjustGenomeInputNetDelay {false}
rt::set_parameter allowRestrictTimer {true}
rt::set_parameter alwaysPushToInputs {false}
rt::set_parameter breakAtWatchNumber {0}
rt::set_parameter breakLoopMode {1}
rt::set_parameter bufNetDelay {200}
rt::set_parameter bypassPinSlackMap {true}
rt::set_parameter cachedCellDelay {true}
rt::set_parameter capacitance_units_for_reports {ff}
rt::set_parameter cellNeighborhood {4.000000}
rt::set_parameter characterizeGenomesWithEmbededAssertions {false}
rt::set_parameter checkStackOverFlowDepth {true}
rt::set_parameter clockUncertaintyUseCaptureOnly {true}
rt::set_parameter compressExceptions {false}
rt::set_parameter computeClockRequiredAtPartitionBoundary {false}
rt::set_parameter computeClockRequiredTimes {true}
rt::set_parameter computeNetOld {false}
rt::set_parameter constrainDefaultDefaultPath {false}
rt::set_parameter createClockErrorsOnUnknownPort {false}
rt::set_parameter createClockPathGroups {false}
rt::set_parameter createLibertyClocks {true}
rt::set_parameter debugCompressExceptions {0}
rt::set_parameter debugPathGroupIgnores {false}
rt::set_parameter debugTiming {false}
rt::set_parameter debugTimingInformation {false}
rt::set_parameter defaultClockTransition {0.000000}
rt::set_parameter delayBudgetFreezeTimer {true}
rt::set_parameter delayPerMilimeterOverride {0.000000}
rt::set_parameter disableEverestCarry8Arcs {1}
rt::set_parameter dontFunnel {true}
rt::set_parameter dontReleaseObjects {true}
rt::set_parameter echoSDC {false}
rt::set_parameter enableSetMaxDelay {false}
rt::set_parameter estimateBuffering {false}
rt::set_parameter estimateFastestFOLoad {0.500000}
rt::set_parameter estimateFastestLoad {0.500000}
rt::set_parameter estimateRepeater {false}
rt::set_parameter estimateSizing {false}
rt::set_parameter estimateSizingTypicalDeltaCap {true}
rt::set_parameter extraLocalNetDelay {0.000000}
rt::set_parameter extraLocalNetDelayOffset {0}
rt::set_parameter falsePathInterClockDomains {false}
rt::set_parameter falsePathZeroWeightPathGroups {false}
rt::set_parameter fixGeneratedClock {3}
rt::set_parameter forceNewGenomeTiming {false}
rt::set_parameter genomeNeighborhood {0.000000}
rt::set_parameter genomesAllowWLM {true}
rt::set_parameter getClockCreatesClock {false}
rt::set_parameter getTimingPinNew {true}
rt::set_parameter ignoreConstantsForTiming {false}
rt::set_parameter ignoreGenomeMultiDrivers {true}
rt::set_parameter ignoreIsSized {false}
rt::set_parameter ignoreMultiDrivers {true}
rt::set_parameter ignoreNetDelay {false}
rt::set_parameter ignoreSlew {false}
rt::set_parameter implementFlopSizing {true}
rt::set_parameter inputBddCacheThreshold {6}
rt::set_parameter mvCornerDebugging {false}
rt::set_parameter newLoopHandling {true}
rt::set_parameter newNEighBorhoodAreaEstimate {true}
rt::set_parameter noRecalculateInvalidSlack {false}
rt::set_parameter pessimisticMinWireLength {false}
rt::set_parameter pessimisticWireLength {0.000000}
rt::set_parameter powerCapacitancePerUnitArea {0.001000}
rt::set_parameter powerCheckGenomeCachedValue {false}
rt::set_parameter powerDefaultClockPeriod {1.250000}
rt::set_parameter powerDefaultStaticProbability {0.200000}
rt::set_parameter powerDefaultSwitchingFactor {0.200000}
rt::set_parameter powerMacroDynamicMultiplier {1.000000}
rt::set_parameter printExtrasAtWatch {0}
rt::set_parameter printSlackNextToArrival {false}
rt::set_parameter printTraceInfo {false}
rt::set_parameter propagateAcrossInputAssertions {false}
rt::set_parameter propagateIdealClockSlew {true}
rt::set_parameter propagateNetlistConstantsForTiming {false}
rt::set_parameter pushClocksToInputsToo {false}
rt::set_parameter pushConstraintsInsideForSDCFile {false}
rt::set_parameter repeaterAllowInverter {true}
rt::set_parameter reportClockNetwork {0}
rt::set_parameter reportLoop {true}
rt::set_parameter reportStyle {soce}
rt::set_parameter reportTricellsLoop {false}
rt::set_parameter resetCellDelay {false}
rt::set_parameter resistance_units_for_reports {ohm}
rt::set_parameter scaleGenomeDelay {100}
rt::set_parameter showGenomeHierarchy {false}
rt::set_parameter slewDegradationAcrossNetFactor {0.000000}
rt::set_parameter stackOverFlowLimitDepth {4000}
rt::set_parameter strictPortDirections {true}
rt::set_parameter tAbstractError {0}
rt::set_parameter tIdealClock {true}
rt::set_parameter tTopGenomeTiming {false}
rt::set_parameter timeAsynchronousArcs {false}
rt::set_parameter timeBidirSelf {false}
rt::set_parameter timeElmore {false}
rt::set_parameter timeExceptionsfromMasterClock {false}
rt::set_parameter timeTreeStateArcs {false}
rt::set_parameter time_units_for_reports {ps}
rt::set_parameter time_units_for_sdc {ns}
rt::set_parameter timingBindEstimatedCell {false}
rt::set_parameter timingCheckUnateness {false}
rt::set_parameter timingEnableMVCheck {false}
rt::set_parameter timingFixExternalReqTime {true}
rt::set_parameter timingLoopLevel {0}
rt::set_parameter timingMaxFromFanout {2}
rt::set_parameter timingPessimisticDelay {false}
rt::set_parameter timingReportMergeArcs {true}
rt::set_parameter timingReportShowEstimateBuffering {true}
rt::set_parameter timingReportShowEstimateSizingAndBuffering {false}
rt::set_parameter timingReportShowVirtualHierarchy {true}
rt::set_parameter timingReportUseDetail {true}
rt::set_parameter topDesignAllowWLM {true}
rt::set_parameter useAgressiveArcMerge {true}
rt::set_parameter useClockSlewFix {true}
rt::set_parameter useGenomeCachedTiming {true}
rt::set_parameter useHierarchicalConstantsForTiming {false}
rt::set_parameter usePhysicalDelays {true}
rt::set_parameter usePinIdInEndPointSort {true}
rt::set_parameter watchTimingPin {false}
rt::set_parameter wlmCapRate {0.000000}
rt::set_parameter wlmResRate {0.000000}
rt::set_parameter writeGenomeTiming {true}
rt::set_parameter write_sdc_split_line {false}
# Group: util
rt::set_parameter dupCreateCells {true}
rt::set_parameter dupDebugStraps {0}
rt::set_parameter dupHeader {true}
rt::set_parameter dupVersion {0}
# Group: utils
rt::set_parameter printMaxStackDepth {50}
rt::set_parameter propagateConstantXZ {true}
rt::set_parameter rtlTraceLimit {100}
rt::set_parameter shortenConstantWithRepetitions {100}
# Group: verify
rt::set_parameter verifyAllowBlackBoxWithFeedthrough {false}
rt::set_parameter verifyCommentKeyword {#}
rt::set_parameter verifyConstraintAssertBBInput {set_assert -net %s "%s"}
rt::set_parameter verifyConstraintForceBBOutput {set_const -pin %s "%s"}
rt::set_parameter verifyConstraintForceInput {set_const -port %s "%s"}
rt::set_parameter verifyConstraintIgnoreBBInput {set_ignore -pin "%s"}
rt::set_parameter verifyConstraintIgnoreOutput {set_ignore -port "%s"}
rt::set_parameter verifyConstraintTieBBOutputPins {set_equiv -pin "%s" "%s"}
rt::set_parameter verifyConstraintTieInputPins {set_equiv -port "%s" "%s"}
rt::set_parameter verifyConstraintTieInvBBOutputPins {set_inv_equiv -pin "%s" "%s"}
rt::set_parameter verifyConstraintTieInvInputPins {set_inv_equiv -port "%s" "%s"}
rt::set_parameter verifyGoldenKeyword {\G}
rt::set_parameter verifyMinHierCellCount {4}
rt::set_parameter verifyPinNameFormat {@/%s/%s}
rt::set_parameter verifyPrefixTopModuleNameToPinNameDelim {/}
rt::set_parameter verifyRevisedKeyword {\R}
rt::set_parameter verifyUserbbList { }
# Group: write
rt::set_parameter alignToParen {false}
rt::set_parameter attrVlog2001 {false}
rt::set_parameter inferredModuleNamesForChecksum {false}
rt::set_parameter skipHiddenAttribute {true}
rt::set_parameter unconnectedPrefix {uc_}
rt::set_parameter verilogLineLength {80}
rt::set_parameter writeBlackboxInterface {true}
rt::set_parameter writeClockGateControlPortConstraint {true}
rt::set_parameter writeEquivInfoForConnectedPins {true}
rt::set_parameter writeFunnel {false}
rt::set_parameter writeHeader {true}
rt::set_parameter writeInferredModules {true}
rt::set_parameter writeLineLength {80}
rt::set_parameter writeModulesBottomUp {true}
rt::set_parameter writeModulesDepthFirst {true}
rt::set_parameter writeMultiBitConstants {false}
rt::set_parameter writeParameters {true}
rt::set_parameter writePortEquivalencies {}
rt::set_parameter writePragmas {true}
rt::set_parameter writeRtlVerilog {false}
rt::set_parameter writeStructuralNetlist {true}
rt::set_parameter writeTraces {1}
rt::set_parameter writeUpfFlatNames {true}
rt::set_parameter writeVerilogCheckNameSpace {true}
rt::set_parameter writeVirtualModules {false}
rt::set_parameter writeVlog2001Directive {true}
rt::set_parameter write_boundary_properties {false}
rt::set_parameter write_implicit_wire_decls {false}
# Unregistered parameters
set rt::flattenHierarchy {4}
set rt::quickRtlOpt {false}
set rt::useAbc {1}
set rt::nl_opt_flow {2}
set rt::postMapTimingOpt {0}
set rt::runtime_optimized {0}
set rt::combineLutsInTechmap {0}
set rt::skipReinfer {false}
set rt::new_mux_part {false}
set rt::doXdc {1}
set rt::afterMapTimingCallRunTimeFix {false}
set rt::timingOptRunTimeFix {false}
