# 
# Synthesis run script generated by Vivado
# 

namespace eval rt {
    variable rc
}
set rt::rc [catch {
  uplevel #0 {
    set ::env(BUILTIN_SYNTH) true
    source $::env(HRT_TCL_PATH)/rtSynthPrep.tcl
    rt::HARTNDb_startJobStats
    set rt::cmdEcho 0
    rt::set_parameter writeXmsg true
    rt::set_parameter enableParallelHelperSpawn true
    set ::env(RT_TMP) "./.Xil/Vivado-2786040-685a421e500f/realtime/tmp"
    if { [ info exists ::env(RT_TMP) ] } {
      file mkdir $::env(RT_TMP)
    }

    rt::delete_design

    rt::set_parameter datapathDensePacking false
    set rt::partid xc7a100tcsg324-1
     file delete -force synth_hints.os

    set rt::multiChipSynthesisFlow false
    set rt::enableVHDL2008 1
    source $::env(SYNTH_COMMON)/common.tcl
    set rt::defaultWorkLibName xil_defaultlib
    rt::set_parameter defaultVhdlWorkLib xil_defaultlib

    rt::set_parameter loadVhdl2008Libs false
    rt::set_parameter loadVhdl2019Libs false
    rt::set_parameter deferParseUntilElab true
    rt::set_parameter sortHdlCommandLine true
    # Skipping read_* RTL commands because this is post-elab optimize flow
    set rt::useElabCache true
    if {$rt::useElabCache == false} {
      rt::read_verilog -sv {
      /eda/processor_ci/rtl/T02x.sv
      /eda/processor-ci-controller/modules/uart.sv
      /eda/processor_ci/internal/ahblite_to_wishbone.sv
      /eda/processor_ci/internal/axi4_to_wishbone.sv
      /eda/processor_ci/internal/axi4lite_to_wishbone.sv
      /eda/processor-ci-controller/rtl/fifo.sv
      /eda/processor-ci-controller/rtl/reset.sv
      /eda/processor-ci-controller/rtl/clk_divider.sv
      /eda/processor-ci-controller/rtl/memory.sv
      /eda/processor-ci-controller/rtl/interpreter.sv
      /eda/processor-ci-controller/rtl/controller.sv
      /eda/processor-ci-controller/rtl/timer.sv
      /eda/processor_ci/internal/fpga_top.sv
    }
      rt::read_verilog {
      /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
      /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
    }
      rt::read_vhdl -vhdl2008 -lib xil_defaultlib {
      /var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/PKG_RiscV_Klessydra_thread_parameters.vhd
      /var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/PKG_RiscV_Klessydra.vhd
      /var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-CSR_Unit.vhd
      /var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Debug_Unit.vhd
      /var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Processing_Pipeline.vhd
      /var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/RTL-Program_Counter_unit.vhd
      /var/jenkins_home/workspace/T02x/T02x/klessydra-t0-2th/STR-Klessydra_top.vhd
    }
      rt::filesetChecksum
    }
    rt::set_parameter usePostFindUniquification true
    set rt::SDCFileList ./.Xil/Vivado-2786040-685a421e500f/realtime/fpga_top_synth.xdc
    rt::sdcChecksum
    set rt::top fpga_top
    rt::set_parameter enableIncremental true
    rt::set_parameter markDebugPreservationLevel "enable"
    set rt::reportTiming false
    rt::set_parameter elaborateOnly false
    rt::set_parameter elaborateRtl false
    rt::set_parameter eliminateRedundantBitOperator true
    rt::set_parameter dataflowBusHighlighting false
    rt::set_parameter generateDataflowBusNetlist false
    rt::set_parameter dataFlowViewInElab false
    rt::set_parameter busViewFixBrokenConnections false
    rt::set_parameter elaborateRtlOnlyFlow false
    rt::set_parameter writeBlackboxInterface true
    rt::set_parameter ramStyle auto
    rt::set_parameter merge_flipflops true
# MODE: 
    rt::set_parameter webTalkPath {./.Xil/Vivado-2786040-685a421e500f/wt}
    rt::set_parameter synthDebugLog false
    rt::set_parameter printModuleName false
    rt::set_parameter enableSplitFlowPath "./.Xil/Vivado-2786040-685a421e500f/"
    set ok_to_delete_rt_tmp true 
    if { [rt::get_parameter parallelDebug] } { 
       set ok_to_delete_rt_tmp false 
    } 
    if {$rt::useElabCache == false} {
        set oldMIITMVal [rt::get_parameter maxInputIncreaseToMerge]; rt::set_parameter maxInputIncreaseToMerge 1000
        set oldCDPCRL [rt::get_parameter createDfgPartConstrRecurLimit]; rt::set_parameter createDfgPartConstrRecurLimit 1
        $rt::db readXRFFile
      rt::run_synthesis -module $rt::top
        rt::set_parameter maxInputIncreaseToMerge $oldMIITMVal
        rt::set_parameter createDfgPartConstrRecurLimit $oldCDPCRL
    }

    set rt::flowresult [ source $::env(SYNTH_COMMON)/flow.tcl ]
    rt::HARTNDb_stopJobStats
    rt::HARTNDb_reportJobStats "Synthesis Optimization Runtime"
    rt::HARTNDb_stopSystemStats
    if { $rt::flowresult == 1 } { return -code error }


  set hsKey [rt::get_parameter helper_shm_key] 
  if { $hsKey != "" && [info exists ::env(BUILTIN_SYNTH)] && [rt::get_parameter enableParallelHelperSpawn] } { 
     $rt::db killSynthHelper $hsKey
  } 
  rt::set_parameter helper_shm_key "" 
    if { [ info exists ::env(RT_TMP) ] } {
      if { [info exists ok_to_delete_rt_tmp] && $ok_to_delete_rt_tmp } { 
        file delete -force $::env(RT_TMP)
      }
    }

    source $::env(HRT_TCL_PATH)/rtSynthCleanup.tcl
  } ; #end uplevel
} rt::result]

if { $rt::rc } {
  $rt::db resetHdlParse
  set hsKey [rt::get_parameter helper_shm_key] 
  if { $hsKey != "" && [info exists ::env(BUILTIN_SYNTH)] && [rt::get_parameter enableParallelHelperSpawn] } { 
     $rt::db killSynthHelper $hsKey
  } 
  source $::env(HRT_TCL_PATH)/rtSynthCleanup.tcl
  return -code "error" $rt::result
}
