Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date         : Fri Apr 17 22:19:37 2026
| Host         : 685a421e500f running 64-bit unknown
| Command      : report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
| Design       : fpga_top
| Device       : xc7a100t
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |   237 |
|    Minimum number of control sets                        |   237 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |   181 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |   237 |
| >= 0 to < 4        |     5 |
| >= 4 to < 6        |     7 |
| >= 6 to < 8        |     9 |
| >= 8 to < 10       |     9 |
| >= 10 to < 12      |     4 |
| >= 12 to < 14      |     3 |
| >= 14 to < 16      |     0 |
| >= 16              |   200 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |             558 |          212 |
| No           | No                    | Yes                    |              72 |           44 |
| No           | Yes                   | No                     |             152 |           62 |
| Yes          | No                    | No                     |             515 |          213 |
| Yes          | No                    | Yes                    |            4895 |         2184 |
| Yes          | Yes                   | No                     |             443 |          126 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------------+----------------+--------------+
|                                      Clock Signal                                      |                                         Enable Signal                                         |                                 Set/Reset Signal                                 | Slice Load Count | Bel Load Count | Bels / Slice |
+----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------------+----------------+--------------+
|  ptop/u_klessydra_t0_3th_core/CSR/CSR_updating_logic[2].trap_hndlr_reg0                |                                                                                               | ptop/u_klessydra_t0_3th_core/CSR/trap_hndlr                                      |                1 |              1 |         1.00 |
|  ptop/u_klessydra_t0_3th_core/CSR/CSR_updating_logic[1].trap_hndlr_reg0                |                                                                                               | ptop/u_klessydra_t0_3th_core/CSR/CSR_updating_logic[1].trap_hndlr_reg[1]_i_2_n_1 |                1 |              1 |         1.00 |
|  ptop/u_klessydra_t0_3th_core/CSR/CSR_updating_logic[0].trap_hndlr_reg0                |                                                                                               | ptop/u_klessydra_t0_3th_core/CSR/CSR_updating_logic[0].trap_hndlr_reg[0]_i_2_n_1 |                1 |              1 |         1.00 |
|  clk_IBUF_BUFG                                                                         |                                                                                               |                                                                                  |                1 |              1 |         1.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_1                                              | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_1_n_1                                 |                1 |              1 |         1.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_2__0_n_1                                    | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_1__0_n_1                       |                1 |              4 |         4.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Uart/i_uart_rx/next_bit                                                     | ptop/u_Controller/Uart/i_uart_rx/bit_counter[3]_i_1_n_1                          |                1 |              4 |         4.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Uart/i_uart_tx/E[0]                                                         |                                                                                  |                1 |              4 |         4.00 |
|  clk_o_BUFG                                                                            | ResetBootSystem/counter                                                                       | ResetBootSystem/counter[3]_i_1__0_n_1                                            |                2 |              4 |         2.00 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/pass_BEQ_ID0                                                | ptop/u_klessydra_t0_3th_core/Pipe/decoded_instruction_IE[48]_i_1_n_1             |                1 |              4 |         4.00 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/pass_BEQ_ID0                                                | ptop/u_klessydra_t0_3th_core/Pipe/decoded_instruction_IE[33]_i_1_n_1             |                2 |              5 |         2.50 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/return_state                                                    | ResetBootSystem/rst_o_reg_0                                                      |                3 |              5 |         1.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/CSR/i___26_n_1                                                   | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |                5 |              6 |         1.20 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/pass_BEQ_ID0                                                | ptop/u_klessydra_t0_3th_core/Pipe/decoded_instruction_IE[28]_i_1_n_1             |                3 |              6 |         2.00 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/served_except_condition9_out                                | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |                2 |              6 |         3.00 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/CSR/i___41_n_1                                                   | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |                3 |              6 |         2.00 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/CSR/i___28_n_1                                                   | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |                5 |              6 |         1.20 |
|  clk_o_BUFG                                                                            |                                                                                               |                                                                                  |                3 |              6 |         2.00 |
|  clk_core                                                                              |                                                                                               |                                                                                  |                5 |              6 |         1.20 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Uart/i_uart_tx/data_to_send[6]_i_1_n_1                                      | ResetBootSystem/rst_o_reg_0                                                      |                2 |              7 |         3.50 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/harc_WB[1]_i_1_n_1                                          |                                                                                  |                4 |              7 |         1.75 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/accumulator[7]_i_1_n_1                                          | ResetBootSystem/rst_o_reg_0                                                      |                4 |              8 |         2.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/counter                                                         | ResetBootSystem/rst_o_reg_0                                                      |                2 |              8 |         4.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Uart/i_uart_rx/uart_rx_data[7]_i_1_n_1                                      | ResetBootSystem/rst_o_reg_0                                                      |                2 |              8 |         4.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Uart/i_uart_rx/E[0]                                                         | ResetBootSystem/rst_o_reg_0                                                      |                2 |              8 |         4.00 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/pass_BEQ_ID0                                                | ptop/u_klessydra_t0_3th_core/Pipe/decoded_instruction_IE[20]_i_1_n_1             |                2 |              8 |         4.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Uart/tx_fifo/FSM_sequential_state_write_reg[2][0]                           | ResetBootSystem/rst_o_reg_0                                                      |                2 |              8 |         4.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Uart/uart_tx_en                                                             | ResetBootSystem/rst_o_reg_0                                                      |                1 |              8 |         8.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Uart/i_uart_rx/recieved_data0                                               | ptop/u_Controller/Uart/i_uart_rx/recieved_data[7]_i_1_n_1                        |                2 |              8 |         4.00 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/pass_BEQ_ID0                                                | ptop/u_klessydra_t0_3th_core/Pipe/decoded_instruction_IE[8]_i_1_n_1              |                4 |              9 |         2.25 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_1                                              | ResetBootSystem/SR[0]                                                            |                3 |             10 |         3.33 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Uart/i_uart_rx/cycle_counter0                                               | ptop/u_Controller/Uart/i_uart_rx/cycle_counter[9]_i_1_n_1                        |                4 |             10 |         2.50 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Uart/tx_fifo/read_ptr[2]_i_1_n_1                                            | ResetBootSystem/rst_o_reg_0                                                      |                3 |             11 |         3.67 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Uart/rx_fifo/read_ptr[2]_i_1__0_n_1                                         | ResetBootSystem/rst_o_reg_0                                                      |                4 |             11 |         2.75 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Uart/tx_fifo/memory_reg_0_7_0_5_i_1__0_n_1                                  |                                                                                  |                2 |             12 |         6.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/address[31]_i_1_n_1                                             |                                                                                  |                9 |             12 |         1.33 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Uart/rx_fifo/memory_reg_0_7_0_5_i_1_n_1                                     |                                                                                  |                2 |             12 |         6.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/memory_page_number[23]_i_2_n_1                                  | ptop/u_Controller/Interpreter/memory_page_number[23]_i_1_n_1                     |                7 |             24 |         3.43 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/num_of_cycles_to_pulse[23]_i_1_n_1                              |                                                                                  |                9 |             24 |         2.67 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/num_of_pages                                                    | ResetBootSystem/rst_o_reg_0                                                      |                4 |             24 |         6.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/timeout                                                         | ResetBootSystem/rst_o_reg_0                                                      |               10 |             24 |         2.40 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/accumulator0                                                    | ResetBootSystem/rst_o_reg_0                                                      |                5 |             24 |         4.80 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/pc_update_logic[0].served_mret_condition_reg[0]_0           | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               16 |             26 |         1.62 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[2].csr_instr_done_replicated_reg[2]_6    | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               19 |             26 |         1.37 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[1].csr_instr_done_replicated_reg[1]_5    | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               17 |             26 |         1.53 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/CSR/CSR_updating_logic[1].MCAUSE_internal[1][30]_i_1_n_1         | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               11 |             28 |         2.55 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/CSR/CSR_updating_logic[0].MCAUSE_internal[0][30]_i_1_n_1         | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               13 |             28 |         2.15 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/CSR/CSR_updating_logic[2].MCAUSE_internal[2][30]_i_1_n_1         | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             28 |         2.33 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/flush_cycle_count[2][30]_i_1_n_1                            | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |                8 |             31 |         3.88 |
|  ptop/u_klessydra_t0_3th_core/Pipe/fsm_IE_comb.PC_offset_wires_reg[0][31]_i_2_n_1_BUFG |                                                                                               |                                                                                  |               18 |             31 |         1.72 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/flush_cycle_count[1][30]_i_1_n_1                            | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |                9 |             31 |         3.44 |
|  ptop/u_klessydra_t0_3th_core/Pipe/fsm_IE_comb.PC_offset_wires_reg[1][31]_i_2_n_1      |                                                                                               |                                                                                  |               11 |             31 |         2.82 |
|  ptop/u_klessydra_t0_3th_core/Pipe/fsm_IE_comb.PC_offset_wires_reg[2][31]_i_2_n_1      |                                                                                               |                                                                                  |               13 |             31 |         2.38 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/flush_cycle_count[0][30]_i_1_n_1                            | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |                8 |             31 |         3.88 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][4][31]_i_1_n_1                              | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               16 |             32 |         2.00 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][5]_115                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               15 |             32 |         2.13 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][23]_101                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               15 |             32 |         2.13 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][22]_100                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               11 |             32 |         2.91 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][0][31]_i_1_n_1                              | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               15 |             32 |         2.13 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][2][31]_i_1_n_1                              | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               13 |             32 |         2.46 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][1][31]_i_1_n_1                              | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               16 |             32 |         2.00 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][0]_78                                       | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               13 |             32 |         2.46 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][30]_140                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][3][31]_i_1_n_1                              | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               19 |             32 |         1.68 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][8]_118                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             32 |         2.29 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][7]_117                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               18 |             32 |         1.78 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][5][31]_i_1_n_1                              | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               17 |             32 |         1.88 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][6]_116                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               17 |             32 |         1.88 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][31]_141                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               15 |             32 |         2.13 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][13]_91                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               13 |             32 |         2.46 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][10]_88                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][6]_84                                       | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               19 |             32 |         1.68 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][5]_83                                       | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               16 |             32 |         2.00 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][4]_82                                       | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               19 |             32 |         1.68 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][8]_86                                       | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             32 |         2.29 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][7]_85                                       | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               16 |             32 |         2.00 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][26]_104                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][9]_87                                       | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               16 |             32 |         2.00 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][17]_95                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             32 |         2.29 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][21]_99                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             32 |         2.29 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][19]_97                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             32 |         2.29 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][11]_89                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               15 |             32 |         2.13 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][12]_90                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][18]_96                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               10 |             32 |         3.20 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][15]_93                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][14]_92                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][20]_98                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               10 |             32 |         3.20 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][16]_94                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             32 |         2.29 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/write_data[31]_i_1_n_1                                          |                                                                                  |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[2].PCER_reg[2][2][0]                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[2].PCER_reg[2][9]_0[0]                   | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               11 |             32 |         2.91 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[2].PCER_reg[2][8][0]                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               10 |             32 |         3.20 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/ClkDivider/pulse_counter[0]_i_1_n_1                                         | ResetBootSystem/rst_o_reg_0                                                      |                8 |             32 |         4.00 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][11]_121                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][10]_120                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               16 |             32 |         2.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/timeout_counter                                                 | ResetBootSystem/rst_o_reg_0                                                      |                5 |             32 |         6.40 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][9]_119                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             32 |         2.29 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/communication_buffer[31]_i_1_n_1                                | ResetBootSystem/rst_o_reg_0                                                      |                7 |             32 |         4.57 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/core_reset_reg_0[0]                                         |                                                                                  |               11 |             32 |         2.91 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/communication_write_data[31]_i_1_n_1                            |                                                                                  |                9 |             32 |         3.56 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/read_buffer[31]_i_1_n_1                                         | ResetBootSystem/rst_o_reg_0                                                      |               17 |             32 |         1.88 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/end_position[31]_i_1_n_1                                        | ResetBootSystem/rst_o_reg_0                                                      |                9 |             32 |         3.56 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Uart/rx_fifo/E[0]                                                           | ResetBootSystem/rst_o_reg_0                                                      |                5 |             32 |         6.40 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][16]_126                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Uart/tx_fifo/E[0]                                                           | ResetBootSystem/rst_o_reg_0                                                      |                6 |             32 |         5.33 |
|  u_klessydra_t0_3th_core/Prg_Ctr/taken_branch_pc_lat_internal[0]_4                     |                                                                                               |                                                                                  |                9 |             32 |         3.56 |
|  u_klessydra_t0_3th_core/Prg_Ctr/taken_branch_pc_lat_internal[1]_2                     |                                                                                               |                                                                                  |                9 |             32 |         3.56 |
|  u_klessydra_t0_3th_core/Prg_Ctr/taken_branch_pc_lat_internal[2]_3                     |                                                                                               |                                                                                  |                9 |             32 |         3.56 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][29]_139                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             32 |         2.29 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/csr_wdata_i[31]_i_1_n_1                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               21 |             32 |         1.52 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][21]_131                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               17 |             32 |         1.88 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][25]_135                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             32 |         2.29 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][26]_136                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               13 |             32 |         2.46 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][24]_134                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               15 |             32 |         2.13 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][23]_133                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               17 |             32 |         1.88 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][22]_132                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][28]_138                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             32 |         2.29 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][27]_137                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               16 |             32 |         2.00 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/WB_RD[31]_i_1_n_1                                           | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               21 |             32 |         1.52 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[0].PCER_reg[0][2][0]                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               11 |             32 |         2.91 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[2].csr_instr_done_replicated_reg[2]_5[0] | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[2].PCER_reg[2][7]_0[0]                   | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               10 |             32 |         3.20 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[2].csr_instr_done_replicated_reg[2]_4[0] | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[2].csr_instr_done_replicated_reg[2]_3[0] | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[2].csr_instr_done_replicated_reg[2]_2[0] | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/csr_addr_i_reg[3]_1[0]                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               10 |             32 |         3.20 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/core_reset_reg[0]                                           |                                                                                  |               15 |             32 |         2.13 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/core_reset_reg_1[0]                                         |                                                                                  |               14 |             32 |         2.29 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[2].csr_instr_done_replicated_reg[2]_1[0] | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][1]_111                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               18 |             32 |         1.78 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][0]_110                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               15 |             32 |         2.13 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][13]_123                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               13 |             32 |         2.46 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][2]_112                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             32 |         2.29 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][3]_113                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               18 |             32 |         1.78 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][4]_114                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               16 |             32 |         2.00 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/csr_addr_i_reg[0]_0[0]                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               19 |             32 |         1.68 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/csr_addr_i_reg[3]_0[0]                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               13 |             32 |         2.46 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/csr_addr_i_reg[3]_2[0]                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             32 |         2.29 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][24]_102                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               15 |             32 |         2.13 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][20][31]_i_1_n_1                             | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               17 |             32 |         1.88 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][2]_80                                       | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[0].PCER_reg[0][7]_0[0]                   | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               10 |             32 |         3.20 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/CSR/i___29_n_1                                                   | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               25 |             32 |         1.28 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][23][31]_i_1_n_1                             | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               15 |             32 |         2.13 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][24][31]_i_1_n_1                             | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               17 |             32 |         1.88 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][25][31]_i_1_n_1                             | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             32 |         2.29 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][26][31]_i_1_n_1                             | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               13 |             32 |         2.46 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][27][31]_i_1_n_1                             | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               15 |             32 |         2.13 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][28][31]_i_1_n_1                             | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             32 |         2.29 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][12]_122                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               13 |             32 |         2.46 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][9][31]_i_1_n_1                              | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               13 |             32 |         2.46 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][25]_103                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][28]_106                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               13 |             32 |         2.46 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][27]_105                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             32 |         2.29 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][29]_107                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][31]_109                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             32 |         2.29 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][30]_108                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               10 |             32 |         3.20 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][6][31]_i_1_n_1                              | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               18 |             32 |         1.78 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][8][31]_i_1_n_1                              | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               15 |             32 |         2.13 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][7][31]_i_1_n_1                              | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               20 |             32 |         1.60 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][10][31]_i_1_n_1                             | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               13 |             32 |         2.46 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/CSR/i___32_n_1                                                   | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               23 |             32 |         1.39 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][11][31]_i_1_n_1                             | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               15 |             32 |         2.13 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][17][31]_i_1_n_1                             | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               16 |             32 |         2.00 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][12][31]_i_1_n_1                             | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             32 |         2.29 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][13][31]_i_1_n_1                             | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               16 |             32 |         2.00 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][15][31]_i_1_n_1                             | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               15 |             32 |         2.13 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][14][31]_i_1_n_1                             | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               17 |             32 |         1.88 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][18][31]_i_1_n_1                             | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               13 |             32 |         2.46 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][16][31]_i_1_n_1                             | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               18 |             32 |         1.78 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][19][31]_i_1_n_1                             | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               13 |             32 |         2.46 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][21][31]_i_1_n_1                             | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               16 |             32 |         2.00 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/pc_update_logic[0].served_except_condition_reg[0][0]        | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               22 |             32 |         1.45 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][29][31]_i_1_n_1                             | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             32 |         2.29 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/pc_update_logic[1].wfi_condition_pending_reg[1][0]          | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][14]_124                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             32 |         2.29 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/pc_except_value_reg[0]0                                     |                                                                                  |               13 |             32 |         2.46 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/pc_except_value_reg[2]0                                     |                                                                                  |               13 |             32 |         2.46 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/pc_update_logic[0].wfi_condition_pending_reg[0][0]          | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/E[0]                                                        | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             32 |         2.29 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][31][31]_i_1_n_1                             | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               17 |             32 |         1.88 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/csr_addr_i_reg[3]_4[0]                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               20 |             32 |         1.60 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/csr_addr_i_reg[2]_1[0]                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               11 |             32 |         2.91 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/csr_addr_i_reg[2]_0[0]                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             32 |         2.29 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/pc_update_logic[2].served_except_condition_reg[2][0]        | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               20 |             32 |         1.60 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/pc_except_value_reg[1]0                                     |                                                                                  |               10 |             32 |         3.20 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[0].PCER_reg[0][8][0]                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/csr_addr_i_reg[0]_2[0]                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               13 |             32 |         2.46 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[0].PCER_reg[0][9]_0[0]                   | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               10 |             32 |         3.20 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/csr_addr_i_reg[2]_2[0]                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               13 |             32 |         2.46 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/csr_addr_i_reg[0]_3[0]                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               16 |             32 |         2.00 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[1].csr_instr_done_replicated_reg[1]_1[0] | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[1].csr_instr_done_replicated_reg[1]_4[0] | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               11 |             32 |         2.91 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[1].csr_instr_done_replicated_reg[1]_3[0] | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               11 |             32 |         2.91 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[1].csr_instr_done_replicated_reg[1]_2[0] | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               10 |             32 |         3.20 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[1].PCER_reg[1][7]_0[0]                   | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][1]_79                                       | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             32 |         2.29 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[1][3]_81                                       | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               18 |             32 |         1.78 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/pc_update_logic[1].served_except_condition_reg[1][0]        | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               17 |             32 |         1.88 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][22][31]_i_1_n_1                             | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               18 |             32 |         1.78 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][15]_125                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               17 |             32 |         1.88 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][17]_127                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             32 |         2.29 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][18]_128                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][19]_129                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[0][20]_130                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               15 |             32 |         2.13 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/CSR/i___30_n_1                                                   | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               15 |             32 |         2.13 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/CSR/i___40_n_1                                                   | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               19 |             32 |         1.68 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[1].PCER_reg[1][9]_0[0]                   | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               10 |             32 |         3.20 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[1].csr_instr_done_replicated_reg[1]_6[0] | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               10 |             32 |         3.20 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[1].PCER_reg[1][2][0]                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               13 |             32 |         2.46 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/CSR_updating_logic[1].PCER_reg[1][8][0]                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             32 |         2.67 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/regfile_wire[2][30][31]_i_1_n_1                             | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               13 |             32 |         2.46 |
|  n_0_10128_BUFG                                                                        |                                                                                               |                                                                                  |               14 |             34 |         2.43 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/instr_word_IE_wire                                          | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               11 |             34 |         3.09 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/csr_addr_i[11]_i_1_n_1                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               12 |             34 |         2.83 |
|  clk_core                                                                              | instr_grant                                                                                   | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               14 |             36 |         2.57 |
|  instr_grant                                                                           |                                                                                               |                                                                                  |               16 |             37 |         2.31 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/num_of_positions[23]_i_1_n_1                                    |                                                                                  |               16 |             55 |         3.44 |
|  clk_core                                                                              |                                                                                               | ptop/u_Controller/Interpreter/memory_mux_selector_reg_0                          |               23 |             64 |         2.78 |
|  clk_core                                                                              |                                                                                               | ptop/u_Controller/Interpreter/core_reset_reg_0                                   |               44 |             72 |         1.64 |
|  clk_o_BUFG                                                                            |                                                                                               | ResetBootSystem/rst_o_reg_0                                                      |               36 |             85 |         2.36 |
|  u_klessydra_t0_3th_core/Prg_Ctr/mepc_interrupt_pc_internal_reg[1]_0                   |                                                                                               |                                                                                  |               33 |             95 |         2.88 |
|  u_klessydra_t0_3th_coren_0_8735_BUFG                                                  |                                                                                               |                                                                                  |               38 |             95 |         2.50 |
|  u_klessydra_t0_3th_core/Prg_Ctr/mepc_interrupt_pc_internal_reg[2]_1                   |                                                                                               |                                                                                  |               33 |             95 |         2.88 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/memory_mux_selector_reg_10                                      |                                                                                  |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/memory_mux_selector_reg_14                                      |                                                                                  |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/memory_mux_selector_reg_15                                      |                                                                                  |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/memory_mux_selector_reg_16                                      |                                                                                  |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/memory_mux_selector_reg_12                                      |                                                                                  |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/memory_mux_selector_reg_11                                      |                                                                                  |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/memory_mux_selector_reg_7                                       |                                                                                  |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/address_reg[11]_0                                               |                                                                                  |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/memory_mux_selector_reg_9                                       |                                                                                  |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/memory_mux_selector_reg_8                                       |                                                                                  |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/address_reg[10]_1                                               |                                                                                  |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                            | ptop/u_Controller/Interpreter/memory_mux_selector_reg_13                                      |                                                                                  |               32 |            128 |         4.00 |
|  clk_core                                                                              | ptop/u_klessydra_t0_3th_core/Pipe/pass_BEQ_ID0                                                |                                                                                  |               77 |            157 |         2.04 |
+----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------------+----------------+--------------+


