Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 | Date : Sun Aug 2 22:41:21 2026 | Host : 685a421e500f running 64-bit unknown | Command : report_drc -file digilent_arty_a7_drc.rpt | Design : fpga_top | Device : xc7a100tcsg324-1 | Speed File : -1 | Design State : Fully Routed --------------------------------------------------------------------------------------------------------------------------------------------- Report DRC Table of Contents ----------------- 1. REPORT SUMMARY 2. REPORT DETAILS 1. REPORT SUMMARY ----------------- Netlist: fpga_top Floorplan: design_1 Design limits: Ruledeck: default Max violations: Violations found: 46 +-----------+------------------+-----------------------------------------------------+------------+ | Rule | Severity | Description | Violations | +-----------+------------------+-----------------------------------------------------+------------+ | LUTLP-1 | Critical Warning | Combinatorial Loop Alert | 1 | | CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | | CHECK-3 | Warning | Report rule limit reached | 1 | | DPIP-1 | Warning | Input pipelining | 8 | | DPOP-1 | Warning | PREG Output pipelining | 3 | | DPOP-2 | Warning | MREG Output pipelining | 11 | | PDRC-153 | Warning | Gated clock check | 1 | | REQP-1839 | Warning | RAMB36 async control check | 20 | +-----------+------------------+-----------------------------------------------------+------------+ 2. REPORT DETAILS ----------------- LUTLP-1#1 Critical Warning Combinatorial Loop Alert 2 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is ptop/u_klessydra_t1_3th_core/Pipe/DECODE/data_mem_we. Please evaluate your design. The cells in the loop are: ptop/u_klessydra_t1_3th_core/Pipe/DECODE/state_LS_i_10 ptop/u_klessydra_t1_3th_core/Pipe/DECODE/state_LS_i_6. Related violations: CFGBVS-1#1 Warning Missing CFGBVS and CONFIG_VOLTAGE Design Properties Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. Related violations: CHECK-3#1 Warning Report rule limit reached REQP-1839 rule limit reached: 20 violations have been found. Related violations: DPIP-1#1 Warning Input pipelining DSP ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].dsp_mul_a_reg[0] input ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].dsp_mul_a_reg[0]/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-1#2 Warning Input pipelining DSP ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].dsp_mul_a_reg[0] input ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].dsp_mul_a_reg[0]/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-1#3 Warning Input pipelining DSP ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].dsp_mul_d_reg[0] input ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].dsp_mul_d_reg[0]/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-1#4 Warning Input pipelining DSP ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].dsp_mul_d_reg[0] input ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].dsp_mul_d_reg[0]/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-1#5 Warning Input pipelining DSP ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/L input ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/L/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-1#6 Warning Input pipelining DSP ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/L input ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/L/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-1#7 Warning Input pipelining DSP ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/L__0 input ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/L__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-1#8 Warning Input pipelining DSP ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/L__0 input ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/L__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPOP-1#1 Warning PREG Output pipelining DSP ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/partial_mul_b_wire0 output ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/partial_mul_b_wire0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-1#2 Warning PREG Output pipelining DSP ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/partial_mul_c_wire0 output ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/partial_mul_c_wire0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-1#3 Warning PREG Output pipelining DSP ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/partial_mul_d_wire0 output ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/partial_mul_d_wire0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. Related violations: DPOP-2#1 Warning MREG Output pipelining DSP ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].dsp_mul_a_reg[0] multiplier stage ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].dsp_mul_a_reg[0]/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. Related violations: DPOP-2#2 Warning MREG Output pipelining DSP ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].dsp_mul_d_reg[0] multiplier stage ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].dsp_mul_d_reg[0]/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. Related violations: DPOP-2#3 Warning MREG Output pipelining DSP ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/L multiplier stage ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/L/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. Related violations: DPOP-2#4 Warning MREG Output pipelining DSP ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/L__0 multiplier stage ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/L__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. Related violations: DPOP-2#5 Warning MREG Output pipelining DSP ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/partial_mul_b_wire0 multiplier stage ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/partial_mul_b_wire0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. Related violations: DPOP-2#6 Warning MREG Output pipelining DSP ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/partial_mul_c_wire0 multiplier stage ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/partial_mul_c_wire0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. Related violations: DPOP-2#7 Warning MREG Output pipelining DSP ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/partial_mul_d_wire0 multiplier stage ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/partial_mul_d_wire0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. Related violations: DPOP-2#8 Warning MREG Output pipelining DSP ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/partial_mulh_a_wire0 multiplier stage ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/partial_mulh_a_wire0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. Related violations: DPOP-2#9 Warning MREG Output pipelining DSP ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/partial_mulh_b_wire0 multiplier stage ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/partial_mulh_b_wire0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. Related violations: DPOP-2#10 Warning MREG Output pipelining DSP ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/partial_mulh_c_wire0 multiplier stage ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/partial_mulh_c_wire0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. Related violations: DPOP-2#11 Warning MREG Output pipelining DSP ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/partial_mulh_d_wire0 multiplier stage ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/partial_mulh_d_wire0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. Related violations: PDRC-153#1 Warning Gated clock check Net ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/dsp_add_8_0_wire[0][0]1 is a gated clock net sourced by a combinational pin ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].carry_16_wire_reg[0][0]_i_2/O, cell ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].carry_16_wire_reg[0][0]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: REQP-1839#1 Warning RAMB36 async control check The RAMB36E1 ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0 has an input control pin ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0/ADDRARDADDR[14] (net: ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0_0[11]) which is driven by a register (ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/DSP_replicated[0].accum_stage_3_en_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#2 Warning RAMB36 async control check The RAMB36E1 ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0 has an input control pin ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0/ADDRARDADDR[14] (net: ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0_0[11]) which is driven by a register (ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/DSP_replicated[0].adder_stage_3_en_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#3 Warning RAMB36 async control check The RAMB36E1 ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0 has an input control pin ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0/ADDRARDADDR[14] (net: ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0_0[11]) which is driven by a register (ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/DSP_replicated[0].cmp_stage_2_en_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#4 Warning RAMB36 async control check The RAMB36E1 ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0 has an input control pin ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0/ADDRARDADDR[14] (net: ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0_0[11]) which is driven by a register (ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/DSP_replicated[0].mul_stage_3_en_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#5 Warning RAMB36 async control check The RAMB36E1 ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0 has an input control pin ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0/ADDRARDADDR[14] (net: ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0_0[11]) which is driven by a register (ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/DSP_replicated[0].recover_state_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#6 Warning RAMB36 async control check The RAMB36E1 ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0 has an input control pin ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0/ADDRARDADDR[14] (net: ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0_0[11]) which is driven by a register (ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/DSP_replicated[0].state_DSP_reg[0][1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#7 Warning RAMB36 async control check The RAMB36E1 ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0 has an input control pin ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0/ADDRARDADDR[14] (net: ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0_0[11]) which is driven by a register (ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SPM_replicated[0].ls_data_gnt_internal_reg[0][0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#8 Warning RAMB36 async control check The RAMB36E1 ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0 has an input control pin ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0/ADDRARDADDR[14] (net: ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0_0[11]) which is driven by a register (ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SPM_replicated[0].ls_data_gnt_internal_reg[0][1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#9 Warning RAMB36 async control check The RAMB36E1 ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0 has an input control pin ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0/ADDRARDADDR[14] (net: ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0_0[11]) which is driven by a register (ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SPM_replicated[0].ls_data_gnt_internal_reg[0][2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#10 Warning RAMB36 async control check The RAMB36E1 ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0 has an input control pin ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0/ADDRARDADDR[14] (net: ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0_0[11]) which is driven by a register (ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SPM_replicated[0].ls_data_gnt_internal_reg[0][3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#11 Warning RAMB36 async control check The RAMB36E1 ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0 has an input control pin ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0/ADDRARDADDR[14] (net: ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0_0[11]) which is driven by a register (ptop/u_klessydra_t1_3th_core/Pipe/DECODE/ls_instr_req_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#12 Warning RAMB36 async control check The RAMB36E1 ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0 has an input control pin ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0/ADDRARDADDR[14] (net: ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0_0[11]) which is driven by a register (ptop/u_klessydra_t1_3th_core/Pipe/LSU/amo_store_lat_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#13 Warning RAMB36 async control check The RAMB36E1 ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0 has an input control pin ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0/ADDRARDADDR[14] (net: ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0_0[11]) which is driven by a register (ptop/u_klessydra_t1_3th_core/Pipe/LSU/sc_word_count_reg[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#14 Warning RAMB36 async control check The RAMB36E1 ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0 has an input control pin ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0/ADDRARDADDR[14] (net: ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0_0[11]) which is driven by a register (ptop/u_klessydra_t1_3th_core/Pipe/LSU/sc_word_count_reg[16]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#15 Warning RAMB36 async control check The RAMB36E1 ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0 has an input control pin ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0/ADDRARDADDR[14] (net: ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0_0[11]) which is driven by a register (ptop/u_klessydra_t1_3th_core/Pipe/LSU/sc_word_count_reg[22]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#16 Warning RAMB36 async control check The RAMB36E1 ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0 has an input control pin ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0/ADDRARDADDR[14] (net: ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0_0[11]) which is driven by a register (ptop/u_klessydra_t1_3th_core/Pipe/LSU/sc_word_count_reg[27]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#17 Warning RAMB36 async control check The RAMB36E1 ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0 has an input control pin ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0/ADDRARDADDR[14] (net: ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0_0[11]) which is driven by a register (ptop/u_klessydra_t1_3th_core/Pipe/LSU/sc_word_count_reg[29]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#18 Warning RAMB36 async control check The RAMB36E1 ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0 has an input control pin ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0/ADDRARDADDR[14] (net: ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0_0[11]) which is driven by a register (ptop/u_klessydra_t1_3th_core/Pipe/LSU/sc_word_count_reg[30]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#19 Warning RAMB36 async control check The RAMB36E1 ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0 has an input control pin ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0/ADDRARDADDR[14] (net: ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0_0[11]) which is driven by a register (ptop/u_klessydra_t1_3th_core/Pipe/LSU/sc_word_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#20 Warning RAMB36 async control check The RAMB36E1 ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0 has an input control pin ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0/ADDRARDADDR[14] (net: ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SC/spm_replicas[0].spm_banks[0].mem_reg[0][0]_0_0[11]) which is driven by a register (ptop/u_klessydra_t1_3th_core/Pipe/LSU/state_LS_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: