Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date         : Sat Sep  5 22:40:15 2026
| Host         : 685a421e500f running 64-bit unknown
| Command      : report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
| Design       : fpga_top
| Device       : xc7a100t
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |   140 |
|    Minimum number of control sets                        |   140 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |   187 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |   140 |
| >= 0 to < 4        |     3 |
| >= 4 to < 6        |    16 |
| >= 6 to < 8        |    13 |
| >= 8 to < 10       |    10 |
| >= 10 to < 12      |     5 |
| >= 12 to < 14      |     3 |
| >= 14 to < 16      |     7 |
| >= 16              |    83 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |              20 |           12 |
| No           | No                    | Yes                    |             175 |          111 |
| No           | Yes                   | No                     |             149 |           58 |
| Yes          | No                    | No                     |            1356 |          612 |
| Yes          | No                    | Yes                    |             734 |          402 |
| Yes          | Yes                   | No                     |             659 |          205 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+
|                                 Clock Signal                                 |                                                              Enable Signal                                                             |                                                       Set/Reset Signal                                                       | Slice Load Count | Bel Load Count | Bels / Slice |
+------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+
|  clk_IBUF_BUFG                                                               |                                                                                                                                        |                                                                                                                              |                1 |              1 |         1.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                                                                                       | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_1_n_0                                                                             |                1 |              1 |         1.00 |
|  ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/dsp_add_8_0_wire[0][0]1 |                                                                                                                                        |                                                                                                                              |                2 |              2 |         1.00 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/DECODE/core_reset_reg_4[0]                                                                           |                                                                                                                              |                2 |              4 |         2.00 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].dsp_add_8_0_reg[0][0]0                                            | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].MSB_stage_2[0][0][3]_i_1_n_0                            |                2 |              4 |         2.00 |
|  clk_core                                                                    | ptop/u_Controller/Interpreter/decoded_instruction_IE0                                                                                  | ptop/u_klessydra_t1_3th_core/Pipe/DECODE/decoded_instruction_IE[40]_i_1_n_0                                                  |                2 |              4 |         2.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_2__0_n_0                                                                             | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_1__0_n_0                                                                   |                1 |              4 |         4.00 |
|  clk_o_BUFG                                                                  | ResetBootSystem/counter                                                                                                                | ResetBootSystem/counter[3]_i_1__0_n_0                                                                                        |                2 |              4 |         2.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Uart/i_uart_tx/E[0]                                                                                                  |                                                                                                                              |                1 |              4 |         4.00 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].dsp_in_shifter_operand_lat_reg[0]0                                |                                                                                                                              |                2 |              4 |         2.00 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/DSP_replicated[0].dsp_sc_data_read_mask_reg[0]0                                    |                                                                                                                              |                1 |              4 |         4.00 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/E[0]                                                                               | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |                2 |              4 |         2.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Uart/i_uart_rx/next_bit                                                                                              | ptop/u_Controller/Uart/i_uart_rx/bit_counter[3]_i_1_n_0                                                                      |                1 |              4 |         4.00 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/pc_update_logic[0].served_mret_condition_reg[0]_0[0]                                         | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |                3 |              5 |         1.67 |
|  clk_core                                                                    | ptop/u_Controller/Interpreter/core_reset_reg_1[0]                                                                                      | ptop/u_klessydra_t1_3th_core/Pipe/FETCH/core_reset_reg                                                                       |                1 |              5 |         5.00 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/DECODE/dsp_instr_req_reg[0]_0                                                                        | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |                4 |              5 |         1.25 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/pc_update_logic[2].served_except_condition_reg[2]_0[0]                                       | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |                3 |              5 |         1.67 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/pc_update_logic[1].served_except_condition_reg[1]_0[0]                                       | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |                2 |              5 |         2.50 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/return_state                                                                                             | ResetBootSystem/rst_o_reg_0                                                                                                  |                3 |              5 |         1.67 |
|  clk_o_BUFG                                                                  |                                                                                                                                        |                                                                                                                              |                3 |              6 |         2.00 |
|  clk_core                                                                    | ptop/u_Controller/Interpreter/core_reset_reg_2                                                                                         | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/div_count[5]_i_1_n_0                                                               |                1 |              6 |         6.00 |
|  clk_core                                                                    | ptop/u_Controller/Interpreter/decoded_instruction_IE0                                                                                  | ptop/u_klessydra_t1_3th_core/Pipe/DECODE/decoded_instruction_IE[28]_i_1_n_0                                                  |                3 |              6 |         2.00 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/served_except_condition9_out                                                                 | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |                3 |              6 |         2.00 |
|  clk_core                                                                    | ptop/u_Controller/Interpreter/E[0]                                                                                                     |                                                                                                                              |                2 |              7 |         3.50 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Uart/i_uart_tx/data_to_send[6]_i_1_n_0                                                                               | ResetBootSystem/rst_o_reg_0                                                                                                  |                2 |              7 |         3.50 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/CSR_updating_logic[2].csr_instr_done_replicated_reg[2]                                       | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |                5 |              7 |         1.40 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/DECODE/state_LS_reg[0]                                                                               | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |                2 |              7 |         3.50 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/CSR_updating_logic[0].csr_instr_done_replicated_reg[0]                                       | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |                5 |              7 |         1.40 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/CSR_updating_logic[1].csr_instr_done_replicated_reg[1]                                       | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |                4 |              7 |         1.75 |
|  clk_core                                                                    | ptop/u_Controller/Interpreter/decoded_instruction_IE0                                                                                  | ptop/u_klessydra_t1_3th_core/Pipe/DECODE/decoded_instruction_IE[6]_i_1_n_0                                                   |                4 |              7 |         1.75 |
|  clk_core                                                                    | ptop/u_Controller/Interpreter/decoded_instruction_IE0                                                                                  | ptop/u_klessydra_t1_3th_core/Pipe/FETCH/core_reset_reg_3                                                                     |                2 |              7 |         3.50 |
|  clk_core                                                                    | ptop/u_Controller/Interpreter/core_reset_reg_1[0]                                                                                      |                                                                                                                              |                4 |              7 |         1.75 |
|  clk_core                                                                    | ptop/u_Controller/Interpreter/decoded_instruction_IE0                                                                                  | ptop/u_klessydra_t1_3th_core/Pipe/FETCH/core_reset_reg_2                                                                     |                6 |              8 |         1.33 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].MSB_stage_3_reg[0][1]0                                            |                                                                                                                              |                3 |              8 |         2.67 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Uart/tx_fifo/FSM_sequential_state_write_reg[2][0]                                                                    | ResetBootSystem/rst_o_reg_0                                                                                                  |                1 |              8 |         8.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Uart/uart_tx_en                                                                                                      | ResetBootSystem/rst_o_reg_0                                                                                                  |                1 |              8 |         8.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/accumulator[7]_i_1_n_0                                                                                   | ResetBootSystem/rst_o_reg_0                                                                                                  |                5 |              8 |         1.60 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Uart/i_uart_rx/E[0]                                                                                                  | ResetBootSystem/rst_o_reg_0                                                                                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Uart/i_uart_rx/recieved_data0                                                                                        | ptop/u_Controller/Uart/i_uart_rx/recieved_data[7]_i_1_n_0                                                                    |                2 |              8 |         4.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/counter                                                                                                  | ResetBootSystem/rst_o_reg_0                                                                                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Uart/i_uart_rx/uart_rx_data[7]_i_1_n_0                                                                               | ResetBootSystem/rst_o_reg_0                                                                                                  |                2 |              8 |         4.00 |
|  clk_core                                                                    | ptop/u_Controller/Interpreter/instr_word_IE0                                                                                           |                                                                                                                              |                7 |              9 |         1.29 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                                                                                       | ResetBootSystem/SR[0]                                                                                                        |                3 |             10 |         3.33 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Uart/i_uart_rx/cycle_counter0                                                                                        | ptop/u_Controller/Uart/i_uart_rx/cycle_counter[9]_i_1_n_0                                                                    |                3 |             10 |         3.33 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Uart/rx_fifo/read_ptr[2]_i_1__0_n_0                                                                                  | ResetBootSystem/rst_o_reg_0                                                                                                  |                3 |             11 |         3.67 |
|  clk_core                                                                    |                                                                                                                                        |                                                                                                                              |                6 |             11 |         1.83 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Uart/tx_fifo/read_ptr[2]_i_1_n_0                                                                                     | ResetBootSystem/rst_o_reg_0                                                                                                  |                3 |             11 |         3.67 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/address[31]_i_1_n_0                                                                                      |                                                                                                                              |                4 |             12 |         3.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Uart/rx_fifo/memory_reg_0_7_0_5_i_1_n_0                                                                              |                                                                                                                              |                2 |             12 |         6.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Uart/tx_fifo/memory_reg_0_7_0_5_i_1__0_n_0                                                                           |                                                                                                                              |                2 |             12 |         6.00 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/DSP_replicated[0].RD_Data_IE_lat_reg[0]0                                           |                                                                                                                              |                3 |             14 |         4.67 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/DSP_replicated[0].MVSIZE_READ_MASK_reg[0]0                                         |                                                                                                                              |                9 |             15 |         1.67 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/pc_update_logic[1].served_except_condition_reg[1]_1[0]                                       | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |                4 |             15 |         3.75 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/pc_update_logic[2].served_except_condition_reg[2]_1[0]                                       | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |                8 |             15 |         1.88 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/DSP_replicated[0].MVSIZE_READ_reg[0]0                                              |                                                                                                                              |                5 |             15 |         3.00 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/DSP_replicated[0].MVSIZE_WRITE_reg[0]0                                             |                                                                                                                              |                7 |             15 |         2.14 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/pc_update_logic[0].served_mret_condition_reg[0]_1[0]                                         | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |                6 |             15 |         2.50 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/ACCUM_STG/ACCUM_replicated[0].ACCUM_SIMD_1.accum_partial_results_stg_1_reg[0]0[15] |                                                                                                                              |                4 |             16 |         4.00 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].dsp_add_8_0_reg[0][0]0                                            | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].dsp_in_adder_operands_lat[0][0][15]_i_1_n_0             |                5 |             16 |         3.20 |
|  clk_core                                                                    | ptop/u_Controller/Interpreter/decoded_instruction_IE0                                                                                  |                                                                                                                              |               10 |             16 |         1.60 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/ACCUM_STG/ACCUM_replicated[0].ACCUM_SIMD_1.accum_partial_results_stg_1_reg[0]0[30] |                                                                                                                              |                5 |             16 |         3.20 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/FETCH/core_reset_reg_1[0]                                                                            |                                                                                                                              |                5 |             17 |         3.40 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/num_of_cycles_to_pulse[23]_i_1_n_0                                                                       |                                                                                                                              |                9 |             24 |         2.67 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/memory_page_number[23]_i_2_n_0                                                                           | ptop/u_Controller/Interpreter/memory_page_number[23]_i_1_n_0                                                                 |                7 |             24 |         3.43 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/timeout                                                                                                  | ResetBootSystem/rst_o_reg_0                                                                                                  |                7 |             24 |         3.43 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/num_of_pages                                                                                             | ResetBootSystem/rst_o_reg_0                                                                                                  |                6 |             24 |         4.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/accumulator0                                                                                             | ResetBootSystem/rst_o_reg_0                                                                                                  |                4 |             24 |         6.00 |
|  clk_core                                                                    | ptop/u_Controller/Interpreter/instr_word_IE0                                                                                           | ptop/u_klessydra_t1_3th_core/Pipe/DECODE/instr_word_IE[31]_i_1_n_0                                                           |               10 |             25 |         2.50 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].dsp_out_cmp_results_reg[0]0                                       |                                                                                                                              |               19 |             31 |         1.63 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/DECODE/harc_EXEC_reg[0]_rep__0_1                                                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |               24 |             32 |         1.33 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/RS2_Data_IE_int0                                                                             |                                                                                                                              |               12 |             32 |         2.67 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/DSP_replicated[0].RS2_Data_IE_lat_reg[0]0                                          |                                                                                                                              |                8 |             32 |         4.00 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/DECODE/state_IE_reg[1][0]                                                                            | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |               19 |             32 |         1.68 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/DECODE/E[0]                                                                                          |                                                                                                                              |               10 |             32 |         3.20 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/DECODE/core_reset_reg_3[0]                                                                           |                                                                                                                              |               19 |             32 |         1.68 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/DECODE/core_reset_reg_2[0]                                                                           |                                                                                                                              |               10 |             32 |         3.20 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/DECODE/harc_EXEC_reg[1]_rep__0_1                                                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |               17 |             32 |         1.88 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/DECODE/harc_EXEC_reg[0]_rep__1_0                                                                     | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |               15 |             32 |         2.13 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/RS1_Data_IE0                                                                       |                                                                                                                              |                9 |             32 |         3.56 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SPM_replicated[0].dsp_sc_data_read_reg[0][1]0                                      |                                                                                                                              |               27 |             32 |         1.19 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].dsp_out_adder_results_reg[0]0                                     |                                                                                                                              |                8 |             32 |         4.00 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/DECODE/pc_IE_reg[28]_0[0]                                                                            | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |               26 |             32 |         1.23 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/DECODE/pc_IE_reg[28]_1[0]                                                                            | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |               25 |             32 |         1.28 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/DECODE/pc_IE_reg[28]_2[0]                                                                            | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |               24 |             32 |         1.33 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/pc_update_logic[0].served_mret_condition_reg[0][0]                                           | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |               18 |             32 |         1.78 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].dsp_out_shifter_results_reg[0]0                                   |                                                                                                                              |               21 |             32 |         1.52 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/DSP_replicated[0].dsp_sc_data_write_int_reg[0]0                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/DSP_replicated[0].dsp_sc_data_write_int[0][31]_i_1_n_0                   |               17 |             32 |         1.88 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/E[0]                                                                                         | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |               17 |             32 |         1.88 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].dsp_out_mul_results_reg[0]0                                       |                                                                                                                              |               13 |             32 |         2.46 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].dsp_int_shifter_operand[0][31]_i_1_n_0                            |                                                                                                                              |               16 |             32 |         2.00 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/state_IE_reg[0]_3[0]                                                                         | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |               24 |             32 |         1.33 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/state_IE_reg[0]_1[0]                                                                         | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |               23 |             32 |         1.39 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SPM_replicated[0].dsp_sc_data_read_reg[0][0]0                                      |                                                                                                                              |               23 |             32 |         1.39 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/communication_buffer[31]_i_1_n_0                                                                         | ResetBootSystem/rst_o_reg_0                                                                                                  |                8 |             32 |         4.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/timeout_counter                                                                                          | ResetBootSystem/rst_o_reg_0                                                                                                  |                7 |             32 |         4.57 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/communication_write_data[31]_i_1_n_0                                                                     |                                                                                                                              |               14 |             32 |         2.29 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/write_data[31]_i_1_n_0                                                                                   |                                                                                                                              |               14 |             32 |         2.29 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/read_buffer[31]_i_1_n_0                                                                                  | ResetBootSystem/rst_o_reg_0                                                                                                  |               19 |             32 |         1.68 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Uart/tx_fifo/E[0]                                                                                                    | ResetBootSystem/rst_o_reg_0                                                                                                  |                6 |             32 |         5.33 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/end_position[31]_i_1_n_0                                                                                 | ResetBootSystem/rst_o_reg_0                                                                                                  |                7 |             32 |         4.57 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Uart/rx_fifo/E[0]                                                                                                    | ResetBootSystem/rst_o_reg_0                                                                                                  |                5 |             32 |         6.40 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/ClkDivider/pulse_counter[0]_i_1_n_0                                                                                  | ResetBootSystem/rst_o_reg_0                                                                                                  |                8 |             32 |         4.00 |
|  clk_core                                                                    | ptop/u_Controller/Interpreter/core_reset_reg_2                                                                                         | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/ACCUM_STG/ACCUM_replicated[0].ACCUM_SIMD_1.dsp_out_accum_results_reg[0]0 |                8 |             32 |         4.00 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.SCI/SPM_replicated[0].ls_sc_data_read_replicated_reg[0]0                               |                                                                                                                              |               29 |             32 |         1.10 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/LSU/core_reset_reg[0]                                                                                |                                                                                                                              |               11 |             32 |         2.91 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/FETCH/RD_EN                                                                                          | ptop/u_klessydra_t1_3th_core/Pipe/FETCH/SR[0]                                                                                |               10 |             32 |         3.20 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/pc_update_logic[2].served_except_condition_reg[2]_2[0]                                       | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |               12 |             32 |         2.67 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/pc_update_logic[2].served_mret_condition_reg[2]_0[0]                                         | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |               16 |             32 |         2.00 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/pc_update_logic[0].served_mret_condition_reg[0]_2[0]                                         | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |               18 |             32 |         1.78 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/pc_update_logic[1].served_mret_condition_reg[1]_0[0]                                         | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |               16 |             32 |         2.00 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/pc_update_logic[1].served_except_condition_reg[1]_2[0]                                       | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |               16 |             32 |         2.00 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/DECODE/MUL_WB0                                                                                       | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/MUL_WB[31]_i_1_n_0                                                                 |                8 |             32 |         4.00 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/FETCH/RD_EN                                                                                          | ptop/u_klessydra_t1_3th_core/Pipe/FETCH/instr_rvalid_state_reg_0[0]                                                          |               13 |             32 |         2.46 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/LSU/core_reset_reg_1[0]                                                                              |                                                                                                                              |               14 |             32 |         2.29 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/LSU/core_reset_reg_0[0]                                                                              |                                                                                                                              |               11 |             32 |         2.91 |
|  clk_core                                                                    | ptop/instr_grant                                                                                                                       |                                                                                                                              |               15 |             35 |         2.33 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/ACCL_generate.DSP/FU_replicated[0].dsp_add_8_0_reg[0][0]0                                            |                                                                                                                              |               20 |             39 |         1.95 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/DECODE/pc_IE[31]_i_1_n_0                                                                             | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |               16 |             41 |         2.56 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/DECODE/DSP_replicated[0].FUNCT_SELECT_MASK_reg[0]0                                                   |                                                                                                                              |               24 |             44 |         1.83 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/RF/RF_LUTRAM.data_addr_internal_IE_reg[31]_0[0]                                                      | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |               17 |             46 |         2.71 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/num_of_positions[23]_i_1_n_0                                                                             |                                                                                                                              |               13 |             55 |         4.23 |
|  clk_core                                                                    |                                                                                                                                        | ptop/u_Controller/Interpreter/memory_mux_selector_reg_1                                                                      |               24 |             64 |         2.67 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/FETCH/RD_EN                                                                                          |                                                                                                                              |               20 |             64 |         3.20 |
|  clk_o_BUFG                                                                  |                                                                                                                                        | ResetBootSystem/rst_o_reg_0                                                                                                  |               34 |             85 |         2.50 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/memory_mux_selector_reg_11                                                                               |                                                                                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/memory_mux_selector_reg_10                                                                               |                                                                                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/memory_mux_selector_reg_12                                                                               |                                                                                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/memory_mux_selector_reg_13                                                                               |                                                                                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/memory_mux_selector_reg_14                                                                               |                                                                                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/memory_mux_selector_reg_15                                                                               |                                                                                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/memory_mux_selector_reg_16                                                                               |                                                                                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/memory_mux_selector_reg_17                                                                               |                                                                                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/memory_mux_selector_reg_9                                                                                |                                                                                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/address_reg[10]_0                                                                                        |                                                                                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/address_reg[11]_0                                                                                        |                                                                                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                  | ptop/u_Controller/Interpreter/memory_mux_selector_reg_8                                                                                |                                                                                                                              |               32 |            128 |         4.00 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/MUL_WB_EN_reg_1                                                                              |                                                                                                                              |               33 |            132 |         4.00 |
|  clk_core                                                                    | ptop/u_klessydra_t1_3th_core/Pipe/EXECUTE/MUL_WB_EN_reg_0                                                                              |                                                                                                                              |               33 |            132 |         4.00 |
|  clk_core                                                                    |                                                                                                                                        | ptop/u_Controller/Interpreter/core_reset_reg_0                                                                               |              111 |            175 |         1.58 |
|  clk_core                                                                    | ptop/u_Controller/Interpreter/core_reset_reg_2                                                                                         |                                                                                                                              |              149 |            305 |         2.05 |
+------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+


