read_verilog -sv /eda/processor_ci/rtl/Tethorax.sv
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/PIPELINE.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/RV32I.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/PIPELINE Components/EXE.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/PIPELINE Components/INSTRUCTION_DECODE.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/PIPELINE Components/INSTRUCTION_FETCH.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/PIPELINE Components/MEMORY.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/PIPELINE Components/PC_REGISTER.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/PIPELINE Components/PIPE_EXE_TO_MEM_REGISTER.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/PIPELINE Components/PIPE_ID_TO_EXE_REGISTER.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/PIPELINE Components/PIPE_IF_TO_ID_REGISTER.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/PIPELINE Components/PIPE_MEM_TO_WB_REGISTER.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/PIPELINE Components/WRITE_BACK.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/ADDER_2B.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/ADDER_2B_MSB.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/BARREL_CELL.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/BARREL_SHIFTER.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/CONTROL_WORD_REGROUP.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/DEC5X32.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/DECODE_TO_EXECUTE.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/EXE_ADDER_SUBBER.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/EXE_ADDER_SUBBER_CELL.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/EXE_ADDER_SUBBER_CELL_MSB.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/EXE_BRANCH_RESOLVE.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/EXE_LOGIC_MODULE.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/EXE_SLT_MODULE.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/ID_ADDER.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/ID_DECODER.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/ID_IMM_GENERATOR.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/IF_INSTRMEM.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/MEM_DATAMEM.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/MEM_LOADS_MASKING.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/MEM_STORE_BYTEEN.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/MEM_TO_WB.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/MUX2X1.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/MUX2X1_BIT.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/MUX32X1.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/MUX4X1.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/MUX8X1.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/PC_PLUS_4.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/REGISTER_FILE.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/REG_32B_CASUAL.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/REG_32B_ZERO.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/Tethorax/Tethorax/TOOLBOX Components/STALL_FWD_PREDICT.vhd
read_verilog -sv /eda/processor-ci-controller/modules/uart.sv
read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v

#read_verilog -sv /eda/processor-ci-controller/modules/spi.sv;
#read_verilog -sv /eda/processor-ci-controller/modules/SPI-Slave/rtl/spi_slave.sv;

read_verilog -sv /eda/processor_ci/internal/ahblite_to_wishbone.sv
read_verilog -sv /eda/processor_ci/internal/axi4_to_wishbone.sv
read_verilog -sv /eda/processor_ci/internal/axi4lite_to_wishbone.sv
read_verilog -sv /eda/processor-ci-controller/rtl/fifo.sv
read_verilog -sv /eda/processor-ci-controller/rtl/reset.sv
read_verilog -sv /eda/processor-ci-controller/rtl/clk_divider.sv
read_verilog -sv /eda/processor-ci-controller/rtl/memory.sv
read_verilog -sv /eda/processor-ci-controller/rtl/interpreter.sv
read_verilog -sv /eda/processor-ci-controller/rtl/controller.sv
read_verilog -sv /eda/processor-ci-controller/rtl/timer.sv
read_verilog -sv /eda/processor_ci/internal/fpga_top.sv

set_param general.maxThreads 16

read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc"
set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]

# synth
synth_design -top "fpga_top" -part "xc7a100tcsg324-1"

# place and route
opt_design
place_design

report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt
report_utilization               -file digilent_arty_a7_utilization_place.rpt
report_io                        -file digilent_arty_a7_io.rpt
report_control_sets -verbose     -file digilent_arty_a7_control_sets.rpt
report_clock_utilization         -file digilent_arty_a7_clock_utilization.rpt


route_design

report_timing_summary -no_header -no_detailed_paths
report_route_status                            -file digilent_arty_a7_route_status.rpt
report_drc                                     -file digilent_arty_a7_drc.rpt
report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt
report_power                                   -file digilent_arty_a7_power.rpt


# write bitstream
write_bitstream -force "digilent_arty_a7_100t.bit"

exit