//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name                         I/O  size props
// RDY_coreReq_start              O     1
// RDY_coreReq_perfReq            O     1 reg
// coreIndInv_perfResp            O    73
// RDY_coreIndInv_perfResp        O     1 reg
// RDY_coreIndInv_terminate       O     1 reg
// dCacheToParent_rsToP_notEmpty  O     1
// RDY_dCacheToParent_rsToP_notEmpty  O     1 const
// RDY_dCacheToParent_rsToP_deq   O     1
// dCacheToParent_rsToP_first     O   579
// RDY_dCacheToParent_rsToP_first  O     1
// dCacheToParent_rqToP_notEmpty  O     1
// RDY_dCacheToParent_rqToP_notEmpty  O     1 const
// RDY_dCacheToParent_rqToP_deq   O     1
// dCacheToParent_rqToP_first     O    72
// RDY_dCacheToParent_rqToP_first  O     1
// dCacheToParent_fromP_notFull   O     1
// RDY_dCacheToParent_fromP_notFull  O     1 const
// RDY_dCacheToParent_fromP_enq   O     1
// iCacheToParent_rsToP_notEmpty  O     1
// RDY_iCacheToParent_rsToP_notEmpty  O     1 const
// RDY_iCacheToParent_rsToP_deq   O     1
// iCacheToParent_rsToP_first     O   579
// RDY_iCacheToParent_rsToP_first  O     1
// iCacheToParent_rqToP_notEmpty  O     1
// RDY_iCacheToParent_rqToP_notEmpty  O     1 const
// RDY_iCacheToParent_rqToP_deq   O     1
// iCacheToParent_rqToP_first     O    72
// RDY_iCacheToParent_rqToP_first  O     1
// iCacheToParent_fromP_notFull   O     1
// RDY_iCacheToParent_fromP_notFull  O     1 const
// RDY_iCacheToParent_fromP_enq   O     1
// tlbToMem_memReq_notEmpty       O     1
// RDY_tlbToMem_memReq_notEmpty   O     1 const
// RDY_tlbToMem_memReq_deq        O     1
// tlbToMem_memReq_first          O    65
// RDY_tlbToMem_memReq_first      O     1
// tlbToMem_respLd_notFull        O     1
// RDY_tlbToMem_respLd_notFull    O     1 const
// RDY_tlbToMem_respLd_enq        O     1
// mmioToPlatform_cRq_notEmpty    O     1
// RDY_mmioToPlatform_cRq_notEmpty  O     1 const
// RDY_mmioToPlatform_cRq_deq     O     1
// mmioToPlatform_cRq_first       O   142
// RDY_mmioToPlatform_cRq_first   O     1
// mmioToPlatform_pRs_notFull     O     1
// RDY_mmioToPlatform_pRs_notFull  O     1 const
// RDY_mmioToPlatform_pRs_enq     O     1
// mmioToPlatform_pRq_notFull     O     1
// RDY_mmioToPlatform_pRq_notFull  O     1 const
// RDY_mmioToPlatform_pRq_enq     O     1
// mmioToPlatform_cRs_notEmpty    O     1
// RDY_mmioToPlatform_cRs_notEmpty  O     1 const
// RDY_mmioToPlatform_cRs_deq     O     1
// mmioToPlatform_cRs_first       O     1 reg
// RDY_mmioToPlatform_cRs_first   O     1
// RDY_mmioToPlatform_setTime     O     1 const
// sendDoStats                    O     1 reg
// RDY_sendDoStats                O     1 reg
// RDY_recvDoStats                O     1 const
// deadlock_dCacheCRqStuck_get    O    73 const
// RDY_deadlock_dCacheCRqStuck_get  O     1 const
// deadlock_dCachePRqStuck_get    O    68 const
// RDY_deadlock_dCachePRqStuck_get  O     1 const
// deadlock_iCacheCRqStuck_get    O    68 const
// RDY_deadlock_iCacheCRqStuck_get  O     1 const
// deadlock_iCachePRqStuck_get    O    68 const
// RDY_deadlock_iCachePRqStuck_get  O     1 const
// deadlock_renameInstStuck_get   O    78 const
// RDY_deadlock_renameInstStuck_get  O     1 const
// deadlock_renameCorrectPathStuck_get  O    78 const
// RDY_deadlock_renameCorrectPathStuck_get  O     1 const
// deadlock_commitInstStuck_get   O   163 const
// RDY_deadlock_commitInstStuck_get  O     1 const
// deadlock_commitUserInstStuck_get  O   163 const
// RDY_deadlock_commitUserInstStuck_get  O     1 const
// RDY_deadlock_checkStarted_get  O     1 const
// renameDebug_renameErr_get      O    89 const
// RDY_renameDebug_renameErr_get  O     1 const
// RDY_setMEIP                    O     1 const
// RDY_setSEIP                    O     1 const
// RDY_hart0_run_halt_server_request_put  O     1 reg
// hart0_run_halt_server_response_get  O     1 reg
// RDY_hart0_run_halt_server_response_get  O     1 reg
// RDY_hart0_gpr_mem_server_request_put  O     1 reg
// hart0_gpr_mem_server_response_get  O    65 reg
// RDY_hart0_gpr_mem_server_response_get  O     1 reg
// RDY_hart0_fpr_mem_server_request_put  O     1 reg
// hart0_fpr_mem_server_response_get  O    65 reg
// RDY_hart0_fpr_mem_server_response_get  O     1 reg
// RDY_hart0_csr_mem_server_request_put  O     1 reg
// hart0_csr_mem_server_response_get  O    65 reg
// RDY_hart0_csr_mem_server_response_get  O     1 reg
// v_to_TV_0_get                  O   862
// RDY_v_to_TV_0_get              O     1 reg
// v_to_TV_1_get                  O   862
// RDY_v_to_TV_1_get              O     1 reg
// CLK                            I     1 clock
// RST_N                          I     1 reset
// coreReq_start_running          I     1
// coreReq_start_startpc          I    64
// coreReq_start_toHostAddr       I    64 reg
// coreReq_start_fromHostAddr     I    64 reg
// coreReq_perfReq_loc            I     4 reg
// coreReq_perfReq_t              I     5 reg
// dCacheToParent_fromP_enq_x     I   583
// iCacheToParent_fromP_enq_x     I   583
// tlbToMem_respLd_enq_x          I    65
// mmioToPlatform_pRs_enq_x       I    67
// mmioToPlatform_pRq_enq_x       I    39
// mmioToPlatform_setTime_t       I    64 reg
// recvDoStats_x                  I     1 reg
// setMEIP_v                      I     1 reg
// setSEIP_v                      I     1
// hart0_run_halt_server_request_put  I     1 reg
// hart0_gpr_mem_server_request_put  I    70 reg
// hart0_fpr_mem_server_request_put  I    70 reg
// hart0_csr_mem_server_request_put  I    77 reg
// EN_coreReq_start               I     1
// EN_coreReq_perfReq             I     1
// EN_coreIndInv_terminate        I     1
// EN_dCacheToParent_rsToP_deq    I     1
// EN_dCacheToParent_rqToP_deq    I     1
// EN_dCacheToParent_fromP_enq    I     1
// EN_iCacheToParent_rsToP_deq    I     1
// EN_iCacheToParent_rqToP_deq    I     1
// EN_iCacheToParent_fromP_enq    I     1
// EN_tlbToMem_memReq_deq         I     1
// EN_tlbToMem_respLd_enq         I     1
// EN_mmioToPlatform_cRq_deq      I     1
// EN_mmioToPlatform_pRs_enq      I     1
// EN_mmioToPlatform_pRq_enq      I     1
// EN_mmioToPlatform_cRs_deq      I     1
// EN_mmioToPlatform_setTime      I     1
// EN_recvDoStats                 I     1
// EN_deadlock_checkStarted_get   I     1 unused
// EN_setMEIP                     I     1
// EN_setSEIP                     I     1
// EN_hart0_run_halt_server_request_put  I     1
// EN_hart0_gpr_mem_server_request_put  I     1
// EN_hart0_fpr_mem_server_request_put  I     1
// EN_hart0_csr_mem_server_request_put  I     1
// EN_coreIndInv_perfResp         I     1
// EN_sendDoStats                 I     1
// EN_deadlock_dCacheCRqStuck_get  I     1 unused
// EN_deadlock_dCachePRqStuck_get  I     1 unused
// EN_deadlock_iCacheCRqStuck_get  I     1 unused
// EN_deadlock_iCachePRqStuck_get  I     1 unused
// EN_deadlock_renameInstStuck_get  I     1 unused
// EN_deadlock_renameCorrectPathStuck_get  I     1 unused
// EN_deadlock_commitInstStuck_get  I     1 unused
// EN_deadlock_commitUserInstStuck_get  I     1 unused
// EN_renameDebug_renameErr_get   I     1 unused
// EN_hart0_run_halt_server_response_get  I     1
// EN_hart0_gpr_mem_server_response_get  I     1
// EN_hart0_fpr_mem_server_response_get  I     1
// EN_hart0_csr_mem_server_response_get  I     1
// EN_v_to_TV_0_get               I     1
// EN_v_to_TV_1_get               I     1
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkCore(CLK,
	      RST_N,

	      coreReq_start_running,
	      coreReq_start_startpc,
	      coreReq_start_toHostAddr,
	      coreReq_start_fromHostAddr,
	      EN_coreReq_start,
	      RDY_coreReq_start,

	      coreReq_perfReq_loc,
	      coreReq_perfReq_t,
	      EN_coreReq_perfReq,
	      RDY_coreReq_perfReq,

	      EN_coreIndInv_perfResp,
	      coreIndInv_perfResp,
	      RDY_coreIndInv_perfResp,

	      EN_coreIndInv_terminate,
	      RDY_coreIndInv_terminate,

	      dCacheToParent_rsToP_notEmpty,
	      RDY_dCacheToParent_rsToP_notEmpty,

	      EN_dCacheToParent_rsToP_deq,
	      RDY_dCacheToParent_rsToP_deq,

	      dCacheToParent_rsToP_first,
	      RDY_dCacheToParent_rsToP_first,

	      dCacheToParent_rqToP_notEmpty,
	      RDY_dCacheToParent_rqToP_notEmpty,

	      EN_dCacheToParent_rqToP_deq,
	      RDY_dCacheToParent_rqToP_deq,

	      dCacheToParent_rqToP_first,
	      RDY_dCacheToParent_rqToP_first,

	      dCacheToParent_fromP_notFull,
	      RDY_dCacheToParent_fromP_notFull,

	      dCacheToParent_fromP_enq_x,
	      EN_dCacheToParent_fromP_enq,
	      RDY_dCacheToParent_fromP_enq,

	      iCacheToParent_rsToP_notEmpty,
	      RDY_iCacheToParent_rsToP_notEmpty,

	      EN_iCacheToParent_rsToP_deq,
	      RDY_iCacheToParent_rsToP_deq,

	      iCacheToParent_rsToP_first,
	      RDY_iCacheToParent_rsToP_first,

	      iCacheToParent_rqToP_notEmpty,
	      RDY_iCacheToParent_rqToP_notEmpty,

	      EN_iCacheToParent_rqToP_deq,
	      RDY_iCacheToParent_rqToP_deq,

	      iCacheToParent_rqToP_first,
	      RDY_iCacheToParent_rqToP_first,

	      iCacheToParent_fromP_notFull,
	      RDY_iCacheToParent_fromP_notFull,

	      iCacheToParent_fromP_enq_x,
	      EN_iCacheToParent_fromP_enq,
	      RDY_iCacheToParent_fromP_enq,

	      tlbToMem_memReq_notEmpty,
	      RDY_tlbToMem_memReq_notEmpty,

	      EN_tlbToMem_memReq_deq,
	      RDY_tlbToMem_memReq_deq,

	      tlbToMem_memReq_first,
	      RDY_tlbToMem_memReq_first,

	      tlbToMem_respLd_notFull,
	      RDY_tlbToMem_respLd_notFull,

	      tlbToMem_respLd_enq_x,
	      EN_tlbToMem_respLd_enq,
	      RDY_tlbToMem_respLd_enq,

	      mmioToPlatform_cRq_notEmpty,
	      RDY_mmioToPlatform_cRq_notEmpty,

	      EN_mmioToPlatform_cRq_deq,
	      RDY_mmioToPlatform_cRq_deq,

	      mmioToPlatform_cRq_first,
	      RDY_mmioToPlatform_cRq_first,

	      mmioToPlatform_pRs_notFull,
	      RDY_mmioToPlatform_pRs_notFull,

	      mmioToPlatform_pRs_enq_x,
	      EN_mmioToPlatform_pRs_enq,
	      RDY_mmioToPlatform_pRs_enq,

	      mmioToPlatform_pRq_notFull,
	      RDY_mmioToPlatform_pRq_notFull,

	      mmioToPlatform_pRq_enq_x,
	      EN_mmioToPlatform_pRq_enq,
	      RDY_mmioToPlatform_pRq_enq,

	      mmioToPlatform_cRs_notEmpty,
	      RDY_mmioToPlatform_cRs_notEmpty,

	      EN_mmioToPlatform_cRs_deq,
	      RDY_mmioToPlatform_cRs_deq,

	      mmioToPlatform_cRs_first,
	      RDY_mmioToPlatform_cRs_first,

	      mmioToPlatform_setTime_t,
	      EN_mmioToPlatform_setTime,
	      RDY_mmioToPlatform_setTime,

	      EN_sendDoStats,
	      sendDoStats,
	      RDY_sendDoStats,

	      recvDoStats_x,
	      EN_recvDoStats,
	      RDY_recvDoStats,

	      EN_deadlock_dCacheCRqStuck_get,
	      deadlock_dCacheCRqStuck_get,
	      RDY_deadlock_dCacheCRqStuck_get,

	      EN_deadlock_dCachePRqStuck_get,
	      deadlock_dCachePRqStuck_get,
	      RDY_deadlock_dCachePRqStuck_get,

	      EN_deadlock_iCacheCRqStuck_get,
	      deadlock_iCacheCRqStuck_get,
	      RDY_deadlock_iCacheCRqStuck_get,

	      EN_deadlock_iCachePRqStuck_get,
	      deadlock_iCachePRqStuck_get,
	      RDY_deadlock_iCachePRqStuck_get,

	      EN_deadlock_renameInstStuck_get,
	      deadlock_renameInstStuck_get,
	      RDY_deadlock_renameInstStuck_get,

	      EN_deadlock_renameCorrectPathStuck_get,
	      deadlock_renameCorrectPathStuck_get,
	      RDY_deadlock_renameCorrectPathStuck_get,

	      EN_deadlock_commitInstStuck_get,
	      deadlock_commitInstStuck_get,
	      RDY_deadlock_commitInstStuck_get,

	      EN_deadlock_commitUserInstStuck_get,
	      deadlock_commitUserInstStuck_get,
	      RDY_deadlock_commitUserInstStuck_get,

	      EN_deadlock_checkStarted_get,
	      RDY_deadlock_checkStarted_get,

	      EN_renameDebug_renameErr_get,
	      renameDebug_renameErr_get,
	      RDY_renameDebug_renameErr_get,

	      setMEIP_v,
	      EN_setMEIP,
	      RDY_setMEIP,

	      setSEIP_v,
	      EN_setSEIP,
	      RDY_setSEIP,

	      hart0_run_halt_server_request_put,
	      EN_hart0_run_halt_server_request_put,
	      RDY_hart0_run_halt_server_request_put,

	      EN_hart0_run_halt_server_response_get,
	      hart0_run_halt_server_response_get,
	      RDY_hart0_run_halt_server_response_get,

	      hart0_gpr_mem_server_request_put,
	      EN_hart0_gpr_mem_server_request_put,
	      RDY_hart0_gpr_mem_server_request_put,

	      EN_hart0_gpr_mem_server_response_get,
	      hart0_gpr_mem_server_response_get,
	      RDY_hart0_gpr_mem_server_response_get,

	      hart0_fpr_mem_server_request_put,
	      EN_hart0_fpr_mem_server_request_put,
	      RDY_hart0_fpr_mem_server_request_put,

	      EN_hart0_fpr_mem_server_response_get,
	      hart0_fpr_mem_server_response_get,
	      RDY_hart0_fpr_mem_server_response_get,

	      hart0_csr_mem_server_request_put,
	      EN_hart0_csr_mem_server_request_put,
	      RDY_hart0_csr_mem_server_request_put,

	      EN_hart0_csr_mem_server_response_get,
	      hart0_csr_mem_server_response_get,
	      RDY_hart0_csr_mem_server_response_get,

	      EN_v_to_TV_0_get,
	      v_to_TV_0_get,
	      RDY_v_to_TV_0_get,

	      EN_v_to_TV_1_get,
	      v_to_TV_1_get,
	      RDY_v_to_TV_1_get);
  input  CLK;
  input  RST_N;

  // action method coreReq_start
  input  coreReq_start_running;
  input  [63 : 0] coreReq_start_startpc;
  input  [63 : 0] coreReq_start_toHostAddr;
  input  [63 : 0] coreReq_start_fromHostAddr;
  input  EN_coreReq_start;
  output RDY_coreReq_start;

  // action method coreReq_perfReq
  input  [3 : 0] coreReq_perfReq_loc;
  input  [4 : 0] coreReq_perfReq_t;
  input  EN_coreReq_perfReq;
  output RDY_coreReq_perfReq;

  // actionvalue method coreIndInv_perfResp
  input  EN_coreIndInv_perfResp;
  output [72 : 0] coreIndInv_perfResp;
  output RDY_coreIndInv_perfResp;

  // action method coreIndInv_terminate
  input  EN_coreIndInv_terminate;
  output RDY_coreIndInv_terminate;

  // value method dCacheToParent_rsToP_notEmpty
  output dCacheToParent_rsToP_notEmpty;
  output RDY_dCacheToParent_rsToP_notEmpty;

  // action method dCacheToParent_rsToP_deq
  input  EN_dCacheToParent_rsToP_deq;
  output RDY_dCacheToParent_rsToP_deq;

  // value method dCacheToParent_rsToP_first
  output [578 : 0] dCacheToParent_rsToP_first;
  output RDY_dCacheToParent_rsToP_first;

  // value method dCacheToParent_rqToP_notEmpty
  output dCacheToParent_rqToP_notEmpty;
  output RDY_dCacheToParent_rqToP_notEmpty;

  // action method dCacheToParent_rqToP_deq
  input  EN_dCacheToParent_rqToP_deq;
  output RDY_dCacheToParent_rqToP_deq;

  // value method dCacheToParent_rqToP_first
  output [71 : 0] dCacheToParent_rqToP_first;
  output RDY_dCacheToParent_rqToP_first;

  // value method dCacheToParent_fromP_notFull
  output dCacheToParent_fromP_notFull;
  output RDY_dCacheToParent_fromP_notFull;

  // action method dCacheToParent_fromP_enq
  input  [582 : 0] dCacheToParent_fromP_enq_x;
  input  EN_dCacheToParent_fromP_enq;
  output RDY_dCacheToParent_fromP_enq;

  // value method iCacheToParent_rsToP_notEmpty
  output iCacheToParent_rsToP_notEmpty;
  output RDY_iCacheToParent_rsToP_notEmpty;

  // action method iCacheToParent_rsToP_deq
  input  EN_iCacheToParent_rsToP_deq;
  output RDY_iCacheToParent_rsToP_deq;

  // value method iCacheToParent_rsToP_first
  output [578 : 0] iCacheToParent_rsToP_first;
  output RDY_iCacheToParent_rsToP_first;

  // value method iCacheToParent_rqToP_notEmpty
  output iCacheToParent_rqToP_notEmpty;
  output RDY_iCacheToParent_rqToP_notEmpty;

  // action method iCacheToParent_rqToP_deq
  input  EN_iCacheToParent_rqToP_deq;
  output RDY_iCacheToParent_rqToP_deq;

  // value method iCacheToParent_rqToP_first
  output [71 : 0] iCacheToParent_rqToP_first;
  output RDY_iCacheToParent_rqToP_first;

  // value method iCacheToParent_fromP_notFull
  output iCacheToParent_fromP_notFull;
  output RDY_iCacheToParent_fromP_notFull;

  // action method iCacheToParent_fromP_enq
  input  [582 : 0] iCacheToParent_fromP_enq_x;
  input  EN_iCacheToParent_fromP_enq;
  output RDY_iCacheToParent_fromP_enq;

  // value method tlbToMem_memReq_notEmpty
  output tlbToMem_memReq_notEmpty;
  output RDY_tlbToMem_memReq_notEmpty;

  // action method tlbToMem_memReq_deq
  input  EN_tlbToMem_memReq_deq;
  output RDY_tlbToMem_memReq_deq;

  // value method tlbToMem_memReq_first
  output [64 : 0] tlbToMem_memReq_first;
  output RDY_tlbToMem_memReq_first;

  // value method tlbToMem_respLd_notFull
  output tlbToMem_respLd_notFull;
  output RDY_tlbToMem_respLd_notFull;

  // action method tlbToMem_respLd_enq
  input  [64 : 0] tlbToMem_respLd_enq_x;
  input  EN_tlbToMem_respLd_enq;
  output RDY_tlbToMem_respLd_enq;

  // value method mmioToPlatform_cRq_notEmpty
  output mmioToPlatform_cRq_notEmpty;
  output RDY_mmioToPlatform_cRq_notEmpty;

  // action method mmioToPlatform_cRq_deq
  input  EN_mmioToPlatform_cRq_deq;
  output RDY_mmioToPlatform_cRq_deq;

  // value method mmioToPlatform_cRq_first
  output [141 : 0] mmioToPlatform_cRq_first;
  output RDY_mmioToPlatform_cRq_first;

  // value method mmioToPlatform_pRs_notFull
  output mmioToPlatform_pRs_notFull;
  output RDY_mmioToPlatform_pRs_notFull;

  // action method mmioToPlatform_pRs_enq
  input  [66 : 0] mmioToPlatform_pRs_enq_x;
  input  EN_mmioToPlatform_pRs_enq;
  output RDY_mmioToPlatform_pRs_enq;

  // value method mmioToPlatform_pRq_notFull
  output mmioToPlatform_pRq_notFull;
  output RDY_mmioToPlatform_pRq_notFull;

  // action method mmioToPlatform_pRq_enq
  input  [38 : 0] mmioToPlatform_pRq_enq_x;
  input  EN_mmioToPlatform_pRq_enq;
  output RDY_mmioToPlatform_pRq_enq;

  // value method mmioToPlatform_cRs_notEmpty
  output mmioToPlatform_cRs_notEmpty;
  output RDY_mmioToPlatform_cRs_notEmpty;

  // action method mmioToPlatform_cRs_deq
  input  EN_mmioToPlatform_cRs_deq;
  output RDY_mmioToPlatform_cRs_deq;

  // value method mmioToPlatform_cRs_first
  output mmioToPlatform_cRs_first;
  output RDY_mmioToPlatform_cRs_first;

  // action method mmioToPlatform_setTime
  input  [63 : 0] mmioToPlatform_setTime_t;
  input  EN_mmioToPlatform_setTime;
  output RDY_mmioToPlatform_setTime;

  // actionvalue method sendDoStats
  input  EN_sendDoStats;
  output sendDoStats;
  output RDY_sendDoStats;

  // action method recvDoStats
  input  recvDoStats_x;
  input  EN_recvDoStats;
  output RDY_recvDoStats;

  // actionvalue method deadlock_dCacheCRqStuck_get
  input  EN_deadlock_dCacheCRqStuck_get;
  output [72 : 0] deadlock_dCacheCRqStuck_get;
  output RDY_deadlock_dCacheCRqStuck_get;

  // actionvalue method deadlock_dCachePRqStuck_get
  input  EN_deadlock_dCachePRqStuck_get;
  output [67 : 0] deadlock_dCachePRqStuck_get;
  output RDY_deadlock_dCachePRqStuck_get;

  // actionvalue method deadlock_iCacheCRqStuck_get
  input  EN_deadlock_iCacheCRqStuck_get;
  output [67 : 0] deadlock_iCacheCRqStuck_get;
  output RDY_deadlock_iCacheCRqStuck_get;

  // actionvalue method deadlock_iCachePRqStuck_get
  input  EN_deadlock_iCachePRqStuck_get;
  output [67 : 0] deadlock_iCachePRqStuck_get;
  output RDY_deadlock_iCachePRqStuck_get;

  // actionvalue method deadlock_renameInstStuck_get
  input  EN_deadlock_renameInstStuck_get;
  output [77 : 0] deadlock_renameInstStuck_get;
  output RDY_deadlock_renameInstStuck_get;

  // actionvalue method deadlock_renameCorrectPathStuck_get
  input  EN_deadlock_renameCorrectPathStuck_get;
  output [77 : 0] deadlock_renameCorrectPathStuck_get;
  output RDY_deadlock_renameCorrectPathStuck_get;

  // actionvalue method deadlock_commitInstStuck_get
  input  EN_deadlock_commitInstStuck_get;
  output [162 : 0] deadlock_commitInstStuck_get;
  output RDY_deadlock_commitInstStuck_get;

  // actionvalue method deadlock_commitUserInstStuck_get
  input  EN_deadlock_commitUserInstStuck_get;
  output [162 : 0] deadlock_commitUserInstStuck_get;
  output RDY_deadlock_commitUserInstStuck_get;

  // action method deadlock_checkStarted_get
  input  EN_deadlock_checkStarted_get;
  output RDY_deadlock_checkStarted_get;

  // actionvalue method renameDebug_renameErr_get
  input  EN_renameDebug_renameErr_get;
  output [88 : 0] renameDebug_renameErr_get;
  output RDY_renameDebug_renameErr_get;

  // action method setMEIP
  input  setMEIP_v;
  input  EN_setMEIP;
  output RDY_setMEIP;

  // action method setSEIP
  input  setSEIP_v;
  input  EN_setSEIP;
  output RDY_setSEIP;

  // action method hart0_run_halt_server_request_put
  input  hart0_run_halt_server_request_put;
  input  EN_hart0_run_halt_server_request_put;
  output RDY_hart0_run_halt_server_request_put;

  // actionvalue method hart0_run_halt_server_response_get
  input  EN_hart0_run_halt_server_response_get;
  output hart0_run_halt_server_response_get;
  output RDY_hart0_run_halt_server_response_get;

  // action method hart0_gpr_mem_server_request_put
  input  [69 : 0] hart0_gpr_mem_server_request_put;
  input  EN_hart0_gpr_mem_server_request_put;
  output RDY_hart0_gpr_mem_server_request_put;

  // actionvalue method hart0_gpr_mem_server_response_get
  input  EN_hart0_gpr_mem_server_response_get;
  output [64 : 0] hart0_gpr_mem_server_response_get;
  output RDY_hart0_gpr_mem_server_response_get;

  // action method hart0_fpr_mem_server_request_put
  input  [69 : 0] hart0_fpr_mem_server_request_put;
  input  EN_hart0_fpr_mem_server_request_put;
  output RDY_hart0_fpr_mem_server_request_put;

  // actionvalue method hart0_fpr_mem_server_response_get
  input  EN_hart0_fpr_mem_server_response_get;
  output [64 : 0] hart0_fpr_mem_server_response_get;
  output RDY_hart0_fpr_mem_server_response_get;

  // action method hart0_csr_mem_server_request_put
  input  [76 : 0] hart0_csr_mem_server_request_put;
  input  EN_hart0_csr_mem_server_request_put;
  output RDY_hart0_csr_mem_server_request_put;

  // actionvalue method hart0_csr_mem_server_response_get
  input  EN_hart0_csr_mem_server_response_get;
  output [64 : 0] hart0_csr_mem_server_response_get;
  output RDY_hart0_csr_mem_server_response_get;

  // actionvalue method v_to_TV_0_get
  input  EN_v_to_TV_0_get;
  output [861 : 0] v_to_TV_0_get;
  output RDY_v_to_TV_0_get;

  // actionvalue method v_to_TV_1_get
  input  EN_v_to_TV_1_get;
  output [861 : 0] v_to_TV_1_get;
  output RDY_v_to_TV_1_get;

  // signals for module outputs
  wire [861 : 0] v_to_TV_0_get, v_to_TV_1_get;
  wire [578 : 0] dCacheToParent_rsToP_first, iCacheToParent_rsToP_first;
  wire [162 : 0] deadlock_commitInstStuck_get,
		 deadlock_commitUserInstStuck_get;
  wire [141 : 0] mmioToPlatform_cRq_first;
  wire [88 : 0] renameDebug_renameErr_get;
  wire [77 : 0] deadlock_renameCorrectPathStuck_get,
		deadlock_renameInstStuck_get;
  wire [72 : 0] coreIndInv_perfResp, deadlock_dCacheCRqStuck_get;
  wire [71 : 0] dCacheToParent_rqToP_first, iCacheToParent_rqToP_first;
  wire [67 : 0] deadlock_dCachePRqStuck_get,
		deadlock_iCacheCRqStuck_get,
		deadlock_iCachePRqStuck_get;
  wire [64 : 0] hart0_csr_mem_server_response_get,
		hart0_fpr_mem_server_response_get,
		hart0_gpr_mem_server_response_get,
		tlbToMem_memReq_first;
  wire RDY_coreIndInv_perfResp,
       RDY_coreIndInv_terminate,
       RDY_coreReq_perfReq,
       RDY_coreReq_start,
       RDY_dCacheToParent_fromP_enq,
       RDY_dCacheToParent_fromP_notFull,
       RDY_dCacheToParent_rqToP_deq,
       RDY_dCacheToParent_rqToP_first,
       RDY_dCacheToParent_rqToP_notEmpty,
       RDY_dCacheToParent_rsToP_deq,
       RDY_dCacheToParent_rsToP_first,
       RDY_dCacheToParent_rsToP_notEmpty,
       RDY_deadlock_checkStarted_get,
       RDY_deadlock_commitInstStuck_get,
       RDY_deadlock_commitUserInstStuck_get,
       RDY_deadlock_dCacheCRqStuck_get,
       RDY_deadlock_dCachePRqStuck_get,
       RDY_deadlock_iCacheCRqStuck_get,
       RDY_deadlock_iCachePRqStuck_get,
       RDY_deadlock_renameCorrectPathStuck_get,
       RDY_deadlock_renameInstStuck_get,
       RDY_hart0_csr_mem_server_request_put,
       RDY_hart0_csr_mem_server_response_get,
       RDY_hart0_fpr_mem_server_request_put,
       RDY_hart0_fpr_mem_server_response_get,
       RDY_hart0_gpr_mem_server_request_put,
       RDY_hart0_gpr_mem_server_response_get,
       RDY_hart0_run_halt_server_request_put,
       RDY_hart0_run_halt_server_response_get,
       RDY_iCacheToParent_fromP_enq,
       RDY_iCacheToParent_fromP_notFull,
       RDY_iCacheToParent_rqToP_deq,
       RDY_iCacheToParent_rqToP_first,
       RDY_iCacheToParent_rqToP_notEmpty,
       RDY_iCacheToParent_rsToP_deq,
       RDY_iCacheToParent_rsToP_first,
       RDY_iCacheToParent_rsToP_notEmpty,
       RDY_mmioToPlatform_cRq_deq,
       RDY_mmioToPlatform_cRq_first,
       RDY_mmioToPlatform_cRq_notEmpty,
       RDY_mmioToPlatform_cRs_deq,
       RDY_mmioToPlatform_cRs_first,
       RDY_mmioToPlatform_cRs_notEmpty,
       RDY_mmioToPlatform_pRq_enq,
       RDY_mmioToPlatform_pRq_notFull,
       RDY_mmioToPlatform_pRs_enq,
       RDY_mmioToPlatform_pRs_notFull,
       RDY_mmioToPlatform_setTime,
       RDY_recvDoStats,
       RDY_renameDebug_renameErr_get,
       RDY_sendDoStats,
       RDY_setMEIP,
       RDY_setSEIP,
       RDY_tlbToMem_memReq_deq,
       RDY_tlbToMem_memReq_first,
       RDY_tlbToMem_memReq_notEmpty,
       RDY_tlbToMem_respLd_enq,
       RDY_tlbToMem_respLd_notFull,
       RDY_v_to_TV_0_get,
       RDY_v_to_TV_1_get,
       dCacheToParent_fromP_notFull,
       dCacheToParent_rqToP_notEmpty,
       dCacheToParent_rsToP_notEmpty,
       hart0_run_halt_server_response_get,
       iCacheToParent_fromP_notFull,
       iCacheToParent_rqToP_notEmpty,
       iCacheToParent_rsToP_notEmpty,
       mmioToPlatform_cRq_notEmpty,
       mmioToPlatform_cRs_first,
       mmioToPlatform_cRs_notEmpty,
       mmioToPlatform_pRq_notFull,
       mmioToPlatform_pRs_notFull,
       sendDoStats,
       tlbToMem_memReq_notEmpty,
       tlbToMem_respLd_notFull;

  // inlined wires
  reg [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget;
  reg [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget;
  reg [58 : 0] coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget;
  reg [1 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget;
  wire [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget;
  wire [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget;
  wire [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget;
  wire [142 : 0] mmio_cRqQ_enqReq_lat_0$wget, mmio_dataReqQ_enqReq_lat_0$wget;
  wire [76 : 0] coreFix_memExe_issueLd$wget;
  wire [72 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget;
  wire [70 : 0] coreFix_aluExe_0_bypassWire_0$wget,
		coreFix_aluExe_0_bypassWire_1$wget,
		coreFix_aluExe_0_bypassWire_2$wget,
		coreFix_aluExe_0_bypassWire_3$wget;
  wire [69 : 0] coreFix_memExe_forwardQ_enqReq_lat_0$wget,
		coreFix_memExe_memRespLdQ_enqReq_lat_0$wget;
  wire [68 : 0] coreFix_memExe_reqLdQ_data_0_lat_0$wget;
  wire [67 : 0] mmio_pRsQ_enqReq_lat_0$wget;
  wire [65 : 0] coreFix_memExe_reqStQ_data_0_lat_0$wget,
		mmio_dataRespQ_enqReq_lat_0$wget;
  wire [39 : 0] mmio_pRqQ_enqReq_lat_0$wget;
  wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget;
  wire [1 : 0] mmio_cRsQ_enqReq_lat_0$wget;
  wire coreFix_aluExe_0_bypassWire_0$whas,
       coreFix_aluExe_0_bypassWire_1$whas,
       coreFix_aluExe_0_bypassWire_2$whas,
       coreFix_aluExe_0_bypassWire_3$whas,
       coreFix_aluExe_1_bypassWire_2$whas,
       coreFix_aluExe_1_bypassWire_3$whas,
       coreFix_fpuMulDivExe_0_bypassWire_2$whas,
       coreFix_fpuMulDivExe_0_bypassWire_3$whas,
       coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas,
       coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas,
       coreFix_globalSpecUpdate_correctSpecTag_0$whas,
       coreFix_globalSpecUpdate_correctSpecTag_1$whas,
       coreFix_memExe_bypassWire_2$whas,
       coreFix_memExe_bypassWire_3$whas,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas,
       coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas,
       coreFix_memExe_forwardQ_enqReq_lat_0$whas,
       coreFix_memExe_issueLd$whas,
       coreFix_memExe_memRespLdQ_enqReq_lat_0$whas,
       coreFix_memExe_reqLdQ_data_0_lat_0$whas,
       coreFix_memExe_reqLdQ_empty_lat_0$whas,
       coreFix_memExe_reqLdQ_full_lat_0$whas,
       coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas,
       coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas,
       coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas,
       coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas,
       csrInstOrInterruptInflight_lat_1$whas,
       csrf_mcycle_ehr_data_lat_0$whas,
       csrf_minstret_ehr_data_dummy_1_0$whas,
       csrf_minstret_ehr_data_lat_0$whas,
       csrf_minstret_ehr_data_lat_1$whas,
       mmio_cRqQ_enqReq_lat_0$whas,
       mmio_dataPendQ_enqReq_lat_0$whas,
       mmio_dataReqQ_enqReq_lat_0$whas,
       mmio_dataRespQ_deqReq_lat_0$whas,
       mmio_pRsQ_deqReq_lat_0$whas;

  // register commitStage_commitTrap
  reg [165 : 0] commitStage_commitTrap;
  wire [165 : 0] commitStage_commitTrap$D_IN;
  wire commitStage_commitTrap$EN;

  // register commitStage_rg_just_after_reset
  reg commitStage_rg_just_after_reset;
  wire commitStage_rg_just_after_reset$D_IN,
       commitStage_rg_just_after_reset$EN;

  // register commitStage_rg_old_mip_csr_val
  reg [63 : 0] commitStage_rg_old_mip_csr_val;
  wire [63 : 0] commitStage_rg_old_mip_csr_val$D_IN;
  wire commitStage_rg_old_mip_csr_val$EN;

  // register commitStage_rg_run_state
  reg commitStage_rg_run_state;
  wire commitStage_rg_run_state$D_IN, commitStage_rg_run_state$EN;

  // register commitStage_rg_serial_num
  reg [63 : 0] commitStage_rg_serial_num;
  reg [63 : 0] commitStage_rg_serial_num$D_IN;
  wire commitStage_rg_serial_num$EN;

  // register coreFix_doStatsReg
  reg coreFix_doStatsReg;
  wire coreFix_doStatsReg$D_IN, coreFix_doStatsReg$EN;

  // register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt
  reg [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt;
  wire [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$D_IN;
  wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$EN;

  // register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init
  reg coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init;
  wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$D_IN,
       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$EN;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit
  reg [1 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit;
  wire [1 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN;
  wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0
  reg [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0;
  wire [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$D_IN;
  wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$EN;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1
  reg [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1;
  wire [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$D_IN;
  wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl
  reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0
  reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0;
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1
  reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1;
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2
  reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2;
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3
  reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3;
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4
  reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4;
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5
  reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5;
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6
  reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6;
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7
  reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7;
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP
  reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP;
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl
  reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty
  reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP
  reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP;
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl
  reg [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl;
  wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full
  reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl
  reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl;
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0
  reg [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0;
  wire [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1
  reg [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1;
  wire [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP
  reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP;
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl
  reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl;
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty
  reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty;
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP
  reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP;
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl
  reg [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl;
  wire [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full
  reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full;
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl
  reg [58 : 0] coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl;
  wire [58 : 0] coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_processAmo
  reg [160 : 0] coreFix_memExe_dMem_cache_m_banks_0_processAmo;
  reg [160 : 0] coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_processAmo$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl
  reg [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl;
  wire [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl
  reg coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl
  reg coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl
  reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0
  reg [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0;
  wire [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1
  reg [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1;
  wire [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP
  reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl
  reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty
  reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP
  reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl
  reg [72 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl;
  wire [72 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full
  reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl
  reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl;
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0
  reg [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0;
  wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1
  reg [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1;
  wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP
  reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP;
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl
  reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl;
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty
  reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty;
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP
  reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP;
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl
  reg [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl;
  wire [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full
  reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full;
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$EN;

  // register coreFix_memExe_dMem_perfReqQ_clearReq_rl
  reg coreFix_memExe_dMem_perfReqQ_clearReq_rl;
  wire coreFix_memExe_dMem_perfReqQ_clearReq_rl$D_IN,
       coreFix_memExe_dMem_perfReqQ_clearReq_rl$EN;

  // register coreFix_memExe_dMem_perfReqQ_data_0
  reg [3 : 0] coreFix_memExe_dMem_perfReqQ_data_0;
  wire [3 : 0] coreFix_memExe_dMem_perfReqQ_data_0$D_IN;
  wire coreFix_memExe_dMem_perfReqQ_data_0$EN;

  // register coreFix_memExe_dMem_perfReqQ_deqReq_rl
  reg coreFix_memExe_dMem_perfReqQ_deqReq_rl;
  wire coreFix_memExe_dMem_perfReqQ_deqReq_rl$D_IN,
       coreFix_memExe_dMem_perfReqQ_deqReq_rl$EN;

  // register coreFix_memExe_dMem_perfReqQ_empty
  reg coreFix_memExe_dMem_perfReqQ_empty;
  wire coreFix_memExe_dMem_perfReqQ_empty$D_IN,
       coreFix_memExe_dMem_perfReqQ_empty$EN;

  // register coreFix_memExe_dMem_perfReqQ_enqReq_rl
  reg [4 : 0] coreFix_memExe_dMem_perfReqQ_enqReq_rl;
  wire [4 : 0] coreFix_memExe_dMem_perfReqQ_enqReq_rl$D_IN;
  wire coreFix_memExe_dMem_perfReqQ_enqReq_rl$EN;

  // register coreFix_memExe_dMem_perfReqQ_full
  reg coreFix_memExe_dMem_perfReqQ_full;
  wire coreFix_memExe_dMem_perfReqQ_full$D_IN,
       coreFix_memExe_dMem_perfReqQ_full$EN;

  // register coreFix_memExe_forwardQ_clearReq_rl
  reg coreFix_memExe_forwardQ_clearReq_rl;
  wire coreFix_memExe_forwardQ_clearReq_rl$D_IN,
       coreFix_memExe_forwardQ_clearReq_rl$EN;

  // register coreFix_memExe_forwardQ_data_0
  reg [68 : 0] coreFix_memExe_forwardQ_data_0;
  wire [68 : 0] coreFix_memExe_forwardQ_data_0$D_IN;
  wire coreFix_memExe_forwardQ_data_0$EN;

  // register coreFix_memExe_forwardQ_data_1
  reg [68 : 0] coreFix_memExe_forwardQ_data_1;
  wire [68 : 0] coreFix_memExe_forwardQ_data_1$D_IN;
  wire coreFix_memExe_forwardQ_data_1$EN;

  // register coreFix_memExe_forwardQ_deqP
  reg coreFix_memExe_forwardQ_deqP;
  wire coreFix_memExe_forwardQ_deqP$D_IN, coreFix_memExe_forwardQ_deqP$EN;

  // register coreFix_memExe_forwardQ_deqReq_rl
  reg coreFix_memExe_forwardQ_deqReq_rl;
  wire coreFix_memExe_forwardQ_deqReq_rl$D_IN,
       coreFix_memExe_forwardQ_deqReq_rl$EN;

  // register coreFix_memExe_forwardQ_empty
  reg coreFix_memExe_forwardQ_empty;
  wire coreFix_memExe_forwardQ_empty$D_IN, coreFix_memExe_forwardQ_empty$EN;

  // register coreFix_memExe_forwardQ_enqP
  reg coreFix_memExe_forwardQ_enqP;
  wire coreFix_memExe_forwardQ_enqP$D_IN, coreFix_memExe_forwardQ_enqP$EN;

  // register coreFix_memExe_forwardQ_enqReq_rl
  reg [69 : 0] coreFix_memExe_forwardQ_enqReq_rl;
  wire [69 : 0] coreFix_memExe_forwardQ_enqReq_rl$D_IN;
  wire coreFix_memExe_forwardQ_enqReq_rl$EN;

  // register coreFix_memExe_forwardQ_full
  reg coreFix_memExe_forwardQ_full;
  wire coreFix_memExe_forwardQ_full$D_IN, coreFix_memExe_forwardQ_full$EN;

  // register coreFix_memExe_memRespLdQ_clearReq_rl
  reg coreFix_memExe_memRespLdQ_clearReq_rl;
  wire coreFix_memExe_memRespLdQ_clearReq_rl$D_IN,
       coreFix_memExe_memRespLdQ_clearReq_rl$EN;

  // register coreFix_memExe_memRespLdQ_data_0
  reg [68 : 0] coreFix_memExe_memRespLdQ_data_0;
  wire [68 : 0] coreFix_memExe_memRespLdQ_data_0$D_IN;
  wire coreFix_memExe_memRespLdQ_data_0$EN;

  // register coreFix_memExe_memRespLdQ_data_1
  reg [68 : 0] coreFix_memExe_memRespLdQ_data_1;
  wire [68 : 0] coreFix_memExe_memRespLdQ_data_1$D_IN;
  wire coreFix_memExe_memRespLdQ_data_1$EN;

  // register coreFix_memExe_memRespLdQ_deqP
  reg coreFix_memExe_memRespLdQ_deqP;
  wire coreFix_memExe_memRespLdQ_deqP$D_IN, coreFix_memExe_memRespLdQ_deqP$EN;

  // register coreFix_memExe_memRespLdQ_deqReq_rl
  reg coreFix_memExe_memRespLdQ_deqReq_rl;
  wire coreFix_memExe_memRespLdQ_deqReq_rl$D_IN,
       coreFix_memExe_memRespLdQ_deqReq_rl$EN;

  // register coreFix_memExe_memRespLdQ_empty
  reg coreFix_memExe_memRespLdQ_empty;
  wire coreFix_memExe_memRespLdQ_empty$D_IN,
       coreFix_memExe_memRespLdQ_empty$EN;

  // register coreFix_memExe_memRespLdQ_enqP
  reg coreFix_memExe_memRespLdQ_enqP;
  wire coreFix_memExe_memRespLdQ_enqP$D_IN, coreFix_memExe_memRespLdQ_enqP$EN;

  // register coreFix_memExe_memRespLdQ_enqReq_rl
  reg [69 : 0] coreFix_memExe_memRespLdQ_enqReq_rl;
  wire [69 : 0] coreFix_memExe_memRespLdQ_enqReq_rl$D_IN;
  wire coreFix_memExe_memRespLdQ_enqReq_rl$EN;

  // register coreFix_memExe_memRespLdQ_full
  reg coreFix_memExe_memRespLdQ_full;
  wire coreFix_memExe_memRespLdQ_full$D_IN, coreFix_memExe_memRespLdQ_full$EN;

  // register coreFix_memExe_reqLdQ_data_0_rl
  reg [68 : 0] coreFix_memExe_reqLdQ_data_0_rl;
  wire [68 : 0] coreFix_memExe_reqLdQ_data_0_rl$D_IN;
  wire coreFix_memExe_reqLdQ_data_0_rl$EN;

  // register coreFix_memExe_reqLdQ_empty_rl
  reg coreFix_memExe_reqLdQ_empty_rl;
  wire coreFix_memExe_reqLdQ_empty_rl$D_IN, coreFix_memExe_reqLdQ_empty_rl$EN;

  // register coreFix_memExe_reqLdQ_full_rl
  reg coreFix_memExe_reqLdQ_full_rl;
  wire coreFix_memExe_reqLdQ_full_rl$D_IN, coreFix_memExe_reqLdQ_full_rl$EN;

  // register coreFix_memExe_reqLrScAmoQ_data_0_rl
  reg [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_rl;
  wire [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN;
  wire coreFix_memExe_reqLrScAmoQ_data_0_rl$EN;

  // register coreFix_memExe_reqLrScAmoQ_empty_rl
  reg coreFix_memExe_reqLrScAmoQ_empty_rl;
  wire coreFix_memExe_reqLrScAmoQ_empty_rl$D_IN,
       coreFix_memExe_reqLrScAmoQ_empty_rl$EN;

  // register coreFix_memExe_reqLrScAmoQ_full_rl
  reg coreFix_memExe_reqLrScAmoQ_full_rl;
  wire coreFix_memExe_reqLrScAmoQ_full_rl$D_IN,
       coreFix_memExe_reqLrScAmoQ_full_rl$EN;

  // register coreFix_memExe_reqStQ_data_0_rl
  reg [65 : 0] coreFix_memExe_reqStQ_data_0_rl;
  wire [65 : 0] coreFix_memExe_reqStQ_data_0_rl$D_IN;
  wire coreFix_memExe_reqStQ_data_0_rl$EN;

  // register coreFix_memExe_reqStQ_empty_rl
  reg coreFix_memExe_reqStQ_empty_rl;
  wire coreFix_memExe_reqStQ_empty_rl$D_IN, coreFix_memExe_reqStQ_empty_rl$EN;

  // register coreFix_memExe_reqStQ_full_rl
  reg coreFix_memExe_reqStQ_full_rl;
  wire coreFix_memExe_reqStQ_full_rl$D_IN, coreFix_memExe_reqStQ_full_rl$EN;

  // register coreFix_memExe_respLrScAmoQ_clearReq_rl
  reg coreFix_memExe_respLrScAmoQ_clearReq_rl;
  wire coreFix_memExe_respLrScAmoQ_clearReq_rl$D_IN,
       coreFix_memExe_respLrScAmoQ_clearReq_rl$EN;

  // register coreFix_memExe_respLrScAmoQ_data_0
  reg [63 : 0] coreFix_memExe_respLrScAmoQ_data_0;
  wire [63 : 0] coreFix_memExe_respLrScAmoQ_data_0$D_IN;
  wire coreFix_memExe_respLrScAmoQ_data_0$EN;

  // register coreFix_memExe_respLrScAmoQ_deqReq_rl
  reg coreFix_memExe_respLrScAmoQ_deqReq_rl;
  wire coreFix_memExe_respLrScAmoQ_deqReq_rl$D_IN,
       coreFix_memExe_respLrScAmoQ_deqReq_rl$EN;

  // register coreFix_memExe_respLrScAmoQ_empty
  reg coreFix_memExe_respLrScAmoQ_empty;
  wire coreFix_memExe_respLrScAmoQ_empty$D_IN,
       coreFix_memExe_respLrScAmoQ_empty$EN;

  // register coreFix_memExe_respLrScAmoQ_enqReq_rl
  reg [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_rl;
  wire [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN;
  wire coreFix_memExe_respLrScAmoQ_enqReq_rl$EN;

  // register coreFix_memExe_respLrScAmoQ_full
  reg coreFix_memExe_respLrScAmoQ_full;
  wire coreFix_memExe_respLrScAmoQ_full$D_IN,
       coreFix_memExe_respLrScAmoQ_full$EN;

  // register coreFix_memExe_waitLrScAmoMMIOResp
  reg [2 : 0] coreFix_memExe_waitLrScAmoMMIOResp;
  reg [2 : 0] coreFix_memExe_waitLrScAmoMMIOResp$D_IN;
  wire coreFix_memExe_waitLrScAmoMMIOResp$EN;

  // register csrInstOrInterruptInflight_rl
  reg csrInstOrInterruptInflight_rl;
  wire csrInstOrInterruptInflight_rl$D_IN, csrInstOrInterruptInflight_rl$EN;

  // register csrf_external_int_en_vec_0
  reg csrf_external_int_en_vec_0;
  wire csrf_external_int_en_vec_0$D_IN, csrf_external_int_en_vec_0$EN;

  // register csrf_external_int_en_vec_1
  reg csrf_external_int_en_vec_1;
  wire csrf_external_int_en_vec_1$D_IN, csrf_external_int_en_vec_1$EN;

  // register csrf_external_int_en_vec_3
  reg csrf_external_int_en_vec_3;
  wire csrf_external_int_en_vec_3$D_IN, csrf_external_int_en_vec_3$EN;

  // register csrf_external_int_pend_vec_0
  reg csrf_external_int_pend_vec_0;
  wire csrf_external_int_pend_vec_0$D_IN, csrf_external_int_pend_vec_0$EN;

  // register csrf_external_int_pend_vec_1
  reg csrf_external_int_pend_vec_1;
  reg csrf_external_int_pend_vec_1$D_IN;
  wire csrf_external_int_pend_vec_1$EN;

  // register csrf_external_int_pend_vec_3
  reg csrf_external_int_pend_vec_3;
  wire csrf_external_int_pend_vec_3$D_IN, csrf_external_int_pend_vec_3$EN;

  // register csrf_fflags_reg
  reg [4 : 0] csrf_fflags_reg;
  reg [4 : 0] csrf_fflags_reg$D_IN;
  wire csrf_fflags_reg$EN;

  // register csrf_frm_reg
  reg [2 : 0] csrf_frm_reg;
  wire [2 : 0] csrf_frm_reg$D_IN;
  wire csrf_frm_reg$EN;

  // register csrf_fs_reg
  reg [1 : 0] csrf_fs_reg;
  reg [1 : 0] csrf_fs_reg$D_IN;
  wire csrf_fs_reg$EN;

  // register csrf_ie_vec_0
  reg csrf_ie_vec_0;
  wire csrf_ie_vec_0$D_IN, csrf_ie_vec_0$EN;

  // register csrf_ie_vec_1
  reg csrf_ie_vec_1;
  reg csrf_ie_vec_1$D_IN;
  wire csrf_ie_vec_1$EN;

  // register csrf_ie_vec_3
  reg csrf_ie_vec_3;
  reg csrf_ie_vec_3$D_IN;
  wire csrf_ie_vec_3$EN;

  // register csrf_mcause_code_reg
  reg [3 : 0] csrf_mcause_code_reg;
  reg [3 : 0] csrf_mcause_code_reg$D_IN;
  wire csrf_mcause_code_reg$EN;

  // register csrf_mcause_interrupt_reg
  reg csrf_mcause_interrupt_reg;
  reg csrf_mcause_interrupt_reg$D_IN;
  wire csrf_mcause_interrupt_reg$EN;

  // register csrf_mcounteren_cy_reg
  reg csrf_mcounteren_cy_reg;
  wire csrf_mcounteren_cy_reg$D_IN, csrf_mcounteren_cy_reg$EN;

  // register csrf_mcounteren_ir_reg
  reg csrf_mcounteren_ir_reg;
  wire csrf_mcounteren_ir_reg$D_IN, csrf_mcounteren_ir_reg$EN;

  // register csrf_mcounteren_tm_reg
  reg csrf_mcounteren_tm_reg;
  wire csrf_mcounteren_tm_reg$D_IN, csrf_mcounteren_tm_reg$EN;

  // register csrf_mcycle_ehr_data_rl
  reg [63 : 0] csrf_mcycle_ehr_data_rl;
  wire [63 : 0] csrf_mcycle_ehr_data_rl$D_IN;
  wire csrf_mcycle_ehr_data_rl$EN;

  // register csrf_medeleg_13_11_reg
  reg [2 : 0] csrf_medeleg_13_11_reg;
  wire [2 : 0] csrf_medeleg_13_11_reg$D_IN;
  wire csrf_medeleg_13_11_reg$EN;

  // register csrf_medeleg_15_reg
  reg csrf_medeleg_15_reg;
  wire csrf_medeleg_15_reg$D_IN, csrf_medeleg_15_reg$EN;

  // register csrf_medeleg_9_0_reg
  reg [9 : 0] csrf_medeleg_9_0_reg;
  wire [9 : 0] csrf_medeleg_9_0_reg$D_IN;
  wire csrf_medeleg_9_0_reg$EN;

  // register csrf_mepc_csr
  reg [63 : 0] csrf_mepc_csr;
  reg [63 : 0] csrf_mepc_csr$D_IN;
  wire csrf_mepc_csr$EN;

  // register csrf_mideleg_11_reg
  reg csrf_mideleg_11_reg;
  wire csrf_mideleg_11_reg$D_IN, csrf_mideleg_11_reg$EN;

  // register csrf_mideleg_1_0_reg
  reg [1 : 0] csrf_mideleg_1_0_reg;
  wire [1 : 0] csrf_mideleg_1_0_reg$D_IN;
  wire csrf_mideleg_1_0_reg$EN;

  // register csrf_mideleg_5_3_reg
  reg [2 : 0] csrf_mideleg_5_3_reg;
  wire [2 : 0] csrf_mideleg_5_3_reg$D_IN;
  wire csrf_mideleg_5_3_reg$EN;

  // register csrf_mideleg_9_7_reg
  reg [2 : 0] csrf_mideleg_9_7_reg;
  wire [2 : 0] csrf_mideleg_9_7_reg$D_IN;
  wire csrf_mideleg_9_7_reg$EN;

  // register csrf_minstret_ehr_data_rl
  reg [63 : 0] csrf_minstret_ehr_data_rl;
  wire [63 : 0] csrf_minstret_ehr_data_rl$D_IN;
  wire csrf_minstret_ehr_data_rl$EN;

  // register csrf_mpp_reg
  reg [1 : 0] csrf_mpp_reg;
  reg [1 : 0] csrf_mpp_reg$D_IN;
  wire csrf_mpp_reg$EN;

  // register csrf_mprv_reg
  reg csrf_mprv_reg;
  wire csrf_mprv_reg$D_IN, csrf_mprv_reg$EN;

  // register csrf_mscratch_csr
  reg [63 : 0] csrf_mscratch_csr;
  wire [63 : 0] csrf_mscratch_csr$D_IN;
  wire csrf_mscratch_csr$EN;

  // register csrf_mtval_csr
  reg [63 : 0] csrf_mtval_csr;
  reg [63 : 0] csrf_mtval_csr$D_IN;
  wire csrf_mtval_csr$EN;

  // register csrf_mtvec_base_hi_reg
  reg [61 : 0] csrf_mtvec_base_hi_reg;
  wire [61 : 0] csrf_mtvec_base_hi_reg$D_IN;
  wire csrf_mtvec_base_hi_reg$EN;

  // register csrf_mtvec_mode_low_reg
  reg csrf_mtvec_mode_low_reg;
  wire csrf_mtvec_mode_low_reg$D_IN, csrf_mtvec_mode_low_reg$EN;

  // register csrf_mxr_reg
  reg csrf_mxr_reg;
  wire csrf_mxr_reg$D_IN, csrf_mxr_reg$EN;

  // register csrf_ppn_reg
  reg [43 : 0] csrf_ppn_reg;
  wire [43 : 0] csrf_ppn_reg$D_IN;
  wire csrf_ppn_reg$EN;

  // register csrf_prev_ie_vec_0
  reg csrf_prev_ie_vec_0;
  wire csrf_prev_ie_vec_0$D_IN, csrf_prev_ie_vec_0$EN;

  // register csrf_prev_ie_vec_1
  reg csrf_prev_ie_vec_1;
  reg csrf_prev_ie_vec_1$D_IN;
  wire csrf_prev_ie_vec_1$EN;

  // register csrf_prev_ie_vec_3
  reg csrf_prev_ie_vec_3;
  reg csrf_prev_ie_vec_3$D_IN;
  wire csrf_prev_ie_vec_3$EN;

  // register csrf_prv_reg
  reg [1 : 0] csrf_prv_reg;
  reg [1 : 0] csrf_prv_reg$D_IN;
  wire csrf_prv_reg$EN;

  // register csrf_rg_dcsr
  reg [63 : 0] csrf_rg_dcsr;
  reg [63 : 0] csrf_rg_dcsr$D_IN;
  wire csrf_rg_dcsr$EN;

  // register csrf_rg_dpc
  reg [63 : 0] csrf_rg_dpc;
  reg [63 : 0] csrf_rg_dpc$D_IN;
  wire csrf_rg_dpc$EN;

  // register csrf_rg_dscratch0
  reg [63 : 0] csrf_rg_dscratch0;
  wire [63 : 0] csrf_rg_dscratch0$D_IN;
  wire csrf_rg_dscratch0$EN;

  // register csrf_rg_dscratch1
  reg [63 : 0] csrf_rg_dscratch1;
  wire [63 : 0] csrf_rg_dscratch1$D_IN;
  wire csrf_rg_dscratch1$EN;

  // register csrf_rg_tdata1_data
  reg [58 : 0] csrf_rg_tdata1_data;
  wire [58 : 0] csrf_rg_tdata1_data$D_IN;
  wire csrf_rg_tdata1_data$EN;

  // register csrf_rg_tdata1_dmode
  reg csrf_rg_tdata1_dmode;
  wire csrf_rg_tdata1_dmode$D_IN, csrf_rg_tdata1_dmode$EN;

  // register csrf_rg_tdata2
  reg [63 : 0] csrf_rg_tdata2;
  wire [63 : 0] csrf_rg_tdata2$D_IN;
  wire csrf_rg_tdata2$EN;

  // register csrf_rg_tdata3
  reg [63 : 0] csrf_rg_tdata3;
  wire [63 : 0] csrf_rg_tdata3$D_IN;
  wire csrf_rg_tdata3$EN;

  // register csrf_rg_tselect
  reg [63 : 0] csrf_rg_tselect;
  wire [63 : 0] csrf_rg_tselect$D_IN;
  wire csrf_rg_tselect$EN;

  // register csrf_scause_code_reg
  reg [3 : 0] csrf_scause_code_reg;
  reg [3 : 0] csrf_scause_code_reg$D_IN;
  wire csrf_scause_code_reg$EN;

  // register csrf_scause_interrupt_reg
  reg csrf_scause_interrupt_reg;
  reg csrf_scause_interrupt_reg$D_IN;
  wire csrf_scause_interrupt_reg$EN;

  // register csrf_scounteren_cy_reg
  reg csrf_scounteren_cy_reg;
  wire csrf_scounteren_cy_reg$D_IN, csrf_scounteren_cy_reg$EN;

  // register csrf_scounteren_ir_reg
  reg csrf_scounteren_ir_reg;
  wire csrf_scounteren_ir_reg$D_IN, csrf_scounteren_ir_reg$EN;

  // register csrf_scounteren_tm_reg
  reg csrf_scounteren_tm_reg;
  wire csrf_scounteren_tm_reg$D_IN, csrf_scounteren_tm_reg$EN;

  // register csrf_sepc_csr
  reg [63 : 0] csrf_sepc_csr;
  reg [63 : 0] csrf_sepc_csr$D_IN;
  wire csrf_sepc_csr$EN;

  // register csrf_software_int_en_vec_0
  reg csrf_software_int_en_vec_0;
  wire csrf_software_int_en_vec_0$D_IN, csrf_software_int_en_vec_0$EN;

  // register csrf_software_int_en_vec_1
  reg csrf_software_int_en_vec_1;
  wire csrf_software_int_en_vec_1$D_IN, csrf_software_int_en_vec_1$EN;

  // register csrf_software_int_en_vec_3
  reg csrf_software_int_en_vec_3;
  wire csrf_software_int_en_vec_3$D_IN, csrf_software_int_en_vec_3$EN;

  // register csrf_software_int_pend_vec_0
  reg csrf_software_int_pend_vec_0;
  wire csrf_software_int_pend_vec_0$D_IN, csrf_software_int_pend_vec_0$EN;

  // register csrf_software_int_pend_vec_1
  reg csrf_software_int_pend_vec_1;
  wire csrf_software_int_pend_vec_1$D_IN, csrf_software_int_pend_vec_1$EN;

  // register csrf_software_int_pend_vec_3
  reg csrf_software_int_pend_vec_3;
  wire csrf_software_int_pend_vec_3$D_IN, csrf_software_int_pend_vec_3$EN;

  // register csrf_spp_reg
  reg csrf_spp_reg;
  reg csrf_spp_reg$D_IN;
  wire csrf_spp_reg$EN;

  // register csrf_sscratch_csr
  reg [63 : 0] csrf_sscratch_csr;
  wire [63 : 0] csrf_sscratch_csr$D_IN;
  wire csrf_sscratch_csr$EN;

  // register csrf_stats_module_doStats
  reg csrf_stats_module_doStats;
  wire csrf_stats_module_doStats$D_IN, csrf_stats_module_doStats$EN;

  // register csrf_stval_csr
  reg [63 : 0] csrf_stval_csr;
  reg [63 : 0] csrf_stval_csr$D_IN;
  wire csrf_stval_csr$EN;

  // register csrf_stvec_base_hi_reg
  reg [61 : 0] csrf_stvec_base_hi_reg;
  wire [61 : 0] csrf_stvec_base_hi_reg$D_IN;
  wire csrf_stvec_base_hi_reg$EN;

  // register csrf_stvec_mode_low_reg
  reg csrf_stvec_mode_low_reg;
  wire csrf_stvec_mode_low_reg$D_IN, csrf_stvec_mode_low_reg$EN;

  // register csrf_sum_reg
  reg csrf_sum_reg;
  wire csrf_sum_reg$D_IN, csrf_sum_reg$EN;

  // register csrf_time_reg
  reg [63 : 0] csrf_time_reg;
  wire [63 : 0] csrf_time_reg$D_IN;
  wire csrf_time_reg$EN;

  // register csrf_timer_int_en_vec_0
  reg csrf_timer_int_en_vec_0;
  wire csrf_timer_int_en_vec_0$D_IN, csrf_timer_int_en_vec_0$EN;

  // register csrf_timer_int_en_vec_1
  reg csrf_timer_int_en_vec_1;
  wire csrf_timer_int_en_vec_1$D_IN, csrf_timer_int_en_vec_1$EN;

  // register csrf_timer_int_en_vec_3
  reg csrf_timer_int_en_vec_3;
  wire csrf_timer_int_en_vec_3$D_IN, csrf_timer_int_en_vec_3$EN;

  // register csrf_timer_int_pend_vec_0
  reg csrf_timer_int_pend_vec_0;
  wire csrf_timer_int_pend_vec_0$D_IN, csrf_timer_int_pend_vec_0$EN;

  // register csrf_timer_int_pend_vec_1
  reg csrf_timer_int_pend_vec_1;
  wire csrf_timer_int_pend_vec_1$D_IN, csrf_timer_int_pend_vec_1$EN;

  // register csrf_timer_int_pend_vec_3
  reg csrf_timer_int_pend_vec_3;
  wire csrf_timer_int_pend_vec_3$D_IN, csrf_timer_int_pend_vec_3$EN;

  // register csrf_tsr_reg
  reg csrf_tsr_reg;
  wire csrf_tsr_reg$D_IN, csrf_tsr_reg$EN;

  // register csrf_tvm_reg
  reg csrf_tvm_reg;
  wire csrf_tvm_reg$D_IN, csrf_tvm_reg$EN;

  // register csrf_tw_reg
  reg csrf_tw_reg;
  wire csrf_tw_reg$D_IN, csrf_tw_reg$EN;

  // register csrf_vm_mode_sv39_reg
  reg csrf_vm_mode_sv39_reg;
  wire csrf_vm_mode_sv39_reg$D_IN, csrf_vm_mode_sv39_reg$EN;

  // register flush_brpred
  reg flush_brpred;
  wire flush_brpred$D_IN, flush_brpred$EN;

  // register flush_caches
  reg flush_caches;
  wire flush_caches$D_IN, flush_caches$EN;

  // register flush_reservation
  reg flush_reservation;
  wire flush_reservation$D_IN, flush_reservation$EN;

  // register flush_tlbs
  reg flush_tlbs;
  wire flush_tlbs$D_IN, flush_tlbs$EN;

  // register mmio_cRqQ_clearReq_rl
  reg mmio_cRqQ_clearReq_rl;
  wire mmio_cRqQ_clearReq_rl$D_IN, mmio_cRqQ_clearReq_rl$EN;

  // register mmio_cRqQ_data_0
  reg [141 : 0] mmio_cRqQ_data_0;
  wire [141 : 0] mmio_cRqQ_data_0$D_IN;
  wire mmio_cRqQ_data_0$EN;

  // register mmio_cRqQ_deqReq_rl
  reg mmio_cRqQ_deqReq_rl;
  wire mmio_cRqQ_deqReq_rl$D_IN, mmio_cRqQ_deqReq_rl$EN;

  // register mmio_cRqQ_empty
  reg mmio_cRqQ_empty;
  wire mmio_cRqQ_empty$D_IN, mmio_cRqQ_empty$EN;

  // register mmio_cRqQ_enqReq_rl
  reg [142 : 0] mmio_cRqQ_enqReq_rl;
  wire [142 : 0] mmio_cRqQ_enqReq_rl$D_IN;
  wire mmio_cRqQ_enqReq_rl$EN;

  // register mmio_cRqQ_full
  reg mmio_cRqQ_full;
  wire mmio_cRqQ_full$D_IN, mmio_cRqQ_full$EN;

  // register mmio_cRsQ_clearReq_rl
  reg mmio_cRsQ_clearReq_rl;
  wire mmio_cRsQ_clearReq_rl$D_IN, mmio_cRsQ_clearReq_rl$EN;

  // register mmio_cRsQ_data_0
  reg mmio_cRsQ_data_0;
  wire mmio_cRsQ_data_0$D_IN, mmio_cRsQ_data_0$EN;

  // register mmio_cRsQ_deqReq_rl
  reg mmio_cRsQ_deqReq_rl;
  wire mmio_cRsQ_deqReq_rl$D_IN, mmio_cRsQ_deqReq_rl$EN;

  // register mmio_cRsQ_empty
  reg mmio_cRsQ_empty;
  wire mmio_cRsQ_empty$D_IN, mmio_cRsQ_empty$EN;

  // register mmio_cRsQ_enqReq_rl
  reg [1 : 0] mmio_cRsQ_enqReq_rl;
  wire [1 : 0] mmio_cRsQ_enqReq_rl$D_IN;
  wire mmio_cRsQ_enqReq_rl$EN;

  // register mmio_cRsQ_full
  reg mmio_cRsQ_full;
  wire mmio_cRsQ_full$D_IN, mmio_cRsQ_full$EN;

  // register mmio_dataPendQ_clearReq_rl
  reg mmio_dataPendQ_clearReq_rl;
  wire mmio_dataPendQ_clearReq_rl$D_IN, mmio_dataPendQ_clearReq_rl$EN;

  // register mmio_dataPendQ_deqReq_rl
  reg mmio_dataPendQ_deqReq_rl;
  wire mmio_dataPendQ_deqReq_rl$D_IN, mmio_dataPendQ_deqReq_rl$EN;

  // register mmio_dataPendQ_empty
  reg mmio_dataPendQ_empty;
  wire mmio_dataPendQ_empty$D_IN, mmio_dataPendQ_empty$EN;

  // register mmio_dataPendQ_enqReq_rl
  reg mmio_dataPendQ_enqReq_rl;
  wire mmio_dataPendQ_enqReq_rl$D_IN, mmio_dataPendQ_enqReq_rl$EN;

  // register mmio_dataPendQ_full
  reg mmio_dataPendQ_full;
  wire mmio_dataPendQ_full$D_IN, mmio_dataPendQ_full$EN;

  // register mmio_dataReqQ_clearReq_rl
  reg mmio_dataReqQ_clearReq_rl;
  wire mmio_dataReqQ_clearReq_rl$D_IN, mmio_dataReqQ_clearReq_rl$EN;

  // register mmio_dataReqQ_data_0
  reg [141 : 0] mmio_dataReqQ_data_0;
  wire [141 : 0] mmio_dataReqQ_data_0$D_IN;
  wire mmio_dataReqQ_data_0$EN;

  // register mmio_dataReqQ_deqReq_rl
  reg mmio_dataReqQ_deqReq_rl;
  wire mmio_dataReqQ_deqReq_rl$D_IN, mmio_dataReqQ_deqReq_rl$EN;

  // register mmio_dataReqQ_empty
  reg mmio_dataReqQ_empty;
  wire mmio_dataReqQ_empty$D_IN, mmio_dataReqQ_empty$EN;

  // register mmio_dataReqQ_enqReq_rl
  reg [142 : 0] mmio_dataReqQ_enqReq_rl;
  wire [142 : 0] mmio_dataReqQ_enqReq_rl$D_IN;
  wire mmio_dataReqQ_enqReq_rl$EN;

  // register mmio_dataReqQ_full
  reg mmio_dataReqQ_full;
  wire mmio_dataReqQ_full$D_IN, mmio_dataReqQ_full$EN;

  // register mmio_dataRespQ_clearReq_rl
  reg mmio_dataRespQ_clearReq_rl;
  wire mmio_dataRespQ_clearReq_rl$D_IN, mmio_dataRespQ_clearReq_rl$EN;

  // register mmio_dataRespQ_data_0
  reg [64 : 0] mmio_dataRespQ_data_0;
  wire [64 : 0] mmio_dataRespQ_data_0$D_IN;
  wire mmio_dataRespQ_data_0$EN;

  // register mmio_dataRespQ_deqReq_rl
  reg mmio_dataRespQ_deqReq_rl;
  wire mmio_dataRespQ_deqReq_rl$D_IN, mmio_dataRespQ_deqReq_rl$EN;

  // register mmio_dataRespQ_empty
  reg mmio_dataRespQ_empty;
  wire mmio_dataRespQ_empty$D_IN, mmio_dataRespQ_empty$EN;

  // register mmio_dataRespQ_enqReq_rl
  reg [65 : 0] mmio_dataRespQ_enqReq_rl;
  wire [65 : 0] mmio_dataRespQ_enqReq_rl$D_IN;
  wire mmio_dataRespQ_enqReq_rl$EN;

  // register mmio_dataRespQ_full
  reg mmio_dataRespQ_full;
  wire mmio_dataRespQ_full$D_IN, mmio_dataRespQ_full$EN;

  // register mmio_fromHostAddr
  reg [60 : 0] mmio_fromHostAddr;
  wire [60 : 0] mmio_fromHostAddr$D_IN;
  wire mmio_fromHostAddr$EN;

  // register mmio_pRqQ_clearReq_rl
  reg mmio_pRqQ_clearReq_rl;
  wire mmio_pRqQ_clearReq_rl$D_IN, mmio_pRqQ_clearReq_rl$EN;

  // register mmio_pRqQ_data_0
  reg [38 : 0] mmio_pRqQ_data_0;
  wire [38 : 0] mmio_pRqQ_data_0$D_IN;
  wire mmio_pRqQ_data_0$EN;

  // register mmio_pRqQ_deqReq_rl
  reg mmio_pRqQ_deqReq_rl;
  wire mmio_pRqQ_deqReq_rl$D_IN, mmio_pRqQ_deqReq_rl$EN;

  // register mmio_pRqQ_empty
  reg mmio_pRqQ_empty;
  wire mmio_pRqQ_empty$D_IN, mmio_pRqQ_empty$EN;

  // register mmio_pRqQ_enqReq_rl
  reg [39 : 0] mmio_pRqQ_enqReq_rl;
  wire [39 : 0] mmio_pRqQ_enqReq_rl$D_IN;
  wire mmio_pRqQ_enqReq_rl$EN;

  // register mmio_pRqQ_full
  reg mmio_pRqQ_full;
  wire mmio_pRqQ_full$D_IN, mmio_pRqQ_full$EN;

  // register mmio_pRsQ_clearReq_rl
  reg mmio_pRsQ_clearReq_rl;
  wire mmio_pRsQ_clearReq_rl$D_IN, mmio_pRsQ_clearReq_rl$EN;

  // register mmio_pRsQ_data_0
  reg [66 : 0] mmio_pRsQ_data_0;
  wire [66 : 0] mmio_pRsQ_data_0$D_IN;
  wire mmio_pRsQ_data_0$EN;

  // register mmio_pRsQ_deqReq_rl
  reg mmio_pRsQ_deqReq_rl;
  wire mmio_pRsQ_deqReq_rl$D_IN, mmio_pRsQ_deqReq_rl$EN;

  // register mmio_pRsQ_empty
  reg mmio_pRsQ_empty;
  wire mmio_pRsQ_empty$D_IN, mmio_pRsQ_empty$EN;

  // register mmio_pRsQ_enqReq_rl
  reg [67 : 0] mmio_pRsQ_enqReq_rl;
  wire [67 : 0] mmio_pRsQ_enqReq_rl$D_IN;
  wire mmio_pRsQ_enqReq_rl$EN;

  // register mmio_pRsQ_full
  reg mmio_pRsQ_full;
  wire mmio_pRsQ_full$D_IN, mmio_pRsQ_full$EN;

  // register mmio_toHostAddr
  reg [60 : 0] mmio_toHostAddr;
  wire [60 : 0] mmio_toHostAddr$D_IN;
  wire mmio_toHostAddr$EN;

  // register outOfReset
  reg outOfReset;
  wire outOfReset$D_IN, outOfReset$EN;

  // register renameStage_rg_m_halt_req
  reg [4 : 0] renameStage_rg_m_halt_req;
  reg [4 : 0] renameStage_rg_m_halt_req$D_IN;
  wire renameStage_rg_m_halt_req$EN;

  // register rg_core_run_state
  reg [1 : 0] rg_core_run_state;
  reg [1 : 0] rg_core_run_state$D_IN;
  wire rg_core_run_state$EN;

  // register started
  reg started;
  wire started$D_IN, started$EN;

  // register update_vm_info
  reg update_vm_info;
  wire update_vm_info$D_IN, update_vm_info$EN;

  // ports of submodule commitStage_f_rob_data
  wire [425 : 0] commitStage_f_rob_data$D_IN, commitStage_f_rob_data$D_OUT;
  wire commitStage_f_rob_data$CLR,
       commitStage_f_rob_data$DEQ,
       commitStage_f_rob_data$EMPTY_N,
       commitStage_f_rob_data$ENQ,
       commitStage_f_rob_data$FULL_N;

  // ports of submodule coreFix_aluExe_0_dispToRegQ
  reg [3 : 0] coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [157 : 0] coreFix_aluExe_0_dispToRegQ$enq_x,
		 coreFix_aluExe_0_dispToRegQ$first;
  wire [11 : 0] coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask;
  wire coreFix_aluExe_0_dispToRegQ$EN_deq,
       coreFix_aluExe_0_dispToRegQ$EN_enq,
       coreFix_aluExe_0_dispToRegQ$EN_specUpdate_correctSpeculation,
       coreFix_aluExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation,
       coreFix_aluExe_0_dispToRegQ$RDY_deq,
       coreFix_aluExe_0_dispToRegQ$RDY_enq,
       coreFix_aluExe_0_dispToRegQ$RDY_first,
       coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_aluExe_0_exeToFinQ
  reg [3 : 0] coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [326 : 0] coreFix_aluExe_0_exeToFinQ$enq_x,
		 coreFix_aluExe_0_exeToFinQ$first;
  wire [11 : 0] coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask;
  wire coreFix_aluExe_0_exeToFinQ$EN_deq,
       coreFix_aluExe_0_exeToFinQ$EN_enq,
       coreFix_aluExe_0_exeToFinQ$EN_specUpdate_correctSpeculation,
       coreFix_aluExe_0_exeToFinQ$EN_specUpdate_incorrectSpeculation,
       coreFix_aluExe_0_exeToFinQ$RDY_deq,
       coreFix_aluExe_0_exeToFinQ$RDY_enq,
       coreFix_aluExe_0_exeToFinQ$RDY_first,
       coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_aluExe_0_regToExeQ
  reg [3 : 0] coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [421 : 0] coreFix_aluExe_0_regToExeQ$enq_x,
		 coreFix_aluExe_0_regToExeQ$first;
  wire [11 : 0] coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask;
  wire coreFix_aluExe_0_regToExeQ$EN_deq,
       coreFix_aluExe_0_regToExeQ$EN_enq,
       coreFix_aluExe_0_regToExeQ$EN_specUpdate_correctSpeculation,
       coreFix_aluExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation,
       coreFix_aluExe_0_regToExeQ$RDY_deq,
       coreFix_aluExe_0_regToExeQ$RDY_enq,
       coreFix_aluExe_0_regToExeQ$RDY_first,
       coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_aluExe_0_rsAlu
  reg [7 : 0] coreFix_aluExe_0_rsAlu$setRegReady_2_put,
	      coreFix_aluExe_0_rsAlu$setRegReady_4_put;
  reg [3 : 0] coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag;
  wire [161 : 0] coreFix_aluExe_0_rsAlu$dispatchData,
		 coreFix_aluExe_0_rsAlu$enq_x;
  wire [11 : 0] coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask;
  wire [7 : 0] coreFix_aluExe_0_rsAlu$setRegReady_0_put,
	       coreFix_aluExe_0_rsAlu$setRegReady_1_put,
	       coreFix_aluExe_0_rsAlu$setRegReady_3_put;
  wire [5 : 0] coreFix_aluExe_0_rsAlu$setRobEnqTime_t;
  wire [4 : 0] coreFix_aluExe_0_rsAlu$approximateCount;
  wire coreFix_aluExe_0_rsAlu$EN_doDispatch,
       coreFix_aluExe_0_rsAlu$EN_enq,
       coreFix_aluExe_0_rsAlu$EN_setRegReady_0_put,
       coreFix_aluExe_0_rsAlu$EN_setRegReady_1_put,
       coreFix_aluExe_0_rsAlu$EN_setRegReady_2_put,
       coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put,
       coreFix_aluExe_0_rsAlu$EN_setRegReady_4_put,
       coreFix_aluExe_0_rsAlu$EN_setRobEnqTime,
       coreFix_aluExe_0_rsAlu$EN_specUpdate_correctSpeculation,
       coreFix_aluExe_0_rsAlu$EN_specUpdate_incorrectSpeculation,
       coreFix_aluExe_0_rsAlu$RDY_dispatchData,
       coreFix_aluExe_0_rsAlu$RDY_doDispatch,
       coreFix_aluExe_0_rsAlu$RDY_enq,
       coreFix_aluExe_0_rsAlu$canEnq,
       coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_aluExe_1_dispToRegQ
  reg [3 : 0] coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [157 : 0] coreFix_aluExe_1_dispToRegQ$enq_x,
		 coreFix_aluExe_1_dispToRegQ$first;
  wire [11 : 0] coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask;
  wire coreFix_aluExe_1_dispToRegQ$EN_deq,
       coreFix_aluExe_1_dispToRegQ$EN_enq,
       coreFix_aluExe_1_dispToRegQ$EN_specUpdate_correctSpeculation,
       coreFix_aluExe_1_dispToRegQ$EN_specUpdate_incorrectSpeculation,
       coreFix_aluExe_1_dispToRegQ$RDY_deq,
       coreFix_aluExe_1_dispToRegQ$RDY_enq,
       coreFix_aluExe_1_dispToRegQ$RDY_first,
       coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_aluExe_1_exeToFinQ
  reg [3 : 0] coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [326 : 0] coreFix_aluExe_1_exeToFinQ$enq_x,
		 coreFix_aluExe_1_exeToFinQ$first;
  wire [11 : 0] coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask;
  wire coreFix_aluExe_1_exeToFinQ$EN_deq,
       coreFix_aluExe_1_exeToFinQ$EN_enq,
       coreFix_aluExe_1_exeToFinQ$EN_specUpdate_correctSpeculation,
       coreFix_aluExe_1_exeToFinQ$EN_specUpdate_incorrectSpeculation,
       coreFix_aluExe_1_exeToFinQ$RDY_deq,
       coreFix_aluExe_1_exeToFinQ$RDY_enq,
       coreFix_aluExe_1_exeToFinQ$RDY_first,
       coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_aluExe_1_regToExeQ
  reg [3 : 0] coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [421 : 0] coreFix_aluExe_1_regToExeQ$enq_x,
		 coreFix_aluExe_1_regToExeQ$first;
  wire [11 : 0] coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask;
  wire coreFix_aluExe_1_regToExeQ$EN_deq,
       coreFix_aluExe_1_regToExeQ$EN_enq,
       coreFix_aluExe_1_regToExeQ$EN_specUpdate_correctSpeculation,
       coreFix_aluExe_1_regToExeQ$EN_specUpdate_incorrectSpeculation,
       coreFix_aluExe_1_regToExeQ$RDY_deq,
       coreFix_aluExe_1_regToExeQ$RDY_enq,
       coreFix_aluExe_1_regToExeQ$RDY_first,
       coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_aluExe_1_rsAlu
  reg [7 : 0] coreFix_aluExe_1_rsAlu$setRegReady_2_put,
	      coreFix_aluExe_1_rsAlu$setRegReady_4_put;
  reg [3 : 0] coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag;
  wire [161 : 0] coreFix_aluExe_1_rsAlu$dispatchData,
		 coreFix_aluExe_1_rsAlu$enq_x;
  wire [11 : 0] coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask;
  wire [7 : 0] coreFix_aluExe_1_rsAlu$setRegReady_0_put,
	       coreFix_aluExe_1_rsAlu$setRegReady_1_put,
	       coreFix_aluExe_1_rsAlu$setRegReady_3_put;
  wire [5 : 0] coreFix_aluExe_1_rsAlu$setRobEnqTime_t;
  wire [4 : 0] coreFix_aluExe_1_rsAlu$approximateCount;
  wire coreFix_aluExe_1_rsAlu$EN_doDispatch,
       coreFix_aluExe_1_rsAlu$EN_enq,
       coreFix_aluExe_1_rsAlu$EN_setRegReady_0_put,
       coreFix_aluExe_1_rsAlu$EN_setRegReady_1_put,
       coreFix_aluExe_1_rsAlu$EN_setRegReady_2_put,
       coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put,
       coreFix_aluExe_1_rsAlu$EN_setRegReady_4_put,
       coreFix_aluExe_1_rsAlu$EN_setRobEnqTime,
       coreFix_aluExe_1_rsAlu$EN_specUpdate_correctSpeculation,
       coreFix_aluExe_1_rsAlu$EN_specUpdate_incorrectSpeculation,
       coreFix_aluExe_1_rsAlu$RDY_dispatchData,
       coreFix_aluExe_1_rsAlu$RDY_doDispatch,
       coreFix_aluExe_1_rsAlu$RDY_enq,
       coreFix_aluExe_1_rsAlu$canEnq,
       coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_fpuMulDivExe_0_dispToRegQ
  reg [3 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [77 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$enq_x,
		coreFix_fpuMulDivExe_0_dispToRegQ$first;
  wire [11 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask;
  wire coreFix_fpuMulDivExe_0_dispToRegQ$EN_deq,
       coreFix_fpuMulDivExe_0_dispToRegQ$EN_enq,
       coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_correctSpeculation,
       coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation,
       coreFix_fpuMulDivExe_0_dispToRegQ$RDY_deq,
       coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq,
       coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first,
       coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_fpuMulDivExe_0_fpuExec_divQ
  reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [42 : 0] coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x,
		coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data;
  wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask;
  wire coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_deq,
       coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_enq,
       coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_correctSpeculation,
       coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_incorrectSpeculation,
       coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq,
       coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq,
       coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_data,
       coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned,
       coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned,
       coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_fpuMulDivExe_0_fpuExec_double_div
  wire [130 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_div$request_put;
  wire [68 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get;
  wire coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_request_put,
       coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_response_get,
       coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put,
       coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get;

  // ports of submodule coreFix_fpuMulDivExe_0_fpuExec_double_fma
  wire [195 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put;
  wire [68 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get;
  wire coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put,
       coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_response_get,
       coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put,
       coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get;

  // ports of submodule coreFix_fpuMulDivExe_0_fpuExec_double_sqrt
  wire [68 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get;
  wire [66 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$request_put;
  wire coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_request_put,
       coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_response_get,
       coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put,
       coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get;

  // ports of submodule coreFix_fpuMulDivExe_0_fpuExec_fmaQ
  reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [42 : 0] coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x,
		coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data;
  wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask;
  wire coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_deq,
       coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_enq,
       coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_correctSpeculation,
       coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_incorrectSpeculation,
       coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq,
       coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq,
       coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_data,
       coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned,
       coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned,
       coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_fpuMulDivExe_0_fpuExec_simpleQ
  reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [101 : 0] coreFix_fpuMulDivExe_0_fpuExec_simpleQ$enq_x,
		 coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first;
  wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask;
  wire coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_deq,
       coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_enq,
       coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_correctSpeculation,
       coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_incorrectSpeculation,
       coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_deq,
       coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq,
       coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_first,
       coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_fpuMulDivExe_0_fpuExec_sqrtQ
  reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [42 : 0] coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x,
		coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data;
  wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask;
  wire coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_deq,
       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_enq,
       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_correctSpeculation,
       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_incorrectSpeculation,
       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq,
       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq,
       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_data,
       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned,
       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned,
       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divQ
  reg [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [35 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divQ$enq_x,
		coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data;
  wire [11 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask;
  wire coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_deq,
       coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_enq,
       coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_correctSpeculation,
       coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_incorrectSpeculation,
       coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq,
       coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq,
       coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_data,
       coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned,
       coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned,
       coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc
  wire [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata;
  wire [75 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser,
		coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser;
  wire [63 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata,
		coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata;
  wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tready,
       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid,
       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tready,
       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid,
       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tready,
       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tvalid;

  // ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg
  wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY;

  // ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulQ
  reg [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [35 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulQ$enq_x,
		coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data;
  wire [11 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask;
  wire coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_deq,
       coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_enq,
       coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_correctSpeculation,
       coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_incorrectSpeculation,
       coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq,
       coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq,
       coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_data,
       coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned,
       coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned,
       coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned
  wire [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$P;
  wire [63 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A,
		coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B;

  // ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned
  wire [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$P;
  wire [63 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A,
		coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B;

  // ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned
  wire [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$P;
  wire [63 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A,
		coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B;

  // ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ
  reg [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN;
  wire [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT;
  wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$CLR,
       coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$DEQ,
       coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N,
       coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$ENQ;

  // ports of submodule coreFix_fpuMulDivExe_0_regToExeQ
  reg [3 : 0] coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [245 : 0] coreFix_fpuMulDivExe_0_regToExeQ$enq_x,
		 coreFix_fpuMulDivExe_0_regToExeQ$first;
  wire [11 : 0] coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask;
  wire coreFix_fpuMulDivExe_0_regToExeQ$EN_deq,
       coreFix_fpuMulDivExe_0_regToExeQ$EN_enq,
       coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_correctSpeculation,
       coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation,
       coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq,
       coreFix_fpuMulDivExe_0_regToExeQ$RDY_enq,
       coreFix_fpuMulDivExe_0_regToExeQ$RDY_first,
       coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv
  reg [7 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put,
	      coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put;
  reg [3 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag;
  wire [86 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData,
		coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x;
  wire [11 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask;
  wire [7 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_0_put,
	       coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_1_put,
	       coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_3_put;
  wire [5 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t;
  wire coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_0_put,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_1_put,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_2_put,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_4_put,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_correctSpeculation,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_incorrectSpeculation,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr
  reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n;
  wire [512 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d,
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData;
  wire [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r,
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq,
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq,
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq,
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq;
  wire [63 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain_addr;
  wire [57 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot,
		coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot,
		coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot,
		coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_slot;
  wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_succ;
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_state,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_n;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_cRqTransfer_getEmptyEntryInit,
       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_releaseEntry,
       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setData,
       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setStateSlot,
       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setSucc,
       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_sendRsToP_cRq_setWaitSt_setSlot_clearData,
       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_stuck_get,
       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_cRqTransfer_getEmptyEntryInit,
       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN,
       coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN,
       coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr
  wire [512 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d,
		 coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData;
  wire [65 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r,
		coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq,
		coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq;
  wire [1 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit,
	       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n,
	       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n,
	       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_releaseEntry_n,
	       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_n,
	       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData_n,
	       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq_n,
	       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_releaseEntry_n;
  wire coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_getEmptyEntryInit,
       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_releaseEntry,
       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_setDone_setData,
       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_sendRsToP_pRq_releaseEntry,
       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_stuck_get,
       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit,
       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_pipelineResp_releaseEntry,
       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_pipeline
  reg [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r;
  reg [569 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam;
  reg [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq;
  reg coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep;
  wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$first;
  wire coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_deqWrite,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_send,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_IN,
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$CLR,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$DEQ,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$EMPTY_N,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$ENQ,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_IN,
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_OUT;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$CLR,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$DEQ,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$EMPTY_N,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$ENQ,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_IN,
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_OUT;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$CLR,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$DEQ,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$EMPTY_N,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$ENQ,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$FULL_N;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ
  wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_IN,
	       coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT;
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$CLR,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$DEQ,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$ENQ,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0
  wire coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1
  wire coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN,
       coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0
  wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1
  wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2
  wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN,
       coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN,
       coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0
  wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1
  wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2
  wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN,
       coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN,
       coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dTlb
  reg [3 : 0] coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag;
  wire [246 : 0] coreFix_memExe_dTlb$procResp;
  wire [177 : 0] coreFix_memExe_dTlb$procReq_req;
  wire [82 : 0] coreFix_memExe_dTlb$toParent_ldTransRsFromP_enq_x;
  wire [48 : 0] coreFix_memExe_dTlb$updateVMInfo_vm;
  wire [28 : 0] coreFix_memExe_dTlb$toParent_rqToP_first;
  wire [11 : 0] coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask;
  wire [2 : 0] coreFix_memExe_dTlb$perf_req_r;
  wire coreFix_memExe_dTlb$EN_deqProcResp,
       coreFix_memExe_dTlb$EN_flush,
       coreFix_memExe_dTlb$EN_perf_req,
       coreFix_memExe_dTlb$EN_perf_resp,
       coreFix_memExe_dTlb$EN_perf_setStatus,
       coreFix_memExe_dTlb$EN_procReq,
       coreFix_memExe_dTlb$EN_specUpdate_correctSpeculation,
       coreFix_memExe_dTlb$EN_specUpdate_incorrectSpeculation,
       coreFix_memExe_dTlb$EN_toParent_flush_request_get,
       coreFix_memExe_dTlb$EN_toParent_flush_response_put,
       coreFix_memExe_dTlb$EN_toParent_ldTransRsFromP_enq,
       coreFix_memExe_dTlb$EN_toParent_rqToP_deq,
       coreFix_memExe_dTlb$EN_updateVMInfo,
       coreFix_memExe_dTlb$RDY_deqProcResp,
       coreFix_memExe_dTlb$RDY_flush,
       coreFix_memExe_dTlb$RDY_procReq,
       coreFix_memExe_dTlb$RDY_procResp,
       coreFix_memExe_dTlb$RDY_toParent_flush_request_get,
       coreFix_memExe_dTlb$RDY_toParent_flush_response_put,
       coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq,
       coreFix_memExe_dTlb$RDY_toParent_rqToP_deq,
       coreFix_memExe_dTlb$RDY_toParent_rqToP_first,
       coreFix_memExe_dTlb$flush_done,
       coreFix_memExe_dTlb$noPendingReq,
       coreFix_memExe_dTlb$perf_setStatus_doStats,
       coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_memExe_dispToRegQ
  reg [3 : 0] coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [97 : 0] coreFix_memExe_dispToRegQ$enq_x,
		coreFix_memExe_dispToRegQ$first;
  wire [11 : 0] coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask;
  wire coreFix_memExe_dispToRegQ$EN_deq,
       coreFix_memExe_dispToRegQ$EN_enq,
       coreFix_memExe_dispToRegQ$EN_specUpdate_correctSpeculation,
       coreFix_memExe_dispToRegQ$EN_specUpdate_incorrectSpeculation,
       coreFix_memExe_dispToRegQ$RDY_deq,
       coreFix_memExe_dispToRegQ$RDY_enq,
       coreFix_memExe_dispToRegQ$RDY_first,
       coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_memExe_forwardQ_clearReq_dummy2_0
  wire coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN,
       coreFix_memExe_forwardQ_clearReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_forwardQ_clearReq_dummy2_1
  wire coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN,
       coreFix_memExe_forwardQ_clearReq_dummy2_1$EN,
       coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_0
  wire coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN,
       coreFix_memExe_forwardQ_deqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_1
  wire coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN,
       coreFix_memExe_forwardQ_deqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_2
  wire coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN,
       coreFix_memExe_forwardQ_deqReq_dummy2_2$EN,
       coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_0
  wire coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN,
       coreFix_memExe_forwardQ_enqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_1
  wire coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN,
       coreFix_memExe_forwardQ_enqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_2
  wire coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN,
       coreFix_memExe_forwardQ_enqReq_dummy2_2$EN,
       coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_lsq
  reg [3 : 0] coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag;
  wire [170 : 0] coreFix_memExe_lsq$firstSt;
  wire [113 : 0] coreFix_memExe_lsq$firstLd;
  wire [85 : 0] coreFix_memExe_lsq$respLd;
  wire [76 : 0] coreFix_memExe_lsq$getIssueLd;
  wire [74 : 0] coreFix_memExe_lsq$issueLd;
  wire [67 : 0] coreFix_memExe_lsq$issueLd_sbRes;
  wire [63 : 0] coreFix_memExe_lsq$issueLd_paddr,
		coreFix_memExe_lsq$respLd_alignedData,
		coreFix_memExe_lsq$updateAddr_paddr,
		coreFix_memExe_lsq$updateData_d;
  wire [17 : 0] coreFix_memExe_lsq$enqLd_mem_inst,
		coreFix_memExe_lsq$enqSt_mem_inst;
  wire [11 : 0] coreFix_memExe_lsq$enqLd_inst_tag,
		coreFix_memExe_lsq$enqLd_spec_bits,
		coreFix_memExe_lsq$enqSt_inst_tag,
		coreFix_memExe_lsq$enqSt_spec_bits,
		coreFix_memExe_lsq$specUpdate_correctSpeculation_mask;
  wire [9 : 0] coreFix_memExe_lsq$getHit;
  wire [8 : 0] coreFix_memExe_lsq$enqLd_dst, coreFix_memExe_lsq$enqSt_dst;
  wire [7 : 0] coreFix_memExe_lsq$getOrigBE,
	       coreFix_memExe_lsq$issueLd_shiftedBE,
	       coreFix_memExe_lsq$updateAddr_shiftedBE;
  wire [6 : 0] coreFix_memExe_lsq$enqLdTag, coreFix_memExe_lsq$enqStTag;
  wire [5 : 0] coreFix_memExe_lsq$getHit_t,
	       coreFix_memExe_lsq$getOrigBE_t,
	       coreFix_memExe_lsq$setAtCommit_0_put,
	       coreFix_memExe_lsq$setAtCommit_1_put,
	       coreFix_memExe_lsq$updateAddr_lsqTag;
  wire [4 : 0] coreFix_memExe_lsq$issueLd_lsqTag,
	       coreFix_memExe_lsq$respLd_t,
	       coreFix_memExe_lsq$updateAddr_fault;
  wire [3 : 0] coreFix_memExe_lsq$updateData_t;
  wire [1 : 0] coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx;
  wire coreFix_memExe_lsq$EN_deqLd,
       coreFix_memExe_lsq$EN_deqSt,
       coreFix_memExe_lsq$EN_enqLd,
       coreFix_memExe_lsq$EN_enqSt,
       coreFix_memExe_lsq$EN_getHit,
       coreFix_memExe_lsq$EN_getIssueLd,
       coreFix_memExe_lsq$EN_issueLd,
       coreFix_memExe_lsq$EN_respLd,
       coreFix_memExe_lsq$EN_setAtCommit_0_put,
       coreFix_memExe_lsq$EN_setAtCommit_1_put,
       coreFix_memExe_lsq$EN_specUpdate_correctSpeculation,
       coreFix_memExe_lsq$EN_specUpdate_incorrectSpeculation,
       coreFix_memExe_lsq$EN_updateAddr,
       coreFix_memExe_lsq$EN_updateData,
       coreFix_memExe_lsq$EN_wakeupLdStalledBySB,
       coreFix_memExe_lsq$RDY_deqLd,
       coreFix_memExe_lsq$RDY_deqSt,
       coreFix_memExe_lsq$RDY_enqLd,
       coreFix_memExe_lsq$RDY_enqSt,
       coreFix_memExe_lsq$RDY_firstLd,
       coreFix_memExe_lsq$RDY_firstSt,
       coreFix_memExe_lsq$RDY_getIssueLd,
       coreFix_memExe_lsq$noWrongPathLoads,
       coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all,
       coreFix_memExe_lsq$stqEmpty,
       coreFix_memExe_lsq$updateAddr,
       coreFix_memExe_lsq$updateAddr_isMMIO;

  // ports of submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0
  wire coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN,
       coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1
  wire coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN,
       coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN,
       coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0
  wire coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN,
       coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1
  wire coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN,
       coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2
  wire coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN,
       coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN,
       coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0
  wire coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN,
       coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1
  wire coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN,
       coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2
  wire coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN,
       coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN,
       coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_regToExeQ
  reg [3 : 0] coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [192 : 0] coreFix_memExe_regToExeQ$enq_x,
		 coreFix_memExe_regToExeQ$first;
  wire [11 : 0] coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask;
  wire coreFix_memExe_regToExeQ$EN_deq,
       coreFix_memExe_regToExeQ$EN_enq,
       coreFix_memExe_regToExeQ$EN_specUpdate_correctSpeculation,
       coreFix_memExe_regToExeQ$EN_specUpdate_incorrectSpeculation,
       coreFix_memExe_regToExeQ$RDY_deq,
       coreFix_memExe_regToExeQ$RDY_enq,
       coreFix_memExe_regToExeQ$RDY_first,
       coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_memExe_reqLdQ_data_0_dummy2_0
  wire coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN,
       coreFix_memExe_reqLdQ_data_0_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqLdQ_data_0_dummy2_1
  wire coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN,
       coreFix_memExe_reqLdQ_data_0_dummy2_1$EN,
       coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_reqLdQ_deqP_dummy2_0
  wire coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN,
       coreFix_memExe_reqLdQ_deqP_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqLdQ_deqP_dummy2_1
  wire coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN,
       coreFix_memExe_reqLdQ_deqP_dummy2_1$EN;

  // ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_0
  wire coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN,
       coreFix_memExe_reqLdQ_empty_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_1
  wire coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN,
       coreFix_memExe_reqLdQ_empty_dummy2_1$EN,
       coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_2
  wire coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN,
       coreFix_memExe_reqLdQ_empty_dummy2_2$EN,
       coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_reqLdQ_enqP_dummy2_0
  wire coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN,
       coreFix_memExe_reqLdQ_enqP_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqLdQ_enqP_dummy2_1
  wire coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN,
       coreFix_memExe_reqLdQ_enqP_dummy2_1$EN;

  // ports of submodule coreFix_memExe_reqLdQ_full_dummy2_0
  wire coreFix_memExe_reqLdQ_full_dummy2_0$D_IN,
       coreFix_memExe_reqLdQ_full_dummy2_0$EN,
       coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT;

  // ports of submodule coreFix_memExe_reqLdQ_full_dummy2_1
  wire coreFix_memExe_reqLdQ_full_dummy2_1$D_IN,
       coreFix_memExe_reqLdQ_full_dummy2_1$EN,
       coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_reqLdQ_full_dummy2_2
  wire coreFix_memExe_reqLdQ_full_dummy2_2$D_IN,
       coreFix_memExe_reqLdQ_full_dummy2_2$EN,
       coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0
  wire coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1
  wire coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0
  wire coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN,
       coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1
  wire coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN,
       coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0
  wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN,
       coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1
  wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN,
       coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN,
       coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2
  wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN,
       coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN,
       coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0
  wire coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN,
       coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1
  wire coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN,
       coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0
  wire coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN,
       coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN,
       coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1
  wire coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN,
       coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN,
       coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2
  wire coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN,
       coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN,
       coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_reqStQ_data_0_dummy2_0
  wire coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN,
       coreFix_memExe_reqStQ_data_0_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqStQ_data_0_dummy2_1
  wire coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN,
       coreFix_memExe_reqStQ_data_0_dummy2_1$EN,
       coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_reqStQ_deqP_dummy2_0
  wire coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN,
       coreFix_memExe_reqStQ_deqP_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqStQ_deqP_dummy2_1
  wire coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN,
       coreFix_memExe_reqStQ_deqP_dummy2_1$EN;

  // ports of submodule coreFix_memExe_reqStQ_empty_dummy2_0
  wire coreFix_memExe_reqStQ_empty_dummy2_0$D_IN,
       coreFix_memExe_reqStQ_empty_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqStQ_empty_dummy2_1
  wire coreFix_memExe_reqStQ_empty_dummy2_1$D_IN,
       coreFix_memExe_reqStQ_empty_dummy2_1$EN,
       coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_reqStQ_empty_dummy2_2
  wire coreFix_memExe_reqStQ_empty_dummy2_2$D_IN,
       coreFix_memExe_reqStQ_empty_dummy2_2$EN,
       coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_reqStQ_enqP_dummy2_0
  wire coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN,
       coreFix_memExe_reqStQ_enqP_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqStQ_enqP_dummy2_1
  wire coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN,
       coreFix_memExe_reqStQ_enqP_dummy2_1$EN;

  // ports of submodule coreFix_memExe_reqStQ_full_dummy2_0
  wire coreFix_memExe_reqStQ_full_dummy2_0$D_IN,
       coreFix_memExe_reqStQ_full_dummy2_0$EN,
       coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT;

  // ports of submodule coreFix_memExe_reqStQ_full_dummy2_1
  wire coreFix_memExe_reqStQ_full_dummy2_1$D_IN,
       coreFix_memExe_reqStQ_full_dummy2_1$EN,
       coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_reqStQ_full_dummy2_2
  wire coreFix_memExe_reqStQ_full_dummy2_2$D_IN,
       coreFix_memExe_reqStQ_full_dummy2_2$EN,
       coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0
  wire coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN,
       coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1
  wire coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN,
       coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN,
       coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0
  wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN,
       coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1
  wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN,
       coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2
  wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN,
       coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN,
       coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0
  wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN,
       coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1
  wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN,
       coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2
  wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN,
       coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN,
       coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_rsMem
  reg [7 : 0] coreFix_memExe_rsMem$setRegReady_2_put,
	      coreFix_memExe_rsMem$setRegReady_4_put;
  reg [3 : 0] coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag;
  wire [106 : 0] coreFix_memExe_rsMem$dispatchData,
		 coreFix_memExe_rsMem$enq_x;
  wire [11 : 0] coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask;
  wire [7 : 0] coreFix_memExe_rsMem$setRegReady_0_put,
	       coreFix_memExe_rsMem$setRegReady_1_put,
	       coreFix_memExe_rsMem$setRegReady_3_put;
  wire [5 : 0] coreFix_memExe_rsMem$setRobEnqTime_t;
  wire coreFix_memExe_rsMem$EN_doDispatch,
       coreFix_memExe_rsMem$EN_enq,
       coreFix_memExe_rsMem$EN_setRegReady_0_put,
       coreFix_memExe_rsMem$EN_setRegReady_1_put,
       coreFix_memExe_rsMem$EN_setRegReady_2_put,
       coreFix_memExe_rsMem$EN_setRegReady_3_put,
       coreFix_memExe_rsMem$EN_setRegReady_4_put,
       coreFix_memExe_rsMem$EN_setRobEnqTime,
       coreFix_memExe_rsMem$EN_specUpdate_correctSpeculation,
       coreFix_memExe_rsMem$EN_specUpdate_incorrectSpeculation,
       coreFix_memExe_rsMem$RDY_dispatchData,
       coreFix_memExe_rsMem$RDY_doDispatch,
       coreFix_memExe_rsMem$RDY_enq,
       coreFix_memExe_rsMem$canEnq,
       coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_memExe_stb
  wire [635 : 0] coreFix_memExe_stb$issue;
  wire [633 : 0] coreFix_memExe_stb$deq;
  wire [67 : 0] coreFix_memExe_stb$search;
  wire [63 : 0] coreFix_memExe_stb$enq_data,
		coreFix_memExe_stb$enq_paddr,
		coreFix_memExe_stb$getEnqIndex_paddr,
		coreFix_memExe_stb$noMatchLdQ_paddr,
		coreFix_memExe_stb$noMatchStQ_paddr,
		coreFix_memExe_stb$search_paddr;
  wire [7 : 0] coreFix_memExe_stb$enq_be,
	       coreFix_memExe_stb$noMatchLdQ_be,
	       coreFix_memExe_stb$noMatchStQ_be,
	       coreFix_memExe_stb$search_be;
  wire [2 : 0] coreFix_memExe_stb$getEnqIndex;
  wire [1 : 0] coreFix_memExe_stb$deq_idx, coreFix_memExe_stb$enq_idx;
  wire coreFix_memExe_stb$EN_deq,
       coreFix_memExe_stb$EN_enq,
       coreFix_memExe_stb$EN_issue,
       coreFix_memExe_stb$RDY_deq,
       coreFix_memExe_stb$RDY_enq,
       coreFix_memExe_stb$RDY_issue,
       coreFix_memExe_stb$isEmpty,
       coreFix_memExe_stb$noMatchLdQ,
       coreFix_memExe_stb$noMatchStQ;

  // ports of submodule coreFix_trainBPQ_0
  wire [159 : 0] coreFix_trainBPQ_0$D_IN, coreFix_trainBPQ_0$D_OUT;
  wire coreFix_trainBPQ_0$CLR,
       coreFix_trainBPQ_0$DEQ,
       coreFix_trainBPQ_0$EMPTY_N,
       coreFix_trainBPQ_0$ENQ,
       coreFix_trainBPQ_0$FULL_N;

  // ports of submodule coreFix_trainBPQ_1
  wire [159 : 0] coreFix_trainBPQ_1$D_IN, coreFix_trainBPQ_1$D_OUT;
  wire coreFix_trainBPQ_1$CLR,
       coreFix_trainBPQ_1$DEQ,
       coreFix_trainBPQ_1$EMPTY_N,
       coreFix_trainBPQ_1$ENQ,
       coreFix_trainBPQ_1$FULL_N;

  // ports of submodule csrInstOrInterruptInflight_dummy2_0
  wire csrInstOrInterruptInflight_dummy2_0$D_IN,
       csrInstOrInterruptInflight_dummy2_0$EN,
       csrInstOrInterruptInflight_dummy2_0$Q_OUT;

  // ports of submodule csrInstOrInterruptInflight_dummy2_1
  wire csrInstOrInterruptInflight_dummy2_1$D_IN,
       csrInstOrInterruptInflight_dummy2_1$EN,
       csrInstOrInterruptInflight_dummy2_1$Q_OUT;

  // ports of submodule csrf_mcycle_ehr_data_dummy2_0
  wire csrf_mcycle_ehr_data_dummy2_0$D_IN,
       csrf_mcycle_ehr_data_dummy2_0$EN,
       csrf_mcycle_ehr_data_dummy2_0$Q_OUT;

  // ports of submodule csrf_mcycle_ehr_data_dummy2_1
  wire csrf_mcycle_ehr_data_dummy2_1$D_IN,
       csrf_mcycle_ehr_data_dummy2_1$EN,
       csrf_mcycle_ehr_data_dummy2_1$Q_OUT;

  // ports of submodule csrf_minstret_ehr_data_dummy2_0
  wire csrf_minstret_ehr_data_dummy2_0$D_IN,
       csrf_minstret_ehr_data_dummy2_0$EN,
       csrf_minstret_ehr_data_dummy2_0$Q_OUT;

  // ports of submodule csrf_minstret_ehr_data_dummy2_1
  wire csrf_minstret_ehr_data_dummy2_1$D_IN,
       csrf_minstret_ehr_data_dummy2_1$EN,
       csrf_minstret_ehr_data_dummy2_1$Q_OUT;

  // ports of submodule csrf_stats_module_writeQ
  wire csrf_stats_module_writeQ$CLR,
       csrf_stats_module_writeQ$DEQ,
       csrf_stats_module_writeQ$D_IN,
       csrf_stats_module_writeQ$D_OUT,
       csrf_stats_module_writeQ$EMPTY_N,
       csrf_stats_module_writeQ$ENQ,
       csrf_stats_module_writeQ$FULL_N;

  // ports of submodule csrf_terminate_module_terminateQ
  wire csrf_terminate_module_terminateQ$CLR,
       csrf_terminate_module_terminateQ$DEQ,
       csrf_terminate_module_terminateQ$EMPTY_N,
       csrf_terminate_module_terminateQ$ENQ,
       csrf_terminate_module_terminateQ$FULL_N;

  // ports of submodule epochManager
  wire [3 : 0] epochManager$checkEpoch_0_check_e,
	       epochManager$checkEpoch_1_check_e,
	       epochManager$updatePrevEpoch_0_update_e,
	       epochManager$updatePrevEpoch_1_update_e;
  wire epochManager$EN_incrementEpoch,
       epochManager$EN_updatePrevEpoch_0_update,
       epochManager$EN_updatePrevEpoch_1_update,
       epochManager$RDY_incrementEpoch,
       epochManager$checkEpoch_0_check,
       epochManager$checkEpoch_1_check;

  // ports of submodule f_csr_reqs
  wire [76 : 0] f_csr_reqs$D_IN, f_csr_reqs$D_OUT;
  wire f_csr_reqs$CLR,
       f_csr_reqs$DEQ,
       f_csr_reqs$EMPTY_N,
       f_csr_reqs$ENQ,
       f_csr_reqs$FULL_N;

  // ports of submodule f_csr_rsps
  reg [64 : 0] f_csr_rsps$D_IN;
  wire [64 : 0] f_csr_rsps$D_OUT;
  wire f_csr_rsps$CLR,
       f_csr_rsps$DEQ,
       f_csr_rsps$EMPTY_N,
       f_csr_rsps$ENQ,
       f_csr_rsps$FULL_N;

  // ports of submodule f_fpr_reqs
  wire [69 : 0] f_fpr_reqs$D_IN, f_fpr_reqs$D_OUT;
  wire f_fpr_reqs$CLR,
       f_fpr_reqs$DEQ,
       f_fpr_reqs$EMPTY_N,
       f_fpr_reqs$ENQ,
       f_fpr_reqs$FULL_N;

  // ports of submodule f_fpr_rsps
  reg [64 : 0] f_fpr_rsps$D_IN;
  wire [64 : 0] f_fpr_rsps$D_OUT;
  wire f_fpr_rsps$CLR,
       f_fpr_rsps$DEQ,
       f_fpr_rsps$EMPTY_N,
       f_fpr_rsps$ENQ,
       f_fpr_rsps$FULL_N;

  // ports of submodule f_gpr_reqs
  wire [69 : 0] f_gpr_reqs$D_IN, f_gpr_reqs$D_OUT;
  wire f_gpr_reqs$CLR,
       f_gpr_reqs$DEQ,
       f_gpr_reqs$EMPTY_N,
       f_gpr_reqs$ENQ,
       f_gpr_reqs$FULL_N;

  // ports of submodule f_gpr_rsps
  reg [64 : 0] f_gpr_rsps$D_IN;
  wire [64 : 0] f_gpr_rsps$D_OUT;
  wire f_gpr_rsps$CLR,
       f_gpr_rsps$DEQ,
       f_gpr_rsps$EMPTY_N,
       f_gpr_rsps$ENQ,
       f_gpr_rsps$FULL_N;

  // ports of submodule f_run_halt_reqs
  wire f_run_halt_reqs$CLR,
       f_run_halt_reqs$DEQ,
       f_run_halt_reqs$D_IN,
       f_run_halt_reqs$D_OUT,
       f_run_halt_reqs$EMPTY_N,
       f_run_halt_reqs$ENQ,
       f_run_halt_reqs$FULL_N;

  // ports of submodule f_run_halt_rsps
  wire f_run_halt_rsps$CLR,
       f_run_halt_rsps$DEQ,
       f_run_halt_rsps$D_IN,
       f_run_halt_rsps$D_OUT,
       f_run_halt_rsps$EMPTY_N,
       f_run_halt_rsps$ENQ,
       f_run_halt_rsps$FULL_N;

  // ports of submodule fetchStage
  reg [63 : 0] fetchStage$redirect_pc;
  wire [582 : 0] fetchStage$iMemIfc_to_parent_fromP_enq_x;
  wire [578 : 0] fetchStage$iMemIfc_to_parent_rsToP_first;
  wire [387 : 0] fetchStage$pipelines_0_first, fetchStage$pipelines_1_first;
  wire [80 : 0] fetchStage$iTlbIfc_toParent_rsFromP_enq_x;
  wire [71 : 0] fetchStage$iMemIfc_to_parent_rqToP_first;
  wire [67 : 0] fetchStage$iMemIfc_cRqStuck_get,
		fetchStage$iMemIfc_pRqStuck_get;
  wire [65 : 0] fetchStage$mmioIfc_instResp_enq_x;
  wire [63 : 0] fetchStage$iMemIfc_to_proc_request_put,
		fetchStage$iTlbIfc_to_proc_request_put,
		fetchStage$mmioIfc_instReq_first_fst,
		fetchStage$mmioIfc_setHtifAddrs_fromHost,
		fetchStage$mmioIfc_setHtifAddrs_toHost,
		fetchStage$start_pc,
		fetchStage$train_predictors_next_pc,
		fetchStage$train_predictors_pc;
  wire [48 : 0] fetchStage$iTlbIfc_updateVMInfo_vm;
  wire [26 : 0] fetchStage$iTlbIfc_toParent_rqToP_first;
  wire [23 : 0] fetchStage$train_predictors_dpTrain;
  wire [4 : 0] fetchStage$train_predictors_iType;
  wire [2 : 0] fetchStage$iTlbIfc_perf_req_r;
  wire [1 : 0] fetchStage$iMemIfc_perf_req_r, fetchStage$perf_req_r;
  wire fetchStage$EN_done_flushing,
       fetchStage$EN_flush_predictors,
       fetchStage$EN_iMemIfc_cRqStuck_get,
       fetchStage$EN_iMemIfc_flush,
       fetchStage$EN_iMemIfc_pRqStuck_get,
       fetchStage$EN_iMemIfc_perf_req,
       fetchStage$EN_iMemIfc_perf_resp,
       fetchStage$EN_iMemIfc_perf_setStatus,
       fetchStage$EN_iMemIfc_to_parent_fromP_enq,
       fetchStage$EN_iMemIfc_to_parent_rqToP_deq,
       fetchStage$EN_iMemIfc_to_parent_rsToP_deq,
       fetchStage$EN_iMemIfc_to_proc_request_put,
       fetchStage$EN_iMemIfc_to_proc_response_get,
       fetchStage$EN_iTlbIfc_flush,
       fetchStage$EN_iTlbIfc_perf_req,
       fetchStage$EN_iTlbIfc_perf_resp,
       fetchStage$EN_iTlbIfc_perf_setStatus,
       fetchStage$EN_iTlbIfc_toParent_flush_request_get,
       fetchStage$EN_iTlbIfc_toParent_flush_response_put,
       fetchStage$EN_iTlbIfc_toParent_rqToP_deq,
       fetchStage$EN_iTlbIfc_toParent_rsFromP_enq,
       fetchStage$EN_iTlbIfc_to_proc_request_put,
       fetchStage$EN_iTlbIfc_to_proc_response_get,
       fetchStage$EN_iTlbIfc_updateVMInfo,
       fetchStage$EN_mmioIfc_instReq_deq,
       fetchStage$EN_mmioIfc_instResp_enq,
       fetchStage$EN_mmioIfc_setHtifAddrs,
       fetchStage$EN_perf_req,
       fetchStage$EN_perf_resp,
       fetchStage$EN_perf_setStatus,
       fetchStage$EN_pipelines_0_deq,
       fetchStage$EN_pipelines_1_deq,
       fetchStage$EN_redirect,
       fetchStage$EN_setWaitFlush,
       fetchStage$EN_setWaitRedirect,
       fetchStage$EN_start,
       fetchStage$EN_stop,
       fetchStage$EN_train_predictors,
       fetchStage$RDY_done_flushing,
       fetchStage$RDY_iMemIfc_cRqStuck_get,
       fetchStage$RDY_iMemIfc_pRqStuck_get,
       fetchStage$RDY_iMemIfc_to_parent_fromP_enq,
       fetchStage$RDY_iMemIfc_to_parent_rqToP_deq,
       fetchStage$RDY_iMemIfc_to_parent_rqToP_first,
       fetchStage$RDY_iMemIfc_to_parent_rsToP_deq,
       fetchStage$RDY_iMemIfc_to_parent_rsToP_first,
       fetchStage$RDY_iTlbIfc_flush,
       fetchStage$RDY_iTlbIfc_toParent_flush_request_get,
       fetchStage$RDY_iTlbIfc_toParent_flush_response_put,
       fetchStage$RDY_iTlbIfc_toParent_rqToP_deq,
       fetchStage$RDY_iTlbIfc_toParent_rqToP_first,
       fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq,
       fetchStage$RDY_mmioIfc_instReq_deq,
       fetchStage$RDY_mmioIfc_instReq_first_fst,
       fetchStage$RDY_mmioIfc_instReq_first_snd,
       fetchStage$RDY_mmioIfc_instResp_enq,
       fetchStage$RDY_pipelines_0_deq,
       fetchStage$RDY_pipelines_0_first,
       fetchStage$RDY_pipelines_1_deq,
       fetchStage$RDY_pipelines_1_first,
       fetchStage$emptyForFlush,
       fetchStage$flush_predictors_done,
       fetchStage$iMemIfc_flush_done,
       fetchStage$iMemIfc_perf_setStatus_doStats,
       fetchStage$iMemIfc_to_parent_fromP_notFull,
       fetchStage$iMemIfc_to_parent_rqToP_notEmpty,
       fetchStage$iMemIfc_to_parent_rsToP_notEmpty,
       fetchStage$iTlbIfc_flush_done,
       fetchStage$iTlbIfc_noPendingReq,
       fetchStage$iTlbIfc_perf_setStatus_doStats,
       fetchStage$mmioIfc_instReq_first_snd,
       fetchStage$perf_setStatus_doStats,
       fetchStage$pipelines_0_canDeq,
       fetchStage$pipelines_1_canDeq,
       fetchStage$train_predictors_isCompressed,
       fetchStage$train_predictors_mispred,
       fetchStage$train_predictors_taken;

  // ports of submodule l2Tlb
  wire [83 : 0] l2Tlb$toChildren_rsToC_first;
  wire [64 : 0] l2Tlb$toMem_memReq_first, l2Tlb$toMem_respLd_enq_x;
  wire [48 : 0] l2Tlb$updateVMInfo_vmD, l2Tlb$updateVMInfo_vmI;
  wire [29 : 0] l2Tlb$toChildren_rqFromC_put;
  wire [3 : 0] l2Tlb$perf_req_r;
  wire l2Tlb$EN_perf_req,
       l2Tlb$EN_perf_resp,
       l2Tlb$EN_perf_setStatus,
       l2Tlb$EN_toChildren_dTlbReqFlush_put,
       l2Tlb$EN_toChildren_flushDone_get,
       l2Tlb$EN_toChildren_iTlbReqFlush_put,
       l2Tlb$EN_toChildren_rqFromC_put,
       l2Tlb$EN_toChildren_rsToC_deq,
       l2Tlb$EN_toMem_memReq_deq,
       l2Tlb$EN_toMem_respLd_enq,
       l2Tlb$EN_updateVMInfo,
       l2Tlb$RDY_toChildren_dTlbReqFlush_put,
       l2Tlb$RDY_toChildren_flushDone_get,
       l2Tlb$RDY_toChildren_iTlbReqFlush_put,
       l2Tlb$RDY_toChildren_rqFromC_put,
       l2Tlb$RDY_toChildren_rsToC_deq,
       l2Tlb$RDY_toChildren_rsToC_first,
       l2Tlb$RDY_toMem_memReq_deq,
       l2Tlb$RDY_toMem_memReq_first,
       l2Tlb$RDY_toMem_respLd_enq,
       l2Tlb$perf_setStatus_doStats,
       l2Tlb$toMem_memReq_notEmpty,
       l2Tlb$toMem_respLd_notFull;

  // ports of submodule mmio_cRqQ_clearReq_dummy2_0
  wire mmio_cRqQ_clearReq_dummy2_0$D_IN, mmio_cRqQ_clearReq_dummy2_0$EN;

  // ports of submodule mmio_cRqQ_clearReq_dummy2_1
  wire mmio_cRqQ_clearReq_dummy2_1$D_IN,
       mmio_cRqQ_clearReq_dummy2_1$EN,
       mmio_cRqQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule mmio_cRqQ_deqReq_dummy2_0
  wire mmio_cRqQ_deqReq_dummy2_0$D_IN, mmio_cRqQ_deqReq_dummy2_0$EN;

  // ports of submodule mmio_cRqQ_deqReq_dummy2_1
  wire mmio_cRqQ_deqReq_dummy2_1$D_IN, mmio_cRqQ_deqReq_dummy2_1$EN;

  // ports of submodule mmio_cRqQ_deqReq_dummy2_2
  wire mmio_cRqQ_deqReq_dummy2_2$D_IN,
       mmio_cRqQ_deqReq_dummy2_2$EN,
       mmio_cRqQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_cRqQ_enqReq_dummy2_0
  wire mmio_cRqQ_enqReq_dummy2_0$D_IN, mmio_cRqQ_enqReq_dummy2_0$EN;

  // ports of submodule mmio_cRqQ_enqReq_dummy2_1
  wire mmio_cRqQ_enqReq_dummy2_1$D_IN, mmio_cRqQ_enqReq_dummy2_1$EN;

  // ports of submodule mmio_cRqQ_enqReq_dummy2_2
  wire mmio_cRqQ_enqReq_dummy2_2$D_IN,
       mmio_cRqQ_enqReq_dummy2_2$EN,
       mmio_cRqQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_cRsQ_clearReq_dummy2_0
  wire mmio_cRsQ_clearReq_dummy2_0$D_IN, mmio_cRsQ_clearReq_dummy2_0$EN;

  // ports of submodule mmio_cRsQ_clearReq_dummy2_1
  wire mmio_cRsQ_clearReq_dummy2_1$D_IN,
       mmio_cRsQ_clearReq_dummy2_1$EN,
       mmio_cRsQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule mmio_cRsQ_deqReq_dummy2_0
  wire mmio_cRsQ_deqReq_dummy2_0$D_IN, mmio_cRsQ_deqReq_dummy2_0$EN;

  // ports of submodule mmio_cRsQ_deqReq_dummy2_1
  wire mmio_cRsQ_deqReq_dummy2_1$D_IN, mmio_cRsQ_deqReq_dummy2_1$EN;

  // ports of submodule mmio_cRsQ_deqReq_dummy2_2
  wire mmio_cRsQ_deqReq_dummy2_2$D_IN,
       mmio_cRsQ_deqReq_dummy2_2$EN,
       mmio_cRsQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_cRsQ_enqReq_dummy2_0
  wire mmio_cRsQ_enqReq_dummy2_0$D_IN, mmio_cRsQ_enqReq_dummy2_0$EN;

  // ports of submodule mmio_cRsQ_enqReq_dummy2_1
  wire mmio_cRsQ_enqReq_dummy2_1$D_IN, mmio_cRsQ_enqReq_dummy2_1$EN;

  // ports of submodule mmio_cRsQ_enqReq_dummy2_2
  wire mmio_cRsQ_enqReq_dummy2_2$D_IN,
       mmio_cRsQ_enqReq_dummy2_2$EN,
       mmio_cRsQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_dataPendQ_clearReq_dummy2_0
  wire mmio_dataPendQ_clearReq_dummy2_0$D_IN,
       mmio_dataPendQ_clearReq_dummy2_0$EN;

  // ports of submodule mmio_dataPendQ_clearReq_dummy2_1
  wire mmio_dataPendQ_clearReq_dummy2_1$D_IN,
       mmio_dataPendQ_clearReq_dummy2_1$EN,
       mmio_dataPendQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule mmio_dataPendQ_deqReq_dummy2_0
  wire mmio_dataPendQ_deqReq_dummy2_0$D_IN, mmio_dataPendQ_deqReq_dummy2_0$EN;

  // ports of submodule mmio_dataPendQ_deqReq_dummy2_1
  wire mmio_dataPendQ_deqReq_dummy2_1$D_IN, mmio_dataPendQ_deqReq_dummy2_1$EN;

  // ports of submodule mmio_dataPendQ_deqReq_dummy2_2
  wire mmio_dataPendQ_deqReq_dummy2_2$D_IN,
       mmio_dataPendQ_deqReq_dummy2_2$EN,
       mmio_dataPendQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_dataPendQ_enqReq_dummy2_0
  wire mmio_dataPendQ_enqReq_dummy2_0$D_IN, mmio_dataPendQ_enqReq_dummy2_0$EN;

  // ports of submodule mmio_dataPendQ_enqReq_dummy2_1
  wire mmio_dataPendQ_enqReq_dummy2_1$D_IN, mmio_dataPendQ_enqReq_dummy2_1$EN;

  // ports of submodule mmio_dataPendQ_enqReq_dummy2_2
  wire mmio_dataPendQ_enqReq_dummy2_2$D_IN,
       mmio_dataPendQ_enqReq_dummy2_2$EN,
       mmio_dataPendQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_dataReqQ_clearReq_dummy2_0
  wire mmio_dataReqQ_clearReq_dummy2_0$D_IN,
       mmio_dataReqQ_clearReq_dummy2_0$EN;

  // ports of submodule mmio_dataReqQ_clearReq_dummy2_1
  wire mmio_dataReqQ_clearReq_dummy2_1$D_IN,
       mmio_dataReqQ_clearReq_dummy2_1$EN,
       mmio_dataReqQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule mmio_dataReqQ_deqReq_dummy2_0
  wire mmio_dataReqQ_deqReq_dummy2_0$D_IN, mmio_dataReqQ_deqReq_dummy2_0$EN;

  // ports of submodule mmio_dataReqQ_deqReq_dummy2_1
  wire mmio_dataReqQ_deqReq_dummy2_1$D_IN, mmio_dataReqQ_deqReq_dummy2_1$EN;

  // ports of submodule mmio_dataReqQ_deqReq_dummy2_2
  wire mmio_dataReqQ_deqReq_dummy2_2$D_IN,
       mmio_dataReqQ_deqReq_dummy2_2$EN,
       mmio_dataReqQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_dataReqQ_enqReq_dummy2_0
  wire mmio_dataReqQ_enqReq_dummy2_0$D_IN, mmio_dataReqQ_enqReq_dummy2_0$EN;

  // ports of submodule mmio_dataReqQ_enqReq_dummy2_1
  wire mmio_dataReqQ_enqReq_dummy2_1$D_IN, mmio_dataReqQ_enqReq_dummy2_1$EN;

  // ports of submodule mmio_dataReqQ_enqReq_dummy2_2
  wire mmio_dataReqQ_enqReq_dummy2_2$D_IN,
       mmio_dataReqQ_enqReq_dummy2_2$EN,
       mmio_dataReqQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_dataRespQ_clearReq_dummy2_0
  wire mmio_dataRespQ_clearReq_dummy2_0$D_IN,
       mmio_dataRespQ_clearReq_dummy2_0$EN;

  // ports of submodule mmio_dataRespQ_clearReq_dummy2_1
  wire mmio_dataRespQ_clearReq_dummy2_1$D_IN,
       mmio_dataRespQ_clearReq_dummy2_1$EN,
       mmio_dataRespQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule mmio_dataRespQ_deqReq_dummy2_0
  wire mmio_dataRespQ_deqReq_dummy2_0$D_IN, mmio_dataRespQ_deqReq_dummy2_0$EN;

  // ports of submodule mmio_dataRespQ_deqReq_dummy2_1
  wire mmio_dataRespQ_deqReq_dummy2_1$D_IN, mmio_dataRespQ_deqReq_dummy2_1$EN;

  // ports of submodule mmio_dataRespQ_deqReq_dummy2_2
  wire mmio_dataRespQ_deqReq_dummy2_2$D_IN,
       mmio_dataRespQ_deqReq_dummy2_2$EN,
       mmio_dataRespQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_dataRespQ_enqReq_dummy2_0
  wire mmio_dataRespQ_enqReq_dummy2_0$D_IN, mmio_dataRespQ_enqReq_dummy2_0$EN;

  // ports of submodule mmio_dataRespQ_enqReq_dummy2_1
  wire mmio_dataRespQ_enqReq_dummy2_1$D_IN, mmio_dataRespQ_enqReq_dummy2_1$EN;

  // ports of submodule mmio_dataRespQ_enqReq_dummy2_2
  wire mmio_dataRespQ_enqReq_dummy2_2$D_IN,
       mmio_dataRespQ_enqReq_dummy2_2$EN,
       mmio_dataRespQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_pRqQ_clearReq_dummy2_0
  wire mmio_pRqQ_clearReq_dummy2_0$D_IN, mmio_pRqQ_clearReq_dummy2_0$EN;

  // ports of submodule mmio_pRqQ_clearReq_dummy2_1
  wire mmio_pRqQ_clearReq_dummy2_1$D_IN,
       mmio_pRqQ_clearReq_dummy2_1$EN,
       mmio_pRqQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule mmio_pRqQ_deqReq_dummy2_0
  wire mmio_pRqQ_deqReq_dummy2_0$D_IN, mmio_pRqQ_deqReq_dummy2_0$EN;

  // ports of submodule mmio_pRqQ_deqReq_dummy2_1
  wire mmio_pRqQ_deqReq_dummy2_1$D_IN, mmio_pRqQ_deqReq_dummy2_1$EN;

  // ports of submodule mmio_pRqQ_deqReq_dummy2_2
  wire mmio_pRqQ_deqReq_dummy2_2$D_IN,
       mmio_pRqQ_deqReq_dummy2_2$EN,
       mmio_pRqQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_pRqQ_enqReq_dummy2_0
  wire mmio_pRqQ_enqReq_dummy2_0$D_IN, mmio_pRqQ_enqReq_dummy2_0$EN;

  // ports of submodule mmio_pRqQ_enqReq_dummy2_1
  wire mmio_pRqQ_enqReq_dummy2_1$D_IN, mmio_pRqQ_enqReq_dummy2_1$EN;

  // ports of submodule mmio_pRqQ_enqReq_dummy2_2
  wire mmio_pRqQ_enqReq_dummy2_2$D_IN,
       mmio_pRqQ_enqReq_dummy2_2$EN,
       mmio_pRqQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_pRsQ_clearReq_dummy2_0
  wire mmio_pRsQ_clearReq_dummy2_0$D_IN, mmio_pRsQ_clearReq_dummy2_0$EN;

  // ports of submodule mmio_pRsQ_clearReq_dummy2_1
  wire mmio_pRsQ_clearReq_dummy2_1$D_IN,
       mmio_pRsQ_clearReq_dummy2_1$EN,
       mmio_pRsQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule mmio_pRsQ_deqReq_dummy2_0
  wire mmio_pRsQ_deqReq_dummy2_0$D_IN, mmio_pRsQ_deqReq_dummy2_0$EN;

  // ports of submodule mmio_pRsQ_deqReq_dummy2_1
  wire mmio_pRsQ_deqReq_dummy2_1$D_IN, mmio_pRsQ_deqReq_dummy2_1$EN;

  // ports of submodule mmio_pRsQ_deqReq_dummy2_2
  wire mmio_pRsQ_deqReq_dummy2_2$D_IN,
       mmio_pRsQ_deqReq_dummy2_2$EN,
       mmio_pRsQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_pRsQ_enqReq_dummy2_0
  wire mmio_pRsQ_enqReq_dummy2_0$D_IN, mmio_pRsQ_enqReq_dummy2_0$EN;

  // ports of submodule mmio_pRsQ_enqReq_dummy2_1
  wire mmio_pRsQ_enqReq_dummy2_1$D_IN, mmio_pRsQ_enqReq_dummy2_1$EN;

  // ports of submodule mmio_pRsQ_enqReq_dummy2_2
  wire mmio_pRsQ_enqReq_dummy2_2$D_IN,
       mmio_pRsQ_enqReq_dummy2_2$EN,
       mmio_pRsQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule perfReqQ
  wire [8 : 0] perfReqQ$D_IN, perfReqQ$D_OUT;
  wire perfReqQ$CLR,
       perfReqQ$DEQ,
       perfReqQ$EMPTY_N,
       perfReqQ$ENQ,
       perfReqQ$FULL_N;

  // ports of submodule regRenamingTable
  reg [26 : 0] regRenamingTable$rename_0_getRename_r;
  reg [3 : 0] regRenamingTable$specUpdate_incorrectSpeculation_kill_tag;
  wire [32 : 0] regRenamingTable$rename_0_getRename,
		regRenamingTable$rename_1_getRename;
  wire [26 : 0] regRenamingTable$rename_0_claimRename_r,
		regRenamingTable$rename_1_claimRename_r,
		regRenamingTable$rename_1_getRename_r;
  wire [11 : 0] regRenamingTable$rename_0_claimRename_sb,
		regRenamingTable$rename_1_claimRename_sb,
		regRenamingTable$specUpdate_correctSpeculation_mask;
  wire regRenamingTable$EN_commit_0_commit,
       regRenamingTable$EN_commit_1_commit,
       regRenamingTable$EN_rename_0_claimRename,
       regRenamingTable$EN_rename_1_claimRename,
       regRenamingTable$EN_specUpdate_correctSpeculation,
       regRenamingTable$EN_specUpdate_incorrectSpeculation,
       regRenamingTable$RDY_commit_0_commit,
       regRenamingTable$RDY_commit_1_commit,
       regRenamingTable$RDY_rename_0_claimRename,
       regRenamingTable$RDY_rename_0_getRename,
       regRenamingTable$RDY_rename_1_claimRename,
       regRenamingTable$RDY_rename_1_getRename,
       regRenamingTable$rename_0_canRename,
       regRenamingTable$rename_1_canRename,
       regRenamingTable$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule rf
  reg [63 : 0] rf$write_2_wr_data, rf$write_3_wr_data;
  reg [6 : 0] rf$write_2_wr_rindx, rf$write_3_wr_rindx;
  wire [63 : 0] rf$read_0_rd1,
		rf$read_0_rd2,
		rf$read_1_rd1,
		rf$read_1_rd2,
		rf$read_2_rd1,
		rf$read_2_rd2,
		rf$read_2_rd3,
		rf$read_3_rd1,
		rf$read_3_rd2,
		rf$read_4_rd1,
		rf$write_0_wr_data,
		rf$write_1_wr_data,
		rf$write_4_wr_data;
  wire [6 : 0] rf$read_0_rd1_rindx,
	       rf$read_0_rd2_rindx,
	       rf$read_0_rd3_rindx,
	       rf$read_1_rd1_rindx,
	       rf$read_1_rd2_rindx,
	       rf$read_1_rd3_rindx,
	       rf$read_2_rd1_rindx,
	       rf$read_2_rd2_rindx,
	       rf$read_2_rd3_rindx,
	       rf$read_3_rd1_rindx,
	       rf$read_3_rd2_rindx,
	       rf$read_3_rd3_rindx,
	       rf$read_4_rd1_rindx,
	       rf$read_4_rd2_rindx,
	       rf$read_4_rd3_rindx,
	       rf$write_0_wr_rindx,
	       rf$write_1_wr_rindx,
	       rf$write_4_wr_rindx;
  wire rf$EN_write_0_wr,
       rf$EN_write_1_wr,
       rf$EN_write_2_wr,
       rf$EN_write_3_wr,
       rf$EN_write_4_wr;

  // ports of submodule rob
  reg [425 : 0] rob$enqPort_0_enq_x;
  reg [63 : 0] rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data,
	       rob$setExecuted_doFinishMem_RegData_dst_data;
  reg [11 : 0] rob$setExecuted_doFinishFpuMulDiv_0_set_x,
	       rob$setExecuted_doFinishMem_RegData_x,
	       rob$specUpdate_incorrectSpeculation_inst_tag;
  reg [4 : 0] rob$setExecuted_deqLSQ_cause,
	      rob$setExecuted_doFinishFpuMulDiv_0_set_fflags;
  reg [3 : 0] rob$specUpdate_incorrectSpeculation_spec_tag;
  wire [425 : 0] rob$deqPort_0_deq_data,
		 rob$deqPort_1_deq_data,
		 rob$enqPort_1_enq_x;
  wire [129 : 0] rob$setExecuted_doFinishAlu_0_set_cf,
		 rob$setExecuted_doFinishAlu_1_set_cf;
  wire [64 : 0] rob$setExecuted_doFinishAlu_0_set_csrData,
		rob$setExecuted_doFinishAlu_1_set_csrData;
  wire [63 : 0] rob$getOrigPC_0_get,
		rob$getOrigPC_1_get,
		rob$getOrigPredPC_0_get,
		rob$getOrigPredPC_1_get,
		rob$setExecuted_doFinishAlu_0_set_dst_data,
		rob$setExecuted_doFinishAlu_1_set_dst_data,
		rob$setExecuted_doFinishMem_store_data,
		rob$setExecuted_doFinishMem_vaddr;
  wire [31 : 0] rob$getOrig_Inst_0_get, rob$getOrig_Inst_1_get;
  wire [11 : 0] rob$deqPort_0_getDeqInstTag,
		rob$enqPort_0_getEnqInstTag,
		rob$enqPort_1_getEnqInstTag,
		rob$getOrigPC_0_get_x,
		rob$getOrigPC_1_get_x,
		rob$getOrigPC_2_get_x,
		rob$getOrigPredPC_0_get_x,
		rob$getOrigPredPC_1_get_x,
		rob$getOrig_Inst_0_get_x,
		rob$getOrig_Inst_1_get_x,
		rob$setExecuted_deqLSQ_x,
		rob$setExecuted_doFinishAlu_0_set_x,
		rob$setExecuted_doFinishAlu_1_set_x,
		rob$setExecuted_doFinishMem_x,
		rob$setLSQAtCommitNotified_x,
		rob$specUpdate_correctSpeculation_mask;
  wire [7 : 0] rob$setExecuted_doFinishMem_store_data_BE;
  wire [5 : 0] rob$getEnqTime;
  wire [2 : 0] rob$setExecuted_deqLSQ_ld_killed;
  wire rob$EN_deqPort_0_deq,
       rob$EN_deqPort_1_deq,
       rob$EN_enqPort_0_enq,
       rob$EN_enqPort_1_enq,
       rob$EN_setExecuted_deqLSQ,
       rob$EN_setExecuted_doFinishAlu_0_set,
       rob$EN_setExecuted_doFinishAlu_1_set,
       rob$EN_setExecuted_doFinishFpuMulDiv_0_set,
       rob$EN_setExecuted_doFinishMem,
       rob$EN_setExecuted_doFinishMem_RegData,
       rob$EN_setLSQAtCommitNotified,
       rob$EN_specUpdate_correctSpeculation,
       rob$EN_specUpdate_incorrectSpeculation,
       rob$RDY_deqPort_0_deq,
       rob$RDY_deqPort_0_deq_data,
       rob$RDY_deqPort_1_deq,
       rob$RDY_deqPort_1_deq_data,
       rob$RDY_enqPort_0_enq,
       rob$RDY_enqPort_1_enq,
       rob$RDY_setExecuted_deqLSQ,
       rob$RDY_setExecuted_doFinishAlu_0_set,
       rob$RDY_setExecuted_doFinishAlu_1_set,
       rob$RDY_setExecuted_doFinishFpuMulDiv_0_set,
       rob$RDY_setExecuted_doFinishMem,
       rob$RDY_setLSQAtCommitNotified,
       rob$deqPort_0_canDeq,
       rob$deqPort_1_canDeq,
       rob$enqPort_0_canEnq,
       rob$enqPort_1_canEnq,
       rob$isEmpty,
       rob$setExecuted_doFinishMem_access_at_commit,
       rob$setExecuted_doFinishMem_non_mmio_st_done,
       rob$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule sbAggr
  reg [6 : 0] sbAggr$setReady_2_put, sbAggr$setReady_4_put;
  wire [32 : 0] sbAggr$eagerLookup_0_get_r, sbAggr$eagerLookup_1_get_r;
  wire [8 : 0] sbAggr$setBusy_0_set_dst, sbAggr$setBusy_1_set_dst;
  wire [6 : 0] sbAggr$setReady_0_put,
	       sbAggr$setReady_1_put,
	       sbAggr$setReady_3_put;
  wire [3 : 0] sbAggr$eagerLookup_0_get, sbAggr$eagerLookup_1_get;
  wire sbAggr$EN_setBusy_0_set,
       sbAggr$EN_setBusy_1_set,
       sbAggr$EN_setReady_0_put,
       sbAggr$EN_setReady_1_put,
       sbAggr$EN_setReady_2_put,
       sbAggr$EN_setReady_3_put,
       sbAggr$EN_setReady_4_put;

  // ports of submodule sbCons
  reg [6 : 0] sbCons$setReady_2_put, sbCons$setReady_3_put;
  wire [32 : 0] sbCons$eagerLookup_0_get_r,
		sbCons$eagerLookup_1_get_r,
		sbCons$lazyLookup_0_get_r,
		sbCons$lazyLookup_1_get_r,
		sbCons$lazyLookup_2_get_r,
		sbCons$lazyLookup_3_get_r,
		sbCons$lazyLookup_4_get_r;
  wire [8 : 0] sbCons$setBusy_0_set_dst, sbCons$setBusy_1_set_dst;
  wire [6 : 0] sbCons$setReady_0_put,
	       sbCons$setReady_1_put,
	       sbCons$setReady_4_put;
  wire [3 : 0] sbCons$lazyLookup_0_get,
	       sbCons$lazyLookup_1_get,
	       sbCons$lazyLookup_2_get,
	       sbCons$lazyLookup_3_get;
  wire sbCons$EN_setBusy_0_set,
       sbCons$EN_setBusy_1_set,
       sbCons$EN_setReady_0_put,
       sbCons$EN_setReady_1_put,
       sbCons$EN_setReady_2_put,
       sbCons$EN_setReady_3_put,
       sbCons$EN_setReady_4_put;

  // ports of submodule specTagManager
  reg [3 : 0] specTagManager$specUpdate_incorrectSpeculation_kill_tag;
  wire [11 : 0] specTagManager$currentSpecBits,
		specTagManager$specUpdate_correctSpeculation_mask;
  wire [3 : 0] specTagManager$nextSpecTag;
  wire specTagManager$EN_claimSpecTag,
       specTagManager$EN_specUpdate_correctSpeculation,
       specTagManager$EN_specUpdate_incorrectSpeculation,
       specTagManager$RDY_claimSpecTag,
       specTagManager$RDY_nextSpecTag,
       specTagManager$canClaim,
       specTagManager$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule v_f_to_TV_0
  reg [861 : 0] v_f_to_TV_0$D_IN;
  wire [861 : 0] v_f_to_TV_0$D_OUT;
  wire v_f_to_TV_0$CLR,
       v_f_to_TV_0$DEQ,
       v_f_to_TV_0$EMPTY_N,
       v_f_to_TV_0$ENQ,
       v_f_to_TV_0$FULL_N;

  // ports of submodule v_f_to_TV_1
  wire [861 : 0] v_f_to_TV_1$D_IN, v_f_to_TV_1$D_OUT;
  wire v_f_to_TV_1$CLR,
       v_f_to_TV_1$DEQ,
       v_f_to_TV_1$EMPTY_N,
       v_f_to_TV_1$ENQ,
       v_f_to_TV_1$FULL_N;

  // rule scheduling signals
  wire CAN_FIRE_RL_commitStage_doCommitKilledLd,
       CAN_FIRE_RL_commitStage_doCommitNormalInst,
       CAN_FIRE_RL_commitStage_doCommitSystemInst,
       CAN_FIRE_RL_commitStage_doCommitTrap_flush,
       CAN_FIRE_RL_commitStage_doCommitTrap_handle,
       CAN_FIRE_RL_commitStage_doSetLSQAtCommit,
       CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1,
       CAN_FIRE_RL_commitStage_notifyLSQCommit,
       CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv,
       CAN_FIRE_RL_commitStage_rl_send_tv_reset,
       CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu,
       CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu,
       CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F,
       CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T,
       CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu,
       CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu,
       CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu,
       CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F,
       CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T,
       CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu,
       CAN_FIRE_RL_coreFix_doFetchTrainBP,
       CAN_FIRE_RL_coreFix_doFetchTrainBP_1,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon,
       CAN_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq,
       CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize,
       CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem,
       CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq,
       CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue,
       CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq,
       CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault,
       CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue,
       CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault,
       CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence,
       CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq,
       CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault,
       CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue,
       CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq,
       CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue,
       CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem,
       CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault,
       CAN_FIRE_RL_coreFix_memExe_doDispatchMem,
       CAN_FIRE_RL_coreFix_memExe_doExeMem,
       CAN_FIRE_RL_coreFix_memExe_doFinishMem,
       CAN_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ,
       CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate,
       CAN_FIRE_RL_coreFix_memExe_doIssueSB,
       CAN_FIRE_RL_coreFix_memExe_doRegReadMem,
       CAN_FIRE_RL_coreFix_memExe_doRespLdForward,
       CAN_FIRE_RL_coreFix_memExe_doRespLdMem,
       CAN_FIRE_RL_coreFix_memExe_forwardQ_canonicalize,
       CAN_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon,
       CAN_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize,
       CAN_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon,
       CAN_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon,
       CAN_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon,
       CAN_FIRE_RL_coreFix_memExe_reqLdQ_full_canon,
       CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon,
       CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon,
       CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon,
       CAN_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon,
       CAN_FIRE_RL_coreFix_memExe_reqStQ_empty_canon,
       CAN_FIRE_RL_coreFix_memExe_reqStQ_full_canon,
       CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize,
       CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon,
       CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_sendLdToMem,
       CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem,
       CAN_FIRE_RL_coreFix_memExe_sendStToMem,
       CAN_FIRE_RL_csrInstOrInterruptInflight_canon,
       CAN_FIRE_RL_csrf_incCycle,
       CAN_FIRE_RL_csrf_mcycle_ehr_data_canon,
       CAN_FIRE_RL_csrf_mcycle_ehr_setRead,
       CAN_FIRE_RL_csrf_minstret_ehr_data_canon,
       CAN_FIRE_RL_csrf_minstret_ehr_setRead,
       CAN_FIRE_RL_flushBrPred,
       CAN_FIRE_RL_flushCaches,
       CAN_FIRE_RL_mkConnectionGetPut,
       CAN_FIRE_RL_mkConnectionGetPut_1,
       CAN_FIRE_RL_mmio_cRqQ_canonicalize,
       CAN_FIRE_RL_mmio_cRqQ_clearReq_canon,
       CAN_FIRE_RL_mmio_cRqQ_deqReq_canon,
       CAN_FIRE_RL_mmio_cRqQ_enqReq_canon,
       CAN_FIRE_RL_mmio_cRsQ_canonicalize,
       CAN_FIRE_RL_mmio_cRsQ_clearReq_canon,
       CAN_FIRE_RL_mmio_cRsQ_deqReq_canon,
       CAN_FIRE_RL_mmio_cRsQ_enqReq_canon,
       CAN_FIRE_RL_mmio_dataPendQ_canonicalize,
       CAN_FIRE_RL_mmio_dataPendQ_clearReq_canon,
       CAN_FIRE_RL_mmio_dataPendQ_deqReq_canon,
       CAN_FIRE_RL_mmio_dataPendQ_enqReq_canon,
       CAN_FIRE_RL_mmio_dataReqQ_canonicalize,
       CAN_FIRE_RL_mmio_dataReqQ_clearReq_canon,
       CAN_FIRE_RL_mmio_dataReqQ_deqReq_canon,
       CAN_FIRE_RL_mmio_dataReqQ_enqReq_canon,
       CAN_FIRE_RL_mmio_dataRespQ_canonicalize,
       CAN_FIRE_RL_mmio_dataRespQ_clearReq_canon,
       CAN_FIRE_RL_mmio_dataRespQ_deqReq_canon,
       CAN_FIRE_RL_mmio_dataRespQ_enqReq_canon,
       CAN_FIRE_RL_mmio_handlePRq,
       CAN_FIRE_RL_mmio_pRqQ_canonicalize,
       CAN_FIRE_RL_mmio_pRqQ_clearReq_canon,
       CAN_FIRE_RL_mmio_pRqQ_deqReq_canon,
       CAN_FIRE_RL_mmio_pRqQ_enqReq_canon,
       CAN_FIRE_RL_mmio_pRsQ_canonicalize,
       CAN_FIRE_RL_mmio_pRsQ_clearReq_canon,
       CAN_FIRE_RL_mmio_pRsQ_deqReq_canon,
       CAN_FIRE_RL_mmio_pRsQ_enqReq_canon,
       CAN_FIRE_RL_mmio_sendDataReq,
       CAN_FIRE_RL_mmio_sendDataResp,
       CAN_FIRE_RL_mmio_sendInstReq,
       CAN_FIRE_RL_mmio_sendInstResp,
       CAN_FIRE_RL_prepareCachesAndTlbs,
       CAN_FIRE_RL_readyToFetch,
       CAN_FIRE_RL_renameStage_doRenaming,
       CAN_FIRE_RL_renameStage_doRenaming_SystemInst,
       CAN_FIRE_RL_renameStage_doRenaming_Trap,
       CAN_FIRE_RL_renameStage_doRenaming_wrongPath,
       CAN_FIRE_RL_rl_debug_csr_access_busy,
       CAN_FIRE_RL_rl_debug_csr_read,
       CAN_FIRE_RL_rl_debug_csr_write,
       CAN_FIRE_RL_rl_debug_fpr_access_busy,
       CAN_FIRE_RL_rl_debug_fpr_read,
       CAN_FIRE_RL_rl_debug_fpr_write,
       CAN_FIRE_RL_rl_debug_gpr_access_busy,
       CAN_FIRE_RL_rl_debug_gpr_read,
       CAN_FIRE_RL_rl_debug_gpr_write,
       CAN_FIRE_RL_rl_debug_halt_req,
       CAN_FIRE_RL_rl_debug_halt_req_already_halted,
       CAN_FIRE_RL_rl_debug_halted,
       CAN_FIRE_RL_rl_debug_resume,
       CAN_FIRE_RL_rl_debug_run_redundant,
       CAN_FIRE_RL_rl_outOfReset,
       CAN_FIRE_RL_sendDTlbReq,
       CAN_FIRE_RL_sendFlushDone,
       CAN_FIRE_RL_sendITlbReq,
       CAN_FIRE_RL_sendRobEnqTime,
       CAN_FIRE_RL_sendRsToDTlb,
       CAN_FIRE_RL_sendRsToITlb,
       CAN_FIRE_RL_setDoFlushBrPred,
       CAN_FIRE_RL_setDoFlushCaches,
       CAN_FIRE_coreIndInv_perfResp,
       CAN_FIRE_coreIndInv_terminate,
       CAN_FIRE_coreReq_perfReq,
       CAN_FIRE_coreReq_start,
       CAN_FIRE_dCacheToParent_fromP_enq,
       CAN_FIRE_dCacheToParent_rqToP_deq,
       CAN_FIRE_dCacheToParent_rsToP_deq,
       CAN_FIRE_deadlock_checkStarted_get,
       CAN_FIRE_deadlock_commitInstStuck_get,
       CAN_FIRE_deadlock_commitUserInstStuck_get,
       CAN_FIRE_deadlock_dCacheCRqStuck_get,
       CAN_FIRE_deadlock_dCachePRqStuck_get,
       CAN_FIRE_deadlock_iCacheCRqStuck_get,
       CAN_FIRE_deadlock_iCachePRqStuck_get,
       CAN_FIRE_deadlock_renameCorrectPathStuck_get,
       CAN_FIRE_deadlock_renameInstStuck_get,
       CAN_FIRE_hart0_csr_mem_server_request_put,
       CAN_FIRE_hart0_csr_mem_server_response_get,
       CAN_FIRE_hart0_fpr_mem_server_request_put,
       CAN_FIRE_hart0_fpr_mem_server_response_get,
       CAN_FIRE_hart0_gpr_mem_server_request_put,
       CAN_FIRE_hart0_gpr_mem_server_response_get,
       CAN_FIRE_hart0_run_halt_server_request_put,
       CAN_FIRE_hart0_run_halt_server_response_get,
       CAN_FIRE_iCacheToParent_fromP_enq,
       CAN_FIRE_iCacheToParent_rqToP_deq,
       CAN_FIRE_iCacheToParent_rsToP_deq,
       CAN_FIRE_mmioToPlatform_cRq_deq,
       CAN_FIRE_mmioToPlatform_cRs_deq,
       CAN_FIRE_mmioToPlatform_pRq_enq,
       CAN_FIRE_mmioToPlatform_pRs_enq,
       CAN_FIRE_mmioToPlatform_setTime,
       CAN_FIRE_recvDoStats,
       CAN_FIRE_renameDebug_renameErr_get,
       CAN_FIRE_sendDoStats,
       CAN_FIRE_setMEIP,
       CAN_FIRE_setSEIP,
       CAN_FIRE_tlbToMem_memReq_deq,
       CAN_FIRE_tlbToMem_respLd_enq,
       CAN_FIRE_v_to_TV_0_get,
       CAN_FIRE_v_to_TV_1_get,
       WILL_FIRE_RL_commitStage_doCommitKilledLd,
       WILL_FIRE_RL_commitStage_doCommitNormalInst,
       WILL_FIRE_RL_commitStage_doCommitSystemInst,
       WILL_FIRE_RL_commitStage_doCommitTrap_flush,
       WILL_FIRE_RL_commitStage_doCommitTrap_handle,
       WILL_FIRE_RL_commitStage_doSetLSQAtCommit,
       WILL_FIRE_RL_commitStage_doSetLSQAtCommit_1,
       WILL_FIRE_RL_commitStage_notifyLSQCommit,
       WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv,
       WILL_FIRE_RL_commitStage_rl_send_tv_reset,
       WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu,
       WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu,
       WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F,
       WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T,
       WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu,
       WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu,
       WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu,
       WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F,
       WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T,
       WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu,
       WILL_FIRE_RL_coreFix_doFetchTrainBP,
       WILL_FIRE_RL_coreFix_doFetchTrainBP_1,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon,
       WILL_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq,
       WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize,
       WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem,
       WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq,
       WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue,
       WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq,
       WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault,
       WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue,
       WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault,
       WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence,
       WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq,
       WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault,
       WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue,
       WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq,
       WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue,
       WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem,
       WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault,
       WILL_FIRE_RL_coreFix_memExe_doDispatchMem,
       WILL_FIRE_RL_coreFix_memExe_doExeMem,
       WILL_FIRE_RL_coreFix_memExe_doFinishMem,
       WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ,
       WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate,
       WILL_FIRE_RL_coreFix_memExe_doIssueSB,
       WILL_FIRE_RL_coreFix_memExe_doRegReadMem,
       WILL_FIRE_RL_coreFix_memExe_doRespLdForward,
       WILL_FIRE_RL_coreFix_memExe_doRespLdMem,
       WILL_FIRE_RL_coreFix_memExe_forwardQ_canonicalize,
       WILL_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon,
       WILL_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize,
       WILL_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon,
       WILL_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon,
       WILL_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon,
       WILL_FIRE_RL_coreFix_memExe_reqLdQ_full_canon,
       WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon,
       WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon,
       WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon,
       WILL_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon,
       WILL_FIRE_RL_coreFix_memExe_reqStQ_empty_canon,
       WILL_FIRE_RL_coreFix_memExe_reqStQ_full_canon,
       WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize,
       WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon,
       WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_sendLdToMem,
       WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem,
       WILL_FIRE_RL_coreFix_memExe_sendStToMem,
       WILL_FIRE_RL_csrInstOrInterruptInflight_canon,
       WILL_FIRE_RL_csrf_incCycle,
       WILL_FIRE_RL_csrf_mcycle_ehr_data_canon,
       WILL_FIRE_RL_csrf_mcycle_ehr_setRead,
       WILL_FIRE_RL_csrf_minstret_ehr_data_canon,
       WILL_FIRE_RL_csrf_minstret_ehr_setRead,
       WILL_FIRE_RL_flushBrPred,
       WILL_FIRE_RL_flushCaches,
       WILL_FIRE_RL_mkConnectionGetPut,
       WILL_FIRE_RL_mkConnectionGetPut_1,
       WILL_FIRE_RL_mmio_cRqQ_canonicalize,
       WILL_FIRE_RL_mmio_cRqQ_clearReq_canon,
       WILL_FIRE_RL_mmio_cRqQ_deqReq_canon,
       WILL_FIRE_RL_mmio_cRqQ_enqReq_canon,
       WILL_FIRE_RL_mmio_cRsQ_canonicalize,
       WILL_FIRE_RL_mmio_cRsQ_clearReq_canon,
       WILL_FIRE_RL_mmio_cRsQ_deqReq_canon,
       WILL_FIRE_RL_mmio_cRsQ_enqReq_canon,
       WILL_FIRE_RL_mmio_dataPendQ_canonicalize,
       WILL_FIRE_RL_mmio_dataPendQ_clearReq_canon,
       WILL_FIRE_RL_mmio_dataPendQ_deqReq_canon,
       WILL_FIRE_RL_mmio_dataPendQ_enqReq_canon,
       WILL_FIRE_RL_mmio_dataReqQ_canonicalize,
       WILL_FIRE_RL_mmio_dataReqQ_clearReq_canon,
       WILL_FIRE_RL_mmio_dataReqQ_deqReq_canon,
       WILL_FIRE_RL_mmio_dataReqQ_enqReq_canon,
       WILL_FIRE_RL_mmio_dataRespQ_canonicalize,
       WILL_FIRE_RL_mmio_dataRespQ_clearReq_canon,
       WILL_FIRE_RL_mmio_dataRespQ_deqReq_canon,
       WILL_FIRE_RL_mmio_dataRespQ_enqReq_canon,
       WILL_FIRE_RL_mmio_handlePRq,
       WILL_FIRE_RL_mmio_pRqQ_canonicalize,
       WILL_FIRE_RL_mmio_pRqQ_clearReq_canon,
       WILL_FIRE_RL_mmio_pRqQ_deqReq_canon,
       WILL_FIRE_RL_mmio_pRqQ_enqReq_canon,
       WILL_FIRE_RL_mmio_pRsQ_canonicalize,
       WILL_FIRE_RL_mmio_pRsQ_clearReq_canon,
       WILL_FIRE_RL_mmio_pRsQ_deqReq_canon,
       WILL_FIRE_RL_mmio_pRsQ_enqReq_canon,
       WILL_FIRE_RL_mmio_sendDataReq,
       WILL_FIRE_RL_mmio_sendDataResp,
       WILL_FIRE_RL_mmio_sendInstReq,
       WILL_FIRE_RL_mmio_sendInstResp,
       WILL_FIRE_RL_prepareCachesAndTlbs,
       WILL_FIRE_RL_readyToFetch,
       WILL_FIRE_RL_renameStage_doRenaming,
       WILL_FIRE_RL_renameStage_doRenaming_SystemInst,
       WILL_FIRE_RL_renameStage_doRenaming_Trap,
       WILL_FIRE_RL_renameStage_doRenaming_wrongPath,
       WILL_FIRE_RL_rl_debug_csr_access_busy,
       WILL_FIRE_RL_rl_debug_csr_read,
       WILL_FIRE_RL_rl_debug_csr_write,
       WILL_FIRE_RL_rl_debug_fpr_access_busy,
       WILL_FIRE_RL_rl_debug_fpr_read,
       WILL_FIRE_RL_rl_debug_fpr_write,
       WILL_FIRE_RL_rl_debug_gpr_access_busy,
       WILL_FIRE_RL_rl_debug_gpr_read,
       WILL_FIRE_RL_rl_debug_gpr_write,
       WILL_FIRE_RL_rl_debug_halt_req,
       WILL_FIRE_RL_rl_debug_halt_req_already_halted,
       WILL_FIRE_RL_rl_debug_halted,
       WILL_FIRE_RL_rl_debug_resume,
       WILL_FIRE_RL_rl_debug_run_redundant,
       WILL_FIRE_RL_rl_outOfReset,
       WILL_FIRE_RL_sendDTlbReq,
       WILL_FIRE_RL_sendFlushDone,
       WILL_FIRE_RL_sendITlbReq,
       WILL_FIRE_RL_sendRobEnqTime,
       WILL_FIRE_RL_sendRsToDTlb,
       WILL_FIRE_RL_sendRsToITlb,
       WILL_FIRE_RL_setDoFlushBrPred,
       WILL_FIRE_RL_setDoFlushCaches,
       WILL_FIRE_coreIndInv_perfResp,
       WILL_FIRE_coreIndInv_terminate,
       WILL_FIRE_coreReq_perfReq,
       WILL_FIRE_coreReq_start,
       WILL_FIRE_dCacheToParent_fromP_enq,
       WILL_FIRE_dCacheToParent_rqToP_deq,
       WILL_FIRE_dCacheToParent_rsToP_deq,
       WILL_FIRE_deadlock_checkStarted_get,
       WILL_FIRE_deadlock_commitInstStuck_get,
       WILL_FIRE_deadlock_commitUserInstStuck_get,
       WILL_FIRE_deadlock_dCacheCRqStuck_get,
       WILL_FIRE_deadlock_dCachePRqStuck_get,
       WILL_FIRE_deadlock_iCacheCRqStuck_get,
       WILL_FIRE_deadlock_iCachePRqStuck_get,
       WILL_FIRE_deadlock_renameCorrectPathStuck_get,
       WILL_FIRE_deadlock_renameInstStuck_get,
       WILL_FIRE_hart0_csr_mem_server_request_put,
       WILL_FIRE_hart0_csr_mem_server_response_get,
       WILL_FIRE_hart0_fpr_mem_server_request_put,
       WILL_FIRE_hart0_fpr_mem_server_response_get,
       WILL_FIRE_hart0_gpr_mem_server_request_put,
       WILL_FIRE_hart0_gpr_mem_server_response_get,
       WILL_FIRE_hart0_run_halt_server_request_put,
       WILL_FIRE_hart0_run_halt_server_response_get,
       WILL_FIRE_iCacheToParent_fromP_enq,
       WILL_FIRE_iCacheToParent_rqToP_deq,
       WILL_FIRE_iCacheToParent_rsToP_deq,
       WILL_FIRE_mmioToPlatform_cRq_deq,
       WILL_FIRE_mmioToPlatform_cRs_deq,
       WILL_FIRE_mmioToPlatform_pRq_enq,
       WILL_FIRE_mmioToPlatform_pRs_enq,
       WILL_FIRE_mmioToPlatform_setTime,
       WILL_FIRE_recvDoStats,
       WILL_FIRE_renameDebug_renameErr_get,
       WILL_FIRE_sendDoStats,
       WILL_FIRE_setMEIP,
       WILL_FIRE_setSEIP,
       WILL_FIRE_tlbToMem_memReq_deq,
       WILL_FIRE_tlbToMem_respLd_enq,
       WILL_FIRE_v_to_TV_0_get,
       WILL_FIRE_v_to_TV_1_get;

  // inputs to muxes for submodule ports
  reg [63 : 0] MUX_coreFix_memExe_lsq$respLd_2__VAL_1,
	       MUX_coreFix_memExe_lsq$respLd_2__VAL_2,
	       MUX_fetchStage$redirect_1__VAL_6;
  reg [4 : 0] MUX_coreFix_memExe_lsq$respLd_1__VAL_1,
	      MUX_coreFix_memExe_lsq$respLd_1__VAL_2;
  reg [1 : 0] MUX_csrf_fs_reg$write_1__VAL_2, MUX_csrf_fs_reg$write_1__VAL_3;
  wire [861 : 0] MUX_v_f_to_TV_0$enq_1__VAL_1,
		 MUX_v_f_to_TV_0$enq_1__VAL_2,
		 MUX_v_f_to_TV_0$enq_1__VAL_4,
		 MUX_v_f_to_TV_0$enq_1__VAL_5;
  wire [583 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1,
		 MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2,
		 MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3,
		 MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4;
  wire [579 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1,
		 MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2;
  wire [569 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1,
		 MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2,
		 MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3,
		 MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4;
  wire [425 : 0] MUX_rob$enqPort_0_enq_1__VAL_1,
		 MUX_rob$enqPort_0_enq_1__VAL_2,
		 MUX_rob$enqPort_0_enq_1__VAL_3;
  wire [165 : 0] MUX_commitStage_commitTrap$write_1__VAL_2;
  wire [161 : 0] MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1,
		 MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2;
  wire [160 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1,
		 MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2;
  wire [159 : 0] MUX_coreFix_trainBPQ_0$enq_1__VAL_1,
		 MUX_coreFix_trainBPQ_0$enq_1__VAL_2,
		 MUX_coreFix_trainBPQ_1$enq_1__VAL_1,
		 MUX_coreFix_trainBPQ_1$enq_1__VAL_2;
  wire [152 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1,
		 MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2,
		 MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3,
		 MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1,
		 MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_2;
  wire [142 : 0] MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1,
		 MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2,
		 MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1,
		 MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_2;
  wire [69 : 0] MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1,
		MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2,
		MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1;
  wire [67 : 0] MUX_coreFix_memExe_lsq$issueLd_4__VAL_1;
  wire [64 : 0] MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1,
		MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2,
		MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3,
		MUX_f_csr_rsps$enq_1__VAL_3,
		MUX_f_fpr_rsps$enq_1__VAL_3;
  wire [63 : 0] MUX_commitStage_rg_serial_num$write_1__VAL_1,
		MUX_commitStage_rg_serial_num$write_1__VAL_3,
		MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2,
		MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1,
		MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2,
		MUX_csrf_mtval_csr$write_1__VAL_1,
		MUX_csrf_rg_dcsr$write_1__VAL_2,
		MUX_csrf_sepc_csr$write_1__VAL_1,
		MUX_csrf_stval_csr$write_1__VAL_1,
		MUX_rf$write_2_wr_2__VAL_2,
		MUX_rf$write_2_wr_2__VAL_3,
		MUX_rf$write_2_wr_2__VAL_4,
		MUX_rf$write_2_wr_2__VAL_5,
		MUX_rf$write_2_wr_2__VAL_6,
		MUX_rf$write_3_wr_2__VAL_3,
		MUX_rf$write_3_wr_2__VAL_4;
  wire [58 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1,
		MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2;
  wire [57 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1,
		MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2;
  wire [48 : 0] MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1,
		MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1;
  wire [29 : 0] MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1,
		MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2;
  wire [26 : 0] MUX_regRenamingTable$rename_0_getRename_1__VAL_2,
		MUX_regRenamingTable$rename_0_getRename_1__VAL_3;
  wire [7 : 0] MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1,
	       MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2,
	       MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3,
	       MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4,
	       MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5,
	       MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6,
	       MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1,
	       MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2,
	       MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
  wire [5 : 0] MUX_coreFix_memExe_lsq$getHit_1__VAL_1;
  wire [4 : 0] MUX_csrf_fflags_reg$write_1__VAL_1,
	       MUX_rob$setExecuted_deqLSQ_2__VAL_2,
	       MUX_rob$setExecuted_deqLSQ_2__VAL_6,
	       MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2,
	       MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3,
	       MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4;
  wire [3 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1,
	       MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1,
	       MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2;
  wire [2 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1,
	       MUX_csrf_frm_reg$write_1__VAL_1,
	       MUX_csrf_frm_reg$write_1__VAL_2;
  wire [1 : 0] MUX_csrf_mpp_reg$write_1__VAL_1,
	       MUX_csrf_prv_reg$write_1__VAL_1;
  wire MUX_commitStage_rg_run_state$write_1__SEL_1,
       MUX_commitStage_rg_serial_num$write_1__SEL_1,
       MUX_commitStage_rg_serial_num$write_1__SEL_2,
       MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1,
       MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3,
       MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4,
       MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1,
       MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2,
       MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1,
       MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2,
       MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1,
       MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1,
       MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2,
       MUX_coreFix_memExe_lsq$getHit_1__SEL_1,
       MUX_coreFix_memExe_lsq$getHit_1__SEL_2,
       MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1,
       MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1,
       MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1,
       MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1,
       MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2,
       MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1,
       MUX_coreFix_trainBPQ_0$enq_1__SEL_1,
       MUX_coreFix_trainBPQ_1$enq_1__SEL_1,
       MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1,
       MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2,
       MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1,
       MUX_csrf_external_int_en_vec_1$write_1__SEL_1,
       MUX_csrf_external_int_en_vec_3$write_1__SEL_1,
       MUX_csrf_external_int_pend_vec_1$write_1__SEL_1,
       MUX_csrf_external_int_pend_vec_1$write_1__SEL_2,
       MUX_csrf_fflags_reg$write_1__SEL_1,
       MUX_csrf_fflags_reg$write_1__SEL_2,
       MUX_csrf_fflags_reg$write_1__SEL_3,
       MUX_csrf_frm_reg$write_1__SEL_1,
       MUX_csrf_fs_reg$write_1__SEL_2,
       MUX_csrf_fs_reg$write_1__SEL_3,
       MUX_csrf_ie_vec_0$write_1__SEL_1,
       MUX_csrf_ie_vec_0$write_1__SEL_2,
       MUX_csrf_ie_vec_1$write_1__SEL_1,
       MUX_csrf_ie_vec_1$write_1__SEL_2,
       MUX_csrf_ie_vec_1$write_1__VAL_1,
       MUX_csrf_ie_vec_3$write_1__SEL_1,
       MUX_csrf_ie_vec_3$write_1__SEL_2,
       MUX_csrf_ie_vec_3$write_1__SEL_3,
       MUX_csrf_ie_vec_3$write_1__VAL_1,
       MUX_csrf_mcause_code_reg$write_1__SEL_1,
       MUX_csrf_mcause_code_reg$write_1__SEL_3,
       MUX_csrf_mcounteren_cy_reg$write_1__SEL_1,
       MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1,
       MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_2,
       MUX_csrf_medeleg_13_11_reg$write_1__SEL_1,
       MUX_csrf_mepc_csr$write_1__SEL_1,
       MUX_csrf_mepc_csr$write_1__SEL_3,
       MUX_csrf_mideleg_11_reg$write_1__SEL_1,
       MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1,
       MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_2,
       MUX_csrf_mpp_reg$write_1__SEL_1,
       MUX_csrf_mscratch_csr$write_1__SEL_1,
       MUX_csrf_mtval_csr$write_1__SEL_1,
       MUX_csrf_mtval_csr$write_1__SEL_3,
       MUX_csrf_mtvec_base_hi_reg$write_1__SEL_1,
       MUX_csrf_ppn_reg$write_1__SEL_1,
       MUX_csrf_prev_ie_vec_1$write_1__SEL_1,
       MUX_csrf_prev_ie_vec_1$write_1__VAL_1,
       MUX_csrf_prev_ie_vec_3$write_1__SEL_1,
       MUX_csrf_prev_ie_vec_3$write_1__VAL_1,
       MUX_csrf_prv_reg$write_1__SEL_1,
       MUX_csrf_prv_reg$write_1__SEL_3,
       MUX_csrf_rg_dcsr$write_1__SEL_1,
       MUX_csrf_rg_dpc$write_1__SEL_1,
       MUX_csrf_rg_dpc$write_1__SEL_3,
       MUX_csrf_rg_dscratch0$write_1__SEL_1,
       MUX_csrf_rg_dscratch1$write_1__SEL_1,
       MUX_csrf_rg_tdata1_data$write_1__SEL_1,
       MUX_csrf_rg_tdata2$write_1__SEL_1,
       MUX_csrf_rg_tdata3$write_1__SEL_1,
       MUX_csrf_rg_tselect$write_1__SEL_1,
       MUX_csrf_scause_code_reg$write_1__SEL_1,
       MUX_csrf_scause_code_reg$write_1__SEL_3,
       MUX_csrf_scounteren_cy_reg$write_1__SEL_1,
       MUX_csrf_sepc_csr$write_1__SEL_1,
       MUX_csrf_sepc_csr$write_1__SEL_3,
       MUX_csrf_spp_reg$write_1__SEL_1,
       MUX_csrf_spp_reg$write_1__VAL_1,
       MUX_csrf_sscratch_csr$write_1__SEL_1,
       MUX_csrf_stats_module_writeQ$enq_1__SEL_1,
       MUX_csrf_stval_csr$write_1__SEL_1,
       MUX_csrf_stval_csr$write_1__SEL_3,
       MUX_csrf_stvec_base_hi_reg$write_1__SEL_1,
       MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2,
       MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2,
       MUX_f_run_halt_rsps$enq_1__SEL_1,
       MUX_flush_reservation$write_1__SEL_1,
       MUX_flush_tlbs$write_1__SEL_1,
       MUX_regRenamingTable$rename_0_getRename_1__SEL_1,
       MUX_regRenamingTable$rename_0_getRename_1__SEL_2,
       MUX_regRenamingTable$rename_0_getRename_1__SEL_3,
       MUX_renameStage_rg_m_halt_req$write_1__SEL_1,
       MUX_renameStage_rg_m_halt_req$write_1__SEL_2,
       MUX_renameStage_rg_m_halt_req$write_1__SEL_3,
       MUX_renameStage_rg_m_halt_req$write_1__SEL_6,
       MUX_rf$write_3_wr_1__PSEL_5,
       MUX_rf$write_3_wr_1__SEL_1,
       MUX_rf$write_3_wr_1__SEL_2,
       MUX_rf$write_3_wr_1__SEL_3,
       MUX_rf$write_3_wr_1__SEL_4,
       MUX_rf$write_3_wr_1__SEL_5,
       MUX_rf$write_3_wr_2__SEL_5,
       MUX_rg_core_run_state$write_1__SEL_4,
       MUX_rob$setExecuted_deqLSQ_1__SEL_1,
       MUX_rob$setExecuted_doFinishMem_RegData_1__SEL_5,
       MUX_rob$setExecuted_doFinishMem_RegData_2__SEL_5,
       MUX_sbAggr$setReady_4_put_1__SEL_1,
       MUX_sbAggr$setReady_4_put_1__SEL_2,
       MUX_sbCons$setReady_3_put_1__SEL_1,
       MUX_sbCons$setReady_3_put_1__SEL_2,
       MUX_sbCons$setReady_3_put_1__SEL_3,
       MUX_v_f_to_TV_0$enq_1__SEL_2;

  // remaining internal signals
  reg [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2500;
  reg [63 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q295,
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q296,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q22,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q23,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q24,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q25,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q26,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q260,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9944,
	       SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2875,
	       addr__h290069,
	       curData__h192918,
	       data_out__h738339,
	       data_warl_xformed__h723426,
	       rVal1__h609052,
	       rVal1__h633784,
	       trap_val__h711491,
	       x__h197128,
	       x__h724034;
  reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15,
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17,
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19,
	       CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219,
	       CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220,
	       CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217,
	       CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218,
	       CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q205,
	       CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q206,
	       CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207,
	       CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208,
	       CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209,
	       CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210,
	       CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q221,
	       CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q222,
	       CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q223,
	       CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q224,
	       CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q225,
	       CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q226,
	       CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215,
	       CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874;
  reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348,
	       SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398;
  reg [22 : 0] CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82,
	       CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83,
	       CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q86,
	       CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q87,
	       CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q88,
	       CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q89,
	       CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q119,
	       CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q120,
	       CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49,
	       CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50,
	       CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q117,
	       CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q118,
	       CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47,
	       CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48,
	       CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q121,
	       CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q122,
	       CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q51,
	       CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q52,
	       CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q123,
	       CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q124,
	       CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q53,
	       CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q54,
	       CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84,
	       CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85,
	       _theResult___fst_sfd__h346070,
	       _theResult___fst_sfd__h354793,
	       _theResult___fst_sfd__h363375,
	       _theResult___fst_sfd__h372559,
	       _theResult___fst_sfd__h381195,
	       _theResult___fst_sfd__h391769,
	       _theResult___fst_sfd__h400490,
	       _theResult___fst_sfd__h409072,
	       _theResult___fst_sfd__h418256,
	       _theResult___fst_sfd__h426892,
	       _theResult___fst_sfd__h437464,
	       _theResult___fst_sfd__h446185,
	       _theResult___fst_sfd__h454767,
	       _theResult___fst_sfd__h463951,
	       _theResult___fst_sfd__h472587;
  reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q285,
	       CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231,
	       CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q282,
	       CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q291,
	       CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228,
	       CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q288,
	       CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298,
	       CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q294,
	       IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883,
	       IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599;
  reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359,
	       SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407;
  reg [11 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q279,
	       CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q286,
	       CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232,
	       CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q283,
	       CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q292,
	       CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229,
	       CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q289,
	       CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235,
	       CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246,
	       CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q300,
	       CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5,
	       CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1,
	       IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973;
  reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14,
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16,
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18,
	       CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q211,
	       CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q212,
	       CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q213,
	       CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q214,
	       CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q183,
	       CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q184,
	       CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q185,
	       CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q186,
	       CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q187,
	       CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q188,
	       CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q160,
	       CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q161,
	       CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q189,
	       CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q190,
	       CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191,
	       CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192,
	       CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q143,
	       CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q144,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803;
  reg [7 : 0] CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q67,
	      CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q68,
	      CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q75,
	      CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q76,
	      CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q80,
	      CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q81,
	      CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q104,
	      CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q105,
	      CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q34,
	      CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q35,
	      CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q102,
	      CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q103,
	      CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q32,
	      CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q33,
	      CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q110,
	      CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q111,
	      CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q40,
	      CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q41,
	      CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q115,
	      CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q116,
	      CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q45,
	      CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q46,
	      CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q69,
	      CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q70,
	      SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373,
	      SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420,
	      _theResult___fst_exp__h346069,
	      _theResult___fst_exp__h354792,
	      _theResult___fst_exp__h363374,
	      _theResult___fst_exp__h372558,
	      _theResult___fst_exp__h381194,
	      _theResult___fst_exp__h391768,
	      _theResult___fst_exp__h400489,
	      _theResult___fst_exp__h409071,
	      _theResult___fst_exp__h418255,
	      _theResult___fst_exp__h426891,
	      _theResult___fst_exp__h437463,
	      _theResult___fst_exp__h446184,
	      _theResult___fst_exp__h454766,
	      _theResult___fst_exp__h463950,
	      _theResult___fst_exp__h472586;
  reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q280,
	      CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9,
	      CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q276,
	      IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998;
  reg [4 : 0] IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14143,
	      IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14276;
  reg [3 : 0] CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234,
	      CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250,
	      CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251,
	      CASE_coreFix_memExe_dTlbprocResp_BITS_177_TO__ETC__q20,
	      CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q21,
	      CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q278,
	      CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q277,
	      CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247,
	      CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248,
	      CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q6,
	      CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q7,
	      CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q2,
	      CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q3,
	      IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146,
	      IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130,
	      IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14277,
	      i__h710467,
	      i__h710627;
  reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q284,
	      CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230,
	      CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q281,
	      CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q290,
	      CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227,
	      CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q287,
	      CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q297,
	      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259,
	      CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q293,
	      CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271,
	      CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233,
	      CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236,
	      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717,
	      x__h285848,
	      x__h291618;
  reg [1 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q249,
	      CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q267,
	      CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299,
	      CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269,
	      CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273,
	      CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265,
	      CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q252,
	      CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q301,
	      CASE_v_f_to_TV_0D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q8,
	      CASE_v_f_to_TV_1D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q4;
  reg CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204,
      CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268,
      CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q274,
      CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q275,
      CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270,
      CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266,
      CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243,
      CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244,
      CASE_fetchStage_pipelines_0_canDeq__2755_AND_N_ETC__q241,
      CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240,
      CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237,
      CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238,
      CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242,
      CASE_guard00503_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93,
      CASE_guard00503_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92,
      CASE_guard02881_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147,
      CASE_guard09433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95,
      CASE_guard09433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94,
      CASE_guard11950_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149,
      CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97,
      CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96,
      CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203,
      CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195,
      CASE_guard37491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126,
      CASE_guard37491_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125,
      CASE_guard41734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199,
      CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193,
      CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56,
      CASE_guard46097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55,
      CASE_guard46198_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128,
      CASE_guard46198_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127,
      CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201,
      CASE_guard50803_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197,
      CASE_guard54806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58,
      CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57,
      CASE_guard55128_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130,
      CASE_guard55128_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129,
      CASE_guard63736_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60,
      CASE_guard63736_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59,
      CASE_guard63964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132,
      CASE_guard63964_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131,
      CASE_guard71726_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172,
      CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162,
      CASE_guard72572_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62,
      CASE_guard72572_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61,
      CASE_guard81038_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168,
      CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164,
      CASE_guard90107_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170,
      CASE_guard90107_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166,
      CASE_guard91796_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91,
      CASE_guard91796_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90,
      CASE_guard93569_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145,
      CASE_k70634_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239,
      IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446,
      IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459,
      IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6463,
      IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476,
      IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489,
      IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502,
      IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509,
      IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6512,
      IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519,
      IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526,
      IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054,
      IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067,
      IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5071,
      IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084,
      IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097,
      IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110,
      IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117,
      IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5120,
      IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127,
      IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134,
      IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838,
      IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851,
      IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7855,
      IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868,
      IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881,
      IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894,
      IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901,
      IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7904,
      IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911,
      IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918,
      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10854,
      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10890,
      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10938,
      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10980,
      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d11022,
      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8396,
      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409,
      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8428,
      IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476,
      IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534,
      IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137,
      IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14140,
      IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13480,
      IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504,
      IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13539,
      IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13865,
      IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13887,
      IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13905,
      IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13960,
      IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962,
      IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13976,
      IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13983,
      IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14059,
      IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14071,
      IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14274,
      IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14275,
      IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917,
      IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14056,
      IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14083,
      SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497,
      SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14017,
      SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463,
      SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787;
  wire [581 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3247;
  wire [569 : 0] IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2510,
		 IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2521,
		 IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2523,
		 IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2522;
  wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2945;
  wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2208,
		 SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938,
		 SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16080;
  wire [463 : 0] commitStage_f_rob_data_first__4770_BIT_167_486_ETC___d14942;
  wire [457 : 0] rob_deqPort_0_deq_data__4354_BITS_161_TO_98_43_ETC___d15324;
  wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2008;
  wire [393 : 0] IF_commitStage_f_rob_data_first__4770_BITS_97__ETC___d14941;
  wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2203,
		 SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2929,
		 SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16071;
  wire [321 : 0] basicExec___d11943, basicExec___d12617;
  wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2003;
  wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2198,
		 SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2920,
		 SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16062;
  wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1998;
  wire [181 : 0] fetchStage_pipelines_0_first__2757_BIT_173_288_ETC___d13411;
  wire [144 : 0] coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d1706;
  wire [68 : 0] execFpuSimple___d11056;
  wire [65 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627,
		IF_rob_deqPort_0_deq_data__4354_BITS_97_TO_96__ETC___d14527;
  wire [64 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2570;
  wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9173,
		IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12448,
		IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12449,
		IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12460,
		IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12461,
		IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11774,
		IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11775,
		IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11786,
		IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11787,
		IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8336,
		IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8337,
		IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8347,
		IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8348,
		IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8358,
		IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8359,
		IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1648,
		IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1649,
		IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1659,
		IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1660,
		IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8070,
		IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10654,
		IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9174,
		IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9884,
		IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9940,
		IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567,
		IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1377,
		IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424,
		IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378,
		IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425,
		IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8,
		IF_rob_deqPort_0_deq_data__4354_BITS_329_TO_32_ETC___d15205,
		_theResult___fst__h603372,
		_theResult___snd__h603373,
		a___1__h603091,
		a___1__h603377,
		a__h602950,
		amoExec___d880,
		b___1__h603092,
		b___1__h603422,
		b__h602951,
		base__h713412,
		base__h713432,
		commitStage_rg_serial_num_4343_PLUS_IF_rob_deq_ETC___d15467,
		data___1__h475010,
		data___1__h475818,
		data__h475284,
		fcsr_csr__read__h609378,
		fflags_csr__read__h609353,
		frm_csr__read__h609364,
		mcause_csr__read__h611020,
		mcounteren_csr__read__h610765,
		medeleg_csr__read__h610372,
		mideleg_csr__read__h610467,
		mie_csr__read__h610591,
		mip_csr__read__h611253,
		mstatus_csr__read__h610224,
		mtvec_csr__read__h610673,
		n___1__h198531,
		n__h194456,
		n__read__h611357,
		n__read__h611548,
		n__read__h6761,
		n__read__h727667,
		new_mstatus___1__h727029,
		next_pc__h723452,
		pc__h713396,
		q___1__h475883,
		rVal1__h481763,
		rVal2__h481764,
		r___1__h475909,
		res_data__h337871,
		res_data__h337876,
		res_data__h383573,
		res_data__h383578,
		res_data__h429268,
		res_data__h429273,
		resp_addr__h291973,
		rg_tdata1__read__h612208,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245,
		satp_csr__read__h610081,
		scause_csr__read__h609878,
		scounteren_csr__read__h609740,
		shiftData__h181569,
		sie_csr__read__h609644,
		sip_csr__read__h610018,
		sstatus_csr__read__h609574,
		stvec_csr__read__h609687,
		trap_val__h710453,
		upd__h3994,
		upd__h5311,
		upd__h6875,
		upd__h727778,
		v__h607936,
		v__h632823,
		x__h153733,
		x__h157280,
		x__h160094,
		x__h161942,
		x__h181478,
		x__h181479,
		x__h18387,
		x__h183904,
		x__h20925,
		x__h287293,
		x__h289147,
		x__h46294,
		x__h481672,
		x__h481673,
		x__h481674,
		x__h48830,
		x__h617237,
		x__h617238,
		x__h639746,
		x__h639747,
		x__h703386,
		x__h715654,
		x__h715846,
		x__h727020,
		x__h727161,
		x__h733741,
		x_addr__h314076,
		x_quotient__h475198,
		x_reg_ifc__read__h609483,
		x_remainder__h475199,
		y__h731435,
		y__h734250,
		y_avValue__h180566,
		y_avValue__h181172,
		y_avValue__h478808,
		y_avValue__h479416,
		y_avValue__h480018,
		y_avValue__h608842,
		y_avValue__h615062,
		y_avValue__h633576,
		y_avValue__h637581,
		y_avValue_new_pc__h713188,
		y_avValue_new_pc__h713374,
		y_avValue_snd_snd_snd_snd_snd_fst__h731458,
		y_avValue_snd_snd_snd_snd_snd_fst__h734311,
		y_avValue_snd_snd_snd_snd_snd_fst__h734347,
		y_avValue_snd_snd_snd_snd_snd_snd_snd__h733723;
  wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10652,
		IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9882,
		IF_csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_c_ETC___d14935,
		r1__read__h613051,
		r1__read__h613455,
		r1__read__h613965,
		r1__read__h613970,
		r1__read__h613989,
		r1__read__h614222,
		r1__read__h614388,
		r1__read__h614481,
		r1__read__h614486,
		r1__read__h614505;
  wire [61 : 0] r1__read__h613053,
		r1__read__h613457,
		r1__read__h613972,
		r1__read__h613991,
		r1__read__h614224,
		r1__read__h614364,
		r1__read__h614390,
		r1__read__h614488,
		r1__read__h614507;
  wire [60 : 0] r1__read__h614226,
		r1__read__h614366,
		r1__read__h614392,
		r1__read__h614509;
  wire [59 : 0] r1__read__h613055,
		r1__read__h613459,
		r1__read__h613983,
		r1__read__h613993,
		r1__read__h614228,
		r1__read__h614394,
		r1__read__h614499,
		r1__read__h614511;
  wire [58 : 0] r1__read__h613057,
		r1__read__h613461,
		r1__read__h613995,
		r1__read__h614230,
		r1__read__h614396,
		r1__read__h614513;
  wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2550,
		IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3012,
		IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2713,
		r1__read__h613059,
		r1__read__h613463,
		r1__read__h613997,
		r1__read__h614232,
		r1__read__h614368,
		r1__read__h614398,
		r1__read__h614515,
		y__h254805;
  wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28,
		IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63,
		IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98,
		IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138,
		IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155,
		IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178,
		IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q108,
		IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q38,
		IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q73,
		IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134,
		IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141,
		IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151,
		IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158,
		IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174,
		IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181,
		IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q100,
		IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113,
		IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q30,
		IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43,
		IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q65,
		IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78,
		_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10138,
		_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8653,
		_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9368,
		_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558,
		_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950,
		_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342,
		_theResult____h346087,
		_theResult____h363726,
		_theResult____h391786,
		_theResult____h409423,
		_theResult____h437481,
		_theResult____h455118,
		_theResult____h502871,
		_theResult____h541724,
		_theResult____h581028,
		_theResult___snd__h354209,
		_theResult___snd__h354220,
		_theResult___snd__h354222,
		_theResult___snd__h354232,
		_theResult___snd__h354238,
		_theResult___snd__h354261,
		_theResult___snd__h362805,
		_theResult___snd__h362807,
		_theResult___snd__h362814,
		_theResult___snd__h362820,
		_theResult___snd__h362843,
		_theResult___snd__h371975,
		_theResult___snd__h371986,
		_theResult___snd__h371988,
		_theResult___snd__h371998,
		_theResult___snd__h372004,
		_theResult___snd__h372027,
		_theResult___snd__h380595,
		_theResult___snd__h380609,
		_theResult___snd__h380615,
		_theResult___snd__h380633,
		_theResult___snd__h399906,
		_theResult___snd__h399917,
		_theResult___snd__h399919,
		_theResult___snd__h399929,
		_theResult___snd__h399935,
		_theResult___snd__h399958,
		_theResult___snd__h408502,
		_theResult___snd__h408504,
		_theResult___snd__h408511,
		_theResult___snd__h408517,
		_theResult___snd__h408540,
		_theResult___snd__h417672,
		_theResult___snd__h417683,
		_theResult___snd__h417685,
		_theResult___snd__h417695,
		_theResult___snd__h417701,
		_theResult___snd__h417724,
		_theResult___snd__h426292,
		_theResult___snd__h426306,
		_theResult___snd__h426312,
		_theResult___snd__h426330,
		_theResult___snd__h445601,
		_theResult___snd__h445612,
		_theResult___snd__h445614,
		_theResult___snd__h445624,
		_theResult___snd__h445630,
		_theResult___snd__h445653,
		_theResult___snd__h454197,
		_theResult___snd__h454199,
		_theResult___snd__h454206,
		_theResult___snd__h454212,
		_theResult___snd__h454235,
		_theResult___snd__h463367,
		_theResult___snd__h463378,
		_theResult___snd__h463380,
		_theResult___snd__h463390,
		_theResult___snd__h463396,
		_theResult___snd__h463419,
		_theResult___snd__h471987,
		_theResult___snd__h472001,
		_theResult___snd__h472007,
		_theResult___snd__h472025,
		_theResult___snd__h501481,
		_theResult___snd__h501483,
		_theResult___snd__h501490,
		_theResult___snd__h501496,
		_theResult___snd__h501519,
		_theResult___snd__h511118,
		_theResult___snd__h511129,
		_theResult___snd__h511131,
		_theResult___snd__h511141,
		_theResult___snd__h511147,
		_theResult___snd__h511170,
		_theResult___snd__h519886,
		_theResult___snd__h519900,
		_theResult___snd__h519906,
		_theResult___snd__h519924,
		_theResult___snd__h540334,
		_theResult___snd__h540336,
		_theResult___snd__h540343,
		_theResult___snd__h540349,
		_theResult___snd__h540372,
		_theResult___snd__h549971,
		_theResult___snd__h549982,
		_theResult___snd__h549984,
		_theResult___snd__h549994,
		_theResult___snd__h550000,
		_theResult___snd__h550023,
		_theResult___snd__h558739,
		_theResult___snd__h558753,
		_theResult___snd__h558759,
		_theResult___snd__h558777,
		_theResult___snd__h579638,
		_theResult___snd__h579640,
		_theResult___snd__h579647,
		_theResult___snd__h579653,
		_theResult___snd__h579676,
		_theResult___snd__h589275,
		_theResult___snd__h589286,
		_theResult___snd__h589288,
		_theResult___snd__h589298,
		_theResult___snd__h589304,
		_theResult___snd__h589327,
		_theResult___snd__h598043,
		_theResult___snd__h598057,
		_theResult___snd__h598063,
		_theResult___snd__h598081,
		r1__read__h614234,
		r1__read__h614370,
		r1__read__h614400,
		r1__read__h614517,
		result__h364339,
		result__h410036,
		result__h455731,
		result__h503484,
		result__h542337,
		result__h581641,
		sfd__h338482,
		sfd__h384184,
		sfd__h429879,
		sfd__h482504,
		sfd__h521498,
		sfd__h560802,
		sfdin__h354192,
		sfdin__h371958,
		sfdin__h399889,
		sfdin__h417655,
		sfdin__h445584,
		sfdin__h463350,
		sfdin__h511101,
		sfdin__h549954,
		sfdin__h589258,
		x__h364436,
		x__h410133,
		x__h455828,
		x__h503579,
		x__h542432,
		x__h581736;
  wire [55 : 0] r1__read__h613061,
		r1__read__h613465,
		r1__read__h613999,
		r1__read__h614236,
		r1__read__h614402,
		r1__read__h614519;
  wire [54 : 0] r1__read__h613063,
		r1__read__h613467,
		r1__read__h614001,
		r1__read__h614238,
		r1__read__h614404,
		r1__read__h614521;
  wire [53 : 0] r1__read__h614347,
		r1__read__h614372,
		r1__read__h614406,
		r1__read__h614523,
		sfd__h501548,
		sfd__h511199,
		sfd__h519959,
		sfd__h540401,
		sfd__h550052,
		sfd__h558812,
		sfd__h579705,
		sfd__h589356,
		sfd__h598116,
		value__h346709,
		value__h392406,
		value__h438101;
  wire [52 : 0] r1__read__h614240,
		r1__read__h614349,
		r1__read__h614374,
		r1__read__h614408,
		r1__read__h614525;
  wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619,
		IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621,
		IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140,
		IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142,
		IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9849,
		IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9851,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10593,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10595,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9823,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9825,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9868,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9870,
		IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10651,
		IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9172,
		IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9881,
		_theResult___fst_sfd__h486458,
		_theResult___fst_sfd__h502286,
		_theResult___fst_sfd__h502289,
		_theResult___fst_sfd__h511937,
		_theResult___fst_sfd__h511940,
		_theResult___fst_sfd__h520721,
		_theResult___fst_sfd__h520724,
		_theResult___fst_sfd__h520733,
		_theResult___fst_sfd__h520739,
		_theResult___fst_sfd__h525311,
		_theResult___fst_sfd__h541139,
		_theResult___fst_sfd__h541142,
		_theResult___fst_sfd__h550790,
		_theResult___fst_sfd__h550793,
		_theResult___fst_sfd__h559574,
		_theResult___fst_sfd__h559577,
		_theResult___fst_sfd__h559586,
		_theResult___fst_sfd__h559592,
		_theResult___fst_sfd__h564615,
		_theResult___fst_sfd__h580443,
		_theResult___fst_sfd__h580446,
		_theResult___fst_sfd__h590094,
		_theResult___fst_sfd__h590097,
		_theResult___fst_sfd__h598878,
		_theResult___fst_sfd__h598881,
		_theResult___fst_sfd__h598890,
		_theResult___fst_sfd__h598896,
		_theResult___sfd__h502186,
		_theResult___sfd__h511837,
		_theResult___sfd__h520621,
		_theResult___sfd__h541039,
		_theResult___sfd__h550690,
		_theResult___sfd__h559474,
		_theResult___sfd__h580343,
		_theResult___sfd__h589994,
		_theResult___sfd__h598778,
		_theResult___snd_fst_sfd__h482458,
		_theResult___snd_fst_sfd__h502292,
		_theResult___snd_fst_sfd__h520727,
		_theResult___snd_fst_sfd__h521452,
		_theResult___snd_fst_sfd__h541145,
		_theResult___snd_fst_sfd__h559580,
		_theResult___snd_fst_sfd__h560756,
		_theResult___snd_fst_sfd__h580449,
		_theResult___snd_fst_sfd__h598884,
		out___1_sfd__h482206,
		out___1_sfd__h521200,
		out___1_sfd__h560504,
		out_sfd__h502189,
		out_sfd__h511840,
		out_sfd__h520624,
		out_sfd__h541042,
		out_sfd__h550693,
		out_sfd__h559477,
		out_sfd__h580346,
		out_sfd__h589997,
		out_sfd__h598781;
  wire [50 : 0] r1__read__h613065, r1__read__h614242;
  wire [49 : 0] r1__read__h614351;
  wire [48 : 0] r1__read__h613067, r1__read__h614244, r1__read__h614353;
  wire [47 : 0] r1__read_BITS_61_TO_14___h727088;
  wire [46 : 0] r1__read__h613069, r1__read__h614246;
  wire [45 : 0] r1__read__h613071, r1__read__h614248;
  wire [44 : 0] r1__read__h613073, r1__read__h614250;
  wire [43 : 0] r1__read__h613075, r1__read__h614252;
  wire [42 : 0] r1__read__h614254;
  wire [41 : 0] r1__read__h614256;
  wire [40 : 0] r1__read__h614258;
  wire [37 : 0] IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14149,
		IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14280;
  wire [31 : 0] IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133,
		coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12,
		coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11,
		coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10,
		data75284_BITS_31_TO_0__q13,
		imm__h655334,
		r1__read__h613077,
		r1__read__h614260,
		x__h193681,
		x__h337886,
		x__h383588,
		x__h429283,
		x__h76239,
		x_data__h66088,
		x_data_imm__h677666,
		x_data_imm__h693720;
  wire [29 : 0] r1__read__h613079, r1__read__h614262;
  wire [27 : 0] r1__read__h614264;
  wire [24 : 0] NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14181,
		sfd__h354290,
		sfd__h362872,
		sfd__h372056,
		sfd__h380668,
		sfd__h399987,
		sfd__h408569,
		sfd__h417753,
		sfd__h426365,
		sfd__h445682,
		sfd__h454264,
		sfd__h463448,
		sfd__h472060,
		value__h487087,
		value__h525940,
		value__h565244;
  wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957,
		IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959,
		IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349,
		IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351,
		IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7741,
		IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7743,
		IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5003,
		IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5005,
		IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6395,
		IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6397,
		IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7787,
		IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7789,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7760,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808,
		_theResult___fst_sfd__h354796,
		_theResult___fst_sfd__h363378,
		_theResult___fst_sfd__h372562,
		_theResult___fst_sfd__h381198,
		_theResult___fst_sfd__h381207,
		_theResult___fst_sfd__h381213,
		_theResult___fst_sfd__h400493,
		_theResult___fst_sfd__h409075,
		_theResult___fst_sfd__h418259,
		_theResult___fst_sfd__h426895,
		_theResult___fst_sfd__h426904,
		_theResult___fst_sfd__h426910,
		_theResult___fst_sfd__h446188,
		_theResult___fst_sfd__h454770,
		_theResult___fst_sfd__h463954,
		_theResult___fst_sfd__h472590,
		_theResult___fst_sfd__h472599,
		_theResult___fst_sfd__h472605,
		_theResult___sfd__h354715,
		_theResult___sfd__h363297,
		_theResult___sfd__h372481,
		_theResult___sfd__h381117,
		_theResult___sfd__h381219,
		_theResult___sfd__h400412,
		_theResult___sfd__h408994,
		_theResult___sfd__h418178,
		_theResult___sfd__h426814,
		_theResult___sfd__h426916,
		_theResult___sfd__h446107,
		_theResult___sfd__h454689,
		_theResult___sfd__h463873,
		_theResult___sfd__h472509,
		_theResult___sfd__h472611,
		_theResult___snd_fst_sfd__h338432,
		_theResult___snd_fst_sfd__h363381,
		_theResult___snd_fst_sfd__h381201,
		_theResult___snd_fst_sfd__h384134,
		_theResult___snd_fst_sfd__h409078,
		_theResult___snd_fst_sfd__h426898,
		_theResult___snd_fst_sfd__h429829,
		_theResult___snd_fst_sfd__h454773,
		_theResult___snd_fst_sfd__h472593,
		f1_sfd__h482143,
		f2_sfd__h521137,
		f3_sfd__h560441,
		out_f_sfd__h381496,
		out_f_sfd__h427193,
		out_f_sfd__h472888,
		out_sfd__h354718,
		out_sfd__h363300,
		out_sfd__h372484,
		out_sfd__h381120,
		out_sfd__h400415,
		out_sfd__h408997,
		out_sfd__h418181,
		out_sfd__h426817,
		out_sfd__h446110,
		out_sfd__h454692,
		out_sfd__h463876,
		out_sfd__h472512;
  wire [19 : 0] r1__read__h614199;
  wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824,
		_theResult____h651123,
		enabled_ints___1__h651648,
		enabled_ints__h651694,
		pend_ints__h651121,
		y__h651660;
  wire [13 : 0] r1__read_BITS_13_TO_0___h651670;
  wire [12 : 0] IF_rob_deqPort_0_deq_data__4354_BITS_329_TO_32_ETC___d15314,
		fetchStage_pipelines_1_first__2766_BIT_173_360_ETC___d13691,
		rob_deqPort_0_deq_data__4354_BIT_181_4429_CONC_ETC___d14520;
  wire [11 : 0] IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10431,
		IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8946,
		IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9661,
		IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698,
		SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131,
		SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8646,
		SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9361,
		SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137,
		SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154,
		SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177,
		SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5943,
		SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72,
		SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4551,
		SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37,
		SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7335,
		SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107,
		_0_CONCAT_csrf_external_int_en_vec_3_read__1664_ETC___d12798,
		_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4011,
		_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5403,
		_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6795,
		_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10134,
		_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8649,
		_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9364,
		_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009,
		_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509,
		_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239,
		_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554,
		_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946,
		_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338,
		csr_addr__h655332,
		renaming_spec_bits__h686248,
		result__h646700,
		result__h646751,
		spec_bits__h689407,
		w__h646695,
		x__h364469,
		x__h410166,
		x__h455861,
		x__h503612,
		x__h542465,
		x__h581769,
		x__h646699,
		x__h646750,
		y__h646729,
		y__h689420,
		y_avValue_fst__h682580,
		y_avValue_fst__h682609,
		y_avValue_fst__h682643;
  wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536,
		IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538,
		IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056,
		IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9058,
		IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766,
		IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10498,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10500,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10569,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9013,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9015,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9087,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9089,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9728,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9730,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799,
		SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140,
		SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157,
		SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180,
		_theResult___exp__h502185,
		_theResult___exp__h511836,
		_theResult___exp__h520620,
		_theResult___exp__h541038,
		_theResult___exp__h550689,
		_theResult___exp__h559473,
		_theResult___exp__h580342,
		_theResult___exp__h589993,
		_theResult___exp__h598777,
		_theResult___fst_exp__h486457,
		_theResult___fst_exp__h501521,
		_theResult___fst_exp__h501527,
		_theResult___fst_exp__h501530,
		_theResult___fst_exp__h502285,
		_theResult___fst_exp__h502288,
		_theResult___fst_exp__h511107,
		_theResult___fst_exp__h511172,
		_theResult___fst_exp__h511178,
		_theResult___fst_exp__h511181,
		_theResult___fst_exp__h511936,
		_theResult___fst_exp__h511939,
		_theResult___fst_exp__h519892,
		_theResult___fst_exp__h519931,
		_theResult___fst_exp__h519937,
		_theResult___fst_exp__h519940,
		_theResult___fst_exp__h520720,
		_theResult___fst_exp__h520723,
		_theResult___fst_exp__h520732,
		_theResult___fst_exp__h520735,
		_theResult___fst_exp__h525310,
		_theResult___fst_exp__h540374,
		_theResult___fst_exp__h540380,
		_theResult___fst_exp__h540383,
		_theResult___fst_exp__h541138,
		_theResult___fst_exp__h541141,
		_theResult___fst_exp__h549960,
		_theResult___fst_exp__h550025,
		_theResult___fst_exp__h550031,
		_theResult___fst_exp__h550034,
		_theResult___fst_exp__h550789,
		_theResult___fst_exp__h550792,
		_theResult___fst_exp__h558745,
		_theResult___fst_exp__h558784,
		_theResult___fst_exp__h558790,
		_theResult___fst_exp__h558793,
		_theResult___fst_exp__h559573,
		_theResult___fst_exp__h559576,
		_theResult___fst_exp__h559585,
		_theResult___fst_exp__h559588,
		_theResult___fst_exp__h564614,
		_theResult___fst_exp__h579678,
		_theResult___fst_exp__h579684,
		_theResult___fst_exp__h579687,
		_theResult___fst_exp__h580442,
		_theResult___fst_exp__h580445,
		_theResult___fst_exp__h589264,
		_theResult___fst_exp__h589329,
		_theResult___fst_exp__h589335,
		_theResult___fst_exp__h589338,
		_theResult___fst_exp__h590093,
		_theResult___fst_exp__h590096,
		_theResult___fst_exp__h598049,
		_theResult___fst_exp__h598088,
		_theResult___fst_exp__h598094,
		_theResult___fst_exp__h598097,
		_theResult___fst_exp__h598877,
		_theResult___fst_exp__h598880,
		_theResult___fst_exp__h598889,
		_theResult___fst_exp__h598892,
		_theResult___snd_fst_exp__h502291,
		_theResult___snd_fst_exp__h520726,
		_theResult___snd_fst_exp__h541144,
		_theResult___snd_fst_exp__h559579,
		_theResult___snd_fst_exp__h580448,
		_theResult___snd_fst_exp__h598883,
		coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q71,
		coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q36,
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q106,
		din_inc___2_exp__h520780,
		din_inc___2_exp__h520815,
		din_inc___2_exp__h520841,
		din_inc___2_exp__h559633,
		din_inc___2_exp__h559668,
		din_inc___2_exp__h559694,
		din_inc___2_exp__h598937,
		din_inc___2_exp__h598972,
		din_inc___2_exp__h598998,
		out_exp__h502188,
		out_exp__h511839,
		out_exp__h520623,
		out_exp__h541041,
		out_exp__h550692,
		out_exp__h559476,
		out_exp__h580345,
		out_exp__h589996,
		out_exp__h598780;
  wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4872,
	       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264,
	       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656;
  wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4310,
	       IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4313,
	       IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5702,
	       IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5705,
	       IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7094,
	       IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7097,
	       IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4857,
	       IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4859,
	       IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6249,
	       IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6251,
	       IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7641,
	       IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7643,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4532,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4534,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4926,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4928,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5924,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5926,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6318,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6320,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7316,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7318,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7710,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7712,
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q77,
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42,
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q112,
	       _theResult___exp__h354714,
	       _theResult___exp__h363296,
	       _theResult___exp__h372480,
	       _theResult___exp__h381116,
	       _theResult___exp__h381218,
	       _theResult___exp__h400411,
	       _theResult___exp__h408993,
	       _theResult___exp__h418177,
	       _theResult___exp__h426813,
	       _theResult___exp__h426915,
	       _theResult___exp__h446106,
	       _theResult___exp__h454688,
	       _theResult___exp__h463872,
	       _theResult___exp__h472508,
	       _theResult___exp__h472610,
	       _theResult___fst_exp__h354198,
	       _theResult___fst_exp__h354263,
	       _theResult___fst_exp__h354269,
	       _theResult___fst_exp__h354272,
	       _theResult___fst_exp__h354795,
	       _theResult___fst_exp__h362845,
	       _theResult___fst_exp__h362851,
	       _theResult___fst_exp__h362854,
	       _theResult___fst_exp__h363377,
	       _theResult___fst_exp__h371964,
	       _theResult___fst_exp__h372029,
	       _theResult___fst_exp__h372035,
	       _theResult___fst_exp__h372038,
	       _theResult___fst_exp__h372561,
	       _theResult___fst_exp__h380601,
	       _theResult___fst_exp__h380640,
	       _theResult___fst_exp__h380646,
	       _theResult___fst_exp__h380649,
	       _theResult___fst_exp__h381197,
	       _theResult___fst_exp__h381206,
	       _theResult___fst_exp__h381209,
	       _theResult___fst_exp__h399895,
	       _theResult___fst_exp__h399960,
	       _theResult___fst_exp__h399966,
	       _theResult___fst_exp__h399969,
	       _theResult___fst_exp__h400492,
	       _theResult___fst_exp__h408542,
	       _theResult___fst_exp__h408548,
	       _theResult___fst_exp__h408551,
	       _theResult___fst_exp__h409074,
	       _theResult___fst_exp__h417661,
	       _theResult___fst_exp__h417726,
	       _theResult___fst_exp__h417732,
	       _theResult___fst_exp__h417735,
	       _theResult___fst_exp__h418258,
	       _theResult___fst_exp__h426298,
	       _theResult___fst_exp__h426337,
	       _theResult___fst_exp__h426343,
	       _theResult___fst_exp__h426346,
	       _theResult___fst_exp__h426894,
	       _theResult___fst_exp__h426903,
	       _theResult___fst_exp__h426906,
	       _theResult___fst_exp__h445590,
	       _theResult___fst_exp__h445655,
	       _theResult___fst_exp__h445661,
	       _theResult___fst_exp__h445664,
	       _theResult___fst_exp__h446187,
	       _theResult___fst_exp__h454237,
	       _theResult___fst_exp__h454243,
	       _theResult___fst_exp__h454246,
	       _theResult___fst_exp__h454769,
	       _theResult___fst_exp__h463356,
	       _theResult___fst_exp__h463421,
	       _theResult___fst_exp__h463427,
	       _theResult___fst_exp__h463430,
	       _theResult___fst_exp__h463953,
	       _theResult___fst_exp__h471993,
	       _theResult___fst_exp__h472032,
	       _theResult___fst_exp__h472038,
	       _theResult___fst_exp__h472041,
	       _theResult___fst_exp__h472589,
	       _theResult___fst_exp__h472598,
	       _theResult___fst_exp__h472601,
	       _theResult___snd_fst_exp__h363380,
	       _theResult___snd_fst_exp__h381200,
	       _theResult___snd_fst_exp__h409077,
	       _theResult___snd_fst_exp__h426897,
	       _theResult___snd_fst_exp__h454772,
	       _theResult___snd_fst_exp__h472592,
	       din_inc___2_exp__h381231,
	       din_inc___2_exp__h381255,
	       din_inc___2_exp__h381285,
	       din_inc___2_exp__h381309,
	       din_inc___2_exp__h426928,
	       din_inc___2_exp__h426952,
	       din_inc___2_exp__h426982,
	       din_inc___2_exp__h427006,
	       din_inc___2_exp__h472623,
	       din_inc___2_exp__h472647,
	       din_inc___2_exp__h472677,
	       din_inc___2_exp__h472701,
	       f1_exp82142_MINUS_127__q136,
	       f1_exp__h482142,
	       f2_exp21136_MINUS_127__q176,
	       f2_exp__h521136,
	       f3_exp60440_MINUS_127__q153,
	       f3_exp__h560440,
	       out_exp__h354717,
	       out_exp__h363299,
	       out_exp__h372483,
	       out_exp__h381119,
	       out_exp__h400414,
	       out_exp__h408996,
	       out_exp__h418180,
	       out_exp__h426816,
	       out_exp__h446109,
	       out_exp__h454691,
	       out_exp__h463875,
	       out_exp__h472511,
	       out_f_exp__h381495,
	       out_f_exp__h427192,
	       out_f_exp__h472887,
	       x__h613036;
  wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247,
	       IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639,
	       IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031,
	       IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380,
	       IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895,
	       IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9610,
	       IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4798,
	       IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190,
	       IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313,
	       IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463,
	       IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172,
	       IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766,
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870,
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478,
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262,
	       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2144,
	       SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16106,
	       x__h181701,
	       x__h713427;
  wire [4 : 0] IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14321,
	       IF_rob_deqPort_0_canDeq__5346_THEN_IF_NOT_rob__ETC___d15673,
	       _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169,
	       _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6561,
	       _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7953,
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758,
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799,
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843,
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198,
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590,
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982,
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741,
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782,
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826,
	       _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5181,
	       _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6573,
	       _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965,
	       checkForException___d13008,
	       checkForException___d13713,
	       fflags__h734227,
	       old_fflags1__h733714,
	       po_fflags__h728951,
	       po_fflags__h731598,
	       r1__read__h614606,
	       res_fflags__h337872,
	       res_fflags__h383574,
	       res_fflags__h429269,
	       rob_deqPort_0_deq_data__4354_BIT_166_4370_CONC_ETC___d14419,
	       rs1__h655333,
	       x__h153727,
	       x__h157274,
	       x__h160090,
	       x__h287281,
	       y_avValue_fst__h730973,
	       y_avValue_fst__h734132,
	       y_avValue_fst__h734164;
  wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1851,
	       IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1853,
	       IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1855,
	       IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1857,
	       IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1859,
	       IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1861,
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13198,
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13199,
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13200,
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13201,
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13202,
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13203,
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13204,
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13205,
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13206,
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13207,
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13208,
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13209,
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13210,
	       IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243,
	       IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795,
	       IF_NOT_renameStage_rg_m_halt_req_2784_BIT_4_27_ETC___d13283,
	       IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159,
	       IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2836,
	       IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796,
	       IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255,
	       cause_code__h710452,
	       vm_mode_reg__read__h614205;
  wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2539,
	       IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2793,
	       IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212,
	       _theResult_____2__h296523,
	       dcsr_cause__h709971,
	       next_deqP___1__h296802,
	       v__h295943,
	       v__h296174,
	       x__h302153,
	       x_decodeInfo_frm__h655017;
  wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789,
	       IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208,
	       IF_rob_deqPort_0_canDeq__5346_THEN_IF_NOT_rob__ETC___d15692,
	       IF_sfdin11101_BIT_4_THEN_2_ELSE_0__q139,
	       IF_sfdin17655_BIT_33_THEN_2_ELSE_0__q74,
	       IF_sfdin45584_BIT_33_THEN_2_ELSE_0__q99,
	       IF_sfdin49954_BIT_4_THEN_2_ELSE_0__q179,
	       IF_sfdin54192_BIT_33_THEN_2_ELSE_0__q29,
	       IF_sfdin63350_BIT_33_THEN_2_ELSE_0__q109,
	       IF_sfdin71958_BIT_33_THEN_2_ELSE_0__q39,
	       IF_sfdin89258_BIT_4_THEN_2_ELSE_0__q156,
	       IF_sfdin99889_BIT_33_THEN_2_ELSE_0__q64,
	       IF_theResult___snd01481_BIT_4_THEN_2_ELSE_0__q135,
	       IF_theResult___snd08502_BIT_33_THEN_2_ELSE_0__q66,
	       IF_theResult___snd19886_BIT_4_THEN_2_ELSE_0__q142,
	       IF_theResult___snd26292_BIT_33_THEN_2_ELSE_0__q79,
	       IF_theResult___snd40334_BIT_4_THEN_2_ELSE_0__q175,
	       IF_theResult___snd54197_BIT_33_THEN_2_ELSE_0__q101,
	       IF_theResult___snd58739_BIT_4_THEN_2_ELSE_0__q182,
	       IF_theResult___snd62805_BIT_33_THEN_2_ELSE_0__q31,
	       IF_theResult___snd71987_BIT_33_THEN_2_ELSE_0__q114,
	       IF_theResult___snd79638_BIT_4_THEN_2_ELSE_0__q152,
	       IF_theResult___snd80595_BIT_33_THEN_2_ELSE_0__q44,
	       IF_theResult___snd98043_BIT_4_THEN_2_ELSE_0__q159,
	       guard__h346097,
	       guard__h354806,
	       guard__h363736,
	       guard__h372572,
	       guard__h391796,
	       guard__h400503,
	       guard__h409433,
	       guard__h418269,
	       guard__h437491,
	       guard__h446198,
	       guard__h455128,
	       guard__h463964,
	       guard__h493569,
	       guard__h502881,
	       guard__h511950,
	       guard__h532422,
	       guard__h541734,
	       guard__h550803,
	       guard__h571726,
	       guard__h581038,
	       guard__h590107,
	       prv__h735894,
	       prv__h735938,
	       r1__read_BITS_13_TO_12___h655202,
	       sbIdx__h157153,
	       v__h603885,
	       v__h603895,
	       v__h604530,
	       x__h723556,
	       x__h734491,
	       x_prv__h713496,
	       x_prv__h724014,
	       y_avValue_snd_snd_snd_fst__h731448,
	       y_avValue_snd_snd_snd_fst__h734301,
	       y_avValue_snd_snd_snd_fst__h734337;
  wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5069,
       IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5119,
       IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6461,
       IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6511,
       IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7853,
       IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7903,
       IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10424,
       IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10691,
       IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d8939,
       IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9654,
       IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9922,
       IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10470,
       IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10676,
       IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10703,
       IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8985,
       IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9700,
       IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9907,
       IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9934,
       IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13052,
       IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13771,
       IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13808,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10474,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10706,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10707,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10803,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10847,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10862,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10872,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10883,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10902,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10916,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10931,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10948,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10960,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10990,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11002,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11015,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8989,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9704,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9937,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9938,
       IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10129,
       IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8644,
       IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9359,
       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12237,
       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12238,
       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12239,
       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12262,
       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12263,
       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12264,
       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11377,
       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11378,
       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11379,
       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11402,
       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11403,
       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11404,
       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8241,
       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8242,
       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8243,
       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8265,
       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8266,
       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8267,
       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8289,
       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8290,
       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8291,
       IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1603,
       IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1604,
       IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1605,
       IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1627,
       IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1628,
       IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1629,
       IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2086,
       IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2103,
       IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13923,
       IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13931,
       IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13846,
       IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13930,
       IF_NOT_rob_deqPort_1_deq_data__5354_BIT_25_535_ETC___d15683,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10472,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10705,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10900,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10914,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10929,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10946,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10958,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10971,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10988,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11000,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11013,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8987,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9702,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9936,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5099,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5136,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5227,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5240,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5253,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6491,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6528,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6619,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6632,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6645,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7883,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7920,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8011,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8024,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8037,
       IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2181_ETC___d12213,
       IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2181_ETC___d12247,
       IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1321_ETC___d11353,
       IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1321_ETC___d11387,
       IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8217,
       IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8250,
       IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8274,
       IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6532,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6493,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6530,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6594,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6605,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6621,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6634,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6647,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5101,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5138,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5202,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5213,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5229,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5242,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5255,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7885,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7922,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7986,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7997,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8013,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8026,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8039,
       IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5140,
       IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7924,
       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10678,
       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8430,
       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9909,
       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2084,
       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2104,
       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2107,
       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031,
       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3046,
       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3058,
       IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3138,
       IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3153,
       IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3160,
       IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3180,
       IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3004,
       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2047,
       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2049,
       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2050,
       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2058,
       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2106,
       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2108,
       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2704,
       IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3309,
       IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3324,
       IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3332,
       IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3405,
       IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3420,
       IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3428,
       IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3447,
       IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1744,
       IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1800,
       IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1804,
       IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1808,
       IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1812,
       IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1816,
       IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1820,
       IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1824,
       IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1828,
       IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1832,
       IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1836,
       IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1840,
       IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1844,
       IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1848,
       IF_coreFix_memExe_dispToRegQ_RDY_first__549_AN_ETC___d1579,
       IF_coreFix_memExe_dispToRegQ_RDY_first__549_AN_ETC___d1612,
       IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3750,
       IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3743,
       IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3728,
       IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3656,
       IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3649,
       IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3634,
       IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3558,
       IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13450,
       IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13848,
       IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13920,
       IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13969,
       IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14099,
       IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339,
       IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783,
       IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46,
       IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201,
       IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642,
       IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491,
       IF_rob_deqPort_1_canDeq__5351_THEN_IF_NOT_rob__ETC___d15684,
       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5221,
       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5249,
       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6613,
       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6641,
       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8005,
       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8033,
       NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13344,
       NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13437,
       NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13740,
       NOT_IF_NOT_rob_deqPort_0_canDeq__5346_5347_OR__ETC___d15689,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10765,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10865,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10905,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10951,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10993,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286,
       NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13499,
       NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14639,
       NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14646,
       NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710,
       NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15020,
       NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15031,
       NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15400,
       NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12229,
       NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12257,
       NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11369,
       NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11397,
       NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8233,
       NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8260,
       NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8284,
       NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815,
       NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423,
       NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207,
       NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1595,
       NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1622,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2526,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2666,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3057,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3078,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3127,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3183,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2123,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2533,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2535,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2557,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2561,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2564,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2578,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2581,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2592,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2598,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2605,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2630,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2638,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2646,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2655,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2677,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3298,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3355,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3394,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3451,
       NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1883,
       NOT_coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_ETC___d1927,
       NOT_coreFix_memExe_dTlb_procResp__714_BITS_246_ETC___d1755,
       NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3717,
       NOT_coreFix_memExe_forwardQ_enqReq_dummy2_2_re_ETC___d3772,
       NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3623,
       NOT_coreFix_memExe_memRespLdQ_enqReq_dummy2_2__ETC___d3678,
       NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1474,
       NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1024,
       NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3547,
       NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3589,
       NOT_coreFix_memExe_respLrScAmoQ_full_952_953_A_ETC___d2082,
       NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13337,
       NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13435,
       NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13738,
       NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757,
       NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13542,
       NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13785,
       NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13829,
       NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13884,
       NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13902,
       NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14051,
       NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14105,
       NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14204,
       NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209,
       NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14211,
       NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14223,
       NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14267,
       NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268,
       NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14298,
       NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13331,
       NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13481,
       NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13761,
       NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13767,
       NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13928,
       NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112,
       NOT_fetchStage_pipelines_0_first__2757_BIT_68__ETC___d13492,
       NOT_fetchStage_pipelines_1_canDeq__2763_2764_O_ETC___d12772,
       NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13515,
       NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13754,
       NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13871,
       NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14220,
       NOT_fetchStage_pipelines_1_first__2766_BIT_68__ETC___d14217,
       NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431,
       NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452,
       NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823,
       NOT_mmio_cRsQ_enqReq_dummy2_2_read__24_39_OR_I_ETC___d844,
       NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091,
       NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390,
       NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325,
       NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140,
       NOT_mmio_dataReqQ_enqReq_dummy2_2_read__41_56__ETC___d161,
       NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241,
       NOT_mmio_dataRespQ_enqReq_dummy2_2_read__42_57_ETC___d262,
       NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734,
       NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755,
       NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593,
       NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614,
       NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13776,
       NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13852,
       NOT_regRenamingTable_rename_0_canRename__3418__ETC___d14199,
       NOT_regRenamingTable_rename_1_canRename__3545__ETC___d13816,
       NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13102,
       NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13442,
       NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13751,
       NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13893,
       NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13911,
       NOT_rob_deqPort_0_canDeq__5346_5347_OR_regRena_ETC___d15388,
       NOT_rob_deqPort_0_canDeq__5346_5347_OR_rob_deq_ETC___d15667,
       NOT_rob_deqPort_0_deq_data__4354_BITS_329_TO_3_ETC___d15008,
       NOT_rob_deqPort_1_deq_data__5354_BIT_25_5355_5_ETC___d15385,
       NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14022,
       NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14089,
       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132,
       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133,
       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647,
       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648,
       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362,
       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363,
       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944,
       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945,
       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552,
       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553,
       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336,
       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337,
       _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4249,
       _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5641,
       _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7033,
       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10382,
       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8897,
       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9612,
       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4800,
       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6192,
       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7584,
       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10085,
       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10432,
       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8585,
       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8947,
       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9315,
       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9662,
       _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4480,
       _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4873,
       _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5872,
       _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6265,
       _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7264,
       _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7657,
       _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13943,
       _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13844,
       _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d14035,
       _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14339,
       _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14731,
       _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14713,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5184,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5209,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5236,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6576,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6601,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6628,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7968,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7993,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8020,
       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010,
       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012,
       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510,
       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512,
       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240,
       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242,
       _dfoo12,
       _dfoo16,
       _dfoo18,
       _dfoo2,
       _dfoo20,
       _dfoo24,
       _dfoo26,
       _dfoo32,
       _dfoo7,
       _dor1coreFix_aluExe_0_bypassWire_2$EN_wset,
       _dor1coreFix_aluExe_0_bypassWire_3$EN_wset,
       _dor1coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put,
       _dor1coreFix_aluExe_1_bypassWire_2$EN_wset,
       _dor1coreFix_aluExe_1_bypassWire_3$EN_wset,
       _dor1coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put,
       _dor1coreFix_fpuMulDivExe_0_bypassWire_2$EN_wset,
       _dor1coreFix_fpuMulDivExe_0_bypassWire_3$EN_wset,
       _dor1coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put,
       _dor1coreFix_memExe_bypassWire_2$EN_wset,
       _dor1coreFix_memExe_bypassWire_3$EN_wset,
       _dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write,
       _dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write,
       _dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write,
       _dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset,
       _dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write,
       _dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write,
       _dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset,
       _dor1coreFix_memExe_rsMem$EN_setRegReady_3_put,
       _dor1rf$EN_write_0_wr,
       _dor1rf$EN_write_1_wr,
       _dor1sbAggr$EN_setReady_3_put,
       _dor1sbCons$EN_setReady_0_put,
       _dor1sbCons$EN_setReady_1_put,
       _theResult_____2__h304519,
       _theResult_____2__h310513,
       _theResult_____2__h318367,
       _theResult_____2__h328711,
       _theResult_____2__h331936,
       commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669,
       coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205,
       coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12244,
       coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12218,
       coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12250,
       coreFix_aluExe_0_bypassWire_2_wget__2224_BITS__ETC___d12226,
       coreFix_aluExe_0_bypassWire_2_wget__2224_BITS__ETC___d12254,
       coreFix_aluExe_0_dispToRegQ_first__2182_BIT_13_ETC___d12267,
       coreFix_aluExe_0_exeToFinQ_RDY_first__2641_AND_ETC___d12680,
       coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459,
       coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11345,
       coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11384,
       coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11358,
       coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11390,
       coreFix_aluExe_1_bypassWire_2_wget__1364_BITS__ETC___d11366,
       coreFix_aluExe_1_bypassWire_2_wget__1364_BITS__ETC___d11394,
       coreFix_aluExe_1_dispToRegQ_first__1322_BIT_13_ETC___d11407,
       coreFix_aluExe_1_exeToFinQ_RDY_first__1967_AND_ETC___d12007,
       coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8209,
       coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8247,
       coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8271,
       coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8222,
       coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8253,
       coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8277,
       coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8230,
       coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8257,
       coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8281,
       coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5272,
       coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3880,
       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6664,
       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d8103,
       coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8056,
       coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10852,
       coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10888,
       coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10936,
       coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10978,
       coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d11020,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14042,
       coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1571,
       coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1609,
       coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1584,
       coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1615,
       coreFix_memExe_bypassWire_2_wget__590_BITS_70__ETC___d1592,
       coreFix_memExe_bypassWire_2_wget__590_BITS_70__ETC___d1619,
       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2577,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3067,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3170,
       coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2070,
       coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150,
       coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2727,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2531,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2560,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2565,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2582,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2599,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2619,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2622,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2643,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2649,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2651,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2697,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2700,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2797,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2801,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2805,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2810,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2814,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2823,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2828,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2848,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enq_ETC___d3341,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enq_ETC___d3437,
       coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2_r_ETC___d1911,
       coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1726,
       coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1727,
       coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1731,
       coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1734,
       coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735,
       coreFix_memExe_forwardQ_enqReq_dummy2_2_read___ETC___d3759,
       coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3665,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1220,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1229,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1233,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267,
       coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3574,
       coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14671,
       csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13045,
       csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13517,
       csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13806,
       csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733,
       csrf_prv_reg_read__2787_ULE_1___d14711,
       csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040,
       csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13513,
       epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13749,
       epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13891,
       epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13909,
       f_csr_rsps_i_notFull__5799_AND_f_csr_reqs_firs_ETC___d15902,
       fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309,
       fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14033,
       fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14115,
       fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14191,
       fetchStage_pipelines_0_canDeq__2755_AND_fetchS_ETC___d14103,
       fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14039,
       fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14046,
       fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14068,
       fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14080,
       fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14311,
       fetchStage_pipelines_0_canDeq__2755_AND_specTa_ETC___d14167,
       fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13038,
       fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13760,
       fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13859,
       fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13971,
       fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13977,
       fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13994,
       fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14006,
       fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14013,
       fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14029,
       fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13524,
       fetchStage_pipelines_0_first__2757_BIT_68_2786_ETC___d13850,
       fetchStage_pipelines_1_first__2766_BITS_194_TO_ETC___d13988,
       fetchStage_pipelines_1_first__2766_BITS_199_TO_ETC___d14000,
       guard__h364334,
       guard__h410031,
       guard__h455726,
       guard__h503479,
       guard__h542332,
       guard__h581636,
       idx__h686379,
       k__h670634,
       mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444,
       mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836,
       mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312,
       mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153,
       mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254,
       mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13055,
       mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13347,
       mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13365,
       mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14107,
       mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14109,
       mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747,
       mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606,
       next_deqP___1__h304798,
       next_deqP___1__h311079,
       next_deqP___1__h318933,
       next_deqP___1__h328990,
       next_deqP___1__h332215,
       r1__read_BIT_20___h655898,
       r__h614580,
       regRenamingTable_RDY_commit_0_commit__4953_AND_ETC___d15013,
       regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13956,
       regRenamingTable_RDY_rename_1_getRename__4019__ETC___d14037,
       regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444,
       regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494,
       regRenamingTable_rename_0_canRename__3418_AND__ETC___d13508,
       regRenamingTable_rename_0_canRename__3418_AND__ETC___d13838,
       regRenamingTable_rename_0_canRename__3418_AND__ETC___d13985,
       regRenamingTable_rename_0_canRename__3418_AND__ETC___d14127,
       regRenamingTable_rename_0_canRename__3418_AND__ETC___d14133,
       regRenamingTable_rename_0_canRename__3418_AND__ETC___d14153,
       regRenamingTable_rename_0_canRename__3418_AND__ETC___d14161,
       regRenamingTable_rename_0_canRename__3418_AND__ETC___d14309,
       regRenamingTable_rename_1_canRename__3545_AND__ETC___d13753,
       regRenamingTable_rename_1_canRename__3545_AND__ETC___d13895,
       regRenamingTable_rename_1_canRename__3545_AND__ETC___d13913,
       regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219,
       regRenamingTable_rename_1_canRename__3545_AND__ETC___d14263,
       renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_N_ETC___d13068,
       renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_N_ETC___d13299,
       renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13774,
       renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13814,
       renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855,
       renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935,
       rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15738,
       rob_RDY_enqPort_1_enq__4085_AND_NOT_fetchStage_ETC___d14093,
       sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8294,
       sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8295,
       sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1632,
       tsr_val__h727281,
       tvm_val__h727283,
       v__h299288,
       v__h299806,
       v__h309802,
       v__h310033,
       v__h313678,
       v__h313909,
       v__h328279,
       v__h328510,
       v__h331504,
       v__h331735,
       x__h603386;

  // action method coreReq_start
  assign RDY_coreReq_start = !renameStage_rg_m_halt_req[4] ;
  assign CAN_FIRE_coreReq_start = !renameStage_rg_m_halt_req[4] ;
  assign WILL_FIRE_coreReq_start = EN_coreReq_start ;

  // action method coreReq_perfReq
  assign RDY_coreReq_perfReq = perfReqQ$FULL_N ;
  assign CAN_FIRE_coreReq_perfReq = perfReqQ$FULL_N ;
  assign WILL_FIRE_coreReq_perfReq = EN_coreReq_perfReq ;

  // actionvalue method coreIndInv_perfResp
  assign coreIndInv_perfResp = { perfReqQ$D_OUT, 64'd0 } ;
  assign RDY_coreIndInv_perfResp = perfReqQ$EMPTY_N ;
  assign CAN_FIRE_coreIndInv_perfResp = perfReqQ$EMPTY_N ;
  assign WILL_FIRE_coreIndInv_perfResp = EN_coreIndInv_perfResp ;

  // action method coreIndInv_terminate
  assign RDY_coreIndInv_terminate = csrf_terminate_module_terminateQ$EMPTY_N ;
  assign CAN_FIRE_coreIndInv_terminate =
	     csrf_terminate_module_terminateQ$EMPTY_N ;
  assign WILL_FIRE_coreIndInv_terminate = EN_coreIndInv_terminate ;

  // value method dCacheToParent_rsToP_notEmpty
  assign dCacheToParent_rsToP_notEmpty =
	     !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
  assign RDY_dCacheToParent_rsToP_notEmpty = 1'd1 ;

  // action method dCacheToParent_rsToP_deq
  assign RDY_dCacheToParent_rsToP_deq =
	     !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
  assign CAN_FIRE_dCacheToParent_rsToP_deq =
	     !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
  assign WILL_FIRE_dCacheToParent_rsToP_deq = EN_dCacheToParent_rsToP_deq ;

  // value method dCacheToParent_rsToP_first
  assign dCacheToParent_rsToP_first =
	     { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265,
	       !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266,
	       SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16080 } ;
  assign RDY_dCacheToParent_rsToP_first =
	     !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;

  // value method dCacheToParent_rqToP_notEmpty
  assign dCacheToParent_rqToP_notEmpty =
	     !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
  assign RDY_dCacheToParent_rqToP_notEmpty = 1'd1 ;

  // action method dCacheToParent_rqToP_deq
  assign RDY_dCacheToParent_rqToP_deq =
	     !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
  assign CAN_FIRE_dCacheToParent_rqToP_deq =
	     !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
  assign WILL_FIRE_dCacheToParent_rqToP_deq = EN_dCacheToParent_rqToP_deq ;

  // value method dCacheToParent_rqToP_first
  assign dCacheToParent_rqToP_first =
	     { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273,
	       SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16106 } ;
  assign RDY_dCacheToParent_rqToP_first =
	     !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;

  // value method dCacheToParent_fromP_notFull
  assign dCacheToParent_fromP_notFull =
	     !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
  assign RDY_dCacheToParent_fromP_notFull = 1'd1 ;

  // action method dCacheToParent_fromP_enq
  assign RDY_dCacheToParent_fromP_enq =
	     !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
  assign CAN_FIRE_dCacheToParent_fromP_enq =
	     !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
  assign WILL_FIRE_dCacheToParent_fromP_enq = EN_dCacheToParent_fromP_enq ;

  // value method iCacheToParent_rsToP_notEmpty
  assign iCacheToParent_rsToP_notEmpty =
	     fetchStage$iMemIfc_to_parent_rsToP_notEmpty ;
  assign RDY_iCacheToParent_rsToP_notEmpty = 1'd1 ;

  // action method iCacheToParent_rsToP_deq
  assign RDY_iCacheToParent_rsToP_deq =
	     fetchStage$RDY_iMemIfc_to_parent_rsToP_deq ;
  assign CAN_FIRE_iCacheToParent_rsToP_deq =
	     fetchStage$RDY_iMemIfc_to_parent_rsToP_deq ;
  assign WILL_FIRE_iCacheToParent_rsToP_deq = EN_iCacheToParent_rsToP_deq ;

  // value method iCacheToParent_rsToP_first
  assign iCacheToParent_rsToP_first =
	     fetchStage$iMemIfc_to_parent_rsToP_first ;
  assign RDY_iCacheToParent_rsToP_first =
	     fetchStage$RDY_iMemIfc_to_parent_rsToP_first ;

  // value method iCacheToParent_rqToP_notEmpty
  assign iCacheToParent_rqToP_notEmpty =
	     fetchStage$iMemIfc_to_parent_rqToP_notEmpty ;
  assign RDY_iCacheToParent_rqToP_notEmpty = 1'd1 ;

  // action method iCacheToParent_rqToP_deq
  assign RDY_iCacheToParent_rqToP_deq =
	     fetchStage$RDY_iMemIfc_to_parent_rqToP_deq ;
  assign CAN_FIRE_iCacheToParent_rqToP_deq =
	     fetchStage$RDY_iMemIfc_to_parent_rqToP_deq ;
  assign WILL_FIRE_iCacheToParent_rqToP_deq = EN_iCacheToParent_rqToP_deq ;

  // value method iCacheToParent_rqToP_first
  assign iCacheToParent_rqToP_first =
	     fetchStage$iMemIfc_to_parent_rqToP_first ;
  assign RDY_iCacheToParent_rqToP_first =
	     fetchStage$RDY_iMemIfc_to_parent_rqToP_first ;

  // value method iCacheToParent_fromP_notFull
  assign iCacheToParent_fromP_notFull =
	     fetchStage$iMemIfc_to_parent_fromP_notFull ;
  assign RDY_iCacheToParent_fromP_notFull = 1'd1 ;

  // action method iCacheToParent_fromP_enq
  assign RDY_iCacheToParent_fromP_enq =
	     fetchStage$RDY_iMemIfc_to_parent_fromP_enq ;
  assign CAN_FIRE_iCacheToParent_fromP_enq =
	     fetchStage$RDY_iMemIfc_to_parent_fromP_enq ;
  assign WILL_FIRE_iCacheToParent_fromP_enq = EN_iCacheToParent_fromP_enq ;

  // value method tlbToMem_memReq_notEmpty
  assign tlbToMem_memReq_notEmpty = l2Tlb$toMem_memReq_notEmpty ;
  assign RDY_tlbToMem_memReq_notEmpty = 1'd1 ;

  // action method tlbToMem_memReq_deq
  assign RDY_tlbToMem_memReq_deq = l2Tlb$RDY_toMem_memReq_deq ;
  assign CAN_FIRE_tlbToMem_memReq_deq = l2Tlb$RDY_toMem_memReq_deq ;
  assign WILL_FIRE_tlbToMem_memReq_deq = EN_tlbToMem_memReq_deq ;

  // value method tlbToMem_memReq_first
  assign tlbToMem_memReq_first = l2Tlb$toMem_memReq_first ;
  assign RDY_tlbToMem_memReq_first = l2Tlb$RDY_toMem_memReq_first ;

  // value method tlbToMem_respLd_notFull
  assign tlbToMem_respLd_notFull = l2Tlb$toMem_respLd_notFull ;
  assign RDY_tlbToMem_respLd_notFull = 1'd1 ;

  // action method tlbToMem_respLd_enq
  assign RDY_tlbToMem_respLd_enq = l2Tlb$RDY_toMem_respLd_enq ;
  assign CAN_FIRE_tlbToMem_respLd_enq = l2Tlb$RDY_toMem_respLd_enq ;
  assign WILL_FIRE_tlbToMem_respLd_enq = EN_tlbToMem_respLd_enq ;

  // value method mmioToPlatform_cRq_notEmpty
  assign mmioToPlatform_cRq_notEmpty = !mmio_cRqQ_empty ;
  assign RDY_mmioToPlatform_cRq_notEmpty = 1'd1 ;

  // action method mmioToPlatform_cRq_deq
  assign RDY_mmioToPlatform_cRq_deq = !mmio_cRqQ_empty ;
  assign CAN_FIRE_mmioToPlatform_cRq_deq = !mmio_cRqQ_empty ;
  assign WILL_FIRE_mmioToPlatform_cRq_deq = EN_mmioToPlatform_cRq_deq ;

  // value method mmioToPlatform_cRq_first
  assign mmioToPlatform_cRq_first =
	     { mmio_cRqQ_data_0[141:78],
	       CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9,
	       mmio_cRqQ_data_0[71:0] } ;
  assign RDY_mmioToPlatform_cRq_first = !mmio_cRqQ_empty ;

  // value method mmioToPlatform_pRs_notFull
  assign mmioToPlatform_pRs_notFull = !mmio_pRsQ_full ;
  assign RDY_mmioToPlatform_pRs_notFull = 1'd1 ;

  // action method mmioToPlatform_pRs_enq
  assign RDY_mmioToPlatform_pRs_enq = !mmio_pRsQ_full ;
  assign CAN_FIRE_mmioToPlatform_pRs_enq = !mmio_pRsQ_full ;
  assign WILL_FIRE_mmioToPlatform_pRs_enq = EN_mmioToPlatform_pRs_enq ;

  // value method mmioToPlatform_pRq_notFull
  assign mmioToPlatform_pRq_notFull = !mmio_pRqQ_full ;
  assign RDY_mmioToPlatform_pRq_notFull = 1'd1 ;

  // action method mmioToPlatform_pRq_enq
  assign RDY_mmioToPlatform_pRq_enq = !mmio_pRqQ_full ;
  assign CAN_FIRE_mmioToPlatform_pRq_enq = !mmio_pRqQ_full ;
  assign WILL_FIRE_mmioToPlatform_pRq_enq = EN_mmioToPlatform_pRq_enq ;

  // value method mmioToPlatform_cRs_notEmpty
  assign mmioToPlatform_cRs_notEmpty = !mmio_cRsQ_empty ;
  assign RDY_mmioToPlatform_cRs_notEmpty = 1'd1 ;

  // action method mmioToPlatform_cRs_deq
  assign RDY_mmioToPlatform_cRs_deq = !mmio_cRsQ_empty ;
  assign CAN_FIRE_mmioToPlatform_cRs_deq = !mmio_cRsQ_empty ;
  assign WILL_FIRE_mmioToPlatform_cRs_deq = EN_mmioToPlatform_cRs_deq ;

  // value method mmioToPlatform_cRs_first
  assign mmioToPlatform_cRs_first = mmio_cRsQ_data_0 ;
  assign RDY_mmioToPlatform_cRs_first = !mmio_cRsQ_empty ;

  // action method mmioToPlatform_setTime
  assign RDY_mmioToPlatform_setTime = 1'd1 ;
  assign CAN_FIRE_mmioToPlatform_setTime = 1'd1 ;
  assign WILL_FIRE_mmioToPlatform_setTime = EN_mmioToPlatform_setTime ;

  // actionvalue method sendDoStats
  assign sendDoStats = csrf_stats_module_writeQ$D_OUT ;
  assign RDY_sendDoStats = csrf_stats_module_writeQ$EMPTY_N ;
  assign CAN_FIRE_sendDoStats = csrf_stats_module_writeQ$EMPTY_N ;
  assign WILL_FIRE_sendDoStats = EN_sendDoStats ;

  // action method recvDoStats
  assign RDY_recvDoStats = 1'd1 ;
  assign CAN_FIRE_recvDoStats = 1'd1 ;
  assign WILL_FIRE_recvDoStats = EN_recvDoStats ;

  // actionvalue method deadlock_dCacheCRqStuck_get
  assign deadlock_dCacheCRqStuck_get = 73'h0AAAAAAAAAAAAAAAAAA ;
  assign RDY_deadlock_dCacheCRqStuck_get = 1'd0 ;
  assign CAN_FIRE_deadlock_dCacheCRqStuck_get = 1'd0 ;
  assign WILL_FIRE_deadlock_dCacheCRqStuck_get =
	     EN_deadlock_dCacheCRqStuck_get ;

  // actionvalue method deadlock_dCachePRqStuck_get
  assign deadlock_dCachePRqStuck_get = 68'hAAAAAAAAAAAAAAAAA ;
  assign RDY_deadlock_dCachePRqStuck_get = 1'd0 ;
  assign CAN_FIRE_deadlock_dCachePRqStuck_get = 1'd0 ;
  assign WILL_FIRE_deadlock_dCachePRqStuck_get =
	     EN_deadlock_dCachePRqStuck_get ;

  // actionvalue method deadlock_iCacheCRqStuck_get
  assign deadlock_iCacheCRqStuck_get = fetchStage$iMemIfc_cRqStuck_get ;
  assign RDY_deadlock_iCacheCRqStuck_get =
	     fetchStage$RDY_iMemIfc_cRqStuck_get ;
  assign CAN_FIRE_deadlock_iCacheCRqStuck_get =
	     fetchStage$RDY_iMemIfc_cRqStuck_get ;
  assign WILL_FIRE_deadlock_iCacheCRqStuck_get =
	     EN_deadlock_iCacheCRqStuck_get ;

  // actionvalue method deadlock_iCachePRqStuck_get
  assign deadlock_iCachePRqStuck_get = fetchStage$iMemIfc_pRqStuck_get ;
  assign RDY_deadlock_iCachePRqStuck_get =
	     fetchStage$RDY_iMemIfc_pRqStuck_get ;
  assign CAN_FIRE_deadlock_iCachePRqStuck_get =
	     fetchStage$RDY_iMemIfc_pRqStuck_get ;
  assign WILL_FIRE_deadlock_iCachePRqStuck_get =
	     EN_deadlock_iCachePRqStuck_get ;

  // actionvalue method deadlock_renameInstStuck_get
  assign deadlock_renameInstStuck_get = 78'h2AAAAAAAAAAAAAAAAAAA ;
  assign RDY_deadlock_renameInstStuck_get = 1'd0 ;
  assign CAN_FIRE_deadlock_renameInstStuck_get = 1'd0 ;
  assign WILL_FIRE_deadlock_renameInstStuck_get =
	     EN_deadlock_renameInstStuck_get ;

  // actionvalue method deadlock_renameCorrectPathStuck_get
  assign deadlock_renameCorrectPathStuck_get = 78'h2AAAAAAAAAAAAAAAAAAA ;
  assign RDY_deadlock_renameCorrectPathStuck_get = 1'd0 ;
  assign CAN_FIRE_deadlock_renameCorrectPathStuck_get = 1'd0 ;
  assign WILL_FIRE_deadlock_renameCorrectPathStuck_get =
	     EN_deadlock_renameCorrectPathStuck_get ;

  // actionvalue method deadlock_commitInstStuck_get
  assign deadlock_commitInstStuck_get =
	     163'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
  assign RDY_deadlock_commitInstStuck_get = 1'd0 ;
  assign CAN_FIRE_deadlock_commitInstStuck_get = 1'd0 ;
  assign WILL_FIRE_deadlock_commitInstStuck_get =
	     EN_deadlock_commitInstStuck_get ;

  // actionvalue method deadlock_commitUserInstStuck_get
  assign deadlock_commitUserInstStuck_get =
	     163'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
  assign RDY_deadlock_commitUserInstStuck_get = 1'd0 ;
  assign CAN_FIRE_deadlock_commitUserInstStuck_get = 1'd0 ;
  assign WILL_FIRE_deadlock_commitUserInstStuck_get =
	     EN_deadlock_commitUserInstStuck_get ;

  // action method deadlock_checkStarted_get
  assign RDY_deadlock_checkStarted_get = 1'd0 ;
  assign CAN_FIRE_deadlock_checkStarted_get = 1'd0 ;
  assign WILL_FIRE_deadlock_checkStarted_get = EN_deadlock_checkStarted_get ;

  // actionvalue method renameDebug_renameErr_get
  assign renameDebug_renameErr_get = 89'h0AAAAAAAAAAAAAAAAAAAAAA ;
  assign RDY_renameDebug_renameErr_get = 1'd0 ;
  assign CAN_FIRE_renameDebug_renameErr_get = 1'd0 ;
  assign WILL_FIRE_renameDebug_renameErr_get = EN_renameDebug_renameErr_get ;

  // action method setMEIP
  assign RDY_setMEIP = 1'd1 ;
  assign CAN_FIRE_setMEIP = 1'd1 ;
  assign WILL_FIRE_setMEIP = EN_setMEIP ;

  // action method setSEIP
  assign RDY_setSEIP = 1'd1 ;
  assign CAN_FIRE_setSEIP = 1'd1 ;
  assign WILL_FIRE_setSEIP = EN_setSEIP ;

  // action method hart0_run_halt_server_request_put
  assign RDY_hart0_run_halt_server_request_put = f_run_halt_reqs$FULL_N ;
  assign CAN_FIRE_hart0_run_halt_server_request_put = f_run_halt_reqs$FULL_N ;
  assign WILL_FIRE_hart0_run_halt_server_request_put =
	     EN_hart0_run_halt_server_request_put ;

  // actionvalue method hart0_run_halt_server_response_get
  assign hart0_run_halt_server_response_get = f_run_halt_rsps$D_OUT ;
  assign RDY_hart0_run_halt_server_response_get = f_run_halt_rsps$EMPTY_N ;
  assign CAN_FIRE_hart0_run_halt_server_response_get =
	     f_run_halt_rsps$EMPTY_N ;
  assign WILL_FIRE_hart0_run_halt_server_response_get =
	     EN_hart0_run_halt_server_response_get ;

  // action method hart0_gpr_mem_server_request_put
  assign RDY_hart0_gpr_mem_server_request_put = f_gpr_reqs$FULL_N ;
  assign CAN_FIRE_hart0_gpr_mem_server_request_put = f_gpr_reqs$FULL_N ;
  assign WILL_FIRE_hart0_gpr_mem_server_request_put =
	     EN_hart0_gpr_mem_server_request_put ;

  // actionvalue method hart0_gpr_mem_server_response_get
  assign hart0_gpr_mem_server_response_get = f_gpr_rsps$D_OUT ;
  assign RDY_hart0_gpr_mem_server_response_get = f_gpr_rsps$EMPTY_N ;
  assign CAN_FIRE_hart0_gpr_mem_server_response_get = f_gpr_rsps$EMPTY_N ;
  assign WILL_FIRE_hart0_gpr_mem_server_response_get =
	     EN_hart0_gpr_mem_server_response_get ;

  // action method hart0_fpr_mem_server_request_put
  assign RDY_hart0_fpr_mem_server_request_put = f_fpr_reqs$FULL_N ;
  assign CAN_FIRE_hart0_fpr_mem_server_request_put = f_fpr_reqs$FULL_N ;
  assign WILL_FIRE_hart0_fpr_mem_server_request_put =
	     EN_hart0_fpr_mem_server_request_put ;

  // actionvalue method hart0_fpr_mem_server_response_get
  assign hart0_fpr_mem_server_response_get = f_fpr_rsps$D_OUT ;
  assign RDY_hart0_fpr_mem_server_response_get = f_fpr_rsps$EMPTY_N ;
  assign CAN_FIRE_hart0_fpr_mem_server_response_get = f_fpr_rsps$EMPTY_N ;
  assign WILL_FIRE_hart0_fpr_mem_server_response_get =
	     EN_hart0_fpr_mem_server_response_get ;

  // action method hart0_csr_mem_server_request_put
  assign RDY_hart0_csr_mem_server_request_put = f_csr_reqs$FULL_N ;
  assign CAN_FIRE_hart0_csr_mem_server_request_put = f_csr_reqs$FULL_N ;
  assign WILL_FIRE_hart0_csr_mem_server_request_put =
	     EN_hart0_csr_mem_server_request_put ;

  // actionvalue method hart0_csr_mem_server_response_get
  assign hart0_csr_mem_server_response_get = f_csr_rsps$D_OUT ;
  assign RDY_hart0_csr_mem_server_response_get = f_csr_rsps$EMPTY_N ;
  assign CAN_FIRE_hart0_csr_mem_server_response_get = f_csr_rsps$EMPTY_N ;
  assign WILL_FIRE_hart0_csr_mem_server_response_get =
	     EN_hart0_csr_mem_server_response_get ;

  // actionvalue method v_to_TV_0_get
  assign v_to_TV_0_get =
	     { v_f_to_TV_0$D_OUT[861:476],
	       CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5,
	       v_f_to_TV_0$D_OUT[463:462],
	       v_f_to_TV_0$D_OUT[462] ?
		 CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q6 :
		 CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q7,
	       v_f_to_TV_0$D_OUT[457:394],
	       CASE_v_f_to_TV_0D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q8,
	       v_f_to_TV_0$D_OUT[391:0] } ;
  assign RDY_v_to_TV_0_get = v_f_to_TV_0$EMPTY_N ;
  assign CAN_FIRE_v_to_TV_0_get = v_f_to_TV_0$EMPTY_N ;
  assign WILL_FIRE_v_to_TV_0_get = EN_v_to_TV_0_get ;

  // actionvalue method v_to_TV_1_get
  assign v_to_TV_1_get =
	     { v_f_to_TV_1$D_OUT[861:476],
	       CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1,
	       v_f_to_TV_1$D_OUT[463:462],
	       v_f_to_TV_1$D_OUT[462] ?
		 CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q2 :
		 CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q3,
	       v_f_to_TV_1$D_OUT[457:394],
	       CASE_v_f_to_TV_1D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q4,
	       v_f_to_TV_1$D_OUT[391:0] } ;
  assign RDY_v_to_TV_1_get = v_f_to_TV_1$EMPTY_N ;
  assign CAN_FIRE_v_to_TV_1_get = v_f_to_TV_1$EMPTY_N ;
  assign WILL_FIRE_v_to_TV_1_get = EN_v_to_TV_1_get ;

  // submodule commitStage_f_rob_data
  FIFO2 #(.width(32'd426),
	  .guarded(32'd1)) commitStage_f_rob_data(.RST(RST_N),
						  .CLK(CLK),
						  .D_IN(commitStage_f_rob_data$D_IN),
						  .ENQ(commitStage_f_rob_data$ENQ),
						  .DEQ(commitStage_f_rob_data$DEQ),
						  .CLR(commitStage_f_rob_data$CLR),
						  .D_OUT(commitStage_f_rob_data$D_OUT),
						  .FULL_N(commitStage_f_rob_data$FULL_N),
						  .EMPTY_N(commitStage_f_rob_data$EMPTY_N));

  // submodule coreFix_aluExe_0_dispToRegQ
  mkAluDispToRegFifo coreFix_aluExe_0_dispToRegQ(.CLK(CLK),
						 .RST_N(RST_N),
						 .enq_x(coreFix_aluExe_0_dispToRegQ$enq_x),
						 .specUpdate_correctSpeculation_mask(coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask),
						 .specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
						 .specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
						 .EN_enq(coreFix_aluExe_0_dispToRegQ$EN_enq),
						 .EN_deq(coreFix_aluExe_0_dispToRegQ$EN_deq),
						 .EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation),
						 .EN_specUpdate_correctSpeculation(coreFix_aluExe_0_dispToRegQ$EN_specUpdate_correctSpeculation),
						 .RDY_enq(coreFix_aluExe_0_dispToRegQ$RDY_enq),
						 .RDY_deq(coreFix_aluExe_0_dispToRegQ$RDY_deq),
						 .first(coreFix_aluExe_0_dispToRegQ$first),
						 .RDY_first(coreFix_aluExe_0_dispToRegQ$RDY_first),
						 .RDY_specUpdate_incorrectSpeculation(),
						 .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_aluExe_0_exeToFinQ
  mkAluExeToFinFifo coreFix_aluExe_0_exeToFinQ(.CLK(CLK),
					       .RST_N(RST_N),
					       .enq_x(coreFix_aluExe_0_exeToFinQ$enq_x),
					       .specUpdate_correctSpeculation_mask(coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask),
					       .specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all),
					       .specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag),
					       .EN_enq(coreFix_aluExe_0_exeToFinQ$EN_enq),
					       .EN_deq(coreFix_aluExe_0_exeToFinQ$EN_deq),
					       .EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_exeToFinQ$EN_specUpdate_incorrectSpeculation),
					       .EN_specUpdate_correctSpeculation(coreFix_aluExe_0_exeToFinQ$EN_specUpdate_correctSpeculation),
					       .RDY_enq(coreFix_aluExe_0_exeToFinQ$RDY_enq),
					       .RDY_deq(coreFix_aluExe_0_exeToFinQ$RDY_deq),
					       .first(coreFix_aluExe_0_exeToFinQ$first),
					       .RDY_first(coreFix_aluExe_0_exeToFinQ$RDY_first),
					       .RDY_specUpdate_incorrectSpeculation(),
					       .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_aluExe_0_regToExeQ
  mkAluRegToExeFifo coreFix_aluExe_0_regToExeQ(.CLK(CLK),
					       .RST_N(RST_N),
					       .enq_x(coreFix_aluExe_0_regToExeQ$enq_x),
					       .specUpdate_correctSpeculation_mask(coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask),
					       .specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
					       .specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
					       .EN_enq(coreFix_aluExe_0_regToExeQ$EN_enq),
					       .EN_deq(coreFix_aluExe_0_regToExeQ$EN_deq),
					       .EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation),
					       .EN_specUpdate_correctSpeculation(coreFix_aluExe_0_regToExeQ$EN_specUpdate_correctSpeculation),
					       .RDY_enq(coreFix_aluExe_0_regToExeQ$RDY_enq),
					       .RDY_deq(coreFix_aluExe_0_regToExeQ$RDY_deq),
					       .first(coreFix_aluExe_0_regToExeQ$first),
					       .RDY_first(coreFix_aluExe_0_regToExeQ$RDY_first),
					       .RDY_specUpdate_incorrectSpeculation(),
					       .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_aluExe_0_rsAlu
  mkReservationStationAlu coreFix_aluExe_0_rsAlu(.CLK(CLK),
						 .RST_N(RST_N),
						 .enq_x(coreFix_aluExe_0_rsAlu$enq_x),
						 .setRegReady_0_put(coreFix_aluExe_0_rsAlu$setRegReady_0_put),
						 .setRegReady_1_put(coreFix_aluExe_0_rsAlu$setRegReady_1_put),
						 .setRegReady_2_put(coreFix_aluExe_0_rsAlu$setRegReady_2_put),
						 .setRegReady_3_put(coreFix_aluExe_0_rsAlu$setRegReady_3_put),
						 .setRegReady_4_put(coreFix_aluExe_0_rsAlu$setRegReady_4_put),
						 .setRobEnqTime_t(coreFix_aluExe_0_rsAlu$setRobEnqTime_t),
						 .specUpdate_correctSpeculation_mask(coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask),
						 .specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all),
						 .specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag),
						 .EN_enq(coreFix_aluExe_0_rsAlu$EN_enq),
						 .EN_setRobEnqTime(coreFix_aluExe_0_rsAlu$EN_setRobEnqTime),
						 .EN_doDispatch(coreFix_aluExe_0_rsAlu$EN_doDispatch),
						 .EN_setRegReady_0_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_0_put),
						 .EN_setRegReady_1_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_1_put),
						 .EN_setRegReady_2_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_2_put),
						 .EN_setRegReady_3_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put),
						 .EN_setRegReady_4_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_4_put),
						 .EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_rsAlu$EN_specUpdate_incorrectSpeculation),
						 .EN_specUpdate_correctSpeculation(coreFix_aluExe_0_rsAlu$EN_specUpdate_correctSpeculation),
						 .RDY_enq(coreFix_aluExe_0_rsAlu$RDY_enq),
						 .canEnq(coreFix_aluExe_0_rsAlu$canEnq),
						 .RDY_canEnq(),
						 .RDY_setRobEnqTime(),
						 .dispatchData(coreFix_aluExe_0_rsAlu$dispatchData),
						 .RDY_dispatchData(coreFix_aluExe_0_rsAlu$RDY_dispatchData),
						 .RDY_doDispatch(coreFix_aluExe_0_rsAlu$RDY_doDispatch),
						 .RDY_setRegReady_0_put(),
						 .RDY_setRegReady_1_put(),
						 .RDY_setRegReady_2_put(),
						 .RDY_setRegReady_3_put(),
						 .RDY_setRegReady_4_put(),
						 .approximateCount(coreFix_aluExe_0_rsAlu$approximateCount),
						 .RDY_approximateCount(),
						 .isFull_ehrPort0(),
						 .RDY_isFull_ehrPort0(),
						 .RDY_specUpdate_incorrectSpeculation(),
						 .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_aluExe_1_dispToRegQ
  mkAluDispToRegFifo coreFix_aluExe_1_dispToRegQ(.CLK(CLK),
						 .RST_N(RST_N),
						 .enq_x(coreFix_aluExe_1_dispToRegQ$enq_x),
						 .specUpdate_correctSpeculation_mask(coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask),
						 .specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
						 .specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
						 .EN_enq(coreFix_aluExe_1_dispToRegQ$EN_enq),
						 .EN_deq(coreFix_aluExe_1_dispToRegQ$EN_deq),
						 .EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_dispToRegQ$EN_specUpdate_incorrectSpeculation),
						 .EN_specUpdate_correctSpeculation(coreFix_aluExe_1_dispToRegQ$EN_specUpdate_correctSpeculation),
						 .RDY_enq(coreFix_aluExe_1_dispToRegQ$RDY_enq),
						 .RDY_deq(coreFix_aluExe_1_dispToRegQ$RDY_deq),
						 .first(coreFix_aluExe_1_dispToRegQ$first),
						 .RDY_first(coreFix_aluExe_1_dispToRegQ$RDY_first),
						 .RDY_specUpdate_incorrectSpeculation(),
						 .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_aluExe_1_exeToFinQ
  mkAluExeToFinFifo coreFix_aluExe_1_exeToFinQ(.CLK(CLK),
					       .RST_N(RST_N),
					       .enq_x(coreFix_aluExe_1_exeToFinQ$enq_x),
					       .specUpdate_correctSpeculation_mask(coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask),
					       .specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all),
					       .specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag),
					       .EN_enq(coreFix_aluExe_1_exeToFinQ$EN_enq),
					       .EN_deq(coreFix_aluExe_1_exeToFinQ$EN_deq),
					       .EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_exeToFinQ$EN_specUpdate_incorrectSpeculation),
					       .EN_specUpdate_correctSpeculation(coreFix_aluExe_1_exeToFinQ$EN_specUpdate_correctSpeculation),
					       .RDY_enq(coreFix_aluExe_1_exeToFinQ$RDY_enq),
					       .RDY_deq(coreFix_aluExe_1_exeToFinQ$RDY_deq),
					       .first(coreFix_aluExe_1_exeToFinQ$first),
					       .RDY_first(coreFix_aluExe_1_exeToFinQ$RDY_first),
					       .RDY_specUpdate_incorrectSpeculation(),
					       .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_aluExe_1_regToExeQ
  mkAluRegToExeFifo coreFix_aluExe_1_regToExeQ(.CLK(CLK),
					       .RST_N(RST_N),
					       .enq_x(coreFix_aluExe_1_regToExeQ$enq_x),
					       .specUpdate_correctSpeculation_mask(coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask),
					       .specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
					       .specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
					       .EN_enq(coreFix_aluExe_1_regToExeQ$EN_enq),
					       .EN_deq(coreFix_aluExe_1_regToExeQ$EN_deq),
					       .EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_regToExeQ$EN_specUpdate_incorrectSpeculation),
					       .EN_specUpdate_correctSpeculation(coreFix_aluExe_1_regToExeQ$EN_specUpdate_correctSpeculation),
					       .RDY_enq(coreFix_aluExe_1_regToExeQ$RDY_enq),
					       .RDY_deq(coreFix_aluExe_1_regToExeQ$RDY_deq),
					       .first(coreFix_aluExe_1_regToExeQ$first),
					       .RDY_first(coreFix_aluExe_1_regToExeQ$RDY_first),
					       .RDY_specUpdate_incorrectSpeculation(),
					       .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_aluExe_1_rsAlu
  mkReservationStationAlu coreFix_aluExe_1_rsAlu(.CLK(CLK),
						 .RST_N(RST_N),
						 .enq_x(coreFix_aluExe_1_rsAlu$enq_x),
						 .setRegReady_0_put(coreFix_aluExe_1_rsAlu$setRegReady_0_put),
						 .setRegReady_1_put(coreFix_aluExe_1_rsAlu$setRegReady_1_put),
						 .setRegReady_2_put(coreFix_aluExe_1_rsAlu$setRegReady_2_put),
						 .setRegReady_3_put(coreFix_aluExe_1_rsAlu$setRegReady_3_put),
						 .setRegReady_4_put(coreFix_aluExe_1_rsAlu$setRegReady_4_put),
						 .setRobEnqTime_t(coreFix_aluExe_1_rsAlu$setRobEnqTime_t),
						 .specUpdate_correctSpeculation_mask(coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask),
						 .specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all),
						 .specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag),
						 .EN_enq(coreFix_aluExe_1_rsAlu$EN_enq),
						 .EN_setRobEnqTime(coreFix_aluExe_1_rsAlu$EN_setRobEnqTime),
						 .EN_doDispatch(coreFix_aluExe_1_rsAlu$EN_doDispatch),
						 .EN_setRegReady_0_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_0_put),
						 .EN_setRegReady_1_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_1_put),
						 .EN_setRegReady_2_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_2_put),
						 .EN_setRegReady_3_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put),
						 .EN_setRegReady_4_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_4_put),
						 .EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_rsAlu$EN_specUpdate_incorrectSpeculation),
						 .EN_specUpdate_correctSpeculation(coreFix_aluExe_1_rsAlu$EN_specUpdate_correctSpeculation),
						 .RDY_enq(coreFix_aluExe_1_rsAlu$RDY_enq),
						 .canEnq(coreFix_aluExe_1_rsAlu$canEnq),
						 .RDY_canEnq(),
						 .RDY_setRobEnqTime(),
						 .dispatchData(coreFix_aluExe_1_rsAlu$dispatchData),
						 .RDY_dispatchData(coreFix_aluExe_1_rsAlu$RDY_dispatchData),
						 .RDY_doDispatch(coreFix_aluExe_1_rsAlu$RDY_doDispatch),
						 .RDY_setRegReady_0_put(),
						 .RDY_setRegReady_1_put(),
						 .RDY_setRegReady_2_put(),
						 .RDY_setRegReady_3_put(),
						 .RDY_setRegReady_4_put(),
						 .approximateCount(coreFix_aluExe_1_rsAlu$approximateCount),
						 .RDY_approximateCount(),
						 .isFull_ehrPort0(),
						 .RDY_isFull_ehrPort0(),
						 .RDY_specUpdate_incorrectSpeculation(),
						 .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_fpuMulDivExe_0_dispToRegQ
  mkFpuMulDivDispToRegFifo coreFix_fpuMulDivExe_0_dispToRegQ(.CLK(CLK),
							     .RST_N(RST_N),
							     .enq_x(coreFix_fpuMulDivExe_0_dispToRegQ$enq_x),
							     .specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask),
							     .specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
							     .specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
							     .EN_enq(coreFix_fpuMulDivExe_0_dispToRegQ$EN_enq),
							     .EN_deq(coreFix_fpuMulDivExe_0_dispToRegQ$EN_deq),
							     .EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation),
							     .EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_correctSpeculation),
							     .RDY_enq(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq),
							     .RDY_deq(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_deq),
							     .first(coreFix_fpuMulDivExe_0_dispToRegQ$first),
							     .RDY_first(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first),
							     .RDY_specUpdate_incorrectSpeculation(),
							     .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_fpuMulDivExe_0_fpuExec_divQ
  mkMinimumExecQ coreFix_fpuMulDivExe_0_fpuExec_divQ(.CLK(CLK),
						     .RST_N(RST_N),
						     .enq_x(coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x),
						     .specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask),
						     .specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all),
						     .specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag),
						     .EN_enq(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_enq),
						     .EN_deq(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_deq),
						     .EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_incorrectSpeculation),
						     .EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_correctSpeculation),
						     .RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq),
						     .RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq),
						     .first_data(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data),
						     .RDY_first_data(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_data),
						     .first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned),
						     .RDY_first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned),
						     .RDY_specUpdate_incorrectSpeculation(),
						     .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_fpuMulDivExe_0_fpuExec_double_div
  mkDoubleDiv coreFix_fpuMulDivExe_0_fpuExec_double_div(.CLK(CLK),
							.RST_N(RST_N),
							.request_put(coreFix_fpuMulDivExe_0_fpuExec_double_div$request_put),
							.EN_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_request_put),
							.EN_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_response_get),
							.RDY_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put),
							.response_get(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get),
							.RDY_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get));

  // submodule coreFix_fpuMulDivExe_0_fpuExec_double_fma
  mkDoubleFMA coreFix_fpuMulDivExe_0_fpuExec_double_fma(.CLK(CLK),
							.RST_N(RST_N),
							.request_put(coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put),
							.EN_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put),
							.EN_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_response_get),
							.RDY_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put),
							.response_get(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get),
							.RDY_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get));

  // submodule coreFix_fpuMulDivExe_0_fpuExec_double_sqrt
  mkDoubleSqrt coreFix_fpuMulDivExe_0_fpuExec_double_sqrt(.CLK(CLK),
							  .RST_N(RST_N),
							  .request_put(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$request_put),
							  .EN_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_request_put),
							  .EN_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_response_get),
							  .RDY_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put),
							  .response_get(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get),
							  .RDY_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get));

  // submodule coreFix_fpuMulDivExe_0_fpuExec_fmaQ
  mkFmaExecQ coreFix_fpuMulDivExe_0_fpuExec_fmaQ(.CLK(CLK),
						 .RST_N(RST_N),
						 .enq_x(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x),
						 .specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask),
						 .specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all),
						 .specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag),
						 .EN_enq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_enq),
						 .EN_deq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_deq),
						 .EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_incorrectSpeculation),
						 .EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_correctSpeculation),
						 .RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq),
						 .RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq),
						 .first_data(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data),
						 .RDY_first_data(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_data),
						 .first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned),
						 .RDY_first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned),
						 .RDY_specUpdate_incorrectSpeculation(),
						 .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_fpuMulDivExe_0_fpuExec_simpleQ
  mkSimpleRespQ coreFix_fpuMulDivExe_0_fpuExec_simpleQ(.CLK(CLK),
						       .RST_N(RST_N),
						       .enq_x(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$enq_x),
						       .specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask),
						       .specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all),
						       .specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag),
						       .EN_enq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_enq),
						       .EN_deq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_deq),
						       .EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_incorrectSpeculation),
						       .EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_correctSpeculation),
						       .RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq),
						       .RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_deq),
						       .first(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first),
						       .RDY_first(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_first),
						       .RDY_specUpdate_incorrectSpeculation(),
						       .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_fpuMulDivExe_0_fpuExec_sqrtQ
  mkMinimumExecQ coreFix_fpuMulDivExe_0_fpuExec_sqrtQ(.CLK(CLK),
						      .RST_N(RST_N),
						      .enq_x(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x),
						      .specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask),
						      .specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all),
						      .specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag),
						      .EN_enq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_enq),
						      .EN_deq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_deq),
						      .EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_incorrectSpeculation),
						      .EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_correctSpeculation),
						      .RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq),
						      .RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq),
						      .first_data(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data),
						      .RDY_first_data(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_data),
						      .first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned),
						      .RDY_first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned),
						      .RDY_specUpdate_incorrectSpeculation(),
						      .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_divQ
  mkDivExecQ coreFix_fpuMulDivExe_0_mulDivExec_divQ(.CLK(CLK),
						    .RST_N(RST_N),
						    .enq_x(coreFix_fpuMulDivExe_0_mulDivExec_divQ$enq_x),
						    .specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask),
						    .specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all),
						    .specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag),
						    .EN_enq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_enq),
						    .EN_deq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_deq),
						    .EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_incorrectSpeculation),
						    .EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_correctSpeculation),
						    .RDY_enq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq),
						    .RDY_deq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq),
						    .first_data(coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data),
						    .RDY_first_data(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_data),
						    .first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned),
						    .RDY_first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned),
						    .RDY_specUpdate_incorrectSpeculation(),
						    .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc
  int_div_unsigned coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc(.aclk(CLK),
								    .s_axis_dividend_tdata(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata),
								    .s_axis_dividend_tuser(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser),
								    .s_axis_divisor_tdata(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata),
								    .s_axis_dividend_tvalid(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid),
								    .s_axis_divisor_tvalid(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tvalid),
								    .m_axis_dout_tready(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tready),
								    .s_axis_dividend_tready(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tready),
								    .s_axis_divisor_tready(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tready),
								    .m_axis_dout_tvalid(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid),
								    .m_axis_dout_tdata(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata),
								    .m_axis_dout_tuser(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser));

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg
  reset_guard coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg(.CLK(CLK),
								.RST(RST_N),
								.IS_READY(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY));

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulQ
  mkMulExecQ coreFix_fpuMulDivExe_0_mulDivExec_mulQ(.CLK(CLK),
						    .RST_N(RST_N),
						    .enq_x(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$enq_x),
						    .specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask),
						    .specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all),
						    .specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag),
						    .EN_enq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_enq),
						    .EN_deq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_deq),
						    .EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_incorrectSpeculation),
						    .EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_correctSpeculation),
						    .RDY_enq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq),
						    .RDY_deq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq),
						    .first_data(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data),
						    .RDY_first_data(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_data),
						    .first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned),
						    .RDY_first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned),
						    .RDY_specUpdate_incorrectSpeculation(),
						    .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned
  int_mul_signed coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned(.CLK(CLK),
								     .A(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A),
								     .B(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B),
								     .P(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$P));

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned
  int_mul_signed_unsigned coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned(.CLK(CLK),
										      .A(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A),
										      .B(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B),
										      .P(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$P));

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned
  int_mul_unsigned coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned(.CLK(CLK),
									 .A(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A),
									 .B(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B),
									 .P(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$P));

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ
  SizedFIFO #(.p1width(32'd128),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(32'd0)) coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ(.RST(RST_N),
									       .CLK(CLK),
									       .D_IN(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN),
									       .ENQ(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$ENQ),
									       .DEQ(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$DEQ),
									       .CLR(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$CLR),
									       .D_OUT(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT),
									       .FULL_N(),
									       .EMPTY_N(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N));

  // submodule coreFix_fpuMulDivExe_0_regToExeQ
  mkFpuMulDivRegToExeFifo coreFix_fpuMulDivExe_0_regToExeQ(.CLK(CLK),
							   .RST_N(RST_N),
							   .enq_x(coreFix_fpuMulDivExe_0_regToExeQ$enq_x),
							   .specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask),
							   .specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
							   .specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
							   .EN_enq(coreFix_fpuMulDivExe_0_regToExeQ$EN_enq),
							   .EN_deq(coreFix_fpuMulDivExe_0_regToExeQ$EN_deq),
							   .EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation),
							   .EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_correctSpeculation),
							   .RDY_enq(coreFix_fpuMulDivExe_0_regToExeQ$RDY_enq),
							   .RDY_deq(coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq),
							   .first(coreFix_fpuMulDivExe_0_regToExeQ$first),
							   .RDY_first(coreFix_fpuMulDivExe_0_regToExeQ$RDY_first),
							   .RDY_specUpdate_incorrectSpeculation(),
							   .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv
  mkReservationStationFpuMulDiv coreFix_fpuMulDivExe_0_rsFpuMulDiv(.CLK(CLK),
								   .RST_N(RST_N),
								   .enq_x(coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x),
								   .setRegReady_0_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_0_put),
								   .setRegReady_1_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_1_put),
								   .setRegReady_2_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put),
								   .setRegReady_3_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_3_put),
								   .setRegReady_4_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put),
								   .setRobEnqTime_t(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t),
								   .specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask),
								   .specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all),
								   .specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag),
								   .EN_enq(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq),
								   .EN_setRobEnqTime(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime),
								   .EN_doDispatch(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch),
								   .EN_setRegReady_0_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_0_put),
								   .EN_setRegReady_1_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_1_put),
								   .EN_setRegReady_2_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_2_put),
								   .EN_setRegReady_3_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put),
								   .EN_setRegReady_4_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_4_put),
								   .EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_incorrectSpeculation),
								   .EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_correctSpeculation),
								   .RDY_enq(coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq),
								   .canEnq(coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq),
								   .RDY_canEnq(),
								   .RDY_setRobEnqTime(),
								   .dispatchData(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData),
								   .RDY_dispatchData(coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData),
								   .RDY_doDispatch(coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch),
								   .RDY_setRegReady_0_put(),
								   .RDY_setRegReady_1_put(),
								   .RDY_setRegReady_2_put(),
								   .RDY_setRegReady_3_put(),
								   .RDY_setRegReady_4_put(),
								   .approximateCount(),
								   .RDY_approximateCount(),
								   .isFull_ehrPort0(),
								   .RDY_isFull_ehrPort0(),
								   .RDY_specUpdate_incorrectSpeculation(),
								   .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr
  mkDCRqMshrWrapper coreFix_memExe_dMem_cache_m_banks_0_cRqMshr(.CLK(CLK),
								.RST_N(RST_N),
								.cRqTransfer_getEmptyEntryInit_r(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r),
								.cRqTransfer_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n),
								.pipelineResp_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n),
								.pipelineResp_getSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n),
								.pipelineResp_getState_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n),
								.pipelineResp_getSucc_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n),
								.pipelineResp_releaseEntry_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n),
								.pipelineResp_searchEndOfChain_addr(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain_addr),
								.pipelineResp_setData_d(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d),
								.pipelineResp_setData_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_n),
								.pipelineResp_setStateSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_n),
								.pipelineResp_setStateSlot_slot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot),
								.pipelineResp_setStateSlot_state(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_state),
								.pipelineResp_setSucc_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_n),
								.pipelineResp_setSucc_succ(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_succ),
								.sendRqToP_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq_n),
								.sendRqToP_getSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot_n),
								.sendRsToP_cRq_getData_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData_n),
								.sendRsToP_cRq_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq_n),
								.sendRsToP_cRq_getSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot_n),
								.sendRsToP_cRq_getState_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState_n),
								.sendRsToP_cRq_setWaitSt_setSlot_clearData_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_n),
								.sendRsToP_cRq_setWaitSt_setSlot_clearData_slot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_slot),
								.EN_cRqTransfer_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_cRqTransfer_getEmptyEntryInit),
								.EN_sendRsToP_cRq_setWaitSt_setSlot_clearData(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_sendRsToP_cRq_setWaitSt_setSlot_clearData),
								.EN_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_releaseEntry),
								.EN_pipelineResp_setData(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setData),
								.EN_pipelineResp_setStateSlot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setStateSlot),
								.EN_pipelineResp_setSucc(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setSucc),
								.EN_stuck_get(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_stuck_get),
								.cRqTransfer_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq),
								.RDY_cRqTransfer_getRq(),
								.cRqTransfer_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit),
								.RDY_cRqTransfer_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_cRqTransfer_getEmptyEntryInit),
								.sendRsToP_cRq_getState(),
								.RDY_sendRsToP_cRq_getState(),
								.sendRsToP_cRq_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq),
								.RDY_sendRsToP_cRq_getRq(),
								.sendRsToP_cRq_getSlot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot),
								.RDY_sendRsToP_cRq_getSlot(),
								.sendRsToP_cRq_getData(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData),
								.RDY_sendRsToP_cRq_getData(),
								.RDY_sendRsToP_cRq_setWaitSt_setSlot_clearData(),
								.sendRqToP_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq),
								.RDY_sendRqToP_getRq(),
								.sendRqToP_getSlot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot),
								.RDY_sendRqToP_getSlot(),
								.RDY_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry),
								.pipelineResp_getState(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState),
								.RDY_pipelineResp_getState(),
								.pipelineResp_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq),
								.RDY_pipelineResp_getRq(),
								.pipelineResp_getSlot(),
								.RDY_pipelineResp_getSlot(),
								.RDY_pipelineResp_setData(),
								.RDY_pipelineResp_setStateSlot(),
								.pipelineResp_getSucc(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc),
								.RDY_pipelineResp_getSucc(),
								.RDY_pipelineResp_setSucc(),
								.pipelineResp_searchEndOfChain(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain),
								.RDY_pipelineResp_searchEndOfChain(),
								.emptyForFlush(),
								.RDY_emptyForFlush(),
								.stuck_get(),
								.RDY_stuck_get());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0(.CLK(CLK),
												.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN),
												.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN),
												.Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1(.CLK(CLK),
												.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN),
												.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN),
												.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0(.CLK(CLK),
											      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN),
											      .EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN),
											      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1(.CLK(CLK),
											      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN),
											      .EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN),
											      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2(.CLK(CLK),
											      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN),
											      .EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN),
											      .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0(.CLK(CLK),
											      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN),
											      .EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN),
											      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1(.CLK(CLK),
											      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN),
											      .EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN),
											      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2(.CLK(CLK),
											      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN),
											      .EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN),
											      .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0(.CLK(CLK),
											.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN),
											.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN),
											.Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1(.CLK(CLK),
											.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN),
											.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN),
											.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN),
										      .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN),
										      .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0(.CLK(CLK),
										    .D_IN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN),
										    .EN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN),
										    .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1(.CLK(CLK),
										    .D_IN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN),
										    .EN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN),
										    .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr
  mkDPRqMshrWrapper coreFix_memExe_dMem_cache_m_banks_0_pRqMshr(.CLK(CLK),
								.RST_N(RST_N),
								.getEmptyEntryInit_r(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r),
								.pipelineResp_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n),
								.pipelineResp_getState_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n),
								.pipelineResp_releaseEntry_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_releaseEntry_n),
								.pipelineResp_setDone_setData_d(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d),
								.pipelineResp_setDone_setData_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_n),
								.sendRsToP_pRq_getData_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData_n),
								.sendRsToP_pRq_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq_n),
								.sendRsToP_pRq_releaseEntry_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_releaseEntry_n),
								.EN_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_getEmptyEntryInit),
								.EN_sendRsToP_pRq_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_sendRsToP_pRq_releaseEntry),
								.EN_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_releaseEntry),
								.EN_pipelineResp_setDone_setData(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_setDone_setData),
								.EN_stuck_get(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_stuck_get),
								.getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit),
								.RDY_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit),
								.sendRsToP_pRq_getRq(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq),
								.RDY_sendRsToP_pRq_getRq(),
								.sendRsToP_pRq_getData(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData),
								.RDY_sendRsToP_pRq_getData(),
								.RDY_sendRsToP_pRq_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry),
								.pipelineResp_getRq(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq),
								.RDY_pipelineResp_getRq(),
								.pipelineResp_getState(),
								.RDY_pipelineResp_getState(),
								.RDY_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_pipelineResp_releaseEntry),
								.RDY_pipelineResp_setDone_setData(),
								.stuck_get(),
								.RDY_stuck_get());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_pipeline
  mkDPipeline coreFix_memExe_dMem_cache_m_banks_0_pipeline(.CLK(CLK),
							   .RST_N(RST_N),
							   .deqWrite_swapRq(coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq),
							   .deqWrite_updateRep(coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep),
							   .deqWrite_wrRam(coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam),
							   .send_r(coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r),
							   .EN_send(coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_send),
							   .EN_deqWrite(coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_deqWrite),
							   .RDY_send(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send),
							   .first(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first),
							   .RDY_first(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first),
							   .RDY_deqWrite(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0(.CLK(CLK),
											.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN),
											.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN),
											.Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1(.CLK(CLK),
											.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN),
											.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN),
											.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0(.CLK(CLK),
										       .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN),
										       .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN),
										       .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1(.CLK(CLK),
										       .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN),
										       .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN),
										       .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2(.CLK(CLK),
										       .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN),
										       .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN),
										       .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN),
										      .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN),
										      .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN),
										      .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ
  SizedFIFO #(.p1width(32'd3),
	      .p2depth(32'd8),
	      .p3cntr_width(32'd3),
	      .guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ(.RST(RST_N),
									       .CLK(CLK),
									       .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_IN),
									       .ENQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$ENQ),
									       .DEQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$DEQ),
									       .CLR(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$CLR),
									       .D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT),
									       .FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N),
									       .EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$EMPTY_N));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp
  FIFO2 #(.width(32'd3),
	  .guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp(.RST(RST_N),
											.CLK(CLK),
											.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_IN),
											.ENQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$ENQ),
											.DEQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$DEQ),
											.CLR(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$CLR),
											.D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_OUT),
											.FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N),
											.EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$EMPTY_N));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP
  FIFO2 #(.width(32'd3),
	  .guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP(.RST(RST_N),
										     .CLK(CLK),
										     .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_IN),
										     .ENQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$ENQ),
										     .DEQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$DEQ),
										     .CLR(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$CLR),
										     .D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_OUT),
										     .FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$FULL_N),
										     .EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$EMPTY_N));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0(.CLK(CLK),
											.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN),
											.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN),
											.Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1(.CLK(CLK),
											.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN),
											.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN),
											.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN),
										      .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN),
										      .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ
  SizedFIFO #(.p1width(32'd4),
	      .p2depth(32'd12),
	      .p3cntr_width(32'd4),
	      .guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ(.RST(RST_N),
									       .CLK(CLK),
									       .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_IN),
									       .ENQ(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$ENQ),
									       .DEQ(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$DEQ),
									       .CLR(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$CLR),
									       .D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT),
									       .FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N),
									       .EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0(.CLK(CLK),
											.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN),
											.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN),
											.Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1(.CLK(CLK),
											.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN),
											.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN),
											.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN),
										      .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN),
										      .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0(.CLK(CLK),
									  .D_IN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN),
									  .EN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN),
									  .Q_OUT());

  // submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1(.CLK(CLK),
									  .D_IN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN),
									  .EN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN),
									  .Q_OUT(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0(.CLK(CLK),
									.D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN),
									.EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN),
									.Q_OUT());

  // submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1(.CLK(CLK),
									.D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN),
									.EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN),
									.Q_OUT());

  // submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2(.CLK(CLK),
									.D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN),
									.EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN),
									.Q_OUT(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0(.CLK(CLK),
									.D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN),
									.EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN),
									.Q_OUT());

  // submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1(.CLK(CLK),
									.D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN),
									.EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN),
									.Q_OUT());

  // submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2(.CLK(CLK),
									.D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN),
									.EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN),
									.Q_OUT(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dTlb
  mkDTlbSynth coreFix_memExe_dTlb(.CLK(CLK),
				  .RST_N(RST_N),
				  .perf_req_r(coreFix_memExe_dTlb$perf_req_r),
				  .perf_setStatus_doStats(coreFix_memExe_dTlb$perf_setStatus_doStats),
				  .procReq_req(coreFix_memExe_dTlb$procReq_req),
				  .specUpdate_correctSpeculation_mask(coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask),
				  .specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all),
				  .specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag),
				  .toParent_ldTransRsFromP_enq_x(coreFix_memExe_dTlb$toParent_ldTransRsFromP_enq_x),
				  .updateVMInfo_vm(coreFix_memExe_dTlb$updateVMInfo_vm),
				  .EN_flush(coreFix_memExe_dTlb$EN_flush),
				  .EN_updateVMInfo(coreFix_memExe_dTlb$EN_updateVMInfo),
				  .EN_procReq(coreFix_memExe_dTlb$EN_procReq),
				  .EN_deqProcResp(coreFix_memExe_dTlb$EN_deqProcResp),
				  .EN_toParent_rqToP_deq(coreFix_memExe_dTlb$EN_toParent_rqToP_deq),
				  .EN_toParent_ldTransRsFromP_enq(coreFix_memExe_dTlb$EN_toParent_ldTransRsFromP_enq),
				  .EN_toParent_flush_request_get(coreFix_memExe_dTlb$EN_toParent_flush_request_get),
				  .EN_toParent_flush_response_put(coreFix_memExe_dTlb$EN_toParent_flush_response_put),
				  .EN_specUpdate_incorrectSpeculation(coreFix_memExe_dTlb$EN_specUpdate_incorrectSpeculation),
				  .EN_specUpdate_correctSpeculation(coreFix_memExe_dTlb$EN_specUpdate_correctSpeculation),
				  .EN_perf_setStatus(coreFix_memExe_dTlb$EN_perf_setStatus),
				  .EN_perf_req(coreFix_memExe_dTlb$EN_perf_req),
				  .EN_perf_resp(coreFix_memExe_dTlb$EN_perf_resp),
				  .flush_done(coreFix_memExe_dTlb$flush_done),
				  .RDY_flush_done(),
				  .RDY_flush(coreFix_memExe_dTlb$RDY_flush),
				  .RDY_updateVMInfo(),
				  .noPendingReq(coreFix_memExe_dTlb$noPendingReq),
				  .RDY_noPendingReq(),
				  .RDY_procReq(coreFix_memExe_dTlb$RDY_procReq),
				  .procResp(coreFix_memExe_dTlb$procResp),
				  .RDY_procResp(coreFix_memExe_dTlb$RDY_procResp),
				  .RDY_deqProcResp(coreFix_memExe_dTlb$RDY_deqProcResp),
				  .toParent_rqToP_notEmpty(),
				  .RDY_toParent_rqToP_notEmpty(),
				  .RDY_toParent_rqToP_deq(coreFix_memExe_dTlb$RDY_toParent_rqToP_deq),
				  .toParent_rqToP_first(coreFix_memExe_dTlb$toParent_rqToP_first),
				  .RDY_toParent_rqToP_first(coreFix_memExe_dTlb$RDY_toParent_rqToP_first),
				  .toParent_ldTransRsFromP_notFull(),
				  .RDY_toParent_ldTransRsFromP_notFull(),
				  .RDY_toParent_ldTransRsFromP_enq(coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq),
				  .RDY_toParent_flush_request_get(coreFix_memExe_dTlb$RDY_toParent_flush_request_get),
				  .RDY_toParent_flush_response_put(coreFix_memExe_dTlb$RDY_toParent_flush_response_put),
				  .RDY_specUpdate_incorrectSpeculation(),
				  .RDY_specUpdate_correctSpeculation(),
				  .RDY_perf_setStatus(),
				  .RDY_perf_req(),
				  .perf_resp(),
				  .RDY_perf_resp(),
				  .perf_respValid(),
				  .RDY_perf_respValid());

  // submodule coreFix_memExe_dispToRegQ
  mkMemDispToRegFifo coreFix_memExe_dispToRegQ(.CLK(CLK),
					       .RST_N(RST_N),
					       .enq_x(coreFix_memExe_dispToRegQ$enq_x),
					       .specUpdate_correctSpeculation_mask(coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask),
					       .specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
					       .specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
					       .EN_enq(coreFix_memExe_dispToRegQ$EN_enq),
					       .EN_deq(coreFix_memExe_dispToRegQ$EN_deq),
					       .EN_specUpdate_incorrectSpeculation(coreFix_memExe_dispToRegQ$EN_specUpdate_incorrectSpeculation),
					       .EN_specUpdate_correctSpeculation(coreFix_memExe_dispToRegQ$EN_specUpdate_correctSpeculation),
					       .RDY_enq(coreFix_memExe_dispToRegQ$RDY_enq),
					       .RDY_deq(coreFix_memExe_dispToRegQ$RDY_deq),
					       .first(coreFix_memExe_dispToRegQ$first),
					       .RDY_first(coreFix_memExe_dispToRegQ$RDY_first),
					       .RDY_specUpdate_incorrectSpeculation(),
					       .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_memExe_forwardQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_forwardQ_clearReq_dummy2_0(.CLK(CLK),
								     .D_IN(coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN),
								     .EN(coreFix_memExe_forwardQ_clearReq_dummy2_0$EN),
								     .Q_OUT());

  // submodule coreFix_memExe_forwardQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_forwardQ_clearReq_dummy2_1(.CLK(CLK),
								     .D_IN(coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN),
								     .EN(coreFix_memExe_forwardQ_clearReq_dummy2_1$EN),
								     .Q_OUT(coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_forwardQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_0(.CLK(CLK),
								   .D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN),
								   .EN(coreFix_memExe_forwardQ_deqReq_dummy2_0$EN),
								   .Q_OUT());

  // submodule coreFix_memExe_forwardQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_1(.CLK(CLK),
								   .D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN),
								   .EN(coreFix_memExe_forwardQ_deqReq_dummy2_1$EN),
								   .Q_OUT());

  // submodule coreFix_memExe_forwardQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_2(.CLK(CLK),
								   .D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN),
								   .EN(coreFix_memExe_forwardQ_deqReq_dummy2_2$EN),
								   .Q_OUT(coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_forwardQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_0(.CLK(CLK),
								   .D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN),
								   .EN(coreFix_memExe_forwardQ_enqReq_dummy2_0$EN),
								   .Q_OUT());

  // submodule coreFix_memExe_forwardQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_1(.CLK(CLK),
								   .D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN),
								   .EN(coreFix_memExe_forwardQ_enqReq_dummy2_1$EN),
								   .Q_OUT());

  // submodule coreFix_memExe_forwardQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_2(.CLK(CLK),
								   .D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN),
								   .EN(coreFix_memExe_forwardQ_enqReq_dummy2_2$EN),
								   .Q_OUT(coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_lsq
  mkSplitLSQ coreFix_memExe_lsq(.CLK(CLK),
				.RST_N(RST_N),
				.enqLd_dst(coreFix_memExe_lsq$enqLd_dst),
				.enqLd_inst_tag(coreFix_memExe_lsq$enqLd_inst_tag),
				.enqLd_mem_inst(coreFix_memExe_lsq$enqLd_mem_inst),
				.enqLd_spec_bits(coreFix_memExe_lsq$enqLd_spec_bits),
				.enqSt_dst(coreFix_memExe_lsq$enqSt_dst),
				.enqSt_inst_tag(coreFix_memExe_lsq$enqSt_inst_tag),
				.enqSt_mem_inst(coreFix_memExe_lsq$enqSt_mem_inst),
				.enqSt_spec_bits(coreFix_memExe_lsq$enqSt_spec_bits),
				.getHit_t(coreFix_memExe_lsq$getHit_t),
				.getOrigBE_t(coreFix_memExe_lsq$getOrigBE_t),
				.issueLd_lsqTag(coreFix_memExe_lsq$issueLd_lsqTag),
				.issueLd_paddr(coreFix_memExe_lsq$issueLd_paddr),
				.issueLd_sbRes(coreFix_memExe_lsq$issueLd_sbRes),
				.issueLd_shiftedBE(coreFix_memExe_lsq$issueLd_shiftedBE),
				.respLd_alignedData(coreFix_memExe_lsq$respLd_alignedData),
				.respLd_t(coreFix_memExe_lsq$respLd_t),
				.setAtCommit_0_put(coreFix_memExe_lsq$setAtCommit_0_put),
				.setAtCommit_1_put(coreFix_memExe_lsq$setAtCommit_1_put),
				.specUpdate_correctSpeculation_mask(coreFix_memExe_lsq$specUpdate_correctSpeculation_mask),
				.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all),
				.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag),
				.updateAddr_fault(coreFix_memExe_lsq$updateAddr_fault),
				.updateAddr_isMMIO(coreFix_memExe_lsq$updateAddr_isMMIO),
				.updateAddr_lsqTag(coreFix_memExe_lsq$updateAddr_lsqTag),
				.updateAddr_paddr(coreFix_memExe_lsq$updateAddr_paddr),
				.updateAddr_shiftedBE(coreFix_memExe_lsq$updateAddr_shiftedBE),
				.updateData_d(coreFix_memExe_lsq$updateData_d),
				.updateData_t(coreFix_memExe_lsq$updateData_t),
				.wakeupLdStalledBySB_sbIdx(coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx),
				.EN_enqLd(coreFix_memExe_lsq$EN_enqLd),
				.EN_enqSt(coreFix_memExe_lsq$EN_enqSt),
				.EN_getHit(coreFix_memExe_lsq$EN_getHit),
				.EN_updateData(coreFix_memExe_lsq$EN_updateData),
				.EN_updateAddr(coreFix_memExe_lsq$EN_updateAddr),
				.EN_issueLd(coreFix_memExe_lsq$EN_issueLd),
				.EN_getIssueLd(coreFix_memExe_lsq$EN_getIssueLd),
				.EN_respLd(coreFix_memExe_lsq$EN_respLd),
				.EN_deqLd(coreFix_memExe_lsq$EN_deqLd),
				.EN_deqSt(coreFix_memExe_lsq$EN_deqSt),
				.EN_wakeupLdStalledBySB(coreFix_memExe_lsq$EN_wakeupLdStalledBySB),
				.EN_setAtCommit_0_put(coreFix_memExe_lsq$EN_setAtCommit_0_put),
				.EN_setAtCommit_1_put(coreFix_memExe_lsq$EN_setAtCommit_1_put),
				.EN_specUpdate_incorrectSpeculation(coreFix_memExe_lsq$EN_specUpdate_incorrectSpeculation),
				.EN_specUpdate_correctSpeculation(coreFix_memExe_lsq$EN_specUpdate_correctSpeculation),
				.enqLdTag(coreFix_memExe_lsq$enqLdTag),
				.RDY_enqLdTag(),
				.enqStTag(coreFix_memExe_lsq$enqStTag),
				.RDY_enqStTag(),
				.RDY_enqLd(coreFix_memExe_lsq$RDY_enqLd),
				.RDY_enqSt(coreFix_memExe_lsq$RDY_enqSt),
				.getOrigBE(coreFix_memExe_lsq$getOrigBE),
				.RDY_getOrigBE(),
				.getHit(coreFix_memExe_lsq$getHit),
				.RDY_getHit(),
				.RDY_updateData(),
				.updateAddr(coreFix_memExe_lsq$updateAddr),
				.RDY_updateAddr(),
				.issueLd(coreFix_memExe_lsq$issueLd),
				.RDY_issueLd(),
				.getIssueLd(coreFix_memExe_lsq$getIssueLd),
				.RDY_getIssueLd(coreFix_memExe_lsq$RDY_getIssueLd),
				.respLd(coreFix_memExe_lsq$respLd),
				.RDY_respLd(),
				.firstLd(coreFix_memExe_lsq$firstLd),
				.RDY_firstLd(coreFix_memExe_lsq$RDY_firstLd),
				.RDY_deqLd(coreFix_memExe_lsq$RDY_deqLd),
				.firstSt(coreFix_memExe_lsq$firstSt),
				.RDY_firstSt(coreFix_memExe_lsq$RDY_firstSt),
				.RDY_deqSt(coreFix_memExe_lsq$RDY_deqSt),
				.RDY_wakeupLdStalledBySB(),
				.stqEmpty(coreFix_memExe_lsq$stqEmpty),
				.RDY_stqEmpty(),
				.RDY_setAtCommit_0_put(),
				.RDY_setAtCommit_1_put(),
				.RDY_specUpdate_incorrectSpeculation(),
				.RDY_specUpdate_correctSpeculation(),
				.stqFull_ehrPort0(),
				.RDY_stqFull_ehrPort0(),
				.ldqFull_ehrPort0(),
				.RDY_ldqFull_ehrPort0(),
				.noWrongPathLoads(coreFix_memExe_lsq$noWrongPathLoads),
				.RDY_noWrongPathLoads());

  // submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_memRespLdQ_clearReq_dummy2_0(.CLK(CLK),
								       .D_IN(coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN),
								       .EN(coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN),
								       .Q_OUT());

  // submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_memRespLdQ_clearReq_dummy2_1(.CLK(CLK),
								       .D_IN(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN),
								       .EN(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN),
								       .Q_OUT(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_0(.CLK(CLK),
								     .D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN),
								     .EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN),
								     .Q_OUT());

  // submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_1(.CLK(CLK),
								     .D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN),
								     .EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN),
								     .Q_OUT());

  // submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_2(.CLK(CLK),
								     .D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN),
								     .EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN),
								     .Q_OUT(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_0(.CLK(CLK),
								     .D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN),
								     .EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN),
								     .Q_OUT());

  // submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_1(.CLK(CLK),
								     .D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN),
								     .EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN),
								     .Q_OUT());

  // submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_2(.CLK(CLK),
								     .D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN),
								     .EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN),
								     .Q_OUT(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_regToExeQ
  mkMemRegToExeFifo coreFix_memExe_regToExeQ(.CLK(CLK),
					     .RST_N(RST_N),
					     .enq_x(coreFix_memExe_regToExeQ$enq_x),
					     .specUpdate_correctSpeculation_mask(coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask),
					     .specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
					     .specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
					     .EN_enq(coreFix_memExe_regToExeQ$EN_enq),
					     .EN_deq(coreFix_memExe_regToExeQ$EN_deq),
					     .EN_specUpdate_incorrectSpeculation(coreFix_memExe_regToExeQ$EN_specUpdate_incorrectSpeculation),
					     .EN_specUpdate_correctSpeculation(coreFix_memExe_regToExeQ$EN_specUpdate_correctSpeculation),
					     .RDY_enq(coreFix_memExe_regToExeQ$RDY_enq),
					     .RDY_deq(coreFix_memExe_regToExeQ$RDY_deq),
					     .first(coreFix_memExe_regToExeQ$first),
					     .RDY_first(coreFix_memExe_regToExeQ$RDY_first),
					     .RDY_specUpdate_incorrectSpeculation(),
					     .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_memExe_reqLdQ_data_0_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_data_0_dummy2_0(.CLK(CLK),
								 .D_IN(coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN),
								 .EN(coreFix_memExe_reqLdQ_data_0_dummy2_0$EN),
								 .Q_OUT());

  // submodule coreFix_memExe_reqLdQ_data_0_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_data_0_dummy2_1(.CLK(CLK),
								 .D_IN(coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN),
								 .EN(coreFix_memExe_reqLdQ_data_0_dummy2_1$EN),
								 .Q_OUT(coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_reqLdQ_deqP_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_deqP_dummy2_0(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN),
							       .EN(coreFix_memExe_reqLdQ_deqP_dummy2_0$EN),
							       .Q_OUT());

  // submodule coreFix_memExe_reqLdQ_deqP_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_deqP_dummy2_1(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN),
							       .EN(coreFix_memExe_reqLdQ_deqP_dummy2_1$EN),
							       .Q_OUT());

  // submodule coreFix_memExe_reqLdQ_empty_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_0(.CLK(CLK),
								.D_IN(coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN),
								.EN(coreFix_memExe_reqLdQ_empty_dummy2_0$EN),
								.Q_OUT());

  // submodule coreFix_memExe_reqLdQ_empty_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_1(.CLK(CLK),
								.D_IN(coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN),
								.EN(coreFix_memExe_reqLdQ_empty_dummy2_1$EN),
								.Q_OUT(coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_reqLdQ_empty_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_2(.CLK(CLK),
								.D_IN(coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN),
								.EN(coreFix_memExe_reqLdQ_empty_dummy2_2$EN),
								.Q_OUT(coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_reqLdQ_enqP_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_enqP_dummy2_0(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN),
							       .EN(coreFix_memExe_reqLdQ_enqP_dummy2_0$EN),
							       .Q_OUT());

  // submodule coreFix_memExe_reqLdQ_enqP_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_enqP_dummy2_1(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN),
							       .EN(coreFix_memExe_reqLdQ_enqP_dummy2_1$EN),
							       .Q_OUT());

  // submodule coreFix_memExe_reqLdQ_full_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_0(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqLdQ_full_dummy2_0$D_IN),
							       .EN(coreFix_memExe_reqLdQ_full_dummy2_0$EN),
							       .Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT));

  // submodule coreFix_memExe_reqLdQ_full_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_1(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqLdQ_full_dummy2_1$D_IN),
							       .EN(coreFix_memExe_reqLdQ_full_dummy2_1$EN),
							       .Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_reqLdQ_full_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_2(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqLdQ_full_dummy2_2$D_IN),
							       .EN(coreFix_memExe_reqLdQ_full_dummy2_2$EN),
							       .Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0(.CLK(CLK),
								      .D_IN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN),
								      .EN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN),
								      .Q_OUT());

  // submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1(.CLK(CLK),
								      .D_IN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN),
								      .EN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN),
								      .Q_OUT(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0(.CLK(CLK),
								    .D_IN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN),
								    .EN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN),
								    .Q_OUT());

  // submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1(.CLK(CLK),
								    .D_IN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN),
								    .EN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN),
								    .Q_OUT());

  // submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_0(.CLK(CLK),
								     .D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN),
								     .EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN),
								     .Q_OUT());

  // submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_1(.CLK(CLK),
								     .D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN),
								     .EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN),
								     .Q_OUT(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_2(.CLK(CLK),
								     .D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN),
								     .EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN),
								     .Q_OUT(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0(.CLK(CLK),
								    .D_IN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN),
								    .EN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN),
								    .Q_OUT());

  // submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1(.CLK(CLK),
								    .D_IN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN),
								    .EN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN),
								    .Q_OUT());

  // submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_0(.CLK(CLK),
								    .D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN),
								    .EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN),
								    .Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT));

  // submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_1(.CLK(CLK),
								    .D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN),
								    .EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN),
								    .Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_2(.CLK(CLK),
								    .D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN),
								    .EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN),
								    .Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_reqStQ_data_0_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_data_0_dummy2_0(.CLK(CLK),
								 .D_IN(coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN),
								 .EN(coreFix_memExe_reqStQ_data_0_dummy2_0$EN),
								 .Q_OUT());

  // submodule coreFix_memExe_reqStQ_data_0_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_data_0_dummy2_1(.CLK(CLK),
								 .D_IN(coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN),
								 .EN(coreFix_memExe_reqStQ_data_0_dummy2_1$EN),
								 .Q_OUT(coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_reqStQ_deqP_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_deqP_dummy2_0(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN),
							       .EN(coreFix_memExe_reqStQ_deqP_dummy2_0$EN),
							       .Q_OUT());

  // submodule coreFix_memExe_reqStQ_deqP_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_deqP_dummy2_1(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN),
							       .EN(coreFix_memExe_reqStQ_deqP_dummy2_1$EN),
							       .Q_OUT());

  // submodule coreFix_memExe_reqStQ_empty_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_0(.CLK(CLK),
								.D_IN(coreFix_memExe_reqStQ_empty_dummy2_0$D_IN),
								.EN(coreFix_memExe_reqStQ_empty_dummy2_0$EN),
								.Q_OUT());

  // submodule coreFix_memExe_reqStQ_empty_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_1(.CLK(CLK),
								.D_IN(coreFix_memExe_reqStQ_empty_dummy2_1$D_IN),
								.EN(coreFix_memExe_reqStQ_empty_dummy2_1$EN),
								.Q_OUT(coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_reqStQ_empty_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_2(.CLK(CLK),
								.D_IN(coreFix_memExe_reqStQ_empty_dummy2_2$D_IN),
								.EN(coreFix_memExe_reqStQ_empty_dummy2_2$EN),
								.Q_OUT(coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_reqStQ_enqP_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_enqP_dummy2_0(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN),
							       .EN(coreFix_memExe_reqStQ_enqP_dummy2_0$EN),
							       .Q_OUT());

  // submodule coreFix_memExe_reqStQ_enqP_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_enqP_dummy2_1(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN),
							       .EN(coreFix_memExe_reqStQ_enqP_dummy2_1$EN),
							       .Q_OUT());

  // submodule coreFix_memExe_reqStQ_full_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_0(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqStQ_full_dummy2_0$D_IN),
							       .EN(coreFix_memExe_reqStQ_full_dummy2_0$EN),
							       .Q_OUT(coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT));

  // submodule coreFix_memExe_reqStQ_full_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_1(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqStQ_full_dummy2_1$D_IN),
							       .EN(coreFix_memExe_reqStQ_full_dummy2_1$EN),
							       .Q_OUT(coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_reqStQ_full_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_2(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqStQ_full_dummy2_2$D_IN),
							       .EN(coreFix_memExe_reqStQ_full_dummy2_2$EN),
							       .Q_OUT(coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0(.CLK(CLK),
									 .D_IN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN),
									 .EN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN),
									 .Q_OUT());

  // submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1(.CLK(CLK),
									 .D_IN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN),
									 .EN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN),
									 .Q_OUT(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0(.CLK(CLK),
								       .D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN),
								       .EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN),
								       .Q_OUT());

  // submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1(.CLK(CLK),
								       .D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN),
								       .EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN),
								       .Q_OUT());

  // submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2(.CLK(CLK),
								       .D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN),
								       .EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN),
								       .Q_OUT(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0(.CLK(CLK),
								       .D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN),
								       .EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN),
								       .Q_OUT());

  // submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1(.CLK(CLK),
								       .D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN),
								       .EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN),
								       .Q_OUT());

  // submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2(.CLK(CLK),
								       .D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN),
								       .EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN),
								       .Q_OUT(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_rsMem
  mkReservationStationMem coreFix_memExe_rsMem(.CLK(CLK),
					       .RST_N(RST_N),
					       .enq_x(coreFix_memExe_rsMem$enq_x),
					       .setRegReady_0_put(coreFix_memExe_rsMem$setRegReady_0_put),
					       .setRegReady_1_put(coreFix_memExe_rsMem$setRegReady_1_put),
					       .setRegReady_2_put(coreFix_memExe_rsMem$setRegReady_2_put),
					       .setRegReady_3_put(coreFix_memExe_rsMem$setRegReady_3_put),
					       .setRegReady_4_put(coreFix_memExe_rsMem$setRegReady_4_put),
					       .setRobEnqTime_t(coreFix_memExe_rsMem$setRobEnqTime_t),
					       .specUpdate_correctSpeculation_mask(coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask),
					       .specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all),
					       .specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag),
					       .EN_enq(coreFix_memExe_rsMem$EN_enq),
					       .EN_setRobEnqTime(coreFix_memExe_rsMem$EN_setRobEnqTime),
					       .EN_doDispatch(coreFix_memExe_rsMem$EN_doDispatch),
					       .EN_setRegReady_0_put(coreFix_memExe_rsMem$EN_setRegReady_0_put),
					       .EN_setRegReady_1_put(coreFix_memExe_rsMem$EN_setRegReady_1_put),
					       .EN_setRegReady_2_put(coreFix_memExe_rsMem$EN_setRegReady_2_put),
					       .EN_setRegReady_3_put(coreFix_memExe_rsMem$EN_setRegReady_3_put),
					       .EN_setRegReady_4_put(coreFix_memExe_rsMem$EN_setRegReady_4_put),
					       .EN_specUpdate_incorrectSpeculation(coreFix_memExe_rsMem$EN_specUpdate_incorrectSpeculation),
					       .EN_specUpdate_correctSpeculation(coreFix_memExe_rsMem$EN_specUpdate_correctSpeculation),
					       .RDY_enq(coreFix_memExe_rsMem$RDY_enq),
					       .canEnq(coreFix_memExe_rsMem$canEnq),
					       .RDY_canEnq(),
					       .RDY_setRobEnqTime(),
					       .dispatchData(coreFix_memExe_rsMem$dispatchData),
					       .RDY_dispatchData(coreFix_memExe_rsMem$RDY_dispatchData),
					       .RDY_doDispatch(coreFix_memExe_rsMem$RDY_doDispatch),
					       .RDY_setRegReady_0_put(),
					       .RDY_setRegReady_1_put(),
					       .RDY_setRegReady_2_put(),
					       .RDY_setRegReady_3_put(),
					       .RDY_setRegReady_4_put(),
					       .approximateCount(),
					       .RDY_approximateCount(),
					       .isFull_ehrPort0(),
					       .RDY_isFull_ehrPort0(),
					       .RDY_specUpdate_incorrectSpeculation(),
					       .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_memExe_stb
  mkStoreBufferEhr coreFix_memExe_stb(.CLK(CLK),
				      .RST_N(RST_N),
				      .deq_idx(coreFix_memExe_stb$deq_idx),
				      .enq_be(coreFix_memExe_stb$enq_be),
				      .enq_data(coreFix_memExe_stb$enq_data),
				      .enq_idx(coreFix_memExe_stb$enq_idx),
				      .enq_paddr(coreFix_memExe_stb$enq_paddr),
				      .getEnqIndex_paddr(coreFix_memExe_stb$getEnqIndex_paddr),
				      .noMatchLdQ_be(coreFix_memExe_stb$noMatchLdQ_be),
				      .noMatchLdQ_paddr(coreFix_memExe_stb$noMatchLdQ_paddr),
				      .noMatchStQ_be(coreFix_memExe_stb$noMatchStQ_be),
				      .noMatchStQ_paddr(coreFix_memExe_stb$noMatchStQ_paddr),
				      .search_be(coreFix_memExe_stb$search_be),
				      .search_paddr(coreFix_memExe_stb$search_paddr),
				      .EN_enq(coreFix_memExe_stb$EN_enq),
				      .EN_deq(coreFix_memExe_stb$EN_deq),
				      .EN_issue(coreFix_memExe_stb$EN_issue),
				      .isEmpty(coreFix_memExe_stb$isEmpty),
				      .RDY_isEmpty(),
				      .getEnqIndex(coreFix_memExe_stb$getEnqIndex),
				      .RDY_getEnqIndex(),
				      .RDY_enq(coreFix_memExe_stb$RDY_enq),
				      .deq(coreFix_memExe_stb$deq),
				      .RDY_deq(coreFix_memExe_stb$RDY_deq),
				      .issue(coreFix_memExe_stb$issue),
				      .RDY_issue(coreFix_memExe_stb$RDY_issue),
				      .search(coreFix_memExe_stb$search),
				      .RDY_search(),
				      .noMatchLdQ(coreFix_memExe_stb$noMatchLdQ),
				      .RDY_noMatchLdQ(),
				      .noMatchStQ(coreFix_memExe_stb$noMatchStQ),
				      .RDY_noMatchStQ());

  // submodule coreFix_trainBPQ_0
  FIFO2 #(.width(32'd160), .guarded(32'd1)) coreFix_trainBPQ_0(.RST(RST_N),
							       .CLK(CLK),
							       .D_IN(coreFix_trainBPQ_0$D_IN),
							       .ENQ(coreFix_trainBPQ_0$ENQ),
							       .DEQ(coreFix_trainBPQ_0$DEQ),
							       .CLR(coreFix_trainBPQ_0$CLR),
							       .D_OUT(coreFix_trainBPQ_0$D_OUT),
							       .FULL_N(coreFix_trainBPQ_0$FULL_N),
							       .EMPTY_N(coreFix_trainBPQ_0$EMPTY_N));

  // submodule coreFix_trainBPQ_1
  FIFO2 #(.width(32'd160), .guarded(32'd1)) coreFix_trainBPQ_1(.RST(RST_N),
							       .CLK(CLK),
							       .D_IN(coreFix_trainBPQ_1$D_IN),
							       .ENQ(coreFix_trainBPQ_1$ENQ),
							       .DEQ(coreFix_trainBPQ_1$DEQ),
							       .CLR(coreFix_trainBPQ_1$CLR),
							       .D_OUT(coreFix_trainBPQ_1$D_OUT),
							       .FULL_N(coreFix_trainBPQ_1$FULL_N),
							       .EMPTY_N(coreFix_trainBPQ_1$EMPTY_N));

  // submodule csrInstOrInterruptInflight_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) csrInstOrInterruptInflight_dummy2_0(.CLK(CLK),
							       .D_IN(csrInstOrInterruptInflight_dummy2_0$D_IN),
							       .EN(csrInstOrInterruptInflight_dummy2_0$EN),
							       .Q_OUT(csrInstOrInterruptInflight_dummy2_0$Q_OUT));

  // submodule csrInstOrInterruptInflight_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) csrInstOrInterruptInflight_dummy2_1(.CLK(CLK),
							       .D_IN(csrInstOrInterruptInflight_dummy2_1$D_IN),
							       .EN(csrInstOrInterruptInflight_dummy2_1$EN),
							       .Q_OUT(csrInstOrInterruptInflight_dummy2_1$Q_OUT));

  // submodule csrf_mcycle_ehr_data_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) csrf_mcycle_ehr_data_dummy2_0(.CLK(CLK),
							 .D_IN(csrf_mcycle_ehr_data_dummy2_0$D_IN),
							 .EN(csrf_mcycle_ehr_data_dummy2_0$EN),
							 .Q_OUT(csrf_mcycle_ehr_data_dummy2_0$Q_OUT));

  // submodule csrf_mcycle_ehr_data_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) csrf_mcycle_ehr_data_dummy2_1(.CLK(CLK),
							 .D_IN(csrf_mcycle_ehr_data_dummy2_1$D_IN),
							 .EN(csrf_mcycle_ehr_data_dummy2_1$EN),
							 .Q_OUT(csrf_mcycle_ehr_data_dummy2_1$Q_OUT));

  // submodule csrf_minstret_ehr_data_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) csrf_minstret_ehr_data_dummy2_0(.CLK(CLK),
							   .D_IN(csrf_minstret_ehr_data_dummy2_0$D_IN),
							   .EN(csrf_minstret_ehr_data_dummy2_0$EN),
							   .Q_OUT(csrf_minstret_ehr_data_dummy2_0$Q_OUT));

  // submodule csrf_minstret_ehr_data_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) csrf_minstret_ehr_data_dummy2_1(.CLK(CLK),
							   .D_IN(csrf_minstret_ehr_data_dummy2_1$D_IN),
							   .EN(csrf_minstret_ehr_data_dummy2_1$EN),
							   .Q_OUT(csrf_minstret_ehr_data_dummy2_1$Q_OUT));

  // submodule csrf_stats_module_writeQ
  FIFO1 #(.width(32'd1),
	  .guarded(32'd1)) csrf_stats_module_writeQ(.RST(RST_N),
						    .CLK(CLK),
						    .D_IN(csrf_stats_module_writeQ$D_IN),
						    .ENQ(csrf_stats_module_writeQ$ENQ),
						    .DEQ(csrf_stats_module_writeQ$DEQ),
						    .CLR(csrf_stats_module_writeQ$CLR),
						    .D_OUT(csrf_stats_module_writeQ$D_OUT),
						    .FULL_N(csrf_stats_module_writeQ$FULL_N),
						    .EMPTY_N(csrf_stats_module_writeQ$EMPTY_N));

  // submodule csrf_terminate_module_terminateQ
  FIFO10 #(.guarded(32'd1)) csrf_terminate_module_terminateQ(.RST(RST_N),
							     .CLK(CLK),
							     .ENQ(csrf_terminate_module_terminateQ$ENQ),
							     .DEQ(csrf_terminate_module_terminateQ$DEQ),
							     .CLR(csrf_terminate_module_terminateQ$CLR),
							     .FULL_N(csrf_terminate_module_terminateQ$FULL_N),
							     .EMPTY_N(csrf_terminate_module_terminateQ$EMPTY_N));

  // submodule epochManager
  mkEpochManager epochManager(.CLK(CLK),
			      .RST_N(RST_N),
			      .checkEpoch_0_check_e(epochManager$checkEpoch_0_check_e),
			      .checkEpoch_1_check_e(epochManager$checkEpoch_1_check_e),
			      .updatePrevEpoch_0_update_e(epochManager$updatePrevEpoch_0_update_e),
			      .updatePrevEpoch_1_update_e(epochManager$updatePrevEpoch_1_update_e),
			      .EN_updatePrevEpoch_0_update(epochManager$EN_updatePrevEpoch_0_update),
			      .EN_updatePrevEpoch_1_update(epochManager$EN_updatePrevEpoch_1_update),
			      .EN_incrementEpoch(epochManager$EN_incrementEpoch),
			      .checkEpoch_0_check(epochManager$checkEpoch_0_check),
			      .RDY_checkEpoch_0_check(),
			      .checkEpoch_1_check(epochManager$checkEpoch_1_check),
			      .RDY_checkEpoch_1_check(),
			      .RDY_updatePrevEpoch_0_update(),
			      .RDY_updatePrevEpoch_1_update(),
			      .getEpoch(),
			      .RDY_getEpoch(),
			      .RDY_incrementEpoch(epochManager$RDY_incrementEpoch),
			      .getEpochState(),
			      .RDY_getEpochState(),
			      .isFull_ehrPort0(),
			      .RDY_isFull_ehrPort0());

  // submodule f_csr_reqs
  FIFO1 #(.width(32'd77), .guarded(32'd1)) f_csr_reqs(.RST(RST_N),
						      .CLK(CLK),
						      .D_IN(f_csr_reqs$D_IN),
						      .ENQ(f_csr_reqs$ENQ),
						      .DEQ(f_csr_reqs$DEQ),
						      .CLR(f_csr_reqs$CLR),
						      .D_OUT(f_csr_reqs$D_OUT),
						      .FULL_N(f_csr_reqs$FULL_N),
						      .EMPTY_N(f_csr_reqs$EMPTY_N));

  // submodule f_csr_rsps
  FIFO1 #(.width(32'd65), .guarded(32'd1)) f_csr_rsps(.RST(RST_N),
						      .CLK(CLK),
						      .D_IN(f_csr_rsps$D_IN),
						      .ENQ(f_csr_rsps$ENQ),
						      .DEQ(f_csr_rsps$DEQ),
						      .CLR(f_csr_rsps$CLR),
						      .D_OUT(f_csr_rsps$D_OUT),
						      .FULL_N(f_csr_rsps$FULL_N),
						      .EMPTY_N(f_csr_rsps$EMPTY_N));

  // submodule f_fpr_reqs
  FIFO1 #(.width(32'd70), .guarded(32'd1)) f_fpr_reqs(.RST(RST_N),
						      .CLK(CLK),
						      .D_IN(f_fpr_reqs$D_IN),
						      .ENQ(f_fpr_reqs$ENQ),
						      .DEQ(f_fpr_reqs$DEQ),
						      .CLR(f_fpr_reqs$CLR),
						      .D_OUT(f_fpr_reqs$D_OUT),
						      .FULL_N(f_fpr_reqs$FULL_N),
						      .EMPTY_N(f_fpr_reqs$EMPTY_N));

  // submodule f_fpr_rsps
  FIFO1 #(.width(32'd65), .guarded(32'd1)) f_fpr_rsps(.RST(RST_N),
						      .CLK(CLK),
						      .D_IN(f_fpr_rsps$D_IN),
						      .ENQ(f_fpr_rsps$ENQ),
						      .DEQ(f_fpr_rsps$DEQ),
						      .CLR(f_fpr_rsps$CLR),
						      .D_OUT(f_fpr_rsps$D_OUT),
						      .FULL_N(f_fpr_rsps$FULL_N),
						      .EMPTY_N(f_fpr_rsps$EMPTY_N));

  // submodule f_gpr_reqs
  FIFO1 #(.width(32'd70), .guarded(32'd1)) f_gpr_reqs(.RST(RST_N),
						      .CLK(CLK),
						      .D_IN(f_gpr_reqs$D_IN),
						      .ENQ(f_gpr_reqs$ENQ),
						      .DEQ(f_gpr_reqs$DEQ),
						      .CLR(f_gpr_reqs$CLR),
						      .D_OUT(f_gpr_reqs$D_OUT),
						      .FULL_N(f_gpr_reqs$FULL_N),
						      .EMPTY_N(f_gpr_reqs$EMPTY_N));

  // submodule f_gpr_rsps
  FIFO1 #(.width(32'd65), .guarded(32'd1)) f_gpr_rsps(.RST(RST_N),
						      .CLK(CLK),
						      .D_IN(f_gpr_rsps$D_IN),
						      .ENQ(f_gpr_rsps$ENQ),
						      .DEQ(f_gpr_rsps$DEQ),
						      .CLR(f_gpr_rsps$CLR),
						      .D_OUT(f_gpr_rsps$D_OUT),
						      .FULL_N(f_gpr_rsps$FULL_N),
						      .EMPTY_N(f_gpr_rsps$EMPTY_N));

  // submodule f_run_halt_reqs
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_run_halt_reqs(.RST(RST_N),
							  .CLK(CLK),
							  .D_IN(f_run_halt_reqs$D_IN),
							  .ENQ(f_run_halt_reqs$ENQ),
							  .DEQ(f_run_halt_reqs$DEQ),
							  .CLR(f_run_halt_reqs$CLR),
							  .D_OUT(f_run_halt_reqs$D_OUT),
							  .FULL_N(f_run_halt_reqs$FULL_N),
							  .EMPTY_N(f_run_halt_reqs$EMPTY_N));

  // submodule f_run_halt_rsps
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_run_halt_rsps(.RST(RST_N),
							  .CLK(CLK),
							  .D_IN(f_run_halt_rsps$D_IN),
							  .ENQ(f_run_halt_rsps$ENQ),
							  .DEQ(f_run_halt_rsps$DEQ),
							  .CLR(f_run_halt_rsps$CLR),
							  .D_OUT(f_run_halt_rsps$D_OUT),
							  .FULL_N(f_run_halt_rsps$FULL_N),
							  .EMPTY_N(f_run_halt_rsps$EMPTY_N));

  // submodule fetchStage
  mkFetchStage fetchStage(.CLK(CLK),
			  .RST_N(RST_N),
			  .iMemIfc_perf_req_r(fetchStage$iMemIfc_perf_req_r),
			  .iMemIfc_perf_setStatus_doStats(fetchStage$iMemIfc_perf_setStatus_doStats),
			  .iMemIfc_to_parent_fromP_enq_x(fetchStage$iMemIfc_to_parent_fromP_enq_x),
			  .iMemIfc_to_proc_request_put(fetchStage$iMemIfc_to_proc_request_put),
			  .iTlbIfc_perf_req_r(fetchStage$iTlbIfc_perf_req_r),
			  .iTlbIfc_perf_setStatus_doStats(fetchStage$iTlbIfc_perf_setStatus_doStats),
			  .iTlbIfc_toParent_rsFromP_enq_x(fetchStage$iTlbIfc_toParent_rsFromP_enq_x),
			  .iTlbIfc_to_proc_request_put(fetchStage$iTlbIfc_to_proc_request_put),
			  .iTlbIfc_updateVMInfo_vm(fetchStage$iTlbIfc_updateVMInfo_vm),
			  .mmioIfc_instResp_enq_x(fetchStage$mmioIfc_instResp_enq_x),
			  .mmioIfc_setHtifAddrs_fromHost(fetchStage$mmioIfc_setHtifAddrs_fromHost),
			  .mmioIfc_setHtifAddrs_toHost(fetchStage$mmioIfc_setHtifAddrs_toHost),
			  .perf_req_r(fetchStage$perf_req_r),
			  .perf_setStatus_doStats(fetchStage$perf_setStatus_doStats),
			  .redirect_pc(fetchStage$redirect_pc),
			  .start_pc(fetchStage$start_pc),
			  .train_predictors_dpTrain(fetchStage$train_predictors_dpTrain),
			  .train_predictors_iType(fetchStage$train_predictors_iType),
			  .train_predictors_isCompressed(fetchStage$train_predictors_isCompressed),
			  .train_predictors_mispred(fetchStage$train_predictors_mispred),
			  .train_predictors_next_pc(fetchStage$train_predictors_next_pc),
			  .train_predictors_pc(fetchStage$train_predictors_pc),
			  .train_predictors_taken(fetchStage$train_predictors_taken),
			  .EN_pipelines_0_deq(fetchStage$EN_pipelines_0_deq),
			  .EN_pipelines_1_deq(fetchStage$EN_pipelines_1_deq),
			  .EN_iTlbIfc_flush(fetchStage$EN_iTlbIfc_flush),
			  .EN_iTlbIfc_updateVMInfo(fetchStage$EN_iTlbIfc_updateVMInfo),
			  .EN_iTlbIfc_to_proc_request_put(fetchStage$EN_iTlbIfc_to_proc_request_put),
			  .EN_iTlbIfc_to_proc_response_get(fetchStage$EN_iTlbIfc_to_proc_response_get),
			  .EN_iTlbIfc_toParent_rqToP_deq(fetchStage$EN_iTlbIfc_toParent_rqToP_deq),
			  .EN_iTlbIfc_toParent_rsFromP_enq(fetchStage$EN_iTlbIfc_toParent_rsFromP_enq),
			  .EN_iTlbIfc_toParent_flush_request_get(fetchStage$EN_iTlbIfc_toParent_flush_request_get),
			  .EN_iTlbIfc_toParent_flush_response_put(fetchStage$EN_iTlbIfc_toParent_flush_response_put),
			  .EN_iTlbIfc_perf_setStatus(fetchStage$EN_iTlbIfc_perf_setStatus),
			  .EN_iTlbIfc_perf_req(fetchStage$EN_iTlbIfc_perf_req),
			  .EN_iTlbIfc_perf_resp(fetchStage$EN_iTlbIfc_perf_resp),
			  .EN_iMemIfc_to_proc_request_put(fetchStage$EN_iMemIfc_to_proc_request_put),
			  .EN_iMemIfc_to_proc_response_get(fetchStage$EN_iMemIfc_to_proc_response_get),
			  .EN_iMemIfc_flush(fetchStage$EN_iMemIfc_flush),
			  .EN_iMemIfc_perf_setStatus(fetchStage$EN_iMemIfc_perf_setStatus),
			  .EN_iMemIfc_perf_req(fetchStage$EN_iMemIfc_perf_req),
			  .EN_iMemIfc_perf_resp(fetchStage$EN_iMemIfc_perf_resp),
			  .EN_iMemIfc_to_parent_rsToP_deq(fetchStage$EN_iMemIfc_to_parent_rsToP_deq),
			  .EN_iMemIfc_to_parent_rqToP_deq(fetchStage$EN_iMemIfc_to_parent_rqToP_deq),
			  .EN_iMemIfc_to_parent_fromP_enq(fetchStage$EN_iMemIfc_to_parent_fromP_enq),
			  .EN_iMemIfc_cRqStuck_get(fetchStage$EN_iMemIfc_cRqStuck_get),
			  .EN_iMemIfc_pRqStuck_get(fetchStage$EN_iMemIfc_pRqStuck_get),
			  .EN_mmioIfc_instReq_deq(fetchStage$EN_mmioIfc_instReq_deq),
			  .EN_mmioIfc_instResp_enq(fetchStage$EN_mmioIfc_instResp_enq),
			  .EN_mmioIfc_setHtifAddrs(fetchStage$EN_mmioIfc_setHtifAddrs),
			  .EN_start(fetchStage$EN_start),
			  .EN_stop(fetchStage$EN_stop),
			  .EN_setWaitRedirect(fetchStage$EN_setWaitRedirect),
			  .EN_redirect(fetchStage$EN_redirect),
			  .EN_setWaitFlush(fetchStage$EN_setWaitFlush),
			  .EN_done_flushing(fetchStage$EN_done_flushing),
			  .EN_train_predictors(fetchStage$EN_train_predictors),
			  .EN_flush_predictors(fetchStage$EN_flush_predictors),
			  .EN_perf_setStatus(fetchStage$EN_perf_setStatus),
			  .EN_perf_req(fetchStage$EN_perf_req),
			  .EN_perf_resp(fetchStage$EN_perf_resp),
			  .pipelines_0_canDeq(fetchStage$pipelines_0_canDeq),
			  .RDY_pipelines_0_canDeq(),
			  .RDY_pipelines_0_deq(fetchStage$RDY_pipelines_0_deq),
			  .pipelines_0_first(fetchStage$pipelines_0_first),
			  .RDY_pipelines_0_first(fetchStage$RDY_pipelines_0_first),
			  .pipelines_1_canDeq(fetchStage$pipelines_1_canDeq),
			  .RDY_pipelines_1_canDeq(),
			  .RDY_pipelines_1_deq(fetchStage$RDY_pipelines_1_deq),
			  .pipelines_1_first(fetchStage$pipelines_1_first),
			  .RDY_pipelines_1_first(fetchStage$RDY_pipelines_1_first),
			  .iTlbIfc_flush_done(fetchStage$iTlbIfc_flush_done),
			  .RDY_iTlbIfc_flush_done(),
			  .RDY_iTlbIfc_flush(fetchStage$RDY_iTlbIfc_flush),
			  .RDY_iTlbIfc_updateVMInfo(),
			  .iTlbIfc_noPendingReq(fetchStage$iTlbIfc_noPendingReq),
			  .RDY_iTlbIfc_noPendingReq(),
			  .RDY_iTlbIfc_to_proc_request_put(),
			  .iTlbIfc_to_proc_response_get(),
			  .RDY_iTlbIfc_to_proc_response_get(),
			  .iTlbIfc_toParent_rqToP_notEmpty(),
			  .RDY_iTlbIfc_toParent_rqToP_notEmpty(),
			  .RDY_iTlbIfc_toParent_rqToP_deq(fetchStage$RDY_iTlbIfc_toParent_rqToP_deq),
			  .iTlbIfc_toParent_rqToP_first(fetchStage$iTlbIfc_toParent_rqToP_first),
			  .RDY_iTlbIfc_toParent_rqToP_first(fetchStage$RDY_iTlbIfc_toParent_rqToP_first),
			  .iTlbIfc_toParent_rsFromP_notFull(),
			  .RDY_iTlbIfc_toParent_rsFromP_notFull(),
			  .RDY_iTlbIfc_toParent_rsFromP_enq(fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq),
			  .RDY_iTlbIfc_toParent_flush_request_get(fetchStage$RDY_iTlbIfc_toParent_flush_request_get),
			  .RDY_iTlbIfc_toParent_flush_response_put(fetchStage$RDY_iTlbIfc_toParent_flush_response_put),
			  .RDY_iTlbIfc_perf_setStatus(),
			  .RDY_iTlbIfc_perf_req(),
			  .iTlbIfc_perf_resp(),
			  .RDY_iTlbIfc_perf_resp(),
			  .iTlbIfc_perf_respValid(),
			  .RDY_iTlbIfc_perf_respValid(),
			  .RDY_iMemIfc_to_proc_request_put(),
			  .iMemIfc_to_proc_response_get(),
			  .RDY_iMemIfc_to_proc_response_get(),
			  .RDY_iMemIfc_flush(),
			  .iMemIfc_flush_done(fetchStage$iMemIfc_flush_done),
			  .RDY_iMemIfc_flush_done(),
			  .RDY_iMemIfc_perf_setStatus(),
			  .RDY_iMemIfc_perf_req(),
			  .iMemIfc_perf_resp(),
			  .RDY_iMemIfc_perf_resp(),
			  .iMemIfc_perf_respValid(),
			  .RDY_iMemIfc_perf_respValid(),
			  .iMemIfc_to_parent_rsToP_notEmpty(fetchStage$iMemIfc_to_parent_rsToP_notEmpty),
			  .RDY_iMemIfc_to_parent_rsToP_notEmpty(),
			  .RDY_iMemIfc_to_parent_rsToP_deq(fetchStage$RDY_iMemIfc_to_parent_rsToP_deq),
			  .iMemIfc_to_parent_rsToP_first(fetchStage$iMemIfc_to_parent_rsToP_first),
			  .RDY_iMemIfc_to_parent_rsToP_first(fetchStage$RDY_iMemIfc_to_parent_rsToP_first),
			  .iMemIfc_to_parent_rqToP_notEmpty(fetchStage$iMemIfc_to_parent_rqToP_notEmpty),
			  .RDY_iMemIfc_to_parent_rqToP_notEmpty(),
			  .RDY_iMemIfc_to_parent_rqToP_deq(fetchStage$RDY_iMemIfc_to_parent_rqToP_deq),
			  .iMemIfc_to_parent_rqToP_first(fetchStage$iMemIfc_to_parent_rqToP_first),
			  .RDY_iMemIfc_to_parent_rqToP_first(fetchStage$RDY_iMemIfc_to_parent_rqToP_first),
			  .iMemIfc_to_parent_fromP_notFull(fetchStage$iMemIfc_to_parent_fromP_notFull),
			  .RDY_iMemIfc_to_parent_fromP_notFull(),
			  .RDY_iMemIfc_to_parent_fromP_enq(fetchStage$RDY_iMemIfc_to_parent_fromP_enq),
			  .iMemIfc_cRqStuck_get(fetchStage$iMemIfc_cRqStuck_get),
			  .RDY_iMemIfc_cRqStuck_get(fetchStage$RDY_iMemIfc_cRqStuck_get),
			  .iMemIfc_pRqStuck_get(fetchStage$iMemIfc_pRqStuck_get),
			  .RDY_iMemIfc_pRqStuck_get(fetchStage$RDY_iMemIfc_pRqStuck_get),
			  .mmioIfc_instReq_notEmpty(),
			  .RDY_mmioIfc_instReq_notEmpty(),
			  .RDY_mmioIfc_instReq_deq(fetchStage$RDY_mmioIfc_instReq_deq),
			  .mmioIfc_instReq_first_fst(fetchStage$mmioIfc_instReq_first_fst),
			  .RDY_mmioIfc_instReq_first_fst(fetchStage$RDY_mmioIfc_instReq_first_fst),
			  .mmioIfc_instReq_first_snd(fetchStage$mmioIfc_instReq_first_snd),
			  .RDY_mmioIfc_instReq_first_snd(fetchStage$RDY_mmioIfc_instReq_first_snd),
			  .mmioIfc_instResp_notFull(),
			  .RDY_mmioIfc_instResp_notFull(),
			  .RDY_mmioIfc_instResp_enq(fetchStage$RDY_mmioIfc_instResp_enq),
			  .RDY_mmioIfc_setHtifAddrs(),
			  .RDY_start(),
			  .RDY_stop(),
			  .RDY_setWaitRedirect(),
			  .RDY_redirect(),
			  .RDY_setWaitFlush(),
			  .RDY_done_flushing(fetchStage$RDY_done_flushing),
			  .RDY_train_predictors(),
			  .emptyForFlush(fetchStage$emptyForFlush),
			  .RDY_emptyForFlush(),
			  .RDY_flush_predictors(),
			  .flush_predictors_done(fetchStage$flush_predictors_done),
			  .RDY_flush_predictors_done(),
			  .getFetchState(),
			  .RDY_getFetchState(),
			  .RDY_perf_setStatus(),
			  .RDY_perf_req(),
			  .perf_resp(),
			  .RDY_perf_resp(),
			  .perf_respValid(),
			  .RDY_perf_respValid());

  // submodule l2Tlb
  mkL2Tlb l2Tlb(.CLK(CLK),
		.RST_N(RST_N),
		.perf_req_r(l2Tlb$perf_req_r),
		.perf_setStatus_doStats(l2Tlb$perf_setStatus_doStats),
		.toChildren_rqFromC_put(l2Tlb$toChildren_rqFromC_put),
		.toMem_respLd_enq_x(l2Tlb$toMem_respLd_enq_x),
		.updateVMInfo_vmD(l2Tlb$updateVMInfo_vmD),
		.updateVMInfo_vmI(l2Tlb$updateVMInfo_vmI),
		.EN_updateVMInfo(l2Tlb$EN_updateVMInfo),
		.EN_toChildren_rqFromC_put(l2Tlb$EN_toChildren_rqFromC_put),
		.EN_toChildren_rsToC_deq(l2Tlb$EN_toChildren_rsToC_deq),
		.EN_toChildren_iTlbReqFlush_put(l2Tlb$EN_toChildren_iTlbReqFlush_put),
		.EN_toChildren_dTlbReqFlush_put(l2Tlb$EN_toChildren_dTlbReqFlush_put),
		.EN_toChildren_flushDone_get(l2Tlb$EN_toChildren_flushDone_get),
		.EN_toMem_memReq_deq(l2Tlb$EN_toMem_memReq_deq),
		.EN_toMem_respLd_enq(l2Tlb$EN_toMem_respLd_enq),
		.EN_perf_setStatus(l2Tlb$EN_perf_setStatus),
		.EN_perf_req(l2Tlb$EN_perf_req),
		.EN_perf_resp(l2Tlb$EN_perf_resp),
		.RDY_updateVMInfo(),
		.RDY_toChildren_rqFromC_put(l2Tlb$RDY_toChildren_rqFromC_put),
		.toChildren_rsToC_notEmpty(),
		.RDY_toChildren_rsToC_notEmpty(),
		.RDY_toChildren_rsToC_deq(l2Tlb$RDY_toChildren_rsToC_deq),
		.toChildren_rsToC_first(l2Tlb$toChildren_rsToC_first),
		.RDY_toChildren_rsToC_first(l2Tlb$RDY_toChildren_rsToC_first),
		.RDY_toChildren_iTlbReqFlush_put(l2Tlb$RDY_toChildren_iTlbReqFlush_put),
		.RDY_toChildren_dTlbReqFlush_put(l2Tlb$RDY_toChildren_dTlbReqFlush_put),
		.RDY_toChildren_flushDone_get(l2Tlb$RDY_toChildren_flushDone_get),
		.toMem_memReq_notEmpty(l2Tlb$toMem_memReq_notEmpty),
		.RDY_toMem_memReq_notEmpty(),
		.RDY_toMem_memReq_deq(l2Tlb$RDY_toMem_memReq_deq),
		.toMem_memReq_first(l2Tlb$toMem_memReq_first),
		.RDY_toMem_memReq_first(l2Tlb$RDY_toMem_memReq_first),
		.toMem_respLd_notFull(l2Tlb$toMem_respLd_notFull),
		.RDY_toMem_respLd_notFull(),
		.RDY_toMem_respLd_enq(l2Tlb$RDY_toMem_respLd_enq),
		.RDY_perf_setStatus(),
		.RDY_perf_req(),
		.perf_resp(),
		.RDY_perf_resp(),
		.perf_respValid(),
		.RDY_perf_respValid());

  // submodule mmio_cRqQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_cRqQ_clearReq_dummy2_0(.CLK(CLK),
						       .D_IN(mmio_cRqQ_clearReq_dummy2_0$D_IN),
						       .EN(mmio_cRqQ_clearReq_dummy2_0$EN),
						       .Q_OUT());

  // submodule mmio_cRqQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_cRqQ_clearReq_dummy2_1(.CLK(CLK),
						       .D_IN(mmio_cRqQ_clearReq_dummy2_1$D_IN),
						       .EN(mmio_cRqQ_clearReq_dummy2_1$EN),
						       .Q_OUT(mmio_cRqQ_clearReq_dummy2_1$Q_OUT));

  // submodule mmio_cRqQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_0(.CLK(CLK),
								    .D_IN(mmio_cRqQ_deqReq_dummy2_0$D_IN),
								    .EN(mmio_cRqQ_deqReq_dummy2_0$EN),
								    .Q_OUT());

  // submodule mmio_cRqQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_1(.CLK(CLK),
								    .D_IN(mmio_cRqQ_deqReq_dummy2_1$D_IN),
								    .EN(mmio_cRqQ_deqReq_dummy2_1$EN),
								    .Q_OUT());

  // submodule mmio_cRqQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_2(.CLK(CLK),
								    .D_IN(mmio_cRqQ_deqReq_dummy2_2$D_IN),
								    .EN(mmio_cRqQ_deqReq_dummy2_2$EN),
								    .Q_OUT(mmio_cRqQ_deqReq_dummy2_2$Q_OUT));

  // submodule mmio_cRqQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_0(.CLK(CLK),
								    .D_IN(mmio_cRqQ_enqReq_dummy2_0$D_IN),
								    .EN(mmio_cRqQ_enqReq_dummy2_0$EN),
								    .Q_OUT());

  // submodule mmio_cRqQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_1(.CLK(CLK),
								    .D_IN(mmio_cRqQ_enqReq_dummy2_1$D_IN),
								    .EN(mmio_cRqQ_enqReq_dummy2_1$EN),
								    .Q_OUT());

  // submodule mmio_cRqQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_2(.CLK(CLK),
								    .D_IN(mmio_cRqQ_enqReq_dummy2_2$D_IN),
								    .EN(mmio_cRqQ_enqReq_dummy2_2$EN),
								    .Q_OUT(mmio_cRqQ_enqReq_dummy2_2$Q_OUT));

  // submodule mmio_cRsQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_cRsQ_clearReq_dummy2_0(.CLK(CLK),
						       .D_IN(mmio_cRsQ_clearReq_dummy2_0$D_IN),
						       .EN(mmio_cRsQ_clearReq_dummy2_0$EN),
						       .Q_OUT());

  // submodule mmio_cRsQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_cRsQ_clearReq_dummy2_1(.CLK(CLK),
						       .D_IN(mmio_cRsQ_clearReq_dummy2_1$D_IN),
						       .EN(mmio_cRsQ_clearReq_dummy2_1$EN),
						       .Q_OUT(mmio_cRsQ_clearReq_dummy2_1$Q_OUT));

  // submodule mmio_cRsQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_0(.CLK(CLK),
								    .D_IN(mmio_cRsQ_deqReq_dummy2_0$D_IN),
								    .EN(mmio_cRsQ_deqReq_dummy2_0$EN),
								    .Q_OUT());

  // submodule mmio_cRsQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_1(.CLK(CLK),
								    .D_IN(mmio_cRsQ_deqReq_dummy2_1$D_IN),
								    .EN(mmio_cRsQ_deqReq_dummy2_1$EN),
								    .Q_OUT());

  // submodule mmio_cRsQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_2(.CLK(CLK),
								    .D_IN(mmio_cRsQ_deqReq_dummy2_2$D_IN),
								    .EN(mmio_cRsQ_deqReq_dummy2_2$EN),
								    .Q_OUT(mmio_cRsQ_deqReq_dummy2_2$Q_OUT));

  // submodule mmio_cRsQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_0(.CLK(CLK),
								    .D_IN(mmio_cRsQ_enqReq_dummy2_0$D_IN),
								    .EN(mmio_cRsQ_enqReq_dummy2_0$EN),
								    .Q_OUT());

  // submodule mmio_cRsQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_1(.CLK(CLK),
								    .D_IN(mmio_cRsQ_enqReq_dummy2_1$D_IN),
								    .EN(mmio_cRsQ_enqReq_dummy2_1$EN),
								    .Q_OUT());

  // submodule mmio_cRsQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_2(.CLK(CLK),
								    .D_IN(mmio_cRsQ_enqReq_dummy2_2$D_IN),
								    .EN(mmio_cRsQ_enqReq_dummy2_2$EN),
								    .Q_OUT(mmio_cRsQ_enqReq_dummy2_2$Q_OUT));

  // submodule mmio_dataPendQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataPendQ_clearReq_dummy2_0(.CLK(CLK),
							    .D_IN(mmio_dataPendQ_clearReq_dummy2_0$D_IN),
							    .EN(mmio_dataPendQ_clearReq_dummy2_0$EN),
							    .Q_OUT());

  // submodule mmio_dataPendQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataPendQ_clearReq_dummy2_1(.CLK(CLK),
							    .D_IN(mmio_dataPendQ_clearReq_dummy2_1$D_IN),
							    .EN(mmio_dataPendQ_clearReq_dummy2_1$EN),
							    .Q_OUT(mmio_dataPendQ_clearReq_dummy2_1$Q_OUT));

  // submodule mmio_dataPendQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataPendQ_deqReq_dummy2_0(.CLK(CLK),
							  .D_IN(mmio_dataPendQ_deqReq_dummy2_0$D_IN),
							  .EN(mmio_dataPendQ_deqReq_dummy2_0$EN),
							  .Q_OUT());

  // submodule mmio_dataPendQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataPendQ_deqReq_dummy2_1(.CLK(CLK),
							  .D_IN(mmio_dataPendQ_deqReq_dummy2_1$D_IN),
							  .EN(mmio_dataPendQ_deqReq_dummy2_1$EN),
							  .Q_OUT());

  // submodule mmio_dataPendQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataPendQ_deqReq_dummy2_2(.CLK(CLK),
							  .D_IN(mmio_dataPendQ_deqReq_dummy2_2$D_IN),
							  .EN(mmio_dataPendQ_deqReq_dummy2_2$EN),
							  .Q_OUT(mmio_dataPendQ_deqReq_dummy2_2$Q_OUT));

  // submodule mmio_dataPendQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataPendQ_enqReq_dummy2_0(.CLK(CLK),
							  .D_IN(mmio_dataPendQ_enqReq_dummy2_0$D_IN),
							  .EN(mmio_dataPendQ_enqReq_dummy2_0$EN),
							  .Q_OUT());

  // submodule mmio_dataPendQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataPendQ_enqReq_dummy2_1(.CLK(CLK),
							  .D_IN(mmio_dataPendQ_enqReq_dummy2_1$D_IN),
							  .EN(mmio_dataPendQ_enqReq_dummy2_1$EN),
							  .Q_OUT());

  // submodule mmio_dataPendQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataPendQ_enqReq_dummy2_2(.CLK(CLK),
							  .D_IN(mmio_dataPendQ_enqReq_dummy2_2$D_IN),
							  .EN(mmio_dataPendQ_enqReq_dummy2_2$EN),
							  .Q_OUT(mmio_dataPendQ_enqReq_dummy2_2$Q_OUT));

  // submodule mmio_dataReqQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataReqQ_clearReq_dummy2_0(.CLK(CLK),
							   .D_IN(mmio_dataReqQ_clearReq_dummy2_0$D_IN),
							   .EN(mmio_dataReqQ_clearReq_dummy2_0$EN),
							   .Q_OUT());

  // submodule mmio_dataReqQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataReqQ_clearReq_dummy2_1(.CLK(CLK),
							   .D_IN(mmio_dataReqQ_clearReq_dummy2_1$D_IN),
							   .EN(mmio_dataReqQ_clearReq_dummy2_1$EN),
							   .Q_OUT(mmio_dataReqQ_clearReq_dummy2_1$Q_OUT));

  // submodule mmio_dataReqQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataReqQ_deqReq_dummy2_0(.CLK(CLK),
							 .D_IN(mmio_dataReqQ_deqReq_dummy2_0$D_IN),
							 .EN(mmio_dataReqQ_deqReq_dummy2_0$EN),
							 .Q_OUT());

  // submodule mmio_dataReqQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataReqQ_deqReq_dummy2_1(.CLK(CLK),
							 .D_IN(mmio_dataReqQ_deqReq_dummy2_1$D_IN),
							 .EN(mmio_dataReqQ_deqReq_dummy2_1$EN),
							 .Q_OUT());

  // submodule mmio_dataReqQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataReqQ_deqReq_dummy2_2(.CLK(CLK),
							 .D_IN(mmio_dataReqQ_deqReq_dummy2_2$D_IN),
							 .EN(mmio_dataReqQ_deqReq_dummy2_2$EN),
							 .Q_OUT(mmio_dataReqQ_deqReq_dummy2_2$Q_OUT));

  // submodule mmio_dataReqQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataReqQ_enqReq_dummy2_0(.CLK(CLK),
							 .D_IN(mmio_dataReqQ_enqReq_dummy2_0$D_IN),
							 .EN(mmio_dataReqQ_enqReq_dummy2_0$EN),
							 .Q_OUT());

  // submodule mmio_dataReqQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataReqQ_enqReq_dummy2_1(.CLK(CLK),
							 .D_IN(mmio_dataReqQ_enqReq_dummy2_1$D_IN),
							 .EN(mmio_dataReqQ_enqReq_dummy2_1$EN),
							 .Q_OUT());

  // submodule mmio_dataReqQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataReqQ_enqReq_dummy2_2(.CLK(CLK),
							 .D_IN(mmio_dataReqQ_enqReq_dummy2_2$D_IN),
							 .EN(mmio_dataReqQ_enqReq_dummy2_2$EN),
							 .Q_OUT(mmio_dataReqQ_enqReq_dummy2_2$Q_OUT));

  // submodule mmio_dataRespQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataRespQ_clearReq_dummy2_0(.CLK(CLK),
							    .D_IN(mmio_dataRespQ_clearReq_dummy2_0$D_IN),
							    .EN(mmio_dataRespQ_clearReq_dummy2_0$EN),
							    .Q_OUT());

  // submodule mmio_dataRespQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataRespQ_clearReq_dummy2_1(.CLK(CLK),
							    .D_IN(mmio_dataRespQ_clearReq_dummy2_1$D_IN),
							    .EN(mmio_dataRespQ_clearReq_dummy2_1$EN),
							    .Q_OUT(mmio_dataRespQ_clearReq_dummy2_1$Q_OUT));

  // submodule mmio_dataRespQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataRespQ_deqReq_dummy2_0(.CLK(CLK),
							  .D_IN(mmio_dataRespQ_deqReq_dummy2_0$D_IN),
							  .EN(mmio_dataRespQ_deqReq_dummy2_0$EN),
							  .Q_OUT());

  // submodule mmio_dataRespQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataRespQ_deqReq_dummy2_1(.CLK(CLK),
							  .D_IN(mmio_dataRespQ_deqReq_dummy2_1$D_IN),
							  .EN(mmio_dataRespQ_deqReq_dummy2_1$EN),
							  .Q_OUT());

  // submodule mmio_dataRespQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataRespQ_deqReq_dummy2_2(.CLK(CLK),
							  .D_IN(mmio_dataRespQ_deqReq_dummy2_2$D_IN),
							  .EN(mmio_dataRespQ_deqReq_dummy2_2$EN),
							  .Q_OUT(mmio_dataRespQ_deqReq_dummy2_2$Q_OUT));

  // submodule mmio_dataRespQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataRespQ_enqReq_dummy2_0(.CLK(CLK),
							  .D_IN(mmio_dataRespQ_enqReq_dummy2_0$D_IN),
							  .EN(mmio_dataRespQ_enqReq_dummy2_0$EN),
							  .Q_OUT());

  // submodule mmio_dataRespQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataRespQ_enqReq_dummy2_1(.CLK(CLK),
							  .D_IN(mmio_dataRespQ_enqReq_dummy2_1$D_IN),
							  .EN(mmio_dataRespQ_enqReq_dummy2_1$EN),
							  .Q_OUT());

  // submodule mmio_dataRespQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataRespQ_enqReq_dummy2_2(.CLK(CLK),
							  .D_IN(mmio_dataRespQ_enqReq_dummy2_2$D_IN),
							  .EN(mmio_dataRespQ_enqReq_dummy2_2$EN),
							  .Q_OUT(mmio_dataRespQ_enqReq_dummy2_2$Q_OUT));

  // submodule mmio_pRqQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_pRqQ_clearReq_dummy2_0(.CLK(CLK),
						       .D_IN(mmio_pRqQ_clearReq_dummy2_0$D_IN),
						       .EN(mmio_pRqQ_clearReq_dummy2_0$EN),
						       .Q_OUT());

  // submodule mmio_pRqQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_pRqQ_clearReq_dummy2_1(.CLK(CLK),
						       .D_IN(mmio_pRqQ_clearReq_dummy2_1$D_IN),
						       .EN(mmio_pRqQ_clearReq_dummy2_1$EN),
						       .Q_OUT(mmio_pRqQ_clearReq_dummy2_1$Q_OUT));

  // submodule mmio_pRqQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_0(.CLK(CLK),
								    .D_IN(mmio_pRqQ_deqReq_dummy2_0$D_IN),
								    .EN(mmio_pRqQ_deqReq_dummy2_0$EN),
								    .Q_OUT());

  // submodule mmio_pRqQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_1(.CLK(CLK),
								    .D_IN(mmio_pRqQ_deqReq_dummy2_1$D_IN),
								    .EN(mmio_pRqQ_deqReq_dummy2_1$EN),
								    .Q_OUT());

  // submodule mmio_pRqQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_2(.CLK(CLK),
								    .D_IN(mmio_pRqQ_deqReq_dummy2_2$D_IN),
								    .EN(mmio_pRqQ_deqReq_dummy2_2$EN),
								    .Q_OUT(mmio_pRqQ_deqReq_dummy2_2$Q_OUT));

  // submodule mmio_pRqQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_0(.CLK(CLK),
								    .D_IN(mmio_pRqQ_enqReq_dummy2_0$D_IN),
								    .EN(mmio_pRqQ_enqReq_dummy2_0$EN),
								    .Q_OUT());

  // submodule mmio_pRqQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_1(.CLK(CLK),
								    .D_IN(mmio_pRqQ_enqReq_dummy2_1$D_IN),
								    .EN(mmio_pRqQ_enqReq_dummy2_1$EN),
								    .Q_OUT());

  // submodule mmio_pRqQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_2(.CLK(CLK),
								    .D_IN(mmio_pRqQ_enqReq_dummy2_2$D_IN),
								    .EN(mmio_pRqQ_enqReq_dummy2_2$EN),
								    .Q_OUT(mmio_pRqQ_enqReq_dummy2_2$Q_OUT));

  // submodule mmio_pRsQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_pRsQ_clearReq_dummy2_0(.CLK(CLK),
						       .D_IN(mmio_pRsQ_clearReq_dummy2_0$D_IN),
						       .EN(mmio_pRsQ_clearReq_dummy2_0$EN),
						       .Q_OUT());

  // submodule mmio_pRsQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_pRsQ_clearReq_dummy2_1(.CLK(CLK),
						       .D_IN(mmio_pRsQ_clearReq_dummy2_1$D_IN),
						       .EN(mmio_pRsQ_clearReq_dummy2_1$EN),
						       .Q_OUT(mmio_pRsQ_clearReq_dummy2_1$Q_OUT));

  // submodule mmio_pRsQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_0(.CLK(CLK),
								    .D_IN(mmio_pRsQ_deqReq_dummy2_0$D_IN),
								    .EN(mmio_pRsQ_deqReq_dummy2_0$EN),
								    .Q_OUT());

  // submodule mmio_pRsQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_1(.CLK(CLK),
								    .D_IN(mmio_pRsQ_deqReq_dummy2_1$D_IN),
								    .EN(mmio_pRsQ_deqReq_dummy2_1$EN),
								    .Q_OUT());

  // submodule mmio_pRsQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_2(.CLK(CLK),
								    .D_IN(mmio_pRsQ_deqReq_dummy2_2$D_IN),
								    .EN(mmio_pRsQ_deqReq_dummy2_2$EN),
								    .Q_OUT(mmio_pRsQ_deqReq_dummy2_2$Q_OUT));

  // submodule mmio_pRsQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_0(.CLK(CLK),
								    .D_IN(mmio_pRsQ_enqReq_dummy2_0$D_IN),
								    .EN(mmio_pRsQ_enqReq_dummy2_0$EN),
								    .Q_OUT());

  // submodule mmio_pRsQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_1(.CLK(CLK),
								    .D_IN(mmio_pRsQ_enqReq_dummy2_1$D_IN),
								    .EN(mmio_pRsQ_enqReq_dummy2_1$EN),
								    .Q_OUT());

  // submodule mmio_pRsQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_2(.CLK(CLK),
								    .D_IN(mmio_pRsQ_enqReq_dummy2_2$D_IN),
								    .EN(mmio_pRsQ_enqReq_dummy2_2$EN),
								    .Q_OUT(mmio_pRsQ_enqReq_dummy2_2$Q_OUT));

  // submodule perfReqQ
  FIFO1 #(.width(32'd9), .guarded(32'd1)) perfReqQ(.RST(RST_N),
						   .CLK(CLK),
						   .D_IN(perfReqQ$D_IN),
						   .ENQ(perfReqQ$ENQ),
						   .DEQ(perfReqQ$DEQ),
						   .CLR(perfReqQ$CLR),
						   .D_OUT(perfReqQ$D_OUT),
						   .FULL_N(perfReqQ$FULL_N),
						   .EMPTY_N(perfReqQ$EMPTY_N));

  // submodule regRenamingTable
  mkRegRenamingTable regRenamingTable(.CLK(CLK),
				      .RST_N(RST_N),
				      .rename_0_claimRename_r(regRenamingTable$rename_0_claimRename_r),
				      .rename_0_claimRename_sb(regRenamingTable$rename_0_claimRename_sb),
				      .rename_0_getRename_r(regRenamingTable$rename_0_getRename_r),
				      .rename_1_claimRename_r(regRenamingTable$rename_1_claimRename_r),
				      .rename_1_claimRename_sb(regRenamingTable$rename_1_claimRename_sb),
				      .rename_1_getRename_r(regRenamingTable$rename_1_getRename_r),
				      .specUpdate_correctSpeculation_mask(regRenamingTable$specUpdate_correctSpeculation_mask),
				      .specUpdate_incorrectSpeculation_kill_all(regRenamingTable$specUpdate_incorrectSpeculation_kill_all),
				      .specUpdate_incorrectSpeculation_kill_tag(regRenamingTable$specUpdate_incorrectSpeculation_kill_tag),
				      .EN_rename_0_claimRename(regRenamingTable$EN_rename_0_claimRename),
				      .EN_rename_1_claimRename(regRenamingTable$EN_rename_1_claimRename),
				      .EN_commit_0_commit(regRenamingTable$EN_commit_0_commit),
				      .EN_commit_1_commit(regRenamingTable$EN_commit_1_commit),
				      .EN_specUpdate_incorrectSpeculation(regRenamingTable$EN_specUpdate_incorrectSpeculation),
				      .EN_specUpdate_correctSpeculation(regRenamingTable$EN_specUpdate_correctSpeculation),
				      .rename_0_getRename(regRenamingTable$rename_0_getRename),
				      .RDY_rename_0_getRename(regRenamingTable$RDY_rename_0_getRename),
				      .RDY_rename_0_claimRename(regRenamingTable$RDY_rename_0_claimRename),
				      .rename_0_canRename(regRenamingTable$rename_0_canRename),
				      .RDY_rename_0_canRename(),
				      .rename_1_getRename(regRenamingTable$rename_1_getRename),
				      .RDY_rename_1_getRename(regRenamingTable$RDY_rename_1_getRename),
				      .RDY_rename_1_claimRename(regRenamingTable$RDY_rename_1_claimRename),
				      .rename_1_canRename(regRenamingTable$rename_1_canRename),
				      .RDY_rename_1_canRename(),
				      .RDY_commit_0_commit(regRenamingTable$RDY_commit_0_commit),
				      .commit_0_canCommit(),
				      .RDY_commit_0_canCommit(),
				      .RDY_commit_1_commit(regRenamingTable$RDY_commit_1_commit),
				      .commit_1_canCommit(),
				      .RDY_commit_1_canCommit(),
				      .RDY_specUpdate_incorrectSpeculation(),
				      .RDY_specUpdate_correctSpeculation());

  // submodule rf
  mkRFileSynth rf(.CLK(CLK),
		  .RST_N(RST_N),
		  .read_0_rd1_rindx(rf$read_0_rd1_rindx),
		  .read_0_rd2_rindx(rf$read_0_rd2_rindx),
		  .read_0_rd3_rindx(rf$read_0_rd3_rindx),
		  .read_1_rd1_rindx(rf$read_1_rd1_rindx),
		  .read_1_rd2_rindx(rf$read_1_rd2_rindx),
		  .read_1_rd3_rindx(rf$read_1_rd3_rindx),
		  .read_2_rd1_rindx(rf$read_2_rd1_rindx),
		  .read_2_rd2_rindx(rf$read_2_rd2_rindx),
		  .read_2_rd3_rindx(rf$read_2_rd3_rindx),
		  .read_3_rd1_rindx(rf$read_3_rd1_rindx),
		  .read_3_rd2_rindx(rf$read_3_rd2_rindx),
		  .read_3_rd3_rindx(rf$read_3_rd3_rindx),
		  .read_4_rd1_rindx(rf$read_4_rd1_rindx),
		  .read_4_rd2_rindx(rf$read_4_rd2_rindx),
		  .read_4_rd3_rindx(rf$read_4_rd3_rindx),
		  .write_0_wr_data(rf$write_0_wr_data),
		  .write_0_wr_rindx(rf$write_0_wr_rindx),
		  .write_1_wr_data(rf$write_1_wr_data),
		  .write_1_wr_rindx(rf$write_1_wr_rindx),
		  .write_2_wr_data(rf$write_2_wr_data),
		  .write_2_wr_rindx(rf$write_2_wr_rindx),
		  .write_3_wr_data(rf$write_3_wr_data),
		  .write_3_wr_rindx(rf$write_3_wr_rindx),
		  .write_4_wr_data(rf$write_4_wr_data),
		  .write_4_wr_rindx(rf$write_4_wr_rindx),
		  .EN_write_0_wr(rf$EN_write_0_wr),
		  .EN_write_1_wr(rf$EN_write_1_wr),
		  .EN_write_2_wr(rf$EN_write_2_wr),
		  .EN_write_3_wr(rf$EN_write_3_wr),
		  .EN_write_4_wr(rf$EN_write_4_wr),
		  .RDY_write_0_wr(),
		  .RDY_write_1_wr(),
		  .RDY_write_2_wr(),
		  .RDY_write_3_wr(),
		  .RDY_write_4_wr(),
		  .read_0_rd1(rf$read_0_rd1),
		  .RDY_read_0_rd1(),
		  .read_0_rd2(rf$read_0_rd2),
		  .RDY_read_0_rd2(),
		  .read_0_rd3(),
		  .RDY_read_0_rd3(),
		  .read_1_rd1(rf$read_1_rd1),
		  .RDY_read_1_rd1(),
		  .read_1_rd2(rf$read_1_rd2),
		  .RDY_read_1_rd2(),
		  .read_1_rd3(),
		  .RDY_read_1_rd3(),
		  .read_2_rd1(rf$read_2_rd1),
		  .RDY_read_2_rd1(),
		  .read_2_rd2(rf$read_2_rd2),
		  .RDY_read_2_rd2(),
		  .read_2_rd3(rf$read_2_rd3),
		  .RDY_read_2_rd3(),
		  .read_3_rd1(rf$read_3_rd1),
		  .RDY_read_3_rd1(),
		  .read_3_rd2(rf$read_3_rd2),
		  .RDY_read_3_rd2(),
		  .read_3_rd3(),
		  .RDY_read_3_rd3(),
		  .read_4_rd1(rf$read_4_rd1),
		  .RDY_read_4_rd1(),
		  .read_4_rd2(),
		  .RDY_read_4_rd2(),
		  .read_4_rd3(),
		  .RDY_read_4_rd3());

  // submodule rob
  mkReorderBufferSynth rob(.CLK(CLK),
			   .RST_N(RST_N),
			   .enqPort_0_enq_x(rob$enqPort_0_enq_x),
			   .enqPort_1_enq_x(rob$enqPort_1_enq_x),
			   .getOrigPC_0_get_x(rob$getOrigPC_0_get_x),
			   .getOrigPC_1_get_x(rob$getOrigPC_1_get_x),
			   .getOrigPC_2_get_x(rob$getOrigPC_2_get_x),
			   .getOrigPredPC_0_get_x(rob$getOrigPredPC_0_get_x),
			   .getOrigPredPC_1_get_x(rob$getOrigPredPC_1_get_x),
			   .getOrig_Inst_0_get_x(rob$getOrig_Inst_0_get_x),
			   .getOrig_Inst_1_get_x(rob$getOrig_Inst_1_get_x),
			   .setExecuted_deqLSQ_cause(rob$setExecuted_deqLSQ_cause),
			   .setExecuted_deqLSQ_ld_killed(rob$setExecuted_deqLSQ_ld_killed),
			   .setExecuted_deqLSQ_x(rob$setExecuted_deqLSQ_x),
			   .setExecuted_doFinishAlu_0_set_cf(rob$setExecuted_doFinishAlu_0_set_cf),
			   .setExecuted_doFinishAlu_0_set_csrData(rob$setExecuted_doFinishAlu_0_set_csrData),
			   .setExecuted_doFinishAlu_0_set_dst_data(rob$setExecuted_doFinishAlu_0_set_dst_data),
			   .setExecuted_doFinishAlu_0_set_x(rob$setExecuted_doFinishAlu_0_set_x),
			   .setExecuted_doFinishAlu_1_set_cf(rob$setExecuted_doFinishAlu_1_set_cf),
			   .setExecuted_doFinishAlu_1_set_csrData(rob$setExecuted_doFinishAlu_1_set_csrData),
			   .setExecuted_doFinishAlu_1_set_dst_data(rob$setExecuted_doFinishAlu_1_set_dst_data),
			   .setExecuted_doFinishAlu_1_set_x(rob$setExecuted_doFinishAlu_1_set_x),
			   .setExecuted_doFinishFpuMulDiv_0_set_dst_data(rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data),
			   .setExecuted_doFinishFpuMulDiv_0_set_fflags(rob$setExecuted_doFinishFpuMulDiv_0_set_fflags),
			   .setExecuted_doFinishFpuMulDiv_0_set_x(rob$setExecuted_doFinishFpuMulDiv_0_set_x),
			   .setExecuted_doFinishMem_RegData_dst_data(rob$setExecuted_doFinishMem_RegData_dst_data),
			   .setExecuted_doFinishMem_RegData_x(rob$setExecuted_doFinishMem_RegData_x),
			   .setExecuted_doFinishMem_access_at_commit(rob$setExecuted_doFinishMem_access_at_commit),
			   .setExecuted_doFinishMem_non_mmio_st_done(rob$setExecuted_doFinishMem_non_mmio_st_done),
			   .setExecuted_doFinishMem_store_data(rob$setExecuted_doFinishMem_store_data),
			   .setExecuted_doFinishMem_store_data_BE(rob$setExecuted_doFinishMem_store_data_BE),
			   .setExecuted_doFinishMem_vaddr(rob$setExecuted_doFinishMem_vaddr),
			   .setExecuted_doFinishMem_x(rob$setExecuted_doFinishMem_x),
			   .setLSQAtCommitNotified_x(rob$setLSQAtCommitNotified_x),
			   .specUpdate_correctSpeculation_mask(rob$specUpdate_correctSpeculation_mask),
			   .specUpdate_incorrectSpeculation_inst_tag(rob$specUpdate_incorrectSpeculation_inst_tag),
			   .specUpdate_incorrectSpeculation_kill_all(rob$specUpdate_incorrectSpeculation_kill_all),
			   .specUpdate_incorrectSpeculation_spec_tag(rob$specUpdate_incorrectSpeculation_spec_tag),
			   .EN_enqPort_0_enq(rob$EN_enqPort_0_enq),
			   .EN_enqPort_1_enq(rob$EN_enqPort_1_enq),
			   .EN_deqPort_0_deq(rob$EN_deqPort_0_deq),
			   .EN_deqPort_1_deq(rob$EN_deqPort_1_deq),
			   .EN_setLSQAtCommitNotified(rob$EN_setLSQAtCommitNotified),
			   .EN_setExecuted_deqLSQ(rob$EN_setExecuted_deqLSQ),
			   .EN_setExecuted_doFinishAlu_0_set(rob$EN_setExecuted_doFinishAlu_0_set),
			   .EN_setExecuted_doFinishAlu_1_set(rob$EN_setExecuted_doFinishAlu_1_set),
			   .EN_setExecuted_doFinishFpuMulDiv_0_set(rob$EN_setExecuted_doFinishFpuMulDiv_0_set),
			   .EN_setExecuted_doFinishMem(rob$EN_setExecuted_doFinishMem),
			   .EN_setExecuted_doFinishMem_RegData(rob$EN_setExecuted_doFinishMem_RegData),
			   .EN_specUpdate_incorrectSpeculation(rob$EN_specUpdate_incorrectSpeculation),
			   .EN_specUpdate_correctSpeculation(rob$EN_specUpdate_correctSpeculation),
			   .enqPort_0_canEnq(rob$enqPort_0_canEnq),
			   .RDY_enqPort_0_canEnq(),
			   .RDY_enqPort_0_enq(rob$RDY_enqPort_0_enq),
			   .enqPort_0_getEnqInstTag(rob$enqPort_0_getEnqInstTag),
			   .RDY_enqPort_0_getEnqInstTag(),
			   .enqPort_1_canEnq(rob$enqPort_1_canEnq),
			   .RDY_enqPort_1_canEnq(),
			   .RDY_enqPort_1_enq(rob$RDY_enqPort_1_enq),
			   .enqPort_1_getEnqInstTag(rob$enqPort_1_getEnqInstTag),
			   .RDY_enqPort_1_getEnqInstTag(),
			   .isEmpty(rob$isEmpty),
			   .RDY_isEmpty(),
			   .deqPort_0_canDeq(rob$deqPort_0_canDeq),
			   .RDY_deqPort_0_canDeq(),
			   .RDY_deqPort_0_deq(rob$RDY_deqPort_0_deq),
			   .deqPort_0_getDeqInstTag(rob$deqPort_0_getDeqInstTag),
			   .RDY_deqPort_0_getDeqInstTag(),
			   .deqPort_0_deq_data(rob$deqPort_0_deq_data),
			   .RDY_deqPort_0_deq_data(rob$RDY_deqPort_0_deq_data),
			   .deqPort_1_canDeq(rob$deqPort_1_canDeq),
			   .RDY_deqPort_1_canDeq(),
			   .RDY_deqPort_1_deq(rob$RDY_deqPort_1_deq),
			   .deqPort_1_getDeqInstTag(),
			   .RDY_deqPort_1_getDeqInstTag(),
			   .deqPort_1_deq_data(rob$deqPort_1_deq_data),
			   .RDY_deqPort_1_deq_data(rob$RDY_deqPort_1_deq_data),
			   .RDY_setLSQAtCommitNotified(rob$RDY_setLSQAtCommitNotified),
			   .RDY_setExecuted_deqLSQ(rob$RDY_setExecuted_deqLSQ),
			   .RDY_setExecuted_doFinishAlu_0_set(rob$RDY_setExecuted_doFinishAlu_0_set),
			   .RDY_setExecuted_doFinishAlu_1_set(rob$RDY_setExecuted_doFinishAlu_1_set),
			   .RDY_setExecuted_doFinishFpuMulDiv_0_set(rob$RDY_setExecuted_doFinishFpuMulDiv_0_set),
			   .RDY_setExecuted_doFinishMem(rob$RDY_setExecuted_doFinishMem),
			   .RDY_setExecuted_doFinishMem_RegData(),
			   .getOrigPC_0_get(rob$getOrigPC_0_get),
			   .RDY_getOrigPC_0_get(),
			   .getOrigPC_1_get(rob$getOrigPC_1_get),
			   .RDY_getOrigPC_1_get(),
			   .getOrigPC_2_get(),
			   .RDY_getOrigPC_2_get(),
			   .getOrigPredPC_0_get(rob$getOrigPredPC_0_get),
			   .RDY_getOrigPredPC_0_get(),
			   .getOrigPredPC_1_get(rob$getOrigPredPC_1_get),
			   .RDY_getOrigPredPC_1_get(),
			   .getOrig_Inst_0_get(rob$getOrig_Inst_0_get),
			   .RDY_getOrig_Inst_0_get(),
			   .getOrig_Inst_1_get(rob$getOrig_Inst_1_get),
			   .RDY_getOrig_Inst_1_get(),
			   .getEnqTime(rob$getEnqTime),
			   .RDY_getEnqTime(),
			   .isEmpty_ehrPort0(),
			   .RDY_isEmpty_ehrPort0(),
			   .isFull_ehrPort0(),
			   .RDY_isFull_ehrPort0(),
			   .RDY_specUpdate_incorrectSpeculation(),
			   .RDY_specUpdate_correctSpeculation());

  // submodule sbAggr
  mkScoreboardAggr sbAggr(.CLK(CLK),
			  .RST_N(RST_N),
			  .eagerLookup_0_get_r(sbAggr$eagerLookup_0_get_r),
			  .eagerLookup_1_get_r(sbAggr$eagerLookup_1_get_r),
			  .setBusy_0_set_dst(sbAggr$setBusy_0_set_dst),
			  .setBusy_1_set_dst(sbAggr$setBusy_1_set_dst),
			  .setReady_0_put(sbAggr$setReady_0_put),
			  .setReady_1_put(sbAggr$setReady_1_put),
			  .setReady_2_put(sbAggr$setReady_2_put),
			  .setReady_3_put(sbAggr$setReady_3_put),
			  .setReady_4_put(sbAggr$setReady_4_put),
			  .EN_setBusy_0_set(sbAggr$EN_setBusy_0_set),
			  .EN_setBusy_1_set(sbAggr$EN_setBusy_1_set),
			  .EN_setReady_0_put(sbAggr$EN_setReady_0_put),
			  .EN_setReady_1_put(sbAggr$EN_setReady_1_put),
			  .EN_setReady_2_put(sbAggr$EN_setReady_2_put),
			  .EN_setReady_3_put(sbAggr$EN_setReady_3_put),
			  .EN_setReady_4_put(sbAggr$EN_setReady_4_put),
			  .eagerLookup_0_get(sbAggr$eagerLookup_0_get),
			  .RDY_eagerLookup_0_get(),
			  .eagerLookup_1_get(sbAggr$eagerLookup_1_get),
			  .RDY_eagerLookup_1_get(),
			  .RDY_setBusy_0_set(),
			  .RDY_setBusy_1_set(),
			  .RDY_setReady_0_put(),
			  .RDY_setReady_1_put(),
			  .RDY_setReady_2_put(),
			  .RDY_setReady_3_put(),
			  .RDY_setReady_4_put());

  // submodule sbCons
  mkScoreboardCons sbCons(.CLK(CLK),
			  .RST_N(RST_N),
			  .eagerLookup_0_get_r(sbCons$eagerLookup_0_get_r),
			  .eagerLookup_1_get_r(sbCons$eagerLookup_1_get_r),
			  .lazyLookup_0_get_r(sbCons$lazyLookup_0_get_r),
			  .lazyLookup_1_get_r(sbCons$lazyLookup_1_get_r),
			  .lazyLookup_2_get_r(sbCons$lazyLookup_2_get_r),
			  .lazyLookup_3_get_r(sbCons$lazyLookup_3_get_r),
			  .lazyLookup_4_get_r(sbCons$lazyLookup_4_get_r),
			  .setBusy_0_set_dst(sbCons$setBusy_0_set_dst),
			  .setBusy_1_set_dst(sbCons$setBusy_1_set_dst),
			  .setReady_0_put(sbCons$setReady_0_put),
			  .setReady_1_put(sbCons$setReady_1_put),
			  .setReady_2_put(sbCons$setReady_2_put),
			  .setReady_3_put(sbCons$setReady_3_put),
			  .setReady_4_put(sbCons$setReady_4_put),
			  .EN_setBusy_0_set(sbCons$EN_setBusy_0_set),
			  .EN_setBusy_1_set(sbCons$EN_setBusy_1_set),
			  .EN_setReady_0_put(sbCons$EN_setReady_0_put),
			  .EN_setReady_1_put(sbCons$EN_setReady_1_put),
			  .EN_setReady_2_put(sbCons$EN_setReady_2_put),
			  .EN_setReady_3_put(sbCons$EN_setReady_3_put),
			  .EN_setReady_4_put(sbCons$EN_setReady_4_put),
			  .eagerLookup_0_get(),
			  .RDY_eagerLookup_0_get(),
			  .eagerLookup_1_get(),
			  .RDY_eagerLookup_1_get(),
			  .RDY_setBusy_0_set(),
			  .RDY_setBusy_1_set(),
			  .RDY_setReady_0_put(),
			  .RDY_setReady_1_put(),
			  .RDY_setReady_2_put(),
			  .RDY_setReady_3_put(),
			  .RDY_setReady_4_put(),
			  .lazyLookup_0_get(sbCons$lazyLookup_0_get),
			  .RDY_lazyLookup_0_get(),
			  .lazyLookup_1_get(sbCons$lazyLookup_1_get),
			  .RDY_lazyLookup_1_get(),
			  .lazyLookup_2_get(sbCons$lazyLookup_2_get),
			  .RDY_lazyLookup_2_get(),
			  .lazyLookup_3_get(sbCons$lazyLookup_3_get),
			  .RDY_lazyLookup_3_get(),
			  .lazyLookup_4_get(),
			  .RDY_lazyLookup_4_get());

  // submodule specTagManager
  mkSpecTagManager specTagManager(.CLK(CLK),
				  .RST_N(RST_N),
				  .specUpdate_correctSpeculation_mask(specTagManager$specUpdate_correctSpeculation_mask),
				  .specUpdate_incorrectSpeculation_kill_all(specTagManager$specUpdate_incorrectSpeculation_kill_all),
				  .specUpdate_incorrectSpeculation_kill_tag(specTagManager$specUpdate_incorrectSpeculation_kill_tag),
				  .EN_claimSpecTag(specTagManager$EN_claimSpecTag),
				  .EN_specUpdate_incorrectSpeculation(specTagManager$EN_specUpdate_incorrectSpeculation),
				  .EN_specUpdate_correctSpeculation(specTagManager$EN_specUpdate_correctSpeculation),
				  .currentSpecBits(specTagManager$currentSpecBits),
				  .RDY_currentSpecBits(),
				  .nextSpecTag(specTagManager$nextSpecTag),
				  .RDY_nextSpecTag(specTagManager$RDY_nextSpecTag),
				  .RDY_claimSpecTag(specTagManager$RDY_claimSpecTag),
				  .canClaim(specTagManager$canClaim),
				  .RDY_canClaim(),
				  .RDY_specUpdate_incorrectSpeculation(),
				  .RDY_specUpdate_correctSpeculation(),
				  .isFull_ehrPort0(),
				  .RDY_isFull_ehrPort0());

  // submodule v_f_to_TV_0
  FIFO2 #(.width(32'd862), .guarded(32'd1)) v_f_to_TV_0(.RST(RST_N),
							.CLK(CLK),
							.D_IN(v_f_to_TV_0$D_IN),
							.ENQ(v_f_to_TV_0$ENQ),
							.DEQ(v_f_to_TV_0$DEQ),
							.CLR(v_f_to_TV_0$CLR),
							.D_OUT(v_f_to_TV_0$D_OUT),
							.FULL_N(v_f_to_TV_0$FULL_N),
							.EMPTY_N(v_f_to_TV_0$EMPTY_N));

  // submodule v_f_to_TV_1
  FIFO2 #(.width(32'd862), .guarded(32'd1)) v_f_to_TV_1(.RST(RST_N),
							.CLK(CLK),
							.D_IN(v_f_to_TV_1$D_IN),
							.ENQ(v_f_to_TV_1$ENQ),
							.DEQ(v_f_to_TV_1$DEQ),
							.CLR(v_f_to_TV_1$CLR),
							.D_OUT(v_f_to_TV_1$D_OUT),
							.FULL_N(v_f_to_TV_1$FULL_N),
							.EMPTY_N(v_f_to_TV_1$EMPTY_N));

  // rule RL_rl_outOfReset
  assign CAN_FIRE_RL_rl_outOfReset = !outOfReset ;
  assign WILL_FIRE_RL_rl_outOfReset = CAN_FIRE_RL_rl_outOfReset ;

  // rule RL_sendDTlbReq
  assign CAN_FIRE_RL_sendDTlbReq =
	     coreFix_memExe_dTlb$RDY_toParent_rqToP_deq &&
	     coreFix_memExe_dTlb$RDY_toParent_rqToP_first &&
	     l2Tlb$RDY_toChildren_rqFromC_put ;
  assign WILL_FIRE_RL_sendDTlbReq = CAN_FIRE_RL_sendDTlbReq ;

  // rule RL_sendITlbReq
  assign CAN_FIRE_RL_sendITlbReq =
	     fetchStage$RDY_iTlbIfc_toParent_rqToP_deq &&
	     fetchStage$RDY_iTlbIfc_toParent_rqToP_first &&
	     l2Tlb$RDY_toChildren_rqFromC_put ;
  assign WILL_FIRE_RL_sendITlbReq =
	     CAN_FIRE_RL_sendITlbReq && !WILL_FIRE_RL_sendDTlbReq ;

  // rule RL_sendRsToDTlb
  assign CAN_FIRE_RL_sendRsToDTlb =
	     l2Tlb$RDY_toChildren_rsToC_deq &&
	     l2Tlb$RDY_toChildren_rsToC_first &&
	     coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq &&
	     l2Tlb$toChildren_rsToC_first[83] ;
  assign WILL_FIRE_RL_sendRsToDTlb = CAN_FIRE_RL_sendRsToDTlb ;

  // rule RL_sendRsToITlb
  assign CAN_FIRE_RL_sendRsToITlb =
	     fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq &&
	     l2Tlb$RDY_toChildren_rsToC_deq &&
	     l2Tlb$RDY_toChildren_rsToC_first &&
	     !l2Tlb$toChildren_rsToC_first[83] ;
  assign WILL_FIRE_RL_sendRsToITlb = CAN_FIRE_RL_sendRsToITlb ;

  // rule RL_mkConnectionGetPut
  assign CAN_FIRE_RL_mkConnectionGetPut =
	     coreFix_memExe_dTlb$RDY_toParent_flush_request_get &&
	     l2Tlb$RDY_toChildren_dTlbReqFlush_put ;
  assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ;

  // rule RL_mkConnectionGetPut_1
  assign CAN_FIRE_RL_mkConnectionGetPut_1 =
	     fetchStage$RDY_iTlbIfc_toParent_flush_request_get &&
	     l2Tlb$RDY_toChildren_iTlbReqFlush_put ;
  assign WILL_FIRE_RL_mkConnectionGetPut_1 =
	     CAN_FIRE_RL_mkConnectionGetPut_1 ;

  // rule RL_sendFlushDone
  assign CAN_FIRE_RL_sendFlushDone =
	     fetchStage$RDY_iTlbIfc_toParent_flush_response_put &&
	     coreFix_memExe_dTlb$RDY_toParent_flush_response_put &&
	     l2Tlb$RDY_toChildren_flushDone_get ;
  assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ;

  // rule RL_sendRobEnqTime
  assign CAN_FIRE_RL_sendRobEnqTime = 1'd1 ;
  assign WILL_FIRE_RL_sendRobEnqTime = 1'd1 ;

  // rule RL_setDoFlushCaches
  assign CAN_FIRE_RL_setDoFlushCaches =
	     flush_caches && fetchStage$emptyForFlush &&
	     coreFix_memExe_lsq$noWrongPathLoads ;
  assign WILL_FIRE_RL_setDoFlushCaches = CAN_FIRE_RL_setDoFlushCaches ;

  // rule RL_setDoFlushBrPred
  assign CAN_FIRE_RL_setDoFlushBrPred =
	     flush_brpred && fetchStage$emptyForFlush ;
  assign WILL_FIRE_RL_setDoFlushBrPred = CAN_FIRE_RL_setDoFlushBrPred ;

  // rule RL_readyToFetch
  assign CAN_FIRE_RL_readyToFetch =
	     fetchStage$RDY_done_flushing &&
	     rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15738 &&
	     !flush_brpred &&
	     fetchStage$iMemIfc_flush_done &&
	     fetchStage$flush_predictors_done ;
  assign WILL_FIRE_RL_readyToFetch = CAN_FIRE_RL_readyToFetch ;

  // rule RL_flushCaches
  assign CAN_FIRE_RL_flushCaches = CAN_FIRE_RL_setDoFlushCaches ;
  assign WILL_FIRE_RL_flushCaches = CAN_FIRE_RL_setDoFlushCaches ;

  // rule RL_flushBrPred
  assign CAN_FIRE_RL_flushBrPred = CAN_FIRE_RL_setDoFlushBrPred ;
  assign WILL_FIRE_RL_flushBrPred = CAN_FIRE_RL_setDoFlushBrPred ;

  // rule RL_rl_debug_gpr_read
  assign CAN_FIRE_RL_rl_debug_gpr_read =
	     regRenamingTable$RDY_rename_0_getRename && f_gpr_reqs$EMPTY_N &&
	     f_gpr_rsps$FULL_N &&
	     rg_core_run_state == 2'd1 &&
	     !f_gpr_reqs$D_OUT[69] ;
  assign WILL_FIRE_RL_rl_debug_gpr_read = CAN_FIRE_RL_rl_debug_gpr_read ;

  // rule RL_rl_debug_gpr_access_busy
  assign CAN_FIRE_RL_rl_debug_gpr_access_busy =
	     f_gpr_reqs$EMPTY_N && f_gpr_rsps$FULL_N &&
	     rg_core_run_state == 2'd2 ;
  assign WILL_FIRE_RL_rl_debug_gpr_access_busy =
	     CAN_FIRE_RL_rl_debug_gpr_access_busy ;

  // rule RL_rl_debug_fpr_read
  assign CAN_FIRE_RL_rl_debug_fpr_read =
	     regRenamingTable$RDY_rename_0_getRename && f_fpr_reqs$EMPTY_N &&
	     f_fpr_rsps$FULL_N &&
	     rg_core_run_state == 2'd1 &&
	     !f_gpr_reqs$EMPTY_N &&
	     !f_fpr_reqs$D_OUT[69] ;
  assign WILL_FIRE_RL_rl_debug_fpr_read = CAN_FIRE_RL_rl_debug_fpr_read ;

  // rule RL_rl_debug_fpr_access_busy
  assign CAN_FIRE_RL_rl_debug_fpr_access_busy =
	     f_fpr_reqs$EMPTY_N && f_fpr_rsps$FULL_N &&
	     rg_core_run_state == 2'd2 ;
  assign WILL_FIRE_RL_rl_debug_fpr_access_busy =
	     CAN_FIRE_RL_rl_debug_fpr_access_busy ;

  // rule RL_rl_debug_csr_access_busy
  assign CAN_FIRE_RL_rl_debug_csr_access_busy =
	     f_csr_reqs$EMPTY_N && f_csr_rsps$FULL_N &&
	     rg_core_run_state == 2'd2 ;
  assign WILL_FIRE_RL_rl_debug_csr_access_busy =
	     CAN_FIRE_RL_rl_debug_csr_access_busy ;

  // rule RL_rl_debug_halt_req
  assign CAN_FIRE_RL_rl_debug_halt_req =
	     f_run_halt_reqs$EMPTY_N && !renameStage_rg_m_halt_req[4] &&
	     rg_core_run_state == 2'd2 &&
	     !f_run_halt_reqs$D_OUT ;
  assign WILL_FIRE_RL_rl_debug_halt_req =
	     CAN_FIRE_RL_rl_debug_halt_req && !EN_coreReq_start ;

  // rule RL_rl_debug_halt_req_already_halted
  assign CAN_FIRE_RL_rl_debug_halt_req_already_halted =
	     f_run_halt_reqs$EMPTY_N && f_run_halt_rsps$FULL_N &&
	     rg_core_run_state != 2'd2 &&
	     !f_run_halt_reqs$D_OUT ;
  assign WILL_FIRE_RL_rl_debug_halt_req_already_halted =
	     CAN_FIRE_RL_rl_debug_halt_req_already_halted ;

  // rule RL_rl_debug_halted
  assign CAN_FIRE_RL_rl_debug_halted =
	     f_run_halt_rsps$FULL_N && rg_core_run_state == 2'd0 ;
  assign WILL_FIRE_RL_rl_debug_halted =
	     CAN_FIRE_RL_rl_debug_halted &&
	     !WILL_FIRE_RL_rl_debug_halt_req_already_halted ;

  // rule RL_rl_debug_run_redundant
  assign CAN_FIRE_RL_rl_debug_run_redundant =
	     f_run_halt_reqs$EMPTY_N && f_run_halt_rsps$FULL_N &&
	     rg_core_run_state == 2'd2 &&
	     f_run_halt_reqs$D_OUT ;
  assign WILL_FIRE_RL_rl_debug_run_redundant =
	     CAN_FIRE_RL_rl_debug_run_redundant ;

  // rule RL_csrf_minstret_ehr_setRead
  assign CAN_FIRE_RL_csrf_minstret_ehr_setRead = 1'd1 ;
  assign WILL_FIRE_RL_csrf_minstret_ehr_setRead = 1'd1 ;

  // rule RL_csrf_mcycle_ehr_setRead
  assign CAN_FIRE_RL_csrf_mcycle_ehr_setRead = 1'd1 ;
  assign WILL_FIRE_RL_csrf_mcycle_ehr_setRead = 1'd1 ;

  // rule RL_rl_debug_csr_read
  assign CAN_FIRE_RL_rl_debug_csr_read =
	     f_csr_reqs$EMPTY_N && f_csr_rsps$FULL_N &&
	     rg_core_run_state == 2'd1 &&
	     !f_csr_reqs$D_OUT[76] ;
  assign WILL_FIRE_RL_rl_debug_csr_read = CAN_FIRE_RL_rl_debug_csr_read ;

  // rule RL_rl_debug_csr_write
  assign CAN_FIRE_RL_rl_debug_csr_write =
	     f_csr_reqs$EMPTY_N &&
	     f_csr_rsps_i_notFull__5799_AND_f_csr_reqs_firs_ETC___d15902 &&
	     rg_core_run_state == 2'd1 &&
	     f_csr_reqs$D_OUT[76] ;
  assign WILL_FIRE_RL_rl_debug_csr_write = CAN_FIRE_RL_rl_debug_csr_write ;

  // rule RL_mmio_handlePRq
  assign CAN_FIRE_RL_mmio_handlePRq =
	     !mmio_pRqQ_empty && !mmio_cRsQ_full &&
	     (!csrInstOrInterruptInflight_dummy2_0$Q_OUT ||
	      !csrInstOrInterruptInflight_dummy2_1$Q_OUT ||
	      !csrInstOrInterruptInflight_rl) ;
  assign WILL_FIRE_RL_mmio_handlePRq = CAN_FIRE_RL_mmio_handlePRq ;

  // rule RL_mmio_sendDataReq
  assign CAN_FIRE_RL_mmio_sendDataReq =
	     !mmio_dataReqQ_empty && !mmio_cRqQ_full ;
  assign WILL_FIRE_RL_mmio_sendDataReq = CAN_FIRE_RL_mmio_sendDataReq ;

  // rule RL_mmio_sendInstReq
  assign CAN_FIRE_RL_mmio_sendInstReq =
	     !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_deq &&
	     fetchStage$RDY_mmioIfc_instReq_first_fst &&
	     fetchStage$RDY_mmioIfc_instReq_first_snd ;
  assign WILL_FIRE_RL_mmio_sendInstReq =
	     CAN_FIRE_RL_mmio_sendInstReq && !WILL_FIRE_RL_mmio_sendDataReq ;

  // rule RL_mmio_sendDataResp
  assign CAN_FIRE_RL_mmio_sendDataResp =
	     !mmio_dataRespQ_full && !mmio_pRsQ_empty &&
	     mmio_pRsQ_data_0[66] ;
  assign WILL_FIRE_RL_mmio_sendDataResp = CAN_FIRE_RL_mmio_sendDataResp ;

  // rule RL_mmio_sendInstResp
  assign CAN_FIRE_RL_mmio_sendInstResp =
	     !mmio_pRsQ_empty && fetchStage$RDY_mmioIfc_instResp_enq &&
	     !mmio_pRsQ_data_0[66] ;
  assign WILL_FIRE_RL_mmio_sendInstResp = CAN_FIRE_RL_mmio_sendInstResp ;

  // rule RL_mmio_cRqQ_canonicalize
  assign CAN_FIRE_RL_mmio_cRqQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_mmio_cRqQ_canonicalize = 1'd1 ;

  // rule RL_mmio_cRqQ_enqReq_canon
  assign CAN_FIRE_RL_mmio_cRqQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_cRqQ_enqReq_canon = 1'd1 ;

  // rule RL_mmio_cRqQ_deqReq_canon
  assign CAN_FIRE_RL_mmio_cRqQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_cRqQ_deqReq_canon = 1'd1 ;

  // rule RL_mmio_cRqQ_clearReq_canon
  assign CAN_FIRE_RL_mmio_cRqQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_cRqQ_clearReq_canon = 1'd1 ;

  // rule RL_mmio_pRsQ_canonicalize
  assign CAN_FIRE_RL_mmio_pRsQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_mmio_pRsQ_canonicalize = 1'd1 ;

  // rule RL_mmio_pRsQ_enqReq_canon
  assign CAN_FIRE_RL_mmio_pRsQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_pRsQ_enqReq_canon = 1'd1 ;

  // rule RL_mmio_pRsQ_deqReq_canon
  assign CAN_FIRE_RL_mmio_pRsQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_pRsQ_deqReq_canon = 1'd1 ;

  // rule RL_mmio_pRsQ_clearReq_canon
  assign CAN_FIRE_RL_mmio_pRsQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_pRsQ_clearReq_canon = 1'd1 ;

  // rule RL_mmio_cRsQ_canonicalize
  assign CAN_FIRE_RL_mmio_cRsQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_mmio_cRsQ_canonicalize = 1'd1 ;

  // rule RL_mmio_cRsQ_enqReq_canon
  assign CAN_FIRE_RL_mmio_cRsQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_cRsQ_enqReq_canon = 1'd1 ;

  // rule RL_mmio_cRsQ_deqReq_canon
  assign CAN_FIRE_RL_mmio_cRsQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_cRsQ_deqReq_canon = 1'd1 ;

  // rule RL_mmio_cRsQ_clearReq_canon
  assign CAN_FIRE_RL_mmio_cRsQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_cRsQ_clearReq_canon = 1'd1 ;

  // rule RL_coreFix_doFetchTrainBP
  assign CAN_FIRE_RL_coreFix_doFetchTrainBP = coreFix_trainBPQ_1$EMPTY_N ;
  assign WILL_FIRE_RL_coreFix_doFetchTrainBP = coreFix_trainBPQ_1$EMPTY_N ;

  // rule RL_coreFix_doFetchTrainBP_1
  assign CAN_FIRE_RL_coreFix_doFetchTrainBP_1 = coreFix_trainBPQ_0$EMPTY_N ;
  assign WILL_FIRE_RL_coreFix_doFetchTrainBP_1 =
	     coreFix_trainBPQ_0$EMPTY_N && !coreFix_trainBPQ_1$EMPTY_N ;

  // rule RL_coreFix_memExe_doIssueSB
  assign CAN_FIRE_RL_coreFix_memExe_doIssueSB =
	     (!coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT ||
	      !coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT ||
	      !coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT ||
	      !coreFix_memExe_reqStQ_full_rl) &&
	     coreFix_memExe_stb$RDY_issue ;
  assign WILL_FIRE_RL_coreFix_memExe_doIssueSB =
	     CAN_FIRE_RL_coreFix_memExe_doIssueSB ;

  // rule RL_coreFix_memExe_doDeqLdQ_Lr_issue
  assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue =
	     NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1024 &&
	     coreFix_memExe_lsq$RDY_firstLd &&
	     !coreFix_memExe_lsq$firstLd[7] &&
	     !coreFix_memExe_lsq$firstLd[16] &&
	     coreFix_memExe_lsq$firstLd[101] &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
	     coreFix_memExe_stb$noMatchLdQ &&
	     (!coreFix_memExe_lsq$firstLd[90] || coreFix_memExe_stb$isEmpty) ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue =
	     CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;

  // rule RL_coreFix_memExe_doDeqLdQ_MMIO_issue
  assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue =
	     !mmio_dataReqQ_full && !mmio_dataPendQ_full &&
	     coreFix_memExe_lsq$RDY_firstLd &&
	     !coreFix_memExe_lsq$firstLd[7] &&
	     coreFix_memExe_lsq$firstLd[16] &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
	     (!coreFix_memExe_lsq$firstLd[90] || coreFix_memExe_stb$isEmpty) ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue =
	     CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ;

  // rule RL_coreFix_memExe_dMem_perfReqQ_canonicalize
  assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize = 1'd1 ;

  // rule RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp =
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$EMPTY_N &&
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP =
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N &&
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$EMPTY_N ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq =
	     !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full &&
	     coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry &&
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N &&
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[3] ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP =
	     !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full &&
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$EMPTY_N ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq =
	     !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full &&
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N &&
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$FULL_N &&
	     !coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[3] ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo =
	     !coreFix_memExe_respLrScAmoQ_full &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
	     coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2704 &&
	     !coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] ==
	     2'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon =
	     1'd1 ;

  // rule RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned =
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned ;

  // rule RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned =
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned ;

  // rule RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned =
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned ;

  // rule RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned =
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned ;

  // rule RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned =
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned ;

  // rule RL_renameStage_doRenaming_wrongPath
  assign CAN_FIRE_RL_renameStage_doRenaming_wrongPath =
	     fetchStage$RDY_pipelines_0_first &&
	     (!fetchStage$pipelines_0_canDeq ||
	      epochManager$checkEpoch_0_check ||
	      fetchStage$RDY_pipelines_0_deq) &&
	     NOT_fetchStage_pipelines_1_canDeq__2763_2764_O_ETC___d12772 &&
	     !epochManager$checkEpoch_0_check ;
  assign WILL_FIRE_RL_renameStage_doRenaming_wrongPath =
	     CAN_FIRE_RL_renameStage_doRenaming_wrongPath ;

  // rule RL_commitStage_doCommitTrap_flush
  assign CAN_FIRE_RL_commitStage_doCommitTrap_flush =
	     rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data &&
	     commitStage_f_rob_data$FULL_N &&
	     (rob$deqPort_0_deq_data[12] ||
	      epochManager$RDY_incrementEpoch) &&
	     !commitStage_rg_run_state &&
	     !commitStage_commitTrap[165] &&
	     rob$deqPort_0_deq_data[167] ;
  assign WILL_FIRE_RL_commitStage_doCommitTrap_flush =
	     CAN_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_renameStage_doRenaming &&
	     !WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	     !WILL_FIRE_RL_renameStage_doRenaming_Trap &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     !WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doExeMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_commitStage_rl_send_tv_reset
  assign CAN_FIRE_RL_commitStage_rl_send_tv_reset =
	     v_f_to_TV_0$FULL_N && commitStage_rg_just_after_reset ;
  assign WILL_FIRE_RL_commitStage_rl_send_tv_reset =
	     CAN_FIRE_RL_commitStage_rl_send_tv_reset ;

  // rule RL_commitStage_rl_send_mip_csr_change_to_tv
  assign CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv =
	     v_f_to_TV_0$FULL_N && !commitStage_rg_just_after_reset &&
	     !_0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14339 ;
  assign WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv =
	     CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv ;

  // rule RL_commitStage_doCommitTrap_handle
  assign CAN_FIRE_RL_commitStage_doCommitTrap_handle =
	     commitStage_f_rob_data$EMPTY_N &&
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14646 &&
	     (commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 ||
	      coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14671) &&
	     commitStage_commitTrap[165] &&
	     !commitStage_rg_run_state &&
	     _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14339 ;
  assign WILL_FIRE_RL_commitStage_doCommitTrap_handle =
	     CAN_FIRE_RL_commitStage_doCommitTrap_handle &&
	     !WILL_FIRE_RL_commitStage_rl_send_tv_reset &&
	     !WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	     !WILL_FIRE_RL_renameStage_doRenaming_Trap &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_prepareCachesAndTlbs ;

  // rule RL_commitStage_doCommitKilledLd
  assign CAN_FIRE_RL_commitStage_doCommitKilledLd =
	     epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq &&
	     rob$RDY_deqPort_0_deq_data &&
	     !commitStage_rg_run_state &&
	     !commitStage_commitTrap[165] &&
	     !rob$deqPort_0_deq_data[167] &&
	     rob$deqPort_0_deq_data[18] ;
  assign WILL_FIRE_RL_commitStage_doCommitKilledLd =
	     CAN_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_renameStage_doRenaming &&
	     !WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	     !WILL_FIRE_RL_renameStage_doRenaming_Trap &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     !WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doExeMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_commitStage_doCommitSystemInst
  assign CAN_FIRE_RL_commitStage_doCommitSystemInst =
	     coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty &&
	     regRenamingTable_RDY_commit_0_commit__4953_AND_ETC___d15013 &&
	     NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15031 ;
  assign WILL_FIRE_RL_commitStage_doCommitSystemInst =
	     CAN_FIRE_RL_commitStage_doCommitSystemInst &&
	     !WILL_FIRE_RL_commitStage_rl_send_tv_reset &&
	     !WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	     !WILL_FIRE_RL_renameStage_doRenaming_Trap &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_rl_debug_csr_write &&
	     !WILL_FIRE_RL_prepareCachesAndTlbs ;

  // rule RL_csrf_incCycle
  assign CAN_FIRE_RL_csrf_incCycle = 1'd1 ;
  assign WILL_FIRE_RL_csrf_incCycle = 1'd1 ;

  // rule RL_csrf_mcycle_ehr_data_canon
  assign CAN_FIRE_RL_csrf_mcycle_ehr_data_canon = 1'd1 ;
  assign WILL_FIRE_RL_csrf_mcycle_ehr_data_canon = 1'd1 ;

  // rule RL_commitStage_notifyLSQCommit
  assign CAN_FIRE_RL_commitStage_notifyLSQCommit =
	     rob$RDY_setLSQAtCommitNotified && rob$RDY_deqPort_0_deq_data &&
	     !commitStage_commitTrap[165] &&
	     !rob$deqPort_0_deq_data[167] &&
	     !rob$deqPort_0_deq_data[18] &&
	     !rob$deqPort_0_deq_data[25] &&
	     rob$deqPort_0_deq_data[15] &&
	     !rob$deqPort_0_deq_data[14] ;
  assign WILL_FIRE_RL_commitStage_notifyLSQCommit =
	     CAN_FIRE_RL_commitStage_notifyLSQCommit ;

  // rule RL_commitStage_doCommitNormalInst
  assign CAN_FIRE_RL_commitStage_doCommitNormalInst =
	     rob$RDY_deqPort_0_deq_data &&
	     NOT_rob_deqPort_0_canDeq__5346_5347_OR_regRena_ETC___d15388 &&
	     NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15400 ;
  assign WILL_FIRE_RL_commitStage_doCommitNormalInst =
	     CAN_FIRE_RL_commitStage_doCommitNormalInst &&
	     !WILL_FIRE_RL_commitStage_rl_send_tv_reset ;

  // rule RL_csrf_minstret_ehr_data_canon
  assign CAN_FIRE_RL_csrf_minstret_ehr_data_canon = 1'd1 ;
  assign WILL_FIRE_RL_csrf_minstret_ehr_data_canon = 1'd1 ;

  // rule RL_coreFix_aluExe_1_doFinishAlu_T
  assign CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T =
	     coreFix_aluExe_1_exeToFinQ$first[17] &&
	     coreFix_aluExe_1_exeToFinQ$RDY_deq &&
	     coreFix_aluExe_1_exeToFinQ$RDY_first &&
	     rob$RDY_setExecuted_doFinishAlu_1_set &&
	     epochManager$RDY_incrementEpoch &&
	     coreFix_trainBPQ_1$FULL_N ;
  assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T =
	     CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     !WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doExeMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault &&
	     !WILL_FIRE_RL_rl_debug_resume ;

  // rule RL_coreFix_aluExe_0_doFinishAlu_T
  assign CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T =
	     coreFix_aluExe_0_exeToFinQ$first[17] &&
	     coreFix_aluExe_0_exeToFinQ$RDY_deq &&
	     coreFix_aluExe_0_exeToFinQ$RDY_first &&
	     rob$RDY_setExecuted_doFinishAlu_0_set &&
	     epochManager$RDY_incrementEpoch &&
	     coreFix_trainBPQ_0$FULL_N ;
  assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T =
	     CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     !WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doExeMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault &&
	     !WILL_FIRE_RL_rl_debug_resume ;

  // rule RL_coreFix_aluExe_0_doFinishAlu_F
  assign CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F =
	     !coreFix_aluExe_0_exeToFinQ$first[17] &&
	     coreFix_aluExe_0_exeToFinQ$RDY_deq &&
	     coreFix_aluExe_0_exeToFinQ_RDY_first__2641_AND_ETC___d12680 ;
  assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F =
	     CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;

  // rule RL_coreFix_aluExe_1_doFinishAlu_F
  assign CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F =
	     !coreFix_aluExe_1_exeToFinQ$first[17] &&
	     coreFix_aluExe_1_exeToFinQ$RDY_deq &&
	     coreFix_aluExe_1_exeToFinQ_RDY_first__1967_AND_ETC___d12007 ;
  assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F =
	     CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;

  // rule RL_coreFix_aluExe_1_doExeAlu
  assign CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu =
	     coreFix_aluExe_1_regToExeQ$RDY_deq &&
	     coreFix_aluExe_1_exeToFinQ$RDY_enq &&
	     coreFix_aluExe_1_regToExeQ$RDY_first ;
  assign WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu =
	     CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_aluExe_0_doExeAlu
  assign CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu =
	     coreFix_aluExe_0_regToExeQ$RDY_deq &&
	     coreFix_aluExe_0_exeToFinQ$RDY_enq &&
	     coreFix_aluExe_0_regToExeQ$RDY_first ;
  assign WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu =
	     CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_aluExe_1_doRegReadAlu
  assign CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu =
	     coreFix_aluExe_1_dispToRegQ$RDY_deq &&
	     coreFix_aluExe_1_regToExeQ$RDY_enq &&
	     coreFix_aluExe_1_dispToRegQ$RDY_first &&
	     coreFix_aluExe_1_dispToRegQ_first__1322_BIT_13_ETC___d11407 ;
  assign WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu =
	     CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_aluExe_0_doRegReadAlu
  assign CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu =
	     coreFix_aluExe_0_dispToRegQ$RDY_deq &&
	     coreFix_aluExe_0_regToExeQ$RDY_enq &&
	     coreFix_aluExe_0_dispToRegQ$RDY_first &&
	     coreFix_aluExe_0_dispToRegQ_first__2182_BIT_13_ETC___d12267 ;
  assign WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu =
	     CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_aluExe_0_doDispatchAlu
  assign CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu =
	     coreFix_aluExe_0_dispToRegQ$RDY_enq &&
	     coreFix_aluExe_0_rsAlu$RDY_dispatchData &&
	     coreFix_aluExe_0_rsAlu$RDY_doDispatch ;
  assign WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu =
	     CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_aluExe_1_doDispatchAlu
  assign CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu =
	     coreFix_aluExe_1_dispToRegQ$RDY_enq &&
	     coreFix_aluExe_1_rsAlu$RDY_dispatchData &&
	     coreFix_aluExe_1_rsAlu$RDY_doDispatch ;
  assign WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu =
	     CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_memExe_doDeqLdQ_Lr_deq
  assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq =
	     !coreFix_memExe_respLrScAmoQ_empty &&
	     rob$RDY_setExecuted_deqLSQ &&
	     coreFix_memExe_lsq$RDY_firstLd &&
	     coreFix_memExe_lsq$RDY_deqLd &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq =
	     CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_coreFix_memExe_doDeqLdQ_MMIO_deq
  assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq =
	     !mmio_dataRespQ_empty &&
	     NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[0] &&
	     mmio_dataRespQ_data_0[64] ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq =
	     CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_coreFix_fpuMulDivExe_0_doFinishFpSimple
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple =
	     coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_first &&
	     rob$RDY_setExecuted_doFinishFpuMulDiv_0_set ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;

  // rule RL_coreFix_fpuMulDivExe_0_doFinishFpFma
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma =
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3880 ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;

  // rule RL_coreFix_fpuMulDivExe_0_doFinishFpDiv
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv =
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5272 ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;

  // rule RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt =
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6664 ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;

  // rule RL_coreFix_fpuMulDivExe_0_doFinishIntMul
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul =
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8056 ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;

  // rule RL_coreFix_fpuMulDivExe_0_doFinishIntDiv
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv =
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d8103 ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;

  // rule RL_coreFix_memExe_doDeqLdQ_fault
  assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault =
	     rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd &&
	     coreFix_memExe_lsq$RDY_deqLd &&
	     coreFix_memExe_lsq$firstLd[7] ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault =
	     CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_coreFix_memExe_doDeqLdQ_Ld_Mem
  assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem =
	     rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd &&
	     coreFix_memExe_lsq$RDY_deqLd &&
	     !coreFix_memExe_lsq$firstLd[7] &&
	     !coreFix_memExe_lsq$firstLd[101] &&
	     !coreFix_memExe_lsq$firstLd[16] ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem =
	     CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ;

  // rule RL_coreFix_memExe_doDeqLdQ_MMIO_fault
  assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault =
	     !mmio_dataRespQ_empty &&
	     NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[0] &&
	     !mmio_dataRespQ_data_0[64] ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault =
	     CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_coreFix_memExe_doFinishMem
  assign CAN_FIRE_RL_coreFix_memExe_doFinishMem =
	     rob$RDY_setExecuted_doFinishMem &&
	     coreFix_memExe_dTlb$RDY_procResp &&
	     coreFix_memExe_dTlb$RDY_deqProcResp ;
  assign WILL_FIRE_RL_coreFix_memExe_doFinishMem =
	     CAN_FIRE_RL_coreFix_memExe_doFinishMem ;

  // rule RL_coreFix_memExe_doDeqStQ_ScAmo_issue
  assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue =
	     NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1024 &&
	     coreFix_memExe_lsq$RDY_firstSt &&
	     !coreFix_memExe_lsq$firstSt[4] &&
	     !coreFix_memExe_lsq$firstSt[77] &&
	     (coreFix_memExe_lsq$firstSt[158:157] == 2'd1 ||
	      coreFix_memExe_lsq$firstSt[158:157] == 2'd2) &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
	     coreFix_memExe_stb$noMatchStQ &&
	     (!coreFix_memExe_lsq$firstSt[151] ||
	      coreFix_memExe_stb$isEmpty) ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue =
	     CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;

  // rule RL_coreFix_memExe_doDeqStQ_MMIO_issue
  assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue =
	     !mmio_dataReqQ_full && !mmio_dataPendQ_full &&
	     coreFix_memExe_lsq$RDY_firstSt &&
	     !coreFix_memExe_lsq$firstSt[4] &&
	     coreFix_memExe_lsq$firstSt[158:157] != 2'd3 &&
	     coreFix_memExe_lsq$firstSt[77] &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
	     (!coreFix_memExe_lsq$firstSt[151] ||
	      coreFix_memExe_stb$isEmpty) ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue =
	     CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;

  // rule RL_mmio_dataReqQ_canonicalize
  assign CAN_FIRE_RL_mmio_dataReqQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataReqQ_canonicalize = 1'd1 ;

  // rule RL_mmio_dataReqQ_enqReq_canon
  assign CAN_FIRE_RL_mmio_dataReqQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataReqQ_enqReq_canon = 1'd1 ;

  // rule RL_mmio_dataReqQ_deqReq_canon
  assign CAN_FIRE_RL_mmio_dataReqQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataReqQ_deqReq_canon = 1'd1 ;

  // rule RL_mmio_dataReqQ_clearReq_canon
  assign CAN_FIRE_RL_mmio_dataReqQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataReqQ_clearReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_sendLrScAmoToMem
  assign CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 &&
	     (!coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT ||
	      !coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT ||
	      coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ||
	      !coreFix_memExe_reqLrScAmoQ_empty_rl) ;
  assign WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem =
	     CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;

  // rule RL_coreFix_memExe_doIssueLdFromIssueQ
  assign CAN_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ =
	     coreFix_memExe_lsq$RDY_getIssueLd &&
	     !coreFix_memExe_forwardQ_full &&
	     NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1474 ;
  assign WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ =
	     CAN_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;

  // rule RL_coreFix_memExe_doIssueLdFromUpdate
  assign CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate =
	     !coreFix_memExe_forwardQ_full &&
	     NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1474 &&
	     coreFix_memExe_issueLd$whas ;
  assign WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate =
	     CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;

  // rule RL_coreFix_memExe_doDeqStQ_fault
  assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault =
	     rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt &&
	     coreFix_memExe_lsq$RDY_deqSt &&
	     coreFix_memExe_lsq$firstSt[4] ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault =
	     CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_coreFix_memExe_doDeqStQ_Fence
  assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence =
	     rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt &&
	     coreFix_memExe_lsq$RDY_deqSt &&
	     !coreFix_memExe_lsq$firstSt[4] &&
	     coreFix_memExe_lsq$firstSt[158:157] == 2'd3 &&
	     (!coreFix_memExe_lsq$firstSt[151] ||
	      coreFix_memExe_stb$isEmpty) ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence =
	     CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_coreFix_memExe_doDeqStQ_ScAmo_deq
  assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq =
	     !coreFix_memExe_respLrScAmoQ_empty &&
	     rob$RDY_setExecuted_deqLSQ &&
	     coreFix_memExe_lsq$RDY_firstSt &&
	     coreFix_memExe_lsq$RDY_deqSt &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd2 ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq =
	     CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     !WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_coreFix_memExe_doDeqStQ_MMIO_deq
  assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq =
	     !mmio_dataRespQ_empty &&
	     NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
	     !coreFix_memExe_waitLrScAmoMMIOResp[0] &&
	     mmio_dataRespQ_data_0[64] ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq =
	     CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     !WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_coreFix_memExe_doDeqStQ_MMIO_fault
  assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault =
	     !mmio_dataRespQ_empty &&
	     NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
	     !coreFix_memExe_waitLrScAmoMMIOResp[0] &&
	     !mmio_dataRespQ_data_0[64] ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault =
	     CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_mmio_dataRespQ_canonicalize
  assign CAN_FIRE_RL_mmio_dataRespQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataRespQ_canonicalize = 1'd1 ;

  // rule RL_mmio_dataRespQ_enqReq_canon
  assign CAN_FIRE_RL_mmio_dataRespQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataRespQ_enqReq_canon = 1'd1 ;

  // rule RL_mmio_dataRespQ_deqReq_canon
  assign CAN_FIRE_RL_mmio_dataRespQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataRespQ_deqReq_canon = 1'd1 ;

  // rule RL_mmio_dataRespQ_clearReq_canon
  assign CAN_FIRE_RL_mmio_dataRespQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataRespQ_clearReq_canon = 1'd1 ;

  // rule RL_mmio_dataPendQ_canonicalize
  assign CAN_FIRE_RL_mmio_dataPendQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataPendQ_canonicalize = 1'd1 ;

  // rule RL_mmio_dataPendQ_enqReq_canon
  assign CAN_FIRE_RL_mmio_dataPendQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataPendQ_enqReq_canon = 1'd1 ;

  // rule RL_mmio_dataPendQ_deqReq_canon
  assign CAN_FIRE_RL_mmio_dataPendQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataPendQ_deqReq_canon = 1'd1 ;

  // rule RL_mmio_dataPendQ_clearReq_canon
  assign CAN_FIRE_RL_mmio_dataPendQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataPendQ_clearReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_sendLdToMem
  assign CAN_FIRE_RL_coreFix_memExe_sendLdToMem =
	     (!coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT ||
	      !coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT ||
	      coreFix_memExe_reqLdQ_empty_lat_0$whas ||
	      !coreFix_memExe_reqLdQ_empty_rl) &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 ;
  assign WILL_FIRE_RL_coreFix_memExe_sendLdToMem =
	     CAN_FIRE_RL_coreFix_memExe_sendLdToMem &&
	     !WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;

  // rule RL_coreFix_memExe_sendStToMem
  assign CAN_FIRE_RL_coreFix_memExe_sendStToMem =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 &&
	     (!coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT ||
	      !coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT ||
	      CAN_FIRE_RL_coreFix_memExe_doIssueSB ||
	      !coreFix_memExe_reqStQ_empty_rl) ;
  assign WILL_FIRE_RL_coreFix_memExe_sendStToMem =
	     CAN_FIRE_RL_coreFix_memExe_sendStToMem &&
	     !WILL_FIRE_RL_coreFix_memExe_sendLdToMem &&
	     !WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2108 &&
	     !coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] ==
	     2'd0 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2677 &&
	     !coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] !=
	     2'd0 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] !=
	     2'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;

  // rule RL_coreFix_memExe_doDeqStQ_St_Mem
  assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem =
	     coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_firstSt &&
	     coreFix_memExe_lsq$RDY_deqSt &&
	     !coreFix_memExe_lsq$firstSt[4] &&
	     coreFix_memExe_lsq$firstSt[158:157] == 2'd0 &&
	     !coreFix_memExe_lsq$firstSt[77] &&
	     coreFix_memExe_stb$getEnqIndex[2] ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem =
	     CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_memExe_doRespLdMem
  assign CAN_FIRE_RL_coreFix_memExe_doRespLdMem =
	     !coreFix_memExe_memRespLdQ_empty ;
  assign WILL_FIRE_RL_coreFix_memExe_doRespLdMem =
	     CAN_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;

  // rule RL_coreFix_memExe_doRespLdForward
  assign CAN_FIRE_RL_coreFix_memExe_doRespLdForward =
	     !coreFix_memExe_forwardQ_empty ;
  assign WILL_FIRE_RL_coreFix_memExe_doRespLdForward =
	     CAN_FIRE_RL_coreFix_memExe_doRespLdForward &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;

  // rule RL_rl_debug_gpr_write
  assign CAN_FIRE_RL_rl_debug_gpr_write =
	     regRenamingTable$RDY_rename_0_getRename && f_gpr_reqs$EMPTY_N &&
	     f_gpr_rsps$FULL_N &&
	     rg_core_run_state == 2'd1 &&
	     f_gpr_reqs$D_OUT[69] ;
  assign WILL_FIRE_RL_rl_debug_gpr_write = CAN_FIRE_RL_rl_debug_gpr_write ;

  // rule RL_rl_debug_fpr_write
  assign CAN_FIRE_RL_rl_debug_fpr_write =
	     regRenamingTable$RDY_rename_0_getRename && f_fpr_reqs$EMPTY_N &&
	     f_fpr_rsps$FULL_N &&
	     rg_core_run_state == 2'd1 &&
	     !f_gpr_reqs$EMPTY_N &&
	     f_fpr_reqs$D_OUT[69] ;
  assign WILL_FIRE_RL_rl_debug_fpr_write = CAN_FIRE_RL_rl_debug_fpr_write ;

  // rule RL_coreFix_memExe_doExeMem
  assign CAN_FIRE_RL_coreFix_memExe_doExeMem =
	     coreFix_memExe_regToExeQ$RDY_deq &&
	     coreFix_memExe_regToExeQ$RDY_first &&
	     coreFix_memExe_dTlb$RDY_procReq ;
  assign WILL_FIRE_RL_coreFix_memExe_doExeMem =
	     CAN_FIRE_RL_coreFix_memExe_doExeMem ;

  // rule RL_prepareCachesAndTlbs
  assign CAN_FIRE_RL_prepareCachesAndTlbs =
	     (!flush_tlbs ||
	      fetchStage$RDY_iTlbIfc_flush &&
	      coreFix_memExe_dTlb$RDY_flush) &&
	     (flush_reservation || flush_tlbs || update_vm_info) ;
  assign WILL_FIRE_RL_prepareCachesAndTlbs =
	     CAN_FIRE_RL_prepareCachesAndTlbs ;

  // rule RL_rl_debug_resume
  assign CAN_FIRE_RL_rl_debug_resume =
	     commitStage_rg_run_state && fetchStage$RDY_iTlbIfc_flush &&
	     coreFix_memExe_dTlb$RDY_flush &&
	     f_run_halt_reqs$EMPTY_N &&
	     f_run_halt_rsps$FULL_N &&
	     rg_core_run_state == 2'd1 &&
	     f_run_halt_reqs$D_OUT &&
	     !f_gpr_reqs$EMPTY_N &&
	     !f_fpr_reqs$EMPTY_N &&
	     !f_csr_reqs$EMPTY_N ;
  assign WILL_FIRE_RL_rl_debug_resume =
	     CAN_FIRE_RL_rl_debug_resume &&
	     !WILL_FIRE_RL_prepareCachesAndTlbs ;

  // rule RL_coreFix_memExe_doRegReadMem
  assign CAN_FIRE_RL_coreFix_memExe_doRegReadMem =
	     coreFix_memExe_dispToRegQ$RDY_deq &&
	     coreFix_memExe_regToExeQ$RDY_enq &&
	     coreFix_memExe_dispToRegQ$RDY_first &&
	     sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1632 ;
  assign WILL_FIRE_RL_coreFix_memExe_doRegReadMem =
	     CAN_FIRE_RL_coreFix_memExe_doRegReadMem &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_memExe_doDispatchMem
  assign CAN_FIRE_RL_coreFix_memExe_doDispatchMem =
	     coreFix_memExe_dispToRegQ$RDY_enq &&
	     coreFix_memExe_rsMem$RDY_dispatchData &&
	     coreFix_memExe_rsMem$RDY_doDispatch ;
  assign WILL_FIRE_RL_coreFix_memExe_doDispatchMem =
	     CAN_FIRE_RL_coreFix_memExe_doDispatchMem &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer =
	     !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send &&
	     coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit &&
	     CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q274 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry =
	     !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new =
	     (!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT ||
	      !coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT ||
	      coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ||
	      !coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl) &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_cRqTransfer_getEmptyEntryInit &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer =
	     !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send &&
	     CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q275 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_respLrScAmoQ_canonicalize
  assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ;

  // rule RL_coreFix_memExe_respLrScAmoQ_clearReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_respLrScAmoQ_deqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_respLrScAmoQ_enqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_memRespLdQ_canonicalize
  assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ;

  // rule RL_coreFix_memExe_memRespLdQ_clearReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_memRespLdQ_deqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_memRespLdQ_enqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_forwardQ_canonicalize
  assign CAN_FIRE_RL_coreFix_memExe_forwardQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_forwardQ_canonicalize = 1'd1 ;

  // rule RL_coreFix_memExe_forwardQ_clearReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_forwardQ_deqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_forwardQ_enqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_reqStQ_full_canon
  assign CAN_FIRE_RL_coreFix_memExe_reqStQ_full_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_reqStQ_full_canon = 1'd1 ;

  // rule RL_coreFix_memExe_reqStQ_empty_canon
  assign CAN_FIRE_RL_coreFix_memExe_reqStQ_empty_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_reqStQ_empty_canon = 1'd1 ;

  // rule RL_coreFix_memExe_reqStQ_data_0_canon
  assign CAN_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon = 1'd1 ;

  // rule RL_coreFix_memExe_reqLrScAmoQ_full_canon
  assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon = 1'd1 ;

  // rule RL_coreFix_memExe_reqLrScAmoQ_empty_canon
  assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ;

  // rule RL_coreFix_memExe_reqLrScAmoQ_data_0_canon
  assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ;

  // rule RL_coreFix_memExe_reqLdQ_full_canon
  assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_full_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_full_canon = 1'd1 ;

  // rule RL_coreFix_memExe_reqLdQ_empty_canon
  assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ;

  // rule RL_coreFix_memExe_reqLdQ_data_0_canon
  assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon = 1'd1 ;

  // rule RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv =
	     coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_regToExeQ$RDY_first &&
	     IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8430 ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv =
	     coreFix_fpuMulDivExe_0_dispToRegQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_regToExeQ$RDY_enq &&
	     coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
	     sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8295 ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv =
	     coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq &&
	     coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData &&
	     coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit =
	     !coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit ;

  // rule RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon = 1'd1 ;

  // rule RL_renameStage_doRenaming_Trap
  assign CAN_FIRE_RL_renameStage_doRenaming_Trap =
	     fetchStage$RDY_pipelines_0_deq &&
	     fetchStage$RDY_pipelines_0_first &&
	     epochManager$RDY_incrementEpoch &&
	     rob$RDY_enqPort_0_enq &&
	     mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13055 &&
	     rob$isEmpty &&
	     rg_core_run_state == 2'd2 ;
  assign WILL_FIRE_RL_renameStage_doRenaming_Trap =
	     CAN_FIRE_RL_renameStage_doRenaming_Trap &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_rl_debug_halt_req &&
	     !EN_coreReq_start ;

  // rule RL_renameStage_doRenaming_SystemInst
  assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst =
	     fetchStage$RDY_pipelines_0_deq &&
	     fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309 &&
	     mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13365 &&
	     rg_core_run_state == 2'd2 ;
  assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst =
	     CAN_FIRE_RL_renameStage_doRenaming_SystemInst &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_rl_debug_halt_req &&
	     !EN_coreReq_start ;

  // rule RL_csrInstOrInterruptInflight_canon
  assign CAN_FIRE_RL_csrInstOrInterruptInflight_canon = 1'd1 ;
  assign WILL_FIRE_RL_csrInstOrInterruptInflight_canon = 1'd1 ;

  // rule RL_commitStage_doSetLSQAtCommit
  assign CAN_FIRE_RL_commitStage_doSetLSQAtCommit =
	     MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 ||
	     WILL_FIRE_RL_commitStage_notifyLSQCommit ;
  assign WILL_FIRE_RL_commitStage_doSetLSQAtCommit =
	     CAN_FIRE_RL_commitStage_doSetLSQAtCommit ;

  // rule RL_commitStage_doSetLSQAtCommit_1
  assign CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 =
	     WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	     rob$deqPort_1_canDeq &&
	     rob$deqPort_1_deq_data[25] &&
	     !rob$deqPort_1_deq_data[18] &&
	     !rob$deqPort_1_deq_data[167] &&
	     rob$deqPort_1_deq_data[329:325] != 5'd0 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd21 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd17 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd18 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd13 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd16 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd15 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd19 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd20 &&
	     rob$deqPort_1_deq_data[13] ;
  assign WILL_FIRE_RL_commitStage_doSetLSQAtCommit_1 =
	     CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 ;

  // rule RL_renameStage_doRenaming
  assign CAN_FIRE_RL_renameStage_doRenaming =
	     (!fetchStage$pipelines_0_canDeq ||
	      IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13450) &&
	     IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13923 &&
	     IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13931 &&
	     NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14105 &&
	     mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14109 ;
  assign WILL_FIRE_RL_renameStage_doRenaming =
	     CAN_FIRE_RL_renameStage_doRenaming &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_rl_debug_halt_req &&
	     !EN_coreReq_start ;

  // rule RL_mmio_pRqQ_canonicalize
  assign CAN_FIRE_RL_mmio_pRqQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_mmio_pRqQ_canonicalize = 1'd1 ;

  // rule RL_mmio_pRqQ_enqReq_canon
  assign CAN_FIRE_RL_mmio_pRqQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_pRqQ_enqReq_canon = 1'd1 ;

  // rule RL_mmio_pRqQ_deqReq_canon
  assign CAN_FIRE_RL_mmio_pRqQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_pRqQ_deqReq_canon = 1'd1 ;

  // rule RL_mmio_pRqQ_clearReq_canon
  assign CAN_FIRE_RL_mmio_pRqQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_pRqQ_clearReq_canon = 1'd1 ;

  // rule RL_coreFix_globalSpecUpdate_canon_correct_spec
  assign CAN_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec = 1'd1 ;

  // inputs to muxes for submodule ports
  assign MUX_regRenamingTable$rename_0_getRename_1__SEL_1 =
	     WILL_FIRE_RL_renameStage_doRenaming ||
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
  assign MUX_regRenamingTable$rename_0_getRename_1__SEL_2 =
	     WILL_FIRE_RL_rl_debug_gpr_write ||
	     WILL_FIRE_RL_rl_debug_gpr_read ;
  assign MUX_regRenamingTable$rename_0_getRename_1__SEL_3 =
	     WILL_FIRE_RL_rl_debug_fpr_write ||
	     WILL_FIRE_RL_rl_debug_fpr_read ;
  assign MUX_commitStage_rg_run_state$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 ;
  assign MUX_commitStage_rg_serial_num$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 ;
  assign MUX_commitStage_rg_serial_num$write_1__SEL_2 =
	     WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst ;
  assign MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	     rob$deqPort_0_canDeq &&
	     rob$deqPort_0_deq_data[13] ;
  assign MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3 =
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 =
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	     fetchStage$pipelines_0_first[194:192] == 3'd0 ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
	     coreFix_memExe_lsq$firstSt[150] ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 =
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
	     coreFix_memExe_lsq$firstLd[89] ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2622 ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 &&
	     coreFix_memExe_lsq$getHit[8] &&
	     !coreFix_memExe_lsq$getHit[9] ;
  assign MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
	     coreFix_memExe_lsq$firstSt[150] ;
  assign MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
	     coreFix_memExe_lsq$firstLd[89] ;
  assign MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
	     coreFix_memExe_lsq$firstSt[150] ;
  assign MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
	     coreFix_memExe_lsq$firstLd[89] ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2599 ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	     3'd4 ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2531 ||
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2535) ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2582 ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd2 ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd3) ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2727 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] ==
	     2'd0 ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	      (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	       3'd4 ||
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027 ||
	       !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017) ||
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2123) ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
	      (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
	       !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd4 ||
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2638) ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd4 ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2697 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2700 ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2666 ;
  assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 =
	     WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ;
  assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ;
  assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2 =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ;
  assign MUX_coreFix_memExe_lsq$getHit_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
	      (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
	       !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd0 ||
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2605) ;
  assign MUX_coreFix_memExe_lsq$getHit_1__SEL_2 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 ;
  assign MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
	      (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
	       !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd1 ||
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2630) ;
  assign MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
	     coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
  assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2565 ;
  assign MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
	     coreFix_memExe_lsq$firstSt[150] ;
  assign MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
	     coreFix_memExe_lsq$firstLd[89] ;
  assign MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
  assign MUX_coreFix_trainBPQ_0$enq_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
	     (coreFix_aluExe_0_exeToFinQ$first[326:322] == 5'd9 ||
	      coreFix_aluExe_0_exeToFinQ$first[326:322] == 5'd10) ;
  assign MUX_coreFix_trainBPQ_1$enq_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
	     (coreFix_aluExe_1_exeToFinQ$first[326:322] == 5'd9 ||
	      coreFix_aluExe_1_exeToFinQ$first[326:322] == 5'd10) ;
  assign MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 ;
  assign MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     (commitStage_commitTrap[36] ||
	      commitStage_commitTrap[35:32] == 4'd3) ;
  assign MUX_csrf_external_int_en_vec_1$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd9 ||
	      IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd22) ;
  assign MUX_csrf_external_int_en_vec_3$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd772 ;
  assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd16 ||
	      IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd29) ;
  assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_2 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     (f_csr_reqs$D_OUT[75:64] == 12'd324 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd836) ;
  assign MUX_csrf_fflags_reg$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	     NOT_IF_NOT_rob_deqPort_0_canDeq__5346_5347_OR__ETC___d15689 ;
  assign MUX_csrf_fflags_reg$write_1__SEL_2 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd0 ||
	      IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd2) ;
  assign MUX_csrf_fflags_reg$write_1__SEL_3 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     (f_csr_reqs$D_OUT[75:64] == 12'd1 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd3) ;
  assign MUX_csrf_frm_reg$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd1 ||
	      IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd2) ;
  assign MUX_csrf_fs_reg$write_1__SEL_2 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd0 ||
	      IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd1 ||
	      IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd2 ||
	      IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd8 ||
	      IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd18) ;
  assign MUX_csrf_fs_reg$write_1__SEL_3 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     (f_csr_reqs$D_OUT[75:64] == 12'd1 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd2 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd3 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd256 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd768) ;
  assign MUX_csrf_ie_vec_0$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd8 ||
	      IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd18) ;
  assign MUX_csrf_ie_vec_0$write_1__SEL_2 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     (f_csr_reqs$D_OUT[75:64] == 12'd256 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd768) ;
  assign MUX_csrf_ie_vec_1$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ;
  assign MUX_csrf_ie_vec_1$write_1__SEL_2 =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 &&
	     csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 ;
  assign MUX_csrf_ie_vec_3$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ;
  assign MUX_csrf_ie_vec_3$write_1__SEL_2 =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 &&
	     NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 ;
  assign MUX_csrf_ie_vec_3$write_1__SEL_3 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd768 ;
  assign MUX_csrf_mcause_code_reg$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd27 ;
  assign MUX_csrf_mcause_code_reg$write_1__SEL_3 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd834 ;
  assign MUX_csrf_mcounteren_cy_reg$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd774 ;
  assign MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd2816 ;
  assign MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_2 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd30 ;
  assign MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd770 ;
  assign MUX_csrf_mepc_csr$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd26 ;
  assign MUX_csrf_mepc_csr$write_1__SEL_3 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd833 ;
  assign MUX_csrf_mideleg_11_reg$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd771 ;
  assign MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd2818 ;
  assign MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_2 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd31 ;
  assign MUX_csrf_mpp_reg$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ;
  assign MUX_csrf_mscratch_csr$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd832 ;
  assign MUX_csrf_mtval_csr$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd28 ;
  assign MUX_csrf_mtval_csr$write_1__SEL_3 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd835 ;
  assign MUX_csrf_mtvec_base_hi_reg$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd773 ;
  assign MUX_csrf_ppn_reg$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd384 ;
  assign MUX_csrf_prev_ie_vec_1$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ;
  assign MUX_csrf_prev_ie_vec_3$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ;
  assign MUX_csrf_prv_reg$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ;
  assign MUX_csrf_prv_reg$write_1__SEL_3 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd1968 ;
  assign MUX_csrf_rg_dcsr$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd40 ;
  assign MUX_csrf_rg_dpc$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd41 ;
  assign MUX_csrf_rg_dpc$write_1__SEL_3 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd1969 ;
  assign MUX_csrf_rg_dscratch0$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd1970 ;
  assign MUX_csrf_rg_dscratch1$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd1971 ;
  assign MUX_csrf_rg_tdata1_data$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd1953 ;
  assign MUX_csrf_rg_tdata2$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd1954 ;
  assign MUX_csrf_rg_tdata3$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd1955 ;
  assign MUX_csrf_rg_tselect$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd1952 ;
  assign MUX_csrf_scause_code_reg$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd14 ;
  assign MUX_csrf_scause_code_reg$write_1__SEL_3 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd322 ;
  assign MUX_csrf_scounteren_cy_reg$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd262 ;
  assign MUX_csrf_sepc_csr$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd13 ;
  assign MUX_csrf_sepc_csr$write_1__SEL_3 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd321 ;
  assign MUX_csrf_spp_reg$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ;
  assign MUX_csrf_sscratch_csr$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd320 ;
  assign MUX_csrf_stats_module_writeQ$enq_1__SEL_1 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd2049 ;
  assign MUX_csrf_stval_csr$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd15 ;
  assign MUX_csrf_stval_csr$write_1__SEL_3 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd323 ;
  assign MUX_csrf_stvec_base_hi_reg$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd261 ;
  assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 =
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     fetchStage$pipelines_0_canDeq &&
	     NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 &&
	     IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 ;
  assign MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 =
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 &&
	     NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14220 &&
	     IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 ;
  assign MUX_f_run_halt_rsps$enq_1__SEL_1 =
	     WILL_FIRE_RL_rl_debug_halted ||
	     WILL_FIRE_RL_rl_debug_halt_req_already_halted ;
  assign MUX_flush_reservation$write_1__SEL_1 =
	     WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ;
  assign MUX_flush_tlbs$write_1__SEL_1 =
	     WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ;
  assign MUX_renameStage_rg_m_halt_req$write_1__SEL_1 =
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 &&
	     csrf_rg_dcsr[2] ;
  assign MUX_renameStage_rg_m_halt_req$write_1__SEL_2 =
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	     csrf_rg_dcsr[2] ;
  assign MUX_renameStage_rg_m_halt_req$write_1__SEL_3 =
	     WILL_FIRE_RL_renameStage_doRenaming_Trap && csrf_rg_dcsr[2] ;
  assign MUX_renameStage_rg_m_halt_req$write_1__SEL_6 =
	     EN_coreReq_start && !coreReq_start_running ;
  assign MUX_rf$write_3_wr_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
	     coreFix_memExe_lsq$firstSt[150] ;
  assign MUX_rf$write_3_wr_1__SEL_2 =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
	     coreFix_memExe_lsq$firstSt[150] ;
  assign MUX_rf$write_3_wr_1__SEL_3 =
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	     coreFix_memExe_lsq$firstLd[89] ;
  assign MUX_rf$write_3_wr_1__SEL_4 =
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     coreFix_memExe_lsq$firstLd[89] ;
  assign MUX_rf$write_3_wr_1__PSEL_5 =
	     WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
	     WILL_FIRE_RL_coreFix_memExe_doRespLdMem ;
  assign MUX_rf$write_3_wr_1__SEL_5 =
	     MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[84] ;
  assign MUX_rf$write_3_wr_2__SEL_5 =
	     MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[84] ;
  assign MUX_rg_core_run_state$write_1__SEL_4 =
	     WILL_FIRE_RL_readyToFetch && commitStage_rg_run_state ;
  assign MUX_rob$setExecuted_deqLSQ_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ;
  assign MUX_rob$setExecuted_doFinishMem_RegData_1__SEL_5 =
	     MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[84] ;
  assign MUX_rob$setExecuted_doFinishMem_RegData_2__SEL_5 =
	     MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[84] ;
  assign MUX_sbAggr$setReady_4_put_1__SEL_1 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
	     coreFix_memExe_lsq$firstSt[150] ;
  assign MUX_sbAggr$setReady_4_put_1__SEL_2 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
	     coreFix_memExe_lsq$firstLd[89] ;
  assign MUX_sbCons$setReady_3_put_1__SEL_1 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
	     coreFix_memExe_lsq$firstSt[150] ;
  assign MUX_sbCons$setReady_3_put_1__SEL_2 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
	     coreFix_memExe_lsq$firstLd[89] ;
  assign MUX_sbCons$setReady_3_put_1__SEL_3 =
	     MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[84] ;
  assign MUX_v_f_to_TV_0$enq_1__SEL_2 =
	     WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	     rob$deqPort_0_canDeq ;
  assign MUX_regRenamingTable$rename_0_getRename_1__VAL_2 =
	     { 2'd2, f_gpr_reqs$D_OUT[68:64], 20'd345386 } ;
  assign MUX_regRenamingTable$rename_0_getRename_1__VAL_3 =
	     { 2'd3, f_fpr_reqs$D_OUT[68:64], 20'd345386 } ;
  assign MUX_commitStage_commitTrap$write_1__VAL_2 =
	     { 1'd1,
	       rob$deqPort_0_deq_data[425:362],
	       x__h703386,
	       rob_deqPort_0_deq_data__4354_BIT_166_4370_CONC_ETC___d14419,
	       rob$deqPort_0_deq_data[361:330] } ;
  assign MUX_commitStage_rg_serial_num$write_1__VAL_1 =
	     commitStage_rg_serial_num + 64'd1 ;
  assign MUX_commitStage_rg_serial_num$write_1__VAL_3 =
	     commitStage_rg_serial_num + y__h734250 ;
  assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 =
	     { fetchStage$pipelines_0_first[199:195],
	       IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883,
	       fetchStage$pipelines_0_first[173],
	       IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973,
	       fetchStage$pipelines_0_first[160:128],
	       fetchStage$pipelines_0_first[255:232],
	       regRenamingTable$rename_0_getRename,
	       rob$enqPort_0_getEnqInstTag,
	       specTagManager$currentSpecBits,
	       5'd10,
	       sbAggr$eagerLookup_0_get } ;
  assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 =
	     (k__h670634 == 1'd0 &&
	      fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14115) ?
	       { fetchStage$pipelines_0_first[199:195],
		 IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883,
		 fetchStage$pipelines_0_first[173],
		 IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973,
		 fetchStage$pipelines_0_first[160:128],
		 fetchStage$pipelines_0_first[255:232],
		 regRenamingTable$rename_0_getRename,
		 rob$enqPort_0_getEnqInstTag,
		 specTagManager$currentSpecBits,
		 fetchStage$pipelines_0_first[194:192] == 3'd1,
		 specTagManager$nextSpecTag,
		 sbAggr$eagerLookup_0_get } :
	       { fetchStage$pipelines_1_first[199:195],
		 IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599,
		 fetchStage_pipelines_1_first__2766_BIT_173_360_ETC___d13691,
		 fetchStage$pipelines_1_first[160:128],
		 fetchStage$pipelines_1_first[255:232],
		 regRenamingTable$rename_1_getRename,
		 rob$enqPort_1_getEnqInstTag,
		 renaming_spec_bits__h686248,
		 fetchStage$pipelines_1_first[194:192] == 3'd1,
		 specTagManager$nextSpecTag,
		 sbAggr$eagerLookup_1_get } ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 =
	     { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25] } ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 =
	     { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25] } ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 =
	     { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25] } ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 =
	     { 1'd1,
	       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25] } ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 =
	     { 1'd1,
	       coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25] } ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6 =
	     { 1'd1,
	       coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25] } ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 =
	     { 1'd1, coreFix_memExe_lsq$firstSt[149:143] } ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 =
	     { 1'd1, coreFix_memExe_lsq$firstLd[88:82] } ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 =
	     { 1'd1, coreFix_memExe_lsq$getHit[7:1] } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
	       (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ?
		  3'd3 :
		  3'd5) :
	       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2539 ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
	       (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ?
		  { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
		    coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
		    53'h15555555555555 } :
		  58'h155555555555554) :
	       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2550 ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2 =
	     { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
	       55'h15555555555555 } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
	       { (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
		  !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
		 3'd2,
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } :
	       { coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
		 (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
		  !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
		 3'd2,
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2 =
	     { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	       3'd2,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
	       { coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
		 (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
		  !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3],
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } :
	       { (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
		  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
		  3'd1) &&
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
		 (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
		  !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3],
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
	       (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ?
		  IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2510 :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:0]) :
	       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2523 ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2 =
	     { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
	       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2144,
	       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2500 } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3 =
	     { coreFix_memExe_dMem_cache_m_banks_0_processAmo[151:100],
	       2'd3,
	       coreFix_memExe_dMem_cache_m_banks_0_processAmo[3:0],
	       IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2008,
	       (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
		3'd0) ?
		 n__h194456 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 =
	     { IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2713,
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
	       (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
		!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) :
	       NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2526 ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 =
	     { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84],
	       x__h285848 } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 =
	     { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
	       x__h287293,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 =
	     { 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
	       SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2875,
	       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 =
	     { 2'd2,
	       addr__h290069,
	       SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2945 } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 =
	     { 1'd1,
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2 =
	     { 1'd1,
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 =
	     { x__h153727, x__h153733, 84'h82AAAAAAAAAAAAAAAAAAA } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 =
	     { x__h157274, x__h157280, 84'hCAAAAAAAAAAAAAAAAAAAA } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 =
	     { x__h160090,
	       x__h160094,
	       IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208,
	       IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212,
	       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216,
	       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1220,
	       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224,
	       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1229,
	       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1233,
	       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238,
	       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242,
	       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247,
	       x__h161942,
	       IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255,
	       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259,
	       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263,
	       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267 } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 =
	     { 1'd1,
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2 =
	     { 1'd0,
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 =
	     { 1'd1,
	       resp_addr__h291973,
	       2'd0,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 =
	     { 1'd1,
	       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq,
	       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ;
  assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 =
	     { prv__h735938,
	       prv__h735938 != 2'd3 && csrf_vm_mode_sv39_reg,
	       csrf_mxr_reg,
	       csrf_sum_reg,
	       csrf_ppn_reg } ;
  assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1 =
	     { 1'd1,
	       coreFix_memExe_lsq$getIssueLd[76:72],
	       coreFix_memExe_lsq$issueLd[63:0] } ;
  assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2 =
	     { 1'd1,
	       coreFix_memExe_issueLd$wget[76:72],
	       coreFix_memExe_lsq$issueLd[63:0] } ;
  assign MUX_coreFix_memExe_lsq$getHit_1__VAL_1 =
	     { 1'd0,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148] } ;
  assign MUX_coreFix_memExe_lsq$issueLd_4__VAL_1 =
	     { coreFix_memExe_stb$search[67],
	       coreFix_memExe_stb$search[67] ?
		 coreFix_memExe_stb$search[66:65] :
		 2'h2,
	       coreFix_memExe_stb$search[64],
	       coreFix_memExe_stb$search[64] ?
		 coreFix_memExe_stb$search[63:0] :
		 64'hAAAAAAAAAAAAAAAA } ;
  always@(coreFix_memExe_memRespLdQ_deqP or
	  coreFix_memExe_memRespLdQ_data_0 or
	  coreFix_memExe_memRespLdQ_data_1)
  begin
    case (coreFix_memExe_memRespLdQ_deqP)
      1'd0:
	  MUX_coreFix_memExe_lsq$respLd_1__VAL_1 =
	      coreFix_memExe_memRespLdQ_data_0[68:64];
      1'd1:
	  MUX_coreFix_memExe_lsq$respLd_1__VAL_1 =
	      coreFix_memExe_memRespLdQ_data_1[68:64];
    endcase
  end
  always@(coreFix_memExe_forwardQ_deqP or
	  coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1)
  begin
    case (coreFix_memExe_forwardQ_deqP)
      1'd0:
	  MUX_coreFix_memExe_lsq$respLd_1__VAL_2 =
	      coreFix_memExe_forwardQ_data_0[68:64];
      1'd1:
	  MUX_coreFix_memExe_lsq$respLd_1__VAL_2 =
	      coreFix_memExe_forwardQ_data_1[68:64];
    endcase
  end
  always@(coreFix_memExe_memRespLdQ_deqP or
	  coreFix_memExe_memRespLdQ_data_0 or
	  coreFix_memExe_memRespLdQ_data_1)
  begin
    case (coreFix_memExe_memRespLdQ_deqP)
      1'd0:
	  MUX_coreFix_memExe_lsq$respLd_2__VAL_1 =
	      coreFix_memExe_memRespLdQ_data_0[63:0];
      1'd1:
	  MUX_coreFix_memExe_lsq$respLd_2__VAL_1 =
	      coreFix_memExe_memRespLdQ_data_1[63:0];
    endcase
  end
  always@(coreFix_memExe_forwardQ_deqP or
	  coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1)
  begin
    case (coreFix_memExe_forwardQ_deqP)
      1'd0:
	  MUX_coreFix_memExe_lsq$respLd_2__VAL_2 =
	      coreFix_memExe_forwardQ_data_0[63:0];
      1'd1:
	  MUX_coreFix_memExe_lsq$respLd_2__VAL_2 =
	      coreFix_memExe_forwardQ_data_1[63:0];
    endcase
  end
  assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 =
	     { 1'd1,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148],
	       x__h197128 } ;
  assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 =
	     { 5'd0,
	       coreFix_memExe_lsq$firstSt[141:78],
	       2'd3,
	       (coreFix_memExe_lsq$firstSt[158:157] == 2'd1) ? 3'd3 : 3'd4,
	       coreFix_memExe_lsq$firstSt[76:5],
	       coreFix_memExe_lsq$firstSt[156:153],
	       coreFix_memExe_lsq$firstSt[69] &&
	       coreFix_memExe_lsq$firstSt[70] &&
	       coreFix_memExe_lsq$firstSt[71] &&
	       coreFix_memExe_lsq$firstSt[72] &&
	       coreFix_memExe_lsq$firstSt[73] &&
	       coreFix_memExe_lsq$firstSt[74] &&
	       coreFix_memExe_lsq$firstSt[75] &&
	       coreFix_memExe_lsq$firstSt[76],
	       coreFix_memExe_lsq$firstSt[152:151] } ;
  assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_2 =
	     { 5'd0,
	       coreFix_memExe_lsq$firstLd[80:17],
	       84'h92AAAAAAAAAAAAAAAAAAA } ;
  assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
	       ((!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
		 !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) ?
		  { 1'd1,
		    IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567 } :
		  65'h10000000000000001) :
	       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2570 ;
  assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2 =
	     { 1'd1,
	       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567 } ;
  assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 =
	     { 1'd1,
	       coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ?
		 curData__h192918 :
		 { {32{x__h193681[31]}}, x__h193681 } } ;
  assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 =
	     { coreFix_aluExe_0_exeToFinQ$first[146:19],
	       coreFix_aluExe_0_exeToFinQ$first[326:322],
	       coreFix_aluExe_0_exeToFinQ$first[18],
	       coreFix_aluExe_0_exeToFinQ$first[300:277],
	       1'd0,
	       coreFix_aluExe_0_exeToFinQ$first[276] } ;
  assign MUX_coreFix_trainBPQ_0$enq_1__VAL_2 =
	     { coreFix_aluExe_0_exeToFinQ$first[146:19],
	       coreFix_aluExe_0_exeToFinQ$first[326:322],
	       coreFix_aluExe_0_exeToFinQ$first[18],
	       coreFix_aluExe_0_exeToFinQ$first[300:277],
	       1'd1,
	       coreFix_aluExe_0_exeToFinQ$first[276] } ;
  assign MUX_coreFix_trainBPQ_1$enq_1__VAL_1 =
	     { coreFix_aluExe_1_exeToFinQ$first[146:19],
	       coreFix_aluExe_1_exeToFinQ$first[326:322],
	       coreFix_aluExe_1_exeToFinQ$first[18],
	       coreFix_aluExe_1_exeToFinQ$first[300:277],
	       1'd0,
	       coreFix_aluExe_1_exeToFinQ$first[276] } ;
  assign MUX_coreFix_trainBPQ_1$enq_1__VAL_2 =
	     { coreFix_aluExe_1_exeToFinQ$first[146:19],
	       coreFix_aluExe_1_exeToFinQ$first[326:322],
	       coreFix_aluExe_1_exeToFinQ$first[18],
	       coreFix_aluExe_1_exeToFinQ$first[300:277],
	       1'd1,
	       coreFix_aluExe_1_exeToFinQ$first[276] } ;
  assign MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1 =
	     MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 ||
	     MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ;
  assign MUX_csrf_fflags_reg$write_1__VAL_1 =
	     csrf_fflags_reg | fflags__h734227 ;
  assign MUX_csrf_frm_reg$write_1__VAL_1 =
	     (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd1) ?
	       robdeqPort_0_deq_data_BITS_95_TO_32__q245[2:0] :
	       robdeqPort_0_deq_data_BITS_95_TO_32__q245[7:5] ;
  assign MUX_csrf_frm_reg$write_1__VAL_2 =
	     (f_csr_reqs$D_OUT[75:64] == 12'd2) ?
	       f_csr_reqs$D_OUT[2:0] :
	       f_csr_reqs$D_OUT[7:5] ;
  always@(IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 or
	  robdeqPort_0_deq_data_BITS_95_TO_32__q245)
  begin
    case (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998)
      6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_2 = 2'b11;
      default: MUX_csrf_fs_reg$write_1__VAL_2 =
		   robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13];
    endcase
  end
  always@(f_csr_reqs$D_OUT)
  begin
    case (f_csr_reqs$D_OUT[75:64])
      12'd1, 12'd2, 12'd3: MUX_csrf_fs_reg$write_1__VAL_3 = 2'b11;
      default: MUX_csrf_fs_reg$write_1__VAL_3 = f_csr_reqs$D_OUT[14:13];
    endcase
  end
  assign MUX_csrf_ie_vec_1$write_1__VAL_1 =
	     (rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	      (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	       6'd8 ||
	       IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	       6'd18)) ?
	       robdeqPort_0_deq_data_BITS_95_TO_32__q245[1] :
	       csrf_prev_ie_vec_1 ;
  assign MUX_csrf_ie_vec_3$write_1__VAL_1 =
	     (rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	      IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd18) ?
	       robdeqPort_0_deq_data_BITS_95_TO_32__q245[3] :
	       csrf_prev_ie_vec_3 ;
  assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 =
	     rob$deqPort_0_deq_data[95:32] ;
  assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 =
	     n__read__h727667 + 64'd1 ;
  assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 =
	     n__read__h727667 + { 62'd0, x__h734491 } ;
  assign MUX_csrf_mpp_reg$write_1__VAL_1 =
	     (rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	      IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd18) ?
	       MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2[12:11] :
	       2'd0 ;
  assign MUX_csrf_mtval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ;
  assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 =
	     rob$deqPort_0_deq_data[329:325] != 5'd13 ||
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 !=
	     6'd8 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 !=
	     6'd18 ||
	     MUX_csrf_mtval_csr$write_1__VAL_1[5] ;
  assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 =
	     rob$deqPort_0_deq_data[329:325] != 5'd13 ||
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 !=
	     6'd18 ||
	     MUX_csrf_mtval_csr$write_1__VAL_1[7] ;
  assign MUX_csrf_prv_reg$write_1__VAL_1 =
	     (rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	      IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd40) ?
	       MUX_csrf_mtval_csr$write_1__VAL_1[1:0] :
	       ((rob$deqPort_0_deq_data[329:325] == 5'd19) ?
		  x__h723556 :
		  csrf_mpp_reg) ;
  assign MUX_csrf_rg_dcsr$write_1__VAL_2 =
	     { 32'b0,
	       csrf_rg_dcsr[31:9],
	       dcsr_cause__h709971,
	       csrf_rg_dcsr[5:2],
	       csrf_prv_reg } ;
  assign MUX_csrf_sepc_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ;
  assign MUX_csrf_spp_reg$write_1__VAL_1 =
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd8 ||
	      IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd18) &&
	     MUX_csrf_sepc_csr$write_1__VAL_1[8] ;
  assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ;
  assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h738339 } ;
  assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1 } ;
  assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 =
	     { csrf_prv_reg,
	       csrf_prv_reg != 2'd3 && csrf_vm_mode_sv39_reg,
	       csrf_mxr_reg,
	       csrf_sum_reg,
	       csrf_ppn_reg } ;
  always@(rob$deqPort_0_deq_data or
	  next_pc__h723452 or csrf_sepc_csr or csrf_mepc_csr)
  begin
    case (rob$deqPort_0_deq_data[329:325])
      5'd19: MUX_fetchStage$redirect_1__VAL_6 = csrf_sepc_csr;
      5'd20: MUX_fetchStage$redirect_1__VAL_6 = csrf_mepc_csr;
      default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h723452;
    endcase
  end
  assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 =
	     { 1'd1,
	       coreFix_memExe_dTlb$toParent_rqToP_first[1:0],
	       coreFix_memExe_dTlb$toParent_rqToP_first[28:2] } ;
  assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2 =
	     { 3'd2, fetchStage$iTlbIfc_toParent_rqToP_first } ;
  assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 =
	     { 1'd1,
	       mmio_dataReqQ_data_0[141:78],
	       CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q276,
	       mmio_dataReqQ_data_0[71:0] } ;
  assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2 =
	     { 1'd1,
	       fetchStage$mmioIfc_instReq_first_fst,
	       5'd2,
	       fetchStage$mmioIfc_instReq_first_snd,
	       72'hAAAAAAAAAAAAAAAAAA } ;
  assign MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1 =
	     { 1'd1,
	       coreFix_memExe_lsq$firstSt[141:78],
	       (coreFix_memExe_lsq$firstSt[158:157] == 2'd0) ?
		 6'd42 :
		 { 2'd3, coreFix_memExe_lsq$firstSt[156:153] },
	       coreFix_memExe_lsq$firstSt[76:5] } ;
  assign MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_2 =
	     { 1'd1,
	       coreFix_memExe_lsq$firstLd[80:17],
	       6'd26,
	       coreFix_memExe_lsq$firstLd[15:0],
	       56'hAAAAAAAAAAAAAA } ;
  assign MUX_rf$write_2_wr_2__VAL_2 =
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ?
	       res_data__h337876 :
	       res_data__h337871 ;
  assign MUX_rf$write_2_wr_2__VAL_3 =
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ?
	       res_data__h383578 :
	       res_data__h383573 ;
  assign MUX_rf$write_2_wr_2__VAL_4 =
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ?
	       res_data__h429273 :
	       res_data__h429268 ;
  assign MUX_rf$write_2_wr_2__VAL_5 =
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ?
	       data___1__h475010 :
	       IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8070 ;
  assign MUX_rf$write_2_wr_2__VAL_6 =
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ?
	       data___1__h475818 :
	       data__h475284 ;
  assign MUX_rf$write_3_wr_2__VAL_3 =
	     coreFix_memExe_lsq$firstLd[100] ?
	       coreFix_memExe_respLrScAmoQ_data_0 :
	       IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378 ;
  assign MUX_rf$write_3_wr_2__VAL_4 =
	     coreFix_memExe_lsq$firstLd[100] ?
	       mmio_dataRespQ_data_0[63:0] :
	       IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425 ;
  assign MUX_rob$enqPort_0_enq_1__VAL_1 =
	     { fetchStage$pipelines_0_first[387:324],
	       fetchStage$pipelines_0_first[127:96],
	       fetchStage$pipelines_0_first[199:195],
	       fetchStage$pipelines_0_first[75:69],
	       136'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
	       fetchStage$pipelines_0_first[173],
	       IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973,
	       73'h1280000000000000000,
	       fetchStage$pipelines_0_first[323:260],
	       5'd0,
	       fetchStage$pipelines_0_first[75] &&
	       fetchStage$pipelines_0_first[74],
	       fetchStage$pipelines_0_first[194:192] != 3'd0 &&
	       fetchStage$pipelines_0_first[194:192] != 3'd1 &&
	       fetchStage$pipelines_0_first[194:192] != 3'd2 &&
	       fetchStage$pipelines_0_first[194:192] != 3'd3 &&
	       fetchStage$pipelines_0_first[194:192] != 3'd4,
	       NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14181 } ;
  assign MUX_rob$enqPort_0_enq_1__VAL_2 =
	     { fetchStage$pipelines_0_first[387:324],
	       fetchStage$pipelines_0_first[127:96],
	       fetchStage$pipelines_0_first[199:195],
	       fetchStage$pipelines_0_first[75:69],
	       136'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
	       fetchStage$pipelines_0_first[173],
	       IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973,
	       2'd1,
	       renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_N_ETC___d13068,
	       IF_NOT_renameStage_rg_m_halt_req_2784_BIT_4_27_ETC___d13283,
	       fetchStage$pipelines_0_first[63:0],
	       2'd0,
	       fetchStage$pipelines_0_first[323:260],
	       20'd13601,
	       specTagManager$currentSpecBits } ;
  assign MUX_rob$enqPort_0_enq_1__VAL_3 =
	     { fetchStage$pipelines_0_first[387:324],
	       fetchStage$pipelines_0_first[127:96],
	       fetchStage$pipelines_0_first[199:195],
	       fetchStage$pipelines_0_first[75:69],
	       136'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
	       fetchStage_pipelines_0_first__2757_BIT_173_288_ETC___d13411 } ;
  assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 =
	     { 1'd1,
	       CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q277 } ;
  assign MUX_rob$setExecuted_deqLSQ_2__VAL_6 =
	     { 1'd1,
	       CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q278 } ;
  assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 =
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ?
	       coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] :
	       res_fflags__h337872 ;
  assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 =
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ?
	       coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] :
	       res_fflags__h383574 ;
  assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 =
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ?
	       coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] :
	       res_fflags__h429269 ;
  assign MUX_v_f_to_TV_0$enq_1__VAL_1 =
	     { commitStage_rg_serial_num,
	       77'h0AAAAAAAAAAAAAAAAAAA,
	       commitStage_f_rob_data$D_OUT[425:181],
	       CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q279,
	       commitStage_f_rob_data_first__4770_BIT_167_486_ETC___d14942 } ;
  assign MUX_v_f_to_TV_0$enq_1__VAL_2 =
	     { commitStage_rg_serial_num,
	       77'h0AAAAAAAAAAAAAAAAAAA,
	       rob$deqPort_0_deq_data[425:182],
	       rob_deqPort_0_deq_data__4354_BIT_181_4429_CONC_ETC___d14520,
	       rob$deqPort_0_deq_data[167],
	       rob_deqPort_0_deq_data__4354_BIT_166_4370_CONC_ETC___d14419,
	       rob$deqPort_0_deq_data[161:98],
	       IF_rob_deqPort_0_deq_data__4354_BITS_97_TO_96__ETC___d14527,
	       po_fflags__h728951,
	       rob$deqPort_0_deq_data[26],
	       new_mstatus___1__h727029,
	       258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
  assign MUX_v_f_to_TV_0$enq_1__VAL_4 =
	     { commitStage_rg_serial_num,
	       13'd4932,
	       mip_csr__read__h611253,
	       721'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
  assign MUX_v_f_to_TV_0$enq_1__VAL_5 =
	     { commitStage_rg_serial_num,
	       77'h0AAAAAAAAAAAAAAAAAAA,
	       x__h724034,
	       rob$deqPort_0_deq_data[361:182],
	       rob_deqPort_0_deq_data__4354_BIT_181_4429_CONC_ETC___d14520,
	       rob$deqPort_0_deq_data[167],
	       rob_deqPort_0_deq_data__4354_BIT_166_4370_CONC_ETC___d14419,
	       rob_deqPort_0_deq_data__4354_BITS_161_TO_98_43_ETC___d15324 } ;

  // inlined wires
  assign csrf_minstret_ehr_data_lat_0$whas =
	     MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 ||
	     MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_2 ;
  assign csrf_minstret_ehr_data_lat_1$whas =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst ||
	     WILL_FIRE_RL_commitStage_doCommitNormalInst ;
  assign csrf_minstret_ehr_data_dummy_1_0$whas =
	     WILL_FIRE_RL_commitStage_doCommitNormalInst ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst ;
  assign csrf_mcycle_ehr_data_lat_0$whas =
	     MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 ||
	     MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_2 ;
  assign csrInstOrInterruptInflight_lat_1$whas =
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	     fetchStage$pipelines_0_first[199:195] == 5'd13 ||
	     WILL_FIRE_RL_renameStage_doRenaming_Trap &&
	     renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_N_ETC___d13299 ;
  assign mmio_dataReqQ_enqReq_lat_0$wget =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ?
	       MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1 :
	       MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_2 ;
  assign mmio_dataReqQ_enqReq_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ;
  assign mmio_dataRespQ_enqReq_lat_0$wget = { 1'd1, mmio_pRsQ_data_0[64:0] } ;
  assign mmio_dataRespQ_deqReq_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ;
  assign mmio_dataPendQ_enqReq_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ;
  assign mmio_cRqQ_enqReq_lat_0$wget =
	     WILL_FIRE_RL_mmio_sendDataReq ?
	       MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 :
	       MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2 ;
  assign mmio_cRqQ_enqReq_lat_0$whas =
	     WILL_FIRE_RL_mmio_sendDataReq || WILL_FIRE_RL_mmio_sendInstReq ;
  assign mmio_pRsQ_enqReq_lat_0$wget = { 1'd1, mmioToPlatform_pRs_enq_x } ;
  assign mmio_pRsQ_deqReq_lat_0$whas =
	     WILL_FIRE_RL_mmio_sendInstResp ||
	     WILL_FIRE_RL_mmio_sendDataResp ;
  assign mmio_pRqQ_enqReq_lat_0$wget =
	     { 1'd1,
	       mmioToPlatform_pRq_enq_x[38],
	       CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q280,
	       mmioToPlatform_pRq_enq_x[31:0] } ;
  assign mmio_cRsQ_enqReq_lat_0$wget =
	     { 1'd1, csrf_software_int_pend_vec_3 } ;
  assign coreFix_globalSpecUpdate_correctSpecTag_0$whas =
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
	     coreFix_aluExe_0_exeToFinQ$first[16] ;
  assign coreFix_globalSpecUpdate_correctSpecTag_1$whas =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
	     coreFix_aluExe_1_exeToFinQ$first[16] ;
  assign coreFix_aluExe_0_bypassWire_0$wget =
	     { coreFix_aluExe_0_regToExeQ$first[348:342],
	       basicExec___d12617[321:258] } ;
  assign coreFix_aluExe_0_bypassWire_0$whas =
	     WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
	     coreFix_aluExe_0_regToExeQ$first[349] ;
  assign coreFix_aluExe_0_bypassWire_1$wget =
	     { coreFix_aluExe_1_regToExeQ$first[348:342],
	       basicExec___d11943[321:258] } ;
  assign coreFix_aluExe_0_bypassWire_1$whas =
	     WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
	     coreFix_aluExe_1_regToExeQ$first[349] ;
  assign coreFix_aluExe_0_bypassWire_2$wget =
	     { coreFix_aluExe_0_exeToFinQ$first[320:314],
	       coreFix_aluExe_0_exeToFinQ$first[275:212] } ;
  assign coreFix_aluExe_0_bypassWire_2$whas =
	     _dor1coreFix_aluExe_0_bypassWire_2$EN_wset &&
	     coreFix_aluExe_0_exeToFinQ$first[321] ;
  assign coreFix_aluExe_0_bypassWire_3$wget =
	     { coreFix_aluExe_1_exeToFinQ$first[320:314],
	       coreFix_aluExe_1_exeToFinQ$first[275:212] } ;
  assign coreFix_aluExe_0_bypassWire_3$whas =
	     _dor1coreFix_aluExe_0_bypassWire_3$EN_wset &&
	     coreFix_aluExe_1_exeToFinQ$first[321] ;
  assign coreFix_aluExe_1_bypassWire_2$whas =
	     _dor1coreFix_aluExe_1_bypassWire_2$EN_wset &&
	     coreFix_aluExe_0_exeToFinQ$first[321] ;
  assign coreFix_aluExe_1_bypassWire_3$whas =
	     _dor1coreFix_aluExe_1_bypassWire_3$EN_wset &&
	     coreFix_aluExe_1_exeToFinQ$first[321] ;
  assign coreFix_fpuMulDivExe_0_bypassWire_2$whas =
	     _dor1coreFix_fpuMulDivExe_0_bypassWire_2$EN_wset &&
	     coreFix_aluExe_0_exeToFinQ$first[321] ;
  assign coreFix_fpuMulDivExe_0_bypassWire_3$whas =
	     _dor1coreFix_fpuMulDivExe_0_bypassWire_3$EN_wset &&
	     coreFix_aluExe_1_exeToFinQ$first[321] ;
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225])
      2'd0, 2'd1:
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[226:225];
      default: coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget = 2'd2;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) ;
  assign coreFix_memExe_bypassWire_2$whas =
	     _dor1coreFix_memExe_bypassWire_2$EN_wset &&
	     coreFix_aluExe_0_exeToFinQ$first[321] ;
  assign coreFix_memExe_bypassWire_3$whas =
	     _dor1coreFix_memExe_bypassWire_3$EN_wset &&
	     coreFix_aluExe_1_exeToFinQ$first[321] ;
  assign coreFix_memExe_issueLd$wget =
	     { coreFix_memExe_dTlb$procResp[161:157],
	       coreFix_memExe_dTlb$procResp[246:183],
	       coreFix_memExe_dTlb$procResp[156:149] } ;
  assign coreFix_memExe_issueLd$whas =
	     WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
	     coreFix_memExe_dTlb$procResp[177:175] == 3'd0 &&
	     NOT_coreFix_memExe_dTlb_procResp__714_BITS_246_ETC___d1755 &&
	     IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1744 &&
	     !coreFix_memExe_lsq$updateAddr ;
  assign coreFix_memExe_reqLdQ_data_0_lat_0$wget =
	     MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1 ?
	       coreFix_memExe_issueLd$wget[76:8] :
	       coreFix_memExe_lsq$getIssueLd[76:8] ;
  assign coreFix_memExe_reqLdQ_data_0_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
	     coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
	     coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
  assign coreFix_memExe_reqLdQ_empty_lat_0$whas =
	     _dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset &&
	     coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
  assign coreFix_memExe_reqLdQ_full_lat_0$whas =
	     _dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset &&
	     coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ?
	       MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 :
	       MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_2 ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;
  assign coreFix_memExe_reqStQ_data_0_lat_0$wget =
	     { coreFix_memExe_stb$issue[635:576], 6'd0 } ;
  assign coreFix_memExe_forwardQ_enqReq_lat_0$wget =
	     MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 ?
	       MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1 :
	       MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2 ;
  assign coreFix_memExe_forwardQ_enqReq_lat_0$whas =
	     MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 ||
	     MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2 ;
  assign coreFix_memExe_memRespLdQ_enqReq_lat_0$wget =
	     MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ?
	       MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 :
	       MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 ;
  assign coreFix_memExe_memRespLdQ_enqReq_lat_0$whas =
	     MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ||
	     MUX_coreFix_memExe_lsq$getHit_1__SEL_2 ;
  always@(MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 or
	  MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 or
	  MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2 or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
	  MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1:
	  coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
	      MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1;
      MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2:
	  coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
	      MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2;
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
	  coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
	      MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3;
      default: coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
		   65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas =
	     MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 ||
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
  assign coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
  always@(WILL_FIRE_RL_coreFix_memExe_sendLdToMem or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 or
	  WILL_FIRE_RL_coreFix_memExe_sendStToMem or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 or
	  WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_memExe_sendLdToMem:
	  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1;
      WILL_FIRE_RL_coreFix_memExe_sendStToMem:
	  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2;
      WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem:
	  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3;
      default: coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
		   153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_sendLdToMem ||
	     WILL_FIRE_RL_coreFix_memExe_sendStToMem ||
	     WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ?
	       MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 :
	       MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget =
	     { 1'd1,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq[147:84],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot[54:53],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq[83:82],
	       1'd1,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot[57:55] } ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget =
	     { 1'd1, dCacheToParent_fromP_enq_x } ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget =
	     { 1'd1,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2649 ;
  always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1:
	  coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1;
      MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2:
	  coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2;
      MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3:
	  coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
	      59'h2AAAAAAAAAAAAAA;
      default: coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
		   59'h2AAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas =
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 ||
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 ||
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ;
  assign coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ||
	     WILL_FIRE_RL_coreFix_memExe_sendStToMem ||
	     WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;

  // register commitStage_commitTrap
  assign commitStage_commitTrap$D_IN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle ?
	       166'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
	       MUX_commitStage_commitTrap$write_1__VAL_2 ;
  assign commitStage_commitTrap$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;

  // register commitStage_rg_just_after_reset
  assign commitStage_rg_just_after_reset$D_IN = 1'd0 ;
  assign commitStage_rg_just_after_reset$EN =
	     CAN_FIRE_RL_commitStage_rl_send_tv_reset ;

  // register commitStage_rg_old_mip_csr_val
  assign commitStage_rg_old_mip_csr_val$D_IN = mip_csr__read__h611253 ;
  assign commitStage_rg_old_mip_csr_val$EN =
	     CAN_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv ;

  // register commitStage_rg_run_state
  assign commitStage_rg_run_state$D_IN =
	     MUX_commitStage_rg_run_state$write_1__SEL_1 ;
  assign commitStage_rg_run_state$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 ||
	     WILL_FIRE_RL_rl_debug_resume ;

  // register commitStage_rg_serial_num
  always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or
	  MUX_commitStage_rg_serial_num$write_1__VAL_1 or
	  MUX_commitStage_rg_serial_num$write_1__SEL_2 or
	  WILL_FIRE_RL_commitStage_doCommitNormalInst or
	  MUX_commitStage_rg_serial_num$write_1__VAL_3 or
	  WILL_FIRE_RL_commitStage_rl_send_tv_reset)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_commitStage_rg_serial_num$write_1__SEL_1:
	  commitStage_rg_serial_num$D_IN =
	      MUX_commitStage_rg_serial_num$write_1__VAL_1;
      MUX_commitStage_rg_serial_num$write_1__SEL_2:
	  commitStage_rg_serial_num$D_IN =
	      MUX_commitStage_rg_serial_num$write_1__VAL_1;
      WILL_FIRE_RL_commitStage_doCommitNormalInst:
	  commitStage_rg_serial_num$D_IN =
	      MUX_commitStage_rg_serial_num$write_1__VAL_3;
      WILL_FIRE_RL_commitStage_rl_send_tv_reset:
	  commitStage_rg_serial_num$D_IN = 64'd1;
      default: commitStage_rg_serial_num$D_IN =
		   64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign commitStage_rg_serial_num$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 ||
	     WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst ||
	     WILL_FIRE_RL_commitStage_doCommitNormalInst ||
	     WILL_FIRE_RL_commitStage_rl_send_tv_reset ;

  // register coreFix_doStatsReg
  assign coreFix_doStatsReg$D_IN = 1'b0 ;
  assign coreFix_doStatsReg$EN = 1'b0 ;

  // register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$D_IN =
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt + 4'd1 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$EN =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit ;

  // register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$D_IN = 1'd1 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$EN =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt == 4'd15 ;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN =
	     coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ?
	       v__h604530 :
	       v__h603885 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$D_IN =
	     { coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas,
	       coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget } ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$EN = 1'd1 ;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$D_IN =
	     coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$D_IN =
	     1'd0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$EN =
	     1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ?
	       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[2:0] :
	       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[2:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
	     3'd0 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3057 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
	     3'd1 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3057 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
	     3'd2 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3057 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
	     3'd3 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3057 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
	     3'd4 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3057 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
	     3'd5 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3057 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
	     3'd6 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3057 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
	     3'd7 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3057 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ?
	       3'd0 :
	       _theResult_____2__h296523 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$D_IN =
	     1'd0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$EN =
	     1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ||
	     IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3058 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3078 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ?
	       3'd0 :
	       v__h295943 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$D_IN =
	     4'b0010 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$EN =
	     1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$D_IN =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3057 &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3058 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3067 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN =
	     { !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT ||
	       IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3180 ||
	       (EN_dCacheToParent_fromP_enq ?
		  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[582] :
		  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[582]),
	       IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3247 } ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP == 1'd0 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3127 &&
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3138 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP == 1'd1 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3127 &&
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3138 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3127 &&
	     _theResult_____2__h304519 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT &&
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl ||
	     IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3160 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3183 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3127 &&
	     v__h299288 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN =
	     584'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$D_IN =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3127 &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3160 &&
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3170 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$D_IN =
	     { IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3004,
	       IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3012 } ;
  assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_processAmo
  always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2 or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1:
	  coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1;
      MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2:
	  coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2;
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
	  coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
	      161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
      default: coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
		   161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_dMem_cache_m_banks_0_processAmo$EN =
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd4 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget :
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$D_IN =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ||
	     !coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas &&
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$D_IN =
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ||
	      coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$D_IN =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[71:0] :
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[71:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP == 1'd0 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3298 &&
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3309 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$D_IN =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[71:0] :
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[71:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP == 1'd1 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3298 &&
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3309 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3298 &&
	     _theResult_____2__h310513 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT &&
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl ||
	     IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3332 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3355 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3298 &&
	     v__h309802 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$D_IN =
	     73'h0AAAAAAAAAAAAAAAAAA ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$D_IN =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3298 &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3332 &&
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enq_ETC___d3341 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN =
	     { x_addr__h314076,
	       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
		 coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] :
		 coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513],
	       !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT ||
	       IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3447 ||
	       (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
		  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[512] :
		  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[512]),
	       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
		 coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[511:0] :
		 coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[511:0] } ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP == 1'd0 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3394 &&
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3405 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP == 1'd1 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3394 &&
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3405 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3394 &&
	     _theResult_____2__h318367 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT &&
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl ||
	     IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3428 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3451 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3394 &&
	     v__h313678 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN =
	     580'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$D_IN =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3394 &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3428 &&
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enq_ETC___d3437 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$EN = 1'd1 ;

  // register coreFix_memExe_dMem_perfReqQ_clearReq_rl
  assign coreFix_memExe_dMem_perfReqQ_clearReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_dMem_perfReqQ_clearReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_perfReqQ_data_0
  assign coreFix_memExe_dMem_perfReqQ_data_0$D_IN =
	     coreFix_memExe_dMem_perfReqQ_enqReq_rl[3:0] ;
  assign coreFix_memExe_dMem_perfReqQ_data_0$EN =
	     NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1883 &&
	     coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT &&
	     coreFix_memExe_dMem_perfReqQ_enqReq_rl[4] ;

  // register coreFix_memExe_dMem_perfReqQ_deqReq_rl
  assign coreFix_memExe_dMem_perfReqQ_deqReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_dMem_perfReqQ_deqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_perfReqQ_empty
  assign coreFix_memExe_dMem_perfReqQ_empty$D_IN =
	     coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT &&
	     coreFix_memExe_dMem_perfReqQ_clearReq_rl ||
	     NOT_coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_ETC___d1927 ;
  assign coreFix_memExe_dMem_perfReqQ_empty$EN = 1'd1 ;

  // register coreFix_memExe_dMem_perfReqQ_enqReq_rl
  assign coreFix_memExe_dMem_perfReqQ_enqReq_rl$D_IN = 5'b01010 ;
  assign coreFix_memExe_dMem_perfReqQ_enqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_perfReqQ_full
  assign coreFix_memExe_dMem_perfReqQ_full$D_IN =
	     NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1883 &&
	     coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2_r_ETC___d1911 ;
  assign coreFix_memExe_dMem_perfReqQ_full$EN = 1'd1 ;

  // register coreFix_memExe_forwardQ_clearReq_rl
  assign coreFix_memExe_forwardQ_clearReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_forwardQ_clearReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_forwardQ_data_0
  assign coreFix_memExe_forwardQ_data_0$D_IN =
	     coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
	       coreFix_memExe_forwardQ_enqReq_lat_0$wget[68:0] :
	       coreFix_memExe_forwardQ_enqReq_rl[68:0] ;
  assign coreFix_memExe_forwardQ_data_0$EN =
	     coreFix_memExe_forwardQ_enqP == 1'd0 &&
	     NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3717 &&
	     coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3728 ;

  // register coreFix_memExe_forwardQ_data_1
  assign coreFix_memExe_forwardQ_data_1$D_IN =
	     coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
	       coreFix_memExe_forwardQ_enqReq_lat_0$wget[68:0] :
	       coreFix_memExe_forwardQ_enqReq_rl[68:0] ;
  assign coreFix_memExe_forwardQ_data_1$EN =
	     coreFix_memExe_forwardQ_enqP == 1'd1 &&
	     NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3717 &&
	     coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3728 ;

  // register coreFix_memExe_forwardQ_deqP
  assign coreFix_memExe_forwardQ_deqP$D_IN =
	     NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3717 &&
	     _theResult_____2__h331936 ;
  assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ;

  // register coreFix_memExe_forwardQ_deqReq_rl
  assign coreFix_memExe_forwardQ_deqReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_forwardQ_deqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_forwardQ_empty
  assign coreFix_memExe_forwardQ_empty$D_IN =
	     coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT &&
	     coreFix_memExe_forwardQ_clearReq_rl ||
	     IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3750 &&
	     NOT_coreFix_memExe_forwardQ_enqReq_dummy2_2_re_ETC___d3772 ;
  assign coreFix_memExe_forwardQ_empty$EN = 1'd1 ;

  // register coreFix_memExe_forwardQ_enqP
  assign coreFix_memExe_forwardQ_enqP$D_IN =
	     NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3717 &&
	     v__h331504 ;
  assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ;

  // register coreFix_memExe_forwardQ_enqReq_rl
  assign coreFix_memExe_forwardQ_enqReq_rl$D_IN = 70'h0AAAAAAAAAAAAAAAAA ;
  assign coreFix_memExe_forwardQ_enqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_forwardQ_full
  assign coreFix_memExe_forwardQ_full$D_IN =
	     NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3717 &&
	     IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3750 &&
	     coreFix_memExe_forwardQ_enqReq_dummy2_2_read___ETC___d3759 ;
  assign coreFix_memExe_forwardQ_full$EN = 1'd1 ;

  // register coreFix_memExe_memRespLdQ_clearReq_rl
  assign coreFix_memExe_memRespLdQ_clearReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_memRespLdQ_clearReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_memRespLdQ_data_0
  assign coreFix_memExe_memRespLdQ_data_0$D_IN =
	     coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
	       coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[68:0] :
	       coreFix_memExe_memRespLdQ_enqReq_rl[68:0] ;
  assign coreFix_memExe_memRespLdQ_data_0$EN =
	     coreFix_memExe_memRespLdQ_enqP == 1'd0 &&
	     NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3623 &&
	     coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3634 ;

  // register coreFix_memExe_memRespLdQ_data_1
  assign coreFix_memExe_memRespLdQ_data_1$D_IN =
	     coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
	       coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[68:0] :
	       coreFix_memExe_memRespLdQ_enqReq_rl[68:0] ;
  assign coreFix_memExe_memRespLdQ_data_1$EN =
	     coreFix_memExe_memRespLdQ_enqP == 1'd1 &&
	     NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3623 &&
	     coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3634 ;

  // register coreFix_memExe_memRespLdQ_deqP
  assign coreFix_memExe_memRespLdQ_deqP$D_IN =
	     NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3623 &&
	     _theResult_____2__h328711 ;
  assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ;

  // register coreFix_memExe_memRespLdQ_deqReq_rl
  assign coreFix_memExe_memRespLdQ_deqReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_memRespLdQ_deqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_memRespLdQ_empty
  assign coreFix_memExe_memRespLdQ_empty$D_IN =
	     coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT &&
	     coreFix_memExe_memRespLdQ_clearReq_rl ||
	     IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3656 &&
	     NOT_coreFix_memExe_memRespLdQ_enqReq_dummy2_2__ETC___d3678 ;
  assign coreFix_memExe_memRespLdQ_empty$EN = 1'd1 ;

  // register coreFix_memExe_memRespLdQ_enqP
  assign coreFix_memExe_memRespLdQ_enqP$D_IN =
	     NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3623 &&
	     v__h328279 ;
  assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ;

  // register coreFix_memExe_memRespLdQ_enqReq_rl
  assign coreFix_memExe_memRespLdQ_enqReq_rl$D_IN = 70'h0AAAAAAAAAAAAAAAAA ;
  assign coreFix_memExe_memRespLdQ_enqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_memRespLdQ_full
  assign coreFix_memExe_memRespLdQ_full$D_IN =
	     NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3623 &&
	     IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3656 &&
	     coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3665 ;
  assign coreFix_memExe_memRespLdQ_full$EN = 1'd1 ;

  // register coreFix_memExe_reqLdQ_data_0_rl
  assign coreFix_memExe_reqLdQ_data_0_rl$D_IN =
	     coreFix_memExe_reqLdQ_data_0_lat_0$whas ?
	       coreFix_memExe_reqLdQ_data_0_lat_0$wget :
	       coreFix_memExe_reqLdQ_data_0_rl ;
  assign coreFix_memExe_reqLdQ_data_0_rl$EN = 1'd1 ;

  // register coreFix_memExe_reqLdQ_empty_rl
  assign coreFix_memExe_reqLdQ_empty_rl$D_IN =
	     WILL_FIRE_RL_coreFix_memExe_sendLdToMem ||
	     !coreFix_memExe_reqLdQ_empty_lat_0$whas &&
	     coreFix_memExe_reqLdQ_empty_rl ;
  assign coreFix_memExe_reqLdQ_empty_rl$EN = 1'd1 ;

  // register coreFix_memExe_reqLdQ_full_rl
  assign coreFix_memExe_reqLdQ_full_rl$D_IN =
	     !WILL_FIRE_RL_coreFix_memExe_sendLdToMem &&
	     (coreFix_memExe_reqLdQ_full_lat_0$whas ||
	      coreFix_memExe_reqLdQ_full_rl) ;
  assign coreFix_memExe_reqLdQ_full_rl$EN = 1'd1 ;

  // register coreFix_memExe_reqLrScAmoQ_data_0_rl
  assign coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN =
	     coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
	       coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget :
	       coreFix_memExe_reqLrScAmoQ_data_0_rl ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_rl$EN = 1'd1 ;

  // register coreFix_memExe_reqLrScAmoQ_empty_rl
  assign coreFix_memExe_reqLrScAmoQ_empty_rl$D_IN =
	     CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ||
	     !coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas &&
	     coreFix_memExe_reqLrScAmoQ_empty_rl ;
  assign coreFix_memExe_reqLrScAmoQ_empty_rl$EN = 1'd1 ;

  // register coreFix_memExe_reqLrScAmoQ_full_rl
  assign coreFix_memExe_reqLrScAmoQ_full_rl$D_IN =
	     !CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem &&
	     (coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ||
	      coreFix_memExe_reqLrScAmoQ_full_rl) ;
  assign coreFix_memExe_reqLrScAmoQ_full_rl$EN = 1'd1 ;

  // register coreFix_memExe_reqStQ_data_0_rl
  assign coreFix_memExe_reqStQ_data_0_rl$D_IN =
	     CAN_FIRE_RL_coreFix_memExe_doIssueSB ?
	       coreFix_memExe_reqStQ_data_0_lat_0$wget :
	       coreFix_memExe_reqStQ_data_0_rl ;
  assign coreFix_memExe_reqStQ_data_0_rl$EN = 1'd1 ;

  // register coreFix_memExe_reqStQ_empty_rl
  assign coreFix_memExe_reqStQ_empty_rl$D_IN =
	     WILL_FIRE_RL_coreFix_memExe_sendStToMem ||
	     !CAN_FIRE_RL_coreFix_memExe_doIssueSB &&
	     coreFix_memExe_reqStQ_empty_rl ;
  assign coreFix_memExe_reqStQ_empty_rl$EN = 1'd1 ;

  // register coreFix_memExe_reqStQ_full_rl
  assign coreFix_memExe_reqStQ_full_rl$D_IN =
	     !WILL_FIRE_RL_coreFix_memExe_sendStToMem &&
	     (CAN_FIRE_RL_coreFix_memExe_doIssueSB ||
	      coreFix_memExe_reqStQ_full_rl) ;
  assign coreFix_memExe_reqStQ_full_rl$EN = 1'd1 ;

  // register coreFix_memExe_respLrScAmoQ_clearReq_rl
  assign coreFix_memExe_respLrScAmoQ_clearReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_respLrScAmoQ_clearReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_respLrScAmoQ_data_0
  assign coreFix_memExe_respLrScAmoQ_data_0$D_IN =
	     coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ?
	       coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[63:0] :
	       coreFix_memExe_respLrScAmoQ_enqReq_rl[63:0] ;
  assign coreFix_memExe_respLrScAmoQ_data_0$EN =
	     NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3547 &&
	     coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3558 ;

  // register coreFix_memExe_respLrScAmoQ_deqReq_rl
  assign coreFix_memExe_respLrScAmoQ_deqReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_respLrScAmoQ_deqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_respLrScAmoQ_empty
  assign coreFix_memExe_respLrScAmoQ_empty$D_IN =
	     coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT &&
	     coreFix_memExe_respLrScAmoQ_clearReq_rl ||
	     NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3589 ;
  assign coreFix_memExe_respLrScAmoQ_empty$EN = 1'd1 ;

  // register coreFix_memExe_respLrScAmoQ_enqReq_rl
  assign coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN = 65'h0AAAAAAAAAAAAAAAA ;
  assign coreFix_memExe_respLrScAmoQ_enqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_respLrScAmoQ_full
  assign coreFix_memExe_respLrScAmoQ_full$D_IN =
	     NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3547 &&
	     coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3574 ;
  assign coreFix_memExe_respLrScAmoQ_full$EN = 1'd1 ;

  // register coreFix_memExe_waitLrScAmoMMIOResp
  always@(MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1 or
	  WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue or
	  WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue or
	  WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue or
	  WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1:
	  coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd0;
      WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue:
	  coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd4;
      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue:
	  coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd2;
      WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue:
	  coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd6;
      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue:
	  coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd7;
      default: coreFix_memExe_waitLrScAmoMMIOResp$D_IN =
		   3'b010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_waitLrScAmoMMIOResp$EN =
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ;

  // register csrInstOrInterruptInflight_rl
  assign csrInstOrInterruptInflight_rl$D_IN =
	     csrInstOrInterruptInflight_lat_1$whas ?
	       1'd1 :
	       (MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1 ?
		  1'd0 :
		  csrInstOrInterruptInflight_rl) ;
  assign csrInstOrInterruptInflight_rl$EN = 1'd1 ;

  // register csrf_external_int_en_vec_0
  assign csrf_external_int_en_vec_0$D_IN = 1'b0 ;
  assign csrf_external_int_en_vec_0$EN = 1'b0 ;

  // register csrf_external_int_en_vec_1
  assign csrf_external_int_en_vec_1$D_IN =
	     MUX_csrf_external_int_en_vec_1$write_1__SEL_1 ?
	       MUX_csrf_stval_csr$write_1__VAL_1[9] :
	       f_csr_reqs$D_OUT[9] ;
  assign csrf_external_int_en_vec_1$EN =
	     MUX_csrf_external_int_en_vec_1$write_1__SEL_1 ||
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     (f_csr_reqs$D_OUT[75:64] == 12'd260 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd772) ;

  // register csrf_external_int_en_vec_3
  assign csrf_external_int_en_vec_3$D_IN =
	     MUX_csrf_external_int_en_vec_3$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[11] :
	       MUX_csrf_stval_csr$write_1__VAL_1[11] ;
  assign csrf_external_int_en_vec_3$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd772 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd22 ;

  // register csrf_external_int_pend_vec_0
  assign csrf_external_int_pend_vec_0$D_IN = 1'b0 ;
  assign csrf_external_int_pend_vec_0$EN = 1'b0 ;

  // register csrf_external_int_pend_vec_1
  always@(MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 or
	  MUX_csrf_stval_csr$write_1__VAL_1 or
	  MUX_csrf_external_int_pend_vec_1$write_1__SEL_2 or
	  f_csr_reqs$D_OUT or EN_setSEIP or setSEIP_v)
  case (1'b1)
    MUX_csrf_external_int_pend_vec_1$write_1__SEL_1:
	csrf_external_int_pend_vec_1$D_IN =
	    MUX_csrf_stval_csr$write_1__VAL_1[9];
    MUX_csrf_external_int_pend_vec_1$write_1__SEL_2:
	csrf_external_int_pend_vec_1$D_IN = f_csr_reqs$D_OUT[9];
    EN_setSEIP: csrf_external_int_pend_vec_1$D_IN = setSEIP_v;
    default: csrf_external_int_pend_vec_1$D_IN =
		 1'b0 /* unspecified value */ ;
  endcase
  assign csrf_external_int_pend_vec_1$EN =
	     MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ||
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     (f_csr_reqs$D_OUT[75:64] == 12'd324 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd836) ||
	     EN_setSEIP ;

  // register csrf_external_int_pend_vec_3
  assign csrf_external_int_pend_vec_3$D_IN = setMEIP_v ;
  assign csrf_external_int_pend_vec_3$EN = EN_setMEIP ;

  // register csrf_fflags_reg
  always@(MUX_csrf_fflags_reg$write_1__SEL_1 or
	  MUX_csrf_fflags_reg$write_1__VAL_1 or
	  MUX_csrf_fflags_reg$write_1__SEL_2 or
	  MUX_csrf_stval_csr$write_1__VAL_1 or
	  MUX_csrf_fflags_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
  case (1'b1)
    MUX_csrf_fflags_reg$write_1__SEL_1:
	csrf_fflags_reg$D_IN = MUX_csrf_fflags_reg$write_1__VAL_1;
    MUX_csrf_fflags_reg$write_1__SEL_2:
	csrf_fflags_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0];
    MUX_csrf_fflags_reg$write_1__SEL_3:
	csrf_fflags_reg$D_IN = f_csr_reqs$D_OUT[4:0];
    default: csrf_fflags_reg$D_IN = 5'b01010 /* unspecified value */ ;
  endcase
  assign csrf_fflags_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd0 ||
	      IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd2) ||
	     WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	     NOT_IF_NOT_rob_deqPort_0_canDeq__5346_5347_OR__ETC___d15689 ||
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     (f_csr_reqs$D_OUT[75:64] == 12'd1 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd3) ;

  // register csrf_frm_reg
  assign csrf_frm_reg$D_IN =
	     MUX_csrf_frm_reg$write_1__SEL_1 ?
	       MUX_csrf_frm_reg$write_1__VAL_1 :
	       MUX_csrf_frm_reg$write_1__VAL_2 ;
  assign csrf_frm_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd1 ||
	      IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd2) ||
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     (f_csr_reqs$D_OUT[75:64] == 12'd2 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd3) ;

  // register csrf_fs_reg
  always@(MUX_csrf_fflags_reg$write_1__SEL_1 or
	  MUX_csrf_fs_reg$write_1__SEL_2 or
	  MUX_csrf_fs_reg$write_1__VAL_2 or
	  MUX_csrf_fs_reg$write_1__SEL_3 or MUX_csrf_fs_reg$write_1__VAL_3)
  case (1'b1)
    MUX_csrf_fflags_reg$write_1__SEL_1: csrf_fs_reg$D_IN = 2'b11;
    MUX_csrf_fs_reg$write_1__SEL_2:
	csrf_fs_reg$D_IN = MUX_csrf_fs_reg$write_1__VAL_2;
    MUX_csrf_fs_reg$write_1__SEL_3:
	csrf_fs_reg$D_IN = MUX_csrf_fs_reg$write_1__VAL_3;
    default: csrf_fs_reg$D_IN = 2'b10 /* unspecified value */ ;
  endcase
  assign csrf_fs_reg$EN =
	     MUX_csrf_fs_reg$write_1__SEL_2 ||
	     WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	     NOT_IF_NOT_rob_deqPort_0_canDeq__5346_5347_OR__ETC___d15689 ||
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     (f_csr_reqs$D_OUT[75:64] == 12'd1 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd2 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd3 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd256 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd768) ;

  // register csrf_ie_vec_0
  assign csrf_ie_vec_0$D_IN =
	     MUX_csrf_ie_vec_0$write_1__SEL_1 ?
	       MUX_csrf_stval_csr$write_1__VAL_1[0] :
	       f_csr_reqs$D_OUT[0] ;
  assign csrf_ie_vec_0$EN =
	     MUX_csrf_ie_vec_0$write_1__SEL_1 ||
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     (f_csr_reqs$D_OUT[75:64] == 12'd256 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd768) ;

  // register csrf_ie_vec_1
  always@(MUX_csrf_ie_vec_1$write_1__SEL_1 or
	  MUX_csrf_ie_vec_1$write_1__VAL_1 or
	  MUX_csrf_ie_vec_1$write_1__SEL_2 or
	  MUX_csrf_ie_vec_0$write_1__SEL_2 or f_csr_reqs$D_OUT)
  case (1'b1)
    MUX_csrf_ie_vec_1$write_1__SEL_1:
	csrf_ie_vec_1$D_IN = MUX_csrf_ie_vec_1$write_1__VAL_1;
    MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_ie_vec_1$D_IN = 1'd0;
    MUX_csrf_ie_vec_0$write_1__SEL_2:
	csrf_ie_vec_1$D_IN = f_csr_reqs$D_OUT[1];
    default: csrf_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign csrf_ie_vec_1$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 &&
	     csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 ||
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     (f_csr_reqs$D_OUT[75:64] == 12'd256 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd768) ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ;

  // register csrf_ie_vec_3
  always@(MUX_csrf_ie_vec_3$write_1__SEL_1 or
	  MUX_csrf_ie_vec_3$write_1__VAL_1 or
	  MUX_csrf_ie_vec_3$write_1__SEL_2 or
	  MUX_csrf_ie_vec_3$write_1__SEL_3 or f_csr_reqs$D_OUT)
  case (1'b1)
    MUX_csrf_ie_vec_3$write_1__SEL_1:
	csrf_ie_vec_3$D_IN = MUX_csrf_ie_vec_3$write_1__VAL_1;
    MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_ie_vec_3$D_IN = 1'd0;
    MUX_csrf_ie_vec_3$write_1__SEL_3:
	csrf_ie_vec_3$D_IN = f_csr_reqs$D_OUT[3];
    default: csrf_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign csrf_ie_vec_3$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd768 ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 &&
	     NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ;

  // register csrf_mcause_code_reg
  always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or
	  MUX_csrf_stval_csr$write_1__VAL_1 or
	  MUX_csrf_ie_vec_3$write_1__SEL_2 or
	  cause_code__h710452 or
	  MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
  case (1'b1)
    MUX_csrf_mcause_code_reg$write_1__SEL_1:
	csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0];
    MUX_csrf_ie_vec_3$write_1__SEL_2:
	csrf_mcause_code_reg$D_IN = cause_code__h710452;
    MUX_csrf_mcause_code_reg$write_1__SEL_3:
	csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0];
    default: csrf_mcause_code_reg$D_IN = 4'b1010 /* unspecified value */ ;
  endcase
  assign csrf_mcause_code_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd834 ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 &&
	     NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd27 ;

  // register csrf_mcause_interrupt_reg
  always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or
	  MUX_csrf_stval_csr$write_1__VAL_1 or
	  MUX_csrf_ie_vec_3$write_1__SEL_2 or
	  commitStage_commitTrap or
	  MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
  case (1'b1)
    MUX_csrf_mcause_code_reg$write_1__SEL_1:
	csrf_mcause_interrupt_reg$D_IN =
	    MUX_csrf_stval_csr$write_1__VAL_1[63];
    MUX_csrf_ie_vec_3$write_1__SEL_2:
	csrf_mcause_interrupt_reg$D_IN = commitStage_commitTrap[36];
    MUX_csrf_mcause_code_reg$write_1__SEL_3:
	csrf_mcause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63];
    default: csrf_mcause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign csrf_mcause_interrupt_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd834 ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 &&
	     NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd27 ;

  // register csrf_mcounteren_cy_reg
  assign csrf_mcounteren_cy_reg$D_IN =
	     MUX_csrf_mcounteren_cy_reg$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[0] :
	       MUX_csrf_stval_csr$write_1__VAL_1[0] ;
  assign csrf_mcounteren_cy_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd774 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd24 ;

  // register csrf_mcounteren_ir_reg
  assign csrf_mcounteren_ir_reg$D_IN =
	     MUX_csrf_mcounteren_cy_reg$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[2] :
	       MUX_csrf_stval_csr$write_1__VAL_1[2] ;
  assign csrf_mcounteren_ir_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd774 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd24 ;

  // register csrf_mcounteren_tm_reg
  assign csrf_mcounteren_tm_reg$D_IN =
	     MUX_csrf_mcounteren_cy_reg$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[1] :
	       MUX_csrf_stval_csr$write_1__VAL_1[1] ;
  assign csrf_mcounteren_tm_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd774 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd24 ;

  // register csrf_mcycle_ehr_data_rl
  assign csrf_mcycle_ehr_data_rl$D_IN = upd__h5311 ;
  assign csrf_mcycle_ehr_data_rl$EN = 1'd1 ;

  // register csrf_medeleg_13_11_reg
  assign csrf_medeleg_13_11_reg$D_IN =
	     MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[13:11] :
	       MUX_csrf_stval_csr$write_1__VAL_1[13:11] ;
  assign csrf_medeleg_13_11_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd770 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd20 ;

  // register csrf_medeleg_15_reg
  assign csrf_medeleg_15_reg$D_IN =
	     MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[15] :
	       MUX_csrf_stval_csr$write_1__VAL_1[15] ;
  assign csrf_medeleg_15_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd770 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd20 ;

  // register csrf_medeleg_9_0_reg
  assign csrf_medeleg_9_0_reg$D_IN =
	     MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[9:0] :
	       MUX_csrf_stval_csr$write_1__VAL_1[9:0] ;
  assign csrf_medeleg_9_0_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd770 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd20 ;

  // register csrf_mepc_csr
  always@(MUX_csrf_mepc_csr$write_1__SEL_1 or
	  rob$deqPort_0_deq_data or
	  MUX_csrf_ie_vec_3$write_1__SEL_2 or
	  commitStage_commitTrap or
	  MUX_csrf_mepc_csr$write_1__SEL_3 or f_csr_reqs$D_OUT)
  case (1'b1)
    MUX_csrf_mepc_csr$write_1__SEL_1:
	csrf_mepc_csr$D_IN = rob$deqPort_0_deq_data[95:32];
    MUX_csrf_ie_vec_3$write_1__SEL_2:
	csrf_mepc_csr$D_IN = commitStage_commitTrap[164:101];
    MUX_csrf_mepc_csr$write_1__SEL_3:
	csrf_mepc_csr$D_IN = f_csr_reqs$D_OUT[63:0];
    default: csrf_mepc_csr$D_IN =
		 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
  endcase
  assign csrf_mepc_csr$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd833 ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 &&
	     NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd26 ;

  // register csrf_mideleg_11_reg
  assign csrf_mideleg_11_reg$D_IN =
	     MUX_csrf_mideleg_11_reg$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[11] :
	       MUX_csrf_stval_csr$write_1__VAL_1[11] ;
  assign csrf_mideleg_11_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd771 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd21 ;

  // register csrf_mideleg_1_0_reg
  assign csrf_mideleg_1_0_reg$D_IN =
	     MUX_csrf_mideleg_11_reg$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[1:0] :
	       MUX_csrf_stval_csr$write_1__VAL_1[1:0] ;
  assign csrf_mideleg_1_0_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd771 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd21 ;

  // register csrf_mideleg_5_3_reg
  assign csrf_mideleg_5_3_reg$D_IN =
	     MUX_csrf_mideleg_11_reg$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[5:3] :
	       MUX_csrf_stval_csr$write_1__VAL_1[5:3] ;
  assign csrf_mideleg_5_3_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd771 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd21 ;

  // register csrf_mideleg_9_7_reg
  assign csrf_mideleg_9_7_reg$D_IN =
	     MUX_csrf_mideleg_11_reg$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[9:7] :
	       MUX_csrf_stval_csr$write_1__VAL_1[9:7] ;
  assign csrf_mideleg_9_7_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd771 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd21 ;

  // register csrf_minstret_ehr_data_rl
  assign csrf_minstret_ehr_data_rl$D_IN =
	     csrf_minstret_ehr_data_lat_1$whas ?
	       upd__h3994 :
	       IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 ;
  assign csrf_minstret_ehr_data_rl$EN = 1'd1 ;

  // register csrf_mpp_reg
  always@(MUX_csrf_mpp_reg$write_1__SEL_1 or
	  MUX_csrf_mpp_reg$write_1__VAL_1 or
	  MUX_csrf_ie_vec_3$write_1__SEL_2 or
	  csrf_prv_reg or
	  MUX_csrf_ie_vec_3$write_1__SEL_3 or f_csr_reqs$D_OUT)
  case (1'b1)
    MUX_csrf_mpp_reg$write_1__SEL_1:
	csrf_mpp_reg$D_IN = MUX_csrf_mpp_reg$write_1__VAL_1;
    MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mpp_reg$D_IN = csrf_prv_reg;
    MUX_csrf_ie_vec_3$write_1__SEL_3:
	csrf_mpp_reg$D_IN = f_csr_reqs$D_OUT[12:11];
    default: csrf_mpp_reg$D_IN = 2'b10 /* unspecified value */ ;
  endcase
  assign csrf_mpp_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd768 ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 &&
	     NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ;

  // register csrf_mprv_reg
  assign csrf_mprv_reg$D_IN =
	     MUX_csrf_ie_vec_3$write_1__SEL_3 ?
	       f_csr_reqs$D_OUT[17] :
	       MUX_csrf_stval_csr$write_1__VAL_1[17] ;
  assign csrf_mprv_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd768 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd18 ;

  // register csrf_mscratch_csr
  assign csrf_mscratch_csr$D_IN =
	     MUX_csrf_mscratch_csr$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[63:0] :
	       rob$deqPort_0_deq_data[95:32] ;
  assign csrf_mscratch_csr$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd832 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd25 ;

  // register csrf_mtval_csr
  always@(MUX_csrf_mtval_csr$write_1__SEL_1 or
	  rob$deqPort_0_deq_data or
	  MUX_csrf_ie_vec_3$write_1__SEL_2 or
	  trap_val__h710453 or
	  MUX_csrf_mtval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT)
  case (1'b1)
    MUX_csrf_mtval_csr$write_1__SEL_1:
	csrf_mtval_csr$D_IN = rob$deqPort_0_deq_data[95:32];
    MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mtval_csr$D_IN = trap_val__h710453;
    MUX_csrf_mtval_csr$write_1__SEL_3:
	csrf_mtval_csr$D_IN = f_csr_reqs$D_OUT[63:0];
    default: csrf_mtval_csr$D_IN =
		 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
  endcase
  assign csrf_mtval_csr$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd835 ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 &&
	     NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd28 ;

  // register csrf_mtvec_base_hi_reg
  assign csrf_mtvec_base_hi_reg$D_IN =
	     MUX_csrf_mtvec_base_hi_reg$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[63:2] :
	       MUX_csrf_stval_csr$write_1__VAL_1[63:2] ;
  assign csrf_mtvec_base_hi_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd773 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd23 ;

  // register csrf_mtvec_mode_low_reg
  assign csrf_mtvec_mode_low_reg$D_IN =
	     MUX_csrf_mtvec_base_hi_reg$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[0] :
	       MUX_csrf_stval_csr$write_1__VAL_1[0] ;
  assign csrf_mtvec_mode_low_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd773 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd23 ;

  // register csrf_mxr_reg
  assign csrf_mxr_reg$D_IN =
	     MUX_csrf_ie_vec_0$write_1__SEL_1 ?
	       MUX_csrf_stval_csr$write_1__VAL_1[19] :
	       f_csr_reqs$D_OUT[19] ;
  assign csrf_mxr_reg$EN =
	     MUX_csrf_ie_vec_0$write_1__SEL_1 ||
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     (f_csr_reqs$D_OUT[75:64] == 12'd256 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd768) ;

  // register csrf_ppn_reg
  assign csrf_ppn_reg$D_IN =
	     MUX_csrf_ppn_reg$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[43:0] :
	       MUX_csrf_stval_csr$write_1__VAL_1[43:0] ;
  assign csrf_ppn_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd384 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd17 ;

  // register csrf_prev_ie_vec_0
  assign csrf_prev_ie_vec_0$D_IN =
	     MUX_csrf_ie_vec_0$write_1__SEL_1 ?
	       MUX_csrf_stval_csr$write_1__VAL_1[4] :
	       f_csr_reqs$D_OUT[4] ;
  assign csrf_prev_ie_vec_0$EN =
	     MUX_csrf_ie_vec_0$write_1__SEL_1 ||
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     (f_csr_reqs$D_OUT[75:64] == 12'd256 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd768) ;

  // register csrf_prev_ie_vec_1
  always@(MUX_csrf_prev_ie_vec_1$write_1__SEL_1 or
	  MUX_csrf_prev_ie_vec_1$write_1__VAL_1 or
	  MUX_csrf_ie_vec_1$write_1__SEL_2 or
	  csrf_ie_vec_1 or
	  MUX_csrf_ie_vec_0$write_1__SEL_2 or f_csr_reqs$D_OUT)
  case (1'b1)
    MUX_csrf_prev_ie_vec_1$write_1__SEL_1:
	csrf_prev_ie_vec_1$D_IN = MUX_csrf_prev_ie_vec_1$write_1__VAL_1;
    MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_prev_ie_vec_1$D_IN = csrf_ie_vec_1;
    MUX_csrf_ie_vec_0$write_1__SEL_2:
	csrf_prev_ie_vec_1$D_IN = f_csr_reqs$D_OUT[5];
    default: csrf_prev_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign csrf_prev_ie_vec_1$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 &&
	     csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 ||
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     (f_csr_reqs$D_OUT[75:64] == 12'd256 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd768) ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ;

  // register csrf_prev_ie_vec_3
  always@(MUX_csrf_prev_ie_vec_3$write_1__SEL_1 or
	  MUX_csrf_prev_ie_vec_3$write_1__VAL_1 or
	  MUX_csrf_ie_vec_3$write_1__SEL_2 or
	  csrf_ie_vec_3 or
	  MUX_csrf_ie_vec_3$write_1__SEL_3 or f_csr_reqs$D_OUT)
  case (1'b1)
    MUX_csrf_prev_ie_vec_3$write_1__SEL_1:
	csrf_prev_ie_vec_3$D_IN = MUX_csrf_prev_ie_vec_3$write_1__VAL_1;
    MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_prev_ie_vec_3$D_IN = csrf_ie_vec_3;
    MUX_csrf_ie_vec_3$write_1__SEL_3:
	csrf_prev_ie_vec_3$D_IN = f_csr_reqs$D_OUT[7];
    default: csrf_prev_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign csrf_prev_ie_vec_3$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd768 ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 &&
	     NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ;

  // register csrf_prv_reg
  always@(MUX_csrf_prv_reg$write_1__SEL_1 or
	  MUX_csrf_prv_reg$write_1__VAL_1 or
	  MUX_commitStage_rg_serial_num$write_1__SEL_1 or
	  x_prv__h713496 or
	  MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
  case (1'b1)
    MUX_csrf_prv_reg$write_1__SEL_1:
	csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_1;
    MUX_commitStage_rg_serial_num$write_1__SEL_1:
	csrf_prv_reg$D_IN = x_prv__h713496;
    MUX_csrf_prv_reg$write_1__SEL_3:
	csrf_prv_reg$D_IN = f_csr_reqs$D_OUT[1:0];
    default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ;
  endcase
  assign csrf_prv_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 ||
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd1968 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ;

  // register csrf_rg_dcsr
  always@(MUX_csrf_rg_dcsr$write_1__SEL_1 or
	  rob$deqPort_0_deq_data or
	  MUX_commitStage_rg_run_state$write_1__SEL_1 or
	  MUX_csrf_rg_dcsr$write_1__VAL_2 or
	  MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
  case (1'b1)
    MUX_csrf_rg_dcsr$write_1__SEL_1:
	csrf_rg_dcsr$D_IN = rob$deqPort_0_deq_data[95:32];
    MUX_commitStage_rg_run_state$write_1__SEL_1:
	csrf_rg_dcsr$D_IN = MUX_csrf_rg_dcsr$write_1__VAL_2;
    MUX_csrf_prv_reg$write_1__SEL_3:
	csrf_rg_dcsr$D_IN = f_csr_reqs$D_OUT[63:0];
    default: csrf_rg_dcsr$D_IN =
		 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
  endcase
  assign csrf_rg_dcsr$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 ||
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd1968 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd40 ;

  // register csrf_rg_dpc
  always@(MUX_csrf_rg_dpc$write_1__SEL_1 or
	  rob$deqPort_0_deq_data or
	  MUX_commitStage_rg_run_state$write_1__SEL_1 or
	  commitStage_commitTrap or
	  MUX_csrf_rg_dpc$write_1__SEL_3 or f_csr_reqs$D_OUT)
  case (1'b1)
    MUX_csrf_rg_dpc$write_1__SEL_1:
	csrf_rg_dpc$D_IN = rob$deqPort_0_deq_data[95:32];
    MUX_commitStage_rg_run_state$write_1__SEL_1:
	csrf_rg_dpc$D_IN = commitStage_commitTrap[164:101];
    MUX_csrf_rg_dpc$write_1__SEL_3: csrf_rg_dpc$D_IN = f_csr_reqs$D_OUT[63:0];
    default: csrf_rg_dpc$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
  endcase
  assign csrf_rg_dpc$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 ||
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd1969 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd41 ;

  // register csrf_rg_dscratch0
  assign csrf_rg_dscratch0$D_IN =
	     MUX_csrf_rg_dscratch0$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[63:0] :
	       rob$deqPort_0_deq_data[95:32] ;
  assign csrf_rg_dscratch0$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd1970 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd42 ;

  // register csrf_rg_dscratch1
  assign csrf_rg_dscratch1$D_IN =
	     MUX_csrf_rg_dscratch1$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[63:0] :
	       rob$deqPort_0_deq_data[95:32] ;
  assign csrf_rg_dscratch1$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd1971 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd43 ;

  // register csrf_rg_tdata1_data
  assign csrf_rg_tdata1_data$D_IN =
	     MUX_csrf_rg_tdata1_data$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[58:0] :
	       MUX_csrf_stval_csr$write_1__VAL_1[58:0] ;
  assign csrf_rg_tdata1_data$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd1953 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd37 ;

  // register csrf_rg_tdata1_dmode
  assign csrf_rg_tdata1_dmode$D_IN =
	     MUX_csrf_rg_tdata1_data$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[59] :
	       MUX_csrf_stval_csr$write_1__VAL_1[59] ;
  assign csrf_rg_tdata1_dmode$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd1953 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd37 ;

  // register csrf_rg_tdata2
  assign csrf_rg_tdata2$D_IN =
	     MUX_csrf_rg_tdata2$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[63:0] :
	       rob$deqPort_0_deq_data[95:32] ;
  assign csrf_rg_tdata2$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd1954 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd38 ;

  // register csrf_rg_tdata3
  assign csrf_rg_tdata3$D_IN =
	     MUX_csrf_rg_tdata3$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[63:0] :
	       rob$deqPort_0_deq_data[95:32] ;
  assign csrf_rg_tdata3$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd1955 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd39 ;

  // register csrf_rg_tselect
  assign csrf_rg_tselect$D_IN =
	     MUX_csrf_rg_tselect$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[63:0] :
	       rob$deqPort_0_deq_data[95:32] ;
  assign csrf_rg_tselect$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd1952 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd36 ;

  // register csrf_scause_code_reg
  always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or
	  MUX_csrf_stval_csr$write_1__VAL_1 or
	  MUX_csrf_ie_vec_1$write_1__SEL_2 or
	  cause_code__h710452 or
	  MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
  case (1'b1)
    MUX_csrf_scause_code_reg$write_1__SEL_1:
	csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0];
    MUX_csrf_ie_vec_1$write_1__SEL_2:
	csrf_scause_code_reg$D_IN = cause_code__h710452;
    MUX_csrf_scause_code_reg$write_1__SEL_3:
	csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0];
    default: csrf_scause_code_reg$D_IN = 4'b1010 /* unspecified value */ ;
  endcase
  assign csrf_scause_code_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd322 ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 &&
	     csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd14 ;

  // register csrf_scause_interrupt_reg
  always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or
	  MUX_csrf_stval_csr$write_1__VAL_1 or
	  MUX_csrf_ie_vec_1$write_1__SEL_2 or
	  commitStage_commitTrap or
	  MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
  case (1'b1)
    MUX_csrf_scause_code_reg$write_1__SEL_1:
	csrf_scause_interrupt_reg$D_IN =
	    MUX_csrf_stval_csr$write_1__VAL_1[63];
    MUX_csrf_ie_vec_1$write_1__SEL_2:
	csrf_scause_interrupt_reg$D_IN = commitStage_commitTrap[36];
    MUX_csrf_scause_code_reg$write_1__SEL_3:
	csrf_scause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63];
    default: csrf_scause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign csrf_scause_interrupt_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd322 ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 &&
	     csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd14 ;

  // register csrf_scounteren_cy_reg
  assign csrf_scounteren_cy_reg$D_IN =
	     MUX_csrf_scounteren_cy_reg$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[0] :
	       MUX_csrf_stval_csr$write_1__VAL_1[0] ;
  assign csrf_scounteren_cy_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd262 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd11 ;

  // register csrf_scounteren_ir_reg
  assign csrf_scounteren_ir_reg$D_IN =
	     MUX_csrf_scounteren_cy_reg$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[2] :
	       MUX_csrf_stval_csr$write_1__VAL_1[2] ;
  assign csrf_scounteren_ir_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd262 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd11 ;

  // register csrf_scounteren_tm_reg
  assign csrf_scounteren_tm_reg$D_IN =
	     MUX_csrf_scounteren_cy_reg$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[1] :
	       MUX_csrf_stval_csr$write_1__VAL_1[1] ;
  assign csrf_scounteren_tm_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd262 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd11 ;

  // register csrf_sepc_csr
  always@(MUX_csrf_sepc_csr$write_1__SEL_1 or
	  rob$deqPort_0_deq_data or
	  MUX_csrf_ie_vec_1$write_1__SEL_2 or
	  commitStage_commitTrap or
	  MUX_csrf_sepc_csr$write_1__SEL_3 or f_csr_reqs$D_OUT)
  case (1'b1)
    MUX_csrf_sepc_csr$write_1__SEL_1:
	csrf_sepc_csr$D_IN = rob$deqPort_0_deq_data[95:32];
    MUX_csrf_ie_vec_1$write_1__SEL_2:
	csrf_sepc_csr$D_IN = commitStage_commitTrap[164:101];
    MUX_csrf_sepc_csr$write_1__SEL_3:
	csrf_sepc_csr$D_IN = f_csr_reqs$D_OUT[63:0];
    default: csrf_sepc_csr$D_IN =
		 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
  endcase
  assign csrf_sepc_csr$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd321 ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 &&
	     csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd13 ;

  // register csrf_software_int_en_vec_0
  assign csrf_software_int_en_vec_0$D_IN = 1'b0 ;
  assign csrf_software_int_en_vec_0$EN = 1'b0 ;

  // register csrf_software_int_en_vec_1
  assign csrf_software_int_en_vec_1$D_IN =
	     MUX_csrf_external_int_en_vec_1$write_1__SEL_1 ?
	       MUX_csrf_stval_csr$write_1__VAL_1[1] :
	       f_csr_reqs$D_OUT[1] ;
  assign csrf_software_int_en_vec_1$EN =
	     MUX_csrf_external_int_en_vec_1$write_1__SEL_1 ||
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     (f_csr_reqs$D_OUT[75:64] == 12'd260 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd772) ;

  // register csrf_software_int_en_vec_3
  assign csrf_software_int_en_vec_3$D_IN =
	     MUX_csrf_external_int_en_vec_3$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[3] :
	       MUX_csrf_stval_csr$write_1__VAL_1[3] ;
  assign csrf_software_int_en_vec_3$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd772 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd22 ;

  // register csrf_software_int_pend_vec_0
  assign csrf_software_int_pend_vec_0$D_IN = 1'b0 ;
  assign csrf_software_int_pend_vec_0$EN = 1'b0 ;

  // register csrf_software_int_pend_vec_1
  assign csrf_software_int_pend_vec_1$D_IN =
	     MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ?
	       MUX_csrf_stval_csr$write_1__VAL_1[1] :
	       f_csr_reqs$D_OUT[1] ;
  assign csrf_software_int_pend_vec_1$EN =
	     MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ||
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     (f_csr_reqs$D_OUT[75:64] == 12'd324 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd836) ;

  // register csrf_software_int_pend_vec_3
  assign csrf_software_int_pend_vec_3$D_IN =
	     (mmio_pRqQ_data_0[37:36] == 2'd2) ?
	       mmio_pRqQ_data_0[0] :
	       amoExec___d880[0] ;
  assign csrf_software_int_pend_vec_3$EN =
	     WILL_FIRE_RL_mmio_handlePRq && !mmio_pRqQ_data_0[38] &&
	     mmio_pRqQ_data_0[37:36] != 2'd0 &&
	     mmio_pRqQ_data_0[37:36] != 2'd1 ;

  // register csrf_spp_reg
  always@(MUX_csrf_spp_reg$write_1__SEL_1 or
	  MUX_csrf_spp_reg$write_1__VAL_1 or
	  MUX_csrf_ie_vec_1$write_1__SEL_2 or
	  csrf_prv_reg or
	  MUX_csrf_ie_vec_0$write_1__SEL_2 or f_csr_reqs$D_OUT)
  case (1'b1)
    MUX_csrf_spp_reg$write_1__SEL_1:
	csrf_spp_reg$D_IN = MUX_csrf_spp_reg$write_1__VAL_1;
    MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_spp_reg$D_IN = csrf_prv_reg[0];
    MUX_csrf_ie_vec_0$write_1__SEL_2: csrf_spp_reg$D_IN = f_csr_reqs$D_OUT[8];
    default: csrf_spp_reg$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign csrf_spp_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 &&
	     csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 ||
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     (f_csr_reqs$D_OUT[75:64] == 12'd256 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd768) ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ;

  // register csrf_sscratch_csr
  assign csrf_sscratch_csr$D_IN =
	     MUX_csrf_sscratch_csr$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[63:0] :
	       rob$deqPort_0_deq_data[95:32] ;
  assign csrf_sscratch_csr$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd320 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd12 ;

  // register csrf_stats_module_doStats
  assign csrf_stats_module_doStats$D_IN = recvDoStats_x ;
  assign csrf_stats_module_doStats$EN = EN_recvDoStats ;

  // register csrf_stval_csr
  always@(MUX_csrf_stval_csr$write_1__SEL_1 or
	  rob$deqPort_0_deq_data or
	  MUX_csrf_ie_vec_1$write_1__SEL_2 or
	  trap_val__h710453 or
	  MUX_csrf_stval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT)
  case (1'b1)
    MUX_csrf_stval_csr$write_1__SEL_1:
	csrf_stval_csr$D_IN = rob$deqPort_0_deq_data[95:32];
    MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_stval_csr$D_IN = trap_val__h710453;
    MUX_csrf_stval_csr$write_1__SEL_3:
	csrf_stval_csr$D_IN = f_csr_reqs$D_OUT[63:0];
    default: csrf_stval_csr$D_IN =
		 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
  endcase
  assign csrf_stval_csr$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd323 ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 &&
	     csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd15 ;

  // register csrf_stvec_base_hi_reg
  assign csrf_stvec_base_hi_reg$D_IN =
	     MUX_csrf_stvec_base_hi_reg$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[63:2] :
	       MUX_csrf_stval_csr$write_1__VAL_1[63:2] ;
  assign csrf_stvec_base_hi_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd261 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd10 ;

  // register csrf_stvec_mode_low_reg
  assign csrf_stvec_mode_low_reg$D_IN =
	     MUX_csrf_stvec_base_hi_reg$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[0] :
	       MUX_csrf_stval_csr$write_1__VAL_1[0] ;
  assign csrf_stvec_mode_low_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd261 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd10 ;

  // register csrf_sum_reg
  assign csrf_sum_reg$D_IN =
	     MUX_csrf_ie_vec_0$write_1__SEL_1 ?
	       MUX_csrf_stval_csr$write_1__VAL_1[18] :
	       f_csr_reqs$D_OUT[18] ;
  assign csrf_sum_reg$EN =
	     MUX_csrf_ie_vec_0$write_1__SEL_1 ||
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     (f_csr_reqs$D_OUT[75:64] == 12'd256 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd768) ;

  // register csrf_time_reg
  assign csrf_time_reg$D_IN = mmioToPlatform_setTime_t ;
  assign csrf_time_reg$EN = EN_mmioToPlatform_setTime ;

  // register csrf_timer_int_en_vec_0
  assign csrf_timer_int_en_vec_0$D_IN = 1'b0 ;
  assign csrf_timer_int_en_vec_0$EN = 1'b0 ;

  // register csrf_timer_int_en_vec_1
  assign csrf_timer_int_en_vec_1$D_IN =
	     MUX_csrf_external_int_en_vec_1$write_1__SEL_1 ?
	       MUX_csrf_stval_csr$write_1__VAL_1[5] :
	       f_csr_reqs$D_OUT[5] ;
  assign csrf_timer_int_en_vec_1$EN =
	     MUX_csrf_external_int_en_vec_1$write_1__SEL_1 ||
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     (f_csr_reqs$D_OUT[75:64] == 12'd260 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd772) ;

  // register csrf_timer_int_en_vec_3
  assign csrf_timer_int_en_vec_3$D_IN =
	     MUX_csrf_external_int_en_vec_3$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[7] :
	       MUX_csrf_stval_csr$write_1__VAL_1[7] ;
  assign csrf_timer_int_en_vec_3$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd772 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd22 ;

  // register csrf_timer_int_pend_vec_0
  assign csrf_timer_int_pend_vec_0$D_IN = 1'b0 ;
  assign csrf_timer_int_pend_vec_0$EN = 1'b0 ;

  // register csrf_timer_int_pend_vec_1
  assign csrf_timer_int_pend_vec_1$D_IN =
	     MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ?
	       MUX_csrf_stval_csr$write_1__VAL_1[5] :
	       f_csr_reqs$D_OUT[5] ;
  assign csrf_timer_int_pend_vec_1$EN =
	     MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ||
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     (f_csr_reqs$D_OUT[75:64] == 12'd324 ||
	      f_csr_reqs$D_OUT[75:64] == 12'd836) ;

  // register csrf_timer_int_pend_vec_3
  assign csrf_timer_int_pend_vec_3$D_IN = mmio_pRqQ_data_0[0] ;
  assign csrf_timer_int_pend_vec_3$EN =
	     WILL_FIRE_RL_mmio_handlePRq && mmio_pRqQ_data_0[38] &&
	     mmio_pRqQ_data_0[37:36] == 2'd2 ;

  // register csrf_tsr_reg
  assign csrf_tsr_reg$D_IN =
	     MUX_csrf_ie_vec_3$write_1__SEL_3 ?
	       f_csr_reqs$D_OUT[22] :
	       MUX_csrf_stval_csr$write_1__VAL_1[22] ;
  assign csrf_tsr_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd768 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd18 ;

  // register csrf_tvm_reg
  assign csrf_tvm_reg$D_IN =
	     MUX_csrf_ie_vec_3$write_1__SEL_3 ?
	       f_csr_reqs$D_OUT[20] :
	       MUX_csrf_stval_csr$write_1__VAL_1[20] ;
  assign csrf_tvm_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd768 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd18 ;

  // register csrf_tw_reg
  assign csrf_tw_reg$D_IN =
	     MUX_csrf_ie_vec_3$write_1__SEL_3 ?
	       f_csr_reqs$D_OUT[21] :
	       MUX_csrf_stval_csr$write_1__VAL_1[21] ;
  assign csrf_tw_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd768 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd18 ;

  // register csrf_vm_mode_sv39_reg
  assign csrf_vm_mode_sv39_reg$D_IN =
	     MUX_csrf_ppn_reg$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[63] :
	       MUX_csrf_stval_csr$write_1__VAL_1[63] ;
  assign csrf_vm_mode_sv39_reg$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd384 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd17 ;

  // register flush_brpred
  assign flush_brpred$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ;
  assign flush_brpred$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 ||
	     WILL_FIRE_RL_flushBrPred ;

  // register flush_caches
  assign flush_caches$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ;
  assign flush_caches$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 ||
	     WILL_FIRE_RL_flushCaches ;

  // register flush_reservation
  assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_1 ;
  assign flush_reservation$EN =
	     WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst ;

  // register flush_tlbs
  assign flush_tlbs$D_IN = !MUX_flush_tlbs$write_1__SEL_1 ;
  assign flush_tlbs$EN =
	     WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     (rob$deqPort_0_deq_data[329:325] == 5'd16 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	      IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd17) ;

  // register mmio_cRqQ_clearReq_rl
  assign mmio_cRqQ_clearReq_rl$D_IN = 1'd0 ;
  assign mmio_cRqQ_clearReq_rl$EN = 1'd1 ;

  // register mmio_cRqQ_data_0
  assign mmio_cRqQ_data_0$D_IN =
	     { x__h46294,
	       (mmio_cRqQ_enqReq_lat_0$whas ?
		  mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd0 :
		  mmio_cRqQ_enqReq_rl[77:76] == 2'd0) ?
		 { 5'd2,
		   mmio_cRqQ_enqReq_lat_0$whas ?
		     mmio_cRqQ_enqReq_lat_0$wget[72] :
		     mmio_cRqQ_enqReq_rl[72] } :
		 IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463,
	       mmio_cRqQ_enqReq_lat_0$whas ?
		 mmio_cRqQ_enqReq_lat_0$wget[71:64] :
		 mmio_cRqQ_enqReq_rl[71:64],
	       x__h48830 } ;
  assign mmio_cRqQ_data_0$EN =
	     NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 &&
	     mmio_cRqQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 ;

  // register mmio_cRqQ_deqReq_rl
  assign mmio_cRqQ_deqReq_rl$D_IN = 1'd0 ;
  assign mmio_cRqQ_deqReq_rl$EN = 1'd1 ;

  // register mmio_cRqQ_empty
  assign mmio_cRqQ_empty$D_IN =
	     mmio_cRqQ_clearReq_dummy2_1$Q_OUT && mmio_cRqQ_clearReq_rl ||
	     NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452 ;
  assign mmio_cRqQ_empty$EN = 1'd1 ;

  // register mmio_cRqQ_enqReq_rl
  assign mmio_cRqQ_enqReq_rl$D_IN =
	     143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
  assign mmio_cRqQ_enqReq_rl$EN = 1'd1 ;

  // register mmio_cRqQ_full
  assign mmio_cRqQ_full$D_IN =
	     NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 &&
	     mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 ;
  assign mmio_cRqQ_full$EN = 1'd1 ;

  // register mmio_cRsQ_clearReq_rl
  assign mmio_cRsQ_clearReq_rl$D_IN = 1'd0 ;
  assign mmio_cRsQ_clearReq_rl$EN = 1'd1 ;

  // register mmio_cRsQ_data_0
  assign mmio_cRsQ_data_0$D_IN =
	     CAN_FIRE_RL_mmio_handlePRq ?
	       mmio_cRsQ_enqReq_lat_0$wget[0] :
	       mmio_cRsQ_enqReq_rl[0] ;
  assign mmio_cRsQ_data_0$EN =
	     NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 &&
	     mmio_cRsQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 ;

  // register mmio_cRsQ_deqReq_rl
  assign mmio_cRsQ_deqReq_rl$D_IN = 1'd0 ;
  assign mmio_cRsQ_deqReq_rl$EN = 1'd1 ;

  // register mmio_cRsQ_empty
  assign mmio_cRsQ_empty$D_IN =
	     mmio_cRsQ_clearReq_dummy2_1$Q_OUT && mmio_cRsQ_clearReq_rl ||
	     NOT_mmio_cRsQ_enqReq_dummy2_2_read__24_39_OR_I_ETC___d844 ;
  assign mmio_cRsQ_empty$EN = 1'd1 ;

  // register mmio_cRsQ_enqReq_rl
  assign mmio_cRsQ_enqReq_rl$D_IN = 2'b0 ;
  assign mmio_cRsQ_enqReq_rl$EN = 1'd1 ;

  // register mmio_cRsQ_full
  assign mmio_cRsQ_full$D_IN =
	     NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 &&
	     mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836 ;
  assign mmio_cRsQ_full$EN = 1'd1 ;

  // register mmio_dataPendQ_clearReq_rl
  assign mmio_dataPendQ_clearReq_rl$D_IN = 1'd0 ;
  assign mmio_dataPendQ_clearReq_rl$EN = 1'd1 ;

  // register mmio_dataPendQ_deqReq_rl
  assign mmio_dataPendQ_deqReq_rl$D_IN = 1'd0 ;
  assign mmio_dataPendQ_deqReq_rl$EN = 1'd1 ;

  // register mmio_dataPendQ_empty
  assign mmio_dataPendQ_empty$D_IN =
	     mmio_dataPendQ_clearReq_dummy2_1$Q_OUT &&
	     mmio_dataPendQ_clearReq_rl ||
	     NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 ;
  assign mmio_dataPendQ_empty$EN = 1'd1 ;

  // register mmio_dataPendQ_enqReq_rl
  assign mmio_dataPendQ_enqReq_rl$D_IN = 1'd0 ;
  assign mmio_dataPendQ_enqReq_rl$EN = 1'd1 ;

  // register mmio_dataPendQ_full
  assign mmio_dataPendQ_full$D_IN =
	     (!mmio_dataPendQ_clearReq_dummy2_1$Q_OUT ||
	      !mmio_dataPendQ_clearReq_rl) &&
	     mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312 ;
  assign mmio_dataPendQ_full$EN = 1'd1 ;

  // register mmio_dataReqQ_clearReq_rl
  assign mmio_dataReqQ_clearReq_rl$D_IN = 1'd0 ;
  assign mmio_dataReqQ_clearReq_rl$EN = 1'd1 ;

  // register mmio_dataReqQ_data_0
  assign mmio_dataReqQ_data_0$D_IN =
	     { x__h18387,
	       (mmio_dataReqQ_enqReq_lat_0$whas ?
		  mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd0 :
		  mmio_dataReqQ_enqReq_rl[77:76] == 2'd0) ?
		 { 5'd2,
		   mmio_dataReqQ_enqReq_lat_0$whas ?
		     mmio_dataReqQ_enqReq_lat_0$wget[72] :
		     mmio_dataReqQ_enqReq_rl[72] } :
		 IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172,
	       mmio_dataReqQ_enqReq_lat_0$whas ?
		 mmio_dataReqQ_enqReq_lat_0$wget[71:64] :
		 mmio_dataReqQ_enqReq_rl[71:64],
	       x__h20925 } ;
  assign mmio_dataReqQ_data_0$EN =
	     NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 &&
	     mmio_dataReqQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 ;

  // register mmio_dataReqQ_deqReq_rl
  assign mmio_dataReqQ_deqReq_rl$D_IN = 1'd0 ;
  assign mmio_dataReqQ_deqReq_rl$EN = 1'd1 ;

  // register mmio_dataReqQ_empty
  assign mmio_dataReqQ_empty$D_IN =
	     mmio_dataReqQ_clearReq_dummy2_1$Q_OUT &&
	     mmio_dataReqQ_clearReq_rl ||
	     NOT_mmio_dataReqQ_enqReq_dummy2_2_read__41_56__ETC___d161 ;
  assign mmio_dataReqQ_empty$EN = 1'd1 ;

  // register mmio_dataReqQ_enqReq_rl
  assign mmio_dataReqQ_enqReq_rl$D_IN =
	     143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
  assign mmio_dataReqQ_enqReq_rl$EN = 1'd1 ;

  // register mmio_dataReqQ_full
  assign mmio_dataReqQ_full$D_IN =
	     NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 &&
	     mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153 ;
  assign mmio_dataReqQ_full$EN = 1'd1 ;

  // register mmio_dataRespQ_clearReq_rl
  assign mmio_dataRespQ_clearReq_rl$D_IN = 1'd0 ;
  assign mmio_dataRespQ_clearReq_rl$EN = 1'd1 ;

  // register mmio_dataRespQ_data_0
  assign mmio_dataRespQ_data_0$D_IN =
	     CAN_FIRE_RL_mmio_sendDataResp ?
	       mmio_dataRespQ_enqReq_lat_0$wget[64:0] :
	       mmio_dataRespQ_enqReq_rl[64:0] ;
  assign mmio_dataRespQ_data_0$EN =
	     NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 &&
	     mmio_dataRespQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 ;

  // register mmio_dataRespQ_deqReq_rl
  assign mmio_dataRespQ_deqReq_rl$D_IN = 1'd0 ;
  assign mmio_dataRespQ_deqReq_rl$EN = 1'd1 ;

  // register mmio_dataRespQ_empty
  assign mmio_dataRespQ_empty$D_IN =
	     mmio_dataRespQ_clearReq_dummy2_1$Q_OUT &&
	     mmio_dataRespQ_clearReq_rl ||
	     NOT_mmio_dataRespQ_enqReq_dummy2_2_read__42_57_ETC___d262 ;
  assign mmio_dataRespQ_empty$EN = 1'd1 ;

  // register mmio_dataRespQ_enqReq_rl
  assign mmio_dataRespQ_enqReq_rl$D_IN = 66'h0AAAAAAAAAAAAAAAA ;
  assign mmio_dataRespQ_enqReq_rl$EN = 1'd1 ;

  // register mmio_dataRespQ_full
  assign mmio_dataRespQ_full$D_IN =
	     NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 &&
	     mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254 ;
  assign mmio_dataRespQ_full$EN = 1'd1 ;

  // register mmio_fromHostAddr
  assign mmio_fromHostAddr$D_IN = coreReq_start_fromHostAddr[63:3] ;
  assign mmio_fromHostAddr$EN = EN_coreReq_start ;

  // register mmio_pRqQ_clearReq_rl
  assign mmio_pRqQ_clearReq_rl$D_IN = 1'd0 ;
  assign mmio_pRqQ_clearReq_rl$EN = 1'd1 ;

  // register mmio_pRqQ_data_0
  assign mmio_pRqQ_data_0$D_IN =
	     { EN_mmioToPlatform_pRq_enq ?
		 mmio_pRqQ_enqReq_lat_0$wget[38] :
		 mmio_pRqQ_enqReq_rl[38],
	       (EN_mmioToPlatform_pRq_enq ?
		  mmio_pRqQ_enqReq_lat_0$wget[37:36] == 2'd0 :
		  mmio_pRqQ_enqReq_rl[37:36] == 2'd0) ?
		 { 5'd2,
		   EN_mmioToPlatform_pRq_enq ?
		     mmio_pRqQ_enqReq_lat_0$wget[32] :
		     mmio_pRqQ_enqReq_rl[32] } :
		 IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766,
	       x_data__h66088 } ;
  assign mmio_pRqQ_data_0$EN =
	     NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 &&
	     mmio_pRqQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 ;

  // register mmio_pRqQ_deqReq_rl
  assign mmio_pRqQ_deqReq_rl$D_IN = 1'd0 ;
  assign mmio_pRqQ_deqReq_rl$EN = 1'd1 ;

  // register mmio_pRqQ_empty
  assign mmio_pRqQ_empty$D_IN =
	     mmio_pRqQ_clearReq_dummy2_1$Q_OUT && mmio_pRqQ_clearReq_rl ||
	     NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755 ;
  assign mmio_pRqQ_empty$EN = 1'd1 ;

  // register mmio_pRqQ_enqReq_rl
  assign mmio_pRqQ_enqReq_rl$D_IN = 40'h2AAAAAAAAA ;
  assign mmio_pRqQ_enqReq_rl$EN = 1'd1 ;

  // register mmio_pRqQ_full
  assign mmio_pRqQ_full$D_IN =
	     NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 &&
	     mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747 ;
  assign mmio_pRqQ_full$EN = 1'd1 ;

  // register mmio_pRsQ_clearReq_rl
  assign mmio_pRsQ_clearReq_rl$D_IN = 1'd0 ;
  assign mmio_pRsQ_clearReq_rl$EN = 1'd1 ;

  // register mmio_pRsQ_data_0
  assign mmio_pRsQ_data_0$D_IN =
	     { EN_mmioToPlatform_pRs_enq ?
		 mmio_pRsQ_enqReq_lat_0$wget[66] :
		 mmio_pRsQ_enqReq_rl[66],
	       IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627 } ;
  assign mmio_pRsQ_data_0$EN =
	     NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 &&
	     mmio_pRsQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 ;

  // register mmio_pRsQ_deqReq_rl
  assign mmio_pRsQ_deqReq_rl$D_IN = 1'd0 ;
  assign mmio_pRsQ_deqReq_rl$EN = 1'd1 ;

  // register mmio_pRsQ_empty
  assign mmio_pRsQ_empty$D_IN =
	     mmio_pRsQ_clearReq_dummy2_1$Q_OUT && mmio_pRsQ_clearReq_rl ||
	     NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614 ;
  assign mmio_pRsQ_empty$EN = 1'd1 ;

  // register mmio_pRsQ_enqReq_rl
  assign mmio_pRsQ_enqReq_rl$D_IN = 68'h2AAAAAAAAAAAAAAAA ;
  assign mmio_pRsQ_enqReq_rl$EN = 1'd1 ;

  // register mmio_pRsQ_full
  assign mmio_pRsQ_full$D_IN =
	     NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 &&
	     mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606 ;
  assign mmio_pRsQ_full$EN = 1'd1 ;

  // register mmio_toHostAddr
  assign mmio_toHostAddr$D_IN = coreReq_start_toHostAddr[63:3] ;
  assign mmio_toHostAddr$EN = EN_coreReq_start ;

  // register outOfReset
  assign outOfReset$D_IN = 1'd1 ;
  assign outOfReset$EN = CAN_FIRE_RL_rl_outOfReset ;

  // register renameStage_rg_m_halt_req
  always@(MUX_renameStage_rg_m_halt_req$write_1__SEL_1 or
	  MUX_renameStage_rg_m_halt_req$write_1__SEL_2 or
	  MUX_renameStage_rg_m_halt_req$write_1__SEL_3 or
	  WILL_FIRE_RL_rl_debug_resume or
	  WILL_FIRE_RL_rl_debug_halt_req or
	  MUX_renameStage_rg_m_halt_req$write_1__SEL_6)
  case (1'b1)
    MUX_renameStage_rg_m_halt_req$write_1__SEL_1 ||
    MUX_renameStage_rg_m_halt_req$write_1__SEL_2 ||
    MUX_renameStage_rg_m_halt_req$write_1__SEL_3:
	renameStage_rg_m_halt_req$D_IN = 5'd31;
    WILL_FIRE_RL_rl_debug_resume: renameStage_rg_m_halt_req$D_IN = 5'd10;
    WILL_FIRE_RL_rl_debug_halt_req ||
    MUX_renameStage_rg_m_halt_req$write_1__SEL_6:
	renameStage_rg_m_halt_req$D_IN = 5'd30;
    default: renameStage_rg_m_halt_req$D_IN =
		 5'b01010 /* unspecified value */ ;
  endcase
  assign renameStage_rg_m_halt_req$EN =
	     (WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
	      WILL_FIRE_RL_renameStage_doRenaming_Trap) &&
	     csrf_rg_dcsr[2] ||
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 &&
	     csrf_rg_dcsr[2] ||
	     EN_coreReq_start && !coreReq_start_running ||
	     WILL_FIRE_RL_rl_debug_resume ||
	     WILL_FIRE_RL_rl_debug_halt_req ;

  // register rg_core_run_state
  always@(WILL_FIRE_RL_rl_debug_resume or
	  WILL_FIRE_RL_rl_debug_halted or
	  EN_coreReq_start or MUX_rg_core_run_state$write_1__SEL_4)
  case (1'b1)
    WILL_FIRE_RL_rl_debug_resume: rg_core_run_state$D_IN = 2'd2;
    WILL_FIRE_RL_rl_debug_halted: rg_core_run_state$D_IN = 2'd1;
    EN_coreReq_start: rg_core_run_state$D_IN = 2'd2;
    MUX_rg_core_run_state$write_1__SEL_4: rg_core_run_state$D_IN = 2'd0;
    default: rg_core_run_state$D_IN = 2'b10 /* unspecified value */ ;
  endcase
  assign rg_core_run_state$EN =
	     WILL_FIRE_RL_readyToFetch && commitStage_rg_run_state ||
	     WILL_FIRE_RL_rl_debug_halted ||
	     WILL_FIRE_RL_rl_debug_resume ||
	     EN_coreReq_start ;

  // register started
  assign started$D_IN = WILL_FIRE_RL_rl_debug_resume || EN_coreReq_start ;
  assign started$EN =
	     WILL_FIRE_RL_readyToFetch && commitStage_rg_run_state ||
	     WILL_FIRE_RL_rl_debug_resume ||
	     EN_coreReq_start ;

  // register update_vm_info
  assign update_vm_info$D_IN =
	     !MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ;
  assign update_vm_info$EN =
	     WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst ;

  // submodule commitStage_f_rob_data
  assign commitStage_f_rob_data$D_IN =
	     { rob$deqPort_0_deq_data[425:182],
	       rob_deqPort_0_deq_data__4354_BIT_181_4429_CONC_ETC___d14520,
	       rob$deqPort_0_deq_data[168:167],
	       rob_deqPort_0_deq_data__4354_BIT_166_4370_CONC_ETC___d14419,
	       rob$deqPort_0_deq_data[161:98],
	       IF_rob_deqPort_0_deq_data__4354_BITS_97_TO_96__ETC___d14527,
	       rob$deqPort_0_deq_data[31:0] } ;
  assign commitStage_f_rob_data$ENQ =
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign commitStage_f_rob_data$DEQ =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle ;
  assign commitStage_f_rob_data$CLR = 1'b0 ;

  // submodule coreFix_aluExe_0_dispToRegQ
  assign coreFix_aluExe_0_dispToRegQ$enq_x =
	     { coreFix_aluExe_0_rsAlu$dispatchData[161:157],
	       CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q282,
	       coreFix_aluExe_0_rsAlu$dispatchData[135],
	       CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q283,
	       coreFix_aluExe_0_rsAlu$dispatchData[122:90],
	       coreFix_aluExe_0_rsAlu$dispatchData[65:21],
	       coreFix_aluExe_0_rsAlu$dispatchData[89:66],
	       coreFix_aluExe_0_rsAlu$dispatchData[8:4],
	       coreFix_aluExe_0_rsAlu$dispatchData[20:9] } ;
  assign coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_0_dispToRegQ$EN_enq =
	     WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ;
  assign coreFix_aluExe_0_dispToRegQ$EN_deq =
	     WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu ;
  assign coreFix_aluExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_aluExe_0_dispToRegQ$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_aluExe_0_exeToFinQ
  assign coreFix_aluExe_0_exeToFinQ$enq_x =
	     { coreFix_aluExe_0_regToExeQ$first[421:417],
	       coreFix_aluExe_0_regToExeQ$first[349:305],
	       coreFix_aluExe_0_regToExeQ$first[18:17] != 2'b11,
	       basicExec___d12617[321:258],
	       coreFix_aluExe_0_regToExeQ$first[395],
	       basicExec___d12617[257:194],
	       basicExec___d12617[129:0],
	       coreFix_aluExe_0_regToExeQ$first[16:0] } ;
  assign coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_0_exeToFinQ$EN_enq =
	     WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu ;
  assign coreFix_aluExe_0_exeToFinQ$EN_deq =
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
  assign coreFix_aluExe_0_exeToFinQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_aluExe_0_exeToFinQ$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_aluExe_0_regToExeQ
  assign coreFix_aluExe_0_regToExeQ$enq_x =
	     { coreFix_aluExe_0_dispToRegQ$first[157:153],
	       CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q285,
	       coreFix_aluExe_0_dispToRegQ$first[131],
	       CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q286,
	       coreFix_aluExe_0_dispToRegQ$first[118:86],
	       coreFix_aluExe_0_dispToRegQ$first[61:17],
	       x__h639746,
	       x__h639747,
	       rob$getOrigPC_0_get,
	       rob$getOrigPredPC_0_get,
	       rob$getOrig_Inst_0_get,
	       coreFix_aluExe_0_dispToRegQ$first[16:0] } ;
  assign coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_0_regToExeQ$EN_enq =
	     WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu ;
  assign coreFix_aluExe_0_regToExeQ$EN_deq =
	     WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu ;
  assign coreFix_aluExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_aluExe_0_regToExeQ$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_aluExe_0_rsAlu
  assign coreFix_aluExe_0_rsAlu$enq_x =
	     MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 ?
	       MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 :
	       MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 ;
  assign coreFix_aluExe_0_rsAlu$setRegReady_0_put =
	     { 1'd1, coreFix_aluExe_0_rsAlu$dispatchData[40:34] } ;
  assign coreFix_aluExe_0_rsAlu$setRegReady_1_put =
	     { 1'd1, coreFix_aluExe_1_rsAlu$dispatchData[40:34] } ;
  always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
	  coreFix_aluExe_0_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
	  coreFix_aluExe_0_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
	  coreFix_aluExe_0_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
	  coreFix_aluExe_0_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
	  coreFix_aluExe_0_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
	  coreFix_aluExe_0_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
      default: coreFix_aluExe_0_rsAlu$setRegReady_2_put =
		   8'b10101010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_0_rsAlu$setRegReady_3_put =
	     { 1'd1, coreFix_memExe_lsq$issueLd[71:65] } ;
  always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1:
	  coreFix_aluExe_0_rsAlu$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2:
	  coreFix_aluExe_0_rsAlu$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
	  coreFix_aluExe_0_rsAlu$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
	  coreFix_aluExe_0_rsAlu$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
      default: coreFix_aluExe_0_rsAlu$setRegReady_4_put =
		   8'b10101010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_0_rsAlu$setRobEnqTime_t = rob$getEnqTime ;
  assign coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_0_rsAlu$EN_enq =
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	     fetchStage$pipelines_0_first[194:192] == 3'd0 ||
	     WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ;
  assign coreFix_aluExe_0_rsAlu$EN_setRobEnqTime = 1'd1 ;
  assign coreFix_aluExe_0_rsAlu$EN_doDispatch =
	     WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ;
  assign coreFix_aluExe_0_rsAlu$EN_setRegReady_0_put =
	     WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
	     coreFix_aluExe_0_rsAlu$dispatchData[41] ;
  assign coreFix_aluExe_0_rsAlu$EN_setRegReady_1_put =
	     WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
	     coreFix_aluExe_1_rsAlu$dispatchData[41] ;
  assign coreFix_aluExe_0_rsAlu$EN_setRegReady_2_put =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
  assign coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put =
	     _dor1coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
	     coreFix_memExe_lsq$issueLd[72] ;
  assign coreFix_aluExe_0_rsAlu$EN_setRegReady_4_put =
	     (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
	     coreFix_memExe_lsq$firstSt[150] ||
	     (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
	     coreFix_memExe_lsq$firstLd[89] ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2622 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 &&
	     coreFix_memExe_lsq$getHit[8] &&
	     !coreFix_memExe_lsq$getHit[9] ;
  assign coreFix_aluExe_0_rsAlu$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_aluExe_0_rsAlu$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_aluExe_1_dispToRegQ
  assign coreFix_aluExe_1_dispToRegQ$enq_x =
	     { coreFix_aluExe_1_rsAlu$dispatchData[161:157],
	       CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q288,
	       coreFix_aluExe_1_rsAlu$dispatchData[135],
	       CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q289,
	       coreFix_aluExe_1_rsAlu$dispatchData[122:90],
	       coreFix_aluExe_1_rsAlu$dispatchData[65:21],
	       coreFix_aluExe_1_rsAlu$dispatchData[89:66],
	       coreFix_aluExe_1_rsAlu$dispatchData[8:4],
	       coreFix_aluExe_1_rsAlu$dispatchData[20:9] } ;
  assign coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_1_dispToRegQ$EN_enq =
	     WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu ;
  assign coreFix_aluExe_1_dispToRegQ$EN_deq =
	     WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu ;
  assign coreFix_aluExe_1_dispToRegQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_aluExe_1_dispToRegQ$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_aluExe_1_exeToFinQ
  assign coreFix_aluExe_1_exeToFinQ$enq_x =
	     { coreFix_aluExe_1_regToExeQ$first[421:417],
	       coreFix_aluExe_1_regToExeQ$first[349:305],
	       coreFix_aluExe_1_regToExeQ$first[18:17] != 2'b11,
	       basicExec___d11943[321:258],
	       coreFix_aluExe_1_regToExeQ$first[395],
	       basicExec___d11943[257:194],
	       basicExec___d11943[129:0],
	       coreFix_aluExe_1_regToExeQ$first[16:0] } ;
  assign coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_1_exeToFinQ$EN_enq =
	     WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu ;
  assign coreFix_aluExe_1_exeToFinQ$EN_deq =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
  assign coreFix_aluExe_1_exeToFinQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_aluExe_1_exeToFinQ$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_aluExe_1_regToExeQ
  assign coreFix_aluExe_1_regToExeQ$enq_x =
	     { coreFix_aluExe_1_dispToRegQ$first[157:153],
	       CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q291,
	       coreFix_aluExe_1_dispToRegQ$first[131],
	       CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q292,
	       coreFix_aluExe_1_dispToRegQ$first[118:86],
	       coreFix_aluExe_1_dispToRegQ$first[61:17],
	       x__h617237,
	       x__h617238,
	       rob$getOrigPC_1_get,
	       rob$getOrigPredPC_1_get,
	       rob$getOrig_Inst_1_get,
	       coreFix_aluExe_1_dispToRegQ$first[16:0] } ;
  assign coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_1_regToExeQ$EN_enq =
	     WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu ;
  assign coreFix_aluExe_1_regToExeQ$EN_deq =
	     WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu ;
  assign coreFix_aluExe_1_regToExeQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_aluExe_1_regToExeQ$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_aluExe_1_rsAlu
  assign coreFix_aluExe_1_rsAlu$enq_x =
	     (k__h670634 == 1'd1 &&
	      fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14115) ?
	       { fetchStage$pipelines_0_first[199:195],
		 IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883,
		 fetchStage$pipelines_0_first[173],
		 IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973,
		 fetchStage$pipelines_0_first[160:128],
		 fetchStage$pipelines_0_first[255:232],
		 regRenamingTable$rename_0_getRename,
		 rob$enqPort_0_getEnqInstTag,
		 specTagManager$currentSpecBits,
		 fetchStage$pipelines_0_first[194:192] == 3'd1,
		 specTagManager$nextSpecTag,
		 sbAggr$eagerLookup_0_get } :
	       { fetchStage$pipelines_1_first[199:195],
		 IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599,
		 fetchStage_pipelines_1_first__2766_BIT_173_360_ETC___d13691,
		 fetchStage$pipelines_1_first[160:128],
		 fetchStage$pipelines_1_first[255:232],
		 regRenamingTable$rename_1_getRename,
		 rob$enqPort_1_getEnqInstTag,
		 renaming_spec_bits__h686248,
		 fetchStage$pipelines_1_first[194:192] == 3'd1,
		 specTagManager$nextSpecTag,
		 sbAggr$eagerLookup_1_get } ;
  assign coreFix_aluExe_1_rsAlu$setRegReady_0_put =
	     coreFix_aluExe_0_rsAlu$setRegReady_0_put ;
  assign coreFix_aluExe_1_rsAlu$setRegReady_1_put =
	     coreFix_aluExe_0_rsAlu$setRegReady_1_put ;
  always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
	  coreFix_aluExe_1_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
	  coreFix_aluExe_1_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
	  coreFix_aluExe_1_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
	  coreFix_aluExe_1_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
	  coreFix_aluExe_1_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
	  coreFix_aluExe_1_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
      default: coreFix_aluExe_1_rsAlu$setRegReady_2_put =
		   8'b10101010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_1_rsAlu$setRegReady_3_put =
	     coreFix_aluExe_0_rsAlu$setRegReady_3_put ;
  always@(MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
	  MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1:
	  coreFix_aluExe_1_rsAlu$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
      MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2:
	  coreFix_aluExe_1_rsAlu$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
	  coreFix_aluExe_1_rsAlu$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
	  coreFix_aluExe_1_rsAlu$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
      default: coreFix_aluExe_1_rsAlu$setRegReady_4_put =
		   8'b10101010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_1_rsAlu$setRobEnqTime_t = rob$getEnqTime ;
  assign coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_1_rsAlu$EN_enq =
	     WILL_FIRE_RL_renameStage_doRenaming && _dfoo16 ;
  assign coreFix_aluExe_1_rsAlu$EN_setRobEnqTime = 1'd1 ;
  assign coreFix_aluExe_1_rsAlu$EN_doDispatch =
	     WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu ;
  assign coreFix_aluExe_1_rsAlu$EN_setRegReady_0_put =
	     WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
	     coreFix_aluExe_0_rsAlu$dispatchData[41] ;
  assign coreFix_aluExe_1_rsAlu$EN_setRegReady_1_put =
	     WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
	     coreFix_aluExe_1_rsAlu$dispatchData[41] ;
  assign coreFix_aluExe_1_rsAlu$EN_setRegReady_2_put =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
  assign coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put =
	     _dor1coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
	     coreFix_memExe_lsq$issueLd[72] ;
  assign coreFix_aluExe_1_rsAlu$EN_setRegReady_4_put =
	     (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
	     coreFix_memExe_lsq$firstSt[150] ||
	     (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
	     coreFix_memExe_lsq$firstLd[89] ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2622 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 &&
	     coreFix_memExe_lsq$getHit[8] &&
	     !coreFix_memExe_lsq$getHit[9] ;
  assign coreFix_aluExe_1_rsAlu$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_aluExe_1_rsAlu$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_fpuMulDivExe_0_dispToRegQ
  assign coreFix_fpuMulDivExe_0_dispToRegQ$enq_x =
	     { CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q294,
	       coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[65:9] } ;
  assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_enq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv ;
  assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_deq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv ;
  assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_correctSpeculation =
	     1'd1 ;

  // submodule coreFix_fpuMulDivExe_0_fpuExec_divQ
  assign coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x =
	     { IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717,
	       coreFix_fpuMulDivExe_0_regToExeQ$first[225],
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10854,
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10890,
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10938,
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10980,
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d11022,
	       coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
	       coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28,
	       coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
	       coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
  assign coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_enq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd3 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_deq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv ;
  assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_correctSpeculation =
	     1'd1 ;

  // submodule coreFix_fpuMulDivExe_0_fpuExec_double_div
  assign coreFix_fpuMulDivExe_0_fpuExec_double_div$request_put =
	     { IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9174,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10654,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 } ;
  assign coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_request_put =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd3 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_response_get =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv ;

  // submodule coreFix_fpuMulDivExe_0_fpuExec_double_fma
  assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put =
	     { coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd2,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9944,
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q295,
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q296,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 } ;
  assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd1 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd2 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) ;
  assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_response_get =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma ;

  // submodule coreFix_fpuMulDivExe_0_fpuExec_double_sqrt
  assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$request_put =
	     { IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9174,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 } ;
  assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_request_put =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd4 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_response_get =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt ;

  // submodule coreFix_fpuMulDivExe_0_fpuExec_fmaQ
  assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x =
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x ;
  assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_enq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd1 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd2 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) ;
  assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_deq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma ;
  assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_correctSpeculation =
	     1'd1 ;

  // submodule coreFix_fpuMulDivExe_0_fpuExec_simpleQ
  assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$enq_x =
	     { execFpuSimple___d11056,
	       coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
	       coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
  assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_enq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd0 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd1 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd2 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd25 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd26 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd27 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd28 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd3 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd4 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_deq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
  assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_correctSpeculation =
	     1'd1 ;

  // submodule coreFix_fpuMulDivExe_0_fpuExec_sqrtQ
  assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x =
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x ;
  assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_enq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd4 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_deq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt ;
  assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_correctSpeculation =
	     1'd1 ;

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_divQ
  assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$enq_x =
	     { coreFix_fpuMulDivExe_0_regToExeQ$first[229:227],
	       coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
	       coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_enq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_deq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_correctSpeculation =
	     1'd1 ;

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ?
	       _theResult___fst__h603372 :
	       a__h602950 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser =
	     { b__h602951 == 64'd0,
	       a__h602950,
	       coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0,
	       x__h603386,
	       a__h602950[63],
	       8'd0 } ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ?
	       _theResult___snd__h603373 :
	       b__h602951 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tvalid =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tready =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv ;

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulQ
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$enq_x =
	     { coreFix_fpuMulDivExe_0_regToExeQ$first[229:227],
	       coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
	       coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_enq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_deq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_correctSpeculation =
	     1'd1 ;

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h602950 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h602951 ;

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A =
	     a__h602950 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B =
	     b__h602951 ;

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A =
	     a__h602950 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B =
	     b__h602951 ;

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ
  always@(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 or
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$P or
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$P or
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$P)
  begin
    case (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1[1:0])
      2'd0:
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN =
	      coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$P;
      2'd1:
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN =
	      coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$P;
      default: coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN =
		   coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$P;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$ENQ =
	     coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1[2] ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$DEQ =
	     coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$CLR = 1'b0 ;

  // submodule coreFix_fpuMulDivExe_0_regToExeQ
  assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x =
	     { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298,
	       coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12],
	       x__h481672,
	       x__h481673,
	       x__h481674,
	       coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ;
  assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_regToExeQ$EN_enq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv ;
  assign coreFix_fpuMulDivExe_0_regToExeQ$EN_deq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ;
  assign coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_correctSpeculation =
	     1'd1 ;

  // submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x =
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3418_AND__ETC___d14127) ?
	       { IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883,
		 regRenamingTable$rename_0_getRename,
		 rob$enqPort_0_getEnqInstTag,
		 specTagManager$currentSpecBits,
		 fetchStage$pipelines_0_first[194:192] == 3'd1,
		 specTagManager$nextSpecTag,
		 sbAggr$eagerLookup_0_get } :
	       { IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599,
		 regRenamingTable$rename_1_getRename,
		 rob$enqPort_1_getEnqInstTag,
		 renaming_spec_bits__h686248,
		 fetchStage$pipelines_1_first[194:192] == 3'd1,
		 specTagManager$nextSpecTag,
		 sbAggr$eagerLookup_1_get } ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_0_put =
	     coreFix_aluExe_0_rsAlu$setRegReady_0_put ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_1_put =
	     coreFix_aluExe_0_rsAlu$setRegReady_1_put ;
  always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
      default: coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
		   8'b10101010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_3_put =
	     coreFix_aluExe_0_rsAlu$setRegReady_3_put ;
  always@(MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
	  MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
      MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
      default: coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
		   8'b10101010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t = rob$getEnqTime ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq =
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3418_AND__ETC___d14127 ||
	      NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 &&
	      regRenamingTable_rename_1_canRename__3545_AND__ETC___d14263) ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime = 1'd1 ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_0_put =
	     WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
	     coreFix_aluExe_0_rsAlu$dispatchData[41] ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_1_put =
	     WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
	     coreFix_aluExe_1_rsAlu$dispatchData[41] ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_2_put =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put =
	     _dor1coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
	     coreFix_memExe_lsq$issueLd[72] ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_4_put =
	     (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
	     coreFix_memExe_lsq$firstSt[150] ||
	     (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
	     coreFix_memExe_lsq$firstLd[89] ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2622 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 &&
	     coreFix_memExe_lsq$getHit[8] &&
	     !coreFix_memExe_lsq$getHit[9] ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_correctSpeculation =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r =
	     { x__h287281,
	       x__h287293,
	       IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789,
	       IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2793,
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2797,
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2801,
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2805,
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2810,
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2814,
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819,
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2823,
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2828,
	       x__h289147,
	       IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2836,
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840,
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844,
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2848 } ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n =
	     x__h285848 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n =
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] ==
	      2'd0) ?
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] :
	       (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] :
		  3'd0) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n =
	     3'h0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ;
  always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1 or
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
	  coreFix_memExe_dMem_cache_m_banks_0_processAmo)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1:
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574];
      MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2:
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512];
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
	      coreFix_memExe_dMem_cache_m_banks_0_processAmo[159:157];
      default: coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
		   3'b010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain_addr =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:84] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d =
	     { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
	       2'd3,
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_n =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_n =
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ?
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] :
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot =
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ?
	       MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1 :
	       MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_state =
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ?
	       MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1 :
	       3'd3 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_n =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[2:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_succ =
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq_n =
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot_n =
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData_n =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq_n =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot_n =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState_n =
	     3'h0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_n =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_slot =
	     { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[57:55],
	       55'h15555555555555 } ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_cRqTransfer_getEmptyEntryInit =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_sendRsToP_cRq_setWaitSt_setSlot_clearData =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_releaseEntry =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2599 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	     3'd4 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setData =
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setStateSlot =
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2697 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2700 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setSucc =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
	      3'd1) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_stuck_get = 1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN =
	     EN_dCacheToParent_fromP_enq ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2582 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd2 ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd3) ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2727 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] ==
	     2'd0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN =
	     MUX_flush_reservation$write_1__SEL_1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r =
	     { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2875,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299 } ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n =
	     2'h0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_releaseEntry_n =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d =
	     { !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
	       2'd3,
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_n =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData_n =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[1:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq_n =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[1:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_releaseEntry_n =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[1:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_getEmptyEntryInit =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_sendRsToP_pRq_releaseEntry =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_releaseEntry =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] ||
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2697 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2700) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_setDone_setData =
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_stuck_get = 1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_pipeline
  always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
	  coreFix_memExe_dMem_cache_m_banks_0_processAmo or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1;
      MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc;
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
	      coreFix_memExe_dMem_cache_m_banks_0_processAmo[3:0];
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq = 4'd2;
      default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1 or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1;
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
	      1'd0;
      MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 ||
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
	      1'd1;
      default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
		   1'b0 /* unspecified value */ ;
    endcase
  end
  always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2 or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3 or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1;
      MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2;
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3;
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4;
      default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
		   570'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  always@(WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1;
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2;
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3;
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4;
      default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
		   584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_send =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_deqWrite =
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	     3'd4 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_IN =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ?
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_OUT :
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_OUT ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$ENQ =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$DEQ =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$CLR = 1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$ENQ =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2651 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	      (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	       3'd1) &&
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2655) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$DEQ =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$CLR =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$ENQ =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$DEQ =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$CLR =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN =
	     EN_dCacheToParent_rqToP_deq ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_IN =
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 ?
	       MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 :
	       MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$ENQ =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2697 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2700 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2666 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$DEQ =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$CLR = 1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN =
	     EN_dCacheToParent_rsToP_deq ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0
  assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1
  assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0
  assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN = 1'b0 ;
  assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN = 1'b0 ;

  // submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1
  assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2
  assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0
  assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN = 1'b0 ;
  assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN = 1'b0 ;

  // submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1
  assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2
  assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule coreFix_memExe_dTlb
  assign coreFix_memExe_dTlb$perf_req_r = 3'h0 ;
  assign coreFix_memExe_dTlb$perf_setStatus_doStats = 1'b0 ;
  assign coreFix_memExe_dTlb$procReq_req =
	     { coreFix_memExe_regToExeQ$first[192:190],
	       coreFix_memExe_regToExeQ$first[157:140],
	       coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d1706,
	       coreFix_memExe_regToExeQ$first[11:0] } ;
  assign coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_dTlb$toParent_ldTransRsFromP_enq_x =
	     { l2Tlb$toChildren_rsToC_first[80:0],
	       l2Tlb$toChildren_rsToC_first[82:81] } ;
  assign coreFix_memExe_dTlb$updateVMInfo_vm =
	     MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ?
	       MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 :
	       MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 ;
  assign coreFix_memExe_dTlb$EN_flush =
	     WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ||
	     WILL_FIRE_RL_rl_debug_resume ;
  assign coreFix_memExe_dTlb$EN_updateVMInfo =
	     WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ||
	     WILL_FIRE_RL_rl_debug_resume ;
  assign coreFix_memExe_dTlb$EN_procReq =
	     CAN_FIRE_RL_coreFix_memExe_doExeMem ;
  assign coreFix_memExe_dTlb$EN_deqProcResp =
	     CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
  assign coreFix_memExe_dTlb$EN_toParent_rqToP_deq = CAN_FIRE_RL_sendDTlbReq ;
  assign coreFix_memExe_dTlb$EN_toParent_ldTransRsFromP_enq =
	     CAN_FIRE_RL_sendRsToDTlb ;
  assign coreFix_memExe_dTlb$EN_toParent_flush_request_get =
	     CAN_FIRE_RL_mkConnectionGetPut ;
  assign coreFix_memExe_dTlb$EN_toParent_flush_response_put =
	     CAN_FIRE_RL_sendFlushDone ;
  assign coreFix_memExe_dTlb$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_memExe_dTlb$EN_specUpdate_correctSpeculation = 1'd1 ;
  assign coreFix_memExe_dTlb$EN_perf_setStatus = 1'b0 ;
  assign coreFix_memExe_dTlb$EN_perf_req = 1'b0 ;
  assign coreFix_memExe_dTlb$EN_perf_resp = 1'b0 ;

  // submodule coreFix_memExe_dispToRegQ
  assign coreFix_memExe_dispToRegQ$enq_x =
	     { coreFix_memExe_rsMem$dispatchData[106:72],
	       coreFix_memExe_rsMem$dispatchData[65:21],
	       coreFix_memExe_rsMem$dispatchData[71:66],
	       coreFix_memExe_rsMem$dispatchData[20:9] } ;
  assign coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_dispToRegQ$EN_enq =
	     WILL_FIRE_RL_coreFix_memExe_doDispatchMem ;
  assign coreFix_memExe_dispToRegQ$EN_deq =
	     WILL_FIRE_RL_coreFix_memExe_doRegReadMem ;
  assign coreFix_memExe_dispToRegQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_memExe_dispToRegQ$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_memExe_forwardQ_clearReq_dummy2_0
  assign coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign coreFix_memExe_forwardQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule coreFix_memExe_forwardQ_clearReq_dummy2_1
  assign coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign coreFix_memExe_forwardQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule coreFix_memExe_forwardQ_deqReq_dummy2_0
  assign coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_forwardQ_deqReq_dummy2_0$EN =
	     WILL_FIRE_RL_coreFix_memExe_doRespLdForward ;

  // submodule coreFix_memExe_forwardQ_deqReq_dummy2_1
  assign coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_forwardQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_forwardQ_deqReq_dummy2_2
  assign coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign coreFix_memExe_forwardQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule coreFix_memExe_forwardQ_enqReq_dummy2_0
  assign coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_forwardQ_enqReq_dummy2_0$EN =
	     _dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ;

  // submodule coreFix_memExe_forwardQ_enqReq_dummy2_1
  assign coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_forwardQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_forwardQ_enqReq_dummy2_2
  assign coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign coreFix_memExe_forwardQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule coreFix_memExe_lsq
  assign coreFix_memExe_lsq$enqLd_dst =
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3418_AND__ETC___d14153) ?
	       regRenamingTable$rename_0_getRename[8:0] :
	       regRenamingTable$rename_1_getRename[8:0] ;
  assign coreFix_memExe_lsq$enqLd_inst_tag =
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3418_AND__ETC___d14153) ?
	       rob$enqPort_0_getEnqInstTag :
	       rob$enqPort_1_getEnqInstTag ;
  assign coreFix_memExe_lsq$enqLd_mem_inst =
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3418_AND__ETC___d14153) ?
	       fetchStage$pipelines_0_first[191:174] :
	       fetchStage$pipelines_1_first[191:174] ;
  assign coreFix_memExe_lsq$enqLd_spec_bits =
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3418_AND__ETC___d14153) ?
	       specTagManager$currentSpecBits :
	       renaming_spec_bits__h686248 ;
  assign coreFix_memExe_lsq$enqSt_dst =
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3418_AND__ETC___d14161) ?
	       regRenamingTable$rename_0_getRename[8:0] :
	       regRenamingTable$rename_1_getRename[8:0] ;
  assign coreFix_memExe_lsq$enqSt_inst_tag =
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3418_AND__ETC___d14161) ?
	       rob$enqPort_0_getEnqInstTag :
	       rob$enqPort_1_getEnqInstTag ;
  assign coreFix_memExe_lsq$enqSt_mem_inst =
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3418_AND__ETC___d14161) ?
	       fetchStage$pipelines_0_first[191:174] :
	       fetchStage$pipelines_1_first[191:174] ;
  assign coreFix_memExe_lsq$enqSt_spec_bits =
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3418_AND__ETC___d14161) ?
	       specTagManager$currentSpecBits :
	       renaming_spec_bits__h686248 ;
  assign coreFix_memExe_lsq$getHit_t =
	     MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ?
	       MUX_coreFix_memExe_lsq$getHit_1__VAL_1 :
	       MUX_coreFix_memExe_lsq$getHit_1__VAL_1 ;
  assign coreFix_memExe_lsq$getOrigBE_t =
	     coreFix_memExe_regToExeQ$first[145:140] ;
  assign coreFix_memExe_lsq$issueLd_lsqTag =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
	       coreFix_memExe_lsq$getIssueLd[76:72] :
	       coreFix_memExe_issueLd$wget[76:72] ;
  assign coreFix_memExe_lsq$issueLd_paddr =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
	       coreFix_memExe_lsq$getIssueLd[71:8] :
	       coreFix_memExe_issueLd$wget[71:8] ;
  assign coreFix_memExe_lsq$issueLd_sbRes =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
	       MUX_coreFix_memExe_lsq$issueLd_4__VAL_1 :
	       coreFix_memExe_stb$search ;
  assign coreFix_memExe_lsq$issueLd_shiftedBE =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
	       coreFix_memExe_lsq$getIssueLd[7:0] :
	       coreFix_memExe_issueLd$wget[7:0] ;
  assign coreFix_memExe_lsq$respLd_alignedData =
	     WILL_FIRE_RL_coreFix_memExe_doRespLdMem ?
	       MUX_coreFix_memExe_lsq$respLd_2__VAL_1 :
	       MUX_coreFix_memExe_lsq$respLd_2__VAL_2 ;
  assign coreFix_memExe_lsq$respLd_t =
	     WILL_FIRE_RL_coreFix_memExe_doRespLdMem ?
	       MUX_coreFix_memExe_lsq$respLd_1__VAL_1 :
	       MUX_coreFix_memExe_lsq$respLd_1__VAL_2 ;
  assign coreFix_memExe_lsq$setAtCommit_0_put =
	     rob$deqPort_0_deq_data[24:19] ;
  assign coreFix_memExe_lsq$setAtCommit_1_put =
	     rob$deqPort_1_deq_data[24:19] ;
  assign coreFix_memExe_lsq$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_lsq$updateAddr_fault =
	     { (!coreFix_memExe_dTlb$procResp[12] &&
		!coreFix_memExe_dTlb$procResp[182] &&
		coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
		 coreFix_memExe_dTlb$procResp[177:175] == 3'd2 ||
		 coreFix_memExe_dTlb$procResp[177:175] == 3'd3 ||
		 coreFix_memExe_dTlb$procResp[12] :
		 coreFix_memExe_dTlb$procResp[12] ||
		 coreFix_memExe_dTlb$procResp[182],
	       IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1861 } ;
  assign coreFix_memExe_lsq$updateAddr_isMMIO =
	     coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735 ;
  assign coreFix_memExe_lsq$updateAddr_lsqTag =
	     coreFix_memExe_dTlb$procResp[162:157] ;
  assign coreFix_memExe_lsq$updateAddr_paddr =
	     coreFix_memExe_dTlb$procResp[246:183] ;
  assign coreFix_memExe_lsq$updateAddr_shiftedBE =
	     coreFix_memExe_dTlb$procResp[156:149] ;
  assign coreFix_memExe_lsq$updateData_d =
	     (coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ?
	       coreFix_memExe_regToExeQ$first[75:12] :
	       shiftData__h181569 ;
  assign coreFix_memExe_lsq$updateData_t =
	     coreFix_memExe_regToExeQ$first[143:140] ;
  assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[149:148] ;
  assign coreFix_memExe_lsq$EN_enqLd =
	     WILL_FIRE_RL_renameStage_doRenaming && _dfoo7 ;
  assign coreFix_memExe_lsq$EN_enqSt =
	     WILL_FIRE_RL_renameStage_doRenaming && _dfoo2 ;
  assign coreFix_memExe_lsq$EN_getHit =
	     MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 ;
  assign coreFix_memExe_lsq$EN_updateData =
	     WILL_FIRE_RL_coreFix_memExe_doExeMem &&
	     coreFix_memExe_regToExeQ$first[145] ;
  assign coreFix_memExe_lsq$EN_updateAddr =
	     CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
  assign coreFix_memExe_lsq$EN_issueLd =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign coreFix_memExe_lsq$EN_getIssueLd =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ;
  assign coreFix_memExe_lsq$EN_respLd =
	     WILL_FIRE_RL_coreFix_memExe_doRespLdMem ||
	     WILL_FIRE_RL_coreFix_memExe_doRespLdForward ;
  assign coreFix_memExe_lsq$EN_deqLd =
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
  assign coreFix_memExe_lsq$EN_deqSt =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault ;
  assign coreFix_memExe_lsq$EN_wakeupLdStalledBySB =
	     MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd1 ;
  assign coreFix_memExe_lsq$EN_setAtCommit_0_put =
	     CAN_FIRE_RL_commitStage_doSetLSQAtCommit ;
  assign coreFix_memExe_lsq$EN_setAtCommit_1_put =
	     CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 ;
  assign coreFix_memExe_lsq$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_memExe_lsq$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0
  assign coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1
  assign coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0
  assign coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN =
	     WILL_FIRE_RL_coreFix_memExe_doRespLdMem ;

  // submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1
  assign coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2
  assign coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0
  assign coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN =
	     MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 ;

  // submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1
  assign coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2
  assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule coreFix_memExe_regToExeQ
  assign coreFix_memExe_regToExeQ$enq_x =
	     { coreFix_memExe_dispToRegQ$first[97:63],
	       coreFix_memExe_dispToRegQ$first[29:12],
	       x__h181478,
	       x__h181479,
	       coreFix_memExe_dispToRegQ$first[11:0] } ;
  assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_regToExeQ$EN_enq =
	     WILL_FIRE_RL_coreFix_memExe_doRegReadMem ;
  assign coreFix_memExe_regToExeQ$EN_deq =
	     CAN_FIRE_RL_coreFix_memExe_doExeMem ;
  assign coreFix_memExe_regToExeQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_memExe_regToExeQ$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_memExe_reqLdQ_data_0_dummy2_0
  assign coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLdQ_data_0_dummy2_0$EN =
	     _dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write &&
	     coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;

  // submodule coreFix_memExe_reqLdQ_data_0_dummy2_1
  assign coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_reqLdQ_data_0_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_reqLdQ_deqP_dummy2_0
  assign coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLdQ_deqP_dummy2_0$EN =
	     WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;

  // submodule coreFix_memExe_reqLdQ_deqP_dummy2_1
  assign coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_reqLdQ_deqP_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_reqLdQ_empty_dummy2_0
  assign coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLdQ_empty_dummy2_0$EN =
	     _dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write &&
	     coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;

  // submodule coreFix_memExe_reqLdQ_empty_dummy2_1
  assign coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLdQ_empty_dummy2_1$EN =
	     WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;

  // submodule coreFix_memExe_reqLdQ_empty_dummy2_2
  assign coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN = 1'b0 ;
  assign coreFix_memExe_reqLdQ_empty_dummy2_2$EN = 1'b0 ;

  // submodule coreFix_memExe_reqLdQ_enqP_dummy2_0
  assign coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLdQ_enqP_dummy2_0$EN =
	     _dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write &&
	     coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;

  // submodule coreFix_memExe_reqLdQ_enqP_dummy2_1
  assign coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_reqLdQ_enqP_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_reqLdQ_full_dummy2_0
  assign coreFix_memExe_reqLdQ_full_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLdQ_full_dummy2_0$EN =
	     _dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write &&
	     coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;

  // submodule coreFix_memExe_reqLdQ_full_dummy2_1
  assign coreFix_memExe_reqLdQ_full_dummy2_1$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLdQ_full_dummy2_1$EN =
	     WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;

  // submodule coreFix_memExe_reqLdQ_full_dummy2_2
  assign coreFix_memExe_reqLdQ_full_dummy2_2$D_IN = 1'b0 ;
  assign coreFix_memExe_reqLdQ_full_dummy2_2$EN = 1'b0 ;

  // submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN =
	     coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;

  // submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0
  assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN =
	     CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;

  // submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1
  assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0
  assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN =
	     coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;

  // submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1
  assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN =
	     CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;

  // submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2
  assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN = 1'b0 ;
  assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN = 1'b0 ;

  // submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0
  assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN =
	     coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;

  // submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1
  assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0
  assign coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN =
	     coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;

  // submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1
  assign coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN =
	     CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;

  // submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2
  assign coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN = 1'b0 ;
  assign coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN = 1'b0 ;

  // submodule coreFix_memExe_reqStQ_data_0_dummy2_0
  assign coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqStQ_data_0_dummy2_0$EN =
	     CAN_FIRE_RL_coreFix_memExe_doIssueSB ;

  // submodule coreFix_memExe_reqStQ_data_0_dummy2_1
  assign coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_reqStQ_data_0_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_reqStQ_deqP_dummy2_0
  assign coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqStQ_deqP_dummy2_0$EN =
	     WILL_FIRE_RL_coreFix_memExe_sendStToMem ;

  // submodule coreFix_memExe_reqStQ_deqP_dummy2_1
  assign coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_reqStQ_deqP_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_reqStQ_empty_dummy2_0
  assign coreFix_memExe_reqStQ_empty_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqStQ_empty_dummy2_0$EN =
	     CAN_FIRE_RL_coreFix_memExe_doIssueSB ;

  // submodule coreFix_memExe_reqStQ_empty_dummy2_1
  assign coreFix_memExe_reqStQ_empty_dummy2_1$D_IN = 1'd1 ;
  assign coreFix_memExe_reqStQ_empty_dummy2_1$EN =
	     WILL_FIRE_RL_coreFix_memExe_sendStToMem ;

  // submodule coreFix_memExe_reqStQ_empty_dummy2_2
  assign coreFix_memExe_reqStQ_empty_dummy2_2$D_IN = 1'b0 ;
  assign coreFix_memExe_reqStQ_empty_dummy2_2$EN = 1'b0 ;

  // submodule coreFix_memExe_reqStQ_enqP_dummy2_0
  assign coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqStQ_enqP_dummy2_0$EN =
	     CAN_FIRE_RL_coreFix_memExe_doIssueSB ;

  // submodule coreFix_memExe_reqStQ_enqP_dummy2_1
  assign coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_reqStQ_enqP_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_reqStQ_full_dummy2_0
  assign coreFix_memExe_reqStQ_full_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqStQ_full_dummy2_0$EN =
	     CAN_FIRE_RL_coreFix_memExe_doIssueSB ;

  // submodule coreFix_memExe_reqStQ_full_dummy2_1
  assign coreFix_memExe_reqStQ_full_dummy2_1$D_IN = 1'd1 ;
  assign coreFix_memExe_reqStQ_full_dummy2_1$EN =
	     WILL_FIRE_RL_coreFix_memExe_sendStToMem ;

  // submodule coreFix_memExe_reqStQ_full_dummy2_2
  assign coreFix_memExe_reqStQ_full_dummy2_2$D_IN = 1'b0 ;
  assign coreFix_memExe_reqStQ_full_dummy2_2$EN = 1'b0 ;

  // submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0
  assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1
  assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0
  assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN =
	     coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas ;

  // submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1
  assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2
  assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0
  assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2565 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd2 ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd3) ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;

  // submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1
  assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2
  assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule coreFix_memExe_rsMem
  assign coreFix_memExe_rsMem$enq_x =
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3418_AND__ETC___d14133) ?
	       { fetchStage$pipelines_0_first[191:189],
		 IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14149,
		 regRenamingTable$rename_0_getRename,
		 rob$enqPort_0_getEnqInstTag,
		 specTagManager$currentSpecBits,
		 fetchStage$pipelines_0_first[194:192] == 3'd1,
		 specTagManager$nextSpecTag,
		 sbAggr$eagerLookup_0_get } :
	       { fetchStage$pipelines_1_first[191:189],
		 IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14280,
		 regRenamingTable$rename_1_getRename,
		 rob$enqPort_1_getEnqInstTag,
		 renaming_spec_bits__h686248,
		 fetchStage$pipelines_1_first[194:192] == 3'd1,
		 specTagManager$nextSpecTag,
		 sbAggr$eagerLookup_1_get } ;
  assign coreFix_memExe_rsMem$setRegReady_0_put =
	     coreFix_aluExe_0_rsAlu$setRegReady_0_put ;
  assign coreFix_memExe_rsMem$setRegReady_1_put =
	     coreFix_aluExe_0_rsAlu$setRegReady_1_put ;
  always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
	  coreFix_memExe_rsMem$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
	  coreFix_memExe_rsMem$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
	  coreFix_memExe_rsMem$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
	  coreFix_memExe_rsMem$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
	  coreFix_memExe_rsMem$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
	  coreFix_memExe_rsMem$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
      default: coreFix_memExe_rsMem$setRegReady_2_put =
		   8'b10101010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_rsMem$setRegReady_3_put =
	     coreFix_aluExe_0_rsAlu$setRegReady_3_put ;
  always@(MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
	  MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1:
	  coreFix_memExe_rsMem$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
      MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2:
	  coreFix_memExe_rsMem$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
	  coreFix_memExe_rsMem$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
	  coreFix_memExe_rsMem$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
      default: coreFix_memExe_rsMem$setRegReady_4_put =
		   8'b10101010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_rsMem$setRobEnqTime_t = rob$getEnqTime ;
  assign coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_rsMem$EN_enq =
	     WILL_FIRE_RL_renameStage_doRenaming && _dfoo12 ;
  assign coreFix_memExe_rsMem$EN_setRobEnqTime = 1'd1 ;
  assign coreFix_memExe_rsMem$EN_doDispatch =
	     WILL_FIRE_RL_coreFix_memExe_doDispatchMem ;
  assign coreFix_memExe_rsMem$EN_setRegReady_0_put =
	     WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
	     coreFix_aluExe_0_rsAlu$dispatchData[41] ;
  assign coreFix_memExe_rsMem$EN_setRegReady_1_put =
	     WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
	     coreFix_aluExe_1_rsAlu$dispatchData[41] ;
  assign coreFix_memExe_rsMem$EN_setRegReady_2_put =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
  assign coreFix_memExe_rsMem$EN_setRegReady_3_put =
	     _dor1coreFix_memExe_rsMem$EN_setRegReady_3_put &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
	     coreFix_memExe_lsq$issueLd[72] ;
  assign coreFix_memExe_rsMem$EN_setRegReady_4_put =
	     (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
	     coreFix_memExe_lsq$firstSt[150] ||
	     (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
	     coreFix_memExe_lsq$firstLd[89] ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2622 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 &&
	     coreFix_memExe_lsq$getHit[8] &&
	     !coreFix_memExe_lsq$getHit[9] ;
  assign coreFix_memExe_rsMem$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_memExe_rsMem$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_memExe_stb
  assign coreFix_memExe_stb$deq_idx =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[149:148] ;
  assign coreFix_memExe_stb$enq_be = coreFix_memExe_lsq$firstSt[76:69] ;
  assign coreFix_memExe_stb$enq_data = coreFix_memExe_lsq$firstSt[68:5] ;
  assign coreFix_memExe_stb$enq_idx = coreFix_memExe_stb$getEnqIndex[1:0] ;
  assign coreFix_memExe_stb$enq_paddr = coreFix_memExe_lsq$firstSt[141:78] ;
  assign coreFix_memExe_stb$getEnqIndex_paddr =
	     coreFix_memExe_lsq$firstSt[141:78] ;
  assign coreFix_memExe_stb$noMatchLdQ_be = coreFix_memExe_lsq$firstLd[15:8] ;
  assign coreFix_memExe_stb$noMatchLdQ_paddr =
	     coreFix_memExe_lsq$firstLd[80:17] ;
  assign coreFix_memExe_stb$noMatchStQ_be =
	     coreFix_memExe_lsq$firstSt[76:69] ;
  assign coreFix_memExe_stb$noMatchStQ_paddr =
	     coreFix_memExe_lsq$firstSt[141:78] ;
  assign coreFix_memExe_stb$search_be =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
	       coreFix_memExe_lsq$getIssueLd[7:0] :
	       coreFix_memExe_issueLd$wget[7:0] ;
  assign coreFix_memExe_stb$search_paddr =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
	       coreFix_memExe_lsq$getIssueLd[71:8] :
	       coreFix_memExe_issueLd$wget[71:8] ;
  assign coreFix_memExe_stb$EN_enq =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem ;
  assign coreFix_memExe_stb$EN_deq =
	     MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd1 ;
  assign coreFix_memExe_stb$EN_issue = CAN_FIRE_RL_coreFix_memExe_doIssueSB ;

  // submodule coreFix_trainBPQ_0
  assign coreFix_trainBPQ_0$D_IN =
	     MUX_coreFix_trainBPQ_0$enq_1__SEL_1 ?
	       MUX_coreFix_trainBPQ_0$enq_1__VAL_1 :
	       MUX_coreFix_trainBPQ_0$enq_1__VAL_2 ;
  assign coreFix_trainBPQ_0$ENQ =
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
	     (coreFix_aluExe_0_exeToFinQ$first[326:322] == 5'd9 ||
	      coreFix_aluExe_0_exeToFinQ$first[326:322] == 5'd10) ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
  assign coreFix_trainBPQ_0$DEQ = WILL_FIRE_RL_coreFix_doFetchTrainBP_1 ;
  assign coreFix_trainBPQ_0$CLR = 1'b0 ;

  // submodule coreFix_trainBPQ_1
  assign coreFix_trainBPQ_1$D_IN =
	     MUX_coreFix_trainBPQ_1$enq_1__SEL_1 ?
	       MUX_coreFix_trainBPQ_1$enq_1__VAL_1 :
	       MUX_coreFix_trainBPQ_1$enq_1__VAL_2 ;
  assign coreFix_trainBPQ_1$ENQ =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
	     (coreFix_aluExe_1_exeToFinQ$first[326:322] == 5'd9 ||
	      coreFix_aluExe_1_exeToFinQ$first[326:322] == 5'd10) ||
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
  assign coreFix_trainBPQ_1$DEQ = coreFix_trainBPQ_1$EMPTY_N ;
  assign coreFix_trainBPQ_1$CLR = 1'b0 ;

  // submodule csrInstOrInterruptInflight_dummy2_0
  assign csrInstOrInterruptInflight_dummy2_0$D_IN = 1'd1 ;
  assign csrInstOrInterruptInflight_dummy2_0$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     (commitStage_commitTrap[36] ||
	      commitStage_commitTrap[35:32] == 4'd3) ;

  // submodule csrInstOrInterruptInflight_dummy2_1
  assign csrInstOrInterruptInflight_dummy2_1$D_IN = 1'd1 ;
  assign csrInstOrInterruptInflight_dummy2_1$EN =
	     csrInstOrInterruptInflight_lat_1$whas ;

  // submodule csrf_mcycle_ehr_data_dummy2_0
  assign csrf_mcycle_ehr_data_dummy2_0$D_IN = 1'd1 ;
  assign csrf_mcycle_ehr_data_dummy2_0$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd2816 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd30 ;

  // submodule csrf_mcycle_ehr_data_dummy2_1
  assign csrf_mcycle_ehr_data_dummy2_1$D_IN = 1'd1 ;
  assign csrf_mcycle_ehr_data_dummy2_1$EN = 1'd1 ;

  // submodule csrf_minstret_ehr_data_dummy2_0
  assign csrf_minstret_ehr_data_dummy2_0$D_IN = 1'd1 ;
  assign csrf_minstret_ehr_data_dummy2_0$EN =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd2818 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd31 ;

  // submodule csrf_minstret_ehr_data_dummy2_1
  assign csrf_minstret_ehr_data_dummy2_1$D_IN = 1'd1 ;
  assign csrf_minstret_ehr_data_dummy2_1$EN =
	     csrf_minstret_ehr_data_dummy_1_0$whas ;

  // submodule csrf_stats_module_writeQ
  assign csrf_stats_module_writeQ$D_IN =
	     MUX_csrf_stats_module_writeQ$enq_1__SEL_1 ?
	       f_csr_reqs$D_OUT[0] :
	       MUX_csrf_stval_csr$write_1__VAL_1[0] ;
  assign csrf_stats_module_writeQ$ENQ =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd2049 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd7 ;
  assign csrf_stats_module_writeQ$DEQ = EN_sendDoStats ;
  assign csrf_stats_module_writeQ$CLR = 1'b0 ;

  // submodule csrf_terminate_module_terminateQ
  assign csrf_terminate_module_terminateQ$ENQ =
	     WILL_FIRE_RL_rl_debug_csr_write &&
	     f_csr_reqs$D_OUT[75:64] == 12'd2048 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd6 ;
  assign csrf_terminate_module_terminateQ$DEQ = EN_coreIndInv_terminate ;
  assign csrf_terminate_module_terminateQ$CLR = 1'b0 ;

  // submodule epochManager
  assign epochManager$checkEpoch_0_check_e =
	     fetchStage$pipelines_0_first[259:256] ;
  assign epochManager$checkEpoch_1_check_e =
	     fetchStage$pipelines_1_first[259:256] ;
  assign epochManager$updatePrevEpoch_0_update_e =
	     fetchStage$pipelines_0_first[259:256] ;
  assign epochManager$updatePrevEpoch_1_update_e =
	     fetchStage$pipelines_1_first[259:256] ;
  assign epochManager$EN_updatePrevEpoch_0_update =
	     WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
	     fetchStage$pipelines_0_canDeq ||
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     fetchStage$pipelines_0_canDeq &&
	     NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 &&
	     IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 ||
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
	     WILL_FIRE_RL_renameStage_doRenaming_Trap ;
  assign epochManager$EN_updatePrevEpoch_1_update =
	     WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
	     fetchStage$pipelines_1_canDeq &&
	     !epochManager$checkEpoch_1_check ||
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 &&
	     NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14220 &&
	     IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 ;
  assign epochManager$EN_incrementEpoch =
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !rob$deqPort_0_deq_data[12] ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
	     WILL_FIRE_RL_renameStage_doRenaming_Trap ;

  // submodule f_csr_reqs
  assign f_csr_reqs$D_IN = hart0_csr_mem_server_request_put ;
  assign f_csr_reqs$ENQ = EN_hart0_csr_mem_server_request_put ;
  assign f_csr_reqs$DEQ =
	     WILL_FIRE_RL_rl_debug_csr_access_busy ||
	     WILL_FIRE_RL_rl_debug_csr_write ||
	     WILL_FIRE_RL_rl_debug_csr_read ;
  assign f_csr_reqs$CLR = 1'b0 ;

  // submodule f_csr_rsps
  always@(WILL_FIRE_RL_rl_debug_csr_access_busy or
	  WILL_FIRE_RL_rl_debug_csr_write or
	  WILL_FIRE_RL_rl_debug_csr_read or MUX_f_csr_rsps$enq_1__VAL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_debug_csr_access_busy:
	  f_csr_rsps$D_IN = 65'h0AAAAAAAAAAAAAAAA;
      WILL_FIRE_RL_rl_debug_csr_write:
	  f_csr_rsps$D_IN = 65'h1AAAAAAAAAAAAAAAA;
      WILL_FIRE_RL_rl_debug_csr_read:
	  f_csr_rsps$D_IN = MUX_f_csr_rsps$enq_1__VAL_3;
      default: f_csr_rsps$D_IN =
		   65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign f_csr_rsps$ENQ =
	     WILL_FIRE_RL_rl_debug_csr_access_busy ||
	     WILL_FIRE_RL_rl_debug_csr_write ||
	     WILL_FIRE_RL_rl_debug_csr_read ;
  assign f_csr_rsps$DEQ = EN_hart0_csr_mem_server_response_get ;
  assign f_csr_rsps$CLR = 1'b0 ;

  // submodule f_fpr_reqs
  assign f_fpr_reqs$D_IN = hart0_fpr_mem_server_request_put ;
  assign f_fpr_reqs$ENQ = EN_hart0_fpr_mem_server_request_put ;
  assign f_fpr_reqs$DEQ =
	     WILL_FIRE_RL_rl_debug_fpr_access_busy ||
	     WILL_FIRE_RL_rl_debug_fpr_write ||
	     WILL_FIRE_RL_rl_debug_fpr_read ;
  assign f_fpr_reqs$CLR = 1'b0 ;

  // submodule f_fpr_rsps
  always@(WILL_FIRE_RL_rl_debug_fpr_access_busy or
	  WILL_FIRE_RL_rl_debug_fpr_write or
	  WILL_FIRE_RL_rl_debug_fpr_read or MUX_f_fpr_rsps$enq_1__VAL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_debug_fpr_access_busy:
	  f_fpr_rsps$D_IN = 65'h0AAAAAAAAAAAAAAAA;
      WILL_FIRE_RL_rl_debug_fpr_write:
	  f_fpr_rsps$D_IN = 65'h1AAAAAAAAAAAAAAAA;
      WILL_FIRE_RL_rl_debug_fpr_read:
	  f_fpr_rsps$D_IN = MUX_f_fpr_rsps$enq_1__VAL_3;
      default: f_fpr_rsps$D_IN =
		   65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign f_fpr_rsps$ENQ =
	     WILL_FIRE_RL_rl_debug_fpr_access_busy ||
	     WILL_FIRE_RL_rl_debug_fpr_write ||
	     WILL_FIRE_RL_rl_debug_fpr_read ;
  assign f_fpr_rsps$DEQ = EN_hart0_fpr_mem_server_response_get ;
  assign f_fpr_rsps$CLR = 1'b0 ;

  // submodule f_gpr_reqs
  assign f_gpr_reqs$D_IN = hart0_gpr_mem_server_request_put ;
  assign f_gpr_reqs$ENQ = EN_hart0_gpr_mem_server_request_put ;
  assign f_gpr_reqs$DEQ =
	     WILL_FIRE_RL_rl_debug_gpr_access_busy ||
	     WILL_FIRE_RL_rl_debug_gpr_write ||
	     WILL_FIRE_RL_rl_debug_gpr_read ;
  assign f_gpr_reqs$CLR = 1'b0 ;

  // submodule f_gpr_rsps
  always@(WILL_FIRE_RL_rl_debug_gpr_access_busy or
	  WILL_FIRE_RL_rl_debug_gpr_write or
	  WILL_FIRE_RL_rl_debug_gpr_read or MUX_f_fpr_rsps$enq_1__VAL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_debug_gpr_access_busy:
	  f_gpr_rsps$D_IN = 65'h0AAAAAAAAAAAAAAAA;
      WILL_FIRE_RL_rl_debug_gpr_write:
	  f_gpr_rsps$D_IN = 65'h1AAAAAAAAAAAAAAAA;
      WILL_FIRE_RL_rl_debug_gpr_read:
	  f_gpr_rsps$D_IN = MUX_f_fpr_rsps$enq_1__VAL_3;
      default: f_gpr_rsps$D_IN =
		   65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign f_gpr_rsps$ENQ =
	     WILL_FIRE_RL_rl_debug_gpr_access_busy ||
	     WILL_FIRE_RL_rl_debug_gpr_write ||
	     WILL_FIRE_RL_rl_debug_gpr_read ;
  assign f_gpr_rsps$DEQ = EN_hart0_gpr_mem_server_response_get ;
  assign f_gpr_rsps$CLR = 1'b0 ;

  // submodule f_run_halt_reqs
  assign f_run_halt_reqs$D_IN = hart0_run_halt_server_request_put ;
  assign f_run_halt_reqs$ENQ = EN_hart0_run_halt_server_request_put ;
  assign f_run_halt_reqs$DEQ =
	     WILL_FIRE_RL_rl_debug_run_redundant ||
	     WILL_FIRE_RL_rl_debug_resume ||
	     WILL_FIRE_RL_rl_debug_halt_req_already_halted ||
	     WILL_FIRE_RL_rl_debug_halt_req ;
  assign f_run_halt_reqs$CLR = 1'b0 ;

  // submodule f_run_halt_rsps
  assign f_run_halt_rsps$D_IN = !MUX_f_run_halt_rsps$enq_1__SEL_1 ;
  assign f_run_halt_rsps$ENQ =
	     WILL_FIRE_RL_rl_debug_halted ||
	     WILL_FIRE_RL_rl_debug_halt_req_already_halted ||
	     WILL_FIRE_RL_rl_debug_run_redundant ||
	     WILL_FIRE_RL_rl_debug_resume ;
  assign f_run_halt_rsps$DEQ = EN_hart0_run_halt_server_response_get ;
  assign f_run_halt_rsps$CLR = 1'b0 ;

  // submodule fetchStage
  assign fetchStage$iMemIfc_perf_req_r = 2'h0 ;
  assign fetchStage$iMemIfc_perf_setStatus_doStats = 1'b0 ;
  assign fetchStage$iMemIfc_to_parent_fromP_enq_x =
	     iCacheToParent_fromP_enq_x ;
  assign fetchStage$iMemIfc_to_proc_request_put = 64'h0 ;
  assign fetchStage$iTlbIfc_perf_req_r = 3'h0 ;
  assign fetchStage$iTlbIfc_perf_setStatus_doStats = 1'b0 ;
  assign fetchStage$iTlbIfc_toParent_rsFromP_enq_x =
	     l2Tlb$toChildren_rsToC_first[80:0] ;
  assign fetchStage$iTlbIfc_to_proc_request_put = 64'h0 ;
  assign fetchStage$iTlbIfc_updateVMInfo_vm =
	     MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ?
	       MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 :
	       MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 ;
  assign fetchStage$mmioIfc_instResp_enq_x = mmio_pRsQ_data_0[65:0] ;
  assign fetchStage$mmioIfc_setHtifAddrs_fromHost =
	     coreReq_start_fromHostAddr ;
  assign fetchStage$mmioIfc_setHtifAddrs_toHost = coreReq_start_toHostAddr ;
  assign fetchStage$perf_req_r = 2'h0 ;
  assign fetchStage$perf_setStatus_doStats = 1'b0 ;
  always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or
	  pc__h713396 or
	  WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  WILL_FIRE_RL_commitStage_doCommitKilledLd or
	  rob$deqPort_0_deq_data or
	  WILL_FIRE_RL_rl_debug_resume or
	  csrf_rg_dpc or
	  WILL_FIRE_RL_commitStage_doCommitSystemInst or
	  MUX_fetchStage$redirect_1__VAL_6)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_commitStage_rg_serial_num$write_1__SEL_1:
	  fetchStage$redirect_pc = pc__h713396;
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  fetchStage$redirect_pc = coreFix_aluExe_1_exeToFinQ$first[82:19];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  fetchStage$redirect_pc = coreFix_aluExe_0_exeToFinQ$first[82:19];
      WILL_FIRE_RL_commitStage_doCommitKilledLd:
	  fetchStage$redirect_pc = rob$deqPort_0_deq_data[425:362];
      WILL_FIRE_RL_rl_debug_resume: fetchStage$redirect_pc = csrf_rg_dpc;
      WILL_FIRE_RL_commitStage_doCommitSystemInst:
	  fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_6;
      default: fetchStage$redirect_pc =
		   64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign fetchStage$start_pc = coreReq_start_startpc ;
  assign fetchStage$train_predictors_dpTrain =
	     coreFix_trainBPQ_1$EMPTY_N ?
	       coreFix_trainBPQ_1$D_OUT[25:2] :
	       coreFix_trainBPQ_0$D_OUT[25:2] ;
  assign fetchStage$train_predictors_iType =
	     coreFix_trainBPQ_1$EMPTY_N ?
	       coreFix_trainBPQ_1$D_OUT[31:27] :
	       coreFix_trainBPQ_0$D_OUT[31:27] ;
  assign fetchStage$train_predictors_isCompressed =
	     coreFix_trainBPQ_1$EMPTY_N ?
	       coreFix_trainBPQ_1$D_OUT[0] :
	       coreFix_trainBPQ_0$D_OUT[0] ;
  assign fetchStage$train_predictors_mispred =
	     coreFix_trainBPQ_1$EMPTY_N ?
	       coreFix_trainBPQ_1$D_OUT[1] :
	       coreFix_trainBPQ_0$D_OUT[1] ;
  assign fetchStage$train_predictors_next_pc =
	     coreFix_trainBPQ_1$EMPTY_N ?
	       coreFix_trainBPQ_1$D_OUT[95:32] :
	       coreFix_trainBPQ_0$D_OUT[95:32] ;
  assign fetchStage$train_predictors_pc =
	     coreFix_trainBPQ_1$EMPTY_N ?
	       coreFix_trainBPQ_1$D_OUT[159:96] :
	       coreFix_trainBPQ_0$D_OUT[159:96] ;
  assign fetchStage$train_predictors_taken =
	     coreFix_trainBPQ_1$EMPTY_N ?
	       coreFix_trainBPQ_1$D_OUT[26] :
	       coreFix_trainBPQ_0$D_OUT[26] ;
  assign fetchStage$EN_pipelines_0_deq =
	     WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
	     fetchStage$pipelines_0_canDeq ||
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     fetchStage$pipelines_0_canDeq &&
	     NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 &&
	     IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 ||
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
	     WILL_FIRE_RL_renameStage_doRenaming_Trap ;
  assign fetchStage$EN_pipelines_1_deq =
	     WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
	     fetchStage$pipelines_1_canDeq &&
	     !epochManager$checkEpoch_1_check ||
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 &&
	     NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14220 &&
	     IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 ;
  assign fetchStage$EN_iTlbIfc_flush =
	     WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ||
	     WILL_FIRE_RL_rl_debug_resume ;
  assign fetchStage$EN_iTlbIfc_updateVMInfo =
	     WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ||
	     WILL_FIRE_RL_rl_debug_resume ;
  assign fetchStage$EN_iTlbIfc_to_proc_request_put = 1'b0 ;
  assign fetchStage$EN_iTlbIfc_to_proc_response_get = 1'b0 ;
  assign fetchStage$EN_iTlbIfc_toParent_rqToP_deq = WILL_FIRE_RL_sendITlbReq ;
  assign fetchStage$EN_iTlbIfc_toParent_rsFromP_enq =
	     CAN_FIRE_RL_sendRsToITlb ;
  assign fetchStage$EN_iTlbIfc_toParent_flush_request_get =
	     CAN_FIRE_RL_mkConnectionGetPut_1 ;
  assign fetchStage$EN_iTlbIfc_toParent_flush_response_put =
	     CAN_FIRE_RL_sendFlushDone ;
  assign fetchStage$EN_iTlbIfc_perf_setStatus = 1'b0 ;
  assign fetchStage$EN_iTlbIfc_perf_req = 1'b0 ;
  assign fetchStage$EN_iTlbIfc_perf_resp = 1'b0 ;
  assign fetchStage$EN_iMemIfc_to_proc_request_put = 1'b0 ;
  assign fetchStage$EN_iMemIfc_to_proc_response_get = 1'b0 ;
  assign fetchStage$EN_iMemIfc_flush = CAN_FIRE_RL_setDoFlushCaches ;
  assign fetchStage$EN_iMemIfc_perf_setStatus = 1'b0 ;
  assign fetchStage$EN_iMemIfc_perf_req = 1'b0 ;
  assign fetchStage$EN_iMemIfc_perf_resp = 1'b0 ;
  assign fetchStage$EN_iMemIfc_to_parent_rsToP_deq =
	     EN_iCacheToParent_rsToP_deq ;
  assign fetchStage$EN_iMemIfc_to_parent_rqToP_deq =
	     EN_iCacheToParent_rqToP_deq ;
  assign fetchStage$EN_iMemIfc_to_parent_fromP_enq =
	     EN_iCacheToParent_fromP_enq ;
  assign fetchStage$EN_iMemIfc_cRqStuck_get = EN_deadlock_iCacheCRqStuck_get ;
  assign fetchStage$EN_iMemIfc_pRqStuck_get = EN_deadlock_iCachePRqStuck_get ;
  assign fetchStage$EN_mmioIfc_instReq_deq = WILL_FIRE_RL_mmio_sendInstReq ;
  assign fetchStage$EN_mmioIfc_instResp_enq = CAN_FIRE_RL_mmio_sendInstResp ;
  assign fetchStage$EN_mmioIfc_setHtifAddrs = EN_coreReq_start ;
  assign fetchStage$EN_start = EN_coreReq_start ;
  assign fetchStage$EN_stop = 1'b0 ;
  assign fetchStage$EN_setWaitRedirect =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !rob$deqPort_0_deq_data[12] ||
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
	     WILL_FIRE_RL_renameStage_doRenaming_Trap ;
  assign fetchStage$EN_redirect =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 ||
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_rl_debug_resume ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst ;
  assign fetchStage$EN_setWaitFlush =
	     MUX_commitStage_rg_run_state$write_1__SEL_1 ;
  assign fetchStage$EN_done_flushing = CAN_FIRE_RL_readyToFetch ;
  assign fetchStage$EN_train_predictors =
	     coreFix_trainBPQ_1$EMPTY_N ||
	     WILL_FIRE_RL_coreFix_doFetchTrainBP_1 ;
  assign fetchStage$EN_flush_predictors = CAN_FIRE_RL_setDoFlushBrPred ;
  assign fetchStage$EN_perf_setStatus = 1'b0 ;
  assign fetchStage$EN_perf_req = 1'b0 ;
  assign fetchStage$EN_perf_resp = 1'b0 ;

  // submodule l2Tlb
  assign l2Tlb$perf_req_r = 4'h0 ;
  assign l2Tlb$perf_setStatus_doStats = 1'b0 ;
  assign l2Tlb$toChildren_rqFromC_put =
	     WILL_FIRE_RL_sendDTlbReq ?
	       MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 :
	       MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2 ;
  assign l2Tlb$toMem_respLd_enq_x = tlbToMem_respLd_enq_x ;
  assign l2Tlb$updateVMInfo_vmD =
	     MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ?
	       MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 :
	       MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 ;
  assign l2Tlb$updateVMInfo_vmI =
	     MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ?
	       MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 :
	       MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 ;
  assign l2Tlb$EN_updateVMInfo =
	     WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ||
	     WILL_FIRE_RL_rl_debug_resume ;
  assign l2Tlb$EN_toChildren_rqFromC_put =
	     WILL_FIRE_RL_sendDTlbReq || WILL_FIRE_RL_sendITlbReq ;
  assign l2Tlb$EN_toChildren_rsToC_deq =
	     WILL_FIRE_RL_sendRsToITlb || WILL_FIRE_RL_sendRsToDTlb ;
  assign l2Tlb$EN_toChildren_iTlbReqFlush_put =
	     CAN_FIRE_RL_mkConnectionGetPut_1 ;
  assign l2Tlb$EN_toChildren_dTlbReqFlush_put =
	     CAN_FIRE_RL_mkConnectionGetPut ;
  assign l2Tlb$EN_toChildren_flushDone_get = CAN_FIRE_RL_sendFlushDone ;
  assign l2Tlb$EN_toMem_memReq_deq = EN_tlbToMem_memReq_deq ;
  assign l2Tlb$EN_toMem_respLd_enq = EN_tlbToMem_respLd_enq ;
  assign l2Tlb$EN_perf_setStatus = 1'b0 ;
  assign l2Tlb$EN_perf_req = 1'b0 ;
  assign l2Tlb$EN_perf_resp = 1'b0 ;

  // submodule mmio_cRqQ_clearReq_dummy2_0
  assign mmio_cRqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign mmio_cRqQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule mmio_cRqQ_clearReq_dummy2_1
  assign mmio_cRqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign mmio_cRqQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule mmio_cRqQ_deqReq_dummy2_0
  assign mmio_cRqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_cRqQ_deqReq_dummy2_0$EN = EN_mmioToPlatform_cRq_deq ;

  // submodule mmio_cRqQ_deqReq_dummy2_1
  assign mmio_cRqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_cRqQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_cRqQ_deqReq_dummy2_2
  assign mmio_cRqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_cRqQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_cRqQ_enqReq_dummy2_0
  assign mmio_cRqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_cRqQ_enqReq_dummy2_0$EN =
	     WILL_FIRE_RL_mmio_sendInstReq || WILL_FIRE_RL_mmio_sendDataReq ;

  // submodule mmio_cRqQ_enqReq_dummy2_1
  assign mmio_cRqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_cRqQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_cRqQ_enqReq_dummy2_2
  assign mmio_cRqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_cRqQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_cRsQ_clearReq_dummy2_0
  assign mmio_cRsQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign mmio_cRsQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule mmio_cRsQ_clearReq_dummy2_1
  assign mmio_cRsQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign mmio_cRsQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule mmio_cRsQ_deqReq_dummy2_0
  assign mmio_cRsQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_cRsQ_deqReq_dummy2_0$EN = EN_mmioToPlatform_cRs_deq ;

  // submodule mmio_cRsQ_deqReq_dummy2_1
  assign mmio_cRsQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_cRsQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_cRsQ_deqReq_dummy2_2
  assign mmio_cRsQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_cRsQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_cRsQ_enqReq_dummy2_0
  assign mmio_cRsQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_cRsQ_enqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_handlePRq ;

  // submodule mmio_cRsQ_enqReq_dummy2_1
  assign mmio_cRsQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_cRsQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_cRsQ_enqReq_dummy2_2
  assign mmio_cRsQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_cRsQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_dataPendQ_clearReq_dummy2_0
  assign mmio_dataPendQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign mmio_dataPendQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule mmio_dataPendQ_clearReq_dummy2_1
  assign mmio_dataPendQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign mmio_dataPendQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule mmio_dataPendQ_deqReq_dummy2_0
  assign mmio_dataPendQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_dataPendQ_deqReq_dummy2_0$EN =
	     mmio_dataRespQ_deqReq_lat_0$whas ;

  // submodule mmio_dataPendQ_deqReq_dummy2_1
  assign mmio_dataPendQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_dataPendQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_dataPendQ_deqReq_dummy2_2
  assign mmio_dataPendQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_dataPendQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_dataPendQ_enqReq_dummy2_0
  assign mmio_dataPendQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_dataPendQ_enqReq_dummy2_0$EN =
	     mmio_dataPendQ_enqReq_lat_0$whas ;

  // submodule mmio_dataPendQ_enqReq_dummy2_1
  assign mmio_dataPendQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_dataPendQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_dataPendQ_enqReq_dummy2_2
  assign mmio_dataPendQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_dataPendQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_dataReqQ_clearReq_dummy2_0
  assign mmio_dataReqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign mmio_dataReqQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule mmio_dataReqQ_clearReq_dummy2_1
  assign mmio_dataReqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign mmio_dataReqQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule mmio_dataReqQ_deqReq_dummy2_0
  assign mmio_dataReqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_dataReqQ_deqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_sendDataReq ;

  // submodule mmio_dataReqQ_deqReq_dummy2_1
  assign mmio_dataReqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_dataReqQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_dataReqQ_deqReq_dummy2_2
  assign mmio_dataReqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_dataReqQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_dataReqQ_enqReq_dummy2_0
  assign mmio_dataReqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_dataReqQ_enqReq_dummy2_0$EN = mmio_dataPendQ_enqReq_lat_0$whas ;

  // submodule mmio_dataReqQ_enqReq_dummy2_1
  assign mmio_dataReqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_dataReqQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_dataReqQ_enqReq_dummy2_2
  assign mmio_dataReqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_dataReqQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_dataRespQ_clearReq_dummy2_0
  assign mmio_dataRespQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign mmio_dataRespQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule mmio_dataRespQ_clearReq_dummy2_1
  assign mmio_dataRespQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign mmio_dataRespQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule mmio_dataRespQ_deqReq_dummy2_0
  assign mmio_dataRespQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_dataRespQ_deqReq_dummy2_0$EN =
	     mmio_dataRespQ_deqReq_lat_0$whas ;

  // submodule mmio_dataRespQ_deqReq_dummy2_1
  assign mmio_dataRespQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_dataRespQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_dataRespQ_deqReq_dummy2_2
  assign mmio_dataRespQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_dataRespQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_dataRespQ_enqReq_dummy2_0
  assign mmio_dataRespQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_dataRespQ_enqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_sendDataResp ;

  // submodule mmio_dataRespQ_enqReq_dummy2_1
  assign mmio_dataRespQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_dataRespQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_dataRespQ_enqReq_dummy2_2
  assign mmio_dataRespQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_dataRespQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_pRqQ_clearReq_dummy2_0
  assign mmio_pRqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign mmio_pRqQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule mmio_pRqQ_clearReq_dummy2_1
  assign mmio_pRqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign mmio_pRqQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule mmio_pRqQ_deqReq_dummy2_0
  assign mmio_pRqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_pRqQ_deqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_handlePRq ;

  // submodule mmio_pRqQ_deqReq_dummy2_1
  assign mmio_pRqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_pRqQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_pRqQ_deqReq_dummy2_2
  assign mmio_pRqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_pRqQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_pRqQ_enqReq_dummy2_0
  assign mmio_pRqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_pRqQ_enqReq_dummy2_0$EN = EN_mmioToPlatform_pRq_enq ;

  // submodule mmio_pRqQ_enqReq_dummy2_1
  assign mmio_pRqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_pRqQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_pRqQ_enqReq_dummy2_2
  assign mmio_pRqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_pRqQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_pRsQ_clearReq_dummy2_0
  assign mmio_pRsQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign mmio_pRsQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule mmio_pRsQ_clearReq_dummy2_1
  assign mmio_pRsQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign mmio_pRsQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule mmio_pRsQ_deqReq_dummy2_0
  assign mmio_pRsQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_pRsQ_deqReq_dummy2_0$EN = mmio_pRsQ_deqReq_lat_0$whas ;

  // submodule mmio_pRsQ_deqReq_dummy2_1
  assign mmio_pRsQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_pRsQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_pRsQ_deqReq_dummy2_2
  assign mmio_pRsQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_pRsQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_pRsQ_enqReq_dummy2_0
  assign mmio_pRsQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_pRsQ_enqReq_dummy2_0$EN = EN_mmioToPlatform_pRs_enq ;

  // submodule mmio_pRsQ_enqReq_dummy2_1
  assign mmio_pRsQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_pRsQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_pRsQ_enqReq_dummy2_2
  assign mmio_pRsQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_pRsQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule perfReqQ
  assign perfReqQ$D_IN = { coreReq_perfReq_loc, coreReq_perfReq_t } ;
  assign perfReqQ$ENQ = EN_coreReq_perfReq ;
  assign perfReqQ$DEQ = EN_coreIndInv_perfResp ;
  assign perfReqQ$CLR = 1'b0 ;

  // submodule regRenamingTable
  assign regRenamingTable$rename_0_claimRename_r =
	     fetchStage$pipelines_0_first[95:69] ;
  assign regRenamingTable$rename_0_claimRename_sb =
	     specTagManager$currentSpecBits ;
  always@(MUX_regRenamingTable$rename_0_getRename_1__SEL_1 or
	  fetchStage$pipelines_0_first or
	  MUX_regRenamingTable$rename_0_getRename_1__SEL_2 or
	  MUX_regRenamingTable$rename_0_getRename_1__VAL_2 or
	  MUX_regRenamingTable$rename_0_getRename_1__SEL_3 or
	  MUX_regRenamingTable$rename_0_getRename_1__VAL_3)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_regRenamingTable$rename_0_getRename_1__SEL_1:
	  regRenamingTable$rename_0_getRename_r =
	      fetchStage$pipelines_0_first[95:69];
      MUX_regRenamingTable$rename_0_getRename_1__SEL_2:
	  regRenamingTable$rename_0_getRename_r =
	      MUX_regRenamingTable$rename_0_getRename_1__VAL_2;
      MUX_regRenamingTable$rename_0_getRename_1__SEL_3:
	  regRenamingTable$rename_0_getRename_r =
	      MUX_regRenamingTable$rename_0_getRename_1__VAL_3;
      default: regRenamingTable$rename_0_getRename_r =
		   27'b010101010101010101010101010 /* unspecified value */ ;
    endcase
  end
  assign regRenamingTable$rename_1_claimRename_r =
	     fetchStage$pipelines_1_first[95:69] ;
  assign regRenamingTable$rename_1_claimRename_sb =
	     renaming_spec_bits__h686248 ;
  assign regRenamingTable$rename_1_getRename_r =
	     fetchStage$pipelines_1_first[95:69] ;
  assign regRenamingTable$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign regRenamingTable$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign regRenamingTable$EN_rename_0_claimRename =
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     fetchStage$pipelines_0_canDeq &&
	     NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 &&
	     IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 ||
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
  assign regRenamingTable$EN_rename_1_claimRename =
	     MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
  assign regRenamingTable$EN_commit_0_commit =
	     WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	     rob$deqPort_0_canDeq ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst ;
  assign regRenamingTable$EN_commit_1_commit =
	     WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	     rob$deqPort_1_canDeq &&
	     rob$deqPort_1_deq_data[25] &&
	     !rob$deqPort_1_deq_data[18] &&
	     !rob$deqPort_1_deq_data[167] &&
	     rob$deqPort_1_deq_data[329:325] != 5'd0 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd21 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd17 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd18 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd13 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd16 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd15 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd19 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd20 ;
  assign regRenamingTable$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign regRenamingTable$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule rf
  assign rf$read_0_rd1_rindx = coreFix_aluExe_0_dispToRegQ$first[84:78] ;
  assign rf$read_0_rd2_rindx = coreFix_aluExe_0_dispToRegQ$first[76:70] ;
  assign rf$read_0_rd3_rindx = 7'h0 ;
  assign rf$read_1_rd1_rindx = coreFix_aluExe_1_dispToRegQ$first[84:78] ;
  assign rf$read_1_rd2_rindx = coreFix_aluExe_1_dispToRegQ$first[76:70] ;
  assign rf$read_1_rd3_rindx = 7'h0 ;
  assign rf$read_2_rd1_rindx =
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
  assign rf$read_2_rd2_rindx =
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
  assign rf$read_2_rd3_rindx =
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
  assign rf$read_3_rd1_rindx = coreFix_memExe_dispToRegQ$first[61:55] ;
  assign rf$read_3_rd2_rindx = coreFix_memExe_dispToRegQ$first[53:47] ;
  assign rf$read_3_rd3_rindx = 7'h0 ;
  assign rf$read_4_rd1_rindx = regRenamingTable$rename_0_getRename[31:25] ;
  assign rf$read_4_rd2_rindx = 7'h0 ;
  assign rf$read_4_rd3_rindx = 7'h0 ;
  assign rf$write_0_wr_data = coreFix_aluExe_0_exeToFinQ$first[275:212] ;
  assign rf$write_0_wr_rindx = coreFix_aluExe_0_exeToFinQ$first[320:314] ;
  assign rf$write_1_wr_data = coreFix_aluExe_1_exeToFinQ$first[275:212] ;
  assign rf$write_1_wr_rindx = coreFix_aluExe_1_exeToFinQ$first[320:314] ;
  always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
	  coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
	  MUX_rf$write_2_wr_2__VAL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
	  MUX_rf$write_2_wr_2__VAL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
	  MUX_rf$write_2_wr_2__VAL_4 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
	  MUX_rf$write_2_wr_2__VAL_5 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
	  MUX_rf$write_2_wr_2__VAL_6)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
	  rf$write_2_wr_data =
	      coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
	  rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_2;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
	  rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_3;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
	  rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_4;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
	  rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_5;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
	  rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_6;
      default: rf$write_2_wr_data =
		   64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
	  coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
	  coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
	  coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
	  coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
	  coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
	  coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
	  rf$write_2_wr_rindx =
	      coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
	  rf$write_2_wr_rindx =
	      coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
	  rf$write_2_wr_rindx =
	      coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
	  rf$write_2_wr_rindx =
	      coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
	  rf$write_2_wr_rindx =
	      coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
	  rf$write_2_wr_rindx =
	      coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25];
      default: rf$write_2_wr_rindx = 7'b0101010 /* unspecified value */ ;
    endcase
  end
  always@(MUX_rf$write_3_wr_1__SEL_1 or
	  coreFix_memExe_respLrScAmoQ_data_0 or
	  MUX_rf$write_3_wr_1__SEL_2 or
	  mmio_dataRespQ_data_0 or
	  MUX_rf$write_3_wr_1__SEL_3 or
	  MUX_rf$write_3_wr_2__VAL_3 or
	  MUX_rf$write_3_wr_1__SEL_4 or
	  MUX_rf$write_3_wr_2__VAL_4 or
	  MUX_rf$write_3_wr_2__SEL_5 or coreFix_memExe_lsq$respLd)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_rf$write_3_wr_1__SEL_1:
	  rf$write_3_wr_data = coreFix_memExe_respLrScAmoQ_data_0;
      MUX_rf$write_3_wr_1__SEL_2:
	  rf$write_3_wr_data = mmio_dataRespQ_data_0[63:0];
      MUX_rf$write_3_wr_1__SEL_3:
	  rf$write_3_wr_data = MUX_rf$write_3_wr_2__VAL_3;
      MUX_rf$write_3_wr_1__SEL_4:
	  rf$write_3_wr_data = MUX_rf$write_3_wr_2__VAL_4;
      MUX_rf$write_3_wr_2__SEL_5:
	  rf$write_3_wr_data = coreFix_memExe_lsq$respLd[63:0];
      default: rf$write_3_wr_data =
		   64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  always@(MUX_rf$write_3_wr_1__SEL_5 or
	  coreFix_memExe_lsq$respLd or
	  MUX_rf$write_3_wr_1__SEL_3 or
	  MUX_rf$write_3_wr_1__SEL_4 or
	  coreFix_memExe_lsq$firstLd or
	  MUX_rf$write_3_wr_1__SEL_1 or
	  MUX_rf$write_3_wr_1__SEL_2 or coreFix_memExe_lsq$firstSt)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_rf$write_3_wr_1__SEL_5:
	  rf$write_3_wr_rindx = coreFix_memExe_lsq$respLd[83:77];
      MUX_rf$write_3_wr_1__SEL_3 || MUX_rf$write_3_wr_1__SEL_4:
	  rf$write_3_wr_rindx = coreFix_memExe_lsq$firstLd[88:82];
      MUX_rf$write_3_wr_1__SEL_1 || MUX_rf$write_3_wr_1__SEL_2:
	  rf$write_3_wr_rindx = coreFix_memExe_lsq$firstSt[149:143];
      default: rf$write_3_wr_rindx = 7'b0101010 /* unspecified value */ ;
    endcase
  end
  assign rf$write_4_wr_data =
	     WILL_FIRE_RL_rl_debug_gpr_write ?
	       f_gpr_reqs$D_OUT[63:0] :
	       f_fpr_reqs$D_OUT[63:0] ;
  assign rf$write_4_wr_rindx = regRenamingTable$rename_0_getRename[31:25] ;
  assign rf$EN_write_0_wr =
	     _dor1rf$EN_write_0_wr && coreFix_aluExe_0_exeToFinQ$first[321] ;
  assign rf$EN_write_1_wr =
	     _dor1rf$EN_write_1_wr && coreFix_aluExe_1_exeToFinQ$first[321] ;
  assign rf$EN_write_2_wr =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
  assign rf$EN_write_3_wr =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
	     coreFix_memExe_lsq$firstSt[150] ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
	     coreFix_memExe_lsq$firstSt[150] ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	     coreFix_memExe_lsq$firstLd[89] ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     coreFix_memExe_lsq$firstLd[89] ||
	     (WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
	      WILL_FIRE_RL_coreFix_memExe_doRespLdMem) &&
	     coreFix_memExe_lsq$respLd[84] ;
  assign rf$EN_write_4_wr =
	     WILL_FIRE_RL_rl_debug_gpr_write ||
	     WILL_FIRE_RL_rl_debug_fpr_write ;

  // submodule rob
  always@(MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 or
	  MUX_rob$enqPort_0_enq_1__VAL_1 or
	  WILL_FIRE_RL_renameStage_doRenaming_Trap or
	  MUX_rob$enqPort_0_enq_1__VAL_2 or
	  WILL_FIRE_RL_renameStage_doRenaming_SystemInst or
	  MUX_rob$enqPort_0_enq_1__VAL_3)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2:
	  rob$enqPort_0_enq_x = MUX_rob$enqPort_0_enq_1__VAL_1;
      WILL_FIRE_RL_renameStage_doRenaming_Trap:
	  rob$enqPort_0_enq_x = MUX_rob$enqPort_0_enq_1__VAL_2;
      WILL_FIRE_RL_renameStage_doRenaming_SystemInst:
	  rob$enqPort_0_enq_x = MUX_rob$enqPort_0_enq_1__VAL_3;
      default: rob$enqPort_0_enq_x =
		   426'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign rob$enqPort_1_enq_x =
	     { fetchStage$pipelines_1_first[387:324],
	       fetchStage$pipelines_1_first[127:96],
	       fetchStage$pipelines_1_first[199:195],
	       fetchStage$pipelines_1_first[75:69],
	       136'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
	       fetchStage_pipelines_1_first__2766_BIT_173_360_ETC___d13691,
	       73'h1280000000000000000,
	       fetchStage$pipelines_1_first[323:260],
	       5'd0,
	       fetchStage$pipelines_1_first[75] &&
	       fetchStage$pipelines_1_first[74],
	       fetchStage$pipelines_1_first[194:192] != 3'd0 &&
	       fetchStage$pipelines_1_first[194:192] != 3'd1 &&
	       fetchStage$pipelines_1_first[194:192] != 3'd2 &&
	       fetchStage$pipelines_1_first[194:192] != 3'd3 &&
	       fetchStage$pipelines_1_first[194:192] != 3'd4,
	       fetchStage$pipelines_1_first[194:192] != 3'd2 ||
	       fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14311 ||
	       IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14274,
	       IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14321,
	       7'd32,
	       renaming_spec_bits__h686248 } ;
  assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ;
  assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ;
  assign rob$getOrigPC_2_get_x = 12'h0 ;
  assign rob$getOrigPredPC_0_get_x =
	     coreFix_aluExe_0_dispToRegQ$first[52:41] ;
  assign rob$getOrigPredPC_1_get_x =
	     coreFix_aluExe_1_dispToRegQ$first[52:41] ;
  assign rob$getOrig_Inst_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ;
  assign rob$getOrig_Inst_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ;
  always@(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or
	  MUX_rob$setExecuted_deqLSQ_2__VAL_2 or
	  WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or
	  MUX_rob$setExecuted_deqLSQ_2__VAL_6 or
	  MUX_rob$setExecuted_deqLSQ_1__SEL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 or
	  WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem or
	  WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault or
	  WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault:
	  rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_2;
      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault:
	  rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_6;
      MUX_rob$setExecuted_deqLSQ_1__SEL_1 ||
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 ||
      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem:
	  rob$setExecuted_deqLSQ_cause = 5'd10;
      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault:
	  rob$setExecuted_deqLSQ_cause = 5'd21;
      WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault:
	  rob$setExecuted_deqLSQ_cause = 5'd23;
      default: rob$setExecuted_deqLSQ_cause =
		   5'b01010 /* unspecified value */ ;
    endcase
  end
  assign rob$setExecuted_deqLSQ_ld_killed =
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ?
	       coreFix_memExe_lsq$firstLd[2:0] :
	       3'd2 ;
  assign rob$setExecuted_deqLSQ_x =
	     (MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) ?
	       coreFix_memExe_lsq$firstLd[113:102] :
	       coreFix_memExe_lsq$firstSt[170:159] ;
  assign rob$setExecuted_doFinishAlu_0_set_cf =
	     coreFix_aluExe_0_exeToFinQ$first[146:17] ;
  assign rob$setExecuted_doFinishAlu_0_set_csrData =
	     coreFix_aluExe_0_exeToFinQ$first[211:147] ;
  assign rob$setExecuted_doFinishAlu_0_set_dst_data =
	     coreFix_aluExe_0_exeToFinQ$first[275:212] ;
  assign rob$setExecuted_doFinishAlu_0_set_x =
	     coreFix_aluExe_0_exeToFinQ$first[312:301] ;
  assign rob$setExecuted_doFinishAlu_1_set_cf =
	     coreFix_aluExe_1_exeToFinQ$first[146:17] ;
  assign rob$setExecuted_doFinishAlu_1_set_csrData =
	     coreFix_aluExe_1_exeToFinQ$first[211:147] ;
  assign rob$setExecuted_doFinishAlu_1_set_dst_data =
	     coreFix_aluExe_1_exeToFinQ$first[275:212] ;
  assign rob$setExecuted_doFinishAlu_1_set_x =
	     coreFix_aluExe_1_exeToFinQ$first[312:301] ;
  always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or
	  coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or
	  MUX_rf$write_2_wr_2__VAL_2 or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or
	  MUX_rf$write_2_wr_2__VAL_3 or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or
	  MUX_rf$write_2_wr_2__VAL_4 or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or
	  MUX_rf$write_2_wr_2__VAL_5 or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or
	  MUX_rf$write_2_wr_2__VAL_6)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
	      coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38];
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
	      MUX_rf$write_2_wr_2__VAL_2;
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
	      MUX_rf$write_2_wr_2__VAL_3;
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
	      MUX_rf$write_2_wr_2__VAL_4;
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
	      MUX_rf$write_2_wr_2__VAL_5;
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
	      MUX_rf$write_2_wr_2__VAL_6;
      default: rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
		   64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or
	  coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or
	  MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or
	  MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or
	  MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
	      coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[37:33];
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
	      MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2;
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
	      MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3;
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
	      MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4;
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ||
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_fflags = 5'd0;
      default: rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
		   5'b01010 /* unspecified value */ ;
    endcase
  end
  always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or
	  coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or
	  coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or
	  coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or
	  coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or
	  coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or
	  coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_x =
	      coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[23:12];
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_x =
	      coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[23:12];
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_x =
	      coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[23:12];
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_x =
	      coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[23:12];
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_x =
	      coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[23:12];
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_x =
	      coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[23:12];
      default: rob$setExecuted_doFinishFpuMulDiv_0_set_x =
		   12'b101010101010 /* unspecified value */ ;
    endcase
  end
  always@(MUX_rf$write_3_wr_1__SEL_1 or
	  coreFix_memExe_respLrScAmoQ_data_0 or
	  MUX_rf$write_3_wr_1__SEL_2 or
	  mmio_dataRespQ_data_0 or
	  MUX_rf$write_3_wr_1__SEL_3 or
	  MUX_rf$write_3_wr_2__VAL_3 or
	  MUX_rf$write_3_wr_1__SEL_4 or
	  MUX_rf$write_3_wr_2__VAL_4 or
	  MUX_rob$setExecuted_doFinishMem_RegData_2__SEL_5 or
	  coreFix_memExe_lsq$respLd)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_rf$write_3_wr_1__SEL_1:
	  rob$setExecuted_doFinishMem_RegData_dst_data =
	      coreFix_memExe_respLrScAmoQ_data_0;
      MUX_rf$write_3_wr_1__SEL_2:
	  rob$setExecuted_doFinishMem_RegData_dst_data =
	      mmio_dataRespQ_data_0[63:0];
      MUX_rf$write_3_wr_1__SEL_3:
	  rob$setExecuted_doFinishMem_RegData_dst_data =
	      MUX_rf$write_3_wr_2__VAL_3;
      MUX_rf$write_3_wr_1__SEL_4:
	  rob$setExecuted_doFinishMem_RegData_dst_data =
	      MUX_rf$write_3_wr_2__VAL_4;
      MUX_rob$setExecuted_doFinishMem_RegData_2__SEL_5:
	  rob$setExecuted_doFinishMem_RegData_dst_data =
	      coreFix_memExe_lsq$respLd[63:0];
      default: rob$setExecuted_doFinishMem_RegData_dst_data =
		   64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  always@(MUX_rob$setExecuted_doFinishMem_RegData_1__SEL_5 or
	  coreFix_memExe_lsq$respLd or
	  MUX_rf$write_3_wr_1__SEL_3 or
	  MUX_rf$write_3_wr_1__SEL_4 or
	  coreFix_memExe_lsq$firstLd or
	  MUX_rf$write_3_wr_1__SEL_1 or
	  MUX_rf$write_3_wr_1__SEL_2 or coreFix_memExe_lsq$firstSt)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_rob$setExecuted_doFinishMem_RegData_1__SEL_5:
	  rob$setExecuted_doFinishMem_RegData_x =
	      coreFix_memExe_lsq$respLd[75:64];
      MUX_rf$write_3_wr_1__SEL_3 || MUX_rf$write_3_wr_1__SEL_4:
	  rob$setExecuted_doFinishMem_RegData_x =
	      coreFix_memExe_lsq$firstLd[113:102];
      MUX_rf$write_3_wr_1__SEL_1 || MUX_rf$write_3_wr_1__SEL_2:
	  rob$setExecuted_doFinishMem_RegData_x =
	      coreFix_memExe_lsq$firstSt[170:159];
      default: rob$setExecuted_doFinishMem_RegData_x =
		   12'b101010101010 /* unspecified value */ ;
    endcase
  end
  assign rob$setExecuted_doFinishMem_access_at_commit =
	     IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1744 &&
	     (coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735 ||
	      coreFix_memExe_dTlb$procResp[177:175] == 3'd2 ||
	      coreFix_memExe_dTlb$procResp[177:175] == 3'd3 ||
	      coreFix_memExe_dTlb$procResp[177:175] == 3'd4) ;
  assign rob$setExecuted_doFinishMem_non_mmio_st_done =
	     IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1744 &&
	     NOT_coreFix_memExe_dTlb_procResp__714_BITS_246_ETC___d1755 &&
	     coreFix_memExe_dTlb$procResp[177:175] == 3'd1 ;
  assign rob$setExecuted_doFinishMem_store_data =
	     coreFix_memExe_dTlb$procResp[84:21] ;
  assign rob$setExecuted_doFinishMem_store_data_BE =
	     coreFix_memExe_dTlb$procResp[20:13] ;
  assign rob$setExecuted_doFinishMem_vaddr =
	     coreFix_memExe_dTlb$procResp[148:85] ;
  assign rob$setExecuted_doFinishMem_x =
	     coreFix_memExe_dTlb$procResp[174:163] ;
  assign rob$setLSQAtCommitNotified_x = rob$deqPort_0_getDeqInstTag ;
  assign rob$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  rob$specUpdate_incorrectSpeculation_inst_tag =
	      coreFix_aluExe_1_exeToFinQ$first[312:301];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  rob$specUpdate_incorrectSpeculation_inst_tag =
	      coreFix_aluExe_0_exeToFinQ$first[312:301];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  rob$specUpdate_incorrectSpeculation_inst_tag =
	      12'b101010101010 /* unspecified value */ ;
      default: rob$specUpdate_incorrectSpeculation_inst_tag =
		   12'b101010101010 /* unspecified value */ ;
    endcase
  end
  assign rob$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  rob$specUpdate_incorrectSpeculation_spec_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  rob$specUpdate_incorrectSpeculation_spec_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  rob$specUpdate_incorrectSpeculation_spec_tag =
	      4'b1010 /* unspecified value */ ;
      default: rob$specUpdate_incorrectSpeculation_spec_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign rob$EN_enqPort_0_enq =
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     fetchStage$pipelines_0_canDeq &&
	     NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 &&
	     IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 ||
	     WILL_FIRE_RL_renameStage_doRenaming_Trap ||
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
  assign rob$EN_enqPort_1_enq =
	     MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
  assign rob$EN_deqPort_0_deq =
	     WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	     rob$deqPort_0_canDeq ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst ;
  assign rob$EN_deqPort_1_deq =
	     WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	     rob$deqPort_1_canDeq &&
	     rob$deqPort_1_deq_data[25] &&
	     !rob$deqPort_1_deq_data[18] &&
	     !rob$deqPort_1_deq_data[167] &&
	     rob$deqPort_1_deq_data[329:325] != 5'd0 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd21 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd17 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd18 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd13 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd16 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd15 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd19 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd20 ;
  assign rob$EN_setLSQAtCommitNotified =
	     CAN_FIRE_RL_commitStage_notifyLSQCommit ;
  assign rob$EN_setExecuted_deqLSQ =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ;
  assign rob$EN_setExecuted_doFinishAlu_0_set =
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
  assign rob$EN_setExecuted_doFinishAlu_1_set =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
  assign rob$EN_setExecuted_doFinishFpuMulDiv_0_set =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv ;
  assign rob$EN_setExecuted_doFinishMem =
	     CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
  assign rob$EN_setExecuted_doFinishMem_RegData =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
	     coreFix_memExe_lsq$firstSt[150] ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
	     coreFix_memExe_lsq$firstSt[150] ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	     coreFix_memExe_lsq$firstLd[89] ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     coreFix_memExe_lsq$firstLd[89] ||
	     (WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
	      WILL_FIRE_RL_coreFix_memExe_doRespLdMem) &&
	     coreFix_memExe_lsq$respLd[84] ;
  assign rob$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign rob$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule sbAggr
  assign sbAggr$eagerLookup_0_get_r = regRenamingTable$rename_0_getRename ;
  assign sbAggr$eagerLookup_1_get_r = regRenamingTable$rename_1_getRename ;
  assign sbAggr$setBusy_0_set_dst = regRenamingTable$rename_0_getRename[8:0] ;
  assign sbAggr$setBusy_1_set_dst = regRenamingTable$rename_1_getRename[8:0] ;
  assign sbAggr$setReady_0_put = coreFix_aluExe_0_rsAlu$dispatchData[40:34] ;
  assign sbAggr$setReady_1_put = coreFix_aluExe_1_rsAlu$dispatchData[40:34] ;
  always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
	  coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
	  coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
	  coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
	  coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
	  coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
	  coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
	  sbAggr$setReady_2_put =
	      coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
	  sbAggr$setReady_2_put =
	      coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
	  sbAggr$setReady_2_put =
	      coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
	  sbAggr$setReady_2_put =
	      coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
	  sbAggr$setReady_2_put =
	      coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
	  sbAggr$setReady_2_put =
	      coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25];
      default: sbAggr$setReady_2_put = 7'b0101010 /* unspecified value */ ;
    endcase
  end
  assign sbAggr$setReady_3_put = coreFix_memExe_lsq$issueLd[71:65] ;
  always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4 or
	  coreFix_memExe_lsq$getHit or
	  MUX_sbAggr$setReady_4_put_1__SEL_2 or
	  coreFix_memExe_lsq$firstLd or
	  MUX_sbAggr$setReady_4_put_1__SEL_1 or coreFix_memExe_lsq$firstSt)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 ||
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
	  sbAggr$setReady_4_put = coreFix_memExe_lsq$getHit[7:1];
      MUX_sbAggr$setReady_4_put_1__SEL_2:
	  sbAggr$setReady_4_put = coreFix_memExe_lsq$firstLd[88:82];
      MUX_sbAggr$setReady_4_put_1__SEL_1:
	  sbAggr$setReady_4_put = coreFix_memExe_lsq$firstSt[149:143];
      default: sbAggr$setReady_4_put = 7'b0101010 /* unspecified value */ ;
    endcase
  end
  assign sbAggr$EN_setBusy_0_set =
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     fetchStage$pipelines_0_canDeq &&
	     NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 &&
	     IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 ||
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
  assign sbAggr$EN_setBusy_1_set =
	     MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
  assign sbAggr$EN_setReady_0_put =
	     WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
	     coreFix_aluExe_0_rsAlu$dispatchData[41] ;
  assign sbAggr$EN_setReady_1_put =
	     WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
	     coreFix_aluExe_1_rsAlu$dispatchData[41] ;
  assign sbAggr$EN_setReady_2_put =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
  assign sbAggr$EN_setReady_3_put =
	     _dor1sbAggr$EN_setReady_3_put &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
	     coreFix_memExe_lsq$issueLd[72] ;
  assign sbAggr$EN_setReady_4_put =
	     (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
	     coreFix_memExe_lsq$firstSt[150] ||
	     (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
	     coreFix_memExe_lsq$firstLd[89] ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2622 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 &&
	     coreFix_memExe_lsq$getHit[8] &&
	     !coreFix_memExe_lsq$getHit[9] ;

  // submodule sbCons
  assign sbCons$eagerLookup_0_get_r = 33'h0 ;
  assign sbCons$eagerLookup_1_get_r = 33'h0 ;
  assign sbCons$lazyLookup_0_get_r =
	     coreFix_aluExe_0_dispToRegQ$first[85:53] ;
  assign sbCons$lazyLookup_1_get_r =
	     coreFix_aluExe_1_dispToRegQ$first[85:53] ;
  assign sbCons$lazyLookup_2_get_r =
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[56:24] ;
  assign sbCons$lazyLookup_3_get_r = coreFix_memExe_dispToRegQ$first[62:30] ;
  assign sbCons$lazyLookup_4_get_r = 33'h0 ;
  assign sbCons$setBusy_0_set_dst = regRenamingTable$rename_0_getRename[8:0] ;
  assign sbCons$setBusy_1_set_dst = regRenamingTable$rename_1_getRename[8:0] ;
  assign sbCons$setReady_0_put = coreFix_aluExe_0_exeToFinQ$first[320:314] ;
  assign sbCons$setReady_1_put = coreFix_aluExe_1_exeToFinQ$first[320:314] ;
  always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
	  coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
	  coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
	  coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
	  coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
	  coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
	  coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
	  sbCons$setReady_2_put =
	      coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
	  sbCons$setReady_2_put =
	      coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
	  sbCons$setReady_2_put =
	      coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
	  sbCons$setReady_2_put =
	      coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
	  sbCons$setReady_2_put =
	      coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
	  sbCons$setReady_2_put =
	      coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25];
      default: sbCons$setReady_2_put = 7'b0101010 /* unspecified value */ ;
    endcase
  end
  always@(MUX_sbCons$setReady_3_put_1__SEL_1 or
	  coreFix_memExe_lsq$firstSt or
	  MUX_sbCons$setReady_3_put_1__SEL_2 or
	  coreFix_memExe_lsq$firstLd or
	  MUX_sbCons$setReady_3_put_1__SEL_3 or coreFix_memExe_lsq$respLd)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_sbCons$setReady_3_put_1__SEL_1:
	  sbCons$setReady_3_put = coreFix_memExe_lsq$firstSt[149:143];
      MUX_sbCons$setReady_3_put_1__SEL_2:
	  sbCons$setReady_3_put = coreFix_memExe_lsq$firstLd[88:82];
      MUX_sbCons$setReady_3_put_1__SEL_3:
	  sbCons$setReady_3_put = coreFix_memExe_lsq$respLd[83:77];
      default: sbCons$setReady_3_put = 7'b0101010 /* unspecified value */ ;
    endcase
  end
  assign sbCons$setReady_4_put = 7'h0 ;
  assign sbCons$EN_setBusy_0_set =
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     fetchStage$pipelines_0_canDeq &&
	     NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 &&
	     IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 ||
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
  assign sbCons$EN_setBusy_1_set =
	     MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
  assign sbCons$EN_setReady_0_put =
	     _dor1sbCons$EN_setReady_0_put &&
	     coreFix_aluExe_0_exeToFinQ$first[321] ;
  assign sbCons$EN_setReady_1_put =
	     _dor1sbCons$EN_setReady_1_put &&
	     coreFix_aluExe_1_exeToFinQ$first[321] ;
  assign sbCons$EN_setReady_2_put =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
  assign sbCons$EN_setReady_3_put =
	     (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
	     coreFix_memExe_lsq$firstSt[150] ||
	     (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
	     coreFix_memExe_lsq$firstLd[89] ||
	     (WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
	      WILL_FIRE_RL_coreFix_memExe_doRespLdMem) &&
	     coreFix_memExe_lsq$respLd[84] ;
  assign sbCons$EN_setReady_4_put = 1'b0 ;

  // submodule specTagManager
  assign specTagManager$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
  assign specTagManager$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  specTagManager$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  specTagManager$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  specTagManager$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: specTagManager$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign specTagManager$EN_claimSpecTag =
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     (fetchStage_pipelines_0_canDeq__2755_AND_specTa_ETC___d14167 ||
	      NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 &&
	      NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14298) ;
  assign specTagManager$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign specTagManager$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule v_f_to_TV_0
  always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or
	  MUX_v_f_to_TV_0$enq_1__VAL_1 or
	  MUX_v_f_to_TV_0$enq_1__SEL_2 or
	  MUX_v_f_to_TV_0$enq_1__VAL_2 or
	  WILL_FIRE_RL_commitStage_rl_send_tv_reset or
	  WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv or
	  MUX_v_f_to_TV_0$enq_1__VAL_4 or
	  WILL_FIRE_RL_commitStage_doCommitSystemInst or
	  MUX_v_f_to_TV_0$enq_1__VAL_5)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_commitStage_rg_serial_num$write_1__SEL_1:
	  v_f_to_TV_0$D_IN = MUX_v_f_to_TV_0$enq_1__VAL_1;
      MUX_v_f_to_TV_0$enq_1__SEL_2:
	  v_f_to_TV_0$D_IN = MUX_v_f_to_TV_0$enq_1__VAL_2;
      WILL_FIRE_RL_commitStage_rl_send_tv_reset:
	  v_f_to_TV_0$D_IN =
	      862'h000000000000000015555555555555555554AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
      WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv:
	  v_f_to_TV_0$D_IN = MUX_v_f_to_TV_0$enq_1__VAL_4;
      WILL_FIRE_RL_commitStage_doCommitSystemInst:
	  v_f_to_TV_0$D_IN = MUX_v_f_to_TV_0$enq_1__VAL_5;
      default: v_f_to_TV_0$D_IN =
		   862'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign v_f_to_TV_0$ENQ =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 ||
	     WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	     rob$deqPort_0_canDeq ||
	     WILL_FIRE_RL_commitStage_rl_send_tv_reset ||
	     WILL_FIRE_RL_commitStage_rl_send_mip_csr_change_to_tv ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst ;
  assign v_f_to_TV_0$DEQ = EN_v_to_TV_0_get ;
  assign v_f_to_TV_0$CLR = 1'b0 ;

  // submodule v_f_to_TV_1
  assign v_f_to_TV_1$D_IN =
	     { commitStage_rg_serial_num_4343_PLUS_IF_rob_deq_ETC___d15467,
	       77'h0AAAAAAAAAAAAAAAAAAA,
	       rob$deqPort_1_deq_data[425:181],
	       CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q300,
	       6'd10,
	       rob$deqPort_1_deq_data[161:98],
	       CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q301,
	       rob$deqPort_1_deq_data[95:32],
	       po_fflags__h731598,
	       rob$deqPort_1_deq_data[26],
	       x__h733741,
	       258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
  assign v_f_to_TV_1$ENQ =
	     WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	     rob$deqPort_1_canDeq &&
	     rob$deqPort_1_deq_data[25] &&
	     !rob$deqPort_1_deq_data[18] &&
	     !rob$deqPort_1_deq_data[167] &&
	     rob$deqPort_1_deq_data[329:325] != 5'd0 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd21 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd17 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd18 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd13 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd16 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd15 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd19 &&
	     rob$deqPort_1_deq_data[329:325] != 5'd20 ;
  assign v_f_to_TV_1$DEQ = EN_v_to_TV_1_get ;
  assign v_f_to_TV_1$CLR = 1'b0 ;

  // remaining internal signals
  module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]),
				    .amoExec_current_data(curData__h192918),
				    .amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]),
				    .amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]),
				    .amoExec(n__h194456));
  module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32],
							3'd0 }),
				    .amoExec_current_data({ 63'd0,
							    r__h614580 }),
				    .amoExec_in_data({ 32'd0, x__h76239 }),
				    .amoExec_upper_32_bits(1'd0),
				    .amoExec(amoExec___d880));
  module_basicExec instance_basicExec_6(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[421:417],
							   CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228,
							   { coreFix_aluExe_1_regToExeQ$first[395],
							     CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229,
							     coreFix_aluExe_1_regToExeQ$first[382],
							     coreFix_aluExe_1_regToExeQ$first[381:350] } }),
					.basicExec_rVal1(coreFix_aluExe_1_regToExeQ$first[304:241]),
					.basicExec_rVal2(coreFix_aluExe_1_regToExeQ$first[240:177]),
					.basicExec_pc(coreFix_aluExe_1_regToExeQ$first[176:113]),
					.basicExec_ppc(coreFix_aluExe_1_regToExeQ$first[112:49]),
					.basicExec_orig_inst(coreFix_aluExe_1_regToExeQ$first[48:17]),
					.basicExec(basicExec___d11943));
  module_basicExec instance_basicExec_5(.basicExec_dInst({ coreFix_aluExe_0_regToExeQ$first[421:417],
							   CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231,
							   { coreFix_aluExe_0_regToExeQ$first[395],
							     CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232,
							     coreFix_aluExe_0_regToExeQ$first[382],
							     coreFix_aluExe_0_regToExeQ$first[381:350] } }),
					.basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[304:241]),
					.basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[240:177]),
					.basicExec_pc(coreFix_aluExe_0_regToExeQ$first[176:113]),
					.basicExec_ppc(coreFix_aluExe_0_regToExeQ$first[112:49]),
					.basicExec_orig_inst(coreFix_aluExe_0_regToExeQ$first[48:17]),
					.basicExec(basicExec___d12617));
  module_checkForException instance_checkForException_0(.checkForException_dInst({ fetchStage$pipelines_0_first[199:195],
										   IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883,
										   { { fetchStage$pipelines_0_first[173],
										       IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973 },
										     fetchStage$pipelines_0_first[160],
										     x_data_imm__h677666 } }),
							.checkForException_regs({ fetchStage$pipelines_0_first[95],
										  fetchStage$pipelines_0_first[94:89],
										  { fetchStage$pipelines_0_first[88],
										    fetchStage$pipelines_0_first[87:82] },
										  { fetchStage$pipelines_0_first[81],
										    fetchStage$pipelines_0_first[80:76],
										    { fetchStage$pipelines_0_first[75],
										      fetchStage$pipelines_0_first[74:69] } } }),
							.checkForException_csrState({ x_decodeInfo_frm__h655017,
										      r1__read_BITS_13_TO_12___h655202 !=
										      2'd0,
										      { prv__h735894,
											tvm_val__h727283,
											{ r1__read_BIT_20___h655898,
											  tsr_val__h727281,
											  { csrf_mcounteren_cy_reg,
											    csrf_mcounteren_cy_reg &&
											    csrf_scounteren_cy_reg,
											    { csrf_mcounteren_ir_reg,
											      csrf_mcounteren_ir_reg &&
											      csrf_scounteren_ir_reg,
											      { csrf_mcounteren_tm_reg,
												csrf_mcounteren_tm_reg &&
												csrf_scounteren_tm_reg } } } } } }),
							.checkForException(checkForException___d13008));
  module_checkForException instance_checkForException_1(.checkForException_dInst({ fetchStage$pipelines_1_first[199:195],
										   IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599,
										   { fetchStage_pipelines_1_first__2766_BIT_173_360_ETC___d13691,
										     fetchStage$pipelines_1_first[160],
										     x_data_imm__h693720 } }),
							.checkForException_regs({ fetchStage$pipelines_1_first[95],
										  fetchStage$pipelines_1_first[94:89],
										  { fetchStage$pipelines_1_first[88],
										    fetchStage$pipelines_1_first[87:82] },
										  { fetchStage$pipelines_1_first[81],
										    fetchStage$pipelines_1_first[80:76],
										    { fetchStage$pipelines_1_first[75],
										      fetchStage$pipelines_1_first[74:69] } } }),
							.checkForException_csrState({ x_decodeInfo_frm__h655017,
										      r1__read_BITS_13_TO_12___h655202 !=
										      2'd0,
										      { prv__h735894,
											tvm_val__h727283,
											{ r1__read_BIT_20___h655898,
											  tsr_val__h727281,
											  { csrf_mcounteren_cy_reg,
											    csrf_mcounteren_cy_reg &&
											    csrf_scounteren_cy_reg,
											    { csrf_mcounteren_ir_reg,
											      csrf_mcounteren_ir_reg &&
											      csrf_scounteren_ir_reg,
											      { csrf_mcounteren_tm_reg,
												csrf_mcounteren_tm_reg &&
												csrf_scounteren_tm_reg } } } } } }),
							.checkForException(checkForException___d13713));
  module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229],
									  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259,
									  coreFix_fpuMulDivExe_0_regToExeQ$first[225] }),
						.execFpuSimple_rVal1(rVal1__h481763),
						.execFpuSimple_rVal2(rVal2__h481764),
						.execFpuSimple(execFpuSimple___d11056));
  assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28 =
	     _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4249 ?
	       _theResult___snd__h354261 :
	       _theResult____h346087 ;
  assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63 =
	     _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5641 ?
	       _theResult___snd__h399958 :
	       _theResult____h391786 ;
  assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98 =
	     _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7033 ?
	       _theResult___snd__h445653 :
	       _theResult____h437481 ;
  assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138 =
	     _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8897 ?
	       _theResult___snd__h511170 :
	       _theResult____h502871 ;
  assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155 =
	     _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9612 ?
	       _theResult___snd__h589327 :
	       _theResult____h581028 ;
  assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178 =
	     _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10382 ?
	       _theResult___snd__h550023 :
	       _theResult____h541724 ;
  assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q108 =
	     _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7584 ?
	       _theResult___snd__h463419 :
	       _theResult____h455118 ;
  assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q38 =
	     _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4800 ?
	       _theResult___snd__h372027 :
	       _theResult____h363726 ;
  assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q73 =
	     _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6192 ?
	       _theResult___snd__h417724 :
	       _theResult____h409423 ;
  assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134 =
	     _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8585 ?
	       _theResult___snd__h501519 :
	       57'd0 ;
  assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141 =
	     _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8947 ?
	       _theResult___snd__h501519 :
	       _theResult___snd__h519924 ;
  assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151 =
	     _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9315 ?
	       _theResult___snd__h579676 :
	       57'd0 ;
  assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158 =
	     _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9662 ?
	       _theResult___snd__h579676 :
	       _theResult___snd__h598081 ;
  assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174 =
	     _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10085 ?
	       _theResult___snd__h540372 :
	       57'd0 ;
  assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181 =
	     _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10432 ?
	       _theResult___snd__h540372 :
	       _theResult___snd__h558777 ;
  assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q100 =
	     _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7264 ?
	       _theResult___snd__h454235 :
	       57'd0 ;
  assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113 =
	     _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7657 ?
	       _theResult___snd__h454235 :
	       _theResult___snd__h472025 ;
  assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q30 =
	     _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4480 ?
	       _theResult___snd__h362843 :
	       57'd0 ;
  assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43 =
	     _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4873 ?
	       _theResult___snd__h362843 :
	       _theResult___snd__h380633 ;
  assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q65 =
	     _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5872 ?
	       _theResult___snd__h408540 :
	       57'd0 ;
  assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78 =
	     _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6265 ?
	       _theResult___snd__h408540 :
	       _theResult___snd__h426330 ;
  assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5069 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ?
	       ((_theResult___fst_exp__h354198 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054) :
	       ((_theResult___fst_exp__h362854 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067) ;
  assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5119 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ?
	       ((_theResult___fst_exp__h354198 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110) :
	       ((_theResult___fst_exp__h362854 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117) ;
  assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6461 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ?
	       ((_theResult___fst_exp__h399895 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446) :
	       ((_theResult___fst_exp__h408551 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459) ;
  assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6511 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ?
	       ((_theResult___fst_exp__h399895 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502) :
	       ((_theResult___fst_exp__h408551 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509) ;
  assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7853 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ?
	       ((_theResult___fst_exp__h445590 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838) :
	       ((_theResult___fst_exp__h454246 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851) ;
  assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7903 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ?
	       ((_theResult___fst_exp__h445590 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894) :
	       ((_theResult___fst_exp__h454246 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901) ;
  assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247 =
	     (_theResult____h346087[56] ?
		6'd0 :
		(_theResult____h346087[55] ?
		   6'd1 :
		   (_theResult____h346087[54] ?
		      6'd2 :
		      (_theResult____h346087[53] ?
			 6'd3 :
			 (_theResult____h346087[52] ?
			    6'd4 :
			    (_theResult____h346087[51] ?
			       6'd5 :
			       (_theResult____h346087[50] ?
				  6'd6 :
				  (_theResult____h346087[49] ?
				     6'd7 :
				     (_theResult____h346087[48] ?
					6'd8 :
					(_theResult____h346087[47] ?
					   6'd9 :
					   (_theResult____h346087[46] ?
					      6'd10 :
					      (_theResult____h346087[45] ?
						 6'd11 :
						 (_theResult____h346087[44] ?
						    6'd12 :
						    (_theResult____h346087[43] ?
						       6'd13 :
						       (_theResult____h346087[42] ?
							  6'd14 :
							  (_theResult____h346087[41] ?
							     6'd15 :
							     (_theResult____h346087[40] ?
								6'd16 :
								(_theResult____h346087[39] ?
								   6'd17 :
								   (_theResult____h346087[38] ?
								      6'd18 :
								      (_theResult____h346087[37] ?
									 6'd19 :
									 (_theResult____h346087[36] ?
									    6'd20 :
									    (_theResult____h346087[35] ?
									       6'd21 :
									       (_theResult____h346087[34] ?
										  6'd22 :
										  (_theResult____h346087[33] ?
										     6'd23 :
										     (_theResult____h346087[32] ?
											6'd24 :
											(_theResult____h346087[31] ?
											   6'd25 :
											   (_theResult____h346087[30] ?
											      6'd26 :
											      (_theResult____h346087[29] ?
												 6'd27 :
												 (_theResult____h346087[28] ?
												    6'd28 :
												    (_theResult____h346087[27] ?
												       6'd29 :
												       (_theResult____h346087[26] ?
													  6'd30 :
													  (_theResult____h346087[25] ?
													     6'd31 :
													     (_theResult____h346087[24] ?
														6'd32 :
														(_theResult____h346087[23] ?
														   6'd33 :
														   (_theResult____h346087[22] ?
														      6'd34 :
														      (_theResult____h346087[21] ?
															 6'd35 :
															 (_theResult____h346087[20] ?
															    6'd36 :
															    (_theResult____h346087[19] ?
															       6'd37 :
															       (_theResult____h346087[18] ?
																  6'd38 :
																  (_theResult____h346087[17] ?
																     6'd39 :
																     (_theResult____h346087[16] ?
																	6'd40 :
																	(_theResult____h346087[15] ?
																	   6'd41 :
																	   (_theResult____h346087[14] ?
																	      6'd42 :
																	      (_theResult____h346087[13] ?
																		 6'd43 :
																		 (_theResult____h346087[12] ?
																		    6'd44 :
																		    (_theResult____h346087[11] ?
																		       6'd45 :
																		       (_theResult____h346087[10] ?
																			  6'd46 :
																			  (_theResult____h346087[9] ?
																			     6'd47 :
																			     (_theResult____h346087[8] ?
																				6'd48 :
																				(_theResult____h346087[7] ?
																				   6'd49 :
																				   (_theResult____h346087[6] ?
																				      6'd50 :
																				      (_theResult____h346087[5] ?
																					 6'd51 :
																					 (_theResult____h346087[4] ?
																					    6'd52 :
																					    (_theResult____h346087[3] ?
																					       6'd53 :
																					       (_theResult____h346087[2] ?
																						  6'd54 :
																						  (_theResult____h346087[1] ?
																						     6'd55 :
																						     (_theResult____h346087[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 =
	     (_theResult____h391786[56] ?
		6'd0 :
		(_theResult____h391786[55] ?
		   6'd1 :
		   (_theResult____h391786[54] ?
		      6'd2 :
		      (_theResult____h391786[53] ?
			 6'd3 :
			 (_theResult____h391786[52] ?
			    6'd4 :
			    (_theResult____h391786[51] ?
			       6'd5 :
			       (_theResult____h391786[50] ?
				  6'd6 :
				  (_theResult____h391786[49] ?
				     6'd7 :
				     (_theResult____h391786[48] ?
					6'd8 :
					(_theResult____h391786[47] ?
					   6'd9 :
					   (_theResult____h391786[46] ?
					      6'd10 :
					      (_theResult____h391786[45] ?
						 6'd11 :
						 (_theResult____h391786[44] ?
						    6'd12 :
						    (_theResult____h391786[43] ?
						       6'd13 :
						       (_theResult____h391786[42] ?
							  6'd14 :
							  (_theResult____h391786[41] ?
							     6'd15 :
							     (_theResult____h391786[40] ?
								6'd16 :
								(_theResult____h391786[39] ?
								   6'd17 :
								   (_theResult____h391786[38] ?
								      6'd18 :
								      (_theResult____h391786[37] ?
									 6'd19 :
									 (_theResult____h391786[36] ?
									    6'd20 :
									    (_theResult____h391786[35] ?
									       6'd21 :
									       (_theResult____h391786[34] ?
										  6'd22 :
										  (_theResult____h391786[33] ?
										     6'd23 :
										     (_theResult____h391786[32] ?
											6'd24 :
											(_theResult____h391786[31] ?
											   6'd25 :
											   (_theResult____h391786[30] ?
											      6'd26 :
											      (_theResult____h391786[29] ?
												 6'd27 :
												 (_theResult____h391786[28] ?
												    6'd28 :
												    (_theResult____h391786[27] ?
												       6'd29 :
												       (_theResult____h391786[26] ?
													  6'd30 :
													  (_theResult____h391786[25] ?
													     6'd31 :
													     (_theResult____h391786[24] ?
														6'd32 :
														(_theResult____h391786[23] ?
														   6'd33 :
														   (_theResult____h391786[22] ?
														      6'd34 :
														      (_theResult____h391786[21] ?
															 6'd35 :
															 (_theResult____h391786[20] ?
															    6'd36 :
															    (_theResult____h391786[19] ?
															       6'd37 :
															       (_theResult____h391786[18] ?
																  6'd38 :
																  (_theResult____h391786[17] ?
																     6'd39 :
																     (_theResult____h391786[16] ?
																	6'd40 :
																	(_theResult____h391786[15] ?
																	   6'd41 :
																	   (_theResult____h391786[14] ?
																	      6'd42 :
																	      (_theResult____h391786[13] ?
																		 6'd43 :
																		 (_theResult____h391786[12] ?
																		    6'd44 :
																		    (_theResult____h391786[11] ?
																		       6'd45 :
																		       (_theResult____h391786[10] ?
																			  6'd46 :
																			  (_theResult____h391786[9] ?
																			     6'd47 :
																			     (_theResult____h391786[8] ?
																				6'd48 :
																				(_theResult____h391786[7] ?
																				   6'd49 :
																				   (_theResult____h391786[6] ?
																				      6'd50 :
																				      (_theResult____h391786[5] ?
																					 6'd51 :
																					 (_theResult____h391786[4] ?
																					    6'd52 :
																					    (_theResult____h391786[3] ?
																					       6'd53 :
																					       (_theResult____h391786[2] ?
																						  6'd54 :
																						  (_theResult____h391786[1] ?
																						     6'd55 :
																						     (_theResult____h391786[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 =
	     (_theResult____h437481[56] ?
		6'd0 :
		(_theResult____h437481[55] ?
		   6'd1 :
		   (_theResult____h437481[54] ?
		      6'd2 :
		      (_theResult____h437481[53] ?
			 6'd3 :
			 (_theResult____h437481[52] ?
			    6'd4 :
			    (_theResult____h437481[51] ?
			       6'd5 :
			       (_theResult____h437481[50] ?
				  6'd6 :
				  (_theResult____h437481[49] ?
				     6'd7 :
				     (_theResult____h437481[48] ?
					6'd8 :
					(_theResult____h437481[47] ?
					   6'd9 :
					   (_theResult____h437481[46] ?
					      6'd10 :
					      (_theResult____h437481[45] ?
						 6'd11 :
						 (_theResult____h437481[44] ?
						    6'd12 :
						    (_theResult____h437481[43] ?
						       6'd13 :
						       (_theResult____h437481[42] ?
							  6'd14 :
							  (_theResult____h437481[41] ?
							     6'd15 :
							     (_theResult____h437481[40] ?
								6'd16 :
								(_theResult____h437481[39] ?
								   6'd17 :
								   (_theResult____h437481[38] ?
								      6'd18 :
								      (_theResult____h437481[37] ?
									 6'd19 :
									 (_theResult____h437481[36] ?
									    6'd20 :
									    (_theResult____h437481[35] ?
									       6'd21 :
									       (_theResult____h437481[34] ?
										  6'd22 :
										  (_theResult____h437481[33] ?
										     6'd23 :
										     (_theResult____h437481[32] ?
											6'd24 :
											(_theResult____h437481[31] ?
											   6'd25 :
											   (_theResult____h437481[30] ?
											      6'd26 :
											      (_theResult____h437481[29] ?
												 6'd27 :
												 (_theResult____h437481[28] ?
												    6'd28 :
												    (_theResult____h437481[27] ?
												       6'd29 :
												       (_theResult____h437481[26] ?
													  6'd30 :
													  (_theResult____h437481[25] ?
													     6'd31 :
													     (_theResult____h437481[24] ?
														6'd32 :
														(_theResult____h437481[23] ?
														   6'd33 :
														   (_theResult____h437481[22] ?
														      6'd34 :
														      (_theResult____h437481[21] ?
															 6'd35 :
															 (_theResult____h437481[20] ?
															    6'd36 :
															    (_theResult____h437481[19] ?
															       6'd37 :
															       (_theResult____h437481[18] ?
																  6'd38 :
																  (_theResult____h437481[17] ?
																     6'd39 :
																     (_theResult____h437481[16] ?
																	6'd40 :
																	(_theResult____h437481[15] ?
																	   6'd41 :
																	   (_theResult____h437481[14] ?
																	      6'd42 :
																	      (_theResult____h437481[13] ?
																		 6'd43 :
																		 (_theResult____h437481[12] ?
																		    6'd44 :
																		    (_theResult____h437481[11] ?
																		       6'd45 :
																		       (_theResult____h437481[10] ?
																			  6'd46 :
																			  (_theResult____h437481[9] ?
																			     6'd47 :
																			     (_theResult____h437481[8] ?
																				6'd48 :
																				(_theResult____h437481[7] ?
																				   6'd49 :
																				   (_theResult____h437481[6] ?
																				      6'd50 :
																				      (_theResult____h437481[5] ?
																					 6'd51 :
																					 (_theResult____h437481[4] ?
																					    6'd52 :
																					    (_theResult____h437481[3] ?
																					       6'd53 :
																					       (_theResult____h437481[2] ?
																						  6'd54 :
																						  (_theResult____h437481[1] ?
																						     6'd55 :
																						     (_theResult____h437481[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 =
	     (_theResult____h541724[56] ?
		6'd0 :
		(_theResult____h541724[55] ?
		   6'd1 :
		   (_theResult____h541724[54] ?
		      6'd2 :
		      (_theResult____h541724[53] ?
			 6'd3 :
			 (_theResult____h541724[52] ?
			    6'd4 :
			    (_theResult____h541724[51] ?
			       6'd5 :
			       (_theResult____h541724[50] ?
				  6'd6 :
				  (_theResult____h541724[49] ?
				     6'd7 :
				     (_theResult____h541724[48] ?
					6'd8 :
					(_theResult____h541724[47] ?
					   6'd9 :
					   (_theResult____h541724[46] ?
					      6'd10 :
					      (_theResult____h541724[45] ?
						 6'd11 :
						 (_theResult____h541724[44] ?
						    6'd12 :
						    (_theResult____h541724[43] ?
						       6'd13 :
						       (_theResult____h541724[42] ?
							  6'd14 :
							  (_theResult____h541724[41] ?
							     6'd15 :
							     (_theResult____h541724[40] ?
								6'd16 :
								(_theResult____h541724[39] ?
								   6'd17 :
								   (_theResult____h541724[38] ?
								      6'd18 :
								      (_theResult____h541724[37] ?
									 6'd19 :
									 (_theResult____h541724[36] ?
									    6'd20 :
									    (_theResult____h541724[35] ?
									       6'd21 :
									       (_theResult____h541724[34] ?
										  6'd22 :
										  (_theResult____h541724[33] ?
										     6'd23 :
										     (_theResult____h541724[32] ?
											6'd24 :
											(_theResult____h541724[31] ?
											   6'd25 :
											   (_theResult____h541724[30] ?
											      6'd26 :
											      (_theResult____h541724[29] ?
												 6'd27 :
												 (_theResult____h541724[28] ?
												    6'd28 :
												    (_theResult____h541724[27] ?
												       6'd29 :
												       (_theResult____h541724[26] ?
													  6'd30 :
													  (_theResult____h541724[25] ?
													     6'd31 :
													     (_theResult____h541724[24] ?
														6'd32 :
														(_theResult____h541724[23] ?
														   6'd33 :
														   (_theResult____h541724[22] ?
														      6'd34 :
														      (_theResult____h541724[21] ?
															 6'd35 :
															 (_theResult____h541724[20] ?
															    6'd36 :
															    (_theResult____h541724[19] ?
															       6'd37 :
															       (_theResult____h541724[18] ?
																  6'd38 :
																  (_theResult____h541724[17] ?
																     6'd39 :
																     (_theResult____h541724[16] ?
																	6'd40 :
																	(_theResult____h541724[15] ?
																	   6'd41 :
																	   (_theResult____h541724[14] ?
																	      6'd42 :
																	      (_theResult____h541724[13] ?
																		 6'd43 :
																		 (_theResult____h541724[12] ?
																		    6'd44 :
																		    (_theResult____h541724[11] ?
																		       6'd45 :
																		       (_theResult____h541724[10] ?
																			  6'd46 :
																			  (_theResult____h541724[9] ?
																			     6'd47 :
																			     (_theResult____h541724[8] ?
																				6'd48 :
																				(_theResult____h541724[7] ?
																				   6'd49 :
																				   (_theResult____h541724[6] ?
																				      6'd50 :
																				      (_theResult____h541724[5] ?
																					 6'd51 :
																					 (_theResult____h541724[4] ?
																					    6'd52 :
																					    (_theResult____h541724[3] ?
																					       6'd53 :
																					       (_theResult____h541724[2] ?
																						  6'd54 :
																						  (_theResult____h541724[1] ?
																						     6'd55 :
																						     (_theResult____h541724[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 =
	     (_theResult____h502871[56] ?
		6'd0 :
		(_theResult____h502871[55] ?
		   6'd1 :
		   (_theResult____h502871[54] ?
		      6'd2 :
		      (_theResult____h502871[53] ?
			 6'd3 :
			 (_theResult____h502871[52] ?
			    6'd4 :
			    (_theResult____h502871[51] ?
			       6'd5 :
			       (_theResult____h502871[50] ?
				  6'd6 :
				  (_theResult____h502871[49] ?
				     6'd7 :
				     (_theResult____h502871[48] ?
					6'd8 :
					(_theResult____h502871[47] ?
					   6'd9 :
					   (_theResult____h502871[46] ?
					      6'd10 :
					      (_theResult____h502871[45] ?
						 6'd11 :
						 (_theResult____h502871[44] ?
						    6'd12 :
						    (_theResult____h502871[43] ?
						       6'd13 :
						       (_theResult____h502871[42] ?
							  6'd14 :
							  (_theResult____h502871[41] ?
							     6'd15 :
							     (_theResult____h502871[40] ?
								6'd16 :
								(_theResult____h502871[39] ?
								   6'd17 :
								   (_theResult____h502871[38] ?
								      6'd18 :
								      (_theResult____h502871[37] ?
									 6'd19 :
									 (_theResult____h502871[36] ?
									    6'd20 :
									    (_theResult____h502871[35] ?
									       6'd21 :
									       (_theResult____h502871[34] ?
										  6'd22 :
										  (_theResult____h502871[33] ?
										     6'd23 :
										     (_theResult____h502871[32] ?
											6'd24 :
											(_theResult____h502871[31] ?
											   6'd25 :
											   (_theResult____h502871[30] ?
											      6'd26 :
											      (_theResult____h502871[29] ?
												 6'd27 :
												 (_theResult____h502871[28] ?
												    6'd28 :
												    (_theResult____h502871[27] ?
												       6'd29 :
												       (_theResult____h502871[26] ?
													  6'd30 :
													  (_theResult____h502871[25] ?
													     6'd31 :
													     (_theResult____h502871[24] ?
														6'd32 :
														(_theResult____h502871[23] ?
														   6'd33 :
														   (_theResult____h502871[22] ?
														      6'd34 :
														      (_theResult____h502871[21] ?
															 6'd35 :
															 (_theResult____h502871[20] ?
															    6'd36 :
															    (_theResult____h502871[19] ?
															       6'd37 :
															       (_theResult____h502871[18] ?
																  6'd38 :
																  (_theResult____h502871[17] ?
																     6'd39 :
																     (_theResult____h502871[16] ?
																	6'd40 :
																	(_theResult____h502871[15] ?
																	   6'd41 :
																	   (_theResult____h502871[14] ?
																	      6'd42 :
																	      (_theResult____h502871[13] ?
																		 6'd43 :
																		 (_theResult____h502871[12] ?
																		    6'd44 :
																		    (_theResult____h502871[11] ?
																		       6'd45 :
																		       (_theResult____h502871[10] ?
																			  6'd46 :
																			  (_theResult____h502871[9] ?
																			     6'd47 :
																			     (_theResult____h502871[8] ?
																				6'd48 :
																				(_theResult____h502871[7] ?
																				   6'd49 :
																				   (_theResult____h502871[6] ?
																				      6'd50 :
																				      (_theResult____h502871[5] ?
																					 6'd51 :
																					 (_theResult____h502871[4] ?
																					    6'd52 :
																					    (_theResult____h502871[3] ?
																					       6'd53 :
																					       (_theResult____h502871[2] ?
																						  6'd54 :
																						  (_theResult____h502871[1] ?
																						     6'd55 :
																						     (_theResult____h502871[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9610 =
	     (_theResult____h581028[56] ?
		6'd0 :
		(_theResult____h581028[55] ?
		   6'd1 :
		   (_theResult____h581028[54] ?
		      6'd2 :
		      (_theResult____h581028[53] ?
			 6'd3 :
			 (_theResult____h581028[52] ?
			    6'd4 :
			    (_theResult____h581028[51] ?
			       6'd5 :
			       (_theResult____h581028[50] ?
				  6'd6 :
				  (_theResult____h581028[49] ?
				     6'd7 :
				     (_theResult____h581028[48] ?
					6'd8 :
					(_theResult____h581028[47] ?
					   6'd9 :
					   (_theResult____h581028[46] ?
					      6'd10 :
					      (_theResult____h581028[45] ?
						 6'd11 :
						 (_theResult____h581028[44] ?
						    6'd12 :
						    (_theResult____h581028[43] ?
						       6'd13 :
						       (_theResult____h581028[42] ?
							  6'd14 :
							  (_theResult____h581028[41] ?
							     6'd15 :
							     (_theResult____h581028[40] ?
								6'd16 :
								(_theResult____h581028[39] ?
								   6'd17 :
								   (_theResult____h581028[38] ?
								      6'd18 :
								      (_theResult____h581028[37] ?
									 6'd19 :
									 (_theResult____h581028[36] ?
									    6'd20 :
									    (_theResult____h581028[35] ?
									       6'd21 :
									       (_theResult____h581028[34] ?
										  6'd22 :
										  (_theResult____h581028[33] ?
										     6'd23 :
										     (_theResult____h581028[32] ?
											6'd24 :
											(_theResult____h581028[31] ?
											   6'd25 :
											   (_theResult____h581028[30] ?
											      6'd26 :
											      (_theResult____h581028[29] ?
												 6'd27 :
												 (_theResult____h581028[28] ?
												    6'd28 :
												    (_theResult____h581028[27] ?
												       6'd29 :
												       (_theResult____h581028[26] ?
													  6'd30 :
													  (_theResult____h581028[25] ?
													     6'd31 :
													     (_theResult____h581028[24] ?
														6'd32 :
														(_theResult____h581028[23] ?
														   6'd33 :
														   (_theResult____h581028[22] ?
														      6'd34 :
														      (_theResult____h581028[21] ?
															 6'd35 :
															 (_theResult____h581028[20] ?
															    6'd36 :
															    (_theResult____h581028[19] ?
															       6'd37 :
															       (_theResult____h581028[18] ?
																  6'd38 :
																  (_theResult____h581028[17] ?
																     6'd39 :
																     (_theResult____h581028[16] ?
																	6'd40 :
																	(_theResult____h581028[15] ?
																	   6'd41 :
																	   (_theResult____h581028[14] ?
																	      6'd42 :
																	      (_theResult____h581028[13] ?
																		 6'd43 :
																		 (_theResult____h581028[12] ?
																		    6'd44 :
																		    (_theResult____h581028[11] ?
																		       6'd45 :
																		       (_theResult____h581028[10] ?
																			  6'd46 :
																			  (_theResult____h581028[9] ?
																			     6'd47 :
																			     (_theResult____h581028[8] ?
																				6'd48 :
																				(_theResult____h581028[7] ?
																				   6'd49 :
																				   (_theResult____h581028[6] ?
																				      6'd50 :
																				      (_theResult____h581028[5] ?
																					 6'd51 :
																					 (_theResult____h581028[4] ?
																					    6'd52 :
																					    (_theResult____h581028[3] ?
																					       6'd53 :
																					       (_theResult____h581028[2] ?
																						  6'd54 :
																						  (_theResult____h581028[1] ?
																						     6'd55 :
																						     (_theResult____h581028[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4798 =
	     (_theResult____h363726[56] ?
		6'd0 :
		(_theResult____h363726[55] ?
		   6'd1 :
		   (_theResult____h363726[54] ?
		      6'd2 :
		      (_theResult____h363726[53] ?
			 6'd3 :
			 (_theResult____h363726[52] ?
			    6'd4 :
			    (_theResult____h363726[51] ?
			       6'd5 :
			       (_theResult____h363726[50] ?
				  6'd6 :
				  (_theResult____h363726[49] ?
				     6'd7 :
				     (_theResult____h363726[48] ?
					6'd8 :
					(_theResult____h363726[47] ?
					   6'd9 :
					   (_theResult____h363726[46] ?
					      6'd10 :
					      (_theResult____h363726[45] ?
						 6'd11 :
						 (_theResult____h363726[44] ?
						    6'd12 :
						    (_theResult____h363726[43] ?
						       6'd13 :
						       (_theResult____h363726[42] ?
							  6'd14 :
							  (_theResult____h363726[41] ?
							     6'd15 :
							     (_theResult____h363726[40] ?
								6'd16 :
								(_theResult____h363726[39] ?
								   6'd17 :
								   (_theResult____h363726[38] ?
								      6'd18 :
								      (_theResult____h363726[37] ?
									 6'd19 :
									 (_theResult____h363726[36] ?
									    6'd20 :
									    (_theResult____h363726[35] ?
									       6'd21 :
									       (_theResult____h363726[34] ?
										  6'd22 :
										  (_theResult____h363726[33] ?
										     6'd23 :
										     (_theResult____h363726[32] ?
											6'd24 :
											(_theResult____h363726[31] ?
											   6'd25 :
											   (_theResult____h363726[30] ?
											      6'd26 :
											      (_theResult____h363726[29] ?
												 6'd27 :
												 (_theResult____h363726[28] ?
												    6'd28 :
												    (_theResult____h363726[27] ?
												       6'd29 :
												       (_theResult____h363726[26] ?
													  6'd30 :
													  (_theResult____h363726[25] ?
													     6'd31 :
													     (_theResult____h363726[24] ?
														6'd32 :
														(_theResult____h363726[23] ?
														   6'd33 :
														   (_theResult____h363726[22] ?
														      6'd34 :
														      (_theResult____h363726[21] ?
															 6'd35 :
															 (_theResult____h363726[20] ?
															    6'd36 :
															    (_theResult____h363726[19] ?
															       6'd37 :
															       (_theResult____h363726[18] ?
																  6'd38 :
																  (_theResult____h363726[17] ?
																     6'd39 :
																     (_theResult____h363726[16] ?
																	6'd40 :
																	(_theResult____h363726[15] ?
																	   6'd41 :
																	   (_theResult____h363726[14] ?
																	      6'd42 :
																	      (_theResult____h363726[13] ?
																		 6'd43 :
																		 (_theResult____h363726[12] ?
																		    6'd44 :
																		    (_theResult____h363726[11] ?
																		       6'd45 :
																		       (_theResult____h363726[10] ?
																			  6'd46 :
																			  (_theResult____h363726[9] ?
																			     6'd47 :
																			     (_theResult____h363726[8] ?
																				6'd48 :
																				(_theResult____h363726[7] ?
																				   6'd49 :
																				   (_theResult____h363726[6] ?
																				      6'd50 :
																				      (_theResult____h363726[5] ?
																					 6'd51 :
																					 (_theResult____h363726[4] ?
																					    6'd52 :
																					    (_theResult____h363726[3] ?
																					       6'd53 :
																					       (_theResult____h363726[2] ?
																						  6'd54 :
																						  (_theResult____h363726[1] ?
																						     6'd55 :
																						     (_theResult____h363726[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 =
	     (_theResult____h409423[56] ?
		6'd0 :
		(_theResult____h409423[55] ?
		   6'd1 :
		   (_theResult____h409423[54] ?
		      6'd2 :
		      (_theResult____h409423[53] ?
			 6'd3 :
			 (_theResult____h409423[52] ?
			    6'd4 :
			    (_theResult____h409423[51] ?
			       6'd5 :
			       (_theResult____h409423[50] ?
				  6'd6 :
				  (_theResult____h409423[49] ?
				     6'd7 :
				     (_theResult____h409423[48] ?
					6'd8 :
					(_theResult____h409423[47] ?
					   6'd9 :
					   (_theResult____h409423[46] ?
					      6'd10 :
					      (_theResult____h409423[45] ?
						 6'd11 :
						 (_theResult____h409423[44] ?
						    6'd12 :
						    (_theResult____h409423[43] ?
						       6'd13 :
						       (_theResult____h409423[42] ?
							  6'd14 :
							  (_theResult____h409423[41] ?
							     6'd15 :
							     (_theResult____h409423[40] ?
								6'd16 :
								(_theResult____h409423[39] ?
								   6'd17 :
								   (_theResult____h409423[38] ?
								      6'd18 :
								      (_theResult____h409423[37] ?
									 6'd19 :
									 (_theResult____h409423[36] ?
									    6'd20 :
									    (_theResult____h409423[35] ?
									       6'd21 :
									       (_theResult____h409423[34] ?
										  6'd22 :
										  (_theResult____h409423[33] ?
										     6'd23 :
										     (_theResult____h409423[32] ?
											6'd24 :
											(_theResult____h409423[31] ?
											   6'd25 :
											   (_theResult____h409423[30] ?
											      6'd26 :
											      (_theResult____h409423[29] ?
												 6'd27 :
												 (_theResult____h409423[28] ?
												    6'd28 :
												    (_theResult____h409423[27] ?
												       6'd29 :
												       (_theResult____h409423[26] ?
													  6'd30 :
													  (_theResult____h409423[25] ?
													     6'd31 :
													     (_theResult____h409423[24] ?
														6'd32 :
														(_theResult____h409423[23] ?
														   6'd33 :
														   (_theResult____h409423[22] ?
														      6'd34 :
														      (_theResult____h409423[21] ?
															 6'd35 :
															 (_theResult____h409423[20] ?
															    6'd36 :
															    (_theResult____h409423[19] ?
															       6'd37 :
															       (_theResult____h409423[18] ?
																  6'd38 :
																  (_theResult____h409423[17] ?
																     6'd39 :
																     (_theResult____h409423[16] ?
																	6'd40 :
																	(_theResult____h409423[15] ?
																	   6'd41 :
																	   (_theResult____h409423[14] ?
																	      6'd42 :
																	      (_theResult____h409423[13] ?
																		 6'd43 :
																		 (_theResult____h409423[12] ?
																		    6'd44 :
																		    (_theResult____h409423[11] ?
																		       6'd45 :
																		       (_theResult____h409423[10] ?
																			  6'd46 :
																			  (_theResult____h409423[9] ?
																			     6'd47 :
																			     (_theResult____h409423[8] ?
																				6'd48 :
																				(_theResult____h409423[7] ?
																				   6'd49 :
																				   (_theResult____h409423[6] ?
																				      6'd50 :
																				      (_theResult____h409423[5] ?
																					 6'd51 :
																					 (_theResult____h409423[4] ?
																					    6'd52 :
																					    (_theResult____h409423[3] ?
																					       6'd53 :
																					       (_theResult____h409423[2] ?
																						  6'd54 :
																						  (_theResult____h409423[1] ?
																						     6'd55 :
																						     (_theResult____h409423[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 =
	     (_theResult____h455118[56] ?
		6'd0 :
		(_theResult____h455118[55] ?
		   6'd1 :
		   (_theResult____h455118[54] ?
		      6'd2 :
		      (_theResult____h455118[53] ?
			 6'd3 :
			 (_theResult____h455118[52] ?
			    6'd4 :
			    (_theResult____h455118[51] ?
			       6'd5 :
			       (_theResult____h455118[50] ?
				  6'd6 :
				  (_theResult____h455118[49] ?
				     6'd7 :
				     (_theResult____h455118[48] ?
					6'd8 :
					(_theResult____h455118[47] ?
					   6'd9 :
					   (_theResult____h455118[46] ?
					      6'd10 :
					      (_theResult____h455118[45] ?
						 6'd11 :
						 (_theResult____h455118[44] ?
						    6'd12 :
						    (_theResult____h455118[43] ?
						       6'd13 :
						       (_theResult____h455118[42] ?
							  6'd14 :
							  (_theResult____h455118[41] ?
							     6'd15 :
							     (_theResult____h455118[40] ?
								6'd16 :
								(_theResult____h455118[39] ?
								   6'd17 :
								   (_theResult____h455118[38] ?
								      6'd18 :
								      (_theResult____h455118[37] ?
									 6'd19 :
									 (_theResult____h455118[36] ?
									    6'd20 :
									    (_theResult____h455118[35] ?
									       6'd21 :
									       (_theResult____h455118[34] ?
										  6'd22 :
										  (_theResult____h455118[33] ?
										     6'd23 :
										     (_theResult____h455118[32] ?
											6'd24 :
											(_theResult____h455118[31] ?
											   6'd25 :
											   (_theResult____h455118[30] ?
											      6'd26 :
											      (_theResult____h455118[29] ?
												 6'd27 :
												 (_theResult____h455118[28] ?
												    6'd28 :
												    (_theResult____h455118[27] ?
												       6'd29 :
												       (_theResult____h455118[26] ?
													  6'd30 :
													  (_theResult____h455118[25] ?
													     6'd31 :
													     (_theResult____h455118[24] ?
														6'd32 :
														(_theResult____h455118[23] ?
														   6'd33 :
														   (_theResult____h455118[22] ?
														      6'd34 :
														      (_theResult____h455118[21] ?
															 6'd35 :
															 (_theResult____h455118[20] ?
															    6'd36 :
															    (_theResult____h455118[19] ?
															       6'd37 :
															       (_theResult____h455118[18] ?
																  6'd38 :
																  (_theResult____h455118[17] ?
																     6'd39 :
																     (_theResult____h455118[16] ?
																	6'd40 :
																	(_theResult____h455118[15] ?
																	   6'd41 :
																	   (_theResult____h455118[14] ?
																	      6'd42 :
																	      (_theResult____h455118[13] ?
																		 6'd43 :
																		 (_theResult____h455118[12] ?
																		    6'd44 :
																		    (_theResult____h455118[11] ?
																		       6'd45 :
																		       (_theResult____h455118[10] ?
																			  6'd46 :
																			  (_theResult____h455118[9] ?
																			     6'd47 :
																			     (_theResult____h455118[8] ?
																				6'd48 :
																				(_theResult____h455118[7] ?
																				   6'd49 :
																				   (_theResult____h455118[6] ?
																				      6'd50 :
																				      (_theResult____h455118[5] ?
																					 6'd51 :
																					 (_theResult____h455118[4] ?
																					    6'd52 :
																					    (_theResult____h455118[3] ?
																					       6'd53 :
																					       (_theResult____h455118[2] ?
																						  6'd54 :
																						  (_theResult____h455118[1] ?
																						     6'd55 :
																						     (_theResult____h455118[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10424 =
	     (_theResult___fst_exp__h549960 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ;
  assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10691 =
	     (_theResult___fst_exp__h549960 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	       32'hFFFFFFFF ||
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard41734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200) ;
  assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d8939 =
	     (_theResult___fst_exp__h511107 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard02881_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148) ;
  assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9654 =
	     (_theResult___fst_exp__h589264 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ;
  assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9922 =
	     (_theResult___fst_exp__h589264 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
	       32'hFFFFFFFF ||
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard81038_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169) ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4310 =
	     (guard__h346097 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
	       _theResult___fst_exp__h354198 :
	       _theResult___exp__h354714 ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4313 =
	     (guard__h346097 == 2'b0) ?
	       _theResult___fst_exp__h354198 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		  _theResult___exp__h354714 :
		  _theResult___fst_exp__h354198) ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957 =
	     (guard__h346097 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
	       sfdin__h354192[56:34] :
	       _theResult___sfd__h354715 ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959 =
	     (guard__h346097 == 2'b0) ?
	       sfdin__h354192[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		  _theResult___sfd__h354715 :
		  sfdin__h354192[56:34]) ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5702 =
	     (guard__h391796 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
	       _theResult___fst_exp__h399895 :
	       _theResult___exp__h400411 ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5705 =
	     (guard__h391796 == 2'b0) ?
	       _theResult___fst_exp__h399895 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		  _theResult___exp__h400411 :
		  _theResult___fst_exp__h399895) ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349 =
	     (guard__h391796 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
	       sfdin__h399889[56:34] :
	       _theResult___sfd__h400412 ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351 =
	     (guard__h391796 == 2'b0) ?
	       sfdin__h399889[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		  _theResult___sfd__h400412 :
		  sfdin__h399889[56:34]) ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7094 =
	     (guard__h437491 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
	       _theResult___fst_exp__h445590 :
	       _theResult___exp__h446106 ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7097 =
	     (guard__h437491 == 2'b0) ?
	       _theResult___fst_exp__h445590 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		  _theResult___exp__h446106 :
		  _theResult___fst_exp__h445590) ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7741 =
	     (guard__h437491 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
	       sfdin__h445584[56:34] :
	       _theResult___sfd__h446107 ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7743 =
	     (guard__h437491 == 2'b0) ?
	       sfdin__h445584[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		  _theResult___sfd__h446107 :
		  sfdin__h445584[56:34]) ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536 =
	     (guard__h541734 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
	       _theResult___fst_exp__h549960 :
	       _theResult___exp__h550689 ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538 =
	     (guard__h541734 == 2'b0) ?
	       _theResult___fst_exp__h549960 :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
		  _theResult___exp__h550689 :
		  _theResult___fst_exp__h549960) ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619 =
	     (guard__h541734 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
	       sfdin__h549954[56:5] :
	       _theResult___sfd__h550690 ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621 =
	     (guard__h541734 == 2'b0) ?
	       sfdin__h549954[56:5] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
		  _theResult___sfd__h550690 :
		  sfdin__h549954[56:5]) ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056 =
	     (guard__h502881 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
	       _theResult___fst_exp__h511107 :
	       _theResult___exp__h511836 ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9058 =
	     (guard__h502881 == 2'b0) ?
	       _theResult___fst_exp__h511107 :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
		  _theResult___exp__h511836 :
		  _theResult___fst_exp__h511107) ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140 =
	     (guard__h502881 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
	       sfdin__h511101[56:5] :
	       _theResult___sfd__h511837 ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142 =
	     (guard__h502881 == 2'b0) ?
	       sfdin__h511101[56:5] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
		  _theResult___sfd__h511837 :
		  sfdin__h511101[56:5]) ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766 =
	     (guard__h581038 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
	       _theResult___fst_exp__h589264 :
	       _theResult___exp__h589993 ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768 =
	     (guard__h581038 == 2'b0) ?
	       _theResult___fst_exp__h589264 :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
		  _theResult___exp__h589993 :
		  _theResult___fst_exp__h589264) ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9849 =
	     (guard__h581038 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
	       sfdin__h589258[56:5] :
	       _theResult___sfd__h589994 ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9851 =
	     (guard__h581038 == 2'b0) ?
	       sfdin__h589258[56:5] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
		  _theResult___sfd__h589994 :
		  sfdin__h589258[56:5]) ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4857 =
	     (guard__h363736 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
	       _theResult___fst_exp__h371964 :
	       _theResult___exp__h372480 ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4859 =
	     (guard__h363736 == 2'b0) ?
	       _theResult___fst_exp__h371964 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		  _theResult___exp__h372480 :
		  _theResult___fst_exp__h371964) ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5003 =
	     (guard__h363736 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
	       sfdin__h371958[56:34] :
	       _theResult___sfd__h372481 ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5005 =
	     (guard__h363736 == 2'b0) ?
	       sfdin__h371958[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		  _theResult___sfd__h372481 :
		  sfdin__h371958[56:34]) ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6249 =
	     (guard__h409433 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
	       _theResult___fst_exp__h417661 :
	       _theResult___exp__h418177 ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6251 =
	     (guard__h409433 == 2'b0) ?
	       _theResult___fst_exp__h417661 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		  _theResult___exp__h418177 :
		  _theResult___fst_exp__h417661) ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6395 =
	     (guard__h409433 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
	       sfdin__h417655[56:34] :
	       _theResult___sfd__h418178 ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6397 =
	     (guard__h409433 == 2'b0) ?
	       sfdin__h417655[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		  _theResult___sfd__h418178 :
		  sfdin__h417655[56:34]) ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7641 =
	     (guard__h455128 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
	       _theResult___fst_exp__h463356 :
	       _theResult___exp__h463872 ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7643 =
	     (guard__h455128 == 2'b0) ?
	       _theResult___fst_exp__h463356 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		  _theResult___exp__h463872 :
		  _theResult___fst_exp__h463356) ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7787 =
	     (guard__h455128 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
	       sfdin__h463350[56:34] :
	       _theResult___sfd__h463873 ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7789 =
	     (guard__h455128 == 2'b0) ?
	       sfdin__h463350[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		  _theResult___sfd__h463873 :
		  sfdin__h463350[56:34]) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10498 =
	     (guard__h532422 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
	       _theResult___fst_exp__h540383 :
	       _theResult___exp__h541038 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10500 =
	     (guard__h532422 == 2'b0) ?
	       _theResult___fst_exp__h540383 :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
		  _theResult___exp__h541038 :
		  _theResult___fst_exp__h540383) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567 =
	     (guard__h550803 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
	       _theResult___fst_exp__h558793 :
	       _theResult___exp__h559473 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10569 =
	     (guard__h550803 == 2'b0) ?
	       _theResult___fst_exp__h558793 :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
		  _theResult___exp__h559473 :
		  _theResult___fst_exp__h558793) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10593 =
	     (guard__h532422 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
	       _theResult___snd__h540334[56:5] :
	       _theResult___sfd__h541039 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10595 =
	     (guard__h532422 == 2'b0) ?
	       _theResult___snd__h540334[56:5] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
		  _theResult___sfd__h541039 :
		  _theResult___snd__h540334[56:5]) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638 =
	     (guard__h550803 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
	       _theResult___snd__h558739[56:5] :
	       _theResult___sfd__h559474 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640 =
	     (guard__h550803 == 2'b0) ?
	       _theResult___snd__h558739[56:5] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
		  _theResult___sfd__h559474 :
		  _theResult___snd__h558739[56:5]) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9013 =
	     (guard__h493569 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
	       _theResult___fst_exp__h501530 :
	       _theResult___exp__h502185 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9015 =
	     (guard__h493569 == 2'b0) ?
	       _theResult___fst_exp__h501530 :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
		  _theResult___exp__h502185 :
		  _theResult___fst_exp__h501530) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9087 =
	     (guard__h511950 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
	       _theResult___fst_exp__h519940 :
	       _theResult___exp__h520620 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9089 =
	     (guard__h511950 == 2'b0) ?
	       _theResult___fst_exp__h519940 :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
		  _theResult___exp__h520620 :
		  _theResult___fst_exp__h519940) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113 =
	     (guard__h493569 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
	       _theResult___snd__h501481[56:5] :
	       _theResult___sfd__h502186 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115 =
	     (guard__h493569 == 2'b0) ?
	       _theResult___snd__h501481[56:5] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
		  _theResult___sfd__h502186 :
		  _theResult___snd__h501481[56:5]) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159 =
	     (guard__h511950 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
	       _theResult___snd__h519886[56:5] :
	       _theResult___sfd__h520621 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161 =
	     (guard__h511950 == 2'b0) ?
	       _theResult___snd__h519886[56:5] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
		  _theResult___sfd__h520621 :
		  _theResult___snd__h519886[56:5]) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9728 =
	     (guard__h571726 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
	       _theResult___fst_exp__h579687 :
	       _theResult___exp__h580342 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9730 =
	     (guard__h571726 == 2'b0) ?
	       _theResult___fst_exp__h579687 :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
		  _theResult___exp__h580342 :
		  _theResult___fst_exp__h579687) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797 =
	     (guard__h590107 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
	       _theResult___fst_exp__h598097 :
	       _theResult___exp__h598777 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799 =
	     (guard__h590107 == 2'b0) ?
	       _theResult___fst_exp__h598097 :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
		  _theResult___exp__h598777 :
		  _theResult___fst_exp__h598097) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9823 =
	     (guard__h571726 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
	       _theResult___snd__h579638[56:5] :
	       _theResult___sfd__h580343 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9825 =
	     (guard__h571726 == 2'b0) ?
	       _theResult___snd__h579638[56:5] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
		  _theResult___sfd__h580343 :
		  _theResult___snd__h579638[56:5]) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9868 =
	     (guard__h590107 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
	       _theResult___snd__h598043[56:5] :
	       _theResult___sfd__h598778 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9870 =
	     (guard__h590107 == 2'b0) ?
	       _theResult___snd__h598043[56:5] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
		  _theResult___sfd__h598778 :
		  _theResult___snd__h598043[56:5]) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4532 =
	     (guard__h354806 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
	       _theResult___fst_exp__h362854 :
	       _theResult___exp__h363296 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4534 =
	     (guard__h354806 == 2'b0) ?
	       _theResult___fst_exp__h362854 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		  _theResult___exp__h363296 :
		  _theResult___fst_exp__h362854) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4926 =
	     (guard__h372572 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
	       _theResult___fst_exp__h380649 :
	       _theResult___exp__h381116 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4928 =
	     (guard__h372572 == 2'b0) ?
	       _theResult___fst_exp__h380649 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		  _theResult___exp__h381116 :
		  _theResult___fst_exp__h380649) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976 =
	     (guard__h354806 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
	       _theResult___snd__h362805[56:34] :
	       _theResult___sfd__h363297 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978 =
	     (guard__h354806 == 2'b0) ?
	       _theResult___snd__h362805[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		  _theResult___sfd__h363297 :
		  _theResult___snd__h362805[56:34]) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 =
	     (guard__h372572 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
	       _theResult___snd__h380595[56:34] :
	       _theResult___sfd__h381117 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 =
	     (guard__h372572 == 2'b0) ?
	       _theResult___snd__h380595[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		  _theResult___sfd__h381117 :
		  _theResult___snd__h380595[56:34]) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5924 =
	     (guard__h400503 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
	       _theResult___fst_exp__h408551 :
	       _theResult___exp__h408993 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5926 =
	     (guard__h400503 == 2'b0) ?
	       _theResult___fst_exp__h408551 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		  _theResult___exp__h408993 :
		  _theResult___fst_exp__h408551) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6318 =
	     (guard__h418269 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
	       _theResult___fst_exp__h426346 :
	       _theResult___exp__h426813 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6320 =
	     (guard__h418269 == 2'b0) ?
	       _theResult___fst_exp__h426346 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		  _theResult___exp__h426813 :
		  _theResult___fst_exp__h426346) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368 =
	     (guard__h400503 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
	       _theResult___snd__h408502[56:34] :
	       _theResult___sfd__h408994 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370 =
	     (guard__h400503 == 2'b0) ?
	       _theResult___snd__h408502[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		  _theResult___sfd__h408994 :
		  _theResult___snd__h408502[56:34]) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 =
	     (guard__h418269 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
	       _theResult___snd__h426292[56:34] :
	       _theResult___sfd__h426814 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 =
	     (guard__h418269 == 2'b0) ?
	       _theResult___snd__h426292[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		  _theResult___sfd__h426814 :
		  _theResult___snd__h426292[56:34]) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7316 =
	     (guard__h446198 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
	       _theResult___fst_exp__h454246 :
	       _theResult___exp__h454688 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7318 =
	     (guard__h446198 == 2'b0) ?
	       _theResult___fst_exp__h454246 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		  _theResult___exp__h454688 :
		  _theResult___fst_exp__h454246) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7710 =
	     (guard__h463964 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
	       _theResult___fst_exp__h472041 :
	       _theResult___exp__h472508 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7712 =
	     (guard__h463964 == 2'b0) ?
	       _theResult___fst_exp__h472041 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		  _theResult___exp__h472508 :
		  _theResult___fst_exp__h472041) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7760 =
	     (guard__h446198 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
	       _theResult___snd__h454197[56:34] :
	       _theResult___sfd__h454689 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762 =
	     (guard__h446198 == 2'b0) ?
	       _theResult___snd__h454197[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		  _theResult___sfd__h454689 :
		  _theResult___snd__h454197[56:34]) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 =
	     (guard__h463964 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
	       _theResult___snd__h471987[56:34] :
	       _theResult___sfd__h472509 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 =
	     (guard__h463964 == 2'b0) ?
	       _theResult___snd__h471987[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		  _theResult___sfd__h472509 :
		  _theResult___snd__h471987[56:34]) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10470 =
	     (_theResult___fst_exp__h558793 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard50803_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10676 =
	     (_theResult___fst_exp__h540383 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	       32'hFFFFFFFF ||
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10703 =
	     (_theResult___fst_exp__h558793 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	       32'hFFFFFFFF ||
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8985 =
	     (_theResult___fst_exp__h519940 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard11950_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9700 =
	     (_theResult___fst_exp__h598097 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard90107_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9907 =
	     (_theResult___fst_exp__h579687 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
	       32'hFFFFFFFF ||
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard71726_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9934 =
	     (_theResult___fst_exp__h598097 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
	       32'hFFFFFFFF ||
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard90107_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171) ;
  assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824 =
	     (_theResult____h651123 == 16'd0 &&
	      (csrf_prv_reg == 2'd0 ||
	       csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ?
	       enabled_ints__h651694 :
	       _theResult____h651123 ;
  assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13052 =
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[10] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[11] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[12] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] ||
	     checkForException___d13008[4] ||
	     csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13045 ||
	     fetchStage$pipelines_0_first[231:200] == 32'h10500073 &&
	     csrf_tw_reg &&
	     csrf_prv_reg != 2'd3 ;
  assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13771 =
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[10] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[11] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[12] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] ||
	     checkForException___d13008[4] ||
	     csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13517 ;
  assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13808 =
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[10] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[11] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[12] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] ||
	     checkForException___d13713[4] ||
	     csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13806 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 =
	     ((f2_exp__h521136 == 8'd0) ?
		(f2_sfd__h521137[22] ?
		   6'd2 :
		   (f2_sfd__h521137[21] ?
		      6'd3 :
		      (f2_sfd__h521137[20] ?
			 6'd4 :
			 (f2_sfd__h521137[19] ?
			    6'd5 :
			    (f2_sfd__h521137[18] ?
			       6'd6 :
			       (f2_sfd__h521137[17] ?
				  6'd7 :
				  (f2_sfd__h521137[16] ?
				     6'd8 :
				     (f2_sfd__h521137[15] ?
					6'd9 :
					(f2_sfd__h521137[14] ?
					   6'd10 :
					   (f2_sfd__h521137[13] ?
					      6'd11 :
					      (f2_sfd__h521137[12] ?
						 6'd12 :
						 (f2_sfd__h521137[11] ?
						    6'd13 :
						    (f2_sfd__h521137[10] ?
						       6'd14 :
						       (f2_sfd__h521137[9] ?
							  6'd15 :
							  (f2_sfd__h521137[8] ?
							     6'd16 :
							     (f2_sfd__h521137[7] ?
								6'd17 :
								(f2_sfd__h521137[6] ?
								   6'd18 :
								   (f2_sfd__h521137[5] ?
								      6'd19 :
								      (f2_sfd__h521137[4] ?
									 6'd20 :
									 (f2_sfd__h521137[3] ?
									    6'd21 :
									    (f2_sfd__h521137[2] ?
									       6'd22 :
									       (f2_sfd__h521137[1] ?
										  6'd23 :
										  (f2_sfd__h521137[0] ?
										     6'd24 :
										     6'd57))))))))))))))))))))))) :
		6'd1) -
	     6'd1 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10474 =
	     (f2_exp__h521136 == 8'd255 && f2_sfd__h521137 != 23'd0 ||
	      (f2_exp__h521136 == 8'd255 || f2_exp__h521136 == 8'd0) &&
	      f2_sfd__h521137 == 23'd0) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
	       ((f2_exp__h521136 == 8'd0) ?
		  IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10129 :
		  IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10472) ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10651 =
	     (f2_exp__h521136 == 8'd255 && f2_sfd__h521137 != 23'd0) ?
	       _theResult___snd_fst_sfd__h521452 :
	       _theResult___fst_sfd__h559592 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10652 =
	     { (f2_exp__h521136 == 8'd255) ?
		 11'd2047 :
		 _theResult___fst_exp__h559588,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10651 } ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10706 =
	     (f2_exp__h521136 == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ?
		  (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 ?
		     coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
		     32'hFFFFFFFF ||
		     !coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
		     IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10676) :
		  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10678) :
	       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10705 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10707 =
	     (f2_exp__h521136 == 8'd255 && f2_sfd__h521137 != 23'd0 ||
	      (f2_exp__h521136 == 8'd255 || f2_exp__h521136 == 8'd0) &&
	      f2_sfd__h521137 == 23'd0) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	       32'hFFFFFFFF ||
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10706 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762 =
	     (f1_exp__h482142 == 8'd0) ?
	       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 &&
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[4] :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 &&
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 &&
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[4] ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10803 =
	     (f2_exp__h521136 == 8'd0) ?
	       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 &&
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[4] :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 &&
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 &&
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[4] ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10847 =
	     (f3_exp__h560440 == 8'd0) ?
	       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 &&
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[4] :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 &&
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 &&
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[4] ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10862 =
	     (f1_exp__h482142 == 8'd0) ?
	       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 &&
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[3] :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 &&
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 &&
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[3] ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10872 =
	     (f2_exp__h521136 == 8'd0) ?
	       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 &&
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[3] :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 &&
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 &&
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[3] ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10883 =
	     (f3_exp__h560440 == 8'd0) ?
	       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 &&
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[3] :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 &&
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 &&
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[3] ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10902 =
	     (f1_exp__h482142 == 8'd0) ?
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 ||
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[2] :
	       !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 ||
	       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10900 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10916 =
	     (f2_exp__h521136 == 8'd0) ?
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ||
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[2] :
	       !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 ||
	       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10914 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10931 =
	     (f3_exp__h560440 == 8'd0) ?
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ||
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[2] :
	       !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 ||
	       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10929 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10948 =
	     (f1_exp__h482142 == 8'd0) ?
	       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 &&
	       (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 ||
		_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[1]) :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 &&
	       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10946 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10960 =
	     (f2_exp__h521136 == 8'd0) ?
	       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 &&
	       (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 ||
		_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[1]) :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 &&
	       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10958 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973 =
	     (f3_exp__h560440 == 8'd0) ?
	       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 &&
	       (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 ||
		_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[1]) :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 &&
	       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10971 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10990 =
	     (f1_exp__h482142 == 8'd0) ?
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 ||
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[0] :
	       !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 ||
	       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10988 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11002 =
	     (f2_exp__h521136 == 8'd0) ?
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ||
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[0] :
	       !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 ||
	       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11000 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11015 =
	     (f3_exp__h560440 == 8'd0) ?
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ||
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[0] :
	       !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 ||
	       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11013 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 =
	     ((f1_exp__h482142 == 8'd0) ?
		(f1_sfd__h482143[22] ?
		   6'd2 :
		   (f1_sfd__h482143[21] ?
		      6'd3 :
		      (f1_sfd__h482143[20] ?
			 6'd4 :
			 (f1_sfd__h482143[19] ?
			    6'd5 :
			    (f1_sfd__h482143[18] ?
			       6'd6 :
			       (f1_sfd__h482143[17] ?
				  6'd7 :
				  (f1_sfd__h482143[16] ?
				     6'd8 :
				     (f1_sfd__h482143[15] ?
					6'd9 :
					(f1_sfd__h482143[14] ?
					   6'd10 :
					   (f1_sfd__h482143[13] ?
					      6'd11 :
					      (f1_sfd__h482143[12] ?
						 6'd12 :
						 (f1_sfd__h482143[11] ?
						    6'd13 :
						    (f1_sfd__h482143[10] ?
						       6'd14 :
						       (f1_sfd__h482143[9] ?
							  6'd15 :
							  (f1_sfd__h482143[8] ?
							     6'd16 :
							     (f1_sfd__h482143[7] ?
								6'd17 :
								(f1_sfd__h482143[6] ?
								   6'd18 :
								   (f1_sfd__h482143[5] ?
								      6'd19 :
								      (f1_sfd__h482143[4] ?
									 6'd20 :
									 (f1_sfd__h482143[3] ?
									    6'd21 :
									    (f1_sfd__h482143[2] ?
									       6'd22 :
									       (f1_sfd__h482143[1] ?
										  6'd23 :
										  (f1_sfd__h482143[0] ?
										     6'd24 :
										     6'd57))))))))))))))))))))))) :
		6'd1) -
	     6'd1 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8989 =
	     (f1_exp__h482142 == 8'd255 && f1_sfd__h482143 != 23'd0 ||
	      (f1_exp__h482142 == 8'd255 || f1_exp__h482142 == 8'd0) &&
	      f1_sfd__h482143 == 23'd0) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
	       ((f1_exp__h482142 == 8'd0) ?
		  IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8644 :
		  IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8987) ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9172 =
	     (f1_exp__h482142 == 8'd255 && f1_sfd__h482143 != 23'd0) ?
	       _theResult___snd_fst_sfd__h482458 :
	       _theResult___fst_sfd__h520739 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9173 =
	     { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8989,
	       (f1_exp__h482142 == 8'd255) ?
		 11'd2047 :
		 _theResult___fst_exp__h520735,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9172 } ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 =
	     ((f3_exp__h560440 == 8'd0) ?
		(f3_sfd__h560441[22] ?
		   6'd2 :
		   (f3_sfd__h560441[21] ?
		      6'd3 :
		      (f3_sfd__h560441[20] ?
			 6'd4 :
			 (f3_sfd__h560441[19] ?
			    6'd5 :
			    (f3_sfd__h560441[18] ?
			       6'd6 :
			       (f3_sfd__h560441[17] ?
				  6'd7 :
				  (f3_sfd__h560441[16] ?
				     6'd8 :
				     (f3_sfd__h560441[15] ?
					6'd9 :
					(f3_sfd__h560441[14] ?
					   6'd10 :
					   (f3_sfd__h560441[13] ?
					      6'd11 :
					      (f3_sfd__h560441[12] ?
						 6'd12 :
						 (f3_sfd__h560441[11] ?
						    6'd13 :
						    (f3_sfd__h560441[10] ?
						       6'd14 :
						       (f3_sfd__h560441[9] ?
							  6'd15 :
							  (f3_sfd__h560441[8] ?
							     6'd16 :
							     (f3_sfd__h560441[7] ?
								6'd17 :
								(f3_sfd__h560441[6] ?
								   6'd18 :
								   (f3_sfd__h560441[5] ?
								      6'd19 :
								      (f3_sfd__h560441[4] ?
									 6'd20 :
									 (f3_sfd__h560441[3] ?
									    6'd21 :
									    (f3_sfd__h560441[2] ?
									       6'd22 :
									       (f3_sfd__h560441[1] ?
										  6'd23 :
										  (f3_sfd__h560441[0] ?
										     6'd24 :
										     6'd57))))))))))))))))))))))) :
		6'd1) -
	     6'd1 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9704 =
	     (f3_exp__h560440 == 8'd255 && f3_sfd__h560441 != 23'd0 ||
	      (f3_exp__h560440 == 8'd255 || f3_exp__h560440 == 8'd0) &&
	      f3_sfd__h560441 == 23'd0) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
	       ((f3_exp__h560440 == 8'd0) ?
		  IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9359 :
		  IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9702) ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9881 =
	     (f3_exp__h560440 == 8'd255 && f3_sfd__h560441 != 23'd0) ?
	       _theResult___snd_fst_sfd__h560756 :
	       _theResult___fst_sfd__h598896 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9882 =
	     { (f3_exp__h560440 == 8'd255) ?
		 11'd2047 :
		 _theResult___fst_exp__h598892,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9881 } ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9937 =
	     (f3_exp__h560440 == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ?
		  (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 ?
		     coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
		     32'hFFFFFFFF ||
		     !coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
		     IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9907) :
		  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9909) :
	       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9936 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9938 =
	     (f3_exp__h560440 == 8'd255 && f3_sfd__h560441 != 23'd0 ||
	      (f3_exp__h560440 == 8'd255 || f3_exp__h560440 == 8'd0) &&
	      f3_sfd__h560441 == 23'd0) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
	       32'hFFFFFFFF ||
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9937 ;
  assign IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1851 =
	     IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1840 ?
	       4'd11 :
	       (IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1844 ?
		  4'd12 :
		  (IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1848 ?
		     4'd13 :
		     4'd15)) ;
  assign IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1853 =
	     IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1832 ?
	       4'd8 :
	       (IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1836 ?
		  4'd9 :
		  IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1851) ;
  assign IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1855 =
	     IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1824 ?
	       4'd6 :
	       (IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1828 ?
		  4'd7 :
		  IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1853) ;
  assign IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1857 =
	     IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1816 ?
	       4'd4 :
	       (IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1820 ?
		  4'd5 :
		  IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1855) ;
  assign IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1859 =
	     IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1808 ?
	       4'd2 :
	       (IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1812 ?
		  4'd3 :
		  IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1857) ;
  assign IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1861 =
	     IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1800 ?
	       4'd0 :
	       (IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1804 ?
		  4'd1 :
		  IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1859) ;
  assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13198 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
		4'd12 :
		IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
		4'd12) ?
	       4'd13 :
	       4'd15 ;
  assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13199 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
		4'd11 :
		IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
		4'd11) ?
	       4'd12 :
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13198 ;
  assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13200 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
		4'd10 :
		IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
		4'd10) ?
	       4'd11 :
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13199 ;
  assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13201 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
		4'd9 :
		IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
		4'd9) ?
	       4'd9 :
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13200 ;
  assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13202 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
		4'd8 :
		IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
		4'd8) ?
	       4'd8 :
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13201 ;
  assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13203 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
		4'd7 :
		IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
		4'd7) ?
	       4'd7 :
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13202 ;
  assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13204 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
		4'd6 :
		IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
		4'd6) ?
	       4'd6 :
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13203 ;
  assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13205 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
		4'd5 :
		IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
		4'd5) ?
	       4'd5 :
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13204 ;
  assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13206 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
		4'd4 :
		IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
		4'd4) ?
	       4'd4 :
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13205 ;
  assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13207 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
		4'd3 :
		IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
		4'd3) ?
	       4'd3 :
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13206 ;
  assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13208 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
		4'd2 :
		IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
		4'd2) ?
	       4'd2 :
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13207 ;
  assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13209 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
		4'd1 :
		IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
		4'd1) ?
	       4'd1 :
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13208 ;
  assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13210 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
		4'd0 :
		IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
		4'd0) ?
	       4'd0 :
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13209 ;
  assign IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463 =
	     { (mmio_cRqQ_enqReq_lat_0$whas ?
		  mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd1 :
		  mmio_cRqQ_enqReq_rl[77:76] == 2'd1) ?
		 2'd1 :
		 ((mmio_cRqQ_enqReq_lat_0$whas ?
		     mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd2 :
		     mmio_cRqQ_enqReq_rl[77:76] == 2'd2) ?
		    2'd2 :
		    2'd3),
	       mmio_cRqQ_enqReq_lat_0$whas ?
		 mmio_cRqQ_enqReq_lat_0$wget[75:72] :
		 mmio_cRqQ_enqReq_rl[75:72] } ;
  assign IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172 =
	     { (mmio_dataReqQ_enqReq_lat_0$whas ?
		  mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd1 :
		  mmio_dataReqQ_enqReq_rl[77:76] == 2'd1) ?
		 2'd1 :
		 ((mmio_dataReqQ_enqReq_lat_0$whas ?
		     mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd2 :
		     mmio_dataReqQ_enqReq_rl[77:76] == 2'd2) ?
		    2'd2 :
		    2'd3),
	       mmio_dataReqQ_enqReq_lat_0$whas ?
		 mmio_dataReqQ_enqReq_lat_0$wget[75:72] :
		 mmio_dataReqQ_enqReq_rl[75:72] } ;
  assign IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766 =
	     { (EN_mmioToPlatform_pRq_enq ?
		  mmio_pRqQ_enqReq_lat_0$wget[37:36] == 2'd1 :
		  mmio_pRqQ_enqReq_rl[37:36] == 2'd1) ?
		 2'd1 :
		 ((EN_mmioToPlatform_pRq_enq ?
		     mmio_pRqQ_enqReq_lat_0$wget[37:36] == 2'd2 :
		     mmio_pRqQ_enqReq_rl[37:36] == 2'd2) ?
		    2'd2 :
		    2'd3),
	       EN_mmioToPlatform_pRq_enq ?
		 mmio_pRqQ_enqReq_lat_0$wget[35:32] :
		 mmio_pRqQ_enqReq_rl[35:32] } ;
  assign IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627 =
	     (EN_mmioToPlatform_pRs_enq ?
		!mmio_pRsQ_enqReq_lat_0$wget[66] :
		!mmio_pRsQ_enqReq_rl[66]) ?
	       { EN_mmioToPlatform_pRs_enq ?
		   mmio_pRsQ_enqReq_lat_0$wget[65] :
		   mmio_pRsQ_enqReq_rl[65],
		 EN_mmioToPlatform_pRs_enq ?
		   mmio_pRsQ_enqReq_lat_0$wget[64:33] :
		   mmio_pRsQ_enqReq_rl[64:33],
		 EN_mmioToPlatform_pRs_enq ?
		   mmio_pRsQ_enqReq_lat_0$wget[32] :
		   mmio_pRsQ_enqReq_rl[32],
		 EN_mmioToPlatform_pRs_enq ?
		   mmio_pRsQ_enqReq_lat_0$wget[31:0] :
		   mmio_pRsQ_enqReq_rl[31:0] } :
	       { 1'h0,
		 EN_mmioToPlatform_pRs_enq ?
		   mmio_pRsQ_enqReq_lat_0$wget[64:0] :
		   mmio_pRsQ_enqReq_rl[64:0] } ;
  assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10129 =
	     (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ||
	      _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 ||
	      _theResult___fst_exp__h540383 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ;
  assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8644 =
	     (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 ||
	      _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 ||
	      _theResult___fst_exp__h501530 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard93569_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146) ;
  assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9359 =
	     (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ||
	      _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 ||
	      _theResult___fst_exp__h579687 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ;
  assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 =
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] ?
	       4'd0 :
	       (IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] ?
		  4'd1 :
		  ((IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] &&
		    !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2]) ?
		     4'd2 :
		     ((IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] &&
		       !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] &&
		       !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3]) ?
			4'd3 :
			((IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] &&
			  !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] &&
			  !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] &&
			  !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4]) ?
			   4'd4 :
			   ((IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] &&
			     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] &&
			     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] &&
			     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] &&
			     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] &&
			     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6]) ?
			      4'd5 :
			      ((IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] &&
				!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] &&
				!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] &&
				!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] &&
				!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] &&
				!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] &&
				!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7]) ?
				 4'd6 :
				 ((IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] &&
				   !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] &&
				   !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] &&
				   !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] &&
				   !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] &&
				   !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] &&
				   !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] &&
				   !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8]) ?
				    4'd7 :
				    ((IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[11] &&
				      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] &&
				      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] &&
				      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] &&
				      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] &&
				      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] &&
				      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] &&
				      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] &&
				      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] &&
				      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[10]) ?
				       4'd8 :
				       ((IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] &&
					 !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] &&
					 !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] &&
					 !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] &&
					 !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] &&
					 !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] &&
					 !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] &&
					 !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] &&
					 !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] &&
					 !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[10] &&
					 !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[11] &&
					 !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[12] &&
					 !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13]) ?
					  4'd9 :
					  4'd10))))))))) ;
  assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12237 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205) ?
	       coreFix_aluExe_0_bypassWire_1$whas &&
	       coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12218 :
	       coreFix_aluExe_0_bypassWire_0$whas ;
  assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12238 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12218)) ?
	       coreFix_aluExe_0_bypassWire_2$whas &&
	       coreFix_aluExe_0_bypassWire_2_wget__2224_BITS__ETC___d12226 :
	       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12237 ;
  assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12239 =
	     NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12229 ?
	       coreFix_aluExe_0_bypassWire_3$whas &&
	       coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
	       coreFix_aluExe_0_dispToRegQ$first[84:78] :
	       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12238 ;
  assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12262 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12244) ?
	       coreFix_aluExe_0_bypassWire_1$whas &&
	       coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12250 :
	       coreFix_aluExe_0_bypassWire_0$whas ;
  assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12263 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12244) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12250)) ?
	       coreFix_aluExe_0_bypassWire_2$whas &&
	       coreFix_aluExe_0_bypassWire_2_wget__2224_BITS__ETC___d12254 :
	       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12262 ;
  assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12264 =
	     NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12257 ?
	       coreFix_aluExe_0_bypassWire_3$whas &&
	       coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
	       coreFix_aluExe_0_dispToRegQ$first[76:70] :
	       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12263 ;
  assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12448 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205) ?
	       coreFix_aluExe_0_bypassWire_1$wget[63:0] :
	       coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
  assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12449 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12218)) ?
	       coreFix_aluExe_0_bypassWire_2$wget[63:0] :
	       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12448 ;
  assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12460 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12244) ?
	       coreFix_aluExe_0_bypassWire_1$wget[63:0] :
	       coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
  assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12461 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12244) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12250)) ?
	       coreFix_aluExe_0_bypassWire_2$wget[63:0] :
	       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12460 ;
  assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11377 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11345) ?
	       coreFix_aluExe_0_bypassWire_1$whas &&
	       coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11358 :
	       coreFix_aluExe_0_bypassWire_0$whas ;
  assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11378 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11345) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11358)) ?
	       coreFix_aluExe_1_bypassWire_2$whas &&
	       coreFix_aluExe_1_bypassWire_2_wget__1364_BITS__ETC___d11366 :
	       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11377 ;
  assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11379 =
	     NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11369 ?
	       coreFix_aluExe_1_bypassWire_3$whas &&
	       coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
	       coreFix_aluExe_1_dispToRegQ$first[84:78] :
	       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11378 ;
  assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11402 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11384) ?
	       coreFix_aluExe_0_bypassWire_1$whas &&
	       coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11390 :
	       coreFix_aluExe_0_bypassWire_0$whas ;
  assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11403 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11384) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11390)) ?
	       coreFix_aluExe_1_bypassWire_2$whas &&
	       coreFix_aluExe_1_bypassWire_2_wget__1364_BITS__ETC___d11394 :
	       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11402 ;
  assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11404 =
	     NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11397 ?
	       coreFix_aluExe_1_bypassWire_3$whas &&
	       coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
	       coreFix_aluExe_1_dispToRegQ$first[76:70] :
	       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11403 ;
  assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11774 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11345) ?
	       coreFix_aluExe_0_bypassWire_1$wget[63:0] :
	       coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
  assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11775 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11345) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11358)) ?
	       coreFix_aluExe_0_bypassWire_2$wget[63:0] :
	       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11774 ;
  assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11786 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11384) ?
	       coreFix_aluExe_0_bypassWire_1$wget[63:0] :
	       coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
  assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11787 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11384) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11390)) ?
	       coreFix_aluExe_0_bypassWire_2$wget[63:0] :
	       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11786 ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8241 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8209) ?
	       coreFix_aluExe_0_bypassWire_1$whas &&
	       coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8222 :
	       coreFix_aluExe_0_bypassWire_0$whas ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8242 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8209) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8222)) ?
	       coreFix_fpuMulDivExe_0_bypassWire_2$whas &&
	       coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8230 :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8241 ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8243 =
	     NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8233 ?
	       coreFix_fpuMulDivExe_0_bypassWire_3$whas &&
	       coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
	       coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8242 ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8265 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8247) ?
	       coreFix_aluExe_0_bypassWire_1$whas &&
	       coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8253 :
	       coreFix_aluExe_0_bypassWire_0$whas ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8266 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8247) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8253)) ?
	       coreFix_fpuMulDivExe_0_bypassWire_2$whas &&
	       coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8257 :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8265 ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8267 =
	     NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8260 ?
	       coreFix_fpuMulDivExe_0_bypassWire_3$whas &&
	       coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
	       coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8266 ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8289 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8271) ?
	       coreFix_aluExe_0_bypassWire_1$whas &&
	       coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8277 :
	       coreFix_aluExe_0_bypassWire_0$whas ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8290 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8271) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8277)) ?
	       coreFix_fpuMulDivExe_0_bypassWire_2$whas &&
	       coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8281 :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8289 ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8291 =
	     NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8284 ?
	       coreFix_fpuMulDivExe_0_bypassWire_3$whas &&
	       coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
	       coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8290 ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8336 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8209) ?
	       coreFix_aluExe_0_bypassWire_1$wget[63:0] :
	       coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8337 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8209) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8222)) ?
	       coreFix_aluExe_0_bypassWire_2$wget[63:0] :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8336 ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8347 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8247) ?
	       coreFix_aluExe_0_bypassWire_1$wget[63:0] :
	       coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8348 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8247) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8253)) ?
	       coreFix_aluExe_0_bypassWire_2$wget[63:0] :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8347 ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8358 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8271) ?
	       coreFix_aluExe_0_bypassWire_1$wget[63:0] :
	       coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8359 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8271) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8277)) ?
	       coreFix_aluExe_0_bypassWire_2$wget[63:0] :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8358 ;
  assign IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1603 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1571) ?
	       coreFix_aluExe_0_bypassWire_1$whas &&
	       coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1584 :
	       coreFix_aluExe_0_bypassWire_0$whas ;
  assign IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1604 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1571) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1584)) ?
	       coreFix_memExe_bypassWire_2$whas &&
	       coreFix_memExe_bypassWire_2_wget__590_BITS_70__ETC___d1592 :
	       IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1603 ;
  assign IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1605 =
	     NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1595 ?
	       coreFix_memExe_bypassWire_3$whas &&
	       coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
	       coreFix_memExe_dispToRegQ$first[61:55] :
	       IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1604 ;
  assign IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1627 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1609) ?
	       coreFix_aluExe_0_bypassWire_1$whas &&
	       coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1615 :
	       coreFix_aluExe_0_bypassWire_0$whas ;
  assign IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1628 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1609) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1615)) ?
	       coreFix_memExe_bypassWire_2$whas &&
	       coreFix_memExe_bypassWire_2_wget__590_BITS_70__ETC___d1619 :
	       IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1627 ;
  assign IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1629 =
	     NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1622 ?
	       coreFix_memExe_bypassWire_3$whas &&
	       coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
	       coreFix_memExe_dispToRegQ$first[53:47] :
	       IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1628 ;
  assign IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1648 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1571) ?
	       coreFix_aluExe_0_bypassWire_1$wget[63:0] :
	       coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
  assign IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1649 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1571) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1584)) ?
	       coreFix_aluExe_0_bypassWire_2$wget[63:0] :
	       IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1648 ;
  assign IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1659 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1609) ?
	       coreFix_aluExe_0_bypassWire_1$wget[63:0] :
	       coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
  assign IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1660 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1609) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1615)) ?
	       coreFix_aluExe_0_bypassWire_2$wget[63:0] :
	       IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1659 ;
  assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2086 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) ?
	       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2058 :
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
	       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2084 ;
  assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2103 =
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
	      2'd0 &&
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096) ?
	       coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N :
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N ;
  assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2510 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) ?
	       { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
		 IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2144,
		 IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2500 } :
	       { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
		  3'd3 &&
		  NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072) ?
		   { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:516],
		     4'd2 } :
		   { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
		     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
		     1'd1,
		     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] },
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
  assign IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 =
	     (!coreFix_memExe_dTlb$procResp[182] &&
	      coreFix_memExe_dTlb$procResp[12]) ?
	       CASE_coreFix_memExe_dTlbprocResp_BITS_177_TO__ETC__q20 :
	       CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q21 ;
  assign IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13923 =
	     ((!fetchStage$pipelines_0_canDeq ||
	       NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13481) &&
	      fetchStage$pipelines_1_canDeq) ?
	       fetchStage$RDY_pipelines_1_first &&
	       (fetchStage$pipelines_1_first[194:192] != 3'd1 ||
		!fetchStage$pipelines_0_canDeq ||
		fetchStage$RDY_pipelines_0_first) &&
	       IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13920 :
	       !fetchStage$pipelines_0_canDeq ||
	       fetchStage$RDY_pipelines_0_first ;
  assign IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13931 =
	     ((!fetchStage$pipelines_0_canDeq ||
	       NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13481) &&
	      fetchStage$pipelines_1_canDeq) ?
	       IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13930 :
	       fetchStage$pipelines_0_canDeq &&
	       NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13928 ;
  assign IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13846 =
	     (fetchStage$pipelines_1_first[194:192] == 3'd3 ||
	      fetchStage$pipelines_1_first[194:192] == 3'd4) ?
	       NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13829 :
	       ((fetchStage$pipelines_1_first[194:192] == 3'd2) ?
		  (!fetchStage$pipelines_0_canDeq ||
		   fetchStage$RDY_pipelines_0_first) &&
		  (regRenamingTable_rename_0_canRename__3418_AND__ETC___d13838 ||
		   NOT_regRenamingTable_rename_1_canRename__3545__ETC___d13816) :
		  _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13844) ;
  assign IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13930 =
	     NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13754 ?
	       IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 ||
	       fetchStage$pipelines_0_canDeq &&
	       (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
		specTagManager$canClaim) &&
	       regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 &&
	       IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 :
	       fetchStage$pipelines_0_canDeq &&
	       NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13928 ;
  assign IF_NOT_renameStage_rg_m_halt_req_2784_BIT_4_27_ETC___d13283 =
	     NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13102 ?
	       IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13210 :
	       ((renameStage_rg_m_halt_req[4] ?
		   renameStage_rg_m_halt_req[3:0] == 4'd0 :
		   IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 ==
		   4'd0) ?
		  4'd0 :
		  ((renameStage_rg_m_halt_req[4] ?
		      renameStage_rg_m_halt_req[3:0] == 4'd1 :
		      IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 ==
		      4'd1) ?
		     4'd1 :
		     ((renameStage_rg_m_halt_req[4] ?
			 renameStage_rg_m_halt_req[3:0] == 4'd3 :
			 IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 ==
			 4'd2) ?
			4'd3 :
			((renameStage_rg_m_halt_req[4] ?
			    renameStage_rg_m_halt_req[3:0] == 4'd4 :
			    IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 ==
			    4'd3) ?
			   4'd4 :
			   ((renameStage_rg_m_halt_req[4] ?
			       renameStage_rg_m_halt_req[3:0] == 4'd5 :
			       IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 ==
			       4'd4) ?
			      4'd5 :
			      ((renameStage_rg_m_halt_req[4] ?
				  renameStage_rg_m_halt_req[3:0] == 4'd7 :
				  IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 ==
				  4'd5) ?
				 4'd7 :
				 ((renameStage_rg_m_halt_req[4] ?
				     renameStage_rg_m_halt_req[3:0] == 4'd8 :
				     IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 ==
				     4'd6) ?
				    4'd8 :
				    ((renameStage_rg_m_halt_req[4] ?
					renameStage_rg_m_halt_req[3:0] ==
					4'd9 :
					IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 ==
					4'd7) ?
				       4'd9 :
				       ((renameStage_rg_m_halt_req[4] ?
					   renameStage_rg_m_halt_req[3:0] ==
					   4'd11 :
					   IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 ==
					   4'd8) ?
					  4'd11 :
					  ((renameStage_rg_m_halt_req[4] ?
					      renameStage_rg_m_halt_req[3:0] ==
					      4'd14 :
					      IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 ==
					      4'd9) ?
					     4'd14 :
					     4'd15)))))))))) ;
  assign IF_NOT_rob_deqPort_1_deq_data__5354_BIT_25_535_ETC___d15683 =
	     (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
	      rob$deqPort_1_deq_data[167] ||
	      rob$deqPort_1_deq_data[329:325] == 5'd0 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd21 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd17 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd18 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd13 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd16 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd15 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd19 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd20) ?
	       rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] :
	       rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ||
	       rob$deqPort_1_deq_data[26] ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10431 =
	     ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] ==
	       11'd0) ?
		12'd3074 :
		{ SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180[10],
		  SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180 }) -
	     12'd3074 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10472 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 ?
	       (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ?
		  IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10424 :
		  IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10470) :
	       coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[107] ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10705 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 ?
	       (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ?
		  IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10691 :
		  IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10703) :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10678 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10900 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ?
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[2] :
	       _theResult___fst_exp__h520723 == 11'd2047 &&
	       _theResult___fst_sfd__h520724 == 52'd0 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10914 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ?
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[2] :
	       _theResult___fst_exp__h559576 == 11'd2047 &&
	       _theResult___fst_sfd__h559577 == 52'd0 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10929 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ?
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[2] :
	       _theResult___fst_exp__h598880 == 11'd2047 &&
	       _theResult___fst_sfd__h598881 == 52'd0 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10946 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ?
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[1] :
	       _theResult___fst_exp__h519940 == 11'd0 &&
	       guard__h511950 != 2'b0 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10958 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ?
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[1] :
	       _theResult___fst_exp__h558793 == 11'd0 &&
	       guard__h550803 != 2'b0 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10971 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ?
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[1] :
	       _theResult___fst_exp__h598097 == 11'd0 &&
	       guard__h590107 != 2'b0 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10988 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ?
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[0] :
	       _theResult___fst_exp__h519940 != 11'd2047 &&
	       guard__h511950 != 2'b0 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11000 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ?
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[0] :
	       _theResult___fst_exp__h558793 != 11'd2047 &&
	       guard__h550803 != 2'b0 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11013 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ?
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[0] :
	       _theResult___fst_exp__h598097 != 11'd2047 &&
	       guard__h590107 != 2'b0 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8946 =
	     ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] ==
	       11'd0) ?
		12'd3074 :
		{ SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140[10],
		  SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140 }) -
	     12'd3074 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8987 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 ?
	       (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ?
		  IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d8939 :
		  IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8985) :
	       coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[171] ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9661 =
	     ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] ==
	       11'd0) ?
		12'd3074 :
		{ SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157[10],
		  SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157 }) -
	     12'd3074 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9702 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 ?
	       (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ?
		  IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9654 :
		  IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9700) :
	       coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[43] ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9936 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 ?
	       (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ?
		  IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9922 :
		  IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9934) :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9909 ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4872 =
	     ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] ==
	       8'd0) ?
		9'd386 :
		{ SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42[7],
		  SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42 }) -
	     9'd386 ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5099 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ?
	       ((_theResult___fst_exp__h371964 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084) :
	       ((_theResult___fst_exp__h380649 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097) ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5136 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ?
	       ((_theResult___fst_exp__h371964 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127) :
	       ((_theResult___fst_exp__h380649 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134) ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5227 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ?
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198[2] :
	       _theResult___fst_exp__h381197 == 8'd255 &&
	       _theResult___fst_sfd__h381198 == 23'd0 ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5240 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ?
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198[1] :
	       _theResult___fst_exp__h380649 == 8'd0 &&
	       guard__h372572 != 2'b0 ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5253 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ?
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198[0] :
	       _theResult___fst_exp__h380649 != 8'd255 &&
	       guard__h372572 != 2'b0 ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264 =
	     ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] ==
	       8'd0) ?
		9'd386 :
		{ SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q77[7],
		  SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q77 }) -
	     9'd386 ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6491 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ?
	       ((_theResult___fst_exp__h417661 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476) :
	       ((_theResult___fst_exp__h426346 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489) ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6528 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ?
	       ((_theResult___fst_exp__h417661 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519) :
	       ((_theResult___fst_exp__h426346 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526) ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6619 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ?
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590[2] :
	       _theResult___fst_exp__h426894 == 8'd255 &&
	       _theResult___fst_sfd__h426895 == 23'd0 ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6632 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ?
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590[1] :
	       _theResult___fst_exp__h426346 == 8'd0 &&
	       guard__h418269 != 2'b0 ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6645 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ?
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590[0] :
	       _theResult___fst_exp__h426346 != 8'd255 &&
	       guard__h418269 != 2'b0 ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656 =
	     ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] ==
	       8'd0) ?
		9'd386 :
		{ SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q112[7],
		  SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q112 }) -
	     9'd386 ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7883 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ?
	       ((_theResult___fst_exp__h463356 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868) :
	       ((_theResult___fst_exp__h472041 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881) ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7920 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ?
	       ((_theResult___fst_exp__h463356 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911) :
	       ((_theResult___fst_exp__h472041 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918) ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8011 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ?
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982[2] :
	       _theResult___fst_exp__h472589 == 8'd255 &&
	       _theResult___fst_sfd__h472590 == 23'd0 ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8024 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ?
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982[1] :
	       _theResult___fst_exp__h472041 == 8'd0 &&
	       guard__h463964 != 2'b0 ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8037 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ?
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982[0] :
	       _theResult___fst_exp__h472041 != 8'd255 &&
	       guard__h463964 != 2'b0 ;
  assign IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 =
	     checkForException___d13008[4] ?
	       CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234 :
	       4'd2 ;
  assign IF_commitStage_f_rob_data_first__4770_BITS_97__ETC___d14941 =
	     { CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q249,
	       commitStage_f_rob_data$D_OUT[95:32],
	       5'h0A,
	       commitStage_f_rob_data$D_OUT[26],
	       64'hAAAAAAAAAAAAAAAA,
	       x_prv__h713496,
	       pc__h713396,
	       x__h715654,
	       x__h715846,
	       commitStage_commitTrap[164:101] } ;
  assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2181_ETC___d12213 =
	     (coreFix_aluExe_0_dispToRegQ$RDY_first &&
	      coreFix_aluExe_0_bypassWire_0$whas &&
	      coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205) ?
	       !coreFix_aluExe_0_bypassWire_0$whas ||
	       coreFix_aluExe_0_dispToRegQ$RDY_first :
	       !coreFix_aluExe_0_bypassWire_1$whas ||
	       coreFix_aluExe_0_dispToRegQ$RDY_first ;
  assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2181_ETC___d12247 =
	     (coreFix_aluExe_0_dispToRegQ$RDY_first &&
	      coreFix_aluExe_0_bypassWire_0$whas &&
	      coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12244) ?
	       !coreFix_aluExe_0_bypassWire_0$whas ||
	       coreFix_aluExe_0_dispToRegQ$RDY_first :
	       !coreFix_aluExe_0_bypassWire_1$whas ||
	       coreFix_aluExe_0_dispToRegQ$RDY_first ;
  assign IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1321_ETC___d11353 =
	     (coreFix_aluExe_1_dispToRegQ$RDY_first &&
	      coreFix_aluExe_0_bypassWire_0$whas &&
	      coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11345) ?
	       !coreFix_aluExe_0_bypassWire_0$whas ||
	       coreFix_aluExe_1_dispToRegQ$RDY_first :
	       !coreFix_aluExe_0_bypassWire_1$whas ||
	       coreFix_aluExe_1_dispToRegQ$RDY_first ;
  assign IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1321_ETC___d11387 =
	     (coreFix_aluExe_1_dispToRegQ$RDY_first &&
	      coreFix_aluExe_0_bypassWire_0$whas &&
	      coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11384) ?
	       !coreFix_aluExe_0_bypassWire_0$whas ||
	       coreFix_aluExe_1_dispToRegQ$RDY_first :
	       !coreFix_aluExe_0_bypassWire_1$whas ||
	       coreFix_aluExe_1_dispToRegQ$RDY_first ;
  assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8217 =
	     (coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
	      coreFix_aluExe_0_bypassWire_0$whas &&
	      coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8209) ?
	       !coreFix_aluExe_0_bypassWire_0$whas ||
	       coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first :
	       !coreFix_aluExe_0_bypassWire_1$whas ||
	       coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ;
  assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8250 =
	     (coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
	      coreFix_aluExe_0_bypassWire_0$whas &&
	      coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8247) ?
	       !coreFix_aluExe_0_bypassWire_0$whas ||
	       coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first :
	       !coreFix_aluExe_0_bypassWire_1$whas ||
	       coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ;
  assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8274 =
	     (coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
	      coreFix_aluExe_0_bypassWire_0$whas &&
	      coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8271) ?
	       !coreFix_aluExe_0_bypassWire_0$whas ||
	       coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first :
	       !coreFix_aluExe_0_bypassWire_1$whas ||
	       coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6532 =
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[33] ?
	       ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
		 11'd2047 &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		 52'd0 ||
		 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
		  11'd2047 ||
		  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
		  11'd0) &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
		 52'd0) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6493) :
	       ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
		 11'd2047 &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		 52'd0 ||
		 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
		  11'd2047 ||
		  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
		  11'd0) &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
		 52'd0) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6530) ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 =
	     ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	       11'd0) ?
		(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] ?
		   6'd2 :
		   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] ?
		      6'd3 :
		      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] ?
			 6'd4 :
			 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[53] ?
			    6'd5 :
			    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[52] ?
			       6'd6 :
			       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[51] ?
				  6'd7 :
				  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[50] ?
				     6'd8 :
				     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[49] ?
					6'd9 :
					(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[48] ?
					   6'd10 :
					   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[47] ?
					      6'd11 :
					      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[46] ?
						 6'd12 :
						 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[45] ?
						    6'd13 :
						    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[44] ?
						       6'd14 :
						       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[43] ?
							  6'd15 :
							  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[42] ?
							     6'd16 :
							     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[41] ?
								6'd17 :
								(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[40] ?
								   6'd18 :
								   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[39] ?
								      6'd19 :
								      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[38] ?
									 6'd20 :
									 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[37] ?
									    6'd21 :
									    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[36] ?
									       6'd22 :
									       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[35] ?
										  6'd23 :
										  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[34] ?
										     6'd24 :
										     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[33] ?
											6'd25 :
											(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[32] ?
											   6'd26 :
											   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[31] ?
											      6'd27 :
											      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[30] ?
												 6'd28 :
												 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[29] ?
												    6'd29 :
												    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[28] ?
												       6'd30 :
												       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[27] ?
													  6'd31 :
													  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[26] ?
													     6'd32 :
													     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[25] ?
														6'd33 :
														(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[24] ?
														   6'd34 :
														   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[23] ?
														      6'd35 :
														      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[22] ?
															 6'd36 :
															 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[21] ?
															    6'd37 :
															    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[20] ?
															       6'd38 :
															       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[19] ?
																  6'd39 :
																  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[18] ?
																     6'd40 :
																     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[17] ?
																	6'd41 :
																	(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[16] ?
																	   6'd42 :
																	   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[15] ?
																	      6'd43 :
																	      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[14] ?
																		 6'd44 :
																		 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[13] ?
																		    6'd45 :
																		    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[12] ?
																		       6'd46 :
																		       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[11] ?
																			  6'd47 :
																			  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[10] ?
																			     6'd48 :
																			     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[9] ?
																				6'd49 :
																				(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[8] ?
																				   6'd50 :
																				   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] ?
																				      6'd51 :
																				      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] ?
																					 6'd52 :
																					 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ?
																					    6'd53 :
																					    6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
		6'd1) -
	     6'd1 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6493 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 ?
		  IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6461 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6463) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 ?
		  IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6491 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6463) ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6530 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 ?
		  IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6511 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6512) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 ?
		  IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6528 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6512) ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6594 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6576 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 &&
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 &&
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590[4] ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6605 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6601 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 &&
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 &&
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590[3] ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6621 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6613 :
	       !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 ||
	       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6619 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6634 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6628 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 &&
	       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6632 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6647 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6641 :
	       !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 ||
	       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6645 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 =
	     ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	       11'd0) ?
		(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] ?
		   6'd2 :
		   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] ?
		      6'd3 :
		      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] ?
			 6'd4 :
			 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[53] ?
			    6'd5 :
			    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[52] ?
			       6'd6 :
			       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[51] ?
				  6'd7 :
				  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[50] ?
				     6'd8 :
				     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[49] ?
					6'd9 :
					(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[48] ?
					   6'd10 :
					   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[47] ?
					      6'd11 :
					      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[46] ?
						 6'd12 :
						 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[45] ?
						    6'd13 :
						    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[44] ?
						       6'd14 :
						       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[43] ?
							  6'd15 :
							  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[42] ?
							     6'd16 :
							     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[41] ?
								6'd17 :
								(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[40] ?
								   6'd18 :
								   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[39] ?
								      6'd19 :
								      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[38] ?
									 6'd20 :
									 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[37] ?
									    6'd21 :
									    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[36] ?
									       6'd22 :
									       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[35] ?
										  6'd23 :
										  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[34] ?
										     6'd24 :
										     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[33] ?
											6'd25 :
											(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[32] ?
											   6'd26 :
											   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[31] ?
											      6'd27 :
											      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[30] ?
												 6'd28 :
												 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[29] ?
												    6'd29 :
												    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[28] ?
												       6'd30 :
												       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[27] ?
													  6'd31 :
													  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[26] ?
													     6'd32 :
													     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[25] ?
														6'd33 :
														(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[24] ?
														   6'd34 :
														   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[23] ?
														      6'd35 :
														      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[22] ?
															 6'd36 :
															 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[21] ?
															    6'd37 :
															    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[20] ?
															       6'd38 :
															       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[19] ?
																  6'd39 :
																  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[18] ?
																     6'd40 :
																     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[17] ?
																	6'd41 :
																	(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[16] ?
																	   6'd42 :
																	   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[15] ?
																	      6'd43 :
																	      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[14] ?
																		 6'd44 :
																		 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[13] ?
																		    6'd45 :
																		    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[12] ?
																		       6'd46 :
																		       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[11] ?
																			  6'd47 :
																			  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[10] ?
																			     6'd48 :
																			     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[9] ?
																				6'd49 :
																				(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[8] ?
																				   6'd50 :
																				   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] ?
																				      6'd51 :
																				      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] ?
																					 6'd52 :
																					 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ?
																					    6'd53 :
																					    6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
		6'd1) -
	     6'd1 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5101 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 ?
		  IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5069 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5071) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 ?
		  IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5099 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5071) ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5138 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 ?
		  IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5119 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5120) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 ?
		  IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5136 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5120) ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5202 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5184 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 &&
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 &&
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198[4] ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5213 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5209 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 &&
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 &&
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198[3] ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5229 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5221 :
	       !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 ||
	       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5227 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5242 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5236 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 &&
	       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5240 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5255 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5249 :
	       !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 ||
	       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5253 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 =
	     ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	       11'd0) ?
		(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] ?
		   6'd2 :
		   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[55] ?
		      6'd3 :
		      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[54] ?
			 6'd4 :
			 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[53] ?
			    6'd5 :
			    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[52] ?
			       6'd6 :
			       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[51] ?
				  6'd7 :
				  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[50] ?
				     6'd8 :
				     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[49] ?
					6'd9 :
					(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[48] ?
					   6'd10 :
					   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[47] ?
					      6'd11 :
					      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[46] ?
						 6'd12 :
						 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[45] ?
						    6'd13 :
						    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[44] ?
						       6'd14 :
						       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[43] ?
							  6'd15 :
							  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[42] ?
							     6'd16 :
							     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[41] ?
								6'd17 :
								(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[40] ?
								   6'd18 :
								   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[39] ?
								      6'd19 :
								      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[38] ?
									 6'd20 :
									 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[37] ?
									    6'd21 :
									    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[36] ?
									       6'd22 :
									       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[35] ?
										  6'd23 :
										  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[34] ?
										     6'd24 :
										     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[33] ?
											6'd25 :
											(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[32] ?
											   6'd26 :
											   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[31] ?
											      6'd27 :
											      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[30] ?
												 6'd28 :
												 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[29] ?
												    6'd29 :
												    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[28] ?
												       6'd30 :
												       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[27] ?
													  6'd31 :
													  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[26] ?
													     6'd32 :
													     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[25] ?
														6'd33 :
														(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[24] ?
														   6'd34 :
														   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[23] ?
														      6'd35 :
														      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[22] ?
															 6'd36 :
															 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[21] ?
															    6'd37 :
															    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[20] ?
															       6'd38 :
															       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[19] ?
																  6'd39 :
																  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[18] ?
																     6'd40 :
																     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[17] ?
																	6'd41 :
																	(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[16] ?
																	   6'd42 :
																	   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[15] ?
																	      6'd43 :
																	      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[14] ?
																		 6'd44 :
																		 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[13] ?
																		    6'd45 :
																		    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[12] ?
																		       6'd46 :
																		       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[11] ?
																			  6'd47 :
																			  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[10] ?
																			     6'd48 :
																			     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[9] ?
																				6'd49 :
																				(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[8] ?
																				   6'd50 :
																				   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[7] ?
																				      6'd51 :
																				      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[6] ?
																					 6'd52 :
																					 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ?
																					    6'd53 :
																					    6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
		6'd1) -
	     6'd1 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7885 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 ?
		  IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7853 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7855) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 ?
		  IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7883 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7855) ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7922 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 ?
		  IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7903 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7904) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 ?
		  IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7920 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7904) ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7986 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7968 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 &&
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 &&
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982[4] ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7997 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7993 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 &&
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 &&
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982[3] ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8013 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8005 :
	       !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 ||
	       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8011 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8026 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8020 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 &&
	       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8024 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8039 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8033 :
	       !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 ||
	       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8037 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5140 =
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[33] ?
	       ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
		 11'd2047 &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		 52'd0 ||
		 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
		  11'd2047 ||
		  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
		  11'd0) &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
		 52'd0) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5101) :
	       ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
		 11'd2047 &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		 52'd0 ||
		 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
		  11'd2047 ||
		  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
		  11'd0) &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
		 52'd0) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5138) ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7924 =
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[33] ?
	       ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
		 11'd2047 &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		 52'd0 ||
		 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
		  11'd2047 ||
		  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
		  11'd0) &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
		 52'd0) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7885) :
	       ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
		 11'd2047 &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		 52'd0 ||
		 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
		  11'd2047 ||
		  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
		  11'd0) &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
		 52'd0) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7922) ;
  assign IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8070 =
	     (coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] ==
	      2'd0) ?
	       coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[63:0] :
	       coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[127:64] ;
  assign IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133 =
	     IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8070[31:0] ;
  assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10654 =
	     coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] :
	       { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10474,
		 IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10652 } ;
  assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10678 =
	     coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	     32'hFFFFFFFF ||
	     !coreFix_fpuMulDivExe_0_regToExeQ$first[107] ;
  assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8430 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4) ?
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8396 &&
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 :
	       coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] != 3'd3 ||
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8428 ;
  assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9174 =
	     coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] :
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9173 ;
  assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9884 =
	     coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[75:12] :
	       { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9704,
		 IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9882 } ;
  assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9909 =
	     coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
	     !coreFix_fpuMulDivExe_0_regToExeQ$first[43] ;
  assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9940 =
	     coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
	       { !coreFix_fpuMulDivExe_0_regToExeQ$first[75],
		 coreFix_fpuMulDivExe_0_regToExeQ$first[74:12] } :
	       { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9938,
		 IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9882 } ;
  assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 =
	     coreFix_globalSpecUpdate_correctSpecTag_1$whas ?
	       result__h646700 :
	       w__h646695 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2084 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd3 &&
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072) ?
	       NOT_coreFix_memExe_respLrScAmoQ_full_952_953_A_ETC___d2082 :
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2104 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd3 &&
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072) ?
	       NOT_coreFix_memExe_respLrScAmoQ_full_952_953_A_ETC___d2082 :
	       IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2103 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2107 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
	      3'd1) ?
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite :
	       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2106 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2198 =
	     { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
		3'd7) ?
		 n___1__h198531 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448],
	       (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
		3'd6) ?
		 n___1__h198531 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384],
	       (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
		3'd5) ?
		 n___1__h198531 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320],
	       (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
		3'd4) ?
		 n___1__h198531 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2203 =
	     { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2198,
	       (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
		3'd3) ?
		 n___1__h198531 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192],
	       (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
		3'd2) ?
		 n___1__h198531 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2208 =
	     { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2203,
	       (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
		3'd1) ?
		 n___1__h198531 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64],
	       (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
		3'd0) ?
		 n___1__h198531 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2521 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd3 &&
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072) ?
	       { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:516],
		 4'd2,
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } :
	       { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
		 (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
		  2'd0 &&
		  !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096) ?
		   { 3'd1,
		     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } :
		   { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
		     1'd1,
		     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] },
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2523 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
	      3'd1) ?
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:0] :
	       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2522 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2539 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
	      3'd1) ?
	       3'd5 :
	       ((coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
		 2'd0 &&
		 !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096) ?
		  3'd2 :
		  3'd3) ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2550 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
	      3'd1) ?
	       58'h155555555555554 :
	       ((coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
		 2'd0 &&
		 !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096) ?
		  { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
		    2'd0,
		    coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518],
		    1'd0 } :
		  { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
		    coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
		    53'h15555555555555 }) ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd2) ?
	       x__h197128 :
	       (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150 ?
		  64'd0 :
		  64'd1) ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ?
	       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[3] :
	       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[3] ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3046 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry ||
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3058 =
	     _theResult_____2__h296523 == v__h295943 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3138 =
	     EN_dCacheToParent_fromP_enq ?
	       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] :
	       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[583] ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3153 =
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas ||
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3160 =
	     _theResult_____2__h304519 == v__h299288 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3180 =
	     EN_dCacheToParent_fromP_enq ?
	       !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] :
	       !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[583] ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3247 =
	     (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3138 &&
	      (EN_dCacheToParent_fromP_enq ?
		 !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[582] :
		 !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[582])) ?
	       { 516'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
		 EN_dCacheToParent_fromP_enq ?
		   coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[65:0] :
		   coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[65:0] } :
	       { EN_dCacheToParent_fromP_enq ?
		   coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[581:518] :
		   coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[581:518],
		 EN_dCacheToParent_fromP_enq ?
		   coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[517:516] :
		   coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[517:516],
		 !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT ||
		 IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3180 ||
		 (EN_dCacheToParent_fromP_enq ?
		    coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[515] :
		    coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[515]),
		 EN_dCacheToParent_fromP_enq ?
		   coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] :
		   coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3],
		 x__h302153 } ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3004 =
	     !MUX_flush_reservation$write_1__SEL_1 &&
	     (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[58] :
		coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58]) ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3012 =
	     MUX_flush_reservation$write_1__SEL_1 ?
	       58'h2AAAAAAAAAAAAAA :
	       (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ?
		  coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[57:0] :
		  coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0]) ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2047 =
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd3) ?
	       !coreFix_memExe_respLrScAmoQ_full :
	       !coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first ||
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	       3'd1 ||
	       coreFix_memExe_stb$RDY_deq ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2049 =
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd2) ?
	       !coreFix_memExe_respLrScAmoQ_full :
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	       3'd4 ||
	       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2047 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2050 =
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd0) ?
	       !coreFix_memExe_memRespLdQ_full :
	       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2049 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2058 =
	     IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2050 &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd4 ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
	      (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	       3'd1 ||
	       coreFix_memExe_stb$RDY_deq)) ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2106 =
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
	      (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
	       !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027)) ?
	       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2058 :
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
	       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2104 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2108 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
	       (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ?
		  IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2086 :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite) :
	       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2107 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2144 =
	     { (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <=
		coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82]) ?
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82] :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2522 =
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
	      (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
	       !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027)) ?
	       { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
		 IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2144,
		 IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2500 } :
	       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2521 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2570 =
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
	      (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
	       !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027)) ?
	       { 1'd1,
		 IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567 } :
	       65'h10000000000000001 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2704 =
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] ||
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2697 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2700) ?
	       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_pipelineResp_releaseEntry :
	       coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2713 =
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] ||
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2697 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2700) ?
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:512] :
	       { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518],
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
		   2'd0 :
		   coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0],
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515:512] } ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1998 =
	     { (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
		3'd7) ?
		 n__h194456 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448],
	       (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
		3'd6) ?
		 n__h194456 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384],
	       (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
		3'd5) ?
		 n__h194456 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2003 =
	     { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1998,
	       (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
		3'd4) ?
		 n__h194456 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256],
	       (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
		3'd3) ?
		 n__h194456 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2008 =
	     { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2003,
	       (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
		3'd2) ?
		 n__h194456 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128],
	       (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
		3'd1) ?
		 n__h194456 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[83:82] :
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[83:82]) :
	       2'd0 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2793 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[81:79] :
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[81:79]) :
	       3'd0 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2836 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[6:3] :
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[6:3]) :
	       4'd0 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3309 =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[72] :
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[72] ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3324 =
	     EN_dCacheToParent_rqToP_deq ||
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3332 =
	     _theResult_____2__h310513 == v__h309802 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3405 =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
	       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] :
	       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[579] ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3420 =
	     EN_dCacheToParent_rsToP_deq ||
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3428 =
	     _theResult_____2__h318367 == v__h313678 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3447 =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
	       !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] :
	       !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[579] ;
  assign IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 =
	     (coreFix_memExe_dTlb$procResp[177:175] == 3'd3) ?
	       4'd7 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ;
  assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1744 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[182] &&
	      coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
	       coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
	       coreFix_memExe_dTlb$procResp[177:175] != 3'd3 &&
	       !coreFix_memExe_dTlb$procResp[12] :
	       !coreFix_memExe_dTlb$procResp[12] &&
	       !coreFix_memExe_dTlb$procResp[182] ;
  assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1800 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[182] &&
	      coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
	       coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
	       4'd0 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
	       4'd0 ;
  assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1804 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[182] &&
	      coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
	       coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
	       4'd1 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
	       4'd1 ;
  assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1808 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[182] &&
	      coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
	       coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
	       4'd2 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
	       4'd2 ;
  assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1812 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[182] &&
	      coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
	       coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
	       4'd3 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
	       4'd3 ;
  assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1816 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[182] &&
	      coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
	       coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
	       4'd4 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
	       4'd4 ;
  assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1820 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[182] &&
	      coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
	       coreFix_memExe_dTlb$procResp[177:175] == 3'd2 ||
	       IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
	       4'd5 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
	       4'd5 ;
  assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1824 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[182] &&
	      coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
	       coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
	       4'd6 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
	       4'd6 ;
  assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1828 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[182] &&
	      coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
	       coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
	       4'd7 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
	       4'd7 ;
  assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1832 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[182] &&
	      coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
	       coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
	       4'd8 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
	       4'd8 ;
  assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1836 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[182] &&
	      coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
	       coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
	       4'd9 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
	       4'd9 ;
  assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1840 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[182] &&
	      coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
	       coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
	       4'd10 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
	       4'd10 ;
  assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1844 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[182] &&
	      coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
	       coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
	       4'd11 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
	       4'd11 ;
  assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1848 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[182] &&
	      coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
	       coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
	       4'd12 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
	       4'd12 ;
  assign IF_coreFix_memExe_dispToRegQ_RDY_first__549_AN_ETC___d1579 =
	     (coreFix_memExe_dispToRegQ$RDY_first &&
	      coreFix_aluExe_0_bypassWire_0$whas &&
	      coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1571) ?
	       !coreFix_aluExe_0_bypassWire_0$whas ||
	       coreFix_memExe_dispToRegQ$RDY_first :
	       !coreFix_aluExe_0_bypassWire_1$whas ||
	       coreFix_memExe_dispToRegQ$RDY_first ;
  assign IF_coreFix_memExe_dispToRegQ_RDY_first__549_AN_ETC___d1612 =
	     (coreFix_memExe_dispToRegQ$RDY_first &&
	      coreFix_aluExe_0_bypassWire_0$whas &&
	      coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1609) ?
	       !coreFix_aluExe_0_bypassWire_0$whas ||
	       coreFix_memExe_dispToRegQ$RDY_first :
	       !coreFix_aluExe_0_bypassWire_1$whas ||
	       coreFix_memExe_dispToRegQ$RDY_first ;
  assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3750 =
	     _theResult_____2__h331936 == v__h331504 ;
  assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3743 =
	     WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
	     coreFix_memExe_forwardQ_deqReq_rl ;
  assign IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3728 =
	     coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
	       coreFix_memExe_forwardQ_enqReq_lat_0$wget[69] :
	       coreFix_memExe_forwardQ_enqReq_rl[69] ;
  assign IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1377 =
	     coreFix_memExe_lsq$firstLd[94] ?
	       (coreFix_memExe_lsq$firstLd[92] ?
		  { 48'd0,
		    SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 } :
		  { {48{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359[15]}},
		    SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 }) :
	       (coreFix_memExe_lsq$firstLd[92] ?
		  { 56'd0,
		    SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 } :
		  { {56{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373[7]}},
		    SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 }) ;
  assign IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424 =
	     coreFix_memExe_lsq$firstLd[94] ?
	       (coreFix_memExe_lsq$firstLd[92] ?
		  { 48'd0,
		    SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 } :
		  { {48{SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407[15]}},
		    SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 }) :
	       (coreFix_memExe_lsq$firstLd[92] ?
		  { 56'd0,
		    SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 } :
		  { {56{SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420[7]}},
		    SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 }) ;
  assign IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378 =
	     coreFix_memExe_lsq$firstLd[96] ?
	       (coreFix_memExe_lsq$firstLd[92] ?
		  { 32'd0,
		    SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 } :
		  { {32{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348[31]}},
		    SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 }) :
	       IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1377 ;
  assign IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425 =
	     coreFix_memExe_lsq$firstLd[96] ?
	       (coreFix_memExe_lsq$firstLd[92] ?
		  { 32'd0,
		    SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 } :
		  { {32{SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398[31]}},
		    SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 }) :
	       IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424 ;
  assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3656 =
	     _theResult_____2__h328711 == v__h328279 ;
  assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3649 =
	     WILL_FIRE_RL_coreFix_memExe_doRespLdMem ||
	     coreFix_memExe_memRespLdQ_deqReq_rl ;
  assign IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3634 =
	     coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
	       coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[69] :
	       coreFix_memExe_memRespLdQ_enqReq_rl[69] ;
  assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		  coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[83:82] :
		  coreFix_memExe_reqLrScAmoQ_data_0_rl[83:82]) :
	       2'd0 ;
  assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		  coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[81:79] :
		  coreFix_memExe_reqLrScAmoQ_data_0_rl[81:79]) :
	       3'd0 ;
  assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		  coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[6:3] :
		  coreFix_memExe_reqLrScAmoQ_data_0_rl[6:3]) :
	       4'd0 ;
  assign IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3558 =
	     coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ?
	       coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[64] :
	       coreFix_memExe_respLrScAmoQ_enqReq_rl[64] ;
  assign IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 =
	     csrf_minstret_ehr_data_lat_0$whas ?
	       upd__h727778 :
	       csrf_minstret_ehr_data_rl ;
  assign IF_csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_c_ETC___d14935 =
	     csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 ?
	       { 43'd8192,
		 csrf_mxr_reg,
		 csrf_sum_reg,
		 3'd0,
		 csrf_fs_reg,
		 4'b0,
		 csrf_prv_reg[0],
		 2'b0,
		 csrf_ie_vec_1,
		 csrf_prev_ie_vec_0,
		 3'd0,
		 csrf_ie_vec_0 } :
	       { 40'd5120,
		 csrf_tsr_reg,
		 csrf_tw_reg,
		 csrf_tvm_reg,
		 csrf_mxr_reg,
		 csrf_sum_reg,
		 csrf_mprv_reg,
		 2'd0,
		 csrf_fs_reg,
		 csrf_prv_reg,
		 2'b0,
		 csrf_spp_reg,
		 csrf_ie_vec_3,
		 1'b0,
		 csrf_prev_ie_vec_1,
		 csrf_prev_ie_vec_0,
		 2'd0,
		 csrf_ie_vec_1,
		 csrf_ie_vec_0 } ;
  assign IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13450 =
	     (fetchStage$RDY_pipelines_0_first &&
	      (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	       specTagManager$canClaim) &&
	      regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444) ?
	       fetchStage$RDY_pipelines_0_first :
	       !regRenamingTable$rename_0_canRename ||
	       fetchStage$RDY_pipelines_0_first ;
  assign IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13848 =
	     (fetchStage$RDY_pipelines_1_first &&
	      (fetchStage$pipelines_1_first[194:192] == 3'd0 ||
	       fetchStage$pipelines_1_first[194:192] == 3'd1)) ?
	       (!fetchStage$pipelines_0_canDeq ||
		fetchStage$RDY_pipelines_0_first) &&
	       (SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787 ||
		fetchStage$pipelines_1_first[194:192] == 3'd1 &&
		regRenamingTable_rename_0_canRename__3418_AND__ETC___d13508 ||
		NOT_regRenamingTable_rename_1_canRename__3545__ETC___d13816) :
	       fetchStage$RDY_pipelines_1_first &&
	       IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13846 ;
  assign IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13920 =
	     (fetchStage$RDY_pipelines_1_first &&
	      NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13515 &&
	      NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13754) ?
	       IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13848 &&
	       (IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 ||
		!fetchStage$pipelines_0_canDeq ||
		fetchStage$RDY_pipelines_0_first) :
	       !fetchStage$pipelines_0_canDeq ||
	       fetchStage$RDY_pipelines_0_first ;
  assign IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13969 =
	     IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962 ||
	     fetchStage$RDY_pipelines_0_deq &&
	     regRenamingTable$RDY_rename_0_getRename &&
	     regRenamingTable$RDY_rename_0_claimRename &&
	     rob$RDY_enqPort_0_enq &&
	     (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	      specTagManager$RDY_claimSpecTag) ;
  assign IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14149 =
	     { fetchStage$pipelines_0_first[159:128],
	       IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137,
	       IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14140 ?
		 IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14143 :
		 { 1'h0,
		   IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 } } ;
  assign IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14099 =
	     IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14056 &&
	     IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13848 &&
	     (IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14083 ||
	      fetchStage$RDY_pipelines_1_deq &&
	      regRenamingTable$RDY_rename_1_getRename &&
	      regRenamingTable$RDY_rename_1_claimRename &&
	      rob_RDY_enqPort_1_enq__4085_AND_NOT_fetchStage_ETC___d14093) ;
  assign IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14321 =
	     (fetchStage$pipelines_1_first[194:192] == 3'd2 &&
	      NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268 &&
	      IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14275) ?
	       IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14276 :
	       { 1'h0,
		 IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14277 } ;
  assign IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14280 =
	     { fetchStage$pipelines_1_first[159:128],
	       IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14274,
	       IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14275 ?
		 IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14276 :
		 { 1'h0,
		   IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14277 } } ;
  assign IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 =
	     mmio_cRqQ_enqReq_lat_0$whas ?
	       mmio_cRqQ_enqReq_lat_0$wget[142] :
	       mmio_cRqQ_enqReq_rl[142] ;
  assign IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 =
	     CAN_FIRE_RL_mmio_handlePRq ?
	       mmio_cRsQ_enqReq_lat_0$wget[1] :
	       mmio_cRsQ_enqReq_rl[1] ;
  assign IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 =
	     mmio_dataReqQ_enqReq_lat_0$whas ?
	       mmio_dataReqQ_enqReq_lat_0$wget[142] :
	       mmio_dataReqQ_enqReq_rl[142] ;
  assign IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 =
	     CAN_FIRE_RL_mmio_sendDataResp ?
	       mmio_dataRespQ_enqReq_lat_0$wget[65] :
	       mmio_dataRespQ_enqReq_rl[65] ;
  assign IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 =
	     EN_mmioToPlatform_pRq_enq ?
	       mmio_pRqQ_enqReq_lat_0$wget[39] :
	       mmio_pRqQ_enqReq_rl[39] ;
  assign IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 =
	     EN_mmioToPlatform_pRs_enq ?
	       mmio_pRsQ_enqReq_lat_0$wget[67] :
	       mmio_pRsQ_enqReq_rl[67] ;
  assign IF_rob_deqPort_0_canDeq__5346_THEN_IF_NOT_rob__ETC___d15673 =
	     rob$deqPort_0_canDeq ? y_avValue_fst__h730973 : 5'd0 ;
  assign IF_rob_deqPort_0_canDeq__5346_THEN_IF_NOT_rob__ETC___d15692 =
	     rob$deqPort_0_canDeq ?
	       y_avValue_snd_snd_snd_fst__h731448 :
	       2'd0 ;
  assign IF_rob_deqPort_0_deq_data__4354_BITS_329_TO_32_ETC___d15205 =
	     (rob$deqPort_0_deq_data[329:325] == 5'd19) ?
	       csrf_sepc_csr :
	       csrf_mepc_csr ;
  assign IF_rob_deqPort_0_deq_data__4354_BITS_329_TO_32_ETC___d15314 =
	     (rob$deqPort_0_deq_data[329:325] == 5'd19) ?
	       { csrf_mpp_reg,
		 3'd0,
		 csrf_prev_ie_vec_3,
		 2'd1,
		 csrf_prev_ie_vec_0,
		 csrf_ie_vec_3,
		 1'b0,
		 csrf_prev_ie_vec_1,
		 csrf_ie_vec_0 } :
	       { 4'd0,
		 csrf_spp_reg,
		 2'd2,
		 csrf_prev_ie_vec_1,
		 csrf_prev_ie_vec_0,
		 csrf_prev_ie_vec_3,
		 1'b0,
		 csrf_ie_vec_1,
		 csrf_ie_vec_0 } ;
  assign IF_rob_deqPort_0_deq_data__4354_BITS_97_TO_96__ETC___d14527 =
	     { CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q252,
	       rob$deqPort_0_deq_data[95:32] } ;
  assign IF_rob_deqPort_1_canDeq__5351_THEN_IF_NOT_rob__ETC___d15684 =
	     rob$deqPort_1_canDeq ?
	       IF_NOT_rob_deqPort_1_deq_data__5354_BIT_25_535_ETC___d15683 :
	       rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ;
  assign IF_sfdin11101_BIT_4_THEN_2_ELSE_0__q139 =
	     sfdin__h511101[4] ? 2'd2 : 2'd0 ;
  assign IF_sfdin17655_BIT_33_THEN_2_ELSE_0__q74 =
	     sfdin__h417655[33] ? 2'd2 : 2'd0 ;
  assign IF_sfdin45584_BIT_33_THEN_2_ELSE_0__q99 =
	     sfdin__h445584[33] ? 2'd2 : 2'd0 ;
  assign IF_sfdin49954_BIT_4_THEN_2_ELSE_0__q179 =
	     sfdin__h549954[4] ? 2'd2 : 2'd0 ;
  assign IF_sfdin54192_BIT_33_THEN_2_ELSE_0__q29 =
	     sfdin__h354192[33] ? 2'd2 : 2'd0 ;
  assign IF_sfdin63350_BIT_33_THEN_2_ELSE_0__q109 =
	     sfdin__h463350[33] ? 2'd2 : 2'd0 ;
  assign IF_sfdin71958_BIT_33_THEN_2_ELSE_0__q39 =
	     sfdin__h371958[33] ? 2'd2 : 2'd0 ;
  assign IF_sfdin89258_BIT_4_THEN_2_ELSE_0__q156 =
	     sfdin__h589258[4] ? 2'd2 : 2'd0 ;
  assign IF_sfdin99889_BIT_33_THEN_2_ELSE_0__q64 =
	     sfdin__h399889[33] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd01481_BIT_4_THEN_2_ELSE_0__q135 =
	     _theResult___snd__h501481[4] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd08502_BIT_33_THEN_2_ELSE_0__q66 =
	     _theResult___snd__h408502[33] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd19886_BIT_4_THEN_2_ELSE_0__q142 =
	     _theResult___snd__h519886[4] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd26292_BIT_33_THEN_2_ELSE_0__q79 =
	     _theResult___snd__h426292[33] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd40334_BIT_4_THEN_2_ELSE_0__q175 =
	     _theResult___snd__h540334[4] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd54197_BIT_33_THEN_2_ELSE_0__q101 =
	     _theResult___snd__h454197[33] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd58739_BIT_4_THEN_2_ELSE_0__q182 =
	     _theResult___snd__h558739[4] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd62805_BIT_33_THEN_2_ELSE_0__q31 =
	     _theResult___snd__h362805[33] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd71987_BIT_33_THEN_2_ELSE_0__q114 =
	     _theResult___snd__h471987[33] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd79638_BIT_4_THEN_2_ELSE_0__q152 =
	     _theResult___snd__h579638[4] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd80595_BIT_33_THEN_2_ELSE_0__q44 =
	     _theResult___snd__h380595[33] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd98043_BIT_4_THEN_2_ELSE_0__q159 =
	     _theResult___snd__h598043[4] ? 2'd2 : 2'd0 ;
  assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5221 =
	     !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 ||
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169[2] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5181[2]) ;
  assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5249 =
	     !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 ||
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169[0] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5181[0]) ;
  assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6613 =
	     !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 ||
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6561[2] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6573[2]) ;
  assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6641 =
	     !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 ||
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6561[0] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6573[0]) ;
  assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8005 =
	     !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 ||
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7953[2] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965[2]) ;
  assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8033 =
	     !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 ||
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7953[0] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965[0]) ;
  assign NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13344 =
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[10] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[11] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[12] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] &&
	     !checkForException___d13008[4] &&
	     NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13337 &&
	     (fetchStage$pipelines_0_first[231:200] != 32'h10500073 ||
	      !csrf_tw_reg ||
	      csrf_prv_reg == 2'd3) ;
  assign NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13437 =
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[10] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[11] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[12] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] &&
	     !checkForException___d13008[4] &&
	     NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13435 ;
  assign NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13740 =
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[10] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[11] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[12] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] &&
	     !checkForException___d13713[4] &&
	     NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13738 ;
  assign NOT_IF_NOT_rob_deqPort_0_canDeq__5346_5347_OR__ETC___d15689 =
	     (fflags__h734227 & csrf_fflags_reg) != fflags__h734227 ||
	     csrf_fs_reg != 2'b11 &&
	     (IF_rob_deqPort_1_canDeq__5351_THEN_IF_NOT_rob__ETC___d15684 ||
	      fflags__h734227 != 5'd0) ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056 =
	     !f2_sfd__h521137[21] && !f2_sfd__h521137[20] &&
	     !f2_sfd__h521137[19] &&
	     !f2_sfd__h521137[18] &&
	     !f2_sfd__h521137[17] &&
	     !f2_sfd__h521137[16] &&
	     !f2_sfd__h521137[15] &&
	     !f2_sfd__h521137[14] &&
	     !f2_sfd__h521137[13] &&
	     !f2_sfd__h521137[12] &&
	     !f2_sfd__h521137[11] &&
	     !f2_sfd__h521137[10] &&
	     !f2_sfd__h521137[9] &&
	     !f2_sfd__h521137[8] &&
	     !f2_sfd__h521137[7] &&
	     !f2_sfd__h521137[6] &&
	     !f2_sfd__h521137[5] &&
	     !f2_sfd__h521137[4] &&
	     !f2_sfd__h521137[3] &&
	     !f2_sfd__h521137[2] &&
	     !f2_sfd__h521137[1] &&
	     !f2_sfd__h521137[0] ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10765 =
	     (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 == 23'd0) &&
	     (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 != 23'd0) &&
	     (f1_exp__h482142 != 8'd0 || f1_sfd__h482143 != 23'd0) &&
	     IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762 ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807 =
	     NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10765 |
	     ((f2_exp__h521136 != 8'd255 || f2_sfd__h521137 == 23'd0) &&
	      (f2_exp__h521136 != 8'd255 || f2_sfd__h521137 != 23'd0) &&
	      (f2_exp__h521136 != 8'd0 || f2_sfd__h521137 != 23'd0) &&
	      IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10803) ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10865 =
	     (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 == 23'd0) &&
	     (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 != 23'd0) &&
	     (f1_exp__h482142 != 8'd0 || f1_sfd__h482143 != 23'd0) &&
	     IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10862 ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 =
	     NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10865 |
	     ((f2_exp__h521136 != 8'd255 || f2_sfd__h521137 == 23'd0) &&
	      (f2_exp__h521136 != 8'd255 || f2_sfd__h521137 != 23'd0) &&
	      (f2_exp__h521136 != 8'd0 || f2_sfd__h521137 != 23'd0) &&
	      IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10872) ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10905 =
	     (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 == 23'd0) &&
	     (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 != 23'd0) &&
	     (f1_exp__h482142 != 8'd0 || f1_sfd__h482143 != 23'd0) &&
	     IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10902 ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920 =
	     NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10905 |
	     ((f2_exp__h521136 != 8'd255 || f2_sfd__h521137 == 23'd0) &&
	      (f2_exp__h521136 != 8'd255 || f2_sfd__h521137 != 23'd0) &&
	      (f2_exp__h521136 != 8'd0 || f2_sfd__h521137 != 23'd0) &&
	      IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10916) ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10951 =
	     (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 == 23'd0) &&
	     (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 != 23'd0) &&
	     (f1_exp__h482142 != 8'd0 || f1_sfd__h482143 != 23'd0) &&
	     IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10948 ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964 =
	     NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10951 |
	     ((f2_exp__h521136 != 8'd255 || f2_sfd__h521137 == 23'd0) &&
	      (f2_exp__h521136 != 8'd255 || f2_sfd__h521137 != 23'd0) &&
	      (f2_exp__h521136 != 8'd0 || f2_sfd__h521137 != 23'd0) &&
	      IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10960) ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10993 =
	     (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 == 23'd0) &&
	     (f1_exp__h482142 != 8'd255 || f1_sfd__h482143 != 23'd0) &&
	     (f1_exp__h482142 != 8'd0 || f1_sfd__h482143 != 23'd0) &&
	     IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10990 ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006 =
	     NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10993 |
	     ((f2_exp__h521136 != 8'd255 || f2_sfd__h521137 == 23'd0) &&
	      (f2_exp__h521136 != 8'd255 || f2_sfd__h521137 != 23'd0) &&
	      (f2_exp__h521136 != 8'd0 || f2_sfd__h521137 != 23'd0) &&
	      IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11002) ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556 =
	     !f1_sfd__h482143[21] && !f1_sfd__h482143[20] &&
	     !f1_sfd__h482143[19] &&
	     !f1_sfd__h482143[18] &&
	     !f1_sfd__h482143[17] &&
	     !f1_sfd__h482143[16] &&
	     !f1_sfd__h482143[15] &&
	     !f1_sfd__h482143[14] &&
	     !f1_sfd__h482143[13] &&
	     !f1_sfd__h482143[12] &&
	     !f1_sfd__h482143[11] &&
	     !f1_sfd__h482143[10] &&
	     !f1_sfd__h482143[9] &&
	     !f1_sfd__h482143[8] &&
	     !f1_sfd__h482143[7] &&
	     !f1_sfd__h482143[6] &&
	     !f1_sfd__h482143[5] &&
	     !f1_sfd__h482143[4] &&
	     !f1_sfd__h482143[3] &&
	     !f1_sfd__h482143[2] &&
	     !f1_sfd__h482143[1] &&
	     !f1_sfd__h482143[0] ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286 =
	     !f3_sfd__h560441[21] && !f3_sfd__h560441[20] &&
	     !f3_sfd__h560441[19] &&
	     !f3_sfd__h560441[18] &&
	     !f3_sfd__h560441[17] &&
	     !f3_sfd__h560441[16] &&
	     !f3_sfd__h560441[15] &&
	     !f3_sfd__h560441[14] &&
	     !f3_sfd__h560441[13] &&
	     !f3_sfd__h560441[12] &&
	     !f3_sfd__h560441[11] &&
	     !f3_sfd__h560441[10] &&
	     !f3_sfd__h560441[9] &&
	     !f3_sfd__h560441[8] &&
	     !f3_sfd__h560441[7] &&
	     !f3_sfd__h560441[6] &&
	     !f3_sfd__h560441[5] &&
	     !f3_sfd__h560441[4] &&
	     !f3_sfd__h560441[3] &&
	     !f3_sfd__h560441[2] &&
	     !f3_sfd__h560441[1] &&
	     !f3_sfd__h560441[0] ;
  assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13499 =
	     !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 &&
	     (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	      specTagManager$canClaim) &&
	     regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444 ;
  assign NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14639 =
	     (!commitStage_commitTrap[36] ||
	      commitStage_commitTrap[35:32] == 4'd0 ||
	      commitStage_commitTrap[35:32] == 4'd1 ||
	      commitStage_commitTrap[35:32] == 4'd3 ||
	      commitStage_commitTrap[35:32] == 4'd4 ||
	      commitStage_commitTrap[35:32] == 4'd5 ||
	      commitStage_commitTrap[35:32] == 4'd7 ||
	      commitStage_commitTrap[35:32] == 4'd8 ||
	      commitStage_commitTrap[35:32] == 4'd9 ||
	      commitStage_commitTrap[35:32] == 4'd11) &&
	     (commitStage_commitTrap[36] ||
	      commitStage_commitTrap[35:32] != 4'd3 ||
	      CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ;
  assign NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14646 =
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14639 ||
	     coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty &&
	     fetchStage$iTlbIfc_noPendingReq &&
	     coreFix_memExe_dTlb$noPendingReq ;
  assign NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 =
	     (!commitStage_commitTrap[36] ||
	      commitStage_commitTrap[35:32] != 4'd14) &&
	     (!commitStage_commitTrap[36] ||
	      commitStage_commitTrap[35:32] == 4'd0 ||
	      commitStage_commitTrap[35:32] == 4'd1 ||
	      commitStage_commitTrap[35:32] == 4'd3 ||
	      commitStage_commitTrap[35:32] == 4'd4 ||
	      commitStage_commitTrap[35:32] == 4'd5 ||
	      commitStage_commitTrap[35:32] == 4'd7 ||
	      commitStage_commitTrap[35:32] == 4'd8 ||
	      commitStage_commitTrap[35:32] == 4'd9 ||
	      commitStage_commitTrap[35:32] == 4'd11 ||
	      commitStage_commitTrap[35:32] == 4'd14) &&
	     (commitStage_commitTrap[36] ||
	      commitStage_commitTrap[35:32] != 4'd3 ||
	      CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ;
  assign NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15020 =
	     !commitStage_rg_run_state && !commitStage_commitTrap[165] &&
	     !rob$deqPort_0_deq_data[167] &&
	     !rob$deqPort_0_deq_data[18] &&
	     rob$deqPort_0_deq_data[25] ;
  assign NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15031 =
	     NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15020 &&
	     (rob$deqPort_0_deq_data[329:325] == 5'd0 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd21 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd17 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd18 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd13 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd16 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd15 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd19 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd20) &&
	     _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14339 ;
  assign NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15400 =
	     NOT_commitStage_rg_run_state_4360_4361_AND_NOT_ETC___d15020 &&
	     rob$deqPort_0_deq_data[329:325] != 5'd0 &&
	     rob$deqPort_0_deq_data[329:325] != 5'd21 &&
	     rob$deqPort_0_deq_data[329:325] != 5'd17 &&
	     rob$deqPort_0_deq_data[329:325] != 5'd18 &&
	     rob$deqPort_0_deq_data[329:325] != 5'd13 &&
	     rob$deqPort_0_deq_data[329:325] != 5'd16 &&
	     rob$deqPort_0_deq_data[329:325] != 5'd15 &&
	     rob$deqPort_0_deq_data[329:325] != 5'd19 &&
	     rob$deqPort_0_deq_data[329:325] != 5'd20 &&
	     _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14339 ;
  assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12229 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205) &&
	     (!coreFix_aluExe_0_bypassWire_1$whas ||
	      !coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12218) &&
	     (!coreFix_aluExe_0_bypassWire_2$whas ||
	      !coreFix_aluExe_0_bypassWire_2_wget__2224_BITS__ETC___d12226) ;
  assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12257 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12244) &&
	     (!coreFix_aluExe_0_bypassWire_1$whas ||
	      !coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12250) &&
	     (!coreFix_aluExe_0_bypassWire_2$whas ||
	      !coreFix_aluExe_0_bypassWire_2_wget__2224_BITS__ETC___d12254) ;
  assign NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11369 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11345) &&
	     (!coreFix_aluExe_0_bypassWire_1$whas ||
	      !coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11358) &&
	     (!coreFix_aluExe_1_bypassWire_2$whas ||
	      !coreFix_aluExe_1_bypassWire_2_wget__1364_BITS__ETC___d11366) ;
  assign NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11397 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11384) &&
	     (!coreFix_aluExe_0_bypassWire_1$whas ||
	      !coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11390) &&
	     (!coreFix_aluExe_1_bypassWire_2$whas ||
	      !coreFix_aluExe_1_bypassWire_2_wget__1364_BITS__ETC___d11394) ;
  assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8233 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8209) &&
	     (!coreFix_aluExe_0_bypassWire_1$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8222) &&
	     (!coreFix_fpuMulDivExe_0_bypassWire_2$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8230) ;
  assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8260 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8247) &&
	     (!coreFix_aluExe_0_bypassWire_1$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8253) &&
	     (!coreFix_fpuMulDivExe_0_bypassWire_2$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8257) ;
  assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8284 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8271) &&
	     (!coreFix_aluExe_0_bypassWire_1$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8277) &&
	     (!coreFix_fpuMulDivExe_0_bypassWire_2$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8281) ;
  assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815 =
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[53] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[52] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[51] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[50] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[49] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[48] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[47] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[46] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[45] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[44] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[43] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[42] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[41] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[40] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[39] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[38] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[37] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[36] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[35] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[34] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[33] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[32] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[31] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[30] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[29] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[28] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[27] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[26] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[25] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[24] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[23] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[22] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[21] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[20] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[19] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[18] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[17] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[16] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[15] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[14] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[13] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[12] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[11] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[10] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[9] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[8] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ;
  assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423 =
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[53] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[52] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[51] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[50] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[49] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[48] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[47] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[46] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[45] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[44] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[43] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[42] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[41] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[40] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[39] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[38] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[37] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[36] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[35] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[34] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[33] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[32] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[31] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[30] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[29] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[28] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[27] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[26] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[25] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[24] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[23] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[22] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[21] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[20] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[19] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[18] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[17] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[16] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[15] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[14] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[13] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[12] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[11] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[10] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[9] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[8] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ;
  assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207 =
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[55] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[54] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[53] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[52] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[51] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[50] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[49] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[48] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[47] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[46] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[45] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[44] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[43] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[42] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[41] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[40] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[39] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[38] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[37] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[36] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[35] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[34] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[33] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[32] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[31] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[30] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[29] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[28] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[27] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[26] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[25] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[24] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[23] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[22] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[21] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[20] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[19] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[18] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[17] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[16] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[15] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[14] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[13] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[12] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[11] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[10] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[9] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[8] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[7] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[6] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ;
  assign NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1595 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1571) &&
	     (!coreFix_aluExe_0_bypassWire_1$whas ||
	      !coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1584) &&
	     (!coreFix_memExe_bypassWire_2$whas ||
	      !coreFix_memExe_bypassWire_2_wget__590_BITS_70__ETC___d1592) ;
  assign NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1622 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1609) &&
	     (!coreFix_aluExe_0_bypassWire_1$whas ||
	      !coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1615) &&
	     (!coreFix_memExe_bypassWire_2$whas ||
	      !coreFix_memExe_bypassWire_2_wget__590_BITS_70__ETC___d1619) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2526 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd1) &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2666 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd1) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	      3'd3 ||
	      coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150) &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
	     2'd0 &&
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3057 =
	     !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT ||
	     !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3078 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT ||
	      (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ?
		 !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[3] :
		 !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[3])) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3046 ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3127 =
	     !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT ||
	     !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3183 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT ||
	      IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3180) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3153 ||
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072 =
	     !coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT ||
	     !coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT ||
	     !coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] ||
	     !coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2070 ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2123 =
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
	      3'd1 ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	      3'd4 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 ||
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2533 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 ||
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	      3'd3 ||
	      coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2535 =
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
	      3'd1 ||
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2533) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2557 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd2 ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd3) ||
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd3 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072 ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2561 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 ||
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd3 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072 ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2564 =
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd1) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2560 ||
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2561) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2578 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 ||
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2577 ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2581 =
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd1) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2560 ||
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2578) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2592 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	     3'd4 ||
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd3 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072 ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2598 =
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd1) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
	      (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
	       !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	      3'd4 ||
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2561) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2605 =
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd1) &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2630 =
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd1) &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd1 ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2638 =
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd1) &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd4 ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2646 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 ||
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd3 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2655 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 ||
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	      3'd3 ||
	      coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
	      2'd0 ||
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2677 =
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ||
	     IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2050 &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd4 ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
	      (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	       3'd1 ||
	       coreFix_memExe_stb$RDY_deq)) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 =
	     !coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT ||
	     !coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT ||
	     !coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT ||
	     !coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3298 =
	     !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT ||
	     !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3355 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT ||
	      (CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
		 !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[72] :
		 !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[72])) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3324 ||
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3394 =
	     !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT ||
	     !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3451 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT ||
	      IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3447) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3420 ||
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty) ;
  assign NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1883 =
	     !coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT ||
	     !coreFix_memExe_dMem_perfReqQ_clearReq_rl ;
  assign NOT_coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_ETC___d1927 =
	     (!coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT ||
	      !coreFix_memExe_dMem_perfReqQ_enqReq_rl[4]) &&
	     (coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT &&
	      coreFix_memExe_dMem_perfReqQ_deqReq_rl ||
	      coreFix_memExe_dMem_perfReqQ_empty) ;
  assign NOT_coreFix_memExe_dTlb_procResp__714_BITS_246_ETC___d1755 =
	     !coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1726 &&
	     coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1727 &&
	     !coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1731 &&
	     !coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1734 ;
  assign NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3717 =
	     !coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT ||
	     !coreFix_memExe_forwardQ_clearReq_rl ;
  assign NOT_coreFix_memExe_forwardQ_enqReq_dummy2_2_re_ETC___d3772 =
	     (!coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT ||
	      (coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
		 !coreFix_memExe_forwardQ_enqReq_lat_0$wget[69] :
		 !coreFix_memExe_forwardQ_enqReq_rl[69])) &&
	     (coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3743 ||
	      coreFix_memExe_forwardQ_empty) ;
  assign NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3623 =
	     !coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT ||
	     !coreFix_memExe_memRespLdQ_clearReq_rl ;
  assign NOT_coreFix_memExe_memRespLdQ_enqReq_dummy2_2__ETC___d3678 =
	     (!coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT ||
	      (coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
		 !coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[69] :
		 !coreFix_memExe_memRespLdQ_enqReq_rl[69])) &&
	     (coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3649 ||
	      coreFix_memExe_memRespLdQ_empty) ;
  assign NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1474 =
	     !coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT ||
	     !coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT ||
	     !coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT ||
	     !coreFix_memExe_reqLdQ_full_rl ;
  assign NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1024 =
	     !coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT ||
	     !coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT ||
	     !coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT ||
	     !coreFix_memExe_reqLrScAmoQ_full_rl ;
  assign NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3547 =
	     !coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT ||
	     !coreFix_memExe_respLrScAmoQ_clearReq_rl ;
  assign NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3589 =
	     (!coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT ||
	      (coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ?
		 !coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[64] :
		 !coreFix_memExe_respLrScAmoQ_enqReq_rl[64])) &&
	     (coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT &&
	      (coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas ||
	       coreFix_memExe_respLrScAmoQ_deqReq_rl) ||
	      coreFix_memExe_respLrScAmoQ_empty) ;
  assign NOT_coreFix_memExe_respLrScAmoQ_full_952_953_A_ETC___d2082 =
	     !coreFix_memExe_respLrScAmoQ_full &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ||
	      !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full) ;
  assign NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13337 =
	     (csrf_fs_reg != 2'd0 ||
	      (!fetchStage$pipelines_0_first[95] ||
	       !fetchStage$pipelines_0_first[94]) &&
	      (!fetchStage$pipelines_0_first[88] ||
	       !fetchStage$pipelines_0_first[87]) &&
	      !fetchStage$pipelines_0_first[81] &&
	      (!fetchStage$pipelines_0_first[75] ||
	       !fetchStage$pipelines_0_first[74])) &&
	     (fetchStage$pipelines_0_first[199:195] != 5'd13 ||
	      NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13331 &&
	      !csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 &&
	      csr_addr__h655332 != 12'h8FF) ;
  assign NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13435 =
	     (csrf_fs_reg != 2'd0 ||
	      (!fetchStage$pipelines_0_first[95] ||
	       !fetchStage$pipelines_0_first[94]) &&
	      (!fetchStage$pipelines_0_first[88] ||
	       !fetchStage$pipelines_0_first[87]) &&
	      !fetchStage$pipelines_0_first[81] &&
	      (!fetchStage$pipelines_0_first[75] ||
	       !fetchStage$pipelines_0_first[74])) &&
	     (fetchStage$pipelines_0_first[231:200] != 32'h10500073 ||
	      !csrf_tw_reg ||
	      csrf_prv_reg == 2'd3) ;
  assign NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13738 =
	     (csrf_fs_reg != 2'd0 ||
	      (!fetchStage$pipelines_1_first[95] ||
	       !fetchStage$pipelines_1_first[94]) &&
	      (!fetchStage$pipelines_1_first[88] ||
	       !fetchStage$pipelines_1_first[87]) &&
	      !fetchStage$pipelines_1_first[81] &&
	      (!fetchStage$pipelines_1_first[75] ||
	       !fetchStage$pipelines_1_first[74])) &&
	     (fetchStage$pipelines_1_first[231:200] != 32'h10500073 ||
	      !csrf_tw_reg ||
	      csrf_prv_reg == 2'd3) ;
  assign NOT_csrf_prv_reg_read__2787_ULE_1_4711_4753_OR_ETC___d14757 =
	     !csrf_prv_reg_read__2787_ULE_1___d14711 ||
	     (commitStage_commitTrap[36] ?
		!_0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14713 :
		!_0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14731) ;
  assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13542 =
	     !fetchStage$pipelines_0_canDeq ||
	     !regRenamingTable$rename_0_canRename ||
	     fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13524 ||
	     IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13539 ||
	     fetchStage$pipelines_0_first[194:192] != 3'd1 ;
  assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13785 =
	     (!fetchStage$pipelines_0_canDeq ||
	      fetchStage$pipelines_0_first[194:192] == 3'd1 &&
	      !specTagManager$canClaim ||
	      NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13776 ||
	      fetchStage$pipelines_0_first[194:192] != 3'd0 &&
	      fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	      !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463) &&
	     coreFix_aluExe_1_rsAlu$canEnq &&
	     !coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459 ;
  assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13829 =
	     (!fetchStage$pipelines_0_canDeq ||
	      fetchStage$RDY_pipelines_0_first) &&
	     (regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 &&
	      (fetchStage$pipelines_0_first[194:192] == 3'd3 ||
	       fetchStage$pipelines_0_first[194:192] == 3'd4) ||
	      !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
	      NOT_regRenamingTable_rename_1_canRename__3545__ETC___d13816) ;
  assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13884 =
	     !fetchStage$pipelines_0_canDeq ||
	     !regRenamingTable$rename_0_canRename ||
	     fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13524 ||
	     fetchStage$pipelines_0_first[194:192] != 3'd3 &&
	     fetchStage$pipelines_0_first[194:192] != 3'd4 ;
  assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13902 =
	     (!fetchStage$pipelines_0_canDeq ||
	      NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13852 ||
	      fetchStage$pipelines_0_first[194:192] != 3'd2 ||
	      IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534) &&
	     coreFix_memExe_rsMem$canEnq &&
	     CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 ;
  assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14051 =
	     (!fetchStage$pipelines_0_canDeq ||
	      NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14022) &&
	     CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242 &&
	     (fetchStage$pipelines_1_first[199:195] == 5'd14 ||
	      coreFix_memExe_rsMem$RDY_enq) ;
  assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14105 =
	     (!fetchStage$pipelines_0_canDeq ||
	      fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13971 &&
	      IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13450) &&
	     fetchStage$RDY_pipelines_0_first &&
	     fetchStage_pipelines_0_canDeq__2755_AND_fetchS_ETC___d14103 ;
  assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14204 =
	     (!fetchStage$pipelines_0_canDeq ||
	      fetchStage$pipelines_0_first[194:192] == 3'd1 &&
	      !specTagManager$canClaim ||
	      NOT_regRenamingTable_rename_0_canRename__3418__ETC___d14199 ||
	      fetchStage$pipelines_0_first[194:192] != 3'd0 &&
	      fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	      !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463) &&
	     coreFix_aluExe_1_rsAlu$canEnq &&
	     !coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459 ;
  assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 =
	     (!fetchStage$pipelines_0_canDeq ||
	      NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 &&
	      IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13480) &&
	     fetchStage$pipelines_1_canDeq ;
  assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14211 =
	     !fetchStage$pipelines_0_canDeq ||
	     !regRenamingTable$rename_0_canRename ||
	     renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935 ||
	     IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13539 ||
	     fetchStage$pipelines_0_first[194:192] != 3'd1 ;
  assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14223 =
	     NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 &&
	     NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14220 &&
	     (fetchStage$pipelines_1_first[194:192] == 3'd0 ||
	      fetchStage$pipelines_1_first[194:192] == 3'd1) &&
	     SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14017 ;
  assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14267 =
	     !fetchStage$pipelines_0_canDeq ||
	     !regRenamingTable$rename_0_canRename ||
	     renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935 ||
	     fetchStage$pipelines_0_first[194:192] != 3'd2 ||
	     IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 ;
  assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268 =
	     NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14267 &&
	     coreFix_memExe_rsMem$canEnq &&
	     CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 ;
  assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14298 =
	     NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14211 &&
	     specTagManager$canClaim &&
	     regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219 &&
	     IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 &&
	     fetchStage$pipelines_1_first[194:192] == 3'd1 ;
  assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13331 =
	     (fetchStage$pipelines_0_first[194:192] != 3'd0 ||
	      fetchStage$pipelines_0_first[178:174] != 5'd15) &&
	     rs1__h655333 == 5'd0 &&
	     imm__h655334 == 32'd0 ||
	     csr_addr__h655332[11:10] != 2'b11 ;
  assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13481 =
	     (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	      specTagManager$canClaim) &&
	     regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444 &&
	     IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13480 ;
  assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13761 =
	     (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	      specTagManager$canClaim) &&
	     regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444 &&
	     fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13760 ;
  assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13767 =
	     (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	      specTagManager$canClaim) &&
	     regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444 &&
	     (fetchStage$pipelines_0_first[194:192] == 3'd0 ||
	      fetchStage$pipelines_0_first[194:192] == 3'd1) &&
	     SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 &&
	     (!coreFix_aluExe_0_rsAlu$canEnq ||
	      !coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459) ;
  assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13928 =
	     (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	      specTagManager$canClaim) &&
	     regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444 &&
	     IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 ;
  assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 =
	     (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	      specTagManager$canClaim) &&
	     regRenamingTable$rename_0_canRename &&
	     !checkForException___d13008[4] &&
	     rob$enqPort_0_canEnq ;
  assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14181 =
	     { fetchStage$pipelines_0_first[194:192] != 3'd2 ||
	       !coreFix_memExe_rsMem$canEnq ||
	       IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 ||
	       IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137,
	       (fetchStage$pipelines_0_first[194:192] == 3'd2 &&
		coreFix_memExe_rsMem$canEnq &&
		IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 &&
		IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14140) ?
		 IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14143 :
		 { 1'h0,
		   IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 },
	       7'd32,
	       specTagManager$currentSpecBits } ;
  assign NOT_fetchStage_pipelines_0_first__2757_BIT_68__ETC___d13492 =
	     !fetchStage$pipelines_0_first[68] &&
	     !checkForException___d13008[4] &&
	     NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13435 &&
	     rob$enqPort_0_canEnq &&
	     epochManager$checkEpoch_0_check ;
  assign NOT_fetchStage_pipelines_1_canDeq__2763_2764_O_ETC___d12772 =
	     !fetchStage$pipelines_1_canDeq ||
	     fetchStage$RDY_pipelines_1_first &&
	     (epochManager$checkEpoch_1_check ||
	      fetchStage$RDY_pipelines_1_deq) ;
  assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13515 =
	     (fetchStage$pipelines_1_first[194:192] != 3'd1 ||
	      !fetchStage$pipelines_0_canDeq ||
	      fetchStage$RDY_pipelines_0_first) &&
	     (fetchStage$RDY_pipelines_0_first &&
	      fetchStage$pipelines_1_first[194:192] == 3'd1 &&
	      regRenamingTable_rename_0_canRename__3418_AND__ETC___d13508 ||
	      csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13513) ;
  assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13754 =
	     (fetchStage$pipelines_1_first[194:192] != 3'd1 ||
	      NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13542 &&
	      specTagManager$canClaim) &&
	     regRenamingTable_rename_1_canRename__3545_AND__ETC___d13753 ;
  assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13871 =
	     (fetchStage$pipelines_1_first[194:192] != 3'd1 ||
	      (!fetchStage$pipelines_0_canDeq ||
	       NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13852 ||
	       IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13865 ||
	       fetchStage$pipelines_0_first[194:192] != 3'd1) &&
	      specTagManager$canClaim) &&
	     regRenamingTable_rename_1_canRename__3545_AND__ETC___d13753 ;
  assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14220 =
	     (fetchStage$pipelines_1_first[194:192] != 3'd1 ||
	      NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14211 &&
	      specTagManager$canClaim) &&
	     regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219 ;
  assign NOT_fetchStage_pipelines_1_first__2766_BIT_68__ETC___d14217 =
	     !fetchStage$pipelines_1_first[68] &&
	     !checkForException___d13713[4] &&
	     NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13738 &&
	     rob$enqPort_1_canEnq &&
	     epochManager$checkEpoch_1_check &&
	     !csrf_rg_dcsr[2] ;
  assign NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 =
	     !mmio_cRqQ_clearReq_dummy2_1$Q_OUT || !mmio_cRqQ_clearReq_rl ;
  assign NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452 =
	     (!mmio_cRqQ_enqReq_dummy2_2$Q_OUT ||
	      (mmio_cRqQ_enqReq_lat_0$whas ?
		 !mmio_cRqQ_enqReq_lat_0$wget[142] :
		 !mmio_cRqQ_enqReq_rl[142])) &&
	     (mmio_cRqQ_deqReq_dummy2_2$Q_OUT &&
	      (EN_mmioToPlatform_cRq_deq || mmio_cRqQ_deqReq_rl) ||
	      mmio_cRqQ_empty) ;
  assign NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 =
	     !mmio_cRsQ_clearReq_dummy2_1$Q_OUT || !mmio_cRsQ_clearReq_rl ;
  assign NOT_mmio_cRsQ_enqReq_dummy2_2_read__24_39_OR_I_ETC___d844 =
	     (!mmio_cRsQ_enqReq_dummy2_2$Q_OUT ||
	      (CAN_FIRE_RL_mmio_handlePRq ?
		 !mmio_cRsQ_enqReq_lat_0$wget[1] :
		 !mmio_cRsQ_enqReq_rl[1])) &&
	     (mmio_cRsQ_deqReq_dummy2_2$Q_OUT &&
	      (EN_mmioToPlatform_cRs_deq || mmio_cRsQ_deqReq_rl) ||
	      mmio_cRsQ_empty) ;
  assign NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091 =
	     !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ &&
	     coreFix_memExe_lsq$RDY_firstSt &&
	     coreFix_memExe_lsq$RDY_deqSt ;
  assign NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390 =
	     !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ &&
	     coreFix_memExe_lsq$RDY_firstLd &&
	     coreFix_memExe_lsq$RDY_deqLd ;
  assign NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 =
	     (!mmio_dataPendQ_enqReq_dummy2_2$Q_OUT ||
	      !mmio_dataPendQ_enqReq_lat_0$whas &&
	      !mmio_dataPendQ_enqReq_rl) &&
	     (mmio_dataPendQ_deqReq_dummy2_2$Q_OUT &&
	      (mmio_dataRespQ_deqReq_lat_0$whas ||
	       mmio_dataPendQ_deqReq_rl) ||
	      mmio_dataPendQ_empty) ;
  assign NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 =
	     !mmio_dataReqQ_clearReq_dummy2_1$Q_OUT ||
	     !mmio_dataReqQ_clearReq_rl ;
  assign NOT_mmio_dataReqQ_enqReq_dummy2_2_read__41_56__ETC___d161 =
	     (!mmio_dataReqQ_enqReq_dummy2_2$Q_OUT ||
	      (mmio_dataReqQ_enqReq_lat_0$whas ?
		 !mmio_dataReqQ_enqReq_lat_0$wget[142] :
		 !mmio_dataReqQ_enqReq_rl[142])) &&
	     (mmio_dataReqQ_deqReq_dummy2_2$Q_OUT &&
	      (CAN_FIRE_RL_mmio_sendDataReq || mmio_dataReqQ_deqReq_rl) ||
	      mmio_dataReqQ_empty) ;
  assign NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 =
	     !mmio_dataRespQ_clearReq_dummy2_1$Q_OUT ||
	     !mmio_dataRespQ_clearReq_rl ;
  assign NOT_mmio_dataRespQ_enqReq_dummy2_2_read__42_57_ETC___d262 =
	     (!mmio_dataRespQ_enqReq_dummy2_2$Q_OUT ||
	      (CAN_FIRE_RL_mmio_sendDataResp ?
		 !mmio_dataRespQ_enqReq_lat_0$wget[65] :
		 !mmio_dataRespQ_enqReq_rl[65])) &&
	     (mmio_dataRespQ_deqReq_dummy2_2$Q_OUT &&
	      (mmio_dataRespQ_deqReq_lat_0$whas ||
	       mmio_dataRespQ_deqReq_rl) ||
	      mmio_dataRespQ_empty) ;
  assign NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 =
	     !mmio_pRqQ_clearReq_dummy2_1$Q_OUT || !mmio_pRqQ_clearReq_rl ;
  assign NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755 =
	     (!mmio_pRqQ_enqReq_dummy2_2$Q_OUT ||
	      (EN_mmioToPlatform_pRq_enq ?
		 !mmio_pRqQ_enqReq_lat_0$wget[39] :
		 !mmio_pRqQ_enqReq_rl[39])) &&
	     (mmio_pRqQ_deqReq_dummy2_2$Q_OUT &&
	      (CAN_FIRE_RL_mmio_handlePRq || mmio_pRqQ_deqReq_rl) ||
	      mmio_pRqQ_empty) ;
  assign NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 =
	     !mmio_pRsQ_clearReq_dummy2_1$Q_OUT || !mmio_pRsQ_clearReq_rl ;
  assign NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614 =
	     (!mmio_pRsQ_enqReq_dummy2_2$Q_OUT ||
	      (EN_mmioToPlatform_pRs_enq ?
		 !mmio_pRsQ_enqReq_lat_0$wget[67] :
		 !mmio_pRsQ_enqReq_rl[67])) &&
	     (mmio_pRsQ_deqReq_dummy2_2$Q_OUT &&
	      (mmio_pRsQ_deqReq_lat_0$whas || mmio_pRsQ_deqReq_rl) ||
	      mmio_pRsQ_empty) ;
  assign NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13776 =
	     !regRenamingTable$rename_0_canRename ||
	     fetchStage$pipelines_0_first[199:195] == 5'd0 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd21 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd17 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd18 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd13 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd16 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd15 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd19 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd20 ||
	     renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13774 ;
  assign NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13852 =
	     !regRenamingTable$rename_0_canRename ||
	     fetchStage$pipelines_0_first[199:195] == 5'd0 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd21 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd17 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd18 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd13 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd16 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd15 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd19 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd20 ||
	     fetchStage_pipelines_0_first__2757_BIT_68_2786_ETC___d13850 ;
  assign NOT_regRenamingTable_rename_0_canRename__3418__ETC___d14199 =
	     !regRenamingTable$rename_0_canRename ||
	     renameStage_rg_m_halt_req[4] ||
	     fetchStage$pipelines_0_first[68] ||
	     checkForException___d13008[4] ||
	     !rob$enqPort_0_canEnq ;
  assign NOT_regRenamingTable_rename_1_canRename__3545__ETC___d13816 =
	     !regRenamingTable$rename_1_canRename ||
	     fetchStage$pipelines_1_first[199:195] == 5'd0 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd21 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd17 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd18 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd13 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd16 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd15 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd19 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd20 ||
	     renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13814 ;
  assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13102 =
	     !renameStage_rg_m_halt_req[4] &&
	     (fetchStage$pipelines_0_first[68] ||
	      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[10] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[11] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[12] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15]) ;
  assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13442 =
	     !renameStage_rg_m_halt_req[4] &&
	     !fetchStage$pipelines_0_first[68] &&
	     NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13437 &&
	     rob$enqPort_0_canEnq &&
	     epochManager$checkEpoch_0_check ;
  assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13751 =
	     !renameStage_rg_m_halt_req[4] &&
	     !fetchStage$pipelines_1_first[68] &&
	     NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13740 &&
	     rob$enqPort_1_canEnq &&
	     epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13749 ;
  assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13893 =
	     !renameStage_rg_m_halt_req[4] &&
	     !fetchStage$pipelines_1_first[68] &&
	     NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13740 &&
	     rob$enqPort_1_canEnq &&
	     epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13891 ;
  assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13911 =
	     !renameStage_rg_m_halt_req[4] &&
	     !fetchStage$pipelines_1_first[68] &&
	     NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13740 &&
	     rob$enqPort_1_canEnq &&
	     epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13909 ;
  assign NOT_rob_deqPort_0_canDeq__5346_5347_OR_regRena_ETC___d15388 =
	     (!rob$deqPort_0_canDeq ||
	      regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq &&
	      v_f_to_TV_0$FULL_N) &&
	     (!rob$deqPort_1_canDeq ||
	      rob$RDY_deqPort_1_deq_data &&
	      NOT_rob_deqPort_1_deq_data__5354_BIT_25_5355_5_ETC___d15385) ;
  assign NOT_rob_deqPort_0_canDeq__5346_5347_OR_rob_deq_ETC___d15667 =
	     (!rob$deqPort_0_canDeq ||
	      rob$deqPort_0_deq_data[25] && !rob$deqPort_0_deq_data[18] &&
	      !rob$deqPort_0_deq_data[167] &&
	      rob$deqPort_0_deq_data[329:325] != 5'd0 &&
	      rob$deqPort_0_deq_data[329:325] != 5'd21 &&
	      rob$deqPort_0_deq_data[329:325] != 5'd17 &&
	      rob$deqPort_0_deq_data[329:325] != 5'd18 &&
	      rob$deqPort_0_deq_data[329:325] != 5'd13 &&
	      rob$deqPort_0_deq_data[329:325] != 5'd16 &&
	      rob$deqPort_0_deq_data[329:325] != 5'd15 &&
	      rob$deqPort_0_deq_data[329:325] != 5'd19 &&
	      rob$deqPort_0_deq_data[329:325] != 5'd20) &&
	     rob$deqPort_1_canDeq ;
  assign NOT_rob_deqPort_0_deq_data__4354_BITS_329_TO_3_ETC___d15008 =
	     rob$deqPort_0_deq_data[329:325] != 5'd13 ||
	     (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 !=
	      6'd7 ||
	      csrf_stats_module_writeQ$FULL_N) &&
	     (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 !=
	      6'd6 ||
	      csrf_terminate_module_terminateQ$FULL_N) ;
  assign NOT_rob_deqPort_1_deq_data__5354_BIT_25_5355_5_ETC___d15385 =
	     !rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
	     rob$deqPort_1_deq_data[167] ||
	     rob$deqPort_1_deq_data[329:325] == 5'd0 ||
	     rob$deqPort_1_deq_data[329:325] == 5'd21 ||
	     rob$deqPort_1_deq_data[329:325] == 5'd17 ||
	     rob$deqPort_1_deq_data[329:325] == 5'd18 ||
	     rob$deqPort_1_deq_data[329:325] == 5'd13 ||
	     rob$deqPort_1_deq_data[329:325] == 5'd16 ||
	     rob$deqPort_1_deq_data[329:325] == 5'd15 ||
	     rob$deqPort_1_deq_data[329:325] == 5'd19 ||
	     rob$deqPort_1_deq_data[329:325] == 5'd20 ||
	     regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq &&
	     v_f_to_TV_1$FULL_N ;
  assign NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14022 =
	     !specTagManager$canClaim ||
	     !regRenamingTable$rename_0_canRename ||
	     fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13524 ||
	     IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962 ||
	     fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	     specTagManager$RDY_nextSpecTag ;
  assign NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14089 =
	     !specTagManager$canClaim ||
	     !regRenamingTable$rename_0_canRename ||
	     renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935 ||
	     IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962 ||
	     fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	     specTagManager$RDY_nextSpecTag ;
  assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2920 =
	     { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q22,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q23,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q24,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q25 } ;
  assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2929 =
	     { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2920,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q26,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27 } ;
  assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938 =
	     { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2929,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q260,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261 } ;
  assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2945 =
	     { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q267,
	       !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268,
	       SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938,
	       x__h291618 } ;
  assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16106 =
	     { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 } ;
  assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16062 =
	     { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 } ;
  assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16071 =
	     { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16062,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 } ;
  assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16080 =
	     { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16071,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 } ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 =
	     { {4{f2_exp21136_MINUS_127__q176[7]}},
	       f2_exp21136_MINUS_127__q176 } ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 =
	     (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 ^
	      12'h800) <=
	     12'd3071 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 =
	     (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 ^
	      12'h800) <
	     12'd1026 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8646 =
	     { {4{f1_exp82142_MINUS_127__q136[7]}},
	       f1_exp82142_MINUS_127__q136 } ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 =
	     (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8646 ^
	      12'h800) <=
	     12'd3071 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 =
	     (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8646 ^
	      12'h800) <
	     12'd1026 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9361 =
	     { {4{f3_exp60440_MINUS_127__q153[7]}},
	       f3_exp60440_MINUS_127__q153 } ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 =
	     (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9361 ^
	      12'h800) <=
	     12'd3071 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 =
	     (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9361 ^
	      12'h800) <
	     12'd1026 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8646 +
	     12'd1023 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] -
	     11'd1023 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9361 +
	     12'd1023 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] -
	     11'd1023 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 +
	     12'd1023 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] -
	     11'd1023 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5943 =
	     { coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q71[10],
	       coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q71 } ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 =
	     (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5943 ^
	      12'h800) <=
	     12'd2175 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 =
	     (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5943 ^
	      12'h800) <
	     12'd1922 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5943 +
	     12'd127 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q77 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] -
	     8'd127 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4551 =
	     { coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q36[10],
	       coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q36 } ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 =
	     (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4551 ^
	      12'h800) <=
	     12'd2175 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 =
	     (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4551 ^
	      12'h800) <
	     12'd1922 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4551 +
	     12'd127 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] -
	     8'd127 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7335 =
	     { coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q106[10],
	       coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q106 } ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 =
	     (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7335 ^
	      12'h800) <=
	     12'd2175 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 =
	     (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7335 ^
	      12'h800) <
	     12'd1922 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7335 +
	     12'd127 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q112 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] -
	     8'd127 ;
  assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4249 =
	     ({ 3'd0,
		IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247 } ^
	      9'h100) <=
	     9'd256 ;
  assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169 =
	     { 3'd0,
	       _theResult___fst_exp__h354198 == 8'd0 &&
	       (sfdin__h354192[56:34] == 23'd0 || guard__h346097 != 2'b0),
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h354795 == 8'd255 &&
	       _theResult___fst_sfd__h354796 == 23'd0,
	       1'd0,
	       _theResult___fst_exp__h354198 != 8'd255 &&
	       guard__h346097 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5641 =
	     ({ 3'd0,
		IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 } ^
	      9'h100) <=
	     9'd256 ;
  assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6561 =
	     { 3'd0,
	       _theResult___fst_exp__h399895 == 8'd0 &&
	       (sfdin__h399889[56:34] == 23'd0 || guard__h391796 != 2'b0),
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h400492 == 8'd255 &&
	       _theResult___fst_sfd__h400493 == 23'd0,
	       1'd0,
	       _theResult___fst_exp__h399895 != 8'd255 &&
	       guard__h391796 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7033 =
	     ({ 3'd0,
		IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 } ^
	      9'h100) <=
	     9'd256 ;
  assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7953 =
	     { 3'd0,
	       _theResult___fst_exp__h445590 == 8'd0 &&
	       (sfdin__h445584[56:34] == 23'd0 || guard__h437491 != 2'b0),
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h446187 == 8'd255 &&
	       _theResult___fst_sfd__h446188 == 23'd0,
	       1'd0,
	       _theResult___fst_exp__h445590 != 8'd255 &&
	       guard__h437491 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10382 =
	     ({ 6'd0,
		IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 } ^
	      12'h800) <=
	     12'd2048 ;
  assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758 =
	     { 3'd0,
	       _theResult___fst_exp__h511107 == 11'd0 &&
	       (sfdin__h511101[56:5] == 52'd0 || guard__h502881 != 2'b0),
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h511939 == 11'd2047 &&
	       _theResult___fst_sfd__h511940 == 52'd0,
	       1'd0,
	       _theResult___fst_exp__h511107 != 11'd2047 &&
	       guard__h502881 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799 =
	     { 3'd0,
	       _theResult___fst_exp__h549960 == 11'd0 &&
	       (sfdin__h549954[56:5] == 52'd0 || guard__h541734 != 2'b0),
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h550792 == 11'd2047 &&
	       _theResult___fst_sfd__h550793 == 52'd0,
	       1'd0,
	       _theResult___fst_exp__h549960 != 11'd2047 &&
	       guard__h541734 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843 =
	     { 3'd0,
	       _theResult___fst_exp__h589264 == 11'd0 &&
	       (sfdin__h589258[56:5] == 52'd0 || guard__h581038 != 2'b0),
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h590096 == 11'd2047 &&
	       _theResult___fst_sfd__h590097 == 52'd0,
	       1'd0,
	       _theResult___fst_exp__h589264 != 11'd2047 &&
	       guard__h581038 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8897 =
	     ({ 6'd0,
		IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 } ^
	      12'h800) <=
	     12'd2048 ;
  assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9612 =
	     ({ 6'd0,
		IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9610 } ^
	      12'h800) <=
	     12'd2048 ;
  assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4800 =
	     ({ 3'd0,
		IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4798 } ^
	      9'h100) <=
	     9'd256 ;
  assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198 =
	     { 3'd0,
	       _theResult___fst_exp__h371964 == 8'd0 &&
	       (sfdin__h371958[56:34] == 23'd0 || guard__h363736 != 2'b0),
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h372561 == 8'd255 &&
	       _theResult___fst_sfd__h372562 == 23'd0,
	       1'd0,
	       _theResult___fst_exp__h371964 != 8'd255 &&
	       guard__h363736 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6192 =
	     ({ 3'd0,
		IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 } ^
	      9'h100) <=
	     9'd256 ;
  assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590 =
	     { 3'd0,
	       _theResult___fst_exp__h417661 == 8'd0 &&
	       (sfdin__h417655[56:34] == 23'd0 || guard__h409433 != 2'b0),
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h418258 == 8'd255 &&
	       _theResult___fst_sfd__h418259 == 23'd0,
	       1'd0,
	       _theResult___fst_exp__h417661 != 8'd255 &&
	       guard__h409433 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7584 =
	     ({ 3'd0,
		IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 } ^
	      9'h100) <=
	     9'd256 ;
  assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982 =
	     { 3'd0,
	       _theResult___fst_exp__h463356 == 8'd0 &&
	       (sfdin__h463350[56:34] == 23'd0 || guard__h455128 != 2'b0),
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h463953 == 8'd255 &&
	       _theResult___fst_sfd__h463954 == 23'd0,
	       1'd0,
	       _theResult___fst_exp__h463356 != 8'd255 &&
	       guard__h455128 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10085 =
	     ({ 6'd0,
		IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 } ^
	      12'h800) <=
	     12'd2944 ;
  assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10432 =
	     ({ 6'd0,
		IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 } ^
	      12'h800) <=
	     (IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10431 ^
	      12'h800) ;
  assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741 =
	     { 3'd0,
	       _theResult___fst_exp__h501530 == 11'd0 &&
	       guard__h493569 != 2'b0,
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h502288 == 11'd2047 &&
	       _theResult___fst_sfd__h502289 == 52'd0,
	       1'd0,
	       _theResult___fst_exp__h501530 != 11'd2047 &&
	       guard__h493569 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782 =
	     { 3'd0,
	       _theResult___fst_exp__h540383 == 11'd0 &&
	       guard__h532422 != 2'b0,
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h541141 == 11'd2047 &&
	       _theResult___fst_sfd__h541142 == 52'd0,
	       1'd0,
	       _theResult___fst_exp__h540383 != 11'd2047 &&
	       guard__h532422 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826 =
	     { 3'd0,
	       _theResult___fst_exp__h579687 == 11'd0 &&
	       guard__h571726 != 2'b0,
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h580445 == 11'd2047 &&
	       _theResult___fst_sfd__h580446 == 52'd0,
	       1'd0,
	       _theResult___fst_exp__h579687 != 11'd2047 &&
	       guard__h571726 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8585 =
	     ({ 6'd0,
		IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 } ^
	      12'h800) <=
	     12'd2944 ;
  assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8947 =
	     ({ 6'd0,
		IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 } ^
	      12'h800) <=
	     (IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8946 ^
	      12'h800) ;
  assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9315 =
	     ({ 6'd0,
		IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 } ^
	      12'h800) <=
	     12'd2944 ;
  assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9662 =
	     ({ 6'd0,
		IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 } ^
	      12'h800) <=
	     (IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9661 ^
	      12'h800) ;
  assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4480 =
	     ({ 3'd0,
		IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 } ^
	      9'h100) <=
	     9'd384 ;
  assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4873 =
	     ({ 3'd0,
		IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 } ^
	      9'h100) <=
	     (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4872 ^
	      9'h100) ;
  assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5181 =
	     { 3'd0,
	       _theResult___fst_exp__h362854 == 8'd0 &&
	       guard__h354806 != 2'b0,
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h363377 == 8'd255 &&
	       _theResult___fst_sfd__h363378 == 23'd0,
	       1'd0,
	       _theResult___fst_exp__h362854 != 8'd255 &&
	       guard__h354806 != 2'b0 } ;
  assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5872 =
	     ({ 3'd0,
		IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 } ^
	      9'h100) <=
	     9'd384 ;
  assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6265 =
	     ({ 3'd0,
		IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 } ^
	      9'h100) <=
	     (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264 ^
	      9'h100) ;
  assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6573 =
	     { 3'd0,
	       _theResult___fst_exp__h408551 == 8'd0 &&
	       guard__h400503 != 2'b0,
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h409074 == 8'd255 &&
	       _theResult___fst_sfd__h409075 == 23'd0,
	       1'd0,
	       _theResult___fst_exp__h408551 != 8'd255 &&
	       guard__h400503 != 2'b0 } ;
  assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7264 =
	     ({ 3'd0,
		IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 } ^
	      9'h100) <=
	     9'd384 ;
  assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7657 =
	     ({ 3'd0,
		IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 } ^
	      9'h100) <=
	     (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656 ^
	      9'h100) ;
  assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965 =
	     { 3'd0,
	       _theResult___fst_exp__h454246 == 8'd0 &&
	       guard__h446198 != 2'b0,
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h454769 == 8'd255 &&
	       _theResult___fst_sfd__h454770 == 23'd0,
	       1'd0,
	       _theResult___fst_exp__h454246 != 8'd255 &&
	       guard__h446198 != 2'b0 } ;
  assign _0_CONCAT_csrf_external_int_en_vec_3_read__1664_ETC___d12798 =
	     { 4'd0,
	       csrf_external_int_en_vec_3 & csrf_external_int_pend_vec_3,
	       1'd0,
	       csrf_external_int_en_vec_1 & csrf_external_int_pend_vec_1,
	       1'd0,
	       csrf_timer_int_en_vec_3 & csrf_timer_int_pend_vec_3,
	       1'd0,
	       csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1,
	       1'd0 } ;
  assign _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13943 =
	     (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	      specTagManager$RDY_nextSpecTag) &&
	     CASE_k70634_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 ;
  assign _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13844 =
	     (fetchStage$pipelines_1_first[194:192] != 3'd1 ||
	      !fetchStage$pipelines_0_canDeq ||
	      fetchStage$RDY_pipelines_0_first) &&
	     (fetchStage$RDY_pipelines_0_first &&
	      fetchStage$pipelines_1_first[194:192] == 3'd1 &&
	      regRenamingTable_rename_0_canRename__3418_AND__ETC___d13508 ||
	      NOT_regRenamingTable_rename_1_canRename__3545__ETC___d13816) ;
  assign _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d14035 =
	     (fetchStage$pipelines_1_first[194:192] != 3'd1 ||
	      specTagManager$RDY_nextSpecTag) &&
	     CASE_fetchStage_pipelines_0_canDeq__2755_AND_N_ETC__q241 ;
  assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10138 =
	     sfd__h521498 >>
	     _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10134 ;
  assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8653 =
	     sfd__h482504 >>
	     _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8649 ;
  assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9368 =
	     sfd__h560802 >>
	     _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9364 ;
  assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558 =
	     sfd__h338482 >>
	     (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554[11] ?
		12'hAAA :
		_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554) ;
  assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950 =
	     sfd__h384184 >>
	     (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946[11] ?
		12'hAAA :
		_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946) ;
  assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342 =
	     sfd__h429879 >>
	     (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338[11] ?
		12'hAAA :
		_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338) ;
  assign _0b0_CONCAT_csrf_external_int_pend_vec_3_read___ETC___d14339 =
	     mip_csr__read__h611253 == commitStage_rg_old_mip_csr_val ;
  assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14731 =
	     medeleg_csr__read__h610372[i__h710467] ;
  assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14713 =
	     mideleg_csr__read__h610467[i__h710627] ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4011 =
	     12'd3074 -
	     { 6'd0,
	       coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] ?
		 6'd0 :
		 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] ?
		    6'd1 :
		    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] ?
		       6'd2 :
		       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[53] ?
			  6'd3 :
			  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[52] ?
			     6'd4 :
			     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[51] ?
				6'd5 :
				(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[50] ?
				   6'd6 :
				   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[49] ?
				      6'd7 :
				      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[48] ?
					 6'd8 :
					 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[47] ?
					    6'd9 :
					    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[46] ?
					       6'd10 :
					       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[45] ?
						  6'd11 :
						  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[44] ?
						     6'd12 :
						     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[43] ?
							6'd13 :
							(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[42] ?
							   6'd14 :
							   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[41] ?
							      6'd15 :
							      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[40] ?
								 6'd16 :
								 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[39] ?
								    6'd17 :
								    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[38] ?
								       6'd18 :
								       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[37] ?
									  6'd19 :
									  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[36] ?
									     6'd20 :
									     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[35] ?
										6'd21 :
										(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[34] ?
										   6'd22 :
										   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[33] ?
										      6'd23 :
										      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[32] ?
											 6'd24 :
											 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[31] ?
											    6'd25 :
											    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[30] ?
											       6'd26 :
											       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[29] ?
												  6'd27 :
												  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[28] ?
												     6'd28 :
												     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[27] ?
													6'd29 :
													(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[26] ?
													   6'd30 :
													   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[25] ?
													      6'd31 :
													      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[24] ?
														 6'd32 :
														 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[23] ?
														    6'd33 :
														    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[22] ?
														       6'd34 :
														       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[21] ?
															  6'd35 :
															  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[20] ?
															     6'd36 :
															     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[19] ?
																6'd37 :
																(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[18] ?
																   6'd38 :
																   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[17] ?
																      6'd39 :
																      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[16] ?
																	 6'd40 :
																	 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[15] ?
																	    6'd41 :
																	    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[14] ?
																	       6'd42 :
																	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[13] ?
																		  6'd43 :
																		  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[12] ?
																		     6'd44 :
																		     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[11] ?
																			6'd45 :
																			(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[10] ?
																			   6'd46 :
																			   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[9] ?
																			      6'd47 :
																			      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[8] ?
																				 6'd48 :
																				 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] ?
																				    6'd49 :
																				    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] ?
																				       6'd50 :
																				       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ?
																					  6'd51 :
																					  6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 =
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4011 ^
	      12'h800) <=
	     12'd2175 ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 =
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4011 ^
	      12'h800) <
	     12'd1922 ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5184 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 &&
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169[4] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5181[4]) ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5209 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 &&
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169[3] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5181[3]) ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5236 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 &&
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169[1] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5181[1]) ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5403 =
	     12'd3074 -
	     { 6'd0,
	       coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] ?
		 6'd0 :
		 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] ?
		    6'd1 :
		    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] ?
		       6'd2 :
		       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[53] ?
			  6'd3 :
			  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[52] ?
			     6'd4 :
			     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[51] ?
				6'd5 :
				(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[50] ?
				   6'd6 :
				   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[49] ?
				      6'd7 :
				      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[48] ?
					 6'd8 :
					 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[47] ?
					    6'd9 :
					    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[46] ?
					       6'd10 :
					       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[45] ?
						  6'd11 :
						  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[44] ?
						     6'd12 :
						     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[43] ?
							6'd13 :
							(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[42] ?
							   6'd14 :
							   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[41] ?
							      6'd15 :
							      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[40] ?
								 6'd16 :
								 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[39] ?
								    6'd17 :
								    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[38] ?
								       6'd18 :
								       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[37] ?
									  6'd19 :
									  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[36] ?
									     6'd20 :
									     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[35] ?
										6'd21 :
										(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[34] ?
										   6'd22 :
										   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[33] ?
										      6'd23 :
										      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[32] ?
											 6'd24 :
											 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[31] ?
											    6'd25 :
											    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[30] ?
											       6'd26 :
											       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[29] ?
												  6'd27 :
												  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[28] ?
												     6'd28 :
												     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[27] ?
													6'd29 :
													(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[26] ?
													   6'd30 :
													   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[25] ?
													      6'd31 :
													      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[24] ?
														 6'd32 :
														 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[23] ?
														    6'd33 :
														    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[22] ?
														       6'd34 :
														       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[21] ?
															  6'd35 :
															  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[20] ?
															     6'd36 :
															     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[19] ?
																6'd37 :
																(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[18] ?
																   6'd38 :
																   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[17] ?
																      6'd39 :
																      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[16] ?
																	 6'd40 :
																	 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[15] ?
																	    6'd41 :
																	    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[14] ?
																	       6'd42 :
																	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[13] ?
																		  6'd43 :
																		  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[12] ?
																		     6'd44 :
																		     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[11] ?
																			6'd45 :
																			(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[10] ?
																			   6'd46 :
																			   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[9] ?
																			      6'd47 :
																			      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[8] ?
																				 6'd48 :
																				 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] ?
																				    6'd49 :
																				    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] ?
																				       6'd50 :
																				       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ?
																					  6'd51 :
																					  6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 =
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5403 ^
	      12'h800) <=
	     12'd2175 ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 =
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5403 ^
	      12'h800) <
	     12'd1922 ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6576 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 &&
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6561[4] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6573[4]) ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6601 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 &&
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6561[3] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6573[3]) ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6628 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 &&
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6561[1] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6573[1]) ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6795 =
	     12'd3074 -
	     { 6'd0,
	       coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] ?
		 6'd0 :
		 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[55] ?
		    6'd1 :
		    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[54] ?
		       6'd2 :
		       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[53] ?
			  6'd3 :
			  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[52] ?
			     6'd4 :
			     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[51] ?
				6'd5 :
				(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[50] ?
				   6'd6 :
				   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[49] ?
				      6'd7 :
				      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[48] ?
					 6'd8 :
					 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[47] ?
					    6'd9 :
					    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[46] ?
					       6'd10 :
					       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[45] ?
						  6'd11 :
						  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[44] ?
						     6'd12 :
						     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[43] ?
							6'd13 :
							(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[42] ?
							   6'd14 :
							   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[41] ?
							      6'd15 :
							      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[40] ?
								 6'd16 :
								 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[39] ?
								    6'd17 :
								    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[38] ?
								       6'd18 :
								       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[37] ?
									  6'd19 :
									  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[36] ?
									     6'd20 :
									     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[35] ?
										6'd21 :
										(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[34] ?
										   6'd22 :
										   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[33] ?
										      6'd23 :
										      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[32] ?
											 6'd24 :
											 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[31] ?
											    6'd25 :
											    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[30] ?
											       6'd26 :
											       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[29] ?
												  6'd27 :
												  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[28] ?
												     6'd28 :
												     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[27] ?
													6'd29 :
													(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[26] ?
													   6'd30 :
													   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[25] ?
													      6'd31 :
													      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[24] ?
														 6'd32 :
														 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[23] ?
														    6'd33 :
														    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[22] ?
														       6'd34 :
														       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[21] ?
															  6'd35 :
															  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[20] ?
															     6'd36 :
															     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[19] ?
																6'd37 :
																(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[18] ?
																   6'd38 :
																   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[17] ?
																      6'd39 :
																      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[16] ?
																	 6'd40 :
																	 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[15] ?
																	    6'd41 :
																	    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[14] ?
																	       6'd42 :
																	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[13] ?
																		  6'd43 :
																		  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[12] ?
																		     6'd44 :
																		     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[11] ?
																			6'd45 :
																			(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[10] ?
																			   6'd46 :
																			   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[9] ?
																			      6'd47 :
																			      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[8] ?
																				 6'd48 :
																				 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[7] ?
																				    6'd49 :
																				    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[6] ?
																				       6'd50 :
																				       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ?
																					  6'd51 :
																					  6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 =
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6795 ^
	      12'h800) <=
	     12'd2175 ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 =
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6795 ^
	      12'h800) <
	     12'd1922 ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7968 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 &&
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7953[4] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965[4]) ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7993 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 &&
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7953[3] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965[3]) ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8020 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 &&
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7953[1] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965[1]) ;
  assign _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10134 =
	     12'd3074 -
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 ;
  assign _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8649 =
	     12'd3074 -
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8646 ;
  assign _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9364 =
	     12'd3074 -
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9361 ;
  assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 =
	     12'd3970 -
	     { 7'd0,
	       f2_sfd__h521137[22] ?
		 5'd0 :
		 (f2_sfd__h521137[21] ?
		    5'd1 :
		    (f2_sfd__h521137[20] ?
		       5'd2 :
		       (f2_sfd__h521137[19] ?
			  5'd3 :
			  (f2_sfd__h521137[18] ?
			     5'd4 :
			     (f2_sfd__h521137[17] ?
				5'd5 :
				(f2_sfd__h521137[16] ?
				   5'd6 :
				   (f2_sfd__h521137[15] ?
				      5'd7 :
				      (f2_sfd__h521137[14] ?
					 5'd8 :
					 (f2_sfd__h521137[13] ?
					    5'd9 :
					    (f2_sfd__h521137[12] ?
					       5'd10 :
					       (f2_sfd__h521137[11] ?
						  5'd11 :
						  (f2_sfd__h521137[10] ?
						     5'd12 :
						     (f2_sfd__h521137[9] ?
							5'd13 :
							(f2_sfd__h521137[8] ?
							   5'd14 :
							   (f2_sfd__h521137[7] ?
							      5'd15 :
							      (f2_sfd__h521137[6] ?
								 5'd16 :
								 (f2_sfd__h521137[5] ?
								    5'd17 :
								    (f2_sfd__h521137[4] ?
								       5'd18 :
								       (f2_sfd__h521137[3] ?
									  5'd19 :
									  (f2_sfd__h521137[2] ?
									     5'd20 :
									     (f2_sfd__h521137[1] ?
										5'd21 :
										(f2_sfd__h521137[0] ?
										   5'd22 :
										   5'd23)))))))))))))))))))))) } ;
  assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 =
	     (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 ^
	      12'h800) <=
	     12'd3071 ;
  assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 =
	     (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 ^
	      12'h800) <
	     12'd1026 ;
  assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 =
	     12'd3970 -
	     { 7'd0,
	       f1_sfd__h482143[22] ?
		 5'd0 :
		 (f1_sfd__h482143[21] ?
		    5'd1 :
		    (f1_sfd__h482143[20] ?
		       5'd2 :
		       (f1_sfd__h482143[19] ?
			  5'd3 :
			  (f1_sfd__h482143[18] ?
			     5'd4 :
			     (f1_sfd__h482143[17] ?
				5'd5 :
				(f1_sfd__h482143[16] ?
				   5'd6 :
				   (f1_sfd__h482143[15] ?
				      5'd7 :
				      (f1_sfd__h482143[14] ?
					 5'd8 :
					 (f1_sfd__h482143[13] ?
					    5'd9 :
					    (f1_sfd__h482143[12] ?
					       5'd10 :
					       (f1_sfd__h482143[11] ?
						  5'd11 :
						  (f1_sfd__h482143[10] ?
						     5'd12 :
						     (f1_sfd__h482143[9] ?
							5'd13 :
							(f1_sfd__h482143[8] ?
							   5'd14 :
							   (f1_sfd__h482143[7] ?
							      5'd15 :
							      (f1_sfd__h482143[6] ?
								 5'd16 :
								 (f1_sfd__h482143[5] ?
								    5'd17 :
								    (f1_sfd__h482143[4] ?
								       5'd18 :
								       (f1_sfd__h482143[3] ?
									  5'd19 :
									  (f1_sfd__h482143[2] ?
									     5'd20 :
									     (f1_sfd__h482143[1] ?
										5'd21 :
										(f1_sfd__h482143[0] ?
										   5'd22 :
										   5'd23)))))))))))))))))))))) } ;
  assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 =
	     (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 ^
	      12'h800) <=
	     12'd3071 ;
  assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 =
	     (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 ^
	      12'h800) <
	     12'd1026 ;
  assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 =
	     12'd3970 -
	     { 7'd0,
	       f3_sfd__h560441[22] ?
		 5'd0 :
		 (f3_sfd__h560441[21] ?
		    5'd1 :
		    (f3_sfd__h560441[20] ?
		       5'd2 :
		       (f3_sfd__h560441[19] ?
			  5'd3 :
			  (f3_sfd__h560441[18] ?
			     5'd4 :
			     (f3_sfd__h560441[17] ?
				5'd5 :
				(f3_sfd__h560441[16] ?
				   5'd6 :
				   (f3_sfd__h560441[15] ?
				      5'd7 :
				      (f3_sfd__h560441[14] ?
					 5'd8 :
					 (f3_sfd__h560441[13] ?
					    5'd9 :
					    (f3_sfd__h560441[12] ?
					       5'd10 :
					       (f3_sfd__h560441[11] ?
						  5'd11 :
						  (f3_sfd__h560441[10] ?
						     5'd12 :
						     (f3_sfd__h560441[9] ?
							5'd13 :
							(f3_sfd__h560441[8] ?
							   5'd14 :
							   (f3_sfd__h560441[7] ?
							      5'd15 :
							      (f3_sfd__h560441[6] ?
								 5'd16 :
								 (f3_sfd__h560441[5] ?
								    5'd17 :
								    (f3_sfd__h560441[4] ?
								       5'd18 :
								       (f3_sfd__h560441[3] ?
									  5'd19 :
									  (f3_sfd__h560441[2] ?
									     5'd20 :
									     (f3_sfd__h560441[1] ?
										5'd21 :
										(f3_sfd__h560441[0] ?
										   5'd22 :
										   5'd23)))))))))))))))))))))) } ;
  assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 =
	     (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 ^
	      12'h800) <=
	     12'd3071 ;
  assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 =
	     (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 ^
	      12'h800) <
	     12'd1026 ;
  assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554 =
	     12'd3970 -
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4551 ;
  assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946 =
	     12'd3970 -
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5943 ;
  assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338 =
	     12'd3970 -
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7335 ;
  assign _dfoo12 =
	     fetchStage$pipelines_0_canDeq &&
	     regRenamingTable_rename_0_canRename__3418_AND__ETC___d14133 ||
	     NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 &&
	     regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219 &&
	     fetchStage$pipelines_1_first[194:192] == 3'd2 &&
	     NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd14 ;
  assign _dfoo16 =
	     k__h670634 == 1'd1 &&
	     fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14115 ||
	     (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14191 ||
	      NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14204) ==
	     1'd1 &&
	     NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14223 ;
  assign _dfoo18 =
	     k__h670634 == 1'd0 &&
	     fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14115 ||
	     (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14191 ||
	      NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14204) ==
	     1'd0 &&
	     NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14223 ;
  assign _dfoo2 =
	     fetchStage$pipelines_0_canDeq &&
	     regRenamingTable_rename_0_canRename__3418_AND__ETC___d14161 ||
	     NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 &&
	     regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219 &&
	     fetchStage$pipelines_1_first[194:192] == 3'd2 &&
	     NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268 &&
	     fetchStage$pipelines_1_first[191:189] != 3'd0 &&
	     fetchStage$pipelines_1_first[191:189] != 3'd2 ;
  assign _dfoo20 =
	     commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 ||
	     NOT_commitStage_commitTrap_4362_BIT_36_4604_46_ETC___d14710 ;
  assign _dfoo24 =
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd40 ||
	     rob$deqPort_0_deq_data[329:325] == 5'd19 ||
	     rob$deqPort_0_deq_data[329:325] == 5'd20 ;
  assign _dfoo26 =
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	     6'd18 ||
	     rob$deqPort_0_deq_data[329:325] == 5'd20 ;
  assign _dfoo32 =
	     rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd8 ||
	      IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 ==
	      6'd18) ||
	     rob$deqPort_0_deq_data[329:325] == 5'd19 ;
  assign _dfoo7 =
	     fetchStage$pipelines_0_canDeq &&
	     regRenamingTable_rename_0_canRename__3418_AND__ETC___d14153 ||
	     NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14209 &&
	     regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219 &&
	     fetchStage$pipelines_1_first[194:192] == 3'd2 &&
	     NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14268 &&
	     (fetchStage$pipelines_1_first[191:189] == 3'd0 ||
	      fetchStage$pipelines_1_first[191:189] == 3'd2) ;
  assign _dor1coreFix_aluExe_0_bypassWire_2$EN_wset =
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
  assign _dor1coreFix_aluExe_0_bypassWire_3$EN_wset =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
  assign _dor1coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1coreFix_aluExe_1_bypassWire_2$EN_wset =
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
  assign _dor1coreFix_aluExe_1_bypassWire_3$EN_wset =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
  assign _dor1coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1coreFix_fpuMulDivExe_0_bypassWire_2$EN_wset =
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
  assign _dor1coreFix_fpuMulDivExe_0_bypassWire_3$EN_wset =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
  assign _dor1coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1coreFix_memExe_bypassWire_2$EN_wset =
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
  assign _dor1coreFix_memExe_bypassWire_3$EN_wset =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
  assign _dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1coreFix_memExe_rsMem$EN_setRegReady_3_put =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1rf$EN_write_0_wr =
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
  assign _dor1rf$EN_write_1_wr =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
  assign _dor1sbAggr$EN_setReady_3_put =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1sbCons$EN_setReady_0_put =
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
  assign _dor1sbCons$EN_setReady_1_put =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
  assign _theResult_____2__h296523 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3046) ?
	       next_deqP___1__h296802 :
	       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ;
  assign _theResult_____2__h304519 =
	     (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3153) ?
	       next_deqP___1__h304798 :
	       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ;
  assign _theResult_____2__h310513 =
	     (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3324) ?
	       next_deqP___1__h311079 :
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ;
  assign _theResult_____2__h318367 =
	     (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3420) ?
	       next_deqP___1__h318933 :
	       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ;
  assign _theResult_____2__h328711 =
	     (coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3649) ?
	       next_deqP___1__h328990 :
	       coreFix_memExe_memRespLdQ_deqP ;
  assign _theResult_____2__h331936 =
	     (coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3743) ?
	       next_deqP___1__h332215 :
	       coreFix_memExe_forwardQ_deqP ;
  assign _theResult____h346087 =
	     (value__h346709 == 54'd0) ? sfd__h338482 : 57'd1 ;
  assign _theResult____h363726 =
	     ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554 ^
	       12'h800) <
	      12'd2105) ?
	       result__h364339 :
	       _theResult____h346087 ;
  assign _theResult____h391786 =
	     (value__h392406 == 54'd0) ? sfd__h384184 : 57'd1 ;
  assign _theResult____h409423 =
	     ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946 ^
	       12'h800) <
	      12'd2105) ?
	       result__h410036 :
	       _theResult____h391786 ;
  assign _theResult____h437481 =
	     (value__h438101 == 54'd0) ? sfd__h429879 : 57'd1 ;
  assign _theResult____h455118 =
	     ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338 ^
	       12'h800) <
	      12'd2105) ?
	       result__h455731 :
	       _theResult____h437481 ;
  assign _theResult____h502871 =
	     ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8649 ^
	       12'h800) <
	      12'd2105) ?
	       result__h503484 :
	       ((value__h487087 == 25'd0) ? sfd__h482504 : 57'd1) ;
  assign _theResult____h541724 =
	     ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10134 ^
	       12'h800) <
	      12'd2105) ?
	       result__h542337 :
	       ((value__h525940 == 25'd0) ? sfd__h521498 : 57'd1) ;
  assign _theResult____h581028 =
	     ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9364 ^
	       12'h800) <
	      12'd2105) ?
	       result__h581641 :
	       ((value__h565244 == 25'd0) ? sfd__h560802 : 57'd1) ;
  assign _theResult____h651123 =
	     (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ?
	       enabled_ints___1__h651648 :
	       16'd0 ;
  assign _theResult___exp__h354714 =
	     sfd__h354290[24] ?
	       ((_theResult___fst_exp__h354198 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h381231) :
	       ((_theResult___fst_exp__h354198 == 8'd0 &&
		 sfd__h354290[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h354198) ;
  assign _theResult___exp__h363296 =
	     sfd__h362872[24] ?
	       ((_theResult___fst_exp__h362854 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h381255) :
	       ((_theResult___fst_exp__h362854 == 8'd0 &&
		 sfd__h362872[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h362854) ;
  assign _theResult___exp__h372480 =
	     sfd__h372056[24] ?
	       ((_theResult___fst_exp__h371964 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h381285) :
	       ((_theResult___fst_exp__h371964 == 8'd0 &&
		 sfd__h372056[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h371964) ;
  assign _theResult___exp__h381116 =
	     sfd__h380668[24] ?
	       ((_theResult___fst_exp__h380649 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h381309) :
	       ((_theResult___fst_exp__h380649 == 8'd0 &&
		 sfd__h380668[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h380649) ;
  assign _theResult___exp__h381218 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd2047) ?
	       8'd255 :
	       _theResult___fst_exp__h381209 ;
  assign _theResult___exp__h400411 =
	     sfd__h399987[24] ?
	       ((_theResult___fst_exp__h399895 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h426928) :
	       ((_theResult___fst_exp__h399895 == 8'd0 &&
		 sfd__h399987[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h399895) ;
  assign _theResult___exp__h408993 =
	     sfd__h408569[24] ?
	       ((_theResult___fst_exp__h408551 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h426952) :
	       ((_theResult___fst_exp__h408551 == 8'd0 &&
		 sfd__h408569[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h408551) ;
  assign _theResult___exp__h418177 =
	     sfd__h417753[24] ?
	       ((_theResult___fst_exp__h417661 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h426982) :
	       ((_theResult___fst_exp__h417661 == 8'd0 &&
		 sfd__h417753[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h417661) ;
  assign _theResult___exp__h426813 =
	     sfd__h426365[24] ?
	       ((_theResult___fst_exp__h426346 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h427006) :
	       ((_theResult___fst_exp__h426346 == 8'd0 &&
		 sfd__h426365[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h426346) ;
  assign _theResult___exp__h426915 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd2047) ?
	       8'd255 :
	       _theResult___fst_exp__h426906 ;
  assign _theResult___exp__h446106 =
	     sfd__h445682[24] ?
	       ((_theResult___fst_exp__h445590 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h472623) :
	       ((_theResult___fst_exp__h445590 == 8'd0 &&
		 sfd__h445682[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h445590) ;
  assign _theResult___exp__h454688 =
	     sfd__h454264[24] ?
	       ((_theResult___fst_exp__h454246 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h472647) :
	       ((_theResult___fst_exp__h454246 == 8'd0 &&
		 sfd__h454264[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h454246) ;
  assign _theResult___exp__h463872 =
	     sfd__h463448[24] ?
	       ((_theResult___fst_exp__h463356 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h472677) :
	       ((_theResult___fst_exp__h463356 == 8'd0 &&
		 sfd__h463448[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h463356) ;
  assign _theResult___exp__h472508 =
	     sfd__h472060[24] ?
	       ((_theResult___fst_exp__h472041 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h472701) :
	       ((_theResult___fst_exp__h472041 == 8'd0 &&
		 sfd__h472060[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h472041) ;
  assign _theResult___exp__h472610 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd2047) ?
	       8'd255 :
	       _theResult___fst_exp__h472601 ;
  assign _theResult___exp__h502185 =
	     sfd__h501548[53] ?
	       ((_theResult___fst_exp__h501530 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h520780) :
	       ((_theResult___fst_exp__h501530 == 11'd0 &&
		 sfd__h501548[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h501530) ;
  assign _theResult___exp__h511836 =
	     sfd__h511199[53] ?
	       ((_theResult___fst_exp__h511107 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h520815) :
	       ((_theResult___fst_exp__h511107 == 11'd0 &&
		 sfd__h511199[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h511107) ;
  assign _theResult___exp__h520620 =
	     sfd__h519959[53] ?
	       ((_theResult___fst_exp__h519940 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h520841) :
	       ((_theResult___fst_exp__h519940 == 11'd0 &&
		 sfd__h519959[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h519940) ;
  assign _theResult___exp__h541038 =
	     sfd__h540401[53] ?
	       ((_theResult___fst_exp__h540383 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h559633) :
	       ((_theResult___fst_exp__h540383 == 11'd0 &&
		 sfd__h540401[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h540383) ;
  assign _theResult___exp__h550689 =
	     sfd__h550052[53] ?
	       ((_theResult___fst_exp__h549960 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h559668) :
	       ((_theResult___fst_exp__h549960 == 11'd0 &&
		 sfd__h550052[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h549960) ;
  assign _theResult___exp__h559473 =
	     sfd__h558812[53] ?
	       ((_theResult___fst_exp__h558793 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h559694) :
	       ((_theResult___fst_exp__h558793 == 11'd0 &&
		 sfd__h558812[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h558793) ;
  assign _theResult___exp__h580342 =
	     sfd__h579705[53] ?
	       ((_theResult___fst_exp__h579687 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h598937) :
	       ((_theResult___fst_exp__h579687 == 11'd0 &&
		 sfd__h579705[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h579687) ;
  assign _theResult___exp__h589993 =
	     sfd__h589356[53] ?
	       ((_theResult___fst_exp__h589264 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h598972) :
	       ((_theResult___fst_exp__h589264 == 11'd0 &&
		 sfd__h589356[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h589264) ;
  assign _theResult___exp__h598777 =
	     sfd__h598116[53] ?
	       ((_theResult___fst_exp__h598097 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h598998) :
	       ((_theResult___fst_exp__h598097 == 11'd0 &&
		 sfd__h598116[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h598097) ;
  assign _theResult___fst__h603372 =
	     a__h602950[63] ? a___1__h603377 : a__h602950 ;
  assign _theResult___fst_exp__h354198 =
	     _theResult____h346087[56] ?
	       8'd2 :
	       _theResult___fst_exp__h354272 ;
  assign _theResult___fst_exp__h354263 =
	     8'd0 -
	     { 2'd0,
	       IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247 } ;
  assign _theResult___fst_exp__h354269 =
	     (!_theResult____h346087[56] && !_theResult____h346087[55] &&
	      !_theResult____h346087[54] &&
	      !_theResult____h346087[53] &&
	      !_theResult____h346087[52] &&
	      !_theResult____h346087[51] &&
	      !_theResult____h346087[50] &&
	      !_theResult____h346087[49] &&
	      !_theResult____h346087[48] &&
	      !_theResult____h346087[47] &&
	      !_theResult____h346087[46] &&
	      !_theResult____h346087[45] &&
	      !_theResult____h346087[44] &&
	      !_theResult____h346087[43] &&
	      !_theResult____h346087[42] &&
	      !_theResult____h346087[41] &&
	      !_theResult____h346087[40] &&
	      !_theResult____h346087[39] &&
	      !_theResult____h346087[38] &&
	      !_theResult____h346087[37] &&
	      !_theResult____h346087[36] &&
	      !_theResult____h346087[35] &&
	      !_theResult____h346087[34] &&
	      !_theResult____h346087[33] &&
	      !_theResult____h346087[32] &&
	      !_theResult____h346087[31] &&
	      !_theResult____h346087[30] &&
	      !_theResult____h346087[29] &&
	      !_theResult____h346087[28] &&
	      !_theResult____h346087[27] &&
	      !_theResult____h346087[26] &&
	      !_theResult____h346087[25] &&
	      !_theResult____h346087[24] &&
	      !_theResult____h346087[23] &&
	      !_theResult____h346087[22] &&
	      !_theResult____h346087[21] &&
	      !_theResult____h346087[20] &&
	      !_theResult____h346087[19] &&
	      !_theResult____h346087[18] &&
	      !_theResult____h346087[17] &&
	      !_theResult____h346087[16] &&
	      !_theResult____h346087[15] &&
	      !_theResult____h346087[14] &&
	      !_theResult____h346087[13] &&
	      !_theResult____h346087[12] &&
	      !_theResult____h346087[11] &&
	      !_theResult____h346087[10] &&
	      !_theResult____h346087[9] &&
	      !_theResult____h346087[8] &&
	      !_theResult____h346087[7] &&
	      !_theResult____h346087[6] &&
	      !_theResult____h346087[5] &&
	      !_theResult____h346087[4] &&
	      !_theResult____h346087[3] &&
	      !_theResult____h346087[2] &&
	      !_theResult____h346087[1] &&
	      !_theResult____h346087[0] ||
	      !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4249) ?
	       8'd0 :
	       _theResult___fst_exp__h354263 ;
  assign _theResult___fst_exp__h354272 =
	     (!_theResult____h346087[56] && _theResult____h346087[55]) ?
	       8'd1 :
	       _theResult___fst_exp__h354269 ;
  assign _theResult___fst_exp__h354795 =
	     (_theResult___fst_exp__h354198 == 8'd255) ?
	       _theResult___fst_exp__h354198 :
	       _theResult___fst_exp__h354792 ;
  assign _theResult___fst_exp__h362845 =
	     8'd129 -
	     { 2'd0,
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 } ;
  assign _theResult___fst_exp__h362851 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423 ||
	      !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4480) ?
	       8'd0 :
	       _theResult___fst_exp__h362845 ;
  assign _theResult___fst_exp__h362854 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       _theResult___fst_exp__h362851 :
	       8'd129 ;
  assign _theResult___fst_exp__h363377 =
	     (_theResult___fst_exp__h362854 == 8'd255) ?
	       _theResult___fst_exp__h362854 :
	       _theResult___fst_exp__h363374 ;
  assign _theResult___fst_exp__h371964 =
	     _theResult____h363726[56] ?
	       8'd2 :
	       _theResult___fst_exp__h372038 ;
  assign _theResult___fst_exp__h372029 =
	     8'd0 -
	     { 2'd0,
	       IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4798 } ;
  assign _theResult___fst_exp__h372035 =
	     (!_theResult____h363726[56] && !_theResult____h363726[55] &&
	      !_theResult____h363726[54] &&
	      !_theResult____h363726[53] &&
	      !_theResult____h363726[52] &&
	      !_theResult____h363726[51] &&
	      !_theResult____h363726[50] &&
	      !_theResult____h363726[49] &&
	      !_theResult____h363726[48] &&
	      !_theResult____h363726[47] &&
	      !_theResult____h363726[46] &&
	      !_theResult____h363726[45] &&
	      !_theResult____h363726[44] &&
	      !_theResult____h363726[43] &&
	      !_theResult____h363726[42] &&
	      !_theResult____h363726[41] &&
	      !_theResult____h363726[40] &&
	      !_theResult____h363726[39] &&
	      !_theResult____h363726[38] &&
	      !_theResult____h363726[37] &&
	      !_theResult____h363726[36] &&
	      !_theResult____h363726[35] &&
	      !_theResult____h363726[34] &&
	      !_theResult____h363726[33] &&
	      !_theResult____h363726[32] &&
	      !_theResult____h363726[31] &&
	      !_theResult____h363726[30] &&
	      !_theResult____h363726[29] &&
	      !_theResult____h363726[28] &&
	      !_theResult____h363726[27] &&
	      !_theResult____h363726[26] &&
	      !_theResult____h363726[25] &&
	      !_theResult____h363726[24] &&
	      !_theResult____h363726[23] &&
	      !_theResult____h363726[22] &&
	      !_theResult____h363726[21] &&
	      !_theResult____h363726[20] &&
	      !_theResult____h363726[19] &&
	      !_theResult____h363726[18] &&
	      !_theResult____h363726[17] &&
	      !_theResult____h363726[16] &&
	      !_theResult____h363726[15] &&
	      !_theResult____h363726[14] &&
	      !_theResult____h363726[13] &&
	      !_theResult____h363726[12] &&
	      !_theResult____h363726[11] &&
	      !_theResult____h363726[10] &&
	      !_theResult____h363726[9] &&
	      !_theResult____h363726[8] &&
	      !_theResult____h363726[7] &&
	      !_theResult____h363726[6] &&
	      !_theResult____h363726[5] &&
	      !_theResult____h363726[4] &&
	      !_theResult____h363726[3] &&
	      !_theResult____h363726[2] &&
	      !_theResult____h363726[1] &&
	      !_theResult____h363726[0] ||
	      !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4800) ?
	       8'd0 :
	       _theResult___fst_exp__h372029 ;
  assign _theResult___fst_exp__h372038 =
	     (!_theResult____h363726[56] && _theResult____h363726[55]) ?
	       8'd1 :
	       _theResult___fst_exp__h372035 ;
  assign _theResult___fst_exp__h372561 =
	     (_theResult___fst_exp__h371964 == 8'd255) ?
	       _theResult___fst_exp__h371964 :
	       _theResult___fst_exp__h372558 ;
  assign _theResult___fst_exp__h380601 =
	     (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] ==
	      8'd0) ?
	       8'd1 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] ;
  assign _theResult___fst_exp__h380640 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] -
	     { 2'd0,
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 } ;
  assign _theResult___fst_exp__h380646 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423 ||
	      !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4873) ?
	       8'd0 :
	       _theResult___fst_exp__h380640 ;
  assign _theResult___fst_exp__h380649 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       _theResult___fst_exp__h380646 :
	       _theResult___fst_exp__h380601 ;
  assign _theResult___fst_exp__h381197 =
	     (_theResult___fst_exp__h380649 == 8'd255) ?
	       _theResult___fst_exp__h380649 :
	       _theResult___fst_exp__h381194 ;
  assign _theResult___fst_exp__h381206 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 ?
		  _theResult___snd_fst_exp__h363380 :
		  _theResult___fst_exp__h346069) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 ?
		  _theResult___snd_fst_exp__h381200 :
		  _theResult___fst_exp__h346069) ;
  assign _theResult___fst_exp__h381209 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
	      52'd0) ?
	       8'd0 :
	       _theResult___fst_exp__h381206 ;
  assign _theResult___fst_exp__h399895 =
	     _theResult____h391786[56] ?
	       8'd2 :
	       _theResult___fst_exp__h399969 ;
  assign _theResult___fst_exp__h399960 =
	     8'd0 -
	     { 2'd0,
	       IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 } ;
  assign _theResult___fst_exp__h399966 =
	     (!_theResult____h391786[56] && !_theResult____h391786[55] &&
	      !_theResult____h391786[54] &&
	      !_theResult____h391786[53] &&
	      !_theResult____h391786[52] &&
	      !_theResult____h391786[51] &&
	      !_theResult____h391786[50] &&
	      !_theResult____h391786[49] &&
	      !_theResult____h391786[48] &&
	      !_theResult____h391786[47] &&
	      !_theResult____h391786[46] &&
	      !_theResult____h391786[45] &&
	      !_theResult____h391786[44] &&
	      !_theResult____h391786[43] &&
	      !_theResult____h391786[42] &&
	      !_theResult____h391786[41] &&
	      !_theResult____h391786[40] &&
	      !_theResult____h391786[39] &&
	      !_theResult____h391786[38] &&
	      !_theResult____h391786[37] &&
	      !_theResult____h391786[36] &&
	      !_theResult____h391786[35] &&
	      !_theResult____h391786[34] &&
	      !_theResult____h391786[33] &&
	      !_theResult____h391786[32] &&
	      !_theResult____h391786[31] &&
	      !_theResult____h391786[30] &&
	      !_theResult____h391786[29] &&
	      !_theResult____h391786[28] &&
	      !_theResult____h391786[27] &&
	      !_theResult____h391786[26] &&
	      !_theResult____h391786[25] &&
	      !_theResult____h391786[24] &&
	      !_theResult____h391786[23] &&
	      !_theResult____h391786[22] &&
	      !_theResult____h391786[21] &&
	      !_theResult____h391786[20] &&
	      !_theResult____h391786[19] &&
	      !_theResult____h391786[18] &&
	      !_theResult____h391786[17] &&
	      !_theResult____h391786[16] &&
	      !_theResult____h391786[15] &&
	      !_theResult____h391786[14] &&
	      !_theResult____h391786[13] &&
	      !_theResult____h391786[12] &&
	      !_theResult____h391786[11] &&
	      !_theResult____h391786[10] &&
	      !_theResult____h391786[9] &&
	      !_theResult____h391786[8] &&
	      !_theResult____h391786[7] &&
	      !_theResult____h391786[6] &&
	      !_theResult____h391786[5] &&
	      !_theResult____h391786[4] &&
	      !_theResult____h391786[3] &&
	      !_theResult____h391786[2] &&
	      !_theResult____h391786[1] &&
	      !_theResult____h391786[0] ||
	      !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5641) ?
	       8'd0 :
	       _theResult___fst_exp__h399960 ;
  assign _theResult___fst_exp__h399969 =
	     (!_theResult____h391786[56] && _theResult____h391786[55]) ?
	       8'd1 :
	       _theResult___fst_exp__h399966 ;
  assign _theResult___fst_exp__h400492 =
	     (_theResult___fst_exp__h399895 == 8'd255) ?
	       _theResult___fst_exp__h399895 :
	       _theResult___fst_exp__h400489 ;
  assign _theResult___fst_exp__h408542 =
	     8'd129 -
	     { 2'd0,
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 } ;
  assign _theResult___fst_exp__h408548 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815 ||
	      !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5872) ?
	       8'd0 :
	       _theResult___fst_exp__h408542 ;
  assign _theResult___fst_exp__h408551 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       _theResult___fst_exp__h408548 :
	       8'd129 ;
  assign _theResult___fst_exp__h409074 =
	     (_theResult___fst_exp__h408551 == 8'd255) ?
	       _theResult___fst_exp__h408551 :
	       _theResult___fst_exp__h409071 ;
  assign _theResult___fst_exp__h417661 =
	     _theResult____h409423[56] ?
	       8'd2 :
	       _theResult___fst_exp__h417735 ;
  assign _theResult___fst_exp__h417726 =
	     8'd0 -
	     { 2'd0,
	       IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 } ;
  assign _theResult___fst_exp__h417732 =
	     (!_theResult____h409423[56] && !_theResult____h409423[55] &&
	      !_theResult____h409423[54] &&
	      !_theResult____h409423[53] &&
	      !_theResult____h409423[52] &&
	      !_theResult____h409423[51] &&
	      !_theResult____h409423[50] &&
	      !_theResult____h409423[49] &&
	      !_theResult____h409423[48] &&
	      !_theResult____h409423[47] &&
	      !_theResult____h409423[46] &&
	      !_theResult____h409423[45] &&
	      !_theResult____h409423[44] &&
	      !_theResult____h409423[43] &&
	      !_theResult____h409423[42] &&
	      !_theResult____h409423[41] &&
	      !_theResult____h409423[40] &&
	      !_theResult____h409423[39] &&
	      !_theResult____h409423[38] &&
	      !_theResult____h409423[37] &&
	      !_theResult____h409423[36] &&
	      !_theResult____h409423[35] &&
	      !_theResult____h409423[34] &&
	      !_theResult____h409423[33] &&
	      !_theResult____h409423[32] &&
	      !_theResult____h409423[31] &&
	      !_theResult____h409423[30] &&
	      !_theResult____h409423[29] &&
	      !_theResult____h409423[28] &&
	      !_theResult____h409423[27] &&
	      !_theResult____h409423[26] &&
	      !_theResult____h409423[25] &&
	      !_theResult____h409423[24] &&
	      !_theResult____h409423[23] &&
	      !_theResult____h409423[22] &&
	      !_theResult____h409423[21] &&
	      !_theResult____h409423[20] &&
	      !_theResult____h409423[19] &&
	      !_theResult____h409423[18] &&
	      !_theResult____h409423[17] &&
	      !_theResult____h409423[16] &&
	      !_theResult____h409423[15] &&
	      !_theResult____h409423[14] &&
	      !_theResult____h409423[13] &&
	      !_theResult____h409423[12] &&
	      !_theResult____h409423[11] &&
	      !_theResult____h409423[10] &&
	      !_theResult____h409423[9] &&
	      !_theResult____h409423[8] &&
	      !_theResult____h409423[7] &&
	      !_theResult____h409423[6] &&
	      !_theResult____h409423[5] &&
	      !_theResult____h409423[4] &&
	      !_theResult____h409423[3] &&
	      !_theResult____h409423[2] &&
	      !_theResult____h409423[1] &&
	      !_theResult____h409423[0] ||
	      !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6192) ?
	       8'd0 :
	       _theResult___fst_exp__h417726 ;
  assign _theResult___fst_exp__h417735 =
	     (!_theResult____h409423[56] && _theResult____h409423[55]) ?
	       8'd1 :
	       _theResult___fst_exp__h417732 ;
  assign _theResult___fst_exp__h418258 =
	     (_theResult___fst_exp__h417661 == 8'd255) ?
	       _theResult___fst_exp__h417661 :
	       _theResult___fst_exp__h418255 ;
  assign _theResult___fst_exp__h426298 =
	     (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] ==
	      8'd0) ?
	       8'd1 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] ;
  assign _theResult___fst_exp__h426337 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] -
	     { 2'd0,
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 } ;
  assign _theResult___fst_exp__h426343 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815 ||
	      !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6265) ?
	       8'd0 :
	       _theResult___fst_exp__h426337 ;
  assign _theResult___fst_exp__h426346 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       _theResult___fst_exp__h426343 :
	       _theResult___fst_exp__h426298 ;
  assign _theResult___fst_exp__h426894 =
	     (_theResult___fst_exp__h426346 == 8'd255) ?
	       _theResult___fst_exp__h426346 :
	       _theResult___fst_exp__h426891 ;
  assign _theResult___fst_exp__h426903 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 ?
		  _theResult___snd_fst_exp__h409077 :
		  _theResult___fst_exp__h391768) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 ?
		  _theResult___snd_fst_exp__h426897 :
		  _theResult___fst_exp__h391768) ;
  assign _theResult___fst_exp__h426906 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
	      52'd0) ?
	       8'd0 :
	       _theResult___fst_exp__h426903 ;
  assign _theResult___fst_exp__h445590 =
	     _theResult____h437481[56] ?
	       8'd2 :
	       _theResult___fst_exp__h445664 ;
  assign _theResult___fst_exp__h445655 =
	     8'd0 -
	     { 2'd0,
	       IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 } ;
  assign _theResult___fst_exp__h445661 =
	     (!_theResult____h437481[56] && !_theResult____h437481[55] &&
	      !_theResult____h437481[54] &&
	      !_theResult____h437481[53] &&
	      !_theResult____h437481[52] &&
	      !_theResult____h437481[51] &&
	      !_theResult____h437481[50] &&
	      !_theResult____h437481[49] &&
	      !_theResult____h437481[48] &&
	      !_theResult____h437481[47] &&
	      !_theResult____h437481[46] &&
	      !_theResult____h437481[45] &&
	      !_theResult____h437481[44] &&
	      !_theResult____h437481[43] &&
	      !_theResult____h437481[42] &&
	      !_theResult____h437481[41] &&
	      !_theResult____h437481[40] &&
	      !_theResult____h437481[39] &&
	      !_theResult____h437481[38] &&
	      !_theResult____h437481[37] &&
	      !_theResult____h437481[36] &&
	      !_theResult____h437481[35] &&
	      !_theResult____h437481[34] &&
	      !_theResult____h437481[33] &&
	      !_theResult____h437481[32] &&
	      !_theResult____h437481[31] &&
	      !_theResult____h437481[30] &&
	      !_theResult____h437481[29] &&
	      !_theResult____h437481[28] &&
	      !_theResult____h437481[27] &&
	      !_theResult____h437481[26] &&
	      !_theResult____h437481[25] &&
	      !_theResult____h437481[24] &&
	      !_theResult____h437481[23] &&
	      !_theResult____h437481[22] &&
	      !_theResult____h437481[21] &&
	      !_theResult____h437481[20] &&
	      !_theResult____h437481[19] &&
	      !_theResult____h437481[18] &&
	      !_theResult____h437481[17] &&
	      !_theResult____h437481[16] &&
	      !_theResult____h437481[15] &&
	      !_theResult____h437481[14] &&
	      !_theResult____h437481[13] &&
	      !_theResult____h437481[12] &&
	      !_theResult____h437481[11] &&
	      !_theResult____h437481[10] &&
	      !_theResult____h437481[9] &&
	      !_theResult____h437481[8] &&
	      !_theResult____h437481[7] &&
	      !_theResult____h437481[6] &&
	      !_theResult____h437481[5] &&
	      !_theResult____h437481[4] &&
	      !_theResult____h437481[3] &&
	      !_theResult____h437481[2] &&
	      !_theResult____h437481[1] &&
	      !_theResult____h437481[0] ||
	      !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7033) ?
	       8'd0 :
	       _theResult___fst_exp__h445655 ;
  assign _theResult___fst_exp__h445664 =
	     (!_theResult____h437481[56] && _theResult____h437481[55]) ?
	       8'd1 :
	       _theResult___fst_exp__h445661 ;
  assign _theResult___fst_exp__h446187 =
	     (_theResult___fst_exp__h445590 == 8'd255) ?
	       _theResult___fst_exp__h445590 :
	       _theResult___fst_exp__h446184 ;
  assign _theResult___fst_exp__h454237 =
	     8'd129 -
	     { 2'd0,
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 } ;
  assign _theResult___fst_exp__h454243 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207 ||
	      !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7264) ?
	       8'd0 :
	       _theResult___fst_exp__h454237 ;
  assign _theResult___fst_exp__h454246 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       _theResult___fst_exp__h454243 :
	       8'd129 ;
  assign _theResult___fst_exp__h454769 =
	     (_theResult___fst_exp__h454246 == 8'd255) ?
	       _theResult___fst_exp__h454246 :
	       _theResult___fst_exp__h454766 ;
  assign _theResult___fst_exp__h463356 =
	     _theResult____h455118[56] ?
	       8'd2 :
	       _theResult___fst_exp__h463430 ;
  assign _theResult___fst_exp__h463421 =
	     8'd0 -
	     { 2'd0,
	       IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 } ;
  assign _theResult___fst_exp__h463427 =
	     (!_theResult____h455118[56] && !_theResult____h455118[55] &&
	      !_theResult____h455118[54] &&
	      !_theResult____h455118[53] &&
	      !_theResult____h455118[52] &&
	      !_theResult____h455118[51] &&
	      !_theResult____h455118[50] &&
	      !_theResult____h455118[49] &&
	      !_theResult____h455118[48] &&
	      !_theResult____h455118[47] &&
	      !_theResult____h455118[46] &&
	      !_theResult____h455118[45] &&
	      !_theResult____h455118[44] &&
	      !_theResult____h455118[43] &&
	      !_theResult____h455118[42] &&
	      !_theResult____h455118[41] &&
	      !_theResult____h455118[40] &&
	      !_theResult____h455118[39] &&
	      !_theResult____h455118[38] &&
	      !_theResult____h455118[37] &&
	      !_theResult____h455118[36] &&
	      !_theResult____h455118[35] &&
	      !_theResult____h455118[34] &&
	      !_theResult____h455118[33] &&
	      !_theResult____h455118[32] &&
	      !_theResult____h455118[31] &&
	      !_theResult____h455118[30] &&
	      !_theResult____h455118[29] &&
	      !_theResult____h455118[28] &&
	      !_theResult____h455118[27] &&
	      !_theResult____h455118[26] &&
	      !_theResult____h455118[25] &&
	      !_theResult____h455118[24] &&
	      !_theResult____h455118[23] &&
	      !_theResult____h455118[22] &&
	      !_theResult____h455118[21] &&
	      !_theResult____h455118[20] &&
	      !_theResult____h455118[19] &&
	      !_theResult____h455118[18] &&
	      !_theResult____h455118[17] &&
	      !_theResult____h455118[16] &&
	      !_theResult____h455118[15] &&
	      !_theResult____h455118[14] &&
	      !_theResult____h455118[13] &&
	      !_theResult____h455118[12] &&
	      !_theResult____h455118[11] &&
	      !_theResult____h455118[10] &&
	      !_theResult____h455118[9] &&
	      !_theResult____h455118[8] &&
	      !_theResult____h455118[7] &&
	      !_theResult____h455118[6] &&
	      !_theResult____h455118[5] &&
	      !_theResult____h455118[4] &&
	      !_theResult____h455118[3] &&
	      !_theResult____h455118[2] &&
	      !_theResult____h455118[1] &&
	      !_theResult____h455118[0] ||
	      !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7584) ?
	       8'd0 :
	       _theResult___fst_exp__h463421 ;
  assign _theResult___fst_exp__h463430 =
	     (!_theResult____h455118[56] && _theResult____h455118[55]) ?
	       8'd1 :
	       _theResult___fst_exp__h463427 ;
  assign _theResult___fst_exp__h463953 =
	     (_theResult___fst_exp__h463356 == 8'd255) ?
	       _theResult___fst_exp__h463356 :
	       _theResult___fst_exp__h463950 ;
  assign _theResult___fst_exp__h471993 =
	     (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] ==
	      8'd0) ?
	       8'd1 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] ;
  assign _theResult___fst_exp__h472032 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] -
	     { 2'd0,
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 } ;
  assign _theResult___fst_exp__h472038 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207 ||
	      !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7657) ?
	       8'd0 :
	       _theResult___fst_exp__h472032 ;
  assign _theResult___fst_exp__h472041 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       _theResult___fst_exp__h472038 :
	       _theResult___fst_exp__h471993 ;
  assign _theResult___fst_exp__h472589 =
	     (_theResult___fst_exp__h472041 == 8'd255) ?
	       _theResult___fst_exp__h472041 :
	       _theResult___fst_exp__h472586 ;
  assign _theResult___fst_exp__h472598 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 ?
		  _theResult___snd_fst_exp__h454772 :
		  _theResult___fst_exp__h437463) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 ?
		  _theResult___snd_fst_exp__h472592 :
		  _theResult___fst_exp__h437463) ;
  assign _theResult___fst_exp__h472601 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
	      52'd0) ?
	       8'd0 :
	       _theResult___fst_exp__h472598 ;
  assign _theResult___fst_exp__h486457 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
	       11'd2047 :
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 ;
  assign _theResult___fst_exp__h501521 =
	     11'd897 -
	     { 5'd0,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 } ;
  assign _theResult___fst_exp__h501527 =
	     (f1_exp__h482142 == 8'd0 && !f1_sfd__h482143[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556 ||
	      !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8585) ?
	       11'd0 :
	       _theResult___fst_exp__h501521 ;
  assign _theResult___fst_exp__h501530 =
	     (f1_exp__h482142 == 8'd0) ?
	       _theResult___fst_exp__h501527 :
	       11'd897 ;
  assign _theResult___fst_exp__h502285 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q144 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 ;
  assign _theResult___fst_exp__h502288 =
	     (_theResult___fst_exp__h501530 == 11'd2047) ?
	       _theResult___fst_exp__h501530 :
	       _theResult___fst_exp__h502285 ;
  assign _theResult___fst_exp__h511107 =
	     _theResult____h502871[56] ?
	       11'd2 :
	       _theResult___fst_exp__h511181 ;
  assign _theResult___fst_exp__h511172 =
	     11'd0 -
	     { 5'd0,
	       IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 } ;
  assign _theResult___fst_exp__h511178 =
	     (!_theResult____h502871[56] && !_theResult____h502871[55] &&
	      !_theResult____h502871[54] &&
	      !_theResult____h502871[53] &&
	      !_theResult____h502871[52] &&
	      !_theResult____h502871[51] &&
	      !_theResult____h502871[50] &&
	      !_theResult____h502871[49] &&
	      !_theResult____h502871[48] &&
	      !_theResult____h502871[47] &&
	      !_theResult____h502871[46] &&
	      !_theResult____h502871[45] &&
	      !_theResult____h502871[44] &&
	      !_theResult____h502871[43] &&
	      !_theResult____h502871[42] &&
	      !_theResult____h502871[41] &&
	      !_theResult____h502871[40] &&
	      !_theResult____h502871[39] &&
	      !_theResult____h502871[38] &&
	      !_theResult____h502871[37] &&
	      !_theResult____h502871[36] &&
	      !_theResult____h502871[35] &&
	      !_theResult____h502871[34] &&
	      !_theResult____h502871[33] &&
	      !_theResult____h502871[32] &&
	      !_theResult____h502871[31] &&
	      !_theResult____h502871[30] &&
	      !_theResult____h502871[29] &&
	      !_theResult____h502871[28] &&
	      !_theResult____h502871[27] &&
	      !_theResult____h502871[26] &&
	      !_theResult____h502871[25] &&
	      !_theResult____h502871[24] &&
	      !_theResult____h502871[23] &&
	      !_theResult____h502871[22] &&
	      !_theResult____h502871[21] &&
	      !_theResult____h502871[20] &&
	      !_theResult____h502871[19] &&
	      !_theResult____h502871[18] &&
	      !_theResult____h502871[17] &&
	      !_theResult____h502871[16] &&
	      !_theResult____h502871[15] &&
	      !_theResult____h502871[14] &&
	      !_theResult____h502871[13] &&
	      !_theResult____h502871[12] &&
	      !_theResult____h502871[11] &&
	      !_theResult____h502871[10] &&
	      !_theResult____h502871[9] &&
	      !_theResult____h502871[8] &&
	      !_theResult____h502871[7] &&
	      !_theResult____h502871[6] &&
	      !_theResult____h502871[5] &&
	      !_theResult____h502871[4] &&
	      !_theResult____h502871[3] &&
	      !_theResult____h502871[2] &&
	      !_theResult____h502871[1] &&
	      !_theResult____h502871[0] ||
	      !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8897) ?
	       11'd0 :
	       _theResult___fst_exp__h511172 ;
  assign _theResult___fst_exp__h511181 =
	     (!_theResult____h502871[56] && _theResult____h502871[55]) ?
	       11'd1 :
	       _theResult___fst_exp__h511178 ;
  assign _theResult___fst_exp__h511936 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q212 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 ;
  assign _theResult___fst_exp__h511939 =
	     (_theResult___fst_exp__h511107 == 11'd2047) ?
	       _theResult___fst_exp__h511107 :
	       _theResult___fst_exp__h511936 ;
  assign _theResult___fst_exp__h519892 =
	     (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] ==
	      11'd0) ?
	       11'd1 :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] ;
  assign _theResult___fst_exp__h519931 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] -
	     { 5'd0,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 } ;
  assign _theResult___fst_exp__h519937 =
	     (f1_exp__h482142 == 8'd0 && !f1_sfd__h482143[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556 ||
	      !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8947) ?
	       11'd0 :
	       _theResult___fst_exp__h519931 ;
  assign _theResult___fst_exp__h519940 =
	     (f1_exp__h482142 == 8'd0) ?
	       _theResult___fst_exp__h519937 :
	       _theResult___fst_exp__h519892 ;
  assign _theResult___fst_exp__h520720 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q214 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 ;
  assign _theResult___fst_exp__h520723 =
	     (_theResult___fst_exp__h519940 == 11'd2047) ?
	       _theResult___fst_exp__h519940 :
	       _theResult___fst_exp__h520720 ;
  assign _theResult___fst_exp__h520732 =
	     (f1_exp__h482142 == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 ?
		  _theResult___snd_fst_exp__h502291 :
		  _theResult___fst_exp__h486457) :
	       (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 ?
		  _theResult___snd_fst_exp__h520726 :
		  _theResult___fst_exp__h486457) ;
  assign _theResult___fst_exp__h520735 =
	     (f1_exp__h482142 == 8'd0 && f1_sfd__h482143 == 23'd0) ?
	       11'd0 :
	       _theResult___fst_exp__h520732 ;
  assign _theResult___fst_exp__h525310 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
	       11'd2047 :
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ;
  assign _theResult___fst_exp__h540374 =
	     11'd897 -
	     { 5'd0,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 } ;
  assign _theResult___fst_exp__h540380 =
	     (f2_exp__h521136 == 8'd0 && !f2_sfd__h521137[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056 ||
	      !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10085) ?
	       11'd0 :
	       _theResult___fst_exp__h540374 ;
  assign _theResult___fst_exp__h540383 =
	     (f2_exp__h521136 == 8'd0) ?
	       _theResult___fst_exp__h540380 :
	       11'd897 ;
  assign _theResult___fst_exp__h541138 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q184 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 ;
  assign _theResult___fst_exp__h541141 =
	     (_theResult___fst_exp__h540383 == 11'd2047) ?
	       _theResult___fst_exp__h540383 :
	       _theResult___fst_exp__h541138 ;
  assign _theResult___fst_exp__h549960 =
	     _theResult____h541724[56] ?
	       11'd2 :
	       _theResult___fst_exp__h550034 ;
  assign _theResult___fst_exp__h550025 =
	     11'd0 -
	     { 5'd0,
	       IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 } ;
  assign _theResult___fst_exp__h550031 =
	     (!_theResult____h541724[56] && !_theResult____h541724[55] &&
	      !_theResult____h541724[54] &&
	      !_theResult____h541724[53] &&
	      !_theResult____h541724[52] &&
	      !_theResult____h541724[51] &&
	      !_theResult____h541724[50] &&
	      !_theResult____h541724[49] &&
	      !_theResult____h541724[48] &&
	      !_theResult____h541724[47] &&
	      !_theResult____h541724[46] &&
	      !_theResult____h541724[45] &&
	      !_theResult____h541724[44] &&
	      !_theResult____h541724[43] &&
	      !_theResult____h541724[42] &&
	      !_theResult____h541724[41] &&
	      !_theResult____h541724[40] &&
	      !_theResult____h541724[39] &&
	      !_theResult____h541724[38] &&
	      !_theResult____h541724[37] &&
	      !_theResult____h541724[36] &&
	      !_theResult____h541724[35] &&
	      !_theResult____h541724[34] &&
	      !_theResult____h541724[33] &&
	      !_theResult____h541724[32] &&
	      !_theResult____h541724[31] &&
	      !_theResult____h541724[30] &&
	      !_theResult____h541724[29] &&
	      !_theResult____h541724[28] &&
	      !_theResult____h541724[27] &&
	      !_theResult____h541724[26] &&
	      !_theResult____h541724[25] &&
	      !_theResult____h541724[24] &&
	      !_theResult____h541724[23] &&
	      !_theResult____h541724[22] &&
	      !_theResult____h541724[21] &&
	      !_theResult____h541724[20] &&
	      !_theResult____h541724[19] &&
	      !_theResult____h541724[18] &&
	      !_theResult____h541724[17] &&
	      !_theResult____h541724[16] &&
	      !_theResult____h541724[15] &&
	      !_theResult____h541724[14] &&
	      !_theResult____h541724[13] &&
	      !_theResult____h541724[12] &&
	      !_theResult____h541724[11] &&
	      !_theResult____h541724[10] &&
	      !_theResult____h541724[9] &&
	      !_theResult____h541724[8] &&
	      !_theResult____h541724[7] &&
	      !_theResult____h541724[6] &&
	      !_theResult____h541724[5] &&
	      !_theResult____h541724[4] &&
	      !_theResult____h541724[3] &&
	      !_theResult____h541724[2] &&
	      !_theResult____h541724[1] &&
	      !_theResult____h541724[0] ||
	      !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10382) ?
	       11'd0 :
	       _theResult___fst_exp__h550025 ;
  assign _theResult___fst_exp__h550034 =
	     (!_theResult____h541724[56] && _theResult____h541724[55]) ?
	       11'd1 :
	       _theResult___fst_exp__h550031 ;
  assign _theResult___fst_exp__h550789 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q186 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 ;
  assign _theResult___fst_exp__h550792 =
	     (_theResult___fst_exp__h549960 == 11'd2047) ?
	       _theResult___fst_exp__h549960 :
	       _theResult___fst_exp__h550789 ;
  assign _theResult___fst_exp__h558745 =
	     (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] ==
	      11'd0) ?
	       11'd1 :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] ;
  assign _theResult___fst_exp__h558784 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] -
	     { 5'd0,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 } ;
  assign _theResult___fst_exp__h558790 =
	     (f2_exp__h521136 == 8'd0 && !f2_sfd__h521137[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056 ||
	      !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10432) ?
	       11'd0 :
	       _theResult___fst_exp__h558784 ;
  assign _theResult___fst_exp__h558793 =
	     (f2_exp__h521136 == 8'd0) ?
	       _theResult___fst_exp__h558790 :
	       _theResult___fst_exp__h558745 ;
  assign _theResult___fst_exp__h559573 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q188 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 ;
  assign _theResult___fst_exp__h559576 =
	     (_theResult___fst_exp__h558793 == 11'd2047) ?
	       _theResult___fst_exp__h558793 :
	       _theResult___fst_exp__h559573 ;
  assign _theResult___fst_exp__h559585 =
	     (f2_exp__h521136 == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ?
		  _theResult___snd_fst_exp__h541144 :
		  _theResult___fst_exp__h525310) :
	       (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 ?
		  _theResult___snd_fst_exp__h559579 :
		  _theResult___fst_exp__h525310) ;
  assign _theResult___fst_exp__h559588 =
	     (f2_exp__h521136 == 8'd0 && f2_sfd__h521137 == 23'd0) ?
	       11'd0 :
	       _theResult___fst_exp__h559585 ;
  assign _theResult___fst_exp__h564614 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
	       11'd2047 :
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 ;
  assign _theResult___fst_exp__h579678 =
	     11'd897 -
	     { 5'd0,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 } ;
  assign _theResult___fst_exp__h579684 =
	     (f3_exp__h560440 == 8'd0 && !f3_sfd__h560441[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286 ||
	      !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9315) ?
	       11'd0 :
	       _theResult___fst_exp__h579678 ;
  assign _theResult___fst_exp__h579687 =
	     (f3_exp__h560440 == 8'd0) ?
	       _theResult___fst_exp__h579684 :
	       11'd897 ;
  assign _theResult___fst_exp__h580442 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q161 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 ;
  assign _theResult___fst_exp__h580445 =
	     (_theResult___fst_exp__h579687 == 11'd2047) ?
	       _theResult___fst_exp__h579687 :
	       _theResult___fst_exp__h580442 ;
  assign _theResult___fst_exp__h589264 =
	     _theResult____h581028[56] ?
	       11'd2 :
	       _theResult___fst_exp__h589338 ;
  assign _theResult___fst_exp__h589329 =
	     11'd0 -
	     { 5'd0,
	       IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9610 } ;
  assign _theResult___fst_exp__h589335 =
	     (!_theResult____h581028[56] && !_theResult____h581028[55] &&
	      !_theResult____h581028[54] &&
	      !_theResult____h581028[53] &&
	      !_theResult____h581028[52] &&
	      !_theResult____h581028[51] &&
	      !_theResult____h581028[50] &&
	      !_theResult____h581028[49] &&
	      !_theResult____h581028[48] &&
	      !_theResult____h581028[47] &&
	      !_theResult____h581028[46] &&
	      !_theResult____h581028[45] &&
	      !_theResult____h581028[44] &&
	      !_theResult____h581028[43] &&
	      !_theResult____h581028[42] &&
	      !_theResult____h581028[41] &&
	      !_theResult____h581028[40] &&
	      !_theResult____h581028[39] &&
	      !_theResult____h581028[38] &&
	      !_theResult____h581028[37] &&
	      !_theResult____h581028[36] &&
	      !_theResult____h581028[35] &&
	      !_theResult____h581028[34] &&
	      !_theResult____h581028[33] &&
	      !_theResult____h581028[32] &&
	      !_theResult____h581028[31] &&
	      !_theResult____h581028[30] &&
	      !_theResult____h581028[29] &&
	      !_theResult____h581028[28] &&
	      !_theResult____h581028[27] &&
	      !_theResult____h581028[26] &&
	      !_theResult____h581028[25] &&
	      !_theResult____h581028[24] &&
	      !_theResult____h581028[23] &&
	      !_theResult____h581028[22] &&
	      !_theResult____h581028[21] &&
	      !_theResult____h581028[20] &&
	      !_theResult____h581028[19] &&
	      !_theResult____h581028[18] &&
	      !_theResult____h581028[17] &&
	      !_theResult____h581028[16] &&
	      !_theResult____h581028[15] &&
	      !_theResult____h581028[14] &&
	      !_theResult____h581028[13] &&
	      !_theResult____h581028[12] &&
	      !_theResult____h581028[11] &&
	      !_theResult____h581028[10] &&
	      !_theResult____h581028[9] &&
	      !_theResult____h581028[8] &&
	      !_theResult____h581028[7] &&
	      !_theResult____h581028[6] &&
	      !_theResult____h581028[5] &&
	      !_theResult____h581028[4] &&
	      !_theResult____h581028[3] &&
	      !_theResult____h581028[2] &&
	      !_theResult____h581028[1] &&
	      !_theResult____h581028[0] ||
	      !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9612) ?
	       11'd0 :
	       _theResult___fst_exp__h589329 ;
  assign _theResult___fst_exp__h589338 =
	     (!_theResult____h581028[56] && _theResult____h581028[55]) ?
	       11'd1 :
	       _theResult___fst_exp__h589335 ;
  assign _theResult___fst_exp__h590093 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q190 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 ;
  assign _theResult___fst_exp__h590096 =
	     (_theResult___fst_exp__h589264 == 11'd2047) ?
	       _theResult___fst_exp__h589264 :
	       _theResult___fst_exp__h590093 ;
  assign _theResult___fst_exp__h598049 =
	     (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] ==
	      11'd0) ?
	       11'd1 :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] ;
  assign _theResult___fst_exp__h598088 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] -
	     { 5'd0,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 } ;
  assign _theResult___fst_exp__h598094 =
	     (f3_exp__h560440 == 8'd0 && !f3_sfd__h560441[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286 ||
	      !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9662) ?
	       11'd0 :
	       _theResult___fst_exp__h598088 ;
  assign _theResult___fst_exp__h598097 =
	     (f3_exp__h560440 == 8'd0) ?
	       _theResult___fst_exp__h598094 :
	       _theResult___fst_exp__h598049 ;
  assign _theResult___fst_exp__h598877 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 ;
  assign _theResult___fst_exp__h598880 =
	     (_theResult___fst_exp__h598097 == 11'd2047) ?
	       _theResult___fst_exp__h598097 :
	       _theResult___fst_exp__h598877 ;
  assign _theResult___fst_exp__h598889 =
	     (f3_exp__h560440 == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ?
		  _theResult___snd_fst_exp__h580448 :
		  _theResult___fst_exp__h564614) :
	       (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 ?
		  _theResult___snd_fst_exp__h598883 :
		  _theResult___fst_exp__h564614) ;
  assign _theResult___fst_exp__h598892 =
	     (f3_exp__h560440 == 8'd0 && f3_sfd__h560441 == 23'd0) ?
	       11'd0 :
	       _theResult___fst_exp__h598889 ;
  assign _theResult___fst_sfd__h354796 =
	     (_theResult___fst_exp__h354198 == 8'd255) ?
	       sfdin__h354192[56:34] :
	       _theResult___fst_sfd__h354793 ;
  assign _theResult___fst_sfd__h363378 =
	     (_theResult___fst_exp__h362854 == 8'd255) ?
	       _theResult___snd__h362805[56:34] :
	       _theResult___fst_sfd__h363375 ;
  assign _theResult___fst_sfd__h372562 =
	     (_theResult___fst_exp__h371964 == 8'd255) ?
	       sfdin__h371958[56:34] :
	       _theResult___fst_sfd__h372559 ;
  assign _theResult___fst_sfd__h381198 =
	     (_theResult___fst_exp__h380649 == 8'd255) ?
	       _theResult___snd__h380595[56:34] :
	       _theResult___fst_sfd__h381195 ;
  assign _theResult___fst_sfd__h381207 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 ?
		  _theResult___snd_fst_sfd__h363381 :
		  _theResult___fst_sfd__h346070) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 ?
		  _theResult___snd_fst_sfd__h381201 :
		  _theResult___fst_sfd__h346070) ;
  assign _theResult___fst_sfd__h381213 =
	     ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	       11'd2047 ||
	       coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	       11'd0) &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
	      52'd0) ?
	       23'd0 :
	       _theResult___fst_sfd__h381207 ;
  assign _theResult___fst_sfd__h400493 =
	     (_theResult___fst_exp__h399895 == 8'd255) ?
	       sfdin__h399889[56:34] :
	       _theResult___fst_sfd__h400490 ;
  assign _theResult___fst_sfd__h409075 =
	     (_theResult___fst_exp__h408551 == 8'd255) ?
	       _theResult___snd__h408502[56:34] :
	       _theResult___fst_sfd__h409072 ;
  assign _theResult___fst_sfd__h418259 =
	     (_theResult___fst_exp__h417661 == 8'd255) ?
	       sfdin__h417655[56:34] :
	       _theResult___fst_sfd__h418256 ;
  assign _theResult___fst_sfd__h426895 =
	     (_theResult___fst_exp__h426346 == 8'd255) ?
	       _theResult___snd__h426292[56:34] :
	       _theResult___fst_sfd__h426892 ;
  assign _theResult___fst_sfd__h426904 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 ?
		  _theResult___snd_fst_sfd__h409078 :
		  _theResult___fst_sfd__h391769) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 ?
		  _theResult___snd_fst_sfd__h426898 :
		  _theResult___fst_sfd__h391769) ;
  assign _theResult___fst_sfd__h426910 =
	     ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	       11'd2047 ||
	       coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	       11'd0) &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
	      52'd0) ?
	       23'd0 :
	       _theResult___fst_sfd__h426904 ;
  assign _theResult___fst_sfd__h446188 =
	     (_theResult___fst_exp__h445590 == 8'd255) ?
	       sfdin__h445584[56:34] :
	       _theResult___fst_sfd__h446185 ;
  assign _theResult___fst_sfd__h454770 =
	     (_theResult___fst_exp__h454246 == 8'd255) ?
	       _theResult___snd__h454197[56:34] :
	       _theResult___fst_sfd__h454767 ;
  assign _theResult___fst_sfd__h463954 =
	     (_theResult___fst_exp__h463356 == 8'd255) ?
	       sfdin__h463350[56:34] :
	       _theResult___fst_sfd__h463951 ;
  assign _theResult___fst_sfd__h472590 =
	     (_theResult___fst_exp__h472041 == 8'd255) ?
	       _theResult___snd__h471987[56:34] :
	       _theResult___fst_sfd__h472587 ;
  assign _theResult___fst_sfd__h472599 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 ?
		  _theResult___snd_fst_sfd__h454773 :
		  _theResult___fst_sfd__h437464) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 ?
		  _theResult___snd_fst_sfd__h472593 :
		  _theResult___fst_sfd__h437464) ;
  assign _theResult___fst_sfd__h472605 =
	     ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	       11'd2047 ||
	       coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	       11'd0) &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
	      52'd0) ?
	       23'd0 :
	       _theResult___fst_sfd__h472599 ;
  assign _theResult___fst_sfd__h486458 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
	       52'd0 :
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 ;
  assign _theResult___fst_sfd__h502286 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 ;
  assign _theResult___fst_sfd__h502289 =
	     (_theResult___fst_exp__h501530 == 11'd2047) ?
	       _theResult___snd__h501481[56:5] :
	       _theResult___fst_sfd__h502286 ;
  assign _theResult___fst_sfd__h511937 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 ;
  assign _theResult___fst_sfd__h511940 =
	     (_theResult___fst_exp__h511107 == 11'd2047) ?
	       sfdin__h511101[56:5] :
	       _theResult___fst_sfd__h511937 ;
  assign _theResult___fst_sfd__h520721 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 ;
  assign _theResult___fst_sfd__h520724 =
	     (_theResult___fst_exp__h519940 == 11'd2047) ?
	       _theResult___snd__h519886[56:5] :
	       _theResult___fst_sfd__h520721 ;
  assign _theResult___fst_sfd__h520733 =
	     (f1_exp__h482142 == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 ?
		  _theResult___snd_fst_sfd__h502292 :
		  _theResult___fst_sfd__h486458) :
	       (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 ?
		  _theResult___snd_fst_sfd__h520727 :
		  _theResult___fst_sfd__h486458) ;
  assign _theResult___fst_sfd__h520739 =
	     ((f1_exp__h482142 == 8'd255 || f1_exp__h482142 == 8'd0) &&
	      f1_sfd__h482143 == 23'd0) ?
	       52'd0 :
	       _theResult___fst_sfd__h520733 ;
  assign _theResult___fst_sfd__h525311 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
	       52'd0 :
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 ;
  assign _theResult___fst_sfd__h541139 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q206 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 ;
  assign _theResult___fst_sfd__h541142 =
	     (_theResult___fst_exp__h540383 == 11'd2047) ?
	       _theResult___snd__h540334[56:5] :
	       _theResult___fst_sfd__h541139 ;
  assign _theResult___fst_sfd__h550790 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 ;
  assign _theResult___fst_sfd__h550793 =
	     (_theResult___fst_exp__h549960 == 11'd2047) ?
	       sfdin__h549954[56:5] :
	       _theResult___fst_sfd__h550790 ;
  assign _theResult___fst_sfd__h559574 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 ;
  assign _theResult___fst_sfd__h559577 =
	     (_theResult___fst_exp__h558793 == 11'd2047) ?
	       _theResult___snd__h558739[56:5] :
	       _theResult___fst_sfd__h559574 ;
  assign _theResult___fst_sfd__h559586 =
	     (f2_exp__h521136 == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ?
		  _theResult___snd_fst_sfd__h541145 :
		  _theResult___fst_sfd__h525311) :
	       (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 ?
		  _theResult___snd_fst_sfd__h559580 :
		  _theResult___fst_sfd__h525311) ;
  assign _theResult___fst_sfd__h559592 =
	     ((f2_exp__h521136 == 8'd255 || f2_exp__h521136 == 8'd0) &&
	      f2_sfd__h521137 == 23'd0) ?
	       52'd0 :
	       _theResult___fst_sfd__h559586 ;
  assign _theResult___fst_sfd__h564615 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
	       52'd0 :
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 ;
  assign _theResult___fst_sfd__h580443 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q222 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 ;
  assign _theResult___fst_sfd__h580446 =
	     (_theResult___fst_exp__h579687 == 11'd2047) ?
	       _theResult___snd__h579638[56:5] :
	       _theResult___fst_sfd__h580443 ;
  assign _theResult___fst_sfd__h590094 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q224 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 ;
  assign _theResult___fst_sfd__h590097 =
	     (_theResult___fst_exp__h589264 == 11'd2047) ?
	       sfdin__h589258[56:5] :
	       _theResult___fst_sfd__h590094 ;
  assign _theResult___fst_sfd__h598878 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q226 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 ;
  assign _theResult___fst_sfd__h598881 =
	     (_theResult___fst_exp__h598097 == 11'd2047) ?
	       _theResult___snd__h598043[56:5] :
	       _theResult___fst_sfd__h598878 ;
  assign _theResult___fst_sfd__h598890 =
	     (f3_exp__h560440 == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ?
		  _theResult___snd_fst_sfd__h580449 :
		  _theResult___fst_sfd__h564615) :
	       (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 ?
		  _theResult___snd_fst_sfd__h598884 :
		  _theResult___fst_sfd__h564615) ;
  assign _theResult___fst_sfd__h598896 =
	     ((f3_exp__h560440 == 8'd255 || f3_exp__h560440 == 8'd0) &&
	      f3_sfd__h560441 == 23'd0) ?
	       52'd0 :
	       _theResult___fst_sfd__h598890 ;
  assign _theResult___sfd__h354715 =
	     sfd__h354290[24] ?
	       ((_theResult___fst_exp__h354198 == 8'd254) ?
		  23'd0 :
		  sfd__h354290[23:1]) :
	       sfd__h354290[22:0] ;
  assign _theResult___sfd__h363297 =
	     sfd__h362872[24] ?
	       ((_theResult___fst_exp__h362854 == 8'd254) ?
		  23'd0 :
		  sfd__h362872[23:1]) :
	       sfd__h362872[22:0] ;
  assign _theResult___sfd__h372481 =
	     sfd__h372056[24] ?
	       ((_theResult___fst_exp__h371964 == 8'd254) ?
		  23'd0 :
		  sfd__h372056[23:1]) :
	       sfd__h372056[22:0] ;
  assign _theResult___sfd__h381117 =
	     sfd__h380668[24] ?
	       ((_theResult___fst_exp__h380649 == 8'd254) ?
		  23'd0 :
		  sfd__h380668[23:1]) :
	       sfd__h380668[22:0] ;
  assign _theResult___sfd__h381219 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd2047 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
	      52'd0) ?
	       _theResult___snd_fst_sfd__h338432 :
	       _theResult___fst_sfd__h381213 ;
  assign _theResult___sfd__h400412 =
	     sfd__h399987[24] ?
	       ((_theResult___fst_exp__h399895 == 8'd254) ?
		  23'd0 :
		  sfd__h399987[23:1]) :
	       sfd__h399987[22:0] ;
  assign _theResult___sfd__h408994 =
	     sfd__h408569[24] ?
	       ((_theResult___fst_exp__h408551 == 8'd254) ?
		  23'd0 :
		  sfd__h408569[23:1]) :
	       sfd__h408569[22:0] ;
  assign _theResult___sfd__h418178 =
	     sfd__h417753[24] ?
	       ((_theResult___fst_exp__h417661 == 8'd254) ?
		  23'd0 :
		  sfd__h417753[23:1]) :
	       sfd__h417753[22:0] ;
  assign _theResult___sfd__h426814 =
	     sfd__h426365[24] ?
	       ((_theResult___fst_exp__h426346 == 8'd254) ?
		  23'd0 :
		  sfd__h426365[23:1]) :
	       sfd__h426365[22:0] ;
  assign _theResult___sfd__h426916 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd2047 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
	      52'd0) ?
	       _theResult___snd_fst_sfd__h384134 :
	       _theResult___fst_sfd__h426910 ;
  assign _theResult___sfd__h446107 =
	     sfd__h445682[24] ?
	       ((_theResult___fst_exp__h445590 == 8'd254) ?
		  23'd0 :
		  sfd__h445682[23:1]) :
	       sfd__h445682[22:0] ;
  assign _theResult___sfd__h454689 =
	     sfd__h454264[24] ?
	       ((_theResult___fst_exp__h454246 == 8'd254) ?
		  23'd0 :
		  sfd__h454264[23:1]) :
	       sfd__h454264[22:0] ;
  assign _theResult___sfd__h463873 =
	     sfd__h463448[24] ?
	       ((_theResult___fst_exp__h463356 == 8'd254) ?
		  23'd0 :
		  sfd__h463448[23:1]) :
	       sfd__h463448[22:0] ;
  assign _theResult___sfd__h472509 =
	     sfd__h472060[24] ?
	       ((_theResult___fst_exp__h472041 == 8'd254) ?
		  23'd0 :
		  sfd__h472060[23:1]) :
	       sfd__h472060[22:0] ;
  assign _theResult___sfd__h472611 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd2047 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
	      52'd0) ?
	       _theResult___snd_fst_sfd__h429829 :
	       _theResult___fst_sfd__h472605 ;
  assign _theResult___sfd__h502186 =
	     sfd__h501548[53] ?
	       ((_theResult___fst_exp__h501530 == 11'd2046) ?
		  52'd0 :
		  sfd__h501548[52:1]) :
	       sfd__h501548[51:0] ;
  assign _theResult___sfd__h511837 =
	     sfd__h511199[53] ?
	       ((_theResult___fst_exp__h511107 == 11'd2046) ?
		  52'd0 :
		  sfd__h511199[52:1]) :
	       sfd__h511199[51:0] ;
  assign _theResult___sfd__h520621 =
	     sfd__h519959[53] ?
	       ((_theResult___fst_exp__h519940 == 11'd2046) ?
		  52'd0 :
		  sfd__h519959[52:1]) :
	       sfd__h519959[51:0] ;
  assign _theResult___sfd__h541039 =
	     sfd__h540401[53] ?
	       ((_theResult___fst_exp__h540383 == 11'd2046) ?
		  52'd0 :
		  sfd__h540401[52:1]) :
	       sfd__h540401[51:0] ;
  assign _theResult___sfd__h550690 =
	     sfd__h550052[53] ?
	       ((_theResult___fst_exp__h549960 == 11'd2046) ?
		  52'd0 :
		  sfd__h550052[52:1]) :
	       sfd__h550052[51:0] ;
  assign _theResult___sfd__h559474 =
	     sfd__h558812[53] ?
	       ((_theResult___fst_exp__h558793 == 11'd2046) ?
		  52'd0 :
		  sfd__h558812[52:1]) :
	       sfd__h558812[51:0] ;
  assign _theResult___sfd__h580343 =
	     sfd__h579705[53] ?
	       ((_theResult___fst_exp__h579687 == 11'd2046) ?
		  52'd0 :
		  sfd__h579705[52:1]) :
	       sfd__h579705[51:0] ;
  assign _theResult___sfd__h589994 =
	     sfd__h589356[53] ?
	       ((_theResult___fst_exp__h589264 == 11'd2046) ?
		  52'd0 :
		  sfd__h589356[52:1]) :
	       sfd__h589356[51:0] ;
  assign _theResult___sfd__h598778 =
	     sfd__h598116[53] ?
	       ((_theResult___fst_exp__h598097 == 11'd2046) ?
		  52'd0 :
		  sfd__h598116[52:1]) :
	       sfd__h598116[51:0] ;
  assign _theResult___snd__h354209 = { _theResult____h346087[55:0], 1'd0 } ;
  assign _theResult___snd__h354220 =
	     (!_theResult____h346087[56] && _theResult____h346087[55]) ?
	       _theResult___snd__h354222 :
	       _theResult___snd__h354232 ;
  assign _theResult___snd__h354222 = { _theResult____h346087[54:0], 2'd0 } ;
  assign _theResult___snd__h354232 =
	     (!_theResult____h346087[56] && !_theResult____h346087[55] &&
	      !_theResult____h346087[54] &&
	      !_theResult____h346087[53] &&
	      !_theResult____h346087[52] &&
	      !_theResult____h346087[51] &&
	      !_theResult____h346087[50] &&
	      !_theResult____h346087[49] &&
	      !_theResult____h346087[48] &&
	      !_theResult____h346087[47] &&
	      !_theResult____h346087[46] &&
	      !_theResult____h346087[45] &&
	      !_theResult____h346087[44] &&
	      !_theResult____h346087[43] &&
	      !_theResult____h346087[42] &&
	      !_theResult____h346087[41] &&
	      !_theResult____h346087[40] &&
	      !_theResult____h346087[39] &&
	      !_theResult____h346087[38] &&
	      !_theResult____h346087[37] &&
	      !_theResult____h346087[36] &&
	      !_theResult____h346087[35] &&
	      !_theResult____h346087[34] &&
	      !_theResult____h346087[33] &&
	      !_theResult____h346087[32] &&
	      !_theResult____h346087[31] &&
	      !_theResult____h346087[30] &&
	      !_theResult____h346087[29] &&
	      !_theResult____h346087[28] &&
	      !_theResult____h346087[27] &&
	      !_theResult____h346087[26] &&
	      !_theResult____h346087[25] &&
	      !_theResult____h346087[24] &&
	      !_theResult____h346087[23] &&
	      !_theResult____h346087[22] &&
	      !_theResult____h346087[21] &&
	      !_theResult____h346087[20] &&
	      !_theResult____h346087[19] &&
	      !_theResult____h346087[18] &&
	      !_theResult____h346087[17] &&
	      !_theResult____h346087[16] &&
	      !_theResult____h346087[15] &&
	      !_theResult____h346087[14] &&
	      !_theResult____h346087[13] &&
	      !_theResult____h346087[12] &&
	      !_theResult____h346087[11] &&
	      !_theResult____h346087[10] &&
	      !_theResult____h346087[9] &&
	      !_theResult____h346087[8] &&
	      !_theResult____h346087[7] &&
	      !_theResult____h346087[6] &&
	      !_theResult____h346087[5] &&
	      !_theResult____h346087[4] &&
	      !_theResult____h346087[3] &&
	      !_theResult____h346087[2] &&
	      !_theResult____h346087[1] &&
	      !_theResult____h346087[0]) ?
	       _theResult____h346087 :
	       _theResult___snd__h354238 ;
  assign _theResult___snd__h354238 =
	     { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28[54:0],
	       2'd0 } ;
  assign _theResult___snd__h354261 =
	     _theResult____h346087 <<
	     IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247 ;
  assign _theResult___snd__h362805 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       _theResult___snd__h362814 :
	       _theResult___snd__h362807 ;
  assign _theResult___snd__h362807 =
	     { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5],
	       5'd0 } ;
  assign _theResult___snd__h362814 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423) ?
	       sfd__h338482 :
	       _theResult___snd__h362820 ;
  assign _theResult___snd__h362820 =
	     { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q30[54:0],
	       2'd0 } ;
  assign _theResult___snd__h362843 =
	     sfd__h338482 <<
	     IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 ;
  assign _theResult___snd__h371975 = { _theResult____h363726[55:0], 1'd0 } ;
  assign _theResult___snd__h371986 =
	     (!_theResult____h363726[56] && _theResult____h363726[55]) ?
	       _theResult___snd__h371988 :
	       _theResult___snd__h371998 ;
  assign _theResult___snd__h371988 = { _theResult____h363726[54:0], 2'd0 } ;
  assign _theResult___snd__h371998 =
	     (!_theResult____h363726[56] && !_theResult____h363726[55] &&
	      !_theResult____h363726[54] &&
	      !_theResult____h363726[53] &&
	      !_theResult____h363726[52] &&
	      !_theResult____h363726[51] &&
	      !_theResult____h363726[50] &&
	      !_theResult____h363726[49] &&
	      !_theResult____h363726[48] &&
	      !_theResult____h363726[47] &&
	      !_theResult____h363726[46] &&
	      !_theResult____h363726[45] &&
	      !_theResult____h363726[44] &&
	      !_theResult____h363726[43] &&
	      !_theResult____h363726[42] &&
	      !_theResult____h363726[41] &&
	      !_theResult____h363726[40] &&
	      !_theResult____h363726[39] &&
	      !_theResult____h363726[38] &&
	      !_theResult____h363726[37] &&
	      !_theResult____h363726[36] &&
	      !_theResult____h363726[35] &&
	      !_theResult____h363726[34] &&
	      !_theResult____h363726[33] &&
	      !_theResult____h363726[32] &&
	      !_theResult____h363726[31] &&
	      !_theResult____h363726[30] &&
	      !_theResult____h363726[29] &&
	      !_theResult____h363726[28] &&
	      !_theResult____h363726[27] &&
	      !_theResult____h363726[26] &&
	      !_theResult____h363726[25] &&
	      !_theResult____h363726[24] &&
	      !_theResult____h363726[23] &&
	      !_theResult____h363726[22] &&
	      !_theResult____h363726[21] &&
	      !_theResult____h363726[20] &&
	      !_theResult____h363726[19] &&
	      !_theResult____h363726[18] &&
	      !_theResult____h363726[17] &&
	      !_theResult____h363726[16] &&
	      !_theResult____h363726[15] &&
	      !_theResult____h363726[14] &&
	      !_theResult____h363726[13] &&
	      !_theResult____h363726[12] &&
	      !_theResult____h363726[11] &&
	      !_theResult____h363726[10] &&
	      !_theResult____h363726[9] &&
	      !_theResult____h363726[8] &&
	      !_theResult____h363726[7] &&
	      !_theResult____h363726[6] &&
	      !_theResult____h363726[5] &&
	      !_theResult____h363726[4] &&
	      !_theResult____h363726[3] &&
	      !_theResult____h363726[2] &&
	      !_theResult____h363726[1] &&
	      !_theResult____h363726[0]) ?
	       _theResult____h363726 :
	       _theResult___snd__h372004 ;
  assign _theResult___snd__h372004 =
	     { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q38[54:0],
	       2'd0 } ;
  assign _theResult___snd__h372027 =
	     _theResult____h363726 <<
	     IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4798 ;
  assign _theResult___snd__h380595 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       _theResult___snd__h380609 :
	       _theResult___snd__h362807 ;
  assign _theResult___snd__h380609 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423) ?
	       sfd__h338482 :
	       _theResult___snd__h380615 ;
  assign _theResult___snd__h380615 =
	     { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43[54:0],
	       2'd0 } ;
  assign _theResult___snd__h380633 =
	     sfd__h338482 <<
	     (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4872[8] ?
		9'h0AA :
		IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4872) ;
  assign _theResult___snd__h399906 = { _theResult____h391786[55:0], 1'd0 } ;
  assign _theResult___snd__h399917 =
	     (!_theResult____h391786[56] && _theResult____h391786[55]) ?
	       _theResult___snd__h399919 :
	       _theResult___snd__h399929 ;
  assign _theResult___snd__h399919 = { _theResult____h391786[54:0], 2'd0 } ;
  assign _theResult___snd__h399929 =
	     (!_theResult____h391786[56] && !_theResult____h391786[55] &&
	      !_theResult____h391786[54] &&
	      !_theResult____h391786[53] &&
	      !_theResult____h391786[52] &&
	      !_theResult____h391786[51] &&
	      !_theResult____h391786[50] &&
	      !_theResult____h391786[49] &&
	      !_theResult____h391786[48] &&
	      !_theResult____h391786[47] &&
	      !_theResult____h391786[46] &&
	      !_theResult____h391786[45] &&
	      !_theResult____h391786[44] &&
	      !_theResult____h391786[43] &&
	      !_theResult____h391786[42] &&
	      !_theResult____h391786[41] &&
	      !_theResult____h391786[40] &&
	      !_theResult____h391786[39] &&
	      !_theResult____h391786[38] &&
	      !_theResult____h391786[37] &&
	      !_theResult____h391786[36] &&
	      !_theResult____h391786[35] &&
	      !_theResult____h391786[34] &&
	      !_theResult____h391786[33] &&
	      !_theResult____h391786[32] &&
	      !_theResult____h391786[31] &&
	      !_theResult____h391786[30] &&
	      !_theResult____h391786[29] &&
	      !_theResult____h391786[28] &&
	      !_theResult____h391786[27] &&
	      !_theResult____h391786[26] &&
	      !_theResult____h391786[25] &&
	      !_theResult____h391786[24] &&
	      !_theResult____h391786[23] &&
	      !_theResult____h391786[22] &&
	      !_theResult____h391786[21] &&
	      !_theResult____h391786[20] &&
	      !_theResult____h391786[19] &&
	      !_theResult____h391786[18] &&
	      !_theResult____h391786[17] &&
	      !_theResult____h391786[16] &&
	      !_theResult____h391786[15] &&
	      !_theResult____h391786[14] &&
	      !_theResult____h391786[13] &&
	      !_theResult____h391786[12] &&
	      !_theResult____h391786[11] &&
	      !_theResult____h391786[10] &&
	      !_theResult____h391786[9] &&
	      !_theResult____h391786[8] &&
	      !_theResult____h391786[7] &&
	      !_theResult____h391786[6] &&
	      !_theResult____h391786[5] &&
	      !_theResult____h391786[4] &&
	      !_theResult____h391786[3] &&
	      !_theResult____h391786[2] &&
	      !_theResult____h391786[1] &&
	      !_theResult____h391786[0]) ?
	       _theResult____h391786 :
	       _theResult___snd__h399935 ;
  assign _theResult___snd__h399935 =
	     { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63[54:0],
	       2'd0 } ;
  assign _theResult___snd__h399958 =
	     _theResult____h391786 <<
	     IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 ;
  assign _theResult___snd__h408502 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       _theResult___snd__h408511 :
	       _theResult___snd__h408504 ;
  assign _theResult___snd__h408504 =
	     { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5],
	       5'd0 } ;
  assign _theResult___snd__h408511 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815) ?
	       sfd__h384184 :
	       _theResult___snd__h408517 ;
  assign _theResult___snd__h408517 =
	     { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q65[54:0],
	       2'd0 } ;
  assign _theResult___snd__h408540 =
	     sfd__h384184 <<
	     IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 ;
  assign _theResult___snd__h417672 = { _theResult____h409423[55:0], 1'd0 } ;
  assign _theResult___snd__h417683 =
	     (!_theResult____h409423[56] && _theResult____h409423[55]) ?
	       _theResult___snd__h417685 :
	       _theResult___snd__h417695 ;
  assign _theResult___snd__h417685 = { _theResult____h409423[54:0], 2'd0 } ;
  assign _theResult___snd__h417695 =
	     (!_theResult____h409423[56] && !_theResult____h409423[55] &&
	      !_theResult____h409423[54] &&
	      !_theResult____h409423[53] &&
	      !_theResult____h409423[52] &&
	      !_theResult____h409423[51] &&
	      !_theResult____h409423[50] &&
	      !_theResult____h409423[49] &&
	      !_theResult____h409423[48] &&
	      !_theResult____h409423[47] &&
	      !_theResult____h409423[46] &&
	      !_theResult____h409423[45] &&
	      !_theResult____h409423[44] &&
	      !_theResult____h409423[43] &&
	      !_theResult____h409423[42] &&
	      !_theResult____h409423[41] &&
	      !_theResult____h409423[40] &&
	      !_theResult____h409423[39] &&
	      !_theResult____h409423[38] &&
	      !_theResult____h409423[37] &&
	      !_theResult____h409423[36] &&
	      !_theResult____h409423[35] &&
	      !_theResult____h409423[34] &&
	      !_theResult____h409423[33] &&
	      !_theResult____h409423[32] &&
	      !_theResult____h409423[31] &&
	      !_theResult____h409423[30] &&
	      !_theResult____h409423[29] &&
	      !_theResult____h409423[28] &&
	      !_theResult____h409423[27] &&
	      !_theResult____h409423[26] &&
	      !_theResult____h409423[25] &&
	      !_theResult____h409423[24] &&
	      !_theResult____h409423[23] &&
	      !_theResult____h409423[22] &&
	      !_theResult____h409423[21] &&
	      !_theResult____h409423[20] &&
	      !_theResult____h409423[19] &&
	      !_theResult____h409423[18] &&
	      !_theResult____h409423[17] &&
	      !_theResult____h409423[16] &&
	      !_theResult____h409423[15] &&
	      !_theResult____h409423[14] &&
	      !_theResult____h409423[13] &&
	      !_theResult____h409423[12] &&
	      !_theResult____h409423[11] &&
	      !_theResult____h409423[10] &&
	      !_theResult____h409423[9] &&
	      !_theResult____h409423[8] &&
	      !_theResult____h409423[7] &&
	      !_theResult____h409423[6] &&
	      !_theResult____h409423[5] &&
	      !_theResult____h409423[4] &&
	      !_theResult____h409423[3] &&
	      !_theResult____h409423[2] &&
	      !_theResult____h409423[1] &&
	      !_theResult____h409423[0]) ?
	       _theResult____h409423 :
	       _theResult___snd__h417701 ;
  assign _theResult___snd__h417701 =
	     { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q73[54:0],
	       2'd0 } ;
  assign _theResult___snd__h417724 =
	     _theResult____h409423 <<
	     IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 ;
  assign _theResult___snd__h426292 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       _theResult___snd__h426306 :
	       _theResult___snd__h408504 ;
  assign _theResult___snd__h426306 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815) ?
	       sfd__h384184 :
	       _theResult___snd__h426312 ;
  assign _theResult___snd__h426312 =
	     { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78[54:0],
	       2'd0 } ;
  assign _theResult___snd__h426330 =
	     sfd__h384184 <<
	     (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264[8] ?
		9'h0AA :
		IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264) ;
  assign _theResult___snd__h445601 = { _theResult____h437481[55:0], 1'd0 } ;
  assign _theResult___snd__h445612 =
	     (!_theResult____h437481[56] && _theResult____h437481[55]) ?
	       _theResult___snd__h445614 :
	       _theResult___snd__h445624 ;
  assign _theResult___snd__h445614 = { _theResult____h437481[54:0], 2'd0 } ;
  assign _theResult___snd__h445624 =
	     (!_theResult____h437481[56] && !_theResult____h437481[55] &&
	      !_theResult____h437481[54] &&
	      !_theResult____h437481[53] &&
	      !_theResult____h437481[52] &&
	      !_theResult____h437481[51] &&
	      !_theResult____h437481[50] &&
	      !_theResult____h437481[49] &&
	      !_theResult____h437481[48] &&
	      !_theResult____h437481[47] &&
	      !_theResult____h437481[46] &&
	      !_theResult____h437481[45] &&
	      !_theResult____h437481[44] &&
	      !_theResult____h437481[43] &&
	      !_theResult____h437481[42] &&
	      !_theResult____h437481[41] &&
	      !_theResult____h437481[40] &&
	      !_theResult____h437481[39] &&
	      !_theResult____h437481[38] &&
	      !_theResult____h437481[37] &&
	      !_theResult____h437481[36] &&
	      !_theResult____h437481[35] &&
	      !_theResult____h437481[34] &&
	      !_theResult____h437481[33] &&
	      !_theResult____h437481[32] &&
	      !_theResult____h437481[31] &&
	      !_theResult____h437481[30] &&
	      !_theResult____h437481[29] &&
	      !_theResult____h437481[28] &&
	      !_theResult____h437481[27] &&
	      !_theResult____h437481[26] &&
	      !_theResult____h437481[25] &&
	      !_theResult____h437481[24] &&
	      !_theResult____h437481[23] &&
	      !_theResult____h437481[22] &&
	      !_theResult____h437481[21] &&
	      !_theResult____h437481[20] &&
	      !_theResult____h437481[19] &&
	      !_theResult____h437481[18] &&
	      !_theResult____h437481[17] &&
	      !_theResult____h437481[16] &&
	      !_theResult____h437481[15] &&
	      !_theResult____h437481[14] &&
	      !_theResult____h437481[13] &&
	      !_theResult____h437481[12] &&
	      !_theResult____h437481[11] &&
	      !_theResult____h437481[10] &&
	      !_theResult____h437481[9] &&
	      !_theResult____h437481[8] &&
	      !_theResult____h437481[7] &&
	      !_theResult____h437481[6] &&
	      !_theResult____h437481[5] &&
	      !_theResult____h437481[4] &&
	      !_theResult____h437481[3] &&
	      !_theResult____h437481[2] &&
	      !_theResult____h437481[1] &&
	      !_theResult____h437481[0]) ?
	       _theResult____h437481 :
	       _theResult___snd__h445630 ;
  assign _theResult___snd__h445630 =
	     { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98[54:0],
	       2'd0 } ;
  assign _theResult___snd__h445653 =
	     _theResult____h437481 <<
	     IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 ;
  assign _theResult___snd__h454197 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       _theResult___snd__h454206 :
	       _theResult___snd__h454199 ;
  assign _theResult___snd__h454199 =
	     { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5],
	       5'd0 } ;
  assign _theResult___snd__h454206 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207) ?
	       sfd__h429879 :
	       _theResult___snd__h454212 ;
  assign _theResult___snd__h454212 =
	     { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q100[54:0],
	       2'd0 } ;
  assign _theResult___snd__h454235 =
	     sfd__h429879 <<
	     IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 ;
  assign _theResult___snd__h463367 = { _theResult____h455118[55:0], 1'd0 } ;
  assign _theResult___snd__h463378 =
	     (!_theResult____h455118[56] && _theResult____h455118[55]) ?
	       _theResult___snd__h463380 :
	       _theResult___snd__h463390 ;
  assign _theResult___snd__h463380 = { _theResult____h455118[54:0], 2'd0 } ;
  assign _theResult___snd__h463390 =
	     (!_theResult____h455118[56] && !_theResult____h455118[55] &&
	      !_theResult____h455118[54] &&
	      !_theResult____h455118[53] &&
	      !_theResult____h455118[52] &&
	      !_theResult____h455118[51] &&
	      !_theResult____h455118[50] &&
	      !_theResult____h455118[49] &&
	      !_theResult____h455118[48] &&
	      !_theResult____h455118[47] &&
	      !_theResult____h455118[46] &&
	      !_theResult____h455118[45] &&
	      !_theResult____h455118[44] &&
	      !_theResult____h455118[43] &&
	      !_theResult____h455118[42] &&
	      !_theResult____h455118[41] &&
	      !_theResult____h455118[40] &&
	      !_theResult____h455118[39] &&
	      !_theResult____h455118[38] &&
	      !_theResult____h455118[37] &&
	      !_theResult____h455118[36] &&
	      !_theResult____h455118[35] &&
	      !_theResult____h455118[34] &&
	      !_theResult____h455118[33] &&
	      !_theResult____h455118[32] &&
	      !_theResult____h455118[31] &&
	      !_theResult____h455118[30] &&
	      !_theResult____h455118[29] &&
	      !_theResult____h455118[28] &&
	      !_theResult____h455118[27] &&
	      !_theResult____h455118[26] &&
	      !_theResult____h455118[25] &&
	      !_theResult____h455118[24] &&
	      !_theResult____h455118[23] &&
	      !_theResult____h455118[22] &&
	      !_theResult____h455118[21] &&
	      !_theResult____h455118[20] &&
	      !_theResult____h455118[19] &&
	      !_theResult____h455118[18] &&
	      !_theResult____h455118[17] &&
	      !_theResult____h455118[16] &&
	      !_theResult____h455118[15] &&
	      !_theResult____h455118[14] &&
	      !_theResult____h455118[13] &&
	      !_theResult____h455118[12] &&
	      !_theResult____h455118[11] &&
	      !_theResult____h455118[10] &&
	      !_theResult____h455118[9] &&
	      !_theResult____h455118[8] &&
	      !_theResult____h455118[7] &&
	      !_theResult____h455118[6] &&
	      !_theResult____h455118[5] &&
	      !_theResult____h455118[4] &&
	      !_theResult____h455118[3] &&
	      !_theResult____h455118[2] &&
	      !_theResult____h455118[1] &&
	      !_theResult____h455118[0]) ?
	       _theResult____h455118 :
	       _theResult___snd__h463396 ;
  assign _theResult___snd__h463396 =
	     { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q108[54:0],
	       2'd0 } ;
  assign _theResult___snd__h463419 =
	     _theResult____h455118 <<
	     IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 ;
  assign _theResult___snd__h471987 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       _theResult___snd__h472001 :
	       _theResult___snd__h454199 ;
  assign _theResult___snd__h472001 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207) ?
	       sfd__h429879 :
	       _theResult___snd__h472007 ;
  assign _theResult___snd__h472007 =
	     { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113[54:0],
	       2'd0 } ;
  assign _theResult___snd__h472025 =
	     sfd__h429879 <<
	     (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656[8] ?
		9'h0AA :
		IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656) ;
  assign _theResult___snd__h501481 =
	     (f1_exp__h482142 == 8'd0) ?
	       _theResult___snd__h501490 :
	       _theResult___snd__h501483 ;
  assign _theResult___snd__h501483 = { f1_sfd__h482143, 34'd0 } ;
  assign _theResult___snd__h501490 =
	     (f1_exp__h482142 == 8'd0 && !f1_sfd__h482143[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556) ?
	       sfd__h482504 :
	       _theResult___snd__h501496 ;
  assign _theResult___snd__h501496 =
	     { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134[54:0],
	       2'd0 } ;
  assign _theResult___snd__h501519 =
	     sfd__h482504 <<
	     IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 ;
  assign _theResult___snd__h511118 = { _theResult____h502871[55:0], 1'd0 } ;
  assign _theResult___snd__h511129 =
	     (!_theResult____h502871[56] && _theResult____h502871[55]) ?
	       _theResult___snd__h511131 :
	       _theResult___snd__h511141 ;
  assign _theResult___snd__h511131 = { _theResult____h502871[54:0], 2'd0 } ;
  assign _theResult___snd__h511141 =
	     (!_theResult____h502871[56] && !_theResult____h502871[55] &&
	      !_theResult____h502871[54] &&
	      !_theResult____h502871[53] &&
	      !_theResult____h502871[52] &&
	      !_theResult____h502871[51] &&
	      !_theResult____h502871[50] &&
	      !_theResult____h502871[49] &&
	      !_theResult____h502871[48] &&
	      !_theResult____h502871[47] &&
	      !_theResult____h502871[46] &&
	      !_theResult____h502871[45] &&
	      !_theResult____h502871[44] &&
	      !_theResult____h502871[43] &&
	      !_theResult____h502871[42] &&
	      !_theResult____h502871[41] &&
	      !_theResult____h502871[40] &&
	      !_theResult____h502871[39] &&
	      !_theResult____h502871[38] &&
	      !_theResult____h502871[37] &&
	      !_theResult____h502871[36] &&
	      !_theResult____h502871[35] &&
	      !_theResult____h502871[34] &&
	      !_theResult____h502871[33] &&
	      !_theResult____h502871[32] &&
	      !_theResult____h502871[31] &&
	      !_theResult____h502871[30] &&
	      !_theResult____h502871[29] &&
	      !_theResult____h502871[28] &&
	      !_theResult____h502871[27] &&
	      !_theResult____h502871[26] &&
	      !_theResult____h502871[25] &&
	      !_theResult____h502871[24] &&
	      !_theResult____h502871[23] &&
	      !_theResult____h502871[22] &&
	      !_theResult____h502871[21] &&
	      !_theResult____h502871[20] &&
	      !_theResult____h502871[19] &&
	      !_theResult____h502871[18] &&
	      !_theResult____h502871[17] &&
	      !_theResult____h502871[16] &&
	      !_theResult____h502871[15] &&
	      !_theResult____h502871[14] &&
	      !_theResult____h502871[13] &&
	      !_theResult____h502871[12] &&
	      !_theResult____h502871[11] &&
	      !_theResult____h502871[10] &&
	      !_theResult____h502871[9] &&
	      !_theResult____h502871[8] &&
	      !_theResult____h502871[7] &&
	      !_theResult____h502871[6] &&
	      !_theResult____h502871[5] &&
	      !_theResult____h502871[4] &&
	      !_theResult____h502871[3] &&
	      !_theResult____h502871[2] &&
	      !_theResult____h502871[1] &&
	      !_theResult____h502871[0]) ?
	       _theResult____h502871 :
	       _theResult___snd__h511147 ;
  assign _theResult___snd__h511147 =
	     { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138[54:0],
	       2'd0 } ;
  assign _theResult___snd__h511170 =
	     _theResult____h502871 <<
	     IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 ;
  assign _theResult___snd__h519886 =
	     (f1_exp__h482142 == 8'd0) ?
	       _theResult___snd__h519900 :
	       _theResult___snd__h501483 ;
  assign _theResult___snd__h519900 =
	     (f1_exp__h482142 == 8'd0 && !f1_sfd__h482143[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556) ?
	       sfd__h482504 :
	       _theResult___snd__h519906 ;
  assign _theResult___snd__h519906 =
	     { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141[54:0],
	       2'd0 } ;
  assign _theResult___snd__h519924 =
	     sfd__h482504 <<
	     IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8946 ;
  assign _theResult___snd__h540334 =
	     (f2_exp__h521136 == 8'd0) ?
	       _theResult___snd__h540343 :
	       _theResult___snd__h540336 ;
  assign _theResult___snd__h540336 = { f2_sfd__h521137, 34'd0 } ;
  assign _theResult___snd__h540343 =
	     (f2_exp__h521136 == 8'd0 && !f2_sfd__h521137[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056) ?
	       sfd__h521498 :
	       _theResult___snd__h540349 ;
  assign _theResult___snd__h540349 =
	     { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174[54:0],
	       2'd0 } ;
  assign _theResult___snd__h540372 =
	     sfd__h521498 <<
	     IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 ;
  assign _theResult___snd__h549971 = { _theResult____h541724[55:0], 1'd0 } ;
  assign _theResult___snd__h549982 =
	     (!_theResult____h541724[56] && _theResult____h541724[55]) ?
	       _theResult___snd__h549984 :
	       _theResult___snd__h549994 ;
  assign _theResult___snd__h549984 = { _theResult____h541724[54:0], 2'd0 } ;
  assign _theResult___snd__h549994 =
	     (!_theResult____h541724[56] && !_theResult____h541724[55] &&
	      !_theResult____h541724[54] &&
	      !_theResult____h541724[53] &&
	      !_theResult____h541724[52] &&
	      !_theResult____h541724[51] &&
	      !_theResult____h541724[50] &&
	      !_theResult____h541724[49] &&
	      !_theResult____h541724[48] &&
	      !_theResult____h541724[47] &&
	      !_theResult____h541724[46] &&
	      !_theResult____h541724[45] &&
	      !_theResult____h541724[44] &&
	      !_theResult____h541724[43] &&
	      !_theResult____h541724[42] &&
	      !_theResult____h541724[41] &&
	      !_theResult____h541724[40] &&
	      !_theResult____h541724[39] &&
	      !_theResult____h541724[38] &&
	      !_theResult____h541724[37] &&
	      !_theResult____h541724[36] &&
	      !_theResult____h541724[35] &&
	      !_theResult____h541724[34] &&
	      !_theResult____h541724[33] &&
	      !_theResult____h541724[32] &&
	      !_theResult____h541724[31] &&
	      !_theResult____h541724[30] &&
	      !_theResult____h541724[29] &&
	      !_theResult____h541724[28] &&
	      !_theResult____h541724[27] &&
	      !_theResult____h541724[26] &&
	      !_theResult____h541724[25] &&
	      !_theResult____h541724[24] &&
	      !_theResult____h541724[23] &&
	      !_theResult____h541724[22] &&
	      !_theResult____h541724[21] &&
	      !_theResult____h541724[20] &&
	      !_theResult____h541724[19] &&
	      !_theResult____h541724[18] &&
	      !_theResult____h541724[17] &&
	      !_theResult____h541724[16] &&
	      !_theResult____h541724[15] &&
	      !_theResult____h541724[14] &&
	      !_theResult____h541724[13] &&
	      !_theResult____h541724[12] &&
	      !_theResult____h541724[11] &&
	      !_theResult____h541724[10] &&
	      !_theResult____h541724[9] &&
	      !_theResult____h541724[8] &&
	      !_theResult____h541724[7] &&
	      !_theResult____h541724[6] &&
	      !_theResult____h541724[5] &&
	      !_theResult____h541724[4] &&
	      !_theResult____h541724[3] &&
	      !_theResult____h541724[2] &&
	      !_theResult____h541724[1] &&
	      !_theResult____h541724[0]) ?
	       _theResult____h541724 :
	       _theResult___snd__h550000 ;
  assign _theResult___snd__h550000 =
	     { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178[54:0],
	       2'd0 } ;
  assign _theResult___snd__h550023 =
	     _theResult____h541724 <<
	     IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 ;
  assign _theResult___snd__h558739 =
	     (f2_exp__h521136 == 8'd0) ?
	       _theResult___snd__h558753 :
	       _theResult___snd__h540336 ;
  assign _theResult___snd__h558753 =
	     (f2_exp__h521136 == 8'd0 && !f2_sfd__h521137[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056) ?
	       sfd__h521498 :
	       _theResult___snd__h558759 ;
  assign _theResult___snd__h558759 =
	     { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181[54:0],
	       2'd0 } ;
  assign _theResult___snd__h558777 =
	     sfd__h521498 <<
	     IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10431 ;
  assign _theResult___snd__h579638 =
	     (f3_exp__h560440 == 8'd0) ?
	       _theResult___snd__h579647 :
	       _theResult___snd__h579640 ;
  assign _theResult___snd__h579640 = { f3_sfd__h560441, 34'd0 } ;
  assign _theResult___snd__h579647 =
	     (f3_exp__h560440 == 8'd0 && !f3_sfd__h560441[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286) ?
	       sfd__h560802 :
	       _theResult___snd__h579653 ;
  assign _theResult___snd__h579653 =
	     { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151[54:0],
	       2'd0 } ;
  assign _theResult___snd__h579676 =
	     sfd__h560802 <<
	     IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 ;
  assign _theResult___snd__h589275 = { _theResult____h581028[55:0], 1'd0 } ;
  assign _theResult___snd__h589286 =
	     (!_theResult____h581028[56] && _theResult____h581028[55]) ?
	       _theResult___snd__h589288 :
	       _theResult___snd__h589298 ;
  assign _theResult___snd__h589288 = { _theResult____h581028[54:0], 2'd0 } ;
  assign _theResult___snd__h589298 =
	     (!_theResult____h581028[56] && !_theResult____h581028[55] &&
	      !_theResult____h581028[54] &&
	      !_theResult____h581028[53] &&
	      !_theResult____h581028[52] &&
	      !_theResult____h581028[51] &&
	      !_theResult____h581028[50] &&
	      !_theResult____h581028[49] &&
	      !_theResult____h581028[48] &&
	      !_theResult____h581028[47] &&
	      !_theResult____h581028[46] &&
	      !_theResult____h581028[45] &&
	      !_theResult____h581028[44] &&
	      !_theResult____h581028[43] &&
	      !_theResult____h581028[42] &&
	      !_theResult____h581028[41] &&
	      !_theResult____h581028[40] &&
	      !_theResult____h581028[39] &&
	      !_theResult____h581028[38] &&
	      !_theResult____h581028[37] &&
	      !_theResult____h581028[36] &&
	      !_theResult____h581028[35] &&
	      !_theResult____h581028[34] &&
	      !_theResult____h581028[33] &&
	      !_theResult____h581028[32] &&
	      !_theResult____h581028[31] &&
	      !_theResult____h581028[30] &&
	      !_theResult____h581028[29] &&
	      !_theResult____h581028[28] &&
	      !_theResult____h581028[27] &&
	      !_theResult____h581028[26] &&
	      !_theResult____h581028[25] &&
	      !_theResult____h581028[24] &&
	      !_theResult____h581028[23] &&
	      !_theResult____h581028[22] &&
	      !_theResult____h581028[21] &&
	      !_theResult____h581028[20] &&
	      !_theResult____h581028[19] &&
	      !_theResult____h581028[18] &&
	      !_theResult____h581028[17] &&
	      !_theResult____h581028[16] &&
	      !_theResult____h581028[15] &&
	      !_theResult____h581028[14] &&
	      !_theResult____h581028[13] &&
	      !_theResult____h581028[12] &&
	      !_theResult____h581028[11] &&
	      !_theResult____h581028[10] &&
	      !_theResult____h581028[9] &&
	      !_theResult____h581028[8] &&
	      !_theResult____h581028[7] &&
	      !_theResult____h581028[6] &&
	      !_theResult____h581028[5] &&
	      !_theResult____h581028[4] &&
	      !_theResult____h581028[3] &&
	      !_theResult____h581028[2] &&
	      !_theResult____h581028[1] &&
	      !_theResult____h581028[0]) ?
	       _theResult____h581028 :
	       _theResult___snd__h589304 ;
  assign _theResult___snd__h589304 =
	     { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155[54:0],
	       2'd0 } ;
  assign _theResult___snd__h589327 =
	     _theResult____h581028 <<
	     IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9610 ;
  assign _theResult___snd__h598043 =
	     (f3_exp__h560440 == 8'd0) ?
	       _theResult___snd__h598057 :
	       _theResult___snd__h579640 ;
  assign _theResult___snd__h598057 =
	     (f3_exp__h560440 == 8'd0 && !f3_sfd__h560441[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286) ?
	       sfd__h560802 :
	       _theResult___snd__h598063 ;
  assign _theResult___snd__h598063 =
	     { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158[54:0],
	       2'd0 } ;
  assign _theResult___snd__h598081 =
	     sfd__h560802 <<
	     IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9661 ;
  assign _theResult___snd__h603373 =
	     b__h602951[63] ? b___1__h603422 : b__h602951 ;
  assign _theResult___snd_fst_exp__h363380 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ?
	       _theResult___fst_exp__h354795 :
	       _theResult___fst_exp__h363377 ;
  assign _theResult___snd_fst_exp__h381200 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ?
	       _theResult___fst_exp__h372561 :
	       _theResult___fst_exp__h381197 ;
  assign _theResult___snd_fst_exp__h409077 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ?
	       _theResult___fst_exp__h400492 :
	       _theResult___fst_exp__h409074 ;
  assign _theResult___snd_fst_exp__h426897 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ?
	       _theResult___fst_exp__h418258 :
	       _theResult___fst_exp__h426894 ;
  assign _theResult___snd_fst_exp__h454772 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ?
	       _theResult___fst_exp__h446187 :
	       _theResult___fst_exp__h454769 ;
  assign _theResult___snd_fst_exp__h472592 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ?
	       _theResult___fst_exp__h463953 :
	       _theResult___fst_exp__h472589 ;
  assign _theResult___snd_fst_exp__h502291 =
	     _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 ?
	       11'd0 :
	       _theResult___fst_exp__h502288 ;
  assign _theResult___snd_fst_exp__h520726 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ?
	       _theResult___fst_exp__h511939 :
	       _theResult___fst_exp__h520723 ;
  assign _theResult___snd_fst_exp__h541144 =
	     _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 ?
	       11'd0 :
	       _theResult___fst_exp__h541141 ;
  assign _theResult___snd_fst_exp__h559579 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ?
	       _theResult___fst_exp__h550792 :
	       _theResult___fst_exp__h559576 ;
  assign _theResult___snd_fst_exp__h580448 =
	     _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 ?
	       11'd0 :
	       _theResult___fst_exp__h580445 ;
  assign _theResult___snd_fst_exp__h598883 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ?
	       _theResult___fst_exp__h590096 :
	       _theResult___fst_exp__h598880 ;
  assign _theResult___snd_fst_sfd__h338432 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ==
	      23'd0) ?
	       23'd2097152 :
	       coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ;
  assign _theResult___snd_fst_sfd__h363381 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ?
	       _theResult___fst_sfd__h354796 :
	       _theResult___fst_sfd__h363378 ;
  assign _theResult___snd_fst_sfd__h381201 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ?
	       _theResult___fst_sfd__h372562 :
	       _theResult___fst_sfd__h381198 ;
  assign _theResult___snd_fst_sfd__h384134 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ==
	      23'd0) ?
	       23'd2097152 :
	       coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ;
  assign _theResult___snd_fst_sfd__h409078 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ?
	       _theResult___fst_sfd__h400493 :
	       _theResult___fst_sfd__h409075 ;
  assign _theResult___snd_fst_sfd__h426898 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ?
	       _theResult___fst_sfd__h418259 :
	       _theResult___fst_sfd__h426895 ;
  assign _theResult___snd_fst_sfd__h429829 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ==
	      23'd0) ?
	       23'd2097152 :
	       coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ;
  assign _theResult___snd_fst_sfd__h454773 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ?
	       _theResult___fst_sfd__h446188 :
	       _theResult___fst_sfd__h454770 ;
  assign _theResult___snd_fst_sfd__h472593 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ?
	       _theResult___fst_sfd__h463954 :
	       _theResult___fst_sfd__h472590 ;
  assign _theResult___snd_fst_sfd__h482458 =
	     (f1_sfd__h482143 == 23'd0) ?
	       52'h4000000000000 :
	       out___1_sfd__h482206 ;
  assign _theResult___snd_fst_sfd__h502292 =
	     _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 ?
	       52'd0 :
	       _theResult___fst_sfd__h502289 ;
  assign _theResult___snd_fst_sfd__h520727 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ?
	       _theResult___fst_sfd__h511940 :
	       _theResult___fst_sfd__h520724 ;
  assign _theResult___snd_fst_sfd__h521452 =
	     (f2_sfd__h521137 == 23'd0) ?
	       52'h4000000000000 :
	       out___1_sfd__h521200 ;
  assign _theResult___snd_fst_sfd__h541145 =
	     _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 ?
	       52'd0 :
	       _theResult___fst_sfd__h541142 ;
  assign _theResult___snd_fst_sfd__h559580 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ?
	       _theResult___fst_sfd__h550793 :
	       _theResult___fst_sfd__h559577 ;
  assign _theResult___snd_fst_sfd__h560756 =
	     (f3_sfd__h560441 == 23'd0) ?
	       52'h4000000000000 :
	       out___1_sfd__h560504 ;
  assign _theResult___snd_fst_sfd__h580449 =
	     _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 ?
	       52'd0 :
	       _theResult___fst_sfd__h580446 ;
  assign _theResult___snd_fst_sfd__h598884 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ?
	       _theResult___fst_sfd__h590097 :
	       _theResult___fst_sfd__h598881 ;
  assign a___1__h603091 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ?
	       { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } :
	       { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11[31]}},
		 coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11 } ;
  assign a___1__h603377 = 64'd0 - a__h602950 ;
  assign a__h602950 =
	     coreFix_fpuMulDivExe_0_regToExeQ$first[227] ?
	       a___1__h603091 :
	       coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ;
  assign b___1__h603092 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ?
	       { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12[31]}},
		 coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12 } :
	       { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ;
  assign b___1__h603422 = 64'd0 - b__h602951 ;
  assign b__h602951 =
	     coreFix_fpuMulDivExe_0_regToExeQ$first[227] ?
	       b___1__h603092 :
	       coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ;
  assign base__h713412 = { csrf_stvec_base_hi_reg, 2'b0 } ;
  assign base__h713432 = { csrf_mtvec_base_hi_reg, 2'b0 } ;
  assign cause_code__h710452 =
	     commitStage_commitTrap[36] ? i__h710627 : i__h710467 ;
  assign commitStage_commitTrap_4362_BIT_36_4604_AND_co_ETC___d14669 =
	     commitStage_commitTrap[36] &&
	     commitStage_commitTrap[35:32] != 4'd0 &&
	     commitStage_commitTrap[35:32] != 4'd1 &&
	     commitStage_commitTrap[35:32] != 4'd3 &&
	     commitStage_commitTrap[35:32] != 4'd4 &&
	     commitStage_commitTrap[35:32] != 4'd5 &&
	     commitStage_commitTrap[35:32] != 4'd7 &&
	     commitStage_commitTrap[35:32] != 4'd8 &&
	     commitStage_commitTrap[35:32] != 4'd9 &&
	     commitStage_commitTrap[35:32] != 4'd11 ||
	     !commitStage_commitTrap[36] &&
	     commitStage_commitTrap[35:32] == 4'd3 &&
	     CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 ;
  assign commitStage_f_rob_data_first__4770_BIT_167_486_ETC___d14942 =
	     { commitStage_f_rob_data$D_OUT[167:166],
	       commitStage_f_rob_data$D_OUT[166] ?
		 CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250 :
		 CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251,
	       trap_val__h710453,
	       IF_commitStage_f_rob_data_first__4770_BITS_97__ETC___d14941 } ;
  assign commitStage_rg_serial_num_4343_PLUS_IF_rob_deq_ETC___d15467 =
	     commitStage_rg_serial_num + y__h731435 ;
  assign coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205 =
	     coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
	     coreFix_aluExe_0_dispToRegQ$first[84:78] ;
  assign coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12244 =
	     coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
	     coreFix_aluExe_0_dispToRegQ$first[76:70] ;
  assign coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12218 =
	     coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
	     coreFix_aluExe_0_dispToRegQ$first[84:78] ;
  assign coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12250 =
	     coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
	     coreFix_aluExe_0_dispToRegQ$first[76:70] ;
  assign coreFix_aluExe_0_bypassWire_2_wget__2224_BITS__ETC___d12226 =
	     coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
	     coreFix_aluExe_0_dispToRegQ$first[84:78] ;
  assign coreFix_aluExe_0_bypassWire_2_wget__2224_BITS__ETC___d12254 =
	     coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
	     coreFix_aluExe_0_dispToRegQ$first[76:70] ;
  assign coreFix_aluExe_0_dispToRegQ_first__2182_BIT_13_ETC___d12267 =
	     (coreFix_aluExe_0_dispToRegQ$first[131] ||
	      sbCons$lazyLookup_0_get[3] ||
	      IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2181_ETC___d12213 &&
	      IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12239) &&
	     (sbCons$lazyLookup_0_get[2] ||
	      IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2181_ETC___d12247 &&
	      IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12264) ;
  assign coreFix_aluExe_0_exeToFinQ_RDY_first__2641_AND_ETC___d12680 =
	     coreFix_aluExe_0_exeToFinQ$RDY_first &&
	     rob$RDY_setExecuted_doFinishAlu_0_set &&
	     (coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd9 &&
	      coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd10 ||
	      coreFix_trainBPQ_0$FULL_N) ;
  assign coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459 =
	     coreFix_aluExe_0_rsAlu$approximateCount <
	     coreFix_aluExe_1_rsAlu$approximateCount ;
  assign coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11345 =
	     coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
	     coreFix_aluExe_1_dispToRegQ$first[84:78] ;
  assign coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11384 =
	     coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
	     coreFix_aluExe_1_dispToRegQ$first[76:70] ;
  assign coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11358 =
	     coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
	     coreFix_aluExe_1_dispToRegQ$first[84:78] ;
  assign coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11390 =
	     coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
	     coreFix_aluExe_1_dispToRegQ$first[76:70] ;
  assign coreFix_aluExe_1_bypassWire_2_wget__1364_BITS__ETC___d11366 =
	     coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
	     coreFix_aluExe_1_dispToRegQ$first[84:78] ;
  assign coreFix_aluExe_1_bypassWire_2_wget__1364_BITS__ETC___d11394 =
	     coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
	     coreFix_aluExe_1_dispToRegQ$first[76:70] ;
  assign coreFix_aluExe_1_dispToRegQ_first__1322_BIT_13_ETC___d11407 =
	     (coreFix_aluExe_1_dispToRegQ$first[131] ||
	      sbCons$lazyLookup_1_get[3] ||
	      IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1321_ETC___d11353 &&
	      IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11379) &&
	     (sbCons$lazyLookup_1_get[2] ||
	      IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1321_ETC___d11387 &&
	      IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11404) ;
  assign coreFix_aluExe_1_exeToFinQ_RDY_first__1967_AND_ETC___d12007 =
	     coreFix_aluExe_1_exeToFinQ$RDY_first &&
	     rob$RDY_setExecuted_doFinishAlu_1_set &&
	     (coreFix_aluExe_1_exeToFinQ$first[326:322] != 5'd9 &&
	      coreFix_aluExe_1_exeToFinQ$first[326:322] != 5'd10 ||
	      coreFix_trainBPQ_1$FULL_N) ;
  assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8209 =
	     coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
  assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8247 =
	     coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
  assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8271 =
	     coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
  assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8222 =
	     coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
  assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8253 =
	     coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
  assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8277 =
	     coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
  assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8230 =
	     coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
  assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8257 =
	     coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
  assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8281 =
	     coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
  assign coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5272 =
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned &&
	     !coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned &&
	     rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
	     coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_data ;
  assign coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q71 =
	     coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] -
	     11'd1023 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q36 =
	     coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] -
	     11'd1023 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q106 =
	     coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] -
	     11'd1023 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3880 =
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned &&
	     !coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned &&
	     rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
	     coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_data ;
  assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6664 =
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned &&
	     !coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned &&
	     rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
	     coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_data ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d8103 =
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned &&
	     !coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned &&
	     rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_data &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY &&
	     ((coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] ==
	       2'd2) ?
		coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid :
		coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] !=
		2'd3 ||
		coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid) ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8056 =
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned &&
	     !coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned &&
	     rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_data &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N ;
  assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10852 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
	     NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807 |
	     ((f3_exp__h560440 != 8'd255 || f3_sfd__h560441 == 23'd0) &&
	      (f3_exp__h560440 != 8'd255 || f3_sfd__h560441 != 23'd0) &&
	      (f3_exp__h560440 != 8'd0 || f3_sfd__h560441 != 23'd0) &&
	      IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10847) ;
  assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10888 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
	     NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 |
	     ((f3_exp__h560440 != 8'd255 || f3_sfd__h560441 == 23'd0) &&
	      (f3_exp__h560440 != 8'd255 || f3_sfd__h560441 != 23'd0) &&
	      (f3_exp__h560440 != 8'd0 || f3_sfd__h560441 != 23'd0) &&
	      IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10883) ;
  assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10936 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
	     NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920 |
	     ((f3_exp__h560440 != 8'd255 || f3_sfd__h560441 == 23'd0) &&
	      (f3_exp__h560440 != 8'd255 || f3_sfd__h560441 != 23'd0) &&
	      (f3_exp__h560440 != 8'd0 || f3_sfd__h560441 != 23'd0) &&
	      IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10931) ;
  assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10978 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
	     NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964 |
	     ((f3_exp__h560440 != 8'd255 || f3_sfd__h560441 == 23'd0) &&
	      (f3_exp__h560440 != 8'd255 || f3_sfd__h560441 != 23'd0) &&
	      (f3_exp__h560440 != 8'd0 || f3_sfd__h560441 != 23'd0) &&
	      IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973) ;
  assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d11020 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
	     NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006 |
	     ((f3_exp__h560440 != 8'd255 || f3_sfd__h560441 == 23'd0) &&
	      (f3_exp__h560440 != 8'd255 || f3_sfd__h560441 != 23'd0) &&
	      (f3_exp__h560440 != 8'd0 || f3_sfd__h560441 != 23'd0) &&
	      IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11015) ;
  assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12 =
	     coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ;
  assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11 =
	     coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14042 =
	     coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq &&
	     regRenamingTable$RDY_rename_1_getRename &&
	     (!fetchStage$pipelines_0_canDeq ||
	      NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14022) ;
  assign coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1571 =
	     coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
	     coreFix_memExe_dispToRegQ$first[61:55] ;
  assign coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1609 =
	     coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
	     coreFix_memExe_dispToRegQ$first[53:47] ;
  assign coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1584 =
	     coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
	     coreFix_memExe_dispToRegQ$first[61:55] ;
  assign coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1615 =
	     coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
	     coreFix_memExe_dispToRegQ$first[53:47] ;
  assign coreFix_memExe_bypassWire_2_wget__590_BITS_70__ETC___d1592 =
	     coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
	     coreFix_memExe_dispToRegQ$first[61:55] ;
  assign coreFix_memExe_bypassWire_2_wget__590_BITS_70__ETC___d1619 =
	     coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
	     coreFix_memExe_dispToRegQ$first[53:47] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2577 =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd3 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072 ||
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
	     2'd0 &&
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] ==
	     y__h254805 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3067 =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 ||
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT ||
	      !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry &&
	      !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl) &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3170 =
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3138 ||
	     (!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT ||
	      !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas &&
	      !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl) &&
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
  assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2070 =
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] ==
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150 =
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2070 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2727 =
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] ==
	     coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[65:8] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] ==
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <
	     2'd2 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518] ==
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2531 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027 &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	      3'd3 ||
	      coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150) ||
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2560 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd2 ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd3) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2565 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2557 ||
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2564 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2582 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2557 ||
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2581 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2599 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2592 ||
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2598 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2619 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 &&
	     coreFix_memExe_lsq$getHit[8] &&
	     !coreFix_memExe_lsq$getHit[9] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2622 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 &&
	     coreFix_memExe_lsq$getHit[8] &&
	     !coreFix_memExe_lsq$getHit[9] ||
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd1) &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2619 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2643 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd3 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2649 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2643 ||
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd1) &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2646 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2651 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027 &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	      3'd3 ||
	      coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2697 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <=
	     coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2700 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518] ==
	     coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[65:14] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2797 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[78] :
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[78]) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2801 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[77] :
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[77]) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2805 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[76] :
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[76]) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2810 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[75] :
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[75]) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2814 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[74] :
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[74]) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[73] :
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[73]) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2823 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[72] :
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[72]) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2828 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[71] :
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[71]) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[2] :
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[2]) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[1] :
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[1]) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2848 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[0] :
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[0]) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enq_ETC___d3341 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3309 ||
	     (!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT ||
	      !EN_dCacheToParent_rqToP_deq &&
	      !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl) &&
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enq_ETC___d3437 =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3405 ||
	     (!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT ||
	      !EN_dCacheToParent_rsToP_deq &&
	      !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl) &&
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full ;
  assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2_r_ETC___d1911 =
	     coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT &&
	     coreFix_memExe_dMem_perfReqQ_enqReq_rl[4] ||
	     (!coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT ||
	      !coreFix_memExe_dMem_perfReqQ_deqReq_rl) &&
	     coreFix_memExe_dMem_perfReqQ_full ;
  assign coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1726 =
	     coreFix_memExe_dTlb$procResp[246:186] < 61'd402653184 ;
  assign coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1727 =
	     coreFix_memExe_dTlb$procResp[246:186] < 61'd536870912 ;
  assign coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1731 =
	     coreFix_memExe_dTlb$procResp[246:186] == mmio_toHostAddr ;
  assign coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1734 =
	     coreFix_memExe_dTlb$procResp[246:186] == mmio_fromHostAddr ;
  assign coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735 =
	     coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1726 ||
	     !coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1727 ||
	     coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1731 ||
	     coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1734 ;
  assign coreFix_memExe_forwardQ_enqReq_dummy2_2_read___ETC___d3759 =
	     coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3728 ||
	     (!coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT ||
	      !WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	      !coreFix_memExe_forwardQ_deqReq_rl) &&
	     coreFix_memExe_forwardQ_full ;
  assign coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d1706 =
	     { coreFix_memExe_lsq$getOrigBE << x__h183904[2:0],
	       x__h183904,
	       coreFix_memExe_regToExeQ$first[75:12],
	       coreFix_memExe_lsq$getOrigBE,
	       coreFix_memExe_lsq$getOrigBE[7] ?
		 x__h183904[2:0] != 3'd0 :
		 (coreFix_memExe_lsq$getOrigBE[3] ?
		    x__h183904[1:0] != 2'd0 :
		    coreFix_memExe_lsq$getOrigBE[1] && x__h183904[0]) } ;
  assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3665 =
	     coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3634 ||
	     (!coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT ||
	      !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	      !coreFix_memExe_memRespLdQ_deqReq_rl) &&
	     coreFix_memExe_memRespLdQ_full ;
  assign coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10 =
	     coreFix_memExe_regToExeQ$first[189:158] ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[78] :
		coreFix_memExe_reqLrScAmoQ_data_0_rl[78]) ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1220 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[77] :
		coreFix_memExe_reqLrScAmoQ_data_0_rl[77]) ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[76] :
		coreFix_memExe_reqLrScAmoQ_data_0_rl[76]) ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1229 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[75] :
		coreFix_memExe_reqLrScAmoQ_data_0_rl[75]) ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1233 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[74] :
		coreFix_memExe_reqLrScAmoQ_data_0_rl[74]) ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[73] :
		coreFix_memExe_reqLrScAmoQ_data_0_rl[73]) ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[72] :
		coreFix_memExe_reqLrScAmoQ_data_0_rl[72]) ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[71] :
		coreFix_memExe_reqLrScAmoQ_data_0_rl[71]) ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[2] :
		coreFix_memExe_reqLrScAmoQ_data_0_rl[2]) ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[1] :
		coreFix_memExe_reqLrScAmoQ_data_0_rl[1]) ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[0] :
		coreFix_memExe_reqLrScAmoQ_data_0_rl[0]) ;
  assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3574 =
	     coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3558 ||
	     (!coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT ||
	      !coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas &&
	      !coreFix_memExe_respLrScAmoQ_deqReq_rl) &&
	     coreFix_memExe_respLrScAmoQ_full ;
  assign coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14671 =
	     coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty &&
	     v_f_to_TV_0$FULL_N &&
	     fetchStage$iTlbIfc_noPendingReq &&
	     coreFix_memExe_dTlb$noPendingReq ;
  assign csr_addr__h655332 =
	     fetchStage$pipelines_0_first[173] ?
	       IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973 :
	       12'hCFF ;
  assign csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13045 =
	     csrf_fs_reg == 2'd0 &&
	     (fetchStage$pipelines_0_first[95] &&
	      fetchStage$pipelines_0_first[94] ||
	      fetchStage$pipelines_0_first[88] &&
	      fetchStage$pipelines_0_first[87] ||
	      fetchStage$pipelines_0_first[81] ||
	      fetchStage$pipelines_0_first[75] &&
	      fetchStage$pipelines_0_first[74]) ||
	     fetchStage$pipelines_0_first[199:195] == 5'd13 &&
	     (fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13038 ||
	      csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 ||
	      csr_addr__h655332 == 12'h8FF) ;
  assign csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13517 =
	     csrf_fs_reg == 2'd0 &&
	     (fetchStage$pipelines_0_first[95] &&
	      fetchStage$pipelines_0_first[94] ||
	      fetchStage$pipelines_0_first[88] &&
	      fetchStage$pipelines_0_first[87] ||
	      fetchStage$pipelines_0_first[81] ||
	      fetchStage$pipelines_0_first[75] &&
	      fetchStage$pipelines_0_first[74]) ||
	     fetchStage$pipelines_0_first[231:200] == 32'h10500073 &&
	     csrf_tw_reg &&
	     csrf_prv_reg != 2'd3 ;
  assign csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13806 =
	     csrf_fs_reg == 2'd0 &&
	     (fetchStage$pipelines_1_first[95] &&
	      fetchStage$pipelines_1_first[94] ||
	      fetchStage$pipelines_1_first[88] &&
	      fetchStage$pipelines_1_first[87] ||
	      fetchStage$pipelines_1_first[81] ||
	      fetchStage$pipelines_1_first[75] &&
	      fetchStage$pipelines_1_first[74]) ||
	     fetchStage$pipelines_1_first[231:200] == 32'h10500073 &&
	     csrf_tw_reg &&
	     csrf_prv_reg != 2'd3 ;
  assign csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 =
	     csrf_prv_reg_read__2787_ULE_1___d14711 &&
	     (commitStage_commitTrap[36] ?
		_0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14713 :
		_0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14731) ;
  assign csrf_prv_reg_read__2787_ULE_1___d14711 = csrf_prv_reg <= 2'd1 ;
  assign csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 =
	     csrf_prv_reg < csr_addr__h655332[9:8] ;
  assign csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13513 =
	     csrf_rg_dcsr[2] || !fetchStage$pipelines_0_canDeq ||
	     fetchStage$RDY_pipelines_0_first &&
	     IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13450 ;
  assign data75284_BITS_31_TO_0__q13 = data__h475284[31:0] ;
  assign data___1__h475010 =
	     { {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133[31]}},
	       IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133 } ;
  assign data___1__h475818 =
	     { {32{data75284_BITS_31_TO_0__q13[31]}},
	       data75284_BITS_31_TO_0__q13 } ;
  assign data__h475284 =
	     (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] ==
	      2'd2) ?
	       x_quotient__h475198 :
	       x_remainder__h475199 ;
  assign dcsr_cause__h709971 =
	     (commitStage_commitTrap[36] &&
	      commitStage_commitTrap[35:32] == 4'd14) ?
	       3'd3 :
	       ((commitStage_commitTrap[36] &&
		 commitStage_commitTrap[35:32] != 4'd0 &&
		 commitStage_commitTrap[35:32] != 4'd1 &&
		 commitStage_commitTrap[35:32] != 4'd3 &&
		 commitStage_commitTrap[35:32] != 4'd4 &&
		 commitStage_commitTrap[35:32] != 4'd5 &&
		 commitStage_commitTrap[35:32] != 4'd7 &&
		 commitStage_commitTrap[35:32] != 4'd8 &&
		 commitStage_commitTrap[35:32] != 4'd9 &&
		 commitStage_commitTrap[35:32] != 4'd11 &&
		 commitStage_commitTrap[35:32] != 4'd14) ?
		  3'd4 :
		  3'd1) ;
  assign din_inc___2_exp__h381231 = _theResult___fst_exp__h354198 + 8'd1 ;
  assign din_inc___2_exp__h381255 = _theResult___fst_exp__h362854 + 8'd1 ;
  assign din_inc___2_exp__h381285 = _theResult___fst_exp__h371964 + 8'd1 ;
  assign din_inc___2_exp__h381309 = _theResult___fst_exp__h380649 + 8'd1 ;
  assign din_inc___2_exp__h426928 = _theResult___fst_exp__h399895 + 8'd1 ;
  assign din_inc___2_exp__h426952 = _theResult___fst_exp__h408551 + 8'd1 ;
  assign din_inc___2_exp__h426982 = _theResult___fst_exp__h417661 + 8'd1 ;
  assign din_inc___2_exp__h427006 = _theResult___fst_exp__h426346 + 8'd1 ;
  assign din_inc___2_exp__h472623 = _theResult___fst_exp__h445590 + 8'd1 ;
  assign din_inc___2_exp__h472647 = _theResult___fst_exp__h454246 + 8'd1 ;
  assign din_inc___2_exp__h472677 = _theResult___fst_exp__h463356 + 8'd1 ;
  assign din_inc___2_exp__h472701 = _theResult___fst_exp__h472041 + 8'd1 ;
  assign din_inc___2_exp__h520780 = _theResult___fst_exp__h501530 + 11'd1 ;
  assign din_inc___2_exp__h520815 = _theResult___fst_exp__h511107 + 11'd1 ;
  assign din_inc___2_exp__h520841 = _theResult___fst_exp__h519940 + 11'd1 ;
  assign din_inc___2_exp__h559633 = _theResult___fst_exp__h540383 + 11'd1 ;
  assign din_inc___2_exp__h559668 = _theResult___fst_exp__h549960 + 11'd1 ;
  assign din_inc___2_exp__h559694 = _theResult___fst_exp__h558793 + 11'd1 ;
  assign din_inc___2_exp__h598937 = _theResult___fst_exp__h579687 + 11'd1 ;
  assign din_inc___2_exp__h598972 = _theResult___fst_exp__h589264 + 11'd1 ;
  assign din_inc___2_exp__h598998 = _theResult___fst_exp__h598097 + 11'd1 ;
  assign enabled_ints___1__h651648 = pend_ints__h651121 & y__h651660 ;
  assign enabled_ints__h651694 =
	     pend_ints__h651121 &
	     { r1__read_BITS_13_TO_0___h651670, csrf_mideleg_1_0_reg } ;
  assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13749 =
	     epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] &&
	     (!fetchStage$pipelines_0_canDeq ||
	      (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	       specTagManager$canClaim) &&
	      regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 &&
	      IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13480) ;
  assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13891 =
	     epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] &&
	     (!fetchStage$pipelines_0_canDeq ||
	      (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	       specTagManager$canClaim) &&
	      regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 &&
	      IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13887) ;
  assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13909 =
	     epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] &&
	     (!fetchStage$pipelines_0_canDeq ||
	      (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	       specTagManager$canClaim) &&
	      regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 &&
	      IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13905) ;
  assign f1_exp82142_MINUS_127__q136 = f1_exp__h482142 - 8'd127 ;
  assign f1_exp__h482142 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] :
	       8'd255 ;
  assign f1_sfd__h482143 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] :
	       23'd4194304 ;
  assign f2_exp21136_MINUS_127__q176 = f2_exp__h521136 - 8'd127 ;
  assign f2_exp__h521136 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] :
	       8'd255 ;
  assign f2_sfd__h521137 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] :
	       23'd4194304 ;
  assign f3_exp60440_MINUS_127__q153 = f3_exp__h560440 - 8'd127 ;
  assign f3_exp__h560440 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] :
	       8'd255 ;
  assign f3_sfd__h560441 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] :
	       23'd4194304 ;
  assign f_csr_rsps_i_notFull__5799_AND_f_csr_reqs_firs_ETC___d15902 =
	     f_csr_rsps$FULL_N &&
	     (f_csr_reqs$D_OUT[75:64] != 12'd2049 ||
	      csrf_stats_module_writeQ$FULL_N) &&
	     (f_csr_reqs$D_OUT[75:64] != 12'd2048 ||
	      csrf_terminate_module_terminateQ$FULL_N) ;
  assign fcsr_csr__read__h609378 = { 56'd0, x__h613036 } ;
  assign fetchStage_RDY_pipelines_0_first__2754_AND_epo_ETC___d13309 =
	     fetchStage$RDY_pipelines_0_first &&
	     epochManager$RDY_incrementEpoch &&
	     regRenamingTable$RDY_rename_0_getRename &&
	     regRenamingTable$RDY_rename_0_claimRename &&
	     rob$RDY_enqPort_0_enq &&
	     (fetchStage$pipelines_0_first[194:192] != 3'd0 ||
	      coreFix_aluExe_0_rsAlu$RDY_enq) ;
  assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14033 =
	     fetchStage$pipelines_0_canDeq &&
	     (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	      specTagManager$canClaim) &&
	     regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 &&
	     fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13760 ||
	     !coreFix_aluExe_0_rsAlu$canEnq ||
	     (!fetchStage$pipelines_0_canDeq ||
	      fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14029) &&
	     coreFix_aluExe_1_rsAlu$canEnq &&
	     !coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459 ;
  assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14115 =
	     fetchStage$pipelines_0_canDeq &&
	     NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 &&
	     (fetchStage$pipelines_0_first[194:192] == 3'd0 ||
	      fetchStage$pipelines_0_first[194:192] == 3'd1) &&
	     SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 ;
  assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14191 =
	     fetchStage$pipelines_0_canDeq &&
	     NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14112 &&
	     fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13760 ||
	     !coreFix_aluExe_0_rsAlu$canEnq ;
  assign fetchStage_pipelines_0_canDeq__2755_AND_fetchS_ETC___d14103 =
	     fetchStage$pipelines_0_canDeq &&
	     fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13977 ||
	     !fetchStage$pipelines_1_canDeq ||
	     fetchStage$RDY_pipelines_1_first &&
	     (fetchStage_pipelines_1_first__2766_BITS_194_TO_ETC___d13988 ||
	      !regRenamingTable$rename_1_canRename ||
	      fetchStage_pipelines_1_first__2766_BITS_199_TO_ETC___d14000 ||
	      IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14099) &&
	     IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13920 ;
  assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14039 =
	     fetchStage$pipelines_0_canDeq &&
	     regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 &&
	     (fetchStage$pipelines_0_first[194:192] == 3'd3 ||
	      fetchStage$pipelines_0_first[194:192] == 3'd4) ;
  assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14046 =
	     fetchStage$pipelines_0_canDeq &&
	     regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 &&
	     fetchStage$pipelines_0_first[194:192] == 3'd2 &&
	     IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 ||
	     !coreFix_memExe_rsMem$canEnq ||
	     CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ;
  assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14068 =
	     fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14039 ||
	     !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
	     fetchStage$pipelines_0_canDeq &&
	     (fetchStage$pipelines_0_first[194:192] == 3'd1 &&
	      !specTagManager$canClaim ||
	      NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13852 ||
	      IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14059) ;
  assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14080 =
	     fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14046 ||
	     fetchStage$pipelines_0_canDeq &&
	     (fetchStage$pipelines_0_first[194:192] == 3'd1 &&
	      !specTagManager$canClaim ||
	      NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13852 ||
	      IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14071) ;
  assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14311 =
	     fetchStage$pipelines_0_canDeq &&
	     regRenamingTable_rename_0_canRename__3418_AND__ETC___d14309 ||
	     !coreFix_memExe_rsMem$canEnq ||
	     CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ;
  assign fetchStage_pipelines_0_canDeq__2755_AND_specTa_ETC___d14167 =
	     fetchStage$pipelines_0_canDeq && specTagManager$canClaim &&
	     regRenamingTable$rename_0_canRename &&
	     !checkForException___d13008[4] &&
	     rob$enqPort_0_canEnq &&
	     IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 &&
	     fetchStage$pipelines_0_first[194:192] == 3'd1 ;
  assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13038 =
	     (fetchStage$pipelines_0_first[194:192] == 3'd0 &&
	      fetchStage$pipelines_0_first[178:174] == 5'd15 ||
	      rs1__h655333 != 5'd0 ||
	      imm__h655334 != 32'd0) &&
	     csr_addr__h655332[11:10] == 2'b11 ;
  assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13760 =
	     (fetchStage$pipelines_0_first[194:192] == 3'd0 ||
	      fetchStage$pipelines_0_first[194:192] == 3'd1) &&
	     SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 &&
	     (!coreFix_aluExe_1_rsAlu$canEnq ||
	      coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459) ;
  assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13859 =
	     fetchStage$pipelines_0_first[194:192] == 3'd1 &&
	     !specTagManager$canClaim ||
	     renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855 ;
  assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13971 =
	     fetchStage$pipelines_0_first[194:192] == 3'd1 &&
	     !specTagManager$canClaim ||
	     !regRenamingTable$rename_0_canRename ||
	     renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935 ||
	     IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13960 &&
	     IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13969 ;
  assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13977 =
	     fetchStage$pipelines_0_first[194:192] == 3'd1 &&
	     !specTagManager$canClaim ||
	     !regRenamingTable$rename_0_canRename ||
	     renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935 ||
	     IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13976 ;
  assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13994 =
	     fetchStage$pipelines_0_first[194:192] == 3'd1 &&
	     !specTagManager$canClaim ||
	     !regRenamingTable$rename_0_canRename ||
	     fetchStage$pipelines_0_first[68] ||
	     checkForException___d13008[4] ||
	     !rob$enqPort_0_canEnq ||
	     IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13976 ;
  assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14006 =
	     fetchStage$pipelines_0_first[194:192] == 3'd1 &&
	     !specTagManager$canClaim ||
	     NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13776 ||
	     fetchStage$pipelines_0_first[194:192] != 3'd0 &&
	     fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	     !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 ||
	     coreFix_aluExe_1_rsAlu$canEnq &&
	     !coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459 ;
  assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14013 =
	     fetchStage$pipelines_0_first[194:192] == 3'd1 &&
	     !specTagManager$canClaim ||
	     NOT_regRenamingTable_rename_0_canRename__3418__ETC___d13776 ||
	     fetchStage$pipelines_0_first[194:192] != 3'd0 &&
	     fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	     !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 ||
	     coreFix_aluExe_0_rsAlu$canEnq &&
	     coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459 ;
  assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14029 =
	     fetchStage$pipelines_0_first[194:192] == 3'd1 &&
	     !specTagManager$canClaim ||
	     !regRenamingTable$rename_0_canRename ||
	     fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13524 ||
	     fetchStage$pipelines_0_first[194:192] != 3'd0 &&
	     fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	     !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 ;
  assign fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13524 =
	     fetchStage$pipelines_0_first[199:195] == 5'd0 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd21 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd17 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd18 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd13 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd16 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd15 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd19 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd20 ||
	     renameStage_rg_m_halt_req[4] ||
	     fetchStage$pipelines_0_first[68] ||
	     checkForException___d13008[4] ||
	     csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13517 ||
	     !rob$enqPort_0_canEnq ||
	     !epochManager$checkEpoch_0_check ;
  assign fetchStage_pipelines_0_first__2757_BIT_173_288_ETC___d13411 =
	     { fetchStage$pipelines_0_first[173],
	       IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973,
	       73'h1280000000000000000,
	       fetchStage$pipelines_0_first[323:260],
	       5'd0,
	       (fetchStage$pipelines_0_first[173] &&
		fetchStage$pipelines_0_first[199:195] == 5'd13 &&
		(fetchStage$pipelines_0_first[172:161] == 12'd1 ||
		 fetchStage$pipelines_0_first[172:161] == 12'd2 ||
		 fetchStage$pipelines_0_first[172:161] == 12'd3)) ?
		 fetchStage$pipelines_0_first[194:192] == 3'd0 &&
		 fetchStage$pipelines_0_first[178:174] == 5'd15 ||
		 (!fetchStage$pipelines_0_first[88] ||
		  fetchStage$pipelines_0_first[87] ||
		  fetchStage$pipelines_0_first[86:82] != 5'd0) &&
		 (!fetchStage$pipelines_0_first[160] ||
		  fetchStage$pipelines_0_first[159:128] != 32'd0) :
		 fetchStage$pipelines_0_first[75] &&
		 fetchStage$pipelines_0_first[74],
	       fetchStage$pipelines_0_first[194:192] != 3'd0,
	       13'h1521,
	       specTagManager$currentSpecBits } ;
  assign fetchStage_pipelines_0_first__2757_BIT_68_2786_ETC___d13850 =
	     fetchStage$pipelines_0_first[68] ||
	     checkForException___d13008[4] ||
	     csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13517 ||
	     !rob$enqPort_0_canEnq ||
	     !epochManager$checkEpoch_0_check ;
  assign fetchStage_pipelines_1_first__2766_BITS_194_TO_ETC___d13988 =
	     fetchStage$pipelines_1_first[194:192] == 3'd1 &&
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3418_AND__ETC___d13985 ||
	      !specTagManager$canClaim) ;
  assign fetchStage_pipelines_1_first__2766_BITS_199_TO_ETC___d14000 =
	     fetchStage$pipelines_1_first[199:195] == 5'd0 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd21 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd17 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd18 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd13 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd16 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd15 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd19 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd20 ||
	     renameStage_rg_m_halt_req[4] ||
	     fetchStage$pipelines_1_first[68] ||
	     checkForException___d13713[4] ||
	     csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13806 ||
	     !rob$enqPort_1_canEnq ||
	     !epochManager$checkEpoch_1_check ||
	     csrf_rg_dcsr[2] ||
	     fetchStage$pipelines_0_canDeq &&
	     fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13994 ;
  assign fetchStage_pipelines_1_first__2766_BIT_173_360_ETC___d13691 =
	     { fetchStage$pipelines_1_first[173],
	       CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 } ;
  assign fflags__h734227 =
	     NOT_rob_deqPort_0_canDeq__5346_5347_OR_rob_deq_ETC___d15667 ?
	       y_avValue_fst__h734164 :
	       IF_rob_deqPort_0_canDeq__5346_THEN_IF_NOT_rob__ETC___d15673 ;
  assign fflags_csr__read__h609353 = { 59'd0, csrf_fflags_reg } ;
  assign frm_csr__read__h609364 = { 61'd0, csrf_frm_reg } ;
  assign guard__h346097 =
	     { IF_sfdin54192_BIT_33_THEN_2_ELSE_0__q29[1],
	       { sfdin__h354192[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h354806 =
	     { IF_theResult___snd62805_BIT_33_THEN_2_ELSE_0__q31[1],
	       { _theResult___snd__h362805[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h363736 =
	     { IF_sfdin71958_BIT_33_THEN_2_ELSE_0__q39[1],
	       { sfdin__h371958[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h364334 = x__h364436 != 57'd0 ;
  assign guard__h372572 =
	     { IF_theResult___snd80595_BIT_33_THEN_2_ELSE_0__q44[1],
	       { _theResult___snd__h380595[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h391796 =
	     { IF_sfdin99889_BIT_33_THEN_2_ELSE_0__q64[1],
	       { sfdin__h399889[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h400503 =
	     { IF_theResult___snd08502_BIT_33_THEN_2_ELSE_0__q66[1],
	       { _theResult___snd__h408502[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h409433 =
	     { IF_sfdin17655_BIT_33_THEN_2_ELSE_0__q74[1],
	       { sfdin__h417655[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h410031 = x__h410133 != 57'd0 ;
  assign guard__h418269 =
	     { IF_theResult___snd26292_BIT_33_THEN_2_ELSE_0__q79[1],
	       { _theResult___snd__h426292[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h437491 =
	     { IF_sfdin45584_BIT_33_THEN_2_ELSE_0__q99[1],
	       { sfdin__h445584[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h446198 =
	     { IF_theResult___snd54197_BIT_33_THEN_2_ELSE_0__q101[1],
	       { _theResult___snd__h454197[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h455128 =
	     { IF_sfdin63350_BIT_33_THEN_2_ELSE_0__q109[1],
	       { sfdin__h463350[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h455726 = x__h455828 != 57'd0 ;
  assign guard__h463964 =
	     { IF_theResult___snd71987_BIT_33_THEN_2_ELSE_0__q114[1],
	       { _theResult___snd__h471987[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h493569 =
	     { IF_theResult___snd01481_BIT_4_THEN_2_ELSE_0__q135[1],
	       { _theResult___snd__h501481[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h502881 =
	     { IF_sfdin11101_BIT_4_THEN_2_ELSE_0__q139[1],
	       { sfdin__h511101[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h503479 = x__h503579 != 57'd0 ;
  assign guard__h511950 =
	     { IF_theResult___snd19886_BIT_4_THEN_2_ELSE_0__q142[1],
	       { _theResult___snd__h519886[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h532422 =
	     { IF_theResult___snd40334_BIT_4_THEN_2_ELSE_0__q175[1],
	       { _theResult___snd__h540334[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h541734 =
	     { IF_sfdin49954_BIT_4_THEN_2_ELSE_0__q179[1],
	       { sfdin__h549954[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h542332 = x__h542432 != 57'd0 ;
  assign guard__h550803 =
	     { IF_theResult___snd58739_BIT_4_THEN_2_ELSE_0__q182[1],
	       { _theResult___snd__h558739[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h571726 =
	     { IF_theResult___snd79638_BIT_4_THEN_2_ELSE_0__q152[1],
	       { _theResult___snd__h579638[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h581038 =
	     { IF_sfdin89258_BIT_4_THEN_2_ELSE_0__q156[1],
	       { sfdin__h589258[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h581636 = x__h581736 != 57'd0 ;
  assign guard__h590107 =
	     { IF_theResult___snd98043_BIT_4_THEN_2_ELSE_0__q159[1],
	       { _theResult___snd__h598043[3:0], 52'd0 } != 56'd0 } ;
  assign idx__h686379 =
	     fetchStage$pipelines_0_canDeq &&
	     NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13761 ||
	     !coreFix_aluExe_0_rsAlu$canEnq ||
	     NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13785 ;
  assign imm__h655334 =
	     fetchStage$pipelines_0_first[160] ?
	       fetchStage$pipelines_0_first[159:128] :
	       32'd0 ;
  assign k__h670634 =
	     !coreFix_aluExe_0_rsAlu$canEnq ||
	     coreFix_aluExe_1_rsAlu$canEnq &&
	     !coreFix_aluExe_0_rsAlu_approximateCount__3457__ETC___d13459 ;
  assign mcause_csr__read__h611020 =
	     { r1__read__h614499, csrf_mcause_code_reg } ;
  assign mcounteren_csr__read__h610765 =
	     { r1__read__h614486, csrf_mcounteren_cy_reg } ;
  assign medeleg_csr__read__h610372 =
	     { r1__read__h614347, csrf_medeleg_9_0_reg } ;
  assign mideleg_csr__read__h610467 =
	     { r1__read__h614364, csrf_mideleg_1_0_reg } ;
  assign mie_csr__read__h610591 = { r1__read__h614388, 1'b0 } ;
  assign mip_csr__read__h611253 = { r1__read__h614505, 1'b0 } ;
  assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 =
	     mmio_cRqQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 ||
	     (!mmio_cRqQ_deqReq_dummy2_2$Q_OUT ||
	      !EN_mmioToPlatform_cRq_deq && !mmio_cRqQ_deqReq_rl) &&
	     mmio_cRqQ_full ;
  assign mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836 =
	     mmio_cRsQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 ||
	     (!mmio_cRsQ_deqReq_dummy2_2$Q_OUT ||
	      !EN_mmioToPlatform_cRs_deq && !mmio_cRsQ_deqReq_rl) &&
	     mmio_cRsQ_full ;
  assign mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312 =
	     mmio_dataPendQ_enqReq_dummy2_2$Q_OUT &&
	     (mmio_dataPendQ_enqReq_lat_0$whas || mmio_dataPendQ_enqReq_rl) ||
	     (!mmio_dataPendQ_deqReq_dummy2_2$Q_OUT ||
	      !mmio_dataRespQ_deqReq_lat_0$whas &&
	      !mmio_dataPendQ_deqReq_rl) &&
	     mmio_dataPendQ_full ;
  assign mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153 =
	     mmio_dataReqQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 ||
	     (!mmio_dataReqQ_deqReq_dummy2_2$Q_OUT ||
	      !CAN_FIRE_RL_mmio_sendDataReq && !mmio_dataReqQ_deqReq_rl) &&
	     mmio_dataReqQ_full ;
  assign mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254 =
	     mmio_dataRespQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 ||
	     (!mmio_dataRespQ_deqReq_dummy2_2$Q_OUT ||
	      !mmio_dataRespQ_deqReq_lat_0$whas &&
	      !mmio_dataRespQ_deqReq_rl) &&
	     mmio_dataRespQ_full ;
  assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13055 =
	     mmio_pRqQ_empty && epochManager$checkEpoch_0_check &&
	     (renameStage_rg_m_halt_req[4] ||
	      fetchStage$pipelines_0_first[68] ||
	      IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13052) ;
  assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13347 =
	     mmio_pRqQ_empty && epochManager$checkEpoch_0_check &&
	     !renameStage_rg_m_halt_req[4] &&
	     !fetchStage$pipelines_0_first[68] &&
	     NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13344 ;
  assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13365 =
	     mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13347 &&
	     (fetchStage$pipelines_0_first[199:195] == 5'd0 ||
	      fetchStage$pipelines_0_first[199:195] == 5'd21 ||
	      fetchStage$pipelines_0_first[199:195] == 5'd17 ||
	      fetchStage$pipelines_0_first[199:195] == 5'd18 ||
	      fetchStage$pipelines_0_first[199:195] == 5'd13 ||
	      fetchStage$pipelines_0_first[199:195] == 5'd16 ||
	      fetchStage$pipelines_0_first[199:195] == 5'd15 ||
	      fetchStage$pipelines_0_first[199:195] == 5'd19 ||
	      fetchStage$pipelines_0_first[199:195] == 5'd20) &&
	     rob$isEmpty ;
  assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14107 =
	     mmio_pRqQ_empty && epochManager$checkEpoch_0_check &&
	     !renameStage_rg_m_halt_req[4] &&
	     !fetchStage$pipelines_0_first[68] &&
	     NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13437 ;
  assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14109 =
	     mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14107 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd0 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd21 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd17 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd18 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd13 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd16 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd15 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd19 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd20 &&
	     rg_core_run_state == 2'd2 ;
  assign mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747 =
	     mmio_pRqQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 ||
	     (!mmio_pRqQ_deqReq_dummy2_2$Q_OUT ||
	      !CAN_FIRE_RL_mmio_handlePRq && !mmio_pRqQ_deqReq_rl) &&
	     mmio_pRqQ_full ;
  assign mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606 =
	     mmio_pRsQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 ||
	     (!mmio_pRsQ_deqReq_dummy2_2$Q_OUT ||
	      !mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) &&
	     mmio_pRsQ_full ;
  assign mstatus_csr__read__h610224 = { r1__read__h614222, csrf_ie_vec_0 } ;
  assign mtvec_csr__read__h610673 =
	     { r1__read__h614481, csrf_mtvec_mode_low_reg } ;
  assign n___1__h198531 =
	     { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ?
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] :
		 x__h197128[63:56],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ?
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] :
		 x__h197128[55:48],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ?
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] :
		 x__h197128[47:40],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ?
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] :
		 x__h197128[39:32],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ?
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] :
		 x__h197128[31:24],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ?
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] :
		 x__h197128[23:16],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ?
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] :
		 x__h197128[15:8],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ?
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] :
		 x__h197128[7:0] } ;
  assign n__read__h611357 =
	     (csrf_mcycle_ehr_data_dummy2_0$Q_OUT &&
	      csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ?
	       csrf_mcycle_ehr_data_rl :
	       64'd0 ;
  assign n__read__h611548 =
	     (csrf_minstret_ehr_data_dummy2_0$Q_OUT &&
	      csrf_minstret_ehr_data_dummy2_1$Q_OUT) ?
	       csrf_minstret_ehr_data_rl :
	       64'd0 ;
  assign n__read__h6761 =
	     csrf_mcycle_ehr_data_dummy2_1$Q_OUT ?
	       (csrf_mcycle_ehr_data_lat_0$whas ?
		  upd__h6875 :
		  csrf_mcycle_ehr_data_rl) :
	       64'd0 ;
  assign n__read__h727667 =
	     csrf_minstret_ehr_data_dummy2_1$Q_OUT ?
	       IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 :
	       64'd0 ;
  assign new_mstatus___1__h727029 = x__h727020 ;
  assign next_deqP___1__h296802 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ==
	      3'd7) ?
	       3'd0 :
	       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP +
	       3'd1 ;
  assign next_deqP___1__h304798 =
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ;
  assign next_deqP___1__h311079 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ;
  assign next_deqP___1__h318933 =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ;
  assign next_deqP___1__h328990 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ;
  assign next_deqP___1__h332215 = coreFix_memExe_forwardQ_deqP + 1'd1 ;
  assign next_pc__h723452 =
	     (rob$deqPort_0_deq_data[329:325] != 5'd13 &&
	      rob$deqPort_0_deq_data[97:96] == 2'd0) ?
	       rob$deqPort_0_deq_data[95:32] :
	       rob$deqPort_0_deq_data[425:362] + 64'd4 ;
  assign old_fflags1__h733714 =
	     csrf_fflags_reg | rob$deqPort_0_deq_data[31:27] ;
  assign out___1_sfd__h482206 = { f1_sfd__h482143, 29'd0 } ;
  assign out___1_sfd__h521200 = { f2_sfd__h521137, 29'd0 } ;
  assign out___1_sfd__h560504 = { f3_sfd__h560441, 29'd0 } ;
  assign out_exp__h354717 =
	     sfdin__h354192[34] ?
	       _theResult___exp__h354714 :
	       _theResult___fst_exp__h354198 ;
  assign out_exp__h363299 =
	     _theResult___snd__h362805[34] ?
	       _theResult___exp__h363296 :
	       _theResult___fst_exp__h362854 ;
  assign out_exp__h372483 =
	     sfdin__h371958[34] ?
	       _theResult___exp__h372480 :
	       _theResult___fst_exp__h371964 ;
  assign out_exp__h381119 =
	     _theResult___snd__h380595[34] ?
	       _theResult___exp__h381116 :
	       _theResult___fst_exp__h380649 ;
  assign out_exp__h400414 =
	     sfdin__h399889[34] ?
	       _theResult___exp__h400411 :
	       _theResult___fst_exp__h399895 ;
  assign out_exp__h408996 =
	     _theResult___snd__h408502[34] ?
	       _theResult___exp__h408993 :
	       _theResult___fst_exp__h408551 ;
  assign out_exp__h418180 =
	     sfdin__h417655[34] ?
	       _theResult___exp__h418177 :
	       _theResult___fst_exp__h417661 ;
  assign out_exp__h426816 =
	     _theResult___snd__h426292[34] ?
	       _theResult___exp__h426813 :
	       _theResult___fst_exp__h426346 ;
  assign out_exp__h446109 =
	     sfdin__h445584[34] ?
	       _theResult___exp__h446106 :
	       _theResult___fst_exp__h445590 ;
  assign out_exp__h454691 =
	     _theResult___snd__h454197[34] ?
	       _theResult___exp__h454688 :
	       _theResult___fst_exp__h454246 ;
  assign out_exp__h463875 =
	     sfdin__h463350[34] ?
	       _theResult___exp__h463872 :
	       _theResult___fst_exp__h463356 ;
  assign out_exp__h472511 =
	     _theResult___snd__h471987[34] ?
	       _theResult___exp__h472508 :
	       _theResult___fst_exp__h472041 ;
  assign out_exp__h502188 =
	     _theResult___snd__h501481[5] ?
	       _theResult___exp__h502185 :
	       _theResult___fst_exp__h501530 ;
  assign out_exp__h511839 =
	     sfdin__h511101[5] ?
	       _theResult___exp__h511836 :
	       _theResult___fst_exp__h511107 ;
  assign out_exp__h520623 =
	     _theResult___snd__h519886[5] ?
	       _theResult___exp__h520620 :
	       _theResult___fst_exp__h519940 ;
  assign out_exp__h541041 =
	     _theResult___snd__h540334[5] ?
	       _theResult___exp__h541038 :
	       _theResult___fst_exp__h540383 ;
  assign out_exp__h550692 =
	     sfdin__h549954[5] ?
	       _theResult___exp__h550689 :
	       _theResult___fst_exp__h549960 ;
  assign out_exp__h559476 =
	     _theResult___snd__h558739[5] ?
	       _theResult___exp__h559473 :
	       _theResult___fst_exp__h558793 ;
  assign out_exp__h580345 =
	     _theResult___snd__h579638[5] ?
	       _theResult___exp__h580342 :
	       _theResult___fst_exp__h579687 ;
  assign out_exp__h589996 =
	     sfdin__h589258[5] ?
	       _theResult___exp__h589993 :
	       _theResult___fst_exp__h589264 ;
  assign out_exp__h598780 =
	     _theResult___snd__h598043[5] ?
	       _theResult___exp__h598777 :
	       _theResult___fst_exp__h598097 ;
  assign out_f_exp__h381495 =
	     (_theResult___exp__h381218 == 8'd255 &&
	      _theResult___sfd__h381219 != 23'd0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd2047) ?
	       8'd255 :
	       _theResult___fst_exp__h381209 ;
  assign out_f_exp__h427192 =
	     (_theResult___exp__h426915 == 8'd255 &&
	      _theResult___sfd__h426916 != 23'd0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd2047) ?
	       8'd255 :
	       _theResult___fst_exp__h426906 ;
  assign out_f_exp__h472887 =
	     (_theResult___exp__h472610 == 8'd255 &&
	      _theResult___sfd__h472611 != 23'd0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd2047) ?
	       8'd255 :
	       _theResult___fst_exp__h472601 ;
  assign out_f_sfd__h381496 =
	     (_theResult___exp__h381218 == 8'd255 &&
	      _theResult___sfd__h381219 != 23'd0) ?
	       23'd4194304 :
	       _theResult___sfd__h381219 ;
  assign out_f_sfd__h427193 =
	     (_theResult___exp__h426915 == 8'd255 &&
	      _theResult___sfd__h426916 != 23'd0) ?
	       23'd4194304 :
	       _theResult___sfd__h426916 ;
  assign out_f_sfd__h472888 =
	     (_theResult___exp__h472610 == 8'd255 &&
	      _theResult___sfd__h472611 != 23'd0) ?
	       23'd4194304 :
	       _theResult___sfd__h472611 ;
  assign out_sfd__h354718 =
	     sfdin__h354192[34] ?
	       _theResult___sfd__h354715 :
	       sfdin__h354192[56:34] ;
  assign out_sfd__h363300 =
	     _theResult___snd__h362805[34] ?
	       _theResult___sfd__h363297 :
	       _theResult___snd__h362805[56:34] ;
  assign out_sfd__h372484 =
	     sfdin__h371958[34] ?
	       _theResult___sfd__h372481 :
	       sfdin__h371958[56:34] ;
  assign out_sfd__h381120 =
	     _theResult___snd__h380595[34] ?
	       _theResult___sfd__h381117 :
	       _theResult___snd__h380595[56:34] ;
  assign out_sfd__h400415 =
	     sfdin__h399889[34] ?
	       _theResult___sfd__h400412 :
	       sfdin__h399889[56:34] ;
  assign out_sfd__h408997 =
	     _theResult___snd__h408502[34] ?
	       _theResult___sfd__h408994 :
	       _theResult___snd__h408502[56:34] ;
  assign out_sfd__h418181 =
	     sfdin__h417655[34] ?
	       _theResult___sfd__h418178 :
	       sfdin__h417655[56:34] ;
  assign out_sfd__h426817 =
	     _theResult___snd__h426292[34] ?
	       _theResult___sfd__h426814 :
	       _theResult___snd__h426292[56:34] ;
  assign out_sfd__h446110 =
	     sfdin__h445584[34] ?
	       _theResult___sfd__h446107 :
	       sfdin__h445584[56:34] ;
  assign out_sfd__h454692 =
	     _theResult___snd__h454197[34] ?
	       _theResult___sfd__h454689 :
	       _theResult___snd__h454197[56:34] ;
  assign out_sfd__h463876 =
	     sfdin__h463350[34] ?
	       _theResult___sfd__h463873 :
	       sfdin__h463350[56:34] ;
  assign out_sfd__h472512 =
	     _theResult___snd__h471987[34] ?
	       _theResult___sfd__h472509 :
	       _theResult___snd__h471987[56:34] ;
  assign out_sfd__h502189 =
	     _theResult___snd__h501481[5] ?
	       _theResult___sfd__h502186 :
	       _theResult___snd__h501481[56:5] ;
  assign out_sfd__h511840 =
	     sfdin__h511101[5] ?
	       _theResult___sfd__h511837 :
	       sfdin__h511101[56:5] ;
  assign out_sfd__h520624 =
	     _theResult___snd__h519886[5] ?
	       _theResult___sfd__h520621 :
	       _theResult___snd__h519886[56:5] ;
  assign out_sfd__h541042 =
	     _theResult___snd__h540334[5] ?
	       _theResult___sfd__h541039 :
	       _theResult___snd__h540334[56:5] ;
  assign out_sfd__h550693 =
	     sfdin__h549954[5] ?
	       _theResult___sfd__h550690 :
	       sfdin__h549954[56:5] ;
  assign out_sfd__h559477 =
	     _theResult___snd__h558739[5] ?
	       _theResult___sfd__h559474 :
	       _theResult___snd__h558739[56:5] ;
  assign out_sfd__h580346 =
	     _theResult___snd__h579638[5] ?
	       _theResult___sfd__h580343 :
	       _theResult___snd__h579638[56:5] ;
  assign out_sfd__h589997 =
	     sfdin__h589258[5] ?
	       _theResult___sfd__h589994 :
	       sfdin__h589258[56:5] ;
  assign out_sfd__h598781 =
	     _theResult___snd__h598043[5] ?
	       _theResult___sfd__h598778 :
	       _theResult___snd__h598043[56:5] ;
  assign pc__h713396 =
	     csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 ?
	       y_avValue_new_pc__h713188 :
	       y_avValue_new_pc__h713374 ;
  assign pend_ints__h651121 =
	     { _0_CONCAT_csrf_external_int_en_vec_3_read__1664_ETC___d12798,
	       csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3,
	       1'd0,
	       csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1,
	       1'd0 } ;
  assign po_fflags__h728951 = old_fflags1__h733714 ;
  assign po_fflags__h731598 =
	     old_fflags1__h733714 | rob$deqPort_1_deq_data[31:27] ;
  assign prv__h735894 = csrf_prv_reg ;
  assign prv__h735938 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ;
  assign q___1__h475883 =
	     64'd0 -
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64] ;
  assign r1__read_BITS_13_TO_0___h651670 =
	     { 4'd0,
	       csrf_mideleg_11_reg,
	       1'b0,
	       csrf_mideleg_9_7_reg,
	       1'b0,
	       csrf_mideleg_5_3_reg,
	       1'b0 } ;
  assign r1__read_BITS_13_TO_12___h655202 = csrf_fs_reg ;
  assign r1__read_BITS_61_TO_14___h727088 =
	     { 40'd5120,
	       csrf_tsr_reg,
	       csrf_tw_reg,
	       csrf_tvm_reg,
	       csrf_mxr_reg,
	       csrf_sum_reg,
	       csrf_mprv_reg,
	       2'd0 } ;
  assign r1__read_BIT_20___h655898 = csrf_tw_reg ;
  assign r1__read__h613051 = { r1__read__h613053, csrf_ie_vec_1 } ;
  assign r1__read__h613053 = { r1__read__h613055, 2'b0 } ;
  assign r1__read__h613055 = { r1__read__h613057, csrf_prev_ie_vec_0 } ;
  assign r1__read__h613057 = { r1__read__h613059, csrf_prev_ie_vec_1 } ;
  assign r1__read__h613059 = { r1__read__h613061, 2'b0 } ;
  assign r1__read__h613061 = { r1__read__h613063, csrf_spp_reg } ;
  assign r1__read__h613063 = { r1__read__h613065, 4'b0 } ;
  assign r1__read__h613065 = { r1__read__h613067, csrf_fs_reg } ;
  assign r1__read__h613067 = { r1__read__h613069, 2'd0 } ;
  assign r1__read__h613069 = { r1__read__h613071, 1'b0 } ;
  assign r1__read__h613071 = { r1__read__h613073, csrf_sum_reg } ;
  assign r1__read__h613073 = { r1__read__h613075, csrf_mxr_reg } ;
  assign r1__read__h613075 = { r1__read__h613077, 12'b0 } ;
  assign r1__read__h613077 = { r1__read__h613079, 2'b10 } ;
  assign r1__read__h613079 = { csrf_fs_reg == 2'b11, 29'b0 } ;
  assign r1__read__h613455 =
	     { r1__read__h613457, csrf_software_int_en_vec_1 } ;
  assign r1__read__h613457 = { r1__read__h613459, 2'b0 } ;
  assign r1__read__h613459 = { r1__read__h613461, 1'b0 } ;
  assign r1__read__h613461 = { r1__read__h613463, csrf_timer_int_en_vec_1 } ;
  assign r1__read__h613463 = { r1__read__h613465, 2'b0 } ;
  assign r1__read__h613465 = { r1__read__h613467, 1'b0 } ;
  assign r1__read__h613467 = { 54'b0, csrf_external_int_en_vec_1 } ;
  assign r1__read__h613965 = { csrf_stvec_base_hi_reg, 1'b0 } ;
  assign r1__read__h613970 = { r1__read__h613972, csrf_scounteren_tm_reg } ;
  assign r1__read__h613972 = { 61'd0, csrf_scounteren_ir_reg } ;
  assign r1__read__h613983 = { csrf_scause_interrupt_reg, 59'b0 } ;
  assign r1__read__h613989 =
	     { r1__read__h613991, csrf_software_int_pend_vec_1 } ;
  assign r1__read__h613991 = { r1__read__h613993, 2'b0 } ;
  assign r1__read__h613993 = { r1__read__h613995, 1'b0 } ;
  assign r1__read__h613995 =
	     { r1__read__h613997, csrf_timer_int_pend_vec_1 } ;
  assign r1__read__h613997 = { r1__read__h613999, 2'b0 } ;
  assign r1__read__h613999 = { r1__read__h614001, 1'b0 } ;
  assign r1__read__h614001 = { 54'b0, csrf_external_int_pend_vec_1 } ;
  assign r1__read__h614199 = { vm_mode_reg__read__h614205, 16'd0 } ;
  assign r1__read__h614222 = { r1__read__h614224, csrf_ie_vec_1 } ;
  assign r1__read__h614224 = { r1__read__h614226, 1'b0 } ;
  assign r1__read__h614226 = { r1__read__h614228, csrf_ie_vec_3 } ;
  assign r1__read__h614228 = { r1__read__h614230, csrf_prev_ie_vec_0 } ;
  assign r1__read__h614230 = { r1__read__h614232, csrf_prev_ie_vec_1 } ;
  assign r1__read__h614232 = { r1__read__h614234, 1'b0 } ;
  assign r1__read__h614234 = { r1__read__h614236, csrf_prev_ie_vec_3 } ;
  assign r1__read__h614236 = { r1__read__h614238, csrf_spp_reg } ;
  assign r1__read__h614238 = { r1__read__h614240, 2'b0 } ;
  assign r1__read__h614240 = { r1__read__h614242, csrf_mpp_reg } ;
  assign r1__read__h614242 = { r1__read__h614244, csrf_fs_reg } ;
  assign r1__read__h614244 = { r1__read__h614246, 2'd0 } ;
  assign r1__read__h614246 = { r1__read__h614248, csrf_mprv_reg } ;
  assign r1__read__h614248 = { r1__read__h614250, csrf_sum_reg } ;
  assign r1__read__h614250 = { r1__read__h614252, csrf_mxr_reg } ;
  assign r1__read__h614252 = { r1__read__h614254, csrf_tvm_reg } ;
  assign r1__read__h614254 = { r1__read__h614256, csrf_tw_reg } ;
  assign r1__read__h614256 = { r1__read__h614258, csrf_tsr_reg } ;
  assign r1__read__h614258 = { r1__read__h614260, 9'b0 } ;
  assign r1__read__h614260 = { r1__read__h614262, 2'b10 } ;
  assign r1__read__h614262 = { r1__read__h614264, 2'b10 } ;
  assign r1__read__h614264 = { csrf_fs_reg == 2'b11, 27'b0 } ;
  assign r1__read__h614347 = { r1__read__h614349, 1'b0 } ;
  assign r1__read__h614349 = { r1__read__h614351, csrf_medeleg_13_11_reg } ;
  assign r1__read__h614351 = { r1__read__h614353, 1'b0 } ;
  assign r1__read__h614353 = { 48'b0, csrf_medeleg_15_reg } ;
  assign r1__read__h614364 = { r1__read__h614366, 1'b0 } ;
  assign r1__read__h614366 = { r1__read__h614368, csrf_mideleg_5_3_reg } ;
  assign r1__read__h614368 = { r1__read__h614370, 1'b0 } ;
  assign r1__read__h614370 = { r1__read__h614372, csrf_mideleg_9_7_reg } ;
  assign r1__read__h614372 = { r1__read__h614374, 1'b0 } ;
  assign r1__read__h614374 = { 52'b0, csrf_mideleg_11_reg } ;
  assign r1__read__h614388 =
	     { r1__read__h614390, csrf_software_int_en_vec_1 } ;
  assign r1__read__h614390 = { r1__read__h614392, 1'b0 } ;
  assign r1__read__h614392 =
	     { r1__read__h614394, csrf_software_int_en_vec_3 } ;
  assign r1__read__h614394 = { r1__read__h614396, 1'b0 } ;
  assign r1__read__h614396 = { r1__read__h614398, csrf_timer_int_en_vec_1 } ;
  assign r1__read__h614398 = { r1__read__h614400, 1'b0 } ;
  assign r1__read__h614400 = { r1__read__h614402, csrf_timer_int_en_vec_3 } ;
  assign r1__read__h614402 = { r1__read__h614404, 1'b0 } ;
  assign r1__read__h614404 =
	     { r1__read__h614406, csrf_external_int_en_vec_1 } ;
  assign r1__read__h614406 = { r1__read__h614408, 1'b0 } ;
  assign r1__read__h614408 = { 52'b0, csrf_external_int_en_vec_3 } ;
  assign r1__read__h614481 = { csrf_mtvec_base_hi_reg, 1'b0 } ;
  assign r1__read__h614486 = { r1__read__h614488, csrf_mcounteren_tm_reg } ;
  assign r1__read__h614488 = { 61'd0, csrf_mcounteren_ir_reg } ;
  assign r1__read__h614499 = { csrf_mcause_interrupt_reg, 59'b0 } ;
  assign r1__read__h614505 =
	     { r1__read__h614507, csrf_software_int_pend_vec_1 } ;
  assign r1__read__h614507 = { r1__read__h614509, 1'b0 } ;
  assign r1__read__h614509 =
	     { r1__read__h614511, csrf_software_int_pend_vec_3 } ;
  assign r1__read__h614511 = { r1__read__h614513, 1'b0 } ;
  assign r1__read__h614513 =
	     { r1__read__h614515, csrf_timer_int_pend_vec_1 } ;
  assign r1__read__h614515 = { r1__read__h614517, 1'b0 } ;
  assign r1__read__h614517 =
	     { r1__read__h614519, csrf_timer_int_pend_vec_3 } ;
  assign r1__read__h614519 = { r1__read__h614521, 1'b0 } ;
  assign r1__read__h614521 =
	     { r1__read__h614523, csrf_external_int_pend_vec_1 } ;
  assign r1__read__h614523 = { r1__read__h614525, 1'b0 } ;
  assign r1__read__h614525 = { 52'b0, csrf_external_int_pend_vec_3 } ;
  assign r1__read__h614606 = { 4'd0, csrf_rg_tdata1_dmode } ;
  assign rVal1__h481763 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ;
  assign rVal2__h481764 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ;
  assign r___1__h475909 =
	     64'd0 -
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ;
  assign r__h614580 = csrf_software_int_pend_vec_3 ;
  assign regRenamingTable_RDY_commit_0_commit__4953_AND_ETC___d15013 =
	     regRenamingTable$RDY_commit_0_commit && rob$RDY_deqPort_0_deq &&
	     rob$RDY_deqPort_0_deq_data &&
	     v_f_to_TV_0$FULL_N &&
	     fetchStage$iTlbIfc_noPendingReq &&
	     coreFix_memExe_dTlb$noPendingReq &&
	     NOT_rob_deqPort_0_deq_data__4354_BITS_329_TO_3_ETC___d15008 ;
  assign regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13956 =
	     regRenamingTable$RDY_rename_0_getRename &&
	     CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 &&
	     (fetchStage$pipelines_0_first[199:195] == 5'd14 ||
	      coreFix_memExe_rsMem$RDY_enq) ;
  assign regRenamingTable_RDY_rename_1_getRename__4019__ETC___d14037 =
	     regRenamingTable$RDY_rename_1_getRename &&
	     (!fetchStage$pipelines_0_canDeq ||
	      NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14022) &&
	     _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d14035 ;
  assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444 =
	     regRenamingTable$rename_0_canRename &&
	     fetchStage$pipelines_0_first[199:195] != 5'd0 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd21 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd17 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd18 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd13 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd16 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd15 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd19 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd20 &&
	     NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13442 ;
  assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 =
	     regRenamingTable$rename_0_canRename &&
	     fetchStage$pipelines_0_first[199:195] != 5'd0 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd21 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd17 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd18 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd13 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd16 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd15 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd19 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd20 &&
	     NOT_fetchStage_pipelines_0_first__2757_BIT_68__ETC___d13492 ;
  assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d13508 =
	     regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 &&
	     IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 &&
	     fetchStage$pipelines_0_first[194:192] == 3'd1 ||
	     !specTagManager$canClaim ;
  assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d13838 =
	     regRenamingTable_rename_0_canRename__3418_AND__ETC___d13494 &&
	     fetchStage$pipelines_0_first[194:192] == 3'd2 &&
	     IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 ||
	     !coreFix_memExe_rsMem$canEnq ||
	     CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ;
  assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d13985 =
	     regRenamingTable$rename_0_canRename &&
	     !checkForException___d13008[4] &&
	     rob$enqPort_0_canEnq &&
	     IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13983 &&
	     fetchStage$pipelines_0_first[194:192] == 3'd1 ;
  assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14127 =
	     regRenamingTable$rename_0_canRename &&
	     !checkForException___d13008[4] &&
	     rob$enqPort_0_canEnq &&
	     (fetchStage$pipelines_0_first[194:192] == 3'd3 ||
	      fetchStage$pipelines_0_first[194:192] == 3'd4) &&
	     coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ;
  assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14133 =
	     regRenamingTable$rename_0_canRename &&
	     !checkForException___d13008[4] &&
	     rob$enqPort_0_canEnq &&
	     fetchStage$pipelines_0_first[194:192] == 3'd2 &&
	     coreFix_memExe_rsMem$canEnq &&
	     IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd14 ;
  assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14153 =
	     regRenamingTable$rename_0_canRename &&
	     !checkForException___d13008[4] &&
	     rob$enqPort_0_canEnq &&
	     fetchStage$pipelines_0_first[194:192] == 3'd2 &&
	     coreFix_memExe_rsMem$canEnq &&
	     IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 &&
	     (fetchStage$pipelines_0_first[191:189] == 3'd0 ||
	      fetchStage$pipelines_0_first[191:189] == 3'd2) ;
  assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14161 =
	     regRenamingTable$rename_0_canRename &&
	     !checkForException___d13008[4] &&
	     rob$enqPort_0_canEnq &&
	     fetchStage$pipelines_0_first[194:192] == 3'd2 &&
	     coreFix_memExe_rsMem$canEnq &&
	     IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 &&
	     fetchStage$pipelines_0_first[191:189] != 3'd0 &&
	     fetchStage$pipelines_0_first[191:189] != 3'd2 ;
  assign regRenamingTable_rename_0_canRename__3418_AND__ETC___d14309 =
	     regRenamingTable$rename_0_canRename &&
	     !checkForException___d13008[4] &&
	     rob$enqPort_0_canEnq &&
	     fetchStage$pipelines_0_first[194:192] == 3'd2 &&
	     IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 ;
  assign regRenamingTable_rename_1_canRename__3545_AND__ETC___d13753 =
	     regRenamingTable$rename_1_canRename &&
	     fetchStage$pipelines_1_first[199:195] != 5'd0 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd21 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd17 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd18 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd13 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd16 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd15 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd19 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd20 &&
	     NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13751 ;
  assign regRenamingTable_rename_1_canRename__3545_AND__ETC___d13895 =
	     regRenamingTable$rename_1_canRename &&
	     fetchStage$pipelines_1_first[199:195] != 5'd0 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd21 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd17 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd18 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd13 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd16 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd15 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd19 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd20 &&
	     NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13893 ;
  assign regRenamingTable_rename_1_canRename__3545_AND__ETC___d13913 =
	     regRenamingTable$rename_1_canRename &&
	     fetchStage$pipelines_1_first[199:195] != 5'd0 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd21 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd17 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd18 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd13 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd16 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd15 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd19 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd20 &&
	     NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13911 ;
  assign regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219 =
	     regRenamingTable$rename_1_canRename &&
	     fetchStage$pipelines_1_first[199:195] != 5'd0 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd21 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd17 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd18 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd13 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd16 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd15 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd19 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd20 &&
	     NOT_fetchStage_pipelines_1_first__2766_BIT_68__ETC___d14217 ;
  assign regRenamingTable_rename_1_canRename__3545_AND__ETC___d14263 =
	     regRenamingTable_rename_1_canRename__3545_AND__ETC___d14219 &&
	     (fetchStage$pipelines_1_first[194:192] == 3'd3 ||
	      fetchStage$pipelines_1_first[194:192] == 3'd4) &&
	     (!fetchStage$pipelines_0_canDeq ||
	      !regRenamingTable$rename_0_canRename ||
	      renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935 ||
	      fetchStage$pipelines_0_first[194:192] != 3'd3 &&
	      fetchStage$pipelines_0_first[194:192] != 3'd4) &&
	     coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ;
  assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_N_ETC___d13068 =
	     renameStage_rg_m_halt_req[4] ||
	     !fetchStage$pipelines_0_first[68] &&
	     (IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] ||
	      IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] ||
	      IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] ||
	      IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] ||
	      IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] ||
	      IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] ||
	      IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] ||
	      IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] ||
	      IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] ||
	      IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] ||
	      IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[10] ||
	      IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[11] ||
	      IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[12] ||
	      IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] ||
	      IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] ||
	      IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15]) ;
  assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_N_ETC___d13299 =
	     renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_N_ETC___d13068 ||
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 :
		IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159) ==
	     4'd3 ;
  assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13774 =
	     renameStage_rg_m_halt_req[4] ||
	     fetchStage$pipelines_0_first[68] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13771 ||
	     !rob$enqPort_0_canEnq ||
	     !epochManager$checkEpoch_0_check ;
  assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13814 =
	     renameStage_rg_m_halt_req[4] ||
	     fetchStage$pipelines_1_first[68] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13808 ||
	     !rob$enqPort_1_canEnq ||
	     !epochManager$checkEpoch_1_check ||
	     csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13513 ;
  assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855 =
	     renameStage_rg_m_halt_req[4] ||
	     fetchStage$pipelines_0_first[68] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[10] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[11] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[12] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] ||
	     IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] ;
  assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13935 =
	     renameStage_rg_m_halt_req[4] ||
	     fetchStage$pipelines_0_first[68] ||
	     checkForException___d13008[4] ||
	     !rob$enqPort_0_canEnq ;
  assign renaming_spec_bits__h686248 =
	     fetchStage$pipelines_0_canDeq ?
	       y_avValue_fst__h682643 :
	       specTagManager$currentSpecBits ;
  assign res_data__h337871 = { 32'hFFFFFFFF, x__h337886 } ;
  assign res_data__h337876 =
	     { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
		52'd0) &&
	       coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[33] ^
	       coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68],
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
		11'd2047 &&
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		52'd0) ?
		 63'h7FF8000000000000 :
		 coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ;
  assign res_data__h383573 = { 32'hFFFFFFFF, x__h383588 } ;
  assign res_data__h383578 =
	     { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
		52'd0) &&
	       coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[33] ^
	       coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68],
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
		11'd2047 &&
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		52'd0) ?
		 63'h7FF8000000000000 :
		 coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ;
  assign res_data__h429268 = { 32'hFFFFFFFF, x__h429283 } ;
  assign res_data__h429273 =
	     { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
		52'd0) &&
	       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[33] ^
	       coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68],
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
		11'd2047 &&
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		52'd0) ?
		 63'h7FF8000000000000 :
		 coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ;
  assign res_fflags__h337872 =
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] |
	     coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] |
	     { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5202,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5213,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5229,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5242,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5255 } ;
  assign res_fflags__h383574 =
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] |
	     coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] |
	     { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6594,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6605,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6621,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6634,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6647 } ;
  assign res_fflags__h429269 =
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] |
	     coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] |
	     { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7986,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7997,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8013,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8026,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8039 } ;
  assign resp_addr__h291973 =
	     { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ;
  assign result__h364339 =
	     { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558[56:1],
	       _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558[0] |
	       guard__h364334 } ;
  assign result__h410036 =
	     { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950[56:1],
	       _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950[0] |
	       guard__h410031 } ;
  assign result__h455731 =
	     { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342[56:1],
	       _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342[0] |
	       guard__h455726 } ;
  assign result__h503484 =
	     { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8653[56:1],
	       _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8653[0] |
	       guard__h503479 } ;
  assign result__h542337 =
	     { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10138[56:1],
	       _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10138[0] |
	       guard__h542332 } ;
  assign result__h581641 =
	     { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9368[56:1],
	       _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9368[0] |
	       guard__h581636 } ;
  assign result__h646700 = w__h646695 & y__h646729 ;
  assign result__h646751 = ~x__h646750 ;
  assign rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15738 =
	     rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs &&
	     !update_vm_info &&
	     fetchStage$iTlbIfc_flush_done &&
	     coreFix_memExe_dTlb$flush_done &&
	     !flush_caches ;
  assign rg_tdata1__read__h612208 =
	     { r1__read__h614606, csrf_rg_tdata1_data } ;
  assign rob_RDY_enqPort_1_enq__4085_AND_NOT_fetchStage_ETC___d14093 =
	     rob$RDY_enqPort_1_enq &&
	     (!fetchStage$pipelines_0_canDeq ||
	      NOT_specTagManager_canClaim__3416_3507_OR_NOT__ETC___d14089) &&
	     (fetchStage$pipelines_1_first[194:192] != 3'd1 ||
	      specTagManager$RDY_claimSpecTag) ;
  assign rob_deqPort_0_deq_data__4354_BITS_161_TO_98_43_ETC___d15324 =
	     { rob$deqPort_0_deq_data[161:98],
	       (rob$deqPort_0_deq_data[329:325] != 5'd13 &&
		rob$deqPort_0_deq_data[97:96] == 2'd0) ?
		 { 2'd0, rob$deqPort_0_deq_data[95:32] } :
		 ((rob$deqPort_0_deq_data[329:325] != 5'd13 &&
		   rob$deqPort_0_deq_data[97:96] == 2'd1) ?
		    { 2'd1, rob$deqPort_0_deq_data[95:32] } :
		    { 2'd2,
		      (rob$deqPort_0_deq_data[329:325] == 5'd13) ?
			data_warl_xformed__h723426 :
			rob$deqPort_0_deq_data[95:32] }),
	       5'h0A,
	       rob$deqPort_0_deq_data[26],
	       x__h727020,
	       x_prv__h724014,
	       64'hAAAAAAAAAAAAAAAA,
	       x__h727161,
	       128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
  assign rob_deqPort_0_deq_data__4354_BIT_166_4370_CONC_ETC___d14419 =
	     { rob$deqPort_0_deq_data[166],
	       rob$deqPort_0_deq_data[166] ?
		 CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 :
		 CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 } ;
  assign rob_deqPort_0_deq_data__4354_BIT_181_4429_CONC_ETC___d14520 =
	     { rob$deqPort_0_deq_data[181],
	       CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 } ;
  assign robdeqPort_0_deq_data_BITS_95_TO_32__q245 =
	     rob$deqPort_0_deq_data[95:32] ;
  assign rs1__h655333 =
	     (fetchStage$pipelines_0_first[88] &&
	      !fetchStage$pipelines_0_first[87]) ?
	       fetchStage$pipelines_0_first[86:82] :
	       5'd0 ;
  assign satp_csr__read__h610081 = { r1__read__h614199, csrf_ppn_reg } ;
  assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8294 =
	     (sbCons$lazyLookup_2_get[2] ||
	      IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8250 &&
	      IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8267) &&
	     (sbCons$lazyLookup_2_get[1] ||
	      IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8274 &&
	      IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8291) ;
  assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8295 =
	     (sbCons$lazyLookup_2_get[3] ||
	      IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8217 &&
	      IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8243) &&
	     sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8294 ;
  assign sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1632 =
	     (sbCons$lazyLookup_3_get[3] ||
	      IF_coreFix_memExe_dispToRegQ_RDY_first__549_AN_ETC___d1579 &&
	      IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1605) &&
	     (sbCons$lazyLookup_3_get[2] ||
	      IF_coreFix_memExe_dispToRegQ_RDY_first__549_AN_ETC___d1612 &&
	      IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1629) ;
  assign sbIdx__h157153 =
	     coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ?
	       (CAN_FIRE_RL_coreFix_memExe_doIssueSB ?
		  coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] :
		  coreFix_memExe_reqStQ_data_0_rl[65:64]) :
	       2'd0 ;
  assign scause_csr__read__h609878 =
	     { r1__read__h613983, csrf_scause_code_reg } ;
  assign scounteren_csr__read__h609740 =
	     { r1__read__h613970, csrf_scounteren_cy_reg } ;
  assign sfd__h338482 = { value__h346709, 3'd0 } ;
  assign sfd__h354290 =
	     { 1'b0,
	       _theResult___fst_exp__h354198 != 8'd0,
	       sfdin__h354192[56:34] } +
	     25'd1 ;
  assign sfd__h362872 =
	     { 1'b0,
	       _theResult___fst_exp__h362854 != 8'd0,
	       _theResult___snd__h362805[56:34] } +
	     25'd1 ;
  assign sfd__h372056 =
	     { 1'b0,
	       _theResult___fst_exp__h371964 != 8'd0,
	       sfdin__h371958[56:34] } +
	     25'd1 ;
  assign sfd__h380668 =
	     { 1'b0,
	       _theResult___fst_exp__h380649 != 8'd0,
	       _theResult___snd__h380595[56:34] } +
	     25'd1 ;
  assign sfd__h384184 = { value__h392406, 3'd0 } ;
  assign sfd__h399987 =
	     { 1'b0,
	       _theResult___fst_exp__h399895 != 8'd0,
	       sfdin__h399889[56:34] } +
	     25'd1 ;
  assign sfd__h408569 =
	     { 1'b0,
	       _theResult___fst_exp__h408551 != 8'd0,
	       _theResult___snd__h408502[56:34] } +
	     25'd1 ;
  assign sfd__h417753 =
	     { 1'b0,
	       _theResult___fst_exp__h417661 != 8'd0,
	       sfdin__h417655[56:34] } +
	     25'd1 ;
  assign sfd__h426365 =
	     { 1'b0,
	       _theResult___fst_exp__h426346 != 8'd0,
	       _theResult___snd__h426292[56:34] } +
	     25'd1 ;
  assign sfd__h429879 = { value__h438101, 3'd0 } ;
  assign sfd__h445682 =
	     { 1'b0,
	       _theResult___fst_exp__h445590 != 8'd0,
	       sfdin__h445584[56:34] } +
	     25'd1 ;
  assign sfd__h454264 =
	     { 1'b0,
	       _theResult___fst_exp__h454246 != 8'd0,
	       _theResult___snd__h454197[56:34] } +
	     25'd1 ;
  assign sfd__h463448 =
	     { 1'b0,
	       _theResult___fst_exp__h463356 != 8'd0,
	       sfdin__h463350[56:34] } +
	     25'd1 ;
  assign sfd__h472060 =
	     { 1'b0,
	       _theResult___fst_exp__h472041 != 8'd0,
	       _theResult___snd__h471987[56:34] } +
	     25'd1 ;
  assign sfd__h482504 = { value__h487087, 32'd0 } ;
  assign sfd__h501548 =
	     { 1'b0,
	       _theResult___fst_exp__h501530 != 11'd0,
	       _theResult___snd__h501481[56:5] } +
	     54'd1 ;
  assign sfd__h511199 =
	     { 1'b0,
	       _theResult___fst_exp__h511107 != 11'd0,
	       sfdin__h511101[56:5] } +
	     54'd1 ;
  assign sfd__h519959 =
	     { 1'b0,
	       _theResult___fst_exp__h519940 != 11'd0,
	       _theResult___snd__h519886[56:5] } +
	     54'd1 ;
  assign sfd__h521498 = { value__h525940, 32'd0 } ;
  assign sfd__h540401 =
	     { 1'b0,
	       _theResult___fst_exp__h540383 != 11'd0,
	       _theResult___snd__h540334[56:5] } +
	     54'd1 ;
  assign sfd__h550052 =
	     { 1'b0,
	       _theResult___fst_exp__h549960 != 11'd0,
	       sfdin__h549954[56:5] } +
	     54'd1 ;
  assign sfd__h558812 =
	     { 1'b0,
	       _theResult___fst_exp__h558793 != 11'd0,
	       _theResult___snd__h558739[56:5] } +
	     54'd1 ;
  assign sfd__h560802 = { value__h565244, 32'd0 } ;
  assign sfd__h579705 =
	     { 1'b0,
	       _theResult___fst_exp__h579687 != 11'd0,
	       _theResult___snd__h579638[56:5] } +
	     54'd1 ;
  assign sfd__h589356 =
	     { 1'b0,
	       _theResult___fst_exp__h589264 != 11'd0,
	       sfdin__h589258[56:5] } +
	     54'd1 ;
  assign sfd__h598116 =
	     { 1'b0,
	       _theResult___fst_exp__h598097 != 11'd0,
	       _theResult___snd__h598043[56:5] } +
	     54'd1 ;
  assign sfdin__h354192 =
	     _theResult____h346087[56] ?
	       _theResult___snd__h354209 :
	       _theResult___snd__h354220 ;
  assign sfdin__h371958 =
	     _theResult____h363726[56] ?
	       _theResult___snd__h371975 :
	       _theResult___snd__h371986 ;
  assign sfdin__h399889 =
	     _theResult____h391786[56] ?
	       _theResult___snd__h399906 :
	       _theResult___snd__h399917 ;
  assign sfdin__h417655 =
	     _theResult____h409423[56] ?
	       _theResult___snd__h417672 :
	       _theResult___snd__h417683 ;
  assign sfdin__h445584 =
	     _theResult____h437481[56] ?
	       _theResult___snd__h445601 :
	       _theResult___snd__h445612 ;
  assign sfdin__h463350 =
	     _theResult____h455118[56] ?
	       _theResult___snd__h463367 :
	       _theResult___snd__h463378 ;
  assign sfdin__h511101 =
	     _theResult____h502871[56] ?
	       _theResult___snd__h511118 :
	       _theResult___snd__h511129 ;
  assign sfdin__h549954 =
	     _theResult____h541724[56] ?
	       _theResult___snd__h549971 :
	       _theResult___snd__h549982 ;
  assign sfdin__h589258 =
	     _theResult____h581028[56] ?
	       _theResult___snd__h589275 :
	       _theResult___snd__h589286 ;
  assign shiftData__h181569 =
	     coreFix_memExe_regToExeQ$first[75:12] << x__h181701 ;
  assign sie_csr__read__h609644 = { r1__read__h613455, 1'b0 } ;
  assign sip_csr__read__h610018 = { r1__read__h613989, 1'b0 } ;
  assign spec_bits__h689407 = specTagManager$currentSpecBits | y__h689420 ;
  assign sstatus_csr__read__h609574 = { r1__read__h613051, csrf_ie_vec_0 } ;
  assign stvec_csr__read__h609687 =
	     { r1__read__h613965, csrf_stvec_mode_low_reg } ;
  assign trap_val__h710453 =
	     commitStage_commitTrap[36] ? 64'd0 : trap_val__h711491 ;
  assign tsr_val__h727281 = csrf_tsr_reg ;
  assign tvm_val__h727283 = csrf_tvm_reg ;
  assign upd__h3994 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst ?
	       MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 :
	       MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 ;
  assign upd__h5311 = n__read__h6761 + 64'd1 ;
  assign upd__h6875 =
	     MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[63:0] :
	       rob$deqPort_0_deq_data[95:32] ;
  assign upd__h727778 =
	     MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 ?
	       f_csr_reqs$D_OUT[63:0] :
	       rob$deqPort_0_deq_data[95:32] ;
  assign v__h295943 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031) ?
	       v__h296174 :
	       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ;
  assign v__h296174 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
	      3'd7) ?
	       3'd0 :
	       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP +
	       3'd1 ;
  assign v__h299288 =
	     (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3138) ?
	       v__h299806 :
	       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ;
  assign v__h299806 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ;
  assign v__h309802 =
	     (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3309) ?
	       v__h310033 :
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ;
  assign v__h310033 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ;
  assign v__h313678 =
	     (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3405) ?
	       v__h313909 :
	       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ;
  assign v__h313909 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ;
  assign v__h328279 =
	     (coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3634) ?
	       v__h328510 :
	       coreFix_memExe_memRespLdQ_enqP ;
  assign v__h328510 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ;
  assign v__h331504 =
	     (coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3728) ?
	       v__h331735 :
	       coreFix_memExe_forwardQ_enqP ;
  assign v__h331735 = coreFix_memExe_forwardQ_enqP + 1'd1 ;
  assign v__h603885 =
	     coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ?
	       v__h603895 :
	       coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ;
  assign v__h603895 =
	     coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ;
  assign v__h604530 = v__h603885 - 2'd1 ;
  assign v__h607936 =
	     sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h608842 ;
  assign v__h632823 =
	     sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h633576 ;
  assign value__h346709 =
	     { 1'b0,
	       coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
	       11'd0,
	       coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ;
  assign value__h392406 =
	     { 1'b0,
	       coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
	       11'd0,
	       coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ;
  assign value__h438101 =
	     { 1'b0,
	       coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
	       11'd0,
	       coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ;
  assign value__h487087 = { 1'b0, f1_exp__h482142 != 8'd0, f1_sfd__h482143 } ;
  assign value__h525940 = { 1'b0, f2_exp__h521136 != 8'd0, f2_sfd__h521137 } ;
  assign value__h565244 = { 1'b0, f3_exp__h560440 != 8'd0, f3_sfd__h560441 } ;
  assign vm_mode_reg__read__h614205 = { csrf_vm_mode_sv39_reg, 3'b0 } ;
  assign w__h646695 =
	     coreFix_globalSpecUpdate_correctSpecTag_0$whas ?
	       result__h646751 :
	       12'd4095 ;
  assign x__h153727 =
	     coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_reqLdQ_data_0_lat_0$whas ?
		  coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] :
		  coreFix_memExe_reqLdQ_data_0_rl[68:64]) :
	       5'd0 ;
  assign x__h153733 =
	     coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_reqLdQ_data_0_lat_0$whas ?
		  coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] :
		  coreFix_memExe_reqLdQ_data_0_rl[63:0]) :
	       64'd0 ;
  assign x__h157274 = { 3'd0, sbIdx__h157153 } ;
  assign x__h157280 =
	     coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ?
	       (CAN_FIRE_RL_coreFix_memExe_doIssueSB ?
		  coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] :
		  coreFix_memExe_reqStQ_data_0_rl[63:0]) :
	       64'd0 ;
  assign x__h160090 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		  coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[152:148] :
		  coreFix_memExe_reqLrScAmoQ_data_0_rl[152:148]) :
	       5'd0 ;
  assign x__h160094 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		  coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[147:84] :
		  coreFix_memExe_reqLrScAmoQ_data_0_rl[147:84]) :
	       64'd0 ;
  assign x__h161942 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		  coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[70:7] :
		  coreFix_memExe_reqLrScAmoQ_data_0_rl[70:7]) :
	       64'd0 ;
  assign x__h181478 =
	     sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h180566 ;
  assign x__h181479 =
	     sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h181172 ;
  assign x__h181701 = { x__h183904[2:0], 3'b0 } ;
  assign x__h18387 =
	     mmio_dataReqQ_enqReq_lat_0$whas ?
	       mmio_dataReqQ_enqReq_lat_0$wget[141:78] :
	       mmio_dataReqQ_enqReq_rl[141:78] ;
  assign x__h183904 =
	     coreFix_memExe_regToExeQ$first[139:76] +
	     { {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10[31]}},
	       coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10 } ;
  assign x__h193681 =
	     coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ?
	       curData__h192918[63:32] :
	       curData__h192918[31:0] ;
  assign x__h20925 =
	     mmio_dataReqQ_enqReq_lat_0$whas ?
	       mmio_dataReqQ_enqReq_lat_0$wget[63:0] :
	       mmio_dataReqQ_enqReq_rl[63:0] ;
  assign x__h287281 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] :
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) :
	       5'd0 ;
  assign x__h287293 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] :
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) :
	       64'd0 ;
  assign x__h289147 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] :
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) :
	       64'd0 ;
  assign x__h302153 =
	     EN_dCacheToParent_fromP_enq ?
	       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] :
	       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ;
  assign x__h337886 =
	     { (_theResult___exp__h381218 != 8'd255 ||
		_theResult___sfd__h381219 == 23'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5140,
	       out_f_exp__h381495,
	       out_f_sfd__h381496 } ;
  assign x__h364436 =
	     sfd__h338482 << (x__h364469[11] ? 12'hAAA : x__h364469) ;
  assign x__h364469 =
	     12'd57 -
	     _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554 ;
  assign x__h383588 =
	     { (_theResult___exp__h426915 != 8'd255 ||
		_theResult___sfd__h426916 == 23'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6532,
	       out_f_exp__h427192,
	       out_f_sfd__h427193 } ;
  assign x__h410133 =
	     sfd__h384184 << (x__h410166[11] ? 12'hAAA : x__h410166) ;
  assign x__h410166 =
	     12'd57 -
	     _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946 ;
  assign x__h429283 =
	     { (_theResult___exp__h472610 != 8'd255 ||
		_theResult___sfd__h472611 == 23'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7924,
	       out_f_exp__h472887,
	       out_f_sfd__h472888 } ;
  assign x__h455828 =
	     sfd__h429879 << (x__h455861[11] ? 12'hAAA : x__h455861) ;
  assign x__h455861 =
	     12'd57 -
	     _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338 ;
  assign x__h46294 =
	     mmio_cRqQ_enqReq_lat_0$whas ?
	       mmio_cRqQ_enqReq_lat_0$wget[141:78] :
	       mmio_cRqQ_enqReq_rl[141:78] ;
  assign x__h481672 =
	     sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h478808 ;
  assign x__h481673 =
	     sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h479416 ;
  assign x__h481674 =
	     sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h480018 ;
  assign x__h48830 =
	     mmio_cRqQ_enqReq_lat_0$whas ?
	       mmio_cRqQ_enqReq_lat_0$wget[63:0] :
	       mmio_cRqQ_enqReq_rl[63:0] ;
  assign x__h503579 = sfd__h482504 << x__h503612 ;
  assign x__h503612 =
	     12'd57 -
	     _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8649 ;
  assign x__h542432 = sfd__h521498 << x__h542465 ;
  assign x__h542465 =
	     12'd57 -
	     _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10134 ;
  assign x__h581736 = sfd__h560802 << x__h581769 ;
  assign x__h581769 =
	     12'd57 -
	     _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9364 ;
  assign x__h603386 = a__h602950[63] ^ b__h602951[63] ;
  assign x__h613036 = { csrf_frm_reg, csrf_fflags_reg } ;
  assign x__h617237 =
	     coreFix_aluExe_1_dispToRegQ$first[131] ?
	       rVal1__h609052 :
	       v__h607936 ;
  assign x__h617238 =
	     sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h615062 ;
  assign x__h639746 =
	     coreFix_aluExe_0_dispToRegQ$first[131] ?
	       rVal1__h633784 :
	       v__h632823 ;
  assign x__h639747 =
	     sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h637581 ;
  assign x__h646699 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ;
  assign x__h646750 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ;
  assign x__h703386 =
	     (!rob$deqPort_0_deq_data[166] &&
	      (rob$deqPort_0_deq_data[165:162] == 4'd1 ||
	       rob$deqPort_0_deq_data[165:162] == 4'd12)) ?
	       rob$deqPort_0_deq_data[161:98] :
	       rob$deqPort_0_deq_data[95:32] ;
  assign x__h713427 = { cause_code__h710452, 2'b0 } ;
  assign x__h715654 =
	     { csrf_fs_reg == 2'b11,
	       IF_csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_c_ETC___d14935 } ;
  assign x__h715846 =
	     { commitStage_commitTrap[36], 59'b0, cause_code__h710452 } ;
  assign x__h723556 = { 1'b0, csrf_spp_reg } ;
  assign x__h727020 =
	     { 1'b1,
	       r1__read_BITS_61_TO_14___h727088,
	       2'b11,
	       csrf_mpp_reg,
	       2'b0,
	       csrf_spp_reg,
	       csrf_prev_ie_vec_3,
	       1'b0,
	       csrf_prev_ie_vec_1,
	       csrf_prev_ie_vec_0,
	       csrf_ie_vec_3,
	       1'b0,
	       csrf_ie_vec_1,
	       csrf_ie_vec_0 } ;
  assign x__h727161 =
	     { csrf_fs_reg == 2'b11,
	       40'd5120,
	       csrf_tsr_reg,
	       csrf_tw_reg,
	       csrf_tvm_reg,
	       csrf_mxr_reg,
	       csrf_sum_reg,
	       csrf_mprv_reg,
	       2'd0,
	       csrf_fs_reg,
	       IF_rob_deqPort_0_deq_data__4354_BITS_329_TO_32_ETC___d15314 } ;
  assign x__h733741 =
	     { 1'b1,
	       y_avValue_snd_snd_snd_snd_snd_snd_snd__h733723[62:15],
	       2'b11,
	       y_avValue_snd_snd_snd_snd_snd_snd_snd__h733723[12:0] } ;
  assign x__h734491 =
	     NOT_rob_deqPort_0_canDeq__5346_5347_OR_rob_deq_ETC___d15667 ?
	       y_avValue_snd_snd_snd_fst__h734301 :
	       IF_rob_deqPort_0_canDeq__5346_THEN_IF_NOT_rob__ETC___d15692 ;
  assign x__h76239 = mmio_pRqQ_data_0[31:0] ;
  assign x_addr__h314076 =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
	       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] :
	       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ;
  assign x_data__h66088 =
	     EN_mmioToPlatform_pRq_enq ?
	       mmio_pRqQ_enqReq_lat_0$wget[31:0] :
	       mmio_pRqQ_enqReq_rl[31:0] ;
  assign x_data_imm__h677666 = fetchStage$pipelines_0_first[159:128] ;
  assign x_data_imm__h693720 = fetchStage$pipelines_1_first[159:128] ;
  assign x_decodeInfo_frm__h655017 = csrf_frm_reg ;
  assign x_prv__h713496 =
	     csrf_prv_reg_read__2787_ULE_1_4711_AND_IF_comm_ETC___d14733 ?
	       2'd1 :
	       2'd3 ;
  assign x_prv__h724014 =
	     (rob$deqPort_0_deq_data[329:325] == 5'd19) ?
	       x__h723556 :
	       csrf_mpp_reg ;
  assign x_quotient__h475198 =
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ?
	       64'hFFFFFFFFFFFFFFFF :
	       ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] &&
		 coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[9]) ?
		  q___1__h475883 :
		  coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64]) ;
  assign x_reg_ifc__read__h609483 = { 63'd0, csrf_stats_module_doStats } ;
  assign x_remainder__h475199 =
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ?
	       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[74:11] :
	       ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] &&
		 coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[8]) ?
		  r___1__h475909 :
		  coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0]) ;
  assign y__h254805 =
	     { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ;
  assign y__h646729 = ~x__h646699 ;
  assign y__h651660 =
	     { 4'd15,
	       ~csrf_mideleg_11_reg,
	       1'd1,
	       ~csrf_mideleg_9_7_reg,
	       1'd1,
	       ~csrf_mideleg_5_3_reg,
	       1'd1,
	       ~csrf_mideleg_1_0_reg } ;
  assign y__h689420 = 12'd1 << specTagManager$nextSpecTag ;
  assign y__h731435 =
	     rob$deqPort_0_canDeq ?
	       y_avValue_snd_snd_snd_snd_snd_fst__h731458 :
	       64'd0 ;
  assign y__h734250 =
	     NOT_rob_deqPort_0_canDeq__5346_5347_OR_rob_deq_ETC___d15667 ?
	       y_avValue_snd_snd_snd_snd_snd_fst__h734311 :
	       y__h731435 ;
  assign y_avValue__h180566 =
	     NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1595 ?
	       coreFix_aluExe_0_bypassWire_3$wget[63:0] :
	       IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1649 ;
  assign y_avValue__h181172 =
	     NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1622 ?
	       coreFix_aluExe_0_bypassWire_3$wget[63:0] :
	       IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1660 ;
  assign y_avValue__h478808 =
	     NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8233 ?
	       coreFix_aluExe_0_bypassWire_3$wget[63:0] :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8337 ;
  assign y_avValue__h479416 =
	     NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8260 ?
	       coreFix_aluExe_0_bypassWire_3$wget[63:0] :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8348 ;
  assign y_avValue__h480018 =
	     NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8284 ?
	       coreFix_aluExe_0_bypassWire_3$wget[63:0] :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8359 ;
  assign y_avValue__h608842 =
	     NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11369 ?
	       coreFix_aluExe_0_bypassWire_3$wget[63:0] :
	       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11775 ;
  assign y_avValue__h615062 =
	     NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11397 ?
	       coreFix_aluExe_0_bypassWire_3$wget[63:0] :
	       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11787 ;
  assign y_avValue__h633576 =
	     NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12229 ?
	       coreFix_aluExe_0_bypassWire_3$wget[63:0] :
	       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12449 ;
  assign y_avValue__h637581 =
	     NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12257 ?
	       coreFix_aluExe_0_bypassWire_3$wget[63:0] :
	       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12461 ;
  assign y_avValue_fst__h682580 =
	     (fetchStage$pipelines_0_first[194:192] == 3'd1) ?
	       spec_bits__h689407 :
	       specTagManager$currentSpecBits ;
  assign y_avValue_fst__h682609 =
	     IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 ?
	       y_avValue_fst__h682580 :
	       specTagManager$currentSpecBits ;
  assign y_avValue_fst__h682643 =
	     ((fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	       specTagManager$canClaim) &&
	      regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444) ?
	       y_avValue_fst__h682609 :
	       specTagManager$currentSpecBits ;
  assign y_avValue_fst__h730973 =
	     (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] ||
	      rob$deqPort_0_deq_data[167] ||
	      rob$deqPort_0_deq_data[329:325] == 5'd0 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd21 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd17 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd18 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd13 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd16 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd15 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd19 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd20) ?
	       5'd0 :
	       rob$deqPort_0_deq_data[31:27] ;
  assign y_avValue_fst__h734132 =
	     IF_rob_deqPort_0_canDeq__5346_THEN_IF_NOT_rob__ETC___d15673 |
	     rob$deqPort_1_deq_data[31:27] ;
  assign y_avValue_fst__h734164 =
	     (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
	      rob$deqPort_1_deq_data[167] ||
	      rob$deqPort_1_deq_data[329:325] == 5'd0 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd21 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd17 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd18 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd13 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd16 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd15 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd19 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd20) ?
	       IF_rob_deqPort_0_canDeq__5346_THEN_IF_NOT_rob__ETC___d15673 :
	       y_avValue_fst__h734132 ;
  assign y_avValue_new_pc__h713188 =
	     (csrf_stvec_mode_low_reg && commitStage_commitTrap[36]) ?
	       base__h713412 + { 58'd0, x__h713427 } :
	       base__h713412 ;
  assign y_avValue_new_pc__h713374 =
	     (csrf_mtvec_mode_low_reg && commitStage_commitTrap[36]) ?
	       base__h713432 + { 58'd0, x__h713427 } :
	       base__h713432 ;
  assign y_avValue_snd_snd_snd_fst__h731448 =
	     (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] ||
	      rob$deqPort_0_deq_data[167] ||
	      rob$deqPort_0_deq_data[329:325] == 5'd0 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd21 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd17 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd18 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd13 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd16 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd15 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd19 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd20) ?
	       2'd0 :
	       2'd1 ;
  assign y_avValue_snd_snd_snd_fst__h734301 =
	     (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
	      rob$deqPort_1_deq_data[167] ||
	      rob$deqPort_1_deq_data[329:325] == 5'd0 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd21 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd17 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd18 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd13 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd16 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd15 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd19 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd20) ?
	       IF_rob_deqPort_0_canDeq__5346_THEN_IF_NOT_rob__ETC___d15692 :
	       y_avValue_snd_snd_snd_fst__h734337 ;
  assign y_avValue_snd_snd_snd_fst__h734337 =
	     IF_rob_deqPort_0_canDeq__5346_THEN_IF_NOT_rob__ETC___d15692 +
	     2'd1 ;
  assign y_avValue_snd_snd_snd_snd_snd_fst__h731458 =
	     (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] ||
	      rob$deqPort_0_deq_data[167] ||
	      rob$deqPort_0_deq_data[329:325] == 5'd0 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd21 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd17 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd18 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd13 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd16 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd15 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd19 ||
	      rob$deqPort_0_deq_data[329:325] == 5'd20) ?
	       64'd0 :
	       64'd1 ;
  assign y_avValue_snd_snd_snd_snd_snd_fst__h734311 =
	     (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
	      rob$deqPort_1_deq_data[167] ||
	      rob$deqPort_1_deq_data[329:325] == 5'd0 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd21 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd17 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd18 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd13 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd16 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd15 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd19 ||
	      rob$deqPort_1_deq_data[329:325] == 5'd20) ?
	       y__h731435 :
	       y_avValue_snd_snd_snd_snd_snd_fst__h734347 ;
  assign y_avValue_snd_snd_snd_snd_snd_fst__h734347 = y__h731435 + 64'd1 ;
  assign y_avValue_snd_snd_snd_snd_snd_snd_snd__h733723 = x__h727020 ;
  always@(v_f_to_TV_1$D_OUT)
  begin
    case (v_f_to_TV_1$D_OUT[475:464])
      12'd1,
      12'd2,
      12'd3,
      12'd256,
      12'd260,
      12'd261,
      12'd262,
      12'd320,
      12'd321,
      12'd322,
      12'd323,
      12'd324,
      12'd384,
      12'd768,
      12'd769,
      12'd770,
      12'd771,
      12'd772,
      12'd773,
      12'd774,
      12'd832,
      12'd833,
      12'd834,
      12'd835,
      12'd836,
      12'd1952,
      12'd1953,
      12'd1954,
      12'd1955,
      12'd1968,
      12'd1969,
      12'd1970,
      12'd1971,
      12'd2048,
      12'd2049,
      12'd2816,
      12'd2818,
      12'd3072,
      12'd3073,
      12'd3074,
      12'd3857,
      12'd3858,
      12'd3859,
      12'd3860:
	  CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1 =
	      v_f_to_TV_1$D_OUT[475:464];
      default: CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1 =
		   12'd2303;
    endcase
  end
  always@(v_f_to_TV_1$D_OUT)
  begin
    case (v_f_to_TV_1$D_OUT[461:458])
      4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
	  CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q2 =
	      v_f_to_TV_1$D_OUT[461:458];
      default: CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q2 = 4'd15;
    endcase
  end
  always@(v_f_to_TV_1$D_OUT)
  begin
    case (v_f_to_TV_1$D_OUT[461:458])
      4'd0,
      4'd1,
      4'd2,
      4'd3,
      4'd4,
      4'd5,
      4'd6,
      4'd7,
      4'd8,
      4'd9,
      4'd11,
      4'd12,
      4'd13:
	  CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q3 =
	      v_f_to_TV_1$D_OUT[461:458];
      default: CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q3 = 4'd15;
    endcase
  end
  always@(v_f_to_TV_1$D_OUT)
  begin
    case (v_f_to_TV_1$D_OUT[393:392])
      2'd0, 2'd1:
	  CASE_v_f_to_TV_1D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q4 =
	      v_f_to_TV_1$D_OUT[393:392];
      default: CASE_v_f_to_TV_1D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q4 = 2'd2;
    endcase
  end
  always@(v_f_to_TV_0$D_OUT)
  begin
    case (v_f_to_TV_0$D_OUT[475:464])
      12'd1,
      12'd2,
      12'd3,
      12'd256,
      12'd260,
      12'd261,
      12'd262,
      12'd320,
      12'd321,
      12'd322,
      12'd323,
      12'd324,
      12'd384,
      12'd768,
      12'd769,
      12'd770,
      12'd771,
      12'd772,
      12'd773,
      12'd774,
      12'd832,
      12'd833,
      12'd834,
      12'd835,
      12'd836,
      12'd1952,
      12'd1953,
      12'd1954,
      12'd1955,
      12'd1968,
      12'd1969,
      12'd1970,
      12'd1971,
      12'd2048,
      12'd2049,
      12'd2816,
      12'd2818,
      12'd3072,
      12'd3073,
      12'd3074,
      12'd3857,
      12'd3858,
      12'd3859,
      12'd3860:
	  CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5 =
	      v_f_to_TV_0$D_OUT[475:464];
      default: CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5 =
		   12'd2303;
    endcase
  end
  always@(v_f_to_TV_0$D_OUT)
  begin
    case (v_f_to_TV_0$D_OUT[461:458])
      4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
	  CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q6 =
	      v_f_to_TV_0$D_OUT[461:458];
      default: CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q6 = 4'd15;
    endcase
  end
  always@(v_f_to_TV_0$D_OUT)
  begin
    case (v_f_to_TV_0$D_OUT[461:458])
      4'd0,
      4'd1,
      4'd2,
      4'd3,
      4'd4,
      4'd5,
      4'd6,
      4'd7,
      4'd8,
      4'd9,
      4'd11,
      4'd12,
      4'd13:
	  CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q7 =
	      v_f_to_TV_0$D_OUT[461:458];
      default: CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q7 = 4'd15;
    endcase
  end
  always@(v_f_to_TV_0$D_OUT)
  begin
    case (v_f_to_TV_0$D_OUT[393:392])
      2'd0, 2'd1:
	  CASE_v_f_to_TV_0D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q8 =
	      v_f_to_TV_0$D_OUT[393:392];
      default: CASE_v_f_to_TV_0D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q8 = 2'd2;
    endcase
  end
  always@(mmio_cRqQ_data_0)
  begin
    case (mmio_cRqQ_data_0[77:76])
      2'd0, 2'd1, 2'd2:
	  CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9 =
	      mmio_cRqQ_data_0[77:72];
      2'd3:
	  CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9 =
	      { 2'd3, mmio_cRqQ_data_0[75:72] };
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87])
      3'd0:
	  x__h197128 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0];
      3'd1:
	  x__h197128 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64];
      3'd2:
	  x__h197128 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128];
      3'd3:
	  x__h197128 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192];
      3'd4:
	  x__h197128 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256];
      3'd5:
	  x__h197128 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320];
      3'd6:
	  x__h197128 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384];
      3'd7:
	  x__h197128 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 or
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 or
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 or
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 or
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 or
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 or
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP)
      3'd0:
	  x__h285848 =
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0;
      3'd1:
	  x__h285848 =
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1;
      3'd2:
	  x__h285848 =
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2;
      3'd3:
	  x__h285848 =
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3;
      3'd4:
	  x__h285848 =
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4;
      3'd5:
	  x__h285848 =
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5;
      3'd6:
	  x__h285848 =
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6;
      3'd7:
	  x__h285848 =
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7;
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  addr__h290069 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518];
      1'd1:
	  addr__h290069 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91])
      3'd0:
	  curData__h192918 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0];
      3'd1:
	  curData__h192918 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64];
      3'd2:
	  curData__h192918 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128];
      3'd3:
	  curData__h192918 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192];
      3'd4:
	  curData__h192918 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256];
      3'd5:
	  curData__h192918 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320];
      3'd6:
	  curData__h192918 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384];
      3'd7:
	  curData__h192918 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448];
    endcase
  end
  always@(commitStage_commitTrap)
  begin
    case (commitStage_commitTrap[35:32])
      4'd0, 4'd3: trap_val__h711491 = commitStage_commitTrap[164:101];
      4'd2: trap_val__h711491 = { 32'd0, commitStage_commitTrap[31:0] };
      default: trap_val__h711491 =
		   (commitStage_commitTrap[35:32] != 4'd8 &&
		    commitStage_commitTrap[35:32] != 4'd9 &&
		    commitStage_commitTrap[35:32] != 4'd11) ?
		     commitStage_commitTrap[100:37] :
		     64'd0;
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  x__h291618 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0];
      1'd1:
	  x__h291618 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0];
    endcase
  end
  always@(f_csr_reqs$D_OUT or
	  fflags_csr__read__h609353 or
	  frm_csr__read__h609364 or
	  fcsr_csr__read__h609378 or
	  sstatus_csr__read__h609574 or
	  sie_csr__read__h609644 or
	  stvec_csr__read__h609687 or
	  scounteren_csr__read__h609740 or
	  csrf_sscratch_csr or
	  csrf_sepc_csr or
	  scause_csr__read__h609878 or
	  csrf_stval_csr or
	  sip_csr__read__h610018 or
	  satp_csr__read__h610081 or
	  mstatus_csr__read__h610224 or
	  medeleg_csr__read__h610372 or
	  mideleg_csr__read__h610467 or
	  mie_csr__read__h610591 or
	  mtvec_csr__read__h610673 or
	  mcounteren_csr__read__h610765 or
	  csrf_mscratch_csr or
	  csrf_mepc_csr or
	  mcause_csr__read__h611020 or
	  csrf_mtval_csr or
	  mip_csr__read__h611253 or
	  csrf_rg_tselect or
	  rg_tdata1__read__h612208 or
	  csrf_rg_tdata2 or
	  csrf_rg_tdata3 or
	  csrf_rg_dcsr or
	  csrf_rg_dpc or
	  csrf_rg_dscratch0 or
	  csrf_rg_dscratch1 or
	  x_reg_ifc__read__h609483 or
	  n__read__h611357 or n__read__h611548 or csrf_time_reg)
  begin
    case (f_csr_reqs$D_OUT[75:64])
      12'd1: data_out__h738339 = fflags_csr__read__h609353;
      12'd2: data_out__h738339 = frm_csr__read__h609364;
      12'd3: data_out__h738339 = fcsr_csr__read__h609378;
      12'd256: data_out__h738339 = sstatus_csr__read__h609574;
      12'd260: data_out__h738339 = sie_csr__read__h609644;
      12'd261: data_out__h738339 = stvec_csr__read__h609687;
      12'd262: data_out__h738339 = scounteren_csr__read__h609740;
      12'd320: data_out__h738339 = csrf_sscratch_csr;
      12'd321: data_out__h738339 = csrf_sepc_csr;
      12'd322: data_out__h738339 = scause_csr__read__h609878;
      12'd323: data_out__h738339 = csrf_stval_csr;
      12'd324: data_out__h738339 = sip_csr__read__h610018;
      12'd384: data_out__h738339 = satp_csr__read__h610081;
      12'd768: data_out__h738339 = mstatus_csr__read__h610224;
      12'd769: data_out__h738339 = 64'h800000000014112D;
      12'd770: data_out__h738339 = medeleg_csr__read__h610372;
      12'd771: data_out__h738339 = mideleg_csr__read__h610467;
      12'd772: data_out__h738339 = mie_csr__read__h610591;
      12'd773: data_out__h738339 = mtvec_csr__read__h610673;
      12'd774: data_out__h738339 = mcounteren_csr__read__h610765;
      12'd832: data_out__h738339 = csrf_mscratch_csr;
      12'd833: data_out__h738339 = csrf_mepc_csr;
      12'd834: data_out__h738339 = mcause_csr__read__h611020;
      12'd835: data_out__h738339 = csrf_mtval_csr;
      12'd836: data_out__h738339 = mip_csr__read__h611253;
      12'd1952: data_out__h738339 = csrf_rg_tselect;
      12'd1953: data_out__h738339 = rg_tdata1__read__h612208;
      12'd1954: data_out__h738339 = csrf_rg_tdata2;
      12'd1955: data_out__h738339 = csrf_rg_tdata3;
      12'd1968: data_out__h738339 = csrf_rg_dcsr;
      12'd1969: data_out__h738339 = csrf_rg_dpc;
      12'd1970: data_out__h738339 = csrf_rg_dscratch0;
      12'd1971: data_out__h738339 = csrf_rg_dscratch1;
      12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860:
	  data_out__h738339 = 64'd0;
      12'd2049: data_out__h738339 = x_reg_ifc__read__h609483;
      12'd2816, 12'd3072: data_out__h738339 = n__read__h611357;
      12'd2818, 12'd3074: data_out__h738339 = n__read__h611548;
      12'd3073: data_out__h738339 = csrf_time_reg;
      default: data_out__h738339 = 64'b0;
    endcase
  end
  always@(coreFix_aluExe_1_dispToRegQ$first or
	  fflags_csr__read__h609353 or
	  frm_csr__read__h609364 or
	  fcsr_csr__read__h609378 or
	  sstatus_csr__read__h609574 or
	  sie_csr__read__h609644 or
	  stvec_csr__read__h609687 or
	  scounteren_csr__read__h609740 or
	  csrf_sscratch_csr or
	  csrf_sepc_csr or
	  scause_csr__read__h609878 or
	  csrf_stval_csr or
	  sip_csr__read__h610018 or
	  satp_csr__read__h610081 or
	  mstatus_csr__read__h610224 or
	  medeleg_csr__read__h610372 or
	  mideleg_csr__read__h610467 or
	  mie_csr__read__h610591 or
	  mtvec_csr__read__h610673 or
	  mcounteren_csr__read__h610765 or
	  csrf_mscratch_csr or
	  csrf_mepc_csr or
	  mcause_csr__read__h611020 or
	  csrf_mtval_csr or
	  mip_csr__read__h611253 or
	  csrf_rg_tselect or
	  rg_tdata1__read__h612208 or
	  csrf_rg_tdata2 or
	  csrf_rg_tdata3 or
	  csrf_rg_dcsr or
	  csrf_rg_dpc or
	  csrf_rg_dscratch0 or
	  csrf_rg_dscratch1 or
	  x_reg_ifc__read__h609483 or
	  n__read__h611357 or n__read__h611548 or csrf_time_reg)
  begin
    case (coreFix_aluExe_1_dispToRegQ$first[130:119])
      12'd1: rVal1__h609052 = fflags_csr__read__h609353;
      12'd2: rVal1__h609052 = frm_csr__read__h609364;
      12'd3: rVal1__h609052 = fcsr_csr__read__h609378;
      12'd256: rVal1__h609052 = sstatus_csr__read__h609574;
      12'd260: rVal1__h609052 = sie_csr__read__h609644;
      12'd261: rVal1__h609052 = stvec_csr__read__h609687;
      12'd262: rVal1__h609052 = scounteren_csr__read__h609740;
      12'd320: rVal1__h609052 = csrf_sscratch_csr;
      12'd321: rVal1__h609052 = csrf_sepc_csr;
      12'd322: rVal1__h609052 = scause_csr__read__h609878;
      12'd323: rVal1__h609052 = csrf_stval_csr;
      12'd324: rVal1__h609052 = sip_csr__read__h610018;
      12'd384: rVal1__h609052 = satp_csr__read__h610081;
      12'd768: rVal1__h609052 = mstatus_csr__read__h610224;
      12'd769: rVal1__h609052 = 64'h800000000014112D;
      12'd770: rVal1__h609052 = medeleg_csr__read__h610372;
      12'd771: rVal1__h609052 = mideleg_csr__read__h610467;
      12'd772: rVal1__h609052 = mie_csr__read__h610591;
      12'd773: rVal1__h609052 = mtvec_csr__read__h610673;
      12'd774: rVal1__h609052 = mcounteren_csr__read__h610765;
      12'd832: rVal1__h609052 = csrf_mscratch_csr;
      12'd833: rVal1__h609052 = csrf_mepc_csr;
      12'd834: rVal1__h609052 = mcause_csr__read__h611020;
      12'd835: rVal1__h609052 = csrf_mtval_csr;
      12'd836: rVal1__h609052 = mip_csr__read__h611253;
      12'd1952: rVal1__h609052 = csrf_rg_tselect;
      12'd1953: rVal1__h609052 = rg_tdata1__read__h612208;
      12'd1954: rVal1__h609052 = csrf_rg_tdata2;
      12'd1955: rVal1__h609052 = csrf_rg_tdata3;
      12'd1968: rVal1__h609052 = csrf_rg_dcsr;
      12'd1969: rVal1__h609052 = csrf_rg_dpc;
      12'd1970: rVal1__h609052 = csrf_rg_dscratch0;
      12'd1971: rVal1__h609052 = csrf_rg_dscratch1;
      12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860:
	  rVal1__h609052 = 64'd0;
      12'd2049: rVal1__h609052 = x_reg_ifc__read__h609483;
      12'd2816, 12'd3072: rVal1__h609052 = n__read__h611357;
      12'd2818, 12'd3074: rVal1__h609052 = n__read__h611548;
      12'd3073: rVal1__h609052 = csrf_time_reg;
      default: rVal1__h609052 = 64'b0;
    endcase
  end
  always@(coreFix_aluExe_0_dispToRegQ$first or
	  fflags_csr__read__h609353 or
	  frm_csr__read__h609364 or
	  fcsr_csr__read__h609378 or
	  sstatus_csr__read__h609574 or
	  sie_csr__read__h609644 or
	  stvec_csr__read__h609687 or
	  scounteren_csr__read__h609740 or
	  csrf_sscratch_csr or
	  csrf_sepc_csr or
	  scause_csr__read__h609878 or
	  csrf_stval_csr or
	  sip_csr__read__h610018 or
	  satp_csr__read__h610081 or
	  mstatus_csr__read__h610224 or
	  medeleg_csr__read__h610372 or
	  mideleg_csr__read__h610467 or
	  mie_csr__read__h610591 or
	  mtvec_csr__read__h610673 or
	  mcounteren_csr__read__h610765 or
	  csrf_mscratch_csr or
	  csrf_mepc_csr or
	  mcause_csr__read__h611020 or
	  csrf_mtval_csr or
	  mip_csr__read__h611253 or
	  csrf_rg_tselect or
	  rg_tdata1__read__h612208 or
	  csrf_rg_tdata2 or
	  csrf_rg_tdata3 or
	  csrf_rg_dcsr or
	  csrf_rg_dpc or
	  csrf_rg_dscratch0 or
	  csrf_rg_dscratch1 or
	  x_reg_ifc__read__h609483 or
	  n__read__h611357 or n__read__h611548 or csrf_time_reg)
  begin
    case (coreFix_aluExe_0_dispToRegQ$first[130:119])
      12'd1: rVal1__h633784 = fflags_csr__read__h609353;
      12'd2: rVal1__h633784 = frm_csr__read__h609364;
      12'd3: rVal1__h633784 = fcsr_csr__read__h609378;
      12'd256: rVal1__h633784 = sstatus_csr__read__h609574;
      12'd260: rVal1__h633784 = sie_csr__read__h609644;
      12'd261: rVal1__h633784 = stvec_csr__read__h609687;
      12'd262: rVal1__h633784 = scounteren_csr__read__h609740;
      12'd320: rVal1__h633784 = csrf_sscratch_csr;
      12'd321: rVal1__h633784 = csrf_sepc_csr;
      12'd322: rVal1__h633784 = scause_csr__read__h609878;
      12'd323: rVal1__h633784 = csrf_stval_csr;
      12'd324: rVal1__h633784 = sip_csr__read__h610018;
      12'd384: rVal1__h633784 = satp_csr__read__h610081;
      12'd768: rVal1__h633784 = mstatus_csr__read__h610224;
      12'd769: rVal1__h633784 = 64'h800000000014112D;
      12'd770: rVal1__h633784 = medeleg_csr__read__h610372;
      12'd771: rVal1__h633784 = mideleg_csr__read__h610467;
      12'd772: rVal1__h633784 = mie_csr__read__h610591;
      12'd773: rVal1__h633784 = mtvec_csr__read__h610673;
      12'd774: rVal1__h633784 = mcounteren_csr__read__h610765;
      12'd832: rVal1__h633784 = csrf_mscratch_csr;
      12'd833: rVal1__h633784 = csrf_mepc_csr;
      12'd834: rVal1__h633784 = mcause_csr__read__h611020;
      12'd835: rVal1__h633784 = csrf_mtval_csr;
      12'd836: rVal1__h633784 = mip_csr__read__h611253;
      12'd1952: rVal1__h633784 = csrf_rg_tselect;
      12'd1953: rVal1__h633784 = rg_tdata1__read__h612208;
      12'd1954: rVal1__h633784 = csrf_rg_tdata2;
      12'd1955: rVal1__h633784 = csrf_rg_tdata3;
      12'd1968: rVal1__h633784 = csrf_rg_dcsr;
      12'd1969: rVal1__h633784 = csrf_rg_dpc;
      12'd1970: rVal1__h633784 = csrf_rg_dscratch0;
      12'd1971: rVal1__h633784 = csrf_rg_dscratch1;
      12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860:
	  rVal1__h633784 = 64'd0;
      12'd2049: rVal1__h633784 = x_reg_ifc__read__h609483;
      12'd2816, 12'd3072: rVal1__h633784 = n__read__h611357;
      12'd2818, 12'd3074: rVal1__h633784 = n__read__h611548;
      12'd3073: rVal1__h633784 = csrf_time_reg;
      default: rVal1__h633784 = 64'b0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0, 3'd1: _theResult___fst_exp__h346069 = 8'd255;
      3'd2:
	  _theResult___fst_exp__h346069 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		8'd254 :
		8'd255;
      3'd3:
	  _theResult___fst_exp__h346069 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		8'd255 :
		8'd254;
      3'd4: _theResult___fst_exp__h346069 = 8'd254;
      default: _theResult___fst_exp__h346069 = 8'd0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0, 3'd1: _theResult___fst_sfd__h346070 = 23'd0;
      3'd2:
	  _theResult___fst_sfd__h346070 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		23'd8388607 :
		23'd0;
      3'd3:
	  _theResult___fst_sfd__h346070 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		23'd0 :
		23'd8388607;
      3'd4: _theResult___fst_sfd__h346070 = 23'd8388607;
      default: _theResult___fst_sfd__h346070 = 23'd0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0, 3'd1: _theResult___fst_exp__h391768 = 8'd255;
      3'd2:
	  _theResult___fst_exp__h391768 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		8'd254 :
		8'd255;
      3'd3:
	  _theResult___fst_exp__h391768 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		8'd255 :
		8'd254;
      3'd4: _theResult___fst_exp__h391768 = 8'd254;
      default: _theResult___fst_exp__h391768 = 8'd0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0, 3'd1: _theResult___fst_sfd__h391769 = 23'd0;
      3'd2:
	  _theResult___fst_sfd__h391769 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		23'd8388607 :
		23'd0;
      3'd3:
	  _theResult___fst_sfd__h391769 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		23'd0 :
		23'd8388607;
      3'd4: _theResult___fst_sfd__h391769 = 23'd8388607;
      default: _theResult___fst_sfd__h391769 = 23'd0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0, 3'd1: _theResult___fst_exp__h437463 = 8'd255;
      3'd2:
	  _theResult___fst_exp__h437463 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		8'd254 :
		8'd255;
      3'd3:
	  _theResult___fst_exp__h437463 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		8'd255 :
		8'd254;
      3'd4: _theResult___fst_exp__h437463 = 8'd254;
      default: _theResult___fst_exp__h437463 = 8'd0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0, 3'd1: _theResult___fst_sfd__h437464 = 23'd0;
      3'd2:
	  _theResult___fst_sfd__h437464 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		23'd8388607 :
		23'd0;
      3'd3:
	  _theResult___fst_sfd__h437464 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		23'd0 :
		23'd8388607;
      3'd4: _theResult___fst_sfd__h437464 = 23'd8388607;
      default: _theResult___fst_sfd__h437464 = 23'd0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = 11'd2046;
      3'd2:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
		11'd2047 :
		11'd2046;
      3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
		11'd2046 :
		11'd2047;
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = 11'd0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 =
	      52'hFFFFFFFFFFFFF;
      3'd2:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
		52'd0 :
		52'hFFFFFFFFFFFFF;
      3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
		52'hFFFFFFFFFFFFF :
		52'd0;
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 52'd0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd2046;
      3'd2:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
		11'd2047 :
		11'd2046;
      3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
		11'd2046 :
		11'd2047;
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 =
	      52'hFFFFFFFFFFFFF;
      3'd2:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
		52'd0 :
		52'hFFFFFFFFFFFFF;
      3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
		52'hFFFFFFFFFFFFF :
		52'd0;
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = 52'd0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = 11'd2046;
      3'd2:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
		11'd2047 :
		11'd2046;
      3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
		11'd2046 :
		11'd2047;
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = 11'd0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 =
	      52'hFFFFFFFFFFFFF;
      3'd2:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
		52'd0 :
		52'hFFFFFFFFFFFFF;
      3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
		52'hFFFFFFFFFFFFF :
		52'd0;
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 = 52'd0;
    endcase
  end
  always@(commitStage_commitTrap)
  begin
    case (commitStage_commitTrap[35:32])
      4'd0,
      4'd1,
      4'd2,
      4'd3,
      4'd4,
      4'd5,
      4'd6,
      4'd7,
      4'd8,
      4'd9,
      4'd11,
      4'd12,
      4'd13:
	  i__h710467 = commitStage_commitTrap[35:32];
      default: i__h710467 = 4'd15;
    endcase
  end
  always@(commitStage_commitTrap)
  begin
    case (commitStage_commitTrap[35:32])
      4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
	  i__h710627 = commitStage_commitTrap[35:32];
      default: i__h710627 = 4'd15;
    endcase
  end
  always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0)
  begin
    case (coreFix_memExe_lsq$firstLd[19])
      1'd0:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 =
	      coreFix_memExe_respLrScAmoQ_data_0[31:0];
      1'd1:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 =
	      coreFix_memExe_respLrScAmoQ_data_0[63:32];
    endcase
  end
  always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0)
  begin
    case (coreFix_memExe_lsq$firstLd[19:18])
      2'd0:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 =
	      coreFix_memExe_respLrScAmoQ_data_0[15:0];
      2'd1:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 =
	      coreFix_memExe_respLrScAmoQ_data_0[31:16];
      2'd2:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 =
	      coreFix_memExe_respLrScAmoQ_data_0[47:32];
      2'd3:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 =
	      coreFix_memExe_respLrScAmoQ_data_0[63:48];
    endcase
  end
  always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0)
  begin
    case (coreFix_memExe_lsq$firstLd[19:17])
      3'd0:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
	      coreFix_memExe_respLrScAmoQ_data_0[7:0];
      3'd1:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
	      coreFix_memExe_respLrScAmoQ_data_0[15:8];
      3'd2:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
	      coreFix_memExe_respLrScAmoQ_data_0[23:16];
      3'd3:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
	      coreFix_memExe_respLrScAmoQ_data_0[31:24];
      3'd4:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
	      coreFix_memExe_respLrScAmoQ_data_0[39:32];
      3'd5:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
	      coreFix_memExe_respLrScAmoQ_data_0[47:40];
      3'd6:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
	      coreFix_memExe_respLrScAmoQ_data_0[55:48];
      3'd7:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
	      coreFix_memExe_respLrScAmoQ_data_0[63:56];
    endcase
  end
  always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0)
  begin
    case (coreFix_memExe_lsq$firstLd[19])
      1'd0:
	  SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 =
	      mmio_dataRespQ_data_0[31:0];
      1'd1:
	  SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 =
	      mmio_dataRespQ_data_0[63:32];
    endcase
  end
  always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0)
  begin
    case (coreFix_memExe_lsq$firstLd[19:18])
      2'd0:
	  SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 =
	      mmio_dataRespQ_data_0[15:0];
      2'd1:
	  SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 =
	      mmio_dataRespQ_data_0[31:16];
      2'd2:
	  SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 =
	      mmio_dataRespQ_data_0[47:32];
      2'd3:
	  SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 =
	      mmio_dataRespQ_data_0[63:48];
    endcase
  end
  always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0)
  begin
    case (coreFix_memExe_lsq$firstLd[19:17])
      3'd0:
	  SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
	      mmio_dataRespQ_data_0[7:0];
      3'd1:
	  SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
	      mmio_dataRespQ_data_0[15:8];
      3'd2:
	  SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
	      mmio_dataRespQ_data_0[23:16];
      3'd3:
	  SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
	      mmio_dataRespQ_data_0[31:24];
      3'd4:
	  SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
	      mmio_dataRespQ_data_0[39:32];
      3'd5:
	  SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
	      mmio_dataRespQ_data_0[47:40];
      3'd6:
	  SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
	      mmio_dataRespQ_data_0[55:48];
      3'd7:
	  SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
	      mmio_dataRespQ_data_0[63:56];
    endcase
  end
  always@(coreFix_memExe_dTlb$procResp)
  begin
    case (coreFix_memExe_dTlb$procResp[177:175])
      3'd0, 3'd2:
	  CASE_coreFix_memExe_dTlbprocResp_BITS_177_TO__ETC__q20 = 4'd4;
      default: CASE_coreFix_memExe_dTlbprocResp_BITS_177_TO__ETC__q20 = 4'd6;
    endcase
  end
  always@(coreFix_memExe_dTlb$procResp)
  begin
    case (coreFix_memExe_dTlb$procResp[181:178])
      4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9:
	  CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q21 =
	      coreFix_memExe_dTlb$procResp[181:178];
      4'd11: CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q21 = 4'd10;
      4'd12: CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q21 = 4'd11;
      4'd13: CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q21 = 4'd12;
      default: CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q21 = 4'd13;
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2875 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[65:2];
      1'd1:
	  SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2875 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[65:2];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q22 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[514:451];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q22 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[514:451];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q23 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[450:387];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q23 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[450:387];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q24 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[386:323];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q24 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[386:323];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q25 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[322:259];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q25 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[322:259];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q26 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[258:195];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q26 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[258:195];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[194:131];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131];
    endcase
  end
  always@(guard__h354806 or
	  _theResult___fst_exp__h362854 or
	  out_exp__h363299 or _theResult___exp__h363296)
  begin
    case (guard__h354806)
      2'b0, 2'b01:
	  CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q32 =
	      _theResult___fst_exp__h362854;
      2'b10:
	  CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q32 =
	      out_exp__h363299;
      2'b11:
	  CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q32 =
	      _theResult___exp__h363296;
    endcase
  end
  always@(guard__h354806 or
	  _theResult___fst_exp__h362854 or _theResult___exp__h363296)
  begin
    case (guard__h354806)
      2'b0:
	  CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q33 =
	      _theResult___fst_exp__h362854;
      2'b01, 2'b10, 2'b11:
	  CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q33 =
	      _theResult___exp__h363296;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q32 or
	  CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q33 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4532 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4534 or
	  _theResult___fst_exp__h362854)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h363374 =
	      CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q32;
      3'd1:
	  _theResult___fst_exp__h363374 =
	      CASE_guard54806_0b0_theResult___fst_exp62854_0_ETC__q33;
      3'd2:
	  _theResult___fst_exp__h363374 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4532;
      3'd3:
	  _theResult___fst_exp__h363374 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4534;
      3'd4: _theResult___fst_exp__h363374 = _theResult___fst_exp__h362854;
      default: _theResult___fst_exp__h363374 = 8'd0;
    endcase
  end
  always@(guard__h346097 or
	  _theResult___fst_exp__h354198 or
	  out_exp__h354717 or _theResult___exp__h354714)
  begin
    case (guard__h346097)
      2'b0, 2'b01:
	  CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q34 =
	      _theResult___fst_exp__h354198;
      2'b10:
	  CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q34 =
	      out_exp__h354717;
      2'b11:
	  CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q34 =
	      _theResult___exp__h354714;
    endcase
  end
  always@(guard__h346097 or
	  _theResult___fst_exp__h354198 or _theResult___exp__h354714)
  begin
    case (guard__h346097)
      2'b0:
	  CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q35 =
	      _theResult___fst_exp__h354198;
      2'b01, 2'b10, 2'b11:
	  CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q35 =
	      _theResult___exp__h354714;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q34 or
	  CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q35 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4310 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4313 or
	  _theResult___fst_exp__h354198)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h354792 =
	      CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q34;
      3'd1:
	  _theResult___fst_exp__h354792 =
	      CASE_guard46097_0b0_theResult___fst_exp54198_0_ETC__q35;
      3'd2:
	  _theResult___fst_exp__h354792 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4310;
      3'd3:
	  _theResult___fst_exp__h354792 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4313;
      3'd4: _theResult___fst_exp__h354792 = _theResult___fst_exp__h354198;
      default: _theResult___fst_exp__h354792 = 8'd0;
    endcase
  end
  always@(guard__h363736 or
	  _theResult___fst_exp__h371964 or
	  out_exp__h372483 or _theResult___exp__h372480)
  begin
    case (guard__h363736)
      2'b0, 2'b01:
	  CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q40 =
	      _theResult___fst_exp__h371964;
      2'b10:
	  CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q40 =
	      out_exp__h372483;
      2'b11:
	  CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q40 =
	      _theResult___exp__h372480;
    endcase
  end
  always@(guard__h363736 or
	  _theResult___fst_exp__h371964 or _theResult___exp__h372480)
  begin
    case (guard__h363736)
      2'b0:
	  CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q41 =
	      _theResult___fst_exp__h371964;
      2'b01, 2'b10, 2'b11:
	  CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q41 =
	      _theResult___exp__h372480;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q40 or
	  CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q41 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4857 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4859 or
	  _theResult___fst_exp__h371964)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h372558 =
	      CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q40;
      3'd1:
	  _theResult___fst_exp__h372558 =
	      CASE_guard63736_0b0_theResult___fst_exp71964_0_ETC__q41;
      3'd2:
	  _theResult___fst_exp__h372558 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4857;
      3'd3:
	  _theResult___fst_exp__h372558 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4859;
      3'd4: _theResult___fst_exp__h372558 = _theResult___fst_exp__h371964;
      default: _theResult___fst_exp__h372558 = 8'd0;
    endcase
  end
  always@(guard__h372572 or
	  _theResult___fst_exp__h380649 or
	  out_exp__h381119 or _theResult___exp__h381116)
  begin
    case (guard__h372572)
      2'b0, 2'b01:
	  CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q45 =
	      _theResult___fst_exp__h380649;
      2'b10:
	  CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q45 =
	      out_exp__h381119;
      2'b11:
	  CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q45 =
	      _theResult___exp__h381116;
    endcase
  end
  always@(guard__h372572 or
	  _theResult___fst_exp__h380649 or _theResult___exp__h381116)
  begin
    case (guard__h372572)
      2'b0:
	  CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q46 =
	      _theResult___fst_exp__h380649;
      2'b01, 2'b10, 2'b11:
	  CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q46 =
	      _theResult___exp__h381116;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q45 or
	  CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q46 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4926 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4928 or
	  _theResult___fst_exp__h380649)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h381194 =
	      CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q45;
      3'd1:
	  _theResult___fst_exp__h381194 =
	      CASE_guard72572_0b0_theResult___fst_exp80649_0_ETC__q46;
      3'd2:
	  _theResult___fst_exp__h381194 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4926;
      3'd3:
	  _theResult___fst_exp__h381194 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4928;
      3'd4: _theResult___fst_exp__h381194 = _theResult___fst_exp__h380649;
      default: _theResult___fst_exp__h381194 = 8'd0;
    endcase
  end
  always@(guard__h354806 or
	  _theResult___snd__h362805 or
	  out_sfd__h363300 or _theResult___sfd__h363297)
  begin
    case (guard__h354806)
      2'b0, 2'b01:
	  CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 =
	      _theResult___snd__h362805[56:34];
      2'b10:
	  CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 =
	      out_sfd__h363300;
      2'b11:
	  CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 =
	      _theResult___sfd__h363297;
    endcase
  end
  always@(guard__h354806 or
	  _theResult___snd__h362805 or _theResult___sfd__h363297)
  begin
    case (guard__h354806)
      2'b0:
	  CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48 =
	      _theResult___snd__h362805[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48 =
	      _theResult___sfd__h363297;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47 or
	  CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978 or
	  _theResult___snd__h362805)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h363375 =
	      CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q47;
      3'd1:
	  _theResult___fst_sfd__h363375 =
	      CASE_guard54806_0b0_theResult___snd62805_BITS__ETC__q48;
      3'd2:
	  _theResult___fst_sfd__h363375 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976;
      3'd3:
	  _theResult___fst_sfd__h363375 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978;
      3'd4: _theResult___fst_sfd__h363375 = _theResult___snd__h362805[56:34];
      default: _theResult___fst_sfd__h363375 = 23'd0;
    endcase
  end
  always@(guard__h346097 or
	  sfdin__h354192 or out_sfd__h354718 or _theResult___sfd__h354715)
  begin
    case (guard__h346097)
      2'b0, 2'b01:
	  CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 =
	      sfdin__h354192[56:34];
      2'b10:
	  CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 =
	      out_sfd__h354718;
      2'b11:
	  CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 =
	      _theResult___sfd__h354715;
    endcase
  end
  always@(guard__h346097 or sfdin__h354192 or _theResult___sfd__h354715)
  begin
    case (guard__h346097)
      2'b0:
	  CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50 =
	      sfdin__h354192[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50 =
	      _theResult___sfd__h354715;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49 or
	  CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959 or
	  sfdin__h354192)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h354793 =
	      CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q49;
      3'd1:
	  _theResult___fst_sfd__h354793 =
	      CASE_guard46097_0b0_sfdin54192_BITS_56_TO_34_0_ETC__q50;
      3'd2:
	  _theResult___fst_sfd__h354793 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957;
      3'd3:
	  _theResult___fst_sfd__h354793 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959;
      3'd4: _theResult___fst_sfd__h354793 = sfdin__h354192[56:34];
      default: _theResult___fst_sfd__h354793 = 23'd0;
    endcase
  end
  always@(guard__h363736 or
	  sfdin__h371958 or out_sfd__h372484 or _theResult___sfd__h372481)
  begin
    case (guard__h363736)
      2'b0, 2'b01:
	  CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q51 =
	      sfdin__h371958[56:34];
      2'b10:
	  CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q51 =
	      out_sfd__h372484;
      2'b11:
	  CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q51 =
	      _theResult___sfd__h372481;
    endcase
  end
  always@(guard__h363736 or sfdin__h371958 or _theResult___sfd__h372481)
  begin
    case (guard__h363736)
      2'b0:
	  CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q52 =
	      sfdin__h371958[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q52 =
	      _theResult___sfd__h372481;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q51 or
	  CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q52 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5003 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5005 or
	  sfdin__h371958)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h372559 =
	      CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q51;
      3'd1:
	  _theResult___fst_sfd__h372559 =
	      CASE_guard63736_0b0_sfdin71958_BITS_56_TO_34_0_ETC__q52;
      3'd2:
	  _theResult___fst_sfd__h372559 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5003;
      3'd3:
	  _theResult___fst_sfd__h372559 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5005;
      3'd4: _theResult___fst_sfd__h372559 = sfdin__h371958[56:34];
      default: _theResult___fst_sfd__h372559 = 23'd0;
    endcase
  end
  always@(guard__h372572 or
	  _theResult___snd__h380595 or
	  out_sfd__h381120 or _theResult___sfd__h381117)
  begin
    case (guard__h372572)
      2'b0, 2'b01:
	  CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q53 =
	      _theResult___snd__h380595[56:34];
      2'b10:
	  CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q53 =
	      out_sfd__h381120;
      2'b11:
	  CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q53 =
	      _theResult___sfd__h381117;
    endcase
  end
  always@(guard__h372572 or
	  _theResult___snd__h380595 or _theResult___sfd__h381117)
  begin
    case (guard__h372572)
      2'b0:
	  CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q54 =
	      _theResult___snd__h380595[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q54 =
	      _theResult___sfd__h381117;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q53 or
	  CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q54 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 or
	  _theResult___snd__h380595)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h381195 =
	      CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q53;
      3'd1:
	  _theResult___fst_sfd__h381195 =
	      CASE_guard72572_0b0_theResult___snd80595_BITS__ETC__q54;
      3'd2:
	  _theResult___fst_sfd__h381195 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022;
      3'd3:
	  _theResult___fst_sfd__h381195 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024;
      3'd4: _theResult___fst_sfd__h381195 = _theResult___snd__h380595[56:34];
      default: _theResult___fst_sfd__h381195 = 23'd0;
    endcase
  end
  always@(guard__h346097 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (guard__h346097)
      2'b0, 2'b01, 2'b10:
	  CASE_guard46097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      2'd3:
	  CASE_guard46097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 =
	      guard__h346097 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
	  CASE_guard46097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 or
	  guard__h346097)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 =
	      CASE_guard46097_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 =
	      (guard__h346097 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		(guard__h346097 == 2'b01 || guard__h346097 == 2'b10 ||
		 guard__h346097 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 =
		   coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(guard__h346097 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (guard__h346097)
      2'b0, 2'b01, 2'b10:
	  CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      2'd3:
	  CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 =
	      guard__h346097 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
	  CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 or
	  guard__h346097)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 =
	      CASE_guard46097_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 =
	      (guard__h346097 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		guard__h346097 != 2'b01 && guard__h346097 != 2'b10 &&
		guard__h346097 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 =
		   coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(guard__h354806 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (guard__h354806)
      2'b0, 2'b01, 2'b10:
	  CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      2'd3:
	  CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 =
	      guard__h354806 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
	  CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 or
	  guard__h354806)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 =
	      CASE_guard54806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 =
	      (guard__h354806 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		(guard__h354806 == 2'b01 || guard__h354806 == 2'b10 ||
		 guard__h354806 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 =
		   coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(guard__h354806 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (guard__h354806)
      2'b0, 2'b01, 2'b10:
	  CASE_guard54806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      2'd3:
	  CASE_guard54806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 =
	      guard__h354806 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
	  CASE_guard54806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 or
	  guard__h354806)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 =
	      CASE_guard54806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 =
	      (guard__h354806 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		guard__h354806 != 2'b01 && guard__h354806 != 2'b10 &&
		guard__h354806 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 =
		   coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(guard__h363736 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (guard__h363736)
      2'b0, 2'b01, 2'b10:
	  CASE_guard63736_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      2'd3:
	  CASE_guard63736_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 =
	      guard__h363736 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
	  CASE_guard63736_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 or
	  guard__h363736)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127 =
	      CASE_guard63736_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127 =
	      (guard__h363736 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		(guard__h363736 == 2'b01 || guard__h363736 == 2'b10 ||
		 guard__h363736 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127 =
		   coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(guard__h363736 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (guard__h363736)
      2'b0, 2'b01, 2'b10:
	  CASE_guard63736_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      2'd3:
	  CASE_guard63736_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 =
	      guard__h363736 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
	  CASE_guard63736_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 or
	  guard__h363736)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084 =
	      CASE_guard63736_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084 =
	      (guard__h363736 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		guard__h363736 != 2'b01 && guard__h363736 != 2'b10 &&
		guard__h363736 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084 =
		   coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(guard__h372572 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (guard__h372572)
      2'b0, 2'b01, 2'b10:
	  CASE_guard72572_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      2'd3:
	  CASE_guard72572_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 =
	      guard__h372572 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
	  CASE_guard72572_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 or
	  guard__h372572)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134 =
	      CASE_guard72572_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134 =
	      (guard__h372572 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		(guard__h372572 == 2'b01 || guard__h372572 == 2'b10 ||
		 guard__h372572 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134 =
		   coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(guard__h372572 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (guard__h372572)
      2'b0, 2'b01, 2'b10:
	  CASE_guard72572_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      2'd3:
	  CASE_guard72572_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 =
	      guard__h372572 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
	  CASE_guard72572_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 or
	  guard__h372572)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097 =
	      CASE_guard72572_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097 =
	      (guard__h372572 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		guard__h372572 != 2'b01 && guard__h372572 != 2'b10 &&
		guard__h372572 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097 =
		   coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0, 3'd1, 3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5120 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5120 =
		   coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0, 3'd1, 3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5071 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5071 =
		   coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(guard__h400503 or
	  _theResult___fst_exp__h408551 or
	  out_exp__h408996 or _theResult___exp__h408993)
  begin
    case (guard__h400503)
      2'b0, 2'b01:
	  CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q67 =
	      _theResult___fst_exp__h408551;
      2'b10:
	  CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q67 =
	      out_exp__h408996;
      2'b11:
	  CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q67 =
	      _theResult___exp__h408993;
    endcase
  end
  always@(guard__h400503 or
	  _theResult___fst_exp__h408551 or _theResult___exp__h408993)
  begin
    case (guard__h400503)
      2'b0:
	  CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q68 =
	      _theResult___fst_exp__h408551;
      2'b01, 2'b10, 2'b11:
	  CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q68 =
	      _theResult___exp__h408993;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q67 or
	  CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q68 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5924 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5926 or
	  _theResult___fst_exp__h408551)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h409071 =
	      CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q67;
      3'd1:
	  _theResult___fst_exp__h409071 =
	      CASE_guard00503_0b0_theResult___fst_exp08551_0_ETC__q68;
      3'd2:
	  _theResult___fst_exp__h409071 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5924;
      3'd3:
	  _theResult___fst_exp__h409071 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5926;
      3'd4: _theResult___fst_exp__h409071 = _theResult___fst_exp__h408551;
      default: _theResult___fst_exp__h409071 = 8'd0;
    endcase
  end
  always@(guard__h391796 or
	  _theResult___fst_exp__h399895 or
	  out_exp__h400414 or _theResult___exp__h400411)
  begin
    case (guard__h391796)
      2'b0, 2'b01:
	  CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q69 =
	      _theResult___fst_exp__h399895;
      2'b10:
	  CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q69 =
	      out_exp__h400414;
      2'b11:
	  CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q69 =
	      _theResult___exp__h400411;
    endcase
  end
  always@(guard__h391796 or
	  _theResult___fst_exp__h399895 or _theResult___exp__h400411)
  begin
    case (guard__h391796)
      2'b0:
	  CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q70 =
	      _theResult___fst_exp__h399895;
      2'b01, 2'b10, 2'b11:
	  CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q70 =
	      _theResult___exp__h400411;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q69 or
	  CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q70 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5702 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5705 or
	  _theResult___fst_exp__h399895)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h400489 =
	      CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q69;
      3'd1:
	  _theResult___fst_exp__h400489 =
	      CASE_guard91796_0b0_theResult___fst_exp99895_0_ETC__q70;
      3'd2:
	  _theResult___fst_exp__h400489 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5702;
      3'd3:
	  _theResult___fst_exp__h400489 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5705;
      3'd4: _theResult___fst_exp__h400489 = _theResult___fst_exp__h399895;
      default: _theResult___fst_exp__h400489 = 8'd0;
    endcase
  end
  always@(guard__h409433 or
	  _theResult___fst_exp__h417661 or
	  out_exp__h418180 or _theResult___exp__h418177)
  begin
    case (guard__h409433)
      2'b0, 2'b01:
	  CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q75 =
	      _theResult___fst_exp__h417661;
      2'b10:
	  CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q75 =
	      out_exp__h418180;
      2'b11:
	  CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q75 =
	      _theResult___exp__h418177;
    endcase
  end
  always@(guard__h409433 or
	  _theResult___fst_exp__h417661 or _theResult___exp__h418177)
  begin
    case (guard__h409433)
      2'b0:
	  CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q76 =
	      _theResult___fst_exp__h417661;
      2'b01, 2'b10, 2'b11:
	  CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q76 =
	      _theResult___exp__h418177;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q75 or
	  CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q76 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6249 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6251 or
	  _theResult___fst_exp__h417661)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h418255 =
	      CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q75;
      3'd1:
	  _theResult___fst_exp__h418255 =
	      CASE_guard09433_0b0_theResult___fst_exp17661_0_ETC__q76;
      3'd2:
	  _theResult___fst_exp__h418255 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6249;
      3'd3:
	  _theResult___fst_exp__h418255 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6251;
      3'd4: _theResult___fst_exp__h418255 = _theResult___fst_exp__h417661;
      default: _theResult___fst_exp__h418255 = 8'd0;
    endcase
  end
  always@(guard__h418269 or
	  _theResult___fst_exp__h426346 or
	  out_exp__h426816 or _theResult___exp__h426813)
  begin
    case (guard__h418269)
      2'b0, 2'b01:
	  CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q80 =
	      _theResult___fst_exp__h426346;
      2'b10:
	  CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q80 =
	      out_exp__h426816;
      2'b11:
	  CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q80 =
	      _theResult___exp__h426813;
    endcase
  end
  always@(guard__h418269 or
	  _theResult___fst_exp__h426346 or _theResult___exp__h426813)
  begin
    case (guard__h418269)
      2'b0:
	  CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q81 =
	      _theResult___fst_exp__h426346;
      2'b01, 2'b10, 2'b11:
	  CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q81 =
	      _theResult___exp__h426813;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q80 or
	  CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q81 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6318 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6320 or
	  _theResult___fst_exp__h426346)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h426891 =
	      CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q80;
      3'd1:
	  _theResult___fst_exp__h426891 =
	      CASE_guard18269_0b0_theResult___fst_exp26346_0_ETC__q81;
      3'd2:
	  _theResult___fst_exp__h426891 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6318;
      3'd3:
	  _theResult___fst_exp__h426891 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6320;
      3'd4: _theResult___fst_exp__h426891 = _theResult___fst_exp__h426346;
      default: _theResult___fst_exp__h426891 = 8'd0;
    endcase
  end
  always@(guard__h400503 or
	  _theResult___snd__h408502 or
	  out_sfd__h408997 or _theResult___sfd__h408994)
  begin
    case (guard__h400503)
      2'b0, 2'b01:
	  CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 =
	      _theResult___snd__h408502[56:34];
      2'b10:
	  CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 =
	      out_sfd__h408997;
      2'b11:
	  CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 =
	      _theResult___sfd__h408994;
    endcase
  end
  always@(guard__h400503 or
	  _theResult___snd__h408502 or _theResult___sfd__h408994)
  begin
    case (guard__h400503)
      2'b0:
	  CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83 =
	      _theResult___snd__h408502[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83 =
	      _theResult___sfd__h408994;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82 or
	  CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370 or
	  _theResult___snd__h408502)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h409072 =
	      CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q82;
      3'd1:
	  _theResult___fst_sfd__h409072 =
	      CASE_guard00503_0b0_theResult___snd08502_BITS__ETC__q83;
      3'd2:
	  _theResult___fst_sfd__h409072 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368;
      3'd3:
	  _theResult___fst_sfd__h409072 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370;
      3'd4: _theResult___fst_sfd__h409072 = _theResult___snd__h408502[56:34];
      default: _theResult___fst_sfd__h409072 = 23'd0;
    endcase
  end
  always@(guard__h391796 or
	  sfdin__h399889 or out_sfd__h400415 or _theResult___sfd__h400412)
  begin
    case (guard__h391796)
      2'b0, 2'b01:
	  CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 =
	      sfdin__h399889[56:34];
      2'b10:
	  CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 =
	      out_sfd__h400415;
      2'b11:
	  CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 =
	      _theResult___sfd__h400412;
    endcase
  end
  always@(guard__h391796 or sfdin__h399889 or _theResult___sfd__h400412)
  begin
    case (guard__h391796)
      2'b0:
	  CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85 =
	      sfdin__h399889[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85 =
	      _theResult___sfd__h400412;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84 or
	  CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351 or
	  sfdin__h399889)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h400490 =
	      CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q84;
      3'd1:
	  _theResult___fst_sfd__h400490 =
	      CASE_guard91796_0b0_sfdin99889_BITS_56_TO_34_0_ETC__q85;
      3'd2:
	  _theResult___fst_sfd__h400490 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349;
      3'd3:
	  _theResult___fst_sfd__h400490 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351;
      3'd4: _theResult___fst_sfd__h400490 = sfdin__h399889[56:34];
      default: _theResult___fst_sfd__h400490 = 23'd0;
    endcase
  end
  always@(guard__h409433 or
	  sfdin__h417655 or out_sfd__h418181 or _theResult___sfd__h418178)
  begin
    case (guard__h409433)
      2'b0, 2'b01:
	  CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q86 =
	      sfdin__h417655[56:34];
      2'b10:
	  CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q86 =
	      out_sfd__h418181;
      2'b11:
	  CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q86 =
	      _theResult___sfd__h418178;
    endcase
  end
  always@(guard__h409433 or sfdin__h417655 or _theResult___sfd__h418178)
  begin
    case (guard__h409433)
      2'b0:
	  CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q87 =
	      sfdin__h417655[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q87 =
	      _theResult___sfd__h418178;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q86 or
	  CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q87 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6395 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6397 or
	  sfdin__h417655)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h418256 =
	      CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q86;
      3'd1:
	  _theResult___fst_sfd__h418256 =
	      CASE_guard09433_0b0_sfdin17655_BITS_56_TO_34_0_ETC__q87;
      3'd2:
	  _theResult___fst_sfd__h418256 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6395;
      3'd3:
	  _theResult___fst_sfd__h418256 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6397;
      3'd4: _theResult___fst_sfd__h418256 = sfdin__h417655[56:34];
      default: _theResult___fst_sfd__h418256 = 23'd0;
    endcase
  end
  always@(guard__h418269 or
	  _theResult___snd__h426292 or
	  out_sfd__h426817 or _theResult___sfd__h426814)
  begin
    case (guard__h418269)
      2'b0, 2'b01:
	  CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q88 =
	      _theResult___snd__h426292[56:34];
      2'b10:
	  CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q88 =
	      out_sfd__h426817;
      2'b11:
	  CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q88 =
	      _theResult___sfd__h426814;
    endcase
  end
  always@(guard__h418269 or
	  _theResult___snd__h426292 or _theResult___sfd__h426814)
  begin
    case (guard__h418269)
      2'b0:
	  CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q89 =
	      _theResult___snd__h426292[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q89 =
	      _theResult___sfd__h426814;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q88 or
	  CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q89 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 or
	  _theResult___snd__h426292)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h426892 =
	      CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q88;
      3'd1:
	  _theResult___fst_sfd__h426892 =
	      CASE_guard18269_0b0_theResult___snd26292_BITS__ETC__q89;
      3'd2:
	  _theResult___fst_sfd__h426892 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414;
      3'd3:
	  _theResult___fst_sfd__h426892 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416;
      3'd4: _theResult___fst_sfd__h426892 = _theResult___snd__h426292[56:34];
      default: _theResult___fst_sfd__h426892 = 23'd0;
    endcase
  end
  always@(guard__h391796 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (guard__h391796)
      2'b0, 2'b01, 2'b10:
	  CASE_guard91796_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      2'd3:
	  CASE_guard91796_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 =
	      guard__h391796 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
	  CASE_guard91796_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 or
	  guard__h391796)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 =
	      CASE_guard91796_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 =
	      (guard__h391796 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		(guard__h391796 == 2'b01 || guard__h391796 == 2'b10 ||
		 guard__h391796 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 =
		   coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(guard__h391796 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (guard__h391796)
      2'b0, 2'b01, 2'b10:
	  CASE_guard91796_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      2'd3:
	  CASE_guard91796_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 =
	      guard__h391796 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
	  CASE_guard91796_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 or
	  guard__h391796)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446 =
	      CASE_guard91796_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446 =
	      (guard__h391796 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		guard__h391796 != 2'b01 && guard__h391796 != 2'b10 &&
		guard__h391796 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446 =
		   coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(guard__h400503 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (guard__h400503)
      2'b0, 2'b01, 2'b10:
	  CASE_guard00503_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      2'd3:
	  CASE_guard00503_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 =
	      guard__h400503 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
	  CASE_guard00503_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 or
	  guard__h400503)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509 =
	      CASE_guard00503_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509 =
	      (guard__h400503 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		(guard__h400503 == 2'b01 || guard__h400503 == 2'b10 ||
		 guard__h400503 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509 =
		   coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(guard__h400503 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (guard__h400503)
      2'b0, 2'b01, 2'b10:
	  CASE_guard00503_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      2'd3:
	  CASE_guard00503_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 =
	      guard__h400503 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
	  CASE_guard00503_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 or
	  guard__h400503)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 =
	      CASE_guard00503_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 =
	      (guard__h400503 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		guard__h400503 != 2'b01 && guard__h400503 != 2'b10 &&
		guard__h400503 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 =
		   coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(guard__h409433 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (guard__h409433)
      2'b0, 2'b01, 2'b10:
	  CASE_guard09433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      2'd3:
	  CASE_guard09433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 =
	      guard__h409433 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
	  CASE_guard09433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 or
	  guard__h409433)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519 =
	      CASE_guard09433_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519 =
	      (guard__h409433 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		(guard__h409433 == 2'b01 || guard__h409433 == 2'b10 ||
		 guard__h409433 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519 =
		   coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(guard__h409433 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (guard__h409433)
      2'b0, 2'b01, 2'b10:
	  CASE_guard09433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      2'd3:
	  CASE_guard09433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 =
	      guard__h409433 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
	  CASE_guard09433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 or
	  guard__h409433)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476 =
	      CASE_guard09433_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476 =
	      (guard__h409433 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		guard__h409433 != 2'b01 && guard__h409433 != 2'b10 &&
		guard__h409433 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476 =
		   coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(guard__h418269 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (guard__h418269)
      2'b0, 2'b01, 2'b10:
	  CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      2'd3:
	  CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 =
	      guard__h418269 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
	  CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 or
	  guard__h418269)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 =
	      CASE_guard18269_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 =
	      (guard__h418269 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		(guard__h418269 == 2'b01 || guard__h418269 == 2'b10 ||
		 guard__h418269 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 =
		   coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(guard__h418269 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (guard__h418269)
      2'b0, 2'b01, 2'b10:
	  CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      2'd3:
	  CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 =
	      guard__h418269 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
	  CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 or
	  guard__h418269)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 =
	      CASE_guard18269_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 =
	      (guard__h418269 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		guard__h418269 != 2'b01 && guard__h418269 != 2'b10 &&
		guard__h418269 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 =
		   coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0, 3'd1, 3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6512 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6512 =
		   coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0, 3'd1, 3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6463 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6463 =
		   coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(guard__h446198 or
	  _theResult___fst_exp__h454246 or
	  out_exp__h454691 or _theResult___exp__h454688)
  begin
    case (guard__h446198)
      2'b0, 2'b01:
	  CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q102 =
	      _theResult___fst_exp__h454246;
      2'b10:
	  CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q102 =
	      out_exp__h454691;
      2'b11:
	  CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q102 =
	      _theResult___exp__h454688;
    endcase
  end
  always@(guard__h446198 or
	  _theResult___fst_exp__h454246 or _theResult___exp__h454688)
  begin
    case (guard__h446198)
      2'b0:
	  CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q103 =
	      _theResult___fst_exp__h454246;
      2'b01, 2'b10, 2'b11:
	  CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q103 =
	      _theResult___exp__h454688;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q102 or
	  CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q103 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7316 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7318 or
	  _theResult___fst_exp__h454246)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h454766 =
	      CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q102;
      3'd1:
	  _theResult___fst_exp__h454766 =
	      CASE_guard46198_0b0_theResult___fst_exp54246_0_ETC__q103;
      3'd2:
	  _theResult___fst_exp__h454766 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7316;
      3'd3:
	  _theResult___fst_exp__h454766 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7318;
      3'd4: _theResult___fst_exp__h454766 = _theResult___fst_exp__h454246;
      default: _theResult___fst_exp__h454766 = 8'd0;
    endcase
  end
  always@(guard__h437491 or
	  _theResult___fst_exp__h445590 or
	  out_exp__h446109 or _theResult___exp__h446106)
  begin
    case (guard__h437491)
      2'b0, 2'b01:
	  CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q104 =
	      _theResult___fst_exp__h445590;
      2'b10:
	  CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q104 =
	      out_exp__h446109;
      2'b11:
	  CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q104 =
	      _theResult___exp__h446106;
    endcase
  end
  always@(guard__h437491 or
	  _theResult___fst_exp__h445590 or _theResult___exp__h446106)
  begin
    case (guard__h437491)
      2'b0:
	  CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q105 =
	      _theResult___fst_exp__h445590;
      2'b01, 2'b10, 2'b11:
	  CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q105 =
	      _theResult___exp__h446106;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q104 or
	  CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q105 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7094 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7097 or
	  _theResult___fst_exp__h445590)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h446184 =
	      CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q104;
      3'd1:
	  _theResult___fst_exp__h446184 =
	      CASE_guard37491_0b0_theResult___fst_exp45590_0_ETC__q105;
      3'd2:
	  _theResult___fst_exp__h446184 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7094;
      3'd3:
	  _theResult___fst_exp__h446184 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7097;
      3'd4: _theResult___fst_exp__h446184 = _theResult___fst_exp__h445590;
      default: _theResult___fst_exp__h446184 = 8'd0;
    endcase
  end
  always@(guard__h455128 or
	  _theResult___fst_exp__h463356 or
	  out_exp__h463875 or _theResult___exp__h463872)
  begin
    case (guard__h455128)
      2'b0, 2'b01:
	  CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q110 =
	      _theResult___fst_exp__h463356;
      2'b10:
	  CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q110 =
	      out_exp__h463875;
      2'b11:
	  CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q110 =
	      _theResult___exp__h463872;
    endcase
  end
  always@(guard__h455128 or
	  _theResult___fst_exp__h463356 or _theResult___exp__h463872)
  begin
    case (guard__h455128)
      2'b0:
	  CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q111 =
	      _theResult___fst_exp__h463356;
      2'b01, 2'b10, 2'b11:
	  CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q111 =
	      _theResult___exp__h463872;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q110 or
	  CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q111 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7641 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7643 or
	  _theResult___fst_exp__h463356)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h463950 =
	      CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q110;
      3'd1:
	  _theResult___fst_exp__h463950 =
	      CASE_guard55128_0b0_theResult___fst_exp63356_0_ETC__q111;
      3'd2:
	  _theResult___fst_exp__h463950 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7641;
      3'd3:
	  _theResult___fst_exp__h463950 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7643;
      3'd4: _theResult___fst_exp__h463950 = _theResult___fst_exp__h463356;
      default: _theResult___fst_exp__h463950 = 8'd0;
    endcase
  end
  always@(guard__h463964 or
	  _theResult___fst_exp__h472041 or
	  out_exp__h472511 or _theResult___exp__h472508)
  begin
    case (guard__h463964)
      2'b0, 2'b01:
	  CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q115 =
	      _theResult___fst_exp__h472041;
      2'b10:
	  CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q115 =
	      out_exp__h472511;
      2'b11:
	  CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q115 =
	      _theResult___exp__h472508;
    endcase
  end
  always@(guard__h463964 or
	  _theResult___fst_exp__h472041 or _theResult___exp__h472508)
  begin
    case (guard__h463964)
      2'b0:
	  CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q116 =
	      _theResult___fst_exp__h472041;
      2'b01, 2'b10, 2'b11:
	  CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q116 =
	      _theResult___exp__h472508;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q115 or
	  CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q116 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7710 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7712 or
	  _theResult___fst_exp__h472041)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h472586 =
	      CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q115;
      3'd1:
	  _theResult___fst_exp__h472586 =
	      CASE_guard63964_0b0_theResult___fst_exp72041_0_ETC__q116;
      3'd2:
	  _theResult___fst_exp__h472586 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7710;
      3'd3:
	  _theResult___fst_exp__h472586 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7712;
      3'd4: _theResult___fst_exp__h472586 = _theResult___fst_exp__h472041;
      default: _theResult___fst_exp__h472586 = 8'd0;
    endcase
  end
  always@(guard__h446198 or
	  _theResult___snd__h454197 or
	  out_sfd__h454692 or _theResult___sfd__h454689)
  begin
    case (guard__h446198)
      2'b0, 2'b01:
	  CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q117 =
	      _theResult___snd__h454197[56:34];
      2'b10:
	  CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q117 =
	      out_sfd__h454692;
      2'b11:
	  CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q117 =
	      _theResult___sfd__h454689;
    endcase
  end
  always@(guard__h446198 or
	  _theResult___snd__h454197 or _theResult___sfd__h454689)
  begin
    case (guard__h446198)
      2'b0:
	  CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q118 =
	      _theResult___snd__h454197[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q118 =
	      _theResult___sfd__h454689;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q117 or
	  CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q118 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7760 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762 or
	  _theResult___snd__h454197)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h454767 =
	      CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q117;
      3'd1:
	  _theResult___fst_sfd__h454767 =
	      CASE_guard46198_0b0_theResult___snd54197_BITS__ETC__q118;
      3'd2:
	  _theResult___fst_sfd__h454767 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7760;
      3'd3:
	  _theResult___fst_sfd__h454767 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762;
      3'd4: _theResult___fst_sfd__h454767 = _theResult___snd__h454197[56:34];
      default: _theResult___fst_sfd__h454767 = 23'd0;
    endcase
  end
  always@(guard__h437491 or
	  sfdin__h445584 or out_sfd__h446110 or _theResult___sfd__h446107)
  begin
    case (guard__h437491)
      2'b0, 2'b01:
	  CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q119 =
	      sfdin__h445584[56:34];
      2'b10:
	  CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q119 =
	      out_sfd__h446110;
      2'b11:
	  CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q119 =
	      _theResult___sfd__h446107;
    endcase
  end
  always@(guard__h437491 or sfdin__h445584 or _theResult___sfd__h446107)
  begin
    case (guard__h437491)
      2'b0:
	  CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q120 =
	      sfdin__h445584[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q120 =
	      _theResult___sfd__h446107;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q119 or
	  CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q120 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7741 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7743 or
	  sfdin__h445584)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h446185 =
	      CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q119;
      3'd1:
	  _theResult___fst_sfd__h446185 =
	      CASE_guard37491_0b0_sfdin45584_BITS_56_TO_34_0_ETC__q120;
      3'd2:
	  _theResult___fst_sfd__h446185 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7741;
      3'd3:
	  _theResult___fst_sfd__h446185 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7743;
      3'd4: _theResult___fst_sfd__h446185 = sfdin__h445584[56:34];
      default: _theResult___fst_sfd__h446185 = 23'd0;
    endcase
  end
  always@(guard__h455128 or
	  sfdin__h463350 or out_sfd__h463876 or _theResult___sfd__h463873)
  begin
    case (guard__h455128)
      2'b0, 2'b01:
	  CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q121 =
	      sfdin__h463350[56:34];
      2'b10:
	  CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q121 =
	      out_sfd__h463876;
      2'b11:
	  CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q121 =
	      _theResult___sfd__h463873;
    endcase
  end
  always@(guard__h455128 or sfdin__h463350 or _theResult___sfd__h463873)
  begin
    case (guard__h455128)
      2'b0:
	  CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q122 =
	      sfdin__h463350[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q122 =
	      _theResult___sfd__h463873;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q121 or
	  CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q122 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7787 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7789 or
	  sfdin__h463350)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h463951 =
	      CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q121;
      3'd1:
	  _theResult___fst_sfd__h463951 =
	      CASE_guard55128_0b0_sfdin63350_BITS_56_TO_34_0_ETC__q122;
      3'd2:
	  _theResult___fst_sfd__h463951 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7787;
      3'd3:
	  _theResult___fst_sfd__h463951 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7789;
      3'd4: _theResult___fst_sfd__h463951 = sfdin__h463350[56:34];
      default: _theResult___fst_sfd__h463951 = 23'd0;
    endcase
  end
  always@(guard__h463964 or
	  _theResult___snd__h471987 or
	  out_sfd__h472512 or _theResult___sfd__h472509)
  begin
    case (guard__h463964)
      2'b0, 2'b01:
	  CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q123 =
	      _theResult___snd__h471987[56:34];
      2'b10:
	  CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q123 =
	      out_sfd__h472512;
      2'b11:
	  CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q123 =
	      _theResult___sfd__h472509;
    endcase
  end
  always@(guard__h463964 or
	  _theResult___snd__h471987 or _theResult___sfd__h472509)
  begin
    case (guard__h463964)
      2'b0:
	  CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q124 =
	      _theResult___snd__h471987[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q124 =
	      _theResult___sfd__h472509;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q123 or
	  CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q124 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 or
	  _theResult___snd__h471987)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h472587 =
	      CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q123;
      3'd1:
	  _theResult___fst_sfd__h472587 =
	      CASE_guard63964_0b0_theResult___snd71987_BITS__ETC__q124;
      3'd2:
	  _theResult___fst_sfd__h472587 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806;
      3'd3:
	  _theResult___fst_sfd__h472587 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808;
      3'd4: _theResult___fst_sfd__h472587 = _theResult___snd__h471987[56:34];
      default: _theResult___fst_sfd__h472587 = 23'd0;
    endcase
  end
  always@(guard__h437491 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (guard__h437491)
      2'b0, 2'b01, 2'b10:
	  CASE_guard37491_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      2'd3:
	  CASE_guard37491_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 =
	      guard__h437491 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
	  CASE_guard37491_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125 or
	  guard__h437491)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894 =
	      CASE_guard37491_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q125;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894 =
	      (guard__h437491 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		(guard__h437491 == 2'b01 || guard__h437491 == 2'b10 ||
		 guard__h437491 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894 =
		   coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(guard__h437491 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (guard__h437491)
      2'b0, 2'b01, 2'b10:
	  CASE_guard37491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      2'd3:
	  CASE_guard37491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 =
	      guard__h437491 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
	  CASE_guard37491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 or
	  guard__h437491)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 =
	      CASE_guard37491_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 =
	      (guard__h437491 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		guard__h437491 != 2'b01 && guard__h437491 != 2'b10 &&
		guard__h437491 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 =
		   coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(guard__h446198 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (guard__h446198)
      2'b0, 2'b01, 2'b10:
	  CASE_guard46198_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      2'd3:
	  CASE_guard46198_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 =
	      guard__h446198 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
	  CASE_guard46198_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 or
	  guard__h446198)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 =
	      CASE_guard46198_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 =
	      (guard__h446198 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		(guard__h446198 == 2'b01 || guard__h446198 == 2'b10 ||
		 guard__h446198 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 =
		   coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(guard__h446198 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (guard__h446198)
      2'b0, 2'b01, 2'b10:
	  CASE_guard46198_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      2'd3:
	  CASE_guard46198_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 =
	      guard__h446198 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
	  CASE_guard46198_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 or
	  guard__h446198)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 =
	      CASE_guard46198_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 =
	      (guard__h446198 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		guard__h446198 != 2'b01 && guard__h446198 != 2'b10 &&
		guard__h446198 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 =
		   coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(guard__h455128 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (guard__h455128)
      2'b0, 2'b01, 2'b10:
	  CASE_guard55128_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      2'd3:
	  CASE_guard55128_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 =
	      guard__h455128 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
	  CASE_guard55128_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 or
	  guard__h455128)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911 =
	      CASE_guard55128_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911 =
	      (guard__h455128 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		(guard__h455128 == 2'b01 || guard__h455128 == 2'b10 ||
		 guard__h455128 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911 =
		   coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(guard__h455128 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (guard__h455128)
      2'b0, 2'b01, 2'b10:
	  CASE_guard55128_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      2'd3:
	  CASE_guard55128_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 =
	      guard__h455128 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
	  CASE_guard55128_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 or
	  guard__h455128)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868 =
	      CASE_guard55128_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868 =
	      (guard__h455128 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		guard__h455128 != 2'b01 && guard__h455128 != 2'b10 &&
		guard__h455128 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868 =
		   coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(guard__h463964 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (guard__h463964)
      2'b0, 2'b01, 2'b10:
	  CASE_guard63964_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      2'd3:
	  CASE_guard63964_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 =
	      guard__h463964 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
	  CASE_guard63964_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 or
	  guard__h463964)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918 =
	      CASE_guard63964_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918 =
	      (guard__h463964 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		(guard__h463964 == 2'b01 || guard__h463964 == 2'b10 ||
		 guard__h463964 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918 =
		   coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(guard__h463964 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (guard__h463964)
      2'b0, 2'b01, 2'b10:
	  CASE_guard63964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      2'd3:
	  CASE_guard63964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 =
	      guard__h463964 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
	  CASE_guard63964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 or
	  guard__h463964)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881 =
	      CASE_guard63964_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881 =
	      (guard__h463964 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		guard__h463964 != 2'b01 && guard__h463964 != 2'b10 &&
		guard__h463964 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881 =
		   coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0, 3'd1, 3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7904 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7904 =
		   coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0, 3'd1, 3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7855 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7855 =
		   coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
      5'd0, 5'd1, 5'd2, 5'd25, 5'd26, 5'd27:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8396 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put;
      5'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8396 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put;
      5'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8396 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8396 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd28 ||
		   coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put;
    endcase
  end
  always@(guard__h493569 or
	  _theResult___fst_exp__h501530 or _theResult___exp__h502185)
  begin
    case (guard__h493569)
      2'b0:
	  CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q143 =
	      _theResult___fst_exp__h501530;
      2'b01, 2'b10, 2'b11:
	  CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q143 =
	      _theResult___exp__h502185;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___fst_exp__h501530 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9015 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9013 or
	  CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q143)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 =
	      _theResult___fst_exp__h501530;
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9015;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9013;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 =
	      CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q143;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 =
		   11'd0;
    endcase
  end
  always@(guard__h493569 or
	  _theResult___fst_exp__h501530 or
	  out_exp__h502188 or _theResult___exp__h502185)
  begin
    case (guard__h493569)
      2'b0, 2'b01:
	  CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q144 =
	      _theResult___fst_exp__h501530;
      2'b10:
	  CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q144 =
	      out_exp__h502188;
      2'b11:
	  CASE_guard93569_0b0_theResult___fst_exp01530_0_ETC__q144 =
	      _theResult___exp__h502185;
    endcase
  end
  always@(guard__h493569 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h493569)
      2'b0, 2'b01, 2'b10:
	  CASE_guard93569_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171];
      2'd3:
	  CASE_guard93569_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 =
	      guard__h493569 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h493569)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 =
	      (guard__h493569 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
		(guard__h493569 == 2'b01 || guard__h493569 == 2'b10 ||
		 guard__h493569 == 2'b11) &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[171];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		   32'hFFFFFFFF &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[171];
    endcase
  end
  always@(guard__h502881 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h502881)
      2'b0, 2'b01, 2'b10:
	  CASE_guard02881_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171];
      2'd3:
	  CASE_guard02881_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 =
	      guard__h502881 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h502881)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 =
	      (guard__h502881 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
		(guard__h502881 == 2'b01 || guard__h502881 == 2'b10 ||
		 guard__h502881 == 2'b11) &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[171];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		   32'hFFFFFFFF &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[171];
    endcase
  end
  always@(guard__h511950 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h511950)
      2'b0, 2'b01, 2'b10:
	  CASE_guard11950_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171];
      2'd3:
	  CASE_guard11950_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 =
	      guard__h511950 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h511950)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 =
	      (guard__h511950 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
		(guard__h511950 == 2'b01 || guard__h511950 == 2'b10 ||
		 guard__h511950 == 2'b11) &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[171];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		   32'hFFFFFFFF &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[171];
    endcase
  end
  always@(guard__h571726 or
	  _theResult___fst_exp__h579687 or _theResult___exp__h580342)
  begin
    case (guard__h571726)
      2'b0:
	  CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q160 =
	      _theResult___fst_exp__h579687;
      2'b01, 2'b10, 2'b11:
	  CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q160 =
	      _theResult___exp__h580342;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___fst_exp__h579687 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9730 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9728 or
	  CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q160)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 =
	      _theResult___fst_exp__h579687;
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9730;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9728;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 =
	      CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q160;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 =
		   11'd0;
    endcase
  end
  always@(guard__h571726 or
	  _theResult___fst_exp__h579687 or
	  out_exp__h580345 or _theResult___exp__h580342)
  begin
    case (guard__h571726)
      2'b0, 2'b01:
	  CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q161 =
	      _theResult___fst_exp__h579687;
      2'b10:
	  CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q161 =
	      out_exp__h580345;
      2'b11:
	  CASE_guard71726_0b0_theResult___fst_exp79687_0_ETC__q161 =
	      _theResult___exp__h580342;
    endcase
  end
  always@(guard__h571726 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h571726)
      2'b0, 2'b01, 2'b10:
	  CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      2'd3:
	  CASE_guard71726_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 =
	      guard__h571726 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571726)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 =
	      (guard__h571726 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
		(guard__h571726 == 2'b01 || guard__h571726 == 2'b10 ||
		 guard__h571726 == 2'b11) &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		   32'hFFFFFFFF &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(guard__h581038 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h581038)
      2'b0, 2'b01, 2'b10:
	  CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      2'd3:
	  CASE_guard81038_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 =
	      guard__h581038 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581038)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 =
	      (guard__h581038 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
		(guard__h581038 == 2'b01 || guard__h581038 == 2'b10 ||
		 guard__h581038 == 2'b11) &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		   32'hFFFFFFFF &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(guard__h590107 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h590107)
      2'b0, 2'b01, 2'b10:
	  CASE_guard90107_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      2'd3:
	  CASE_guard90107_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 =
	      guard__h590107 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590107)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 =
	      (guard__h590107 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
		(guard__h590107 == 2'b01 || guard__h590107 == 2'b10 ||
		 guard__h590107 == 2'b11) &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		   32'hFFFFFFFF &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(guard__h581038 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h581038)
      2'b0, 2'b01, 2'b10:
	  CASE_guard81038_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      2'd3:
	  CASE_guard81038_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 =
	      guard__h581038 != 2'b11 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581038)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169 =
	      (guard__h581038 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
		guard__h581038 != 2'b01 && guard__h581038 != 2'b10 &&
		guard__h581038 != 2'b11 ||
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
		   coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
		   32'hFFFFFFFF ||
		   !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(guard__h590107 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h590107)
      2'b0, 2'b01, 2'b10:
	  CASE_guard90107_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      2'd3:
	  CASE_guard90107_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 =
	      guard__h590107 != 2'b11 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590107)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 =
	      (guard__h590107 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
		guard__h590107 != 2'b01 && guard__h590107 != 2'b10 &&
		guard__h590107 != 2'b11 ||
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
		   coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
		   32'hFFFFFFFF ||
		   !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(guard__h571726 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h571726)
      2'b0, 2'b01, 2'b10:
	  CASE_guard71726_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      2'd3:
	  CASE_guard71726_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 =
	      guard__h571726 != 2'b11 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571726)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 =
	      (guard__h571726 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
		guard__h571726 != 2'b01 && guard__h571726 != 2'b10 &&
		guard__h571726 != 2'b11 ||
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
		   coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
		   32'hFFFFFFFF ||
		   !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(guard__h532422 or
	  _theResult___fst_exp__h540383 or _theResult___exp__h541038)
  begin
    case (guard__h532422)
      2'b0:
	  CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q183 =
	      _theResult___fst_exp__h540383;
      2'b01, 2'b10, 2'b11:
	  CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q183 =
	      _theResult___exp__h541038;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___fst_exp__h540383 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10500 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10498 or
	  CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q183)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 =
	      _theResult___fst_exp__h540383;
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10500;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10498;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 =
	      CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q183;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 =
		   11'd0;
    endcase
  end
  always@(guard__h532422 or
	  _theResult___fst_exp__h540383 or
	  out_exp__h541041 or _theResult___exp__h541038)
  begin
    case (guard__h532422)
      2'b0, 2'b01:
	  CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q184 =
	      _theResult___fst_exp__h540383;
      2'b10:
	  CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q184 =
	      out_exp__h541041;
      2'b11:
	  CASE_guard32422_0b0_theResult___fst_exp40383_0_ETC__q184 =
	      _theResult___exp__h541038;
    endcase
  end
  always@(guard__h541734 or
	  _theResult___fst_exp__h549960 or _theResult___exp__h550689)
  begin
    case (guard__h541734)
      2'b0:
	  CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q185 =
	      _theResult___fst_exp__h549960;
      2'b01, 2'b10, 2'b11:
	  CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q185 =
	      _theResult___exp__h550689;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___fst_exp__h549960 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536 or
	  CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q185)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 =
	      _theResult___fst_exp__h549960;
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 =
	      CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q185;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 =
		   11'd0;
    endcase
  end
  always@(guard__h541734 or
	  _theResult___fst_exp__h549960 or
	  out_exp__h550692 or _theResult___exp__h550689)
  begin
    case (guard__h541734)
      2'b0, 2'b01:
	  CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q186 =
	      _theResult___fst_exp__h549960;
      2'b10:
	  CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q186 =
	      out_exp__h550692;
      2'b11:
	  CASE_guard41734_0b0_theResult___fst_exp49960_0_ETC__q186 =
	      _theResult___exp__h550689;
    endcase
  end
  always@(guard__h550803 or
	  _theResult___fst_exp__h558793 or _theResult___exp__h559473)
  begin
    case (guard__h550803)
      2'b0:
	  CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q187 =
	      _theResult___fst_exp__h558793;
      2'b01, 2'b10, 2'b11:
	  CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q187 =
	      _theResult___exp__h559473;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___fst_exp__h558793 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10569 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567 or
	  CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q187)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 =
	      _theResult___fst_exp__h558793;
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10569;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 =
	      CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q187;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 =
		   11'd0;
    endcase
  end
  always@(guard__h550803 or
	  _theResult___fst_exp__h558793 or
	  out_exp__h559476 or _theResult___exp__h559473)
  begin
    case (guard__h550803)
      2'b0, 2'b01:
	  CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q188 =
	      _theResult___fst_exp__h558793;
      2'b10:
	  CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q188 =
	      out_exp__h559476;
      2'b11:
	  CASE_guard50803_0b0_theResult___fst_exp58793_0_ETC__q188 =
	      _theResult___exp__h559473;
    endcase
  end
  always@(guard__h581038 or
	  _theResult___fst_exp__h589264 or _theResult___exp__h589993)
  begin
    case (guard__h581038)
      2'b0:
	  CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q189 =
	      _theResult___fst_exp__h589264;
      2'b01, 2'b10, 2'b11:
	  CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q189 =
	      _theResult___exp__h589993;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___fst_exp__h589264 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766 or
	  CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q189)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 =
	      _theResult___fst_exp__h589264;
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 =
	      CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q189;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 =
		   11'd0;
    endcase
  end
  always@(guard__h581038 or
	  _theResult___fst_exp__h589264 or
	  out_exp__h589996 or _theResult___exp__h589993)
  begin
    case (guard__h581038)
      2'b0, 2'b01:
	  CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q190 =
	      _theResult___fst_exp__h589264;
      2'b10:
	  CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q190 =
	      out_exp__h589996;
      2'b11:
	  CASE_guard81038_0b0_theResult___fst_exp89264_0_ETC__q190 =
	      _theResult___exp__h589993;
    endcase
  end
  always@(guard__h590107 or
	  _theResult___fst_exp__h598097 or _theResult___exp__h598777)
  begin
    case (guard__h590107)
      2'b0:
	  CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191 =
	      _theResult___fst_exp__h598097;
      2'b01, 2'b10, 2'b11:
	  CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191 =
	      _theResult___exp__h598777;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___fst_exp__h598097 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797 or
	  CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 =
	      _theResult___fst_exp__h598097;
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 =
	      CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q191;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 =
		   11'd0;
    endcase
  end
  always@(guard__h590107 or
	  _theResult___fst_exp__h598097 or
	  out_exp__h598780 or _theResult___exp__h598777)
  begin
    case (guard__h590107)
      2'b0, 2'b01:
	  CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 =
	      _theResult___fst_exp__h598097;
      2'b10:
	  CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 =
	      out_exp__h598780;
      2'b11:
	  CASE_guard90107_0b0_theResult___fst_exp98097_0_ETC__q192 =
	      _theResult___exp__h598777;
    endcase
  end
  always@(guard__h541734 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h541734)
      2'b0, 2'b01, 2'b10:
	  CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      2'd3:
	  CASE_guard41734_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 =
	      guard__h541734 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h541734)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 =
	      (guard__h541734 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
		(guard__h541734 == 2'b01 || guard__h541734 == 2'b10 ||
		 guard__h541734 == 2'b11) &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		   32'hFFFFFFFF &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(guard__h532422 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h532422)
      2'b0, 2'b01, 2'b10:
	  CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      2'd3:
	  CASE_guard32422_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 =
	      guard__h532422 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532422)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 =
	      (guard__h532422 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
		(guard__h532422 == 2'b01 || guard__h532422 == 2'b10 ||
		 guard__h532422 == 2'b11) &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		   32'hFFFFFFFF &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(guard__h550803 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h550803)
      2'b0, 2'b01, 2'b10:
	  CASE_guard50803_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      2'd3:
	  CASE_guard50803_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 =
	      guard__h550803 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h550803)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198 =
	      (guard__h550803 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
		(guard__h550803 == 2'b01 || guard__h550803 == 2'b10 ||
		 guard__h550803 == 2'b11) &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		   32'hFFFFFFFF &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(guard__h541734 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h541734)
      2'b0, 2'b01, 2'b10:
	  CASE_guard41734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	      32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      2'd3:
	  CASE_guard41734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 =
	      guard__h541734 != 2'b11 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	      32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h541734)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	      32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200 =
	      (guard__h541734 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
		guard__h541734 != 2'b01 && guard__h541734 != 2'b10 &&
		guard__h541734 != 2'b11 ||
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
		   coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
		   32'hFFFFFFFF ||
		   !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(guard__h550803 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h550803)
      2'b0, 2'b01, 2'b10:
	  CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	      32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      2'd3:
	  CASE_guard50803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 =
	      guard__h550803 != 2'b11 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	      32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h550803)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	      32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 =
	      (guard__h550803 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
		guard__h550803 != 2'b01 && guard__h550803 != 2'b10 &&
		guard__h550803 != 2'b11 ||
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
		   coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
		   32'hFFFFFFFF ||
		   !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(guard__h532422 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h532422)
      2'b0, 2'b01, 2'b10:
	  CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	      32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      2'd3:
	  CASE_guard32422_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 =
	      guard__h532422 != 2'b11 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	      32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532422)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	      32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 =
	      (guard__h532422 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
		guard__h532422 != 2'b01 && guard__h532422 != 2'b10 &&
		guard__h532422 != 2'b11 ||
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
		   coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
		   32'hFFFFFFFF ||
		   !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(guard__h532422 or
	  _theResult___snd__h540334 or _theResult___sfd__h541039)
  begin
    case (guard__h532422)
      2'b0:
	  CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q205 =
	      _theResult___snd__h540334[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q205 =
	      _theResult___sfd__h541039;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___snd__h540334 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10595 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10593 or
	  CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q205)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 =
	      _theResult___snd__h540334[56:5];
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10595;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10593;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 =
	      CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q205;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 =
		   52'd0;
    endcase
  end
  always@(guard__h532422 or
	  _theResult___snd__h540334 or
	  out_sfd__h541042 or _theResult___sfd__h541039)
  begin
    case (guard__h532422)
      2'b0, 2'b01:
	  CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q206 =
	      _theResult___snd__h540334[56:5];
      2'b10:
	  CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q206 =
	      out_sfd__h541042;
      2'b11:
	  CASE_guard32422_0b0_theResult___snd40334_BITS__ETC__q206 =
	      _theResult___sfd__h541039;
    endcase
  end
  always@(guard__h541734 or sfdin__h549954 or _theResult___sfd__h550690)
  begin
    case (guard__h541734)
      2'b0:
	  CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207 =
	      sfdin__h549954[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207 =
	      _theResult___sfd__h550690;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  sfdin__h549954 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619 or
	  CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 =
	      sfdin__h549954[56:5];
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 =
	      CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q207;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 =
		   52'd0;
    endcase
  end
  always@(guard__h541734 or
	  sfdin__h549954 or out_sfd__h550693 or _theResult___sfd__h550690)
  begin
    case (guard__h541734)
      2'b0, 2'b01:
	  CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 =
	      sfdin__h549954[56:5];
      2'b10:
	  CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 =
	      out_sfd__h550693;
      2'b11:
	  CASE_guard41734_0b0_sfdin49954_BITS_56_TO_5_0b_ETC__q208 =
	      _theResult___sfd__h550690;
    endcase
  end
  always@(guard__h550803 or
	  _theResult___snd__h558739 or _theResult___sfd__h559474)
  begin
    case (guard__h550803)
      2'b0:
	  CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209 =
	      _theResult___snd__h558739[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209 =
	      _theResult___sfd__h559474;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___snd__h558739 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638 or
	  CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 =
	      _theResult___snd__h558739[56:5];
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 =
	      CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q209;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 =
		   52'd0;
    endcase
  end
  always@(guard__h550803 or
	  _theResult___snd__h558739 or
	  out_sfd__h559477 or _theResult___sfd__h559474)
  begin
    case (guard__h550803)
      2'b0, 2'b01:
	  CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 =
	      _theResult___snd__h558739[56:5];
      2'b10:
	  CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 =
	      out_sfd__h559477;
      2'b11:
	  CASE_guard50803_0b0_theResult___snd58739_BITS__ETC__q210 =
	      _theResult___sfd__h559474;
    endcase
  end
  always@(guard__h502881 or
	  _theResult___fst_exp__h511107 or _theResult___exp__h511836)
  begin
    case (guard__h502881)
      2'b0:
	  CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q211 =
	      _theResult___fst_exp__h511107;
      2'b01, 2'b10, 2'b11:
	  CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q211 =
	      _theResult___exp__h511836;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___fst_exp__h511107 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9058 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056 or
	  CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q211)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 =
	      _theResult___fst_exp__h511107;
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9058;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 =
	      CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q211;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 =
		   11'd0;
    endcase
  end
  always@(guard__h502881 or
	  _theResult___fst_exp__h511107 or
	  out_exp__h511839 or _theResult___exp__h511836)
  begin
    case (guard__h502881)
      2'b0, 2'b01:
	  CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q212 =
	      _theResult___fst_exp__h511107;
      2'b10:
	  CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q212 =
	      out_exp__h511839;
      2'b11:
	  CASE_guard02881_0b0_theResult___fst_exp11107_0_ETC__q212 =
	      _theResult___exp__h511836;
    endcase
  end
  always@(guard__h511950 or
	  _theResult___fst_exp__h519940 or _theResult___exp__h520620)
  begin
    case (guard__h511950)
      2'b0:
	  CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q213 =
	      _theResult___fst_exp__h519940;
      2'b01, 2'b10, 2'b11:
	  CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q213 =
	      _theResult___exp__h520620;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___fst_exp__h519940 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9089 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9087 or
	  CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q213)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 =
	      _theResult___fst_exp__h519940;
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9089;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9087;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 =
	      CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q213;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 =
		   11'd0;
    endcase
  end
  always@(guard__h511950 or
	  _theResult___fst_exp__h519940 or
	  out_exp__h520623 or _theResult___exp__h520620)
  begin
    case (guard__h511950)
      2'b0, 2'b01:
	  CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q214 =
	      _theResult___fst_exp__h519940;
      2'b10:
	  CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q214 =
	      out_exp__h520623;
      2'b11:
	  CASE_guard11950_0b0_theResult___fst_exp19940_0_ETC__q214 =
	      _theResult___exp__h520620;
    endcase
  end
  always@(guard__h493569 or
	  _theResult___snd__h501481 or _theResult___sfd__h502186)
  begin
    case (guard__h493569)
      2'b0:
	  CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215 =
	      _theResult___snd__h501481[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215 =
	      _theResult___sfd__h502186;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___snd__h501481 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113 or
	  CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 =
	      _theResult___snd__h501481[56:5];
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 =
	      CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q215;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 =
		   52'd0;
    endcase
  end
  always@(guard__h493569 or
	  _theResult___snd__h501481 or
	  out_sfd__h502189 or _theResult___sfd__h502186)
  begin
    case (guard__h493569)
      2'b0, 2'b01:
	  CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 =
	      _theResult___snd__h501481[56:5];
      2'b10:
	  CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 =
	      out_sfd__h502189;
      2'b11:
	  CASE_guard93569_0b0_theResult___snd01481_BITS__ETC__q216 =
	      _theResult___sfd__h502186;
    endcase
  end
  always@(guard__h511950 or
	  _theResult___snd__h519886 or _theResult___sfd__h520621)
  begin
    case (guard__h511950)
      2'b0:
	  CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217 =
	      _theResult___snd__h519886[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217 =
	      _theResult___sfd__h520621;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___snd__h519886 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159 or
	  CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 =
	      _theResult___snd__h519886[56:5];
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 =
	      CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q217;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 =
		   52'd0;
    endcase
  end
  always@(guard__h511950 or
	  _theResult___snd__h519886 or
	  out_sfd__h520624 or _theResult___sfd__h520621)
  begin
    case (guard__h511950)
      2'b0, 2'b01:
	  CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218 =
	      _theResult___snd__h519886[56:5];
      2'b10:
	  CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218 =
	      out_sfd__h520624;
      2'b11:
	  CASE_guard11950_0b0_theResult___snd19886_BITS__ETC__q218 =
	      _theResult___sfd__h520621;
    endcase
  end
  always@(guard__h502881 or sfdin__h511101 or _theResult___sfd__h511837)
  begin
    case (guard__h502881)
      2'b0:
	  CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219 =
	      sfdin__h511101[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219 =
	      _theResult___sfd__h511837;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  sfdin__h511101 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140 or
	  CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 =
	      sfdin__h511101[56:5];
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 =
	      CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q219;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 =
		   52'd0;
    endcase
  end
  always@(guard__h502881 or
	  sfdin__h511101 or out_sfd__h511840 or _theResult___sfd__h511837)
  begin
    case (guard__h502881)
      2'b0, 2'b01:
	  CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220 =
	      sfdin__h511101[56:5];
      2'b10:
	  CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220 =
	      out_sfd__h511840;
      2'b11:
	  CASE_guard02881_0b0_sfdin11101_BITS_56_TO_5_0b_ETC__q220 =
	      _theResult___sfd__h511837;
    endcase
  end
  always@(guard__h571726 or
	  _theResult___snd__h579638 or _theResult___sfd__h580343)
  begin
    case (guard__h571726)
      2'b0:
	  CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q221 =
	      _theResult___snd__h579638[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q221 =
	      _theResult___sfd__h580343;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___snd__h579638 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9825 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9823 or
	  CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q221)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 =
	      _theResult___snd__h579638[56:5];
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9825;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9823;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 =
	      CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q221;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 =
		   52'd0;
    endcase
  end
  always@(guard__h571726 or
	  _theResult___snd__h579638 or
	  out_sfd__h580346 or _theResult___sfd__h580343)
  begin
    case (guard__h571726)
      2'b0, 2'b01:
	  CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q222 =
	      _theResult___snd__h579638[56:5];
      2'b10:
	  CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q222 =
	      out_sfd__h580346;
      2'b11:
	  CASE_guard71726_0b0_theResult___snd79638_BITS__ETC__q222 =
	      _theResult___sfd__h580343;
    endcase
  end
  always@(guard__h581038 or sfdin__h589258 or _theResult___sfd__h589994)
  begin
    case (guard__h581038)
      2'b0:
	  CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q223 =
	      sfdin__h589258[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q223 =
	      _theResult___sfd__h589994;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  sfdin__h589258 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9851 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9849 or
	  CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q223)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 =
	      sfdin__h589258[56:5];
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9851;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9849;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 =
	      CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q223;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 =
		   52'd0;
    endcase
  end
  always@(guard__h581038 or
	  sfdin__h589258 or out_sfd__h589997 or _theResult___sfd__h589994)
  begin
    case (guard__h581038)
      2'b0, 2'b01:
	  CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q224 =
	      sfdin__h589258[56:5];
      2'b10:
	  CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q224 =
	      out_sfd__h589997;
      2'b11:
	  CASE_guard81038_0b0_sfdin89258_BITS_56_TO_5_0b_ETC__q224 =
	      _theResult___sfd__h589994;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10888 or
	  NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 or
	  NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10865)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
      5'd0, 5'd1, 5'd2, 5'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10890 =
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876;
      5'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10890 =
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10865;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10890 =
		   coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10888;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10852 or
	  NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807 or
	  NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10765)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
      5'd0, 5'd1, 5'd2, 5'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10854 =
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807;
      5'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10854 =
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10765;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10854 =
		   coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10852;
    endcase
  end
  always@(guard__h590107 or
	  _theResult___snd__h598043 or _theResult___sfd__h598778)
  begin
    case (guard__h590107)
      2'b0:
	  CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q225 =
	      _theResult___snd__h598043[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q225 =
	      _theResult___sfd__h598778;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___snd__h598043 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9870 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9868 or
	  CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q225)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 =
	      _theResult___snd__h598043[56:5];
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9870;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9868;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 =
	      CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q225;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 =
		   52'd0;
    endcase
  end
  always@(guard__h590107 or
	  _theResult___snd__h598043 or
	  out_sfd__h598781 or _theResult___sfd__h598778)
  begin
    case (guard__h590107)
      2'b0, 2'b01:
	  CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q226 =
	      _theResult___snd__h598043[56:5];
      2'b10:
	  CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q226 =
	      out_sfd__h598781;
      2'b11:
	  CASE_guard90107_0b0_theResult___snd98043_BITS__ETC__q226 =
	      _theResult___sfd__h598778;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10936 or
	  NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920 or
	  NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10905)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
      5'd0, 5'd1, 5'd2, 5'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10938 =
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920;
      5'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10938 =
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10905;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10938 =
		   coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10936;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10978 or
	  NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964 or
	  NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10951)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
      5'd0, 5'd1, 5'd2, 5'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10980 =
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964;
      5'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10980 =
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10951;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10980 =
		   coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10978;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d11020 or
	  NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006 or
	  NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10993)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
      5'd0, 5'd1, 5'd2, 5'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d11022 =
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006;
      5'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d11022 =
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10993;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d11022 =
		   coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d11020;
    endcase
  end
  always@(coreFix_aluExe_1_regToExeQ$first)
  begin
    case (coreFix_aluExe_1_regToExeQ$first[399:397])
      3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
	  CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227 =
	      coreFix_aluExe_1_regToExeQ$first[399:397];
      default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227 = 3'd7;
    endcase
  end
  always@(coreFix_aluExe_1_regToExeQ$first or
	  CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227)
  begin
    case (coreFix_aluExe_1_regToExeQ$first[416:414])
      3'd3, 3'd2, 3'd1, 3'd0:
	  CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228 =
	      coreFix_aluExe_1_regToExeQ$first[416:396];
      3'd4:
	  CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228 =
	      { coreFix_aluExe_1_regToExeQ$first[416:414],
		9'h0AA,
		coreFix_aluExe_1_regToExeQ$first[404:400],
		CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227,
		coreFix_aluExe_1_regToExeQ$first[396] };
      default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228 =
		   { 3'd5, 18'h2AAAA };
    endcase
  end
  always@(coreFix_aluExe_1_regToExeQ$first)
  begin
    case (coreFix_aluExe_1_regToExeQ$first[394:383])
      12'd1971,
      12'd1970,
      12'd1969,
      12'd1968,
      12'd1955,
      12'd1954,
      12'd1953,
      12'd1952,
      12'd3860,
      12'd3859,
      12'd3858,
      12'd3857,
      12'd2818,
      12'd2816,
      12'd836,
      12'd835,
      12'd834,
      12'd833,
      12'd832,
      12'd774,
      12'd773,
      12'd772,
      12'd771,
      12'd770,
      12'd769,
      12'd768,
      12'd384,
      12'd324,
      12'd323,
      12'd322,
      12'd321,
      12'd320,
      12'd262,
      12'd261,
      12'd260,
      12'd256,
      12'd2049,
      12'd2048,
      12'd3074,
      12'd3073,
      12'd3072,
      12'd3,
      12'd2,
      12'd1:
	  CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229 =
	      coreFix_aluExe_1_regToExeQ$first[394:383];
      default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229 =
		   12'd2303;
    endcase
  end
  always@(coreFix_aluExe_0_regToExeQ$first)
  begin
    case (coreFix_aluExe_0_regToExeQ$first[399:397])
      3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
	  CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230 =
	      coreFix_aluExe_0_regToExeQ$first[399:397];
      default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230 = 3'd7;
    endcase
  end
  always@(coreFix_aluExe_0_regToExeQ$first or
	  CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230)
  begin
    case (coreFix_aluExe_0_regToExeQ$first[416:414])
      3'd3, 3'd2, 3'd1, 3'd0:
	  CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231 =
	      coreFix_aluExe_0_regToExeQ$first[416:396];
      3'd4:
	  CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231 =
	      { coreFix_aluExe_0_regToExeQ$first[416:414],
		9'h0AA,
		coreFix_aluExe_0_regToExeQ$first[404:400],
		CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230,
		coreFix_aluExe_0_regToExeQ$first[396] };
      default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231 =
		   { 3'd5, 18'h2AAAA };
    endcase
  end
  always@(coreFix_aluExe_0_regToExeQ$first)
  begin
    case (coreFix_aluExe_0_regToExeQ$first[394:383])
      12'd1971,
      12'd1970,
      12'd1969,
      12'd1968,
      12'd1955,
      12'd1954,
      12'd1953,
      12'd1952,
      12'd3860,
      12'd3859,
      12'd3858,
      12'd3857,
      12'd2818,
      12'd2816,
      12'd836,
      12'd835,
      12'd834,
      12'd833,
      12'd832,
      12'd774,
      12'd773,
      12'd772,
      12'd771,
      12'd770,
      12'd769,
      12'd768,
      12'd384,
      12'd324,
      12'd323,
      12'd322,
      12'd321,
      12'd320,
      12'd262,
      12'd261,
      12'd260,
      12'd256,
      12'd2049,
      12'd2048,
      12'd3074,
      12'd3073,
      12'd3072,
      12'd3,
      12'd2,
      12'd1:
	  CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232 =
	      coreFix_aluExe_0_regToExeQ$first[394:383];
      default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232 =
		   12'd2303;
    endcase
  end
  always@(fetchStage$pipelines_0_first)
  begin
    case (fetchStage$pipelines_0_first[172:161])
      12'd1,
      12'd2,
      12'd3,
      12'd256,
      12'd260,
      12'd261,
      12'd262,
      12'd320,
      12'd321,
      12'd322,
      12'd323,
      12'd324,
      12'd384,
      12'd768,
      12'd769,
      12'd770,
      12'd771,
      12'd772,
      12'd773,
      12'd774,
      12'd832,
      12'd833,
      12'd834,
      12'd835,
      12'd836,
      12'd1952,
      12'd1953,
      12'd1954,
      12'd1955,
      12'd1968,
      12'd1969,
      12'd1970,
      12'd1971,
      12'd2048,
      12'd2049,
      12'd2816,
      12'd2818,
      12'd3072,
      12'd3073,
      12'd3074,
      12'd3857,
      12'd3858,
      12'd3859,
      12'd3860:
	  IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973 =
	      fetchStage$pipelines_0_first[172:161];
      default: IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973 =
		   12'd2303;
    endcase
  end
  always@(fetchStage$pipelines_0_first)
  begin
    case (fetchStage$pipelines_0_first[67:64])
      4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9:
	  IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 =
	      fetchStage$pipelines_0_first[67:64];
      4'd11:
	  IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 = 4'd10;
      4'd12:
	  IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 = 4'd11;
      4'd13:
	  IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 = 4'd12;
      default: IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 =
		   4'd13;
    endcase
  end
  always@(fetchStage$pipelines_0_first)
  begin
    case (fetchStage$pipelines_0_first[177:175])
      3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
	  CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233 =
	      fetchStage$pipelines_0_first[177:175];
      default: CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233 = 3'd7;
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1, 3'd2, 3'd3:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883 =
	      fetchStage$pipelines_0_first[194:174];
      3'd4:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883 =
	      { fetchStage$pipelines_0_first[194:192],
		9'h0AA,
		fetchStage$pipelines_0_first[182:178],
		CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233,
		fetchStage$pipelines_0_first[174] };
      default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883 =
		   21'd1485482;
    endcase
  end
  always@(checkForException___d13008)
  begin
    case (checkForException___d13008[3:0])
      4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9:
	  CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234 =
	      checkForException___d13008[3:0];
      4'd11: CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234 = 4'd10;
      4'd12: CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234 = 4'd11;
      4'd13: CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234 = 4'd12;
      default: CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234 =
		   4'd13;
    endcase
  end
  always@(k__h670634 or
	  coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq)
  begin
    case (k__h670634)
      1'd0:
	  SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 =
	      coreFix_aluExe_0_rsAlu$canEnq;
      1'd1:
	  SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 =
	      coreFix_aluExe_1_rsAlu$canEnq;
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_0_first[191:189])
      3'd0, 3'd2:
	  IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 =
	      coreFix_memExe_lsq$enqLdTag[6];
      default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 =
		   coreFix_memExe_lsq$enqStTag[6];
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_rsMem$canEnq or
	  IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 or
	  SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13480 =
	      SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13480 =
	      coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
      default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13480 =
		   fetchStage$pipelines_0_first[194:192] != 3'd2 ||
		   coreFix_memExe_rsMem$canEnq &&
		   IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476;
    endcase
  end
  always@(k__h670634 or
	  coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq)
  begin
    case (k__h670634)
      1'd0:
	  SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 =
	      !coreFix_aluExe_0_rsAlu$canEnq;
      1'd1:
	  SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 =
	      !coreFix_aluExe_1_rsAlu$canEnq;
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444 or
	  NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13499 or
	  coreFix_memExe_rsMem$canEnq or
	  IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 =
	      NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13499;
      3'd2:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 =
	      coreFix_memExe_rsMem$canEnq &&
	      IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 &&
	      regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 =
	      coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq &&
	      regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444;
      default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13504 =
		   regRenamingTable_rename_0_canRename__3418_AND__ETC___d13444;
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_0_first[191:189])
      3'd0, 3'd2:
	  IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 =
	      !coreFix_memExe_lsq$enqLdTag[6];
      default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 =
		   !coreFix_memExe_lsq$enqStTag[6];
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_rsMem$canEnq or
	  IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 or
	  SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 or
	  specTagManager$canClaim or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13539 =
	      SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 ||
	      fetchStage$pipelines_0_first[194:192] == 3'd1 &&
	      !specTagManager$canClaim;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13539 =
	      !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
      default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13539 =
		   fetchStage$pipelines_0_first[194:192] == 3'd2 &&
		   (!coreFix_memExe_rsMem$canEnq ||
		    IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534);
    endcase
  end
  always@(fetchStage$pipelines_1_first)
  begin
    case (fetchStage$pipelines_1_first[172:161])
      12'd1,
      12'd2,
      12'd3,
      12'd256,
      12'd260,
      12'd261,
      12'd262,
      12'd320,
      12'd321,
      12'd322,
      12'd323,
      12'd324,
      12'd384,
      12'd768,
      12'd769,
      12'd770,
      12'd771,
      12'd772,
      12'd773,
      12'd774,
      12'd832,
      12'd833,
      12'd834,
      12'd835,
      12'd836,
      12'd1952,
      12'd1953,
      12'd1954,
      12'd1955,
      12'd1968,
      12'd1969,
      12'd1970,
      12'd1971,
      12'd2048,
      12'd2049,
      12'd2816,
      12'd2818,
      12'd3072,
      12'd3073,
      12'd3074,
      12'd3857,
      12'd3858,
      12'd3859,
      12'd3860:
	  CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 =
	      fetchStage$pipelines_1_first[172:161];
      default: CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 =
		   12'd2303;
    endcase
  end
  always@(fetchStage$pipelines_1_first)
  begin
    case (fetchStage$pipelines_1_first[177:175])
      3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
	  CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236 =
	      fetchStage$pipelines_1_first[177:175];
      default: CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236 = 3'd7;
    endcase
  end
  always@(fetchStage$pipelines_1_first or
	  CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236)
  begin
    case (fetchStage$pipelines_1_first[194:192])
      3'd0, 3'd1, 3'd2, 3'd3:
	  IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599 =
	      fetchStage$pipelines_1_first[194:174];
      3'd4:
	  IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599 =
	      { fetchStage$pipelines_1_first[194:192],
		9'h0AA,
		fetchStage$pipelines_1_first[182:178],
		CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236,
		fetchStage$pipelines_1_first[174] };
      default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13599 =
		   21'd1485482;
    endcase
  end
  always@(idx__h686379 or
	  fetchStage$pipelines_0_canDeq or
	  NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13761 or
	  coreFix_aluExe_0_rsAlu$canEnq or
	  NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13767 or
	  coreFix_aluExe_1_rsAlu$canEnq)
  begin
    case (idx__h686379)
      1'd0:
	  SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787 =
	      fetchStage$pipelines_0_canDeq &&
	      NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13761 ||
	      !coreFix_aluExe_0_rsAlu$canEnq;
      1'd1:
	  SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787 =
	      fetchStage$pipelines_0_canDeq &&
	      NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13767 ||
	      !coreFix_aluExe_1_rsAlu$canEnq;
    endcase
  end
  always@(fetchStage$pipelines_1_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_1_first[191:189])
      3'd0, 3'd2:
	  CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 =
	      !coreFix_memExe_lsq$enqLdTag[6];
      default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 =
		   !coreFix_memExe_lsq$enqStTag[6];
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855 or
	  SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 or
	  fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13859 or
	  coreFix_memExe_rsMem$canEnq or
	  IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13865 =
	      SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 ||
	      fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13859;
      3'd2:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13865 =
	      !coreFix_memExe_rsMem$canEnq ||
	      IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 ||
	      renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13865 =
	      !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
	      renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855;
      default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13865 =
		   renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13855;
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_rsMem$canEnq or
	  IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 or
	  SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13887 =
	      SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463;
      default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13887 =
		   fetchStage$pipelines_0_first[194:192] != 3'd2 ||
		   coreFix_memExe_rsMem$canEnq &&
		   IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476;
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 or
	  SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13905 =
	      SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13905 =
	      coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
      default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13905 =
		   fetchStage$pipelines_0_first[194:192] != 3'd2 ||
		   IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476;
    endcase
  end
  always@(fetchStage$pipelines_1_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_1_first[191:189])
      3'd0, 3'd2:
	  CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 =
	      coreFix_memExe_lsq$enqLdTag[6];
      default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 =
		   coreFix_memExe_lsq$enqStTag[6];
    endcase
  end
  always@(fetchStage$pipelines_1_first or
	  regRenamingTable_rename_1_canRename__3545_AND__ETC___d13753 or
	  SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787 or
	  NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13871 or
	  NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13902 or
	  regRenamingTable_rename_1_canRename__3545_AND__ETC___d13913 or
	  NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13884 or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or
	  regRenamingTable_rename_1_canRename__3545_AND__ETC___d13895)
  begin
    case (fetchStage$pipelines_1_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 =
	      !SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787 &&
	      NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13871;
      3'd2:
	  IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 =
	      NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13902 &&
	      regRenamingTable_rename_1_canRename__3545_AND__ETC___d13913;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 =
	      NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13884 &&
	      coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq &&
	      regRenamingTable_rename_1_canRename__3545_AND__ETC___d13895;
      default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13917 =
		   regRenamingTable_rename_1_canRename__3545_AND__ETC___d13753;
    endcase
  end
  always@(k__h670634 or
	  coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq)
  begin
    case (k__h670634)
      1'd0:
	  CASE_k70634_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 =
	      coreFix_aluExe_0_rsAlu$RDY_enq;
      1'd1:
	  CASE_k70634_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 =
	      coreFix_aluExe_1_rsAlu$RDY_enq;
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd)
  begin
    case (fetchStage$pipelines_0_first[191:189])
      3'd0, 3'd2:
	  CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 =
	      coreFix_memExe_lsq$RDY_enqLd;
      default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 =
		   coreFix_memExe_lsq$RDY_enqSt;
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_rsMem$canEnq or
	  IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 or
	  SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962 =
	      SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962 =
	      !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
      default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13962 =
		   fetchStage$pipelines_0_first[194:192] == 3'd2 &&
		   (!coreFix_memExe_rsMem$canEnq ||
		    IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534);
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_rsMem$canEnq or
	  IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 or
	  regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13956 or
	  SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 or
	  regRenamingTable$RDY_rename_0_getRename or
	  _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13943 or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13960 =
	      !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 ||
	      regRenamingTable$RDY_rename_0_getRename &&
	      _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13943;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13960 =
	      !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
	      coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq &&
	      regRenamingTable$RDY_rename_0_getRename;
      default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13960 =
		   fetchStage$pipelines_0_first[194:192] != 3'd2 ||
		   !coreFix_memExe_rsMem$canEnq ||
		   IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 ||
		   regRenamingTable_RDY_rename_0_getRename__3300__ETC___d13956;
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_rsMem$canEnq or
	  IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 or
	  SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13976 =
	      !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13976 =
	      !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
      default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13976 =
		   fetchStage$pipelines_0_first[194:192] == 3'd2 &&
		   (!coreFix_memExe_rsMem$canEnq ||
		    IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534);
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_rsMem$canEnq or
	  IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476 or
	  SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 or
	  specTagManager$canClaim or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13983 =
	      !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__345_ETC___d13497 &&
	      (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	       specTagManager$canClaim);
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13983 =
	      coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
      default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13983 =
		   fetchStage$pipelines_0_first[194:192] != 3'd2 ||
		   coreFix_memExe_rsMem$canEnq &&
		   IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13476;
    endcase
  end
  always@(idx__h686379 or
	  fetchStage$pipelines_0_canDeq or
	  fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14006 or
	  coreFix_aluExe_0_rsAlu$canEnq or
	  fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14013 or
	  coreFix_aluExe_1_rsAlu$canEnq)
  begin
    case (idx__h686379)
      1'd0:
	  SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14017 =
	      (!fetchStage$pipelines_0_canDeq ||
	       fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14006) &&
	      coreFix_aluExe_0_rsAlu$canEnq;
      1'd1:
	  SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14017 =
	      (!fetchStage$pipelines_0_canDeq ||
	       fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14013) &&
	      coreFix_aluExe_1_rsAlu$canEnq;
    endcase
  end
  always@(fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14033 or
	  coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq)
  begin
    case (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14033)
      1'd0:
	  CASE_fetchStage_pipelines_0_canDeq__2755_AND_N_ETC__q241 =
	      coreFix_aluExe_0_rsAlu$RDY_enq;
      1'd1:
	  CASE_fetchStage_pipelines_0_canDeq__2755_AND_N_ETC__q241 =
	      coreFix_aluExe_1_rsAlu$RDY_enq;
    endcase
  end
  always@(fetchStage$pipelines_1_first or
	  coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd)
  begin
    case (fetchStage$pipelines_1_first[191:189])
      3'd0, 3'd2:
	  CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242 =
	      coreFix_memExe_lsq$RDY_enqLd;
      default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242 =
		   coreFix_memExe_lsq$RDY_enqSt;
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_rsMem$canEnq or
	  IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 or
	  SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14059 =
	      !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463;
      default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14059 =
		   fetchStage$pipelines_0_first[194:192] == 3'd2 &&
		   (!coreFix_memExe_rsMem$canEnq ||
		    IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534);
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534 or
	  SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463 or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14071 =
	      !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3453_co_ETC___d13463;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14071 =
	      !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
      default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14071 =
		   fetchStage$pipelines_0_first[194:192] == 3'd2 &&
		   IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13534;
    endcase
  end
  always@(fetchStage$pipelines_1_first or
	  fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14080 or
	  SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787 or
	  fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14068)
  begin
    case (fetchStage$pipelines_1_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14083 =
	      SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13787;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14083 =
	      fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14068;
      default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14083 =
		   fetchStage$pipelines_1_first[194:192] == 3'd2 &&
		   fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14080;
    endcase
  end
  always@(fetchStage$pipelines_1_first or
	  fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14046 or
	  regRenamingTable$RDY_rename_1_getRename or
	  NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14051 or
	  SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14017 or
	  regRenamingTable_RDY_rename_1_getRename__4019__ETC___d14037 or
	  fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14039 or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14042)
  begin
    case (fetchStage$pipelines_1_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14056 =
	      !SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14017 ||
	      regRenamingTable_RDY_rename_1_getRename__4019__ETC___d14037;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14056 =
	      fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14039 ||
	      !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
	      coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14042;
      default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14056 =
		   fetchStage$pipelines_1_first[194:192] != 3'd2 ||
		   fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14046 ||
		   regRenamingTable$RDY_rename_1_getRename &&
		   NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14051;
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_0_first[191:189])
      3'd0, 3'd2:
	  IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14140 =
	      !coreFix_memExe_lsq$enqLdTag[5];
      default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14140 =
		   !coreFix_memExe_lsq$enqStTag[5];
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_0_first[191:189])
      3'd0, 3'd2:
	  IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137 =
	      coreFix_memExe_lsq$enqLdTag[5];
      default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14137 =
		   coreFix_memExe_lsq$enqStTag[5];
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_0_first[191:189])
      3'd0, 3'd2:
	  IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 =
	      coreFix_memExe_lsq$enqLdTag[3:0];
      default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14146 =
		   coreFix_memExe_lsq$enqStTag[3:0];
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_0_first[191:189])
      3'd0, 3'd2:
	  IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14143 =
	      coreFix_memExe_lsq$enqLdTag[4:0];
      default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14143 =
		   coreFix_memExe_lsq$enqStTag[4:0];
    endcase
  end
  always@(fetchStage$pipelines_1_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_1_first[191:189])
      3'd0, 3'd2:
	  IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14277 =
	      coreFix_memExe_lsq$enqLdTag[3:0];
      default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14277 =
		   coreFix_memExe_lsq$enqStTag[3:0];
    endcase
  end
  always@(fetchStage$pipelines_1_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_1_first[191:189])
      3'd0, 3'd2:
	  IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14275 =
	      !coreFix_memExe_lsq$enqLdTag[5];
      default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14275 =
		   !coreFix_memExe_lsq$enqStTag[5];
    endcase
  end
  always@(fetchStage$pipelines_1_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_1_first[191:189])
      3'd0, 3'd2:
	  IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14274 =
	      coreFix_memExe_lsq$enqLdTag[5];
      default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14274 =
		   coreFix_memExe_lsq$enqStTag[5];
    endcase
  end
  always@(fetchStage$pipelines_1_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_1_first[191:189])
      3'd0, 3'd2:
	  IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14276 =
	      coreFix_memExe_lsq$enqLdTag[4:0];
      default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14276 =
		   coreFix_memExe_lsq$enqStTag[4:0];
    endcase
  end
  always@(csrf_prv_reg or csrf_rg_dcsr)
  begin
    case (csrf_prv_reg)
      2'd1:
	  CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 =
	      !csrf_rg_dcsr[13];
      2'd3:
	  CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 =
	      !csrf_rg_dcsr[15];
      default: CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 =
		   !csrf_rg_dcsr[12];
    endcase
  end
  always@(csrf_prv_reg or csrf_rg_dcsr)
  begin
    case (csrf_prv_reg)
      2'd1:
	  CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 =
	      csrf_rg_dcsr[13];
      2'd3:
	  CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 =
	      csrf_rg_dcsr[15];
      default: CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 =
		   csrf_rg_dcsr[12];
    endcase
  end
  always@(rob$deqPort_0_deq_data)
  begin
    case (rob$deqPort_0_deq_data[180:169])
      12'd1:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd0;
      12'd2:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd1;
      12'd3:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd2;
      12'd256:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd8;
      12'd260:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd9;
      12'd261:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd10;
      12'd262:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd11;
      12'd320:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd12;
      12'd321:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd13;
      12'd322:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd14;
      12'd323:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd15;
      12'd324:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd16;
      12'd384:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd17;
      12'd768:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd18;
      12'd769:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd19;
      12'd770:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd20;
      12'd771:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd21;
      12'd772:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd22;
      12'd773:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd23;
      12'd774:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd24;
      12'd832:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd25;
      12'd833:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd26;
      12'd834:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd27;
      12'd835:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd28;
      12'd836:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd29;
      12'd1952:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd36;
      12'd1953:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd37;
      12'd1954:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd38;
      12'd1955:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd39;
      12'd1968:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd40;
      12'd1969:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd41;
      12'd1970:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd42;
      12'd1971:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd43;
      12'd2048:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd6;
      12'd2049:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd7;
      12'd2816:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd30;
      12'd2818:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd31;
      12'd3072:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd3;
      12'd3073:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd4;
      12'd3074:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd5;
      12'd3857:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd32;
      12'd3858:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd33;
      12'd3859:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd34;
      12'd3860:
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 = 6'd35;
      default: IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 =
		   6'd44;
    endcase
  end
  always@(IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 or
	  rob$deqPort_0_deq_data or
	  robdeqPort_0_deq_data_BITS_95_TO_32__q245 or
	  r1__read__h614523 or
	  csrf_timer_int_pend_vec_3 or csrf_software_int_pend_vec_3)
  begin
    case (IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998)
      6'd0:
	  data_warl_xformed__h723426 =
	      { 59'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] };
      6'd1, 6'd11, 6'd24:
	  data_warl_xformed__h723426 =
	      { 61'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[2:0] };
      6'd2:
	  data_warl_xformed__h723426 =
	      { 56'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[7:0] };
      6'd8:
	  data_warl_xformed__h723426 =
	      { robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11,
		43'd8192,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[19:18],
		3'd0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13],
		4'b0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[8],
		2'b0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:4],
		2'b0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] };
      6'd9, 6'd16, 6'd22:
	  data_warl_xformed__h723426 =
	      { 54'd0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[9],
		3'd0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[5],
		3'd0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[1],
		1'd0 };
      6'd10, 6'd23:
	  data_warl_xformed__h723426 =
	      { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63:2],
		1'b0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[0] };
      6'd14, 6'd27:
	  data_warl_xformed__h723426 =
	      { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63],
		59'b0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[3:0] };
      6'd17:
	  data_warl_xformed__h723426 =
	      { robdeqPort_0_deq_data_BITS_95_TO_32__q245[63],
		19'd0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[43:0] };
      6'd18:
	  data_warl_xformed__h723426 =
	      { robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11,
		40'd5120,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[22:17],
		2'b0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:11],
		2'b0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[8:7],
		1'b0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:3],
		1'b0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] };
      6'd19: data_warl_xformed__h723426 = 64'h800000000014112D;
      6'd20:
	  data_warl_xformed__h723426 =
	      { 48'b0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[15],
		1'b0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[13:11],
		1'b0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[9:0] };
      6'd21:
	  data_warl_xformed__h723426 =
	      { 52'b0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[11],
		1'b0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[9:7],
		1'b0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:3],
		1'b0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] };
      6'd29:
	  data_warl_xformed__h723426 =
	      { r1__read__h614523,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[9],
		1'b0,
		csrf_timer_int_pend_vec_3,
		1'b0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[5],
		1'b0,
		csrf_software_int_pend_vec_3,
		1'b0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[1],
		1'd0 };
      6'd32, 6'd33, 6'd34, 6'd35: data_warl_xformed__h723426 = 64'd0;
      6'd37:
	  data_warl_xformed__h723426 =
	      { 4'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[59:0] };
      6'd40:
	  data_warl_xformed__h723426 =
	      { 32'b0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[31:28],
		12'b0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[14],
		1'b0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[13:6],
		1'b0,
		robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] };
      default: data_warl_xformed__h723426 = rob$deqPort_0_deq_data[95:32];
    endcase
  end
  always@(rob$deqPort_0_deq_data or
	  IF_rob_deqPort_0_deq_data__4354_BITS_329_TO_32_ETC___d15205)
  begin
    case (rob$deqPort_0_deq_data[329:325])
      5'd19, 5'd20:
	  x__h724034 =
	      IF_rob_deqPort_0_deq_data__4354_BITS_329_TO_32_ETC___d15205;
      default: x__h724034 = rob$deqPort_0_deq_data[425:362];
    endcase
  end
  always@(rob$deqPort_0_deq_data)
  begin
    case (rob$deqPort_0_deq_data[180:169])
      12'd1,
      12'd2,
      12'd3,
      12'd256,
      12'd260,
      12'd261,
      12'd262,
      12'd320,
      12'd321,
      12'd322,
      12'd323,
      12'd324,
      12'd384,
      12'd768,
      12'd769,
      12'd770,
      12'd771,
      12'd772,
      12'd773,
      12'd774,
      12'd832,
      12'd833,
      12'd834,
      12'd835,
      12'd836,
      12'd1952,
      12'd1953,
      12'd1954,
      12'd1955,
      12'd1968,
      12'd1969,
      12'd1970,
      12'd1971,
      12'd2048,
      12'd2049,
      12'd2816,
      12'd2818,
      12'd3072,
      12'd3073,
      12'd3074,
      12'd3857,
      12'd3858,
      12'd3859,
      12'd3860:
	  CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 =
	      rob$deqPort_0_deq_data[180:169];
      default: CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q246 =
		   12'd2303;
    endcase
  end
  always@(rob$deqPort_0_deq_data)
  begin
    case (rob$deqPort_0_deq_data[165:162])
      4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
	  CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 =
	      rob$deqPort_0_deq_data[165:162];
      default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q247 =
		   4'd15;
    endcase
  end
  always@(rob$deqPort_0_deq_data)
  begin
    case (rob$deqPort_0_deq_data[165:162])
      4'd0,
      4'd1,
      4'd2,
      4'd3,
      4'd4,
      4'd5,
      4'd6,
      4'd7,
      4'd8,
      4'd9,
      4'd11,
      4'd12,
      4'd13:
	  CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 =
	      rob$deqPort_0_deq_data[165:162];
      default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q248 =
		   4'd15;
    endcase
  end
  always@(commitStage_f_rob_data$D_OUT)
  begin
    case (commitStage_f_rob_data$D_OUT[97:96])
      2'd0, 2'd1:
	  CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q249 =
	      commitStage_f_rob_data$D_OUT[97:96];
      default: CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q249 = 2'd2;
    endcase
  end
  always@(commitStage_f_rob_data$D_OUT)
  begin
    case (commitStage_f_rob_data$D_OUT[165:162])
      4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
	  CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250 =
	      commitStage_f_rob_data$D_OUT[165:162];
      default: CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q250 =
		   4'd15;
    endcase
  end
  always@(commitStage_f_rob_data$D_OUT)
  begin
    case (commitStage_f_rob_data$D_OUT[165:162])
      4'd0,
      4'd1,
      4'd2,
      4'd3,
      4'd4,
      4'd5,
      4'd6,
      4'd7,
      4'd8,
      4'd9,
      4'd11,
      4'd12,
      4'd13:
	  CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251 =
	      commitStage_f_rob_data$D_OUT[165:162];
      default: CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q251 =
		   4'd15;
    endcase
  end
  always@(rob$deqPort_0_deq_data)
  begin
    case (rob$deqPort_0_deq_data[97:96])
      2'd0, 2'd1:
	  CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q252 =
	      rob$deqPort_0_deq_data[97:96];
      default: CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q252 = 2'd2;
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[511:448];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q253 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[511:448];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[447:384];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q254 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[447:384];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[383:320];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q255 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[383:320];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[319:256];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[319:256];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[255:192];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[255:192];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[191:128];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[191:128];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226];
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd4;
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd3;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd2;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd1;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 =
		   3'd0;
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or
	  coreFix_memExe_stb$deq or
	  coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150 or
	  IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2208)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79])
      3'd0, 3'd2, 3'd4:
	  IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2500 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0];
      3'd1:
	  IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2500 =
	      { coreFix_memExe_stb$deq[575] ?
		  coreFix_memExe_stb$deq[511:504] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:504],
		coreFix_memExe_stb$deq[574] ?
		  coreFix_memExe_stb$deq[503:496] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[503:496],
		coreFix_memExe_stb$deq[573] ?
		  coreFix_memExe_stb$deq[495:488] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[495:488],
		coreFix_memExe_stb$deq[572] ?
		  coreFix_memExe_stb$deq[487:480] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[487:480],
		coreFix_memExe_stb$deq[571] ?
		  coreFix_memExe_stb$deq[479:472] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[479:472],
		coreFix_memExe_stb$deq[570] ?
		  coreFix_memExe_stb$deq[471:464] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[471:464],
		coreFix_memExe_stb$deq[569] ?
		  coreFix_memExe_stb$deq[463:456] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[463:456],
		coreFix_memExe_stb$deq[568] ?
		  coreFix_memExe_stb$deq[455:448] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[455:448],
		coreFix_memExe_stb$deq[567] ?
		  coreFix_memExe_stb$deq[447:440] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:440],
		coreFix_memExe_stb$deq[566] ?
		  coreFix_memExe_stb$deq[439:432] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[439:432],
		coreFix_memExe_stb$deq[565] ?
		  coreFix_memExe_stb$deq[431:424] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[431:424],
		coreFix_memExe_stb$deq[564] ?
		  coreFix_memExe_stb$deq[423:416] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[423:416],
		coreFix_memExe_stb$deq[563] ?
		  coreFix_memExe_stb$deq[415:408] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[415:408],
		coreFix_memExe_stb$deq[562] ?
		  coreFix_memExe_stb$deq[407:400] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[407:400],
		coreFix_memExe_stb$deq[561] ?
		  coreFix_memExe_stb$deq[399:392] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[399:392],
		coreFix_memExe_stb$deq[560] ?
		  coreFix_memExe_stb$deq[391:384] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[391:384],
		coreFix_memExe_stb$deq[559] ?
		  coreFix_memExe_stb$deq[383:376] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:376],
		coreFix_memExe_stb$deq[558] ?
		  coreFix_memExe_stb$deq[375:368] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[375:368],
		coreFix_memExe_stb$deq[557] ?
		  coreFix_memExe_stb$deq[367:360] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[367:360],
		coreFix_memExe_stb$deq[556] ?
		  coreFix_memExe_stb$deq[359:352] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[359:352],
		coreFix_memExe_stb$deq[555] ?
		  coreFix_memExe_stb$deq[351:344] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[351:344],
		coreFix_memExe_stb$deq[554] ?
		  coreFix_memExe_stb$deq[343:336] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[343:336],
		coreFix_memExe_stb$deq[553] ?
		  coreFix_memExe_stb$deq[335:328] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[335:328],
		coreFix_memExe_stb$deq[552] ?
		  coreFix_memExe_stb$deq[327:320] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[327:320],
		coreFix_memExe_stb$deq[551] ?
		  coreFix_memExe_stb$deq[319:312] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:312],
		coreFix_memExe_stb$deq[550] ?
		  coreFix_memExe_stb$deq[311:304] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[311:304],
		coreFix_memExe_stb$deq[549] ?
		  coreFix_memExe_stb$deq[303:296] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[303:296],
		coreFix_memExe_stb$deq[548] ?
		  coreFix_memExe_stb$deq[295:288] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[295:288],
		coreFix_memExe_stb$deq[547] ?
		  coreFix_memExe_stb$deq[287:280] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[287:280],
		coreFix_memExe_stb$deq[546] ?
		  coreFix_memExe_stb$deq[279:272] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[279:272],
		coreFix_memExe_stb$deq[545] ?
		  coreFix_memExe_stb$deq[271:264] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[271:264],
		coreFix_memExe_stb$deq[544] ?
		  coreFix_memExe_stb$deq[263:256] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[263:256],
		coreFix_memExe_stb$deq[543] ?
		  coreFix_memExe_stb$deq[255:248] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:248],
		coreFix_memExe_stb$deq[542] ?
		  coreFix_memExe_stb$deq[247:240] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[247:240],
		coreFix_memExe_stb$deq[541] ?
		  coreFix_memExe_stb$deq[239:232] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[239:232],
		coreFix_memExe_stb$deq[540] ?
		  coreFix_memExe_stb$deq[231:224] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[231:224],
		coreFix_memExe_stb$deq[539] ?
		  coreFix_memExe_stb$deq[223:216] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[223:216],
		coreFix_memExe_stb$deq[538] ?
		  coreFix_memExe_stb$deq[215:208] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[215:208],
		coreFix_memExe_stb$deq[537] ?
		  coreFix_memExe_stb$deq[207:200] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[207:200],
		coreFix_memExe_stb$deq[536] ?
		  coreFix_memExe_stb$deq[199:192] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[199:192],
		coreFix_memExe_stb$deq[535] ?
		  coreFix_memExe_stb$deq[191:184] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:184],
		coreFix_memExe_stb$deq[534] ?
		  coreFix_memExe_stb$deq[183:176] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[183:176],
		coreFix_memExe_stb$deq[533] ?
		  coreFix_memExe_stb$deq[175:168] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[175:168],
		coreFix_memExe_stb$deq[532] ?
		  coreFix_memExe_stb$deq[167:160] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[167:160],
		coreFix_memExe_stb$deq[531] ?
		  coreFix_memExe_stb$deq[159:152] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[159:152],
		coreFix_memExe_stb$deq[530] ?
		  coreFix_memExe_stb$deq[151:144] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[151:144],
		coreFix_memExe_stb$deq[529] ?
		  coreFix_memExe_stb$deq[143:136] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[143:136],
		coreFix_memExe_stb$deq[528] ?
		  coreFix_memExe_stb$deq[135:128] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[135:128],
		coreFix_memExe_stb$deq[527] ?
		  coreFix_memExe_stb$deq[127:120] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:120],
		coreFix_memExe_stb$deq[526] ?
		  coreFix_memExe_stb$deq[119:112] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[119:112],
		coreFix_memExe_stb$deq[525] ?
		  coreFix_memExe_stb$deq[111:104] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[111:104],
		coreFix_memExe_stb$deq[524] ?
		  coreFix_memExe_stb$deq[103:96] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[103:96],
		coreFix_memExe_stb$deq[523] ?
		  coreFix_memExe_stb$deq[95:88] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[95:88],
		coreFix_memExe_stb$deq[522] ?
		  coreFix_memExe_stb$deq[87:80] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[87:80],
		coreFix_memExe_stb$deq[521] ?
		  coreFix_memExe_stb$deq[79:72] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[79:72],
		coreFix_memExe_stb$deq[520] ?
		  coreFix_memExe_stb$deq[71:64] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[71:64],
		coreFix_memExe_stb$deq[519] ?
		  coreFix_memExe_stb$deq[63:56] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:56],
		coreFix_memExe_stb$deq[518] ?
		  coreFix_memExe_stb$deq[55:48] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[55:48],
		coreFix_memExe_stb$deq[517] ?
		  coreFix_memExe_stb$deq[47:40] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[47:40],
		coreFix_memExe_stb$deq[516] ?
		  coreFix_memExe_stb$deq[39:32] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[39:32],
		coreFix_memExe_stb$deq[515] ?
		  coreFix_memExe_stb$deq[31:24] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[31:24],
		coreFix_memExe_stb$deq[514] ?
		  coreFix_memExe_stb$deq[23:16] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[23:16],
		coreFix_memExe_stb$deq[513] ?
		  coreFix_memExe_stb$deq[15:8] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[15:8],
		coreFix_memExe_stb$deq[512] ?
		  coreFix_memExe_stb$deq[7:0] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[7:0] };
      3'd3:
	  IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2500 =
	      coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150 ?
		IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2208 :
		coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0];
      default: IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2500 =
		   coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd4, 3'd3, 3'd2, 3'd1, 3'd0:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q259 = 3'd7;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9884 or
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9174 or
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9940)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
      5'd0, 5'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9944 =
	      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9174;
      5'd25:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9944 =
	      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9884;
      5'd26, 5'd27:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9944 =
	      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9940;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9944 =
		   IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9884;
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q260 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[130:67];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q260 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[130:67];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[66:3];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[66:3];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[127:64];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[127:64];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[63:0];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[63:0];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[578:515];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[578:515];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[514:513];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q265 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[514:513];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266 =
	      !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[512];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q266 =
	      !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[512];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q267 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[517:516];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q267 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[517:516];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268 =
	      !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[515];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268 =
	      !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[515];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq or
	  coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq or
	  coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq or
	  coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
      5'd0, 5'd1, 5'd2, 5'd25, 5'd26, 5'd27, 5'd28:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 =
	      coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq;
      5'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 =
	      coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq;
      5'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 =
	      coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 =
		   coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tready or
	  coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tready or
	  coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq or
	  coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init or
	  coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY or
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit or
	  coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[229:228])
      2'd0, 2'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8428 =
	      coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit != 2'd0 &&
	      coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8428 =
		   coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tready &&
		   coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tready &&
		   coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq &&
		   coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init &&
		   coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY;
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269 =
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[5:4];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269 =
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[5:4];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270 =
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[3];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270 =
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[3];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 =
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[2:0];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 =
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[2:0];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272 =
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[71:8];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q272 =
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[71:8];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273 =
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[7:6];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q273 =
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[7:6];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q274 =
	      !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q274 =
	      !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q275 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q275 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582];
    endcase
  end
  always@(mmio_dataReqQ_data_0)
  begin
    case (mmio_dataReqQ_data_0[77:76])
      2'd0, 2'd1, 2'd2:
	  CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q276 =
	      mmio_dataReqQ_data_0[77:72];
      2'd3:
	  CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q276 =
	      { 2'd3, mmio_dataReqQ_data_0[75:72] };
    endcase
  end
  always@(coreFix_memExe_lsq$firstSt)
  begin
    case (coreFix_memExe_lsq$firstSt[3:0])
      4'd0,
      4'd1,
      4'd2,
      4'd3,
      4'd4,
      4'd5,
      4'd6,
      4'd7,
      4'd8,
      4'd9,
      4'd11,
      4'd12,
      4'd13:
	  CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q277 =
	      coreFix_memExe_lsq$firstSt[3:0];
      default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q277 =
		   4'd15;
    endcase
  end
  always@(coreFix_memExe_lsq$firstLd)
  begin
    case (coreFix_memExe_lsq$firstLd[6:3])
      4'd0,
      4'd1,
      4'd2,
      4'd3,
      4'd4,
      4'd5,
      4'd6,
      4'd7,
      4'd8,
      4'd9,
      4'd11,
      4'd12,
      4'd13:
	  CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q278 =
	      coreFix_memExe_lsq$firstLd[6:3];
      default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q278 =
		   4'd15;
    endcase
  end
  always@(commitStage_f_rob_data$D_OUT)
  begin
    case (commitStage_f_rob_data$D_OUT[180:169])
      12'd1,
      12'd2,
      12'd3,
      12'd256,
      12'd260,
      12'd261,
      12'd262,
      12'd320,
      12'd321,
      12'd322,
      12'd323,
      12'd324,
      12'd384,
      12'd768,
      12'd769,
      12'd770,
      12'd771,
      12'd772,
      12'd773,
      12'd774,
      12'd832,
      12'd833,
      12'd834,
      12'd835,
      12'd836,
      12'd1952,
      12'd1953,
      12'd1954,
      12'd1955,
      12'd1968,
      12'd1969,
      12'd1970,
      12'd1971,
      12'd2048,
      12'd2049,
      12'd2816,
      12'd2818,
      12'd3072,
      12'd3073,
      12'd3074,
      12'd3857,
      12'd3858,
      12'd3859,
      12'd3860:
	  CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q279 =
	      commitStage_f_rob_data$D_OUT[180:169];
      default: CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q279 =
		   12'd2303;
    endcase
  end
  always@(mmioToPlatform_pRq_enq_x)
  begin
    case (mmioToPlatform_pRq_enq_x[37:36])
      2'd0, 2'd1, 2'd2:
	  CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q280 =
	      mmioToPlatform_pRq_enq_x[37:32];
      2'd3:
	  CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q280 =
	      { 2'd3, mmioToPlatform_pRq_enq_x[35:32] };
    endcase
  end
  always@(coreFix_aluExe_0_rsAlu$dispatchData)
  begin
    case (coreFix_aluExe_0_rsAlu$dispatchData[139:137])
      3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
	  CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q281 =
	      coreFix_aluExe_0_rsAlu$dispatchData[139:137];
      default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q281 = 3'd7;
    endcase
  end
  always@(coreFix_aluExe_0_rsAlu$dispatchData or
	  CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q281)
  begin
    case (coreFix_aluExe_0_rsAlu$dispatchData[156:154])
      3'd0, 3'd1, 3'd2, 3'd3:
	  CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q282 =
	      coreFix_aluExe_0_rsAlu$dispatchData[156:136];
      3'd4:
	  CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q282 =
	      { coreFix_aluExe_0_rsAlu$dispatchData[156:154],
		9'h0AA,
		coreFix_aluExe_0_rsAlu$dispatchData[144:140],
		CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q281,
		coreFix_aluExe_0_rsAlu$dispatchData[136] };
      default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q282 =
		   21'd1485482;
    endcase
  end
  always@(coreFix_aluExe_0_rsAlu$dispatchData)
  begin
    case (coreFix_aluExe_0_rsAlu$dispatchData[134:123])
      12'd1,
      12'd2,
      12'd3,
      12'd256,
      12'd260,
      12'd261,
      12'd262,
      12'd320,
      12'd321,
      12'd322,
      12'd323,
      12'd324,
      12'd384,
      12'd768,
      12'd769,
      12'd770,
      12'd771,
      12'd772,
      12'd773,
      12'd774,
      12'd832,
      12'd833,
      12'd834,
      12'd835,
      12'd836,
      12'd1952,
      12'd1953,
      12'd1954,
      12'd1955,
      12'd1968,
      12'd1969,
      12'd1970,
      12'd1971,
      12'd2048,
      12'd2049,
      12'd2816,
      12'd2818,
      12'd3072,
      12'd3073,
      12'd3074,
      12'd3857,
      12'd3858,
      12'd3859,
      12'd3860:
	  CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q283 =
	      coreFix_aluExe_0_rsAlu$dispatchData[134:123];
      default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q283 =
		   12'd2303;
    endcase
  end
  always@(coreFix_aluExe_0_dispToRegQ$first)
  begin
    case (coreFix_aluExe_0_dispToRegQ$first[135:133])
      3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
	  CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q284 =
	      coreFix_aluExe_0_dispToRegQ$first[135:133];
      default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q284 = 3'd7;
    endcase
  end
  always@(coreFix_aluExe_0_dispToRegQ$first or
	  CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q284)
  begin
    case (coreFix_aluExe_0_dispToRegQ$first[152:150])
      3'd0, 3'd1, 3'd2, 3'd3:
	  CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q285 =
	      coreFix_aluExe_0_dispToRegQ$first[152:132];
      3'd4:
	  CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q285 =
	      { coreFix_aluExe_0_dispToRegQ$first[152:150],
		9'h0AA,
		coreFix_aluExe_0_dispToRegQ$first[140:136],
		CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q284,
		coreFix_aluExe_0_dispToRegQ$first[132] };
      default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q285 =
		   21'd1485482;
    endcase
  end
  always@(coreFix_aluExe_0_dispToRegQ$first)
  begin
    case (coreFix_aluExe_0_dispToRegQ$first[130:119])
      12'd1,
      12'd2,
      12'd3,
      12'd256,
      12'd260,
      12'd261,
      12'd262,
      12'd320,
      12'd321,
      12'd322,
      12'd323,
      12'd324,
      12'd384,
      12'd768,
      12'd769,
      12'd770,
      12'd771,
      12'd772,
      12'd773,
      12'd774,
      12'd832,
      12'd833,
      12'd834,
      12'd835,
      12'd836,
      12'd1952,
      12'd1953,
      12'd1954,
      12'd1955,
      12'd1968,
      12'd1969,
      12'd1970,
      12'd1971,
      12'd2048,
      12'd2049,
      12'd2816,
      12'd2818,
      12'd3072,
      12'd3073,
      12'd3074,
      12'd3857,
      12'd3858,
      12'd3859,
      12'd3860:
	  CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q286 =
	      coreFix_aluExe_0_dispToRegQ$first[130:119];
      default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q286 =
		   12'd2303;
    endcase
  end
  always@(coreFix_aluExe_1_rsAlu$dispatchData)
  begin
    case (coreFix_aluExe_1_rsAlu$dispatchData[139:137])
      3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
	  CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q287 =
	      coreFix_aluExe_1_rsAlu$dispatchData[139:137];
      default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q287 = 3'd7;
    endcase
  end
  always@(coreFix_aluExe_1_rsAlu$dispatchData or
	  CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q287)
  begin
    case (coreFix_aluExe_1_rsAlu$dispatchData[156:154])
      3'd0, 3'd1, 3'd2, 3'd3:
	  CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q288 =
	      coreFix_aluExe_1_rsAlu$dispatchData[156:136];
      3'd4:
	  CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q288 =
	      { coreFix_aluExe_1_rsAlu$dispatchData[156:154],
		9'h0AA,
		coreFix_aluExe_1_rsAlu$dispatchData[144:140],
		CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q287,
		coreFix_aluExe_1_rsAlu$dispatchData[136] };
      default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q288 =
		   21'd1485482;
    endcase
  end
  always@(coreFix_aluExe_1_rsAlu$dispatchData)
  begin
    case (coreFix_aluExe_1_rsAlu$dispatchData[134:123])
      12'd1,
      12'd2,
      12'd3,
      12'd256,
      12'd260,
      12'd261,
      12'd262,
      12'd320,
      12'd321,
      12'd322,
      12'd323,
      12'd324,
      12'd384,
      12'd768,
      12'd769,
      12'd770,
      12'd771,
      12'd772,
      12'd773,
      12'd774,
      12'd832,
      12'd833,
      12'd834,
      12'd835,
      12'd836,
      12'd1952,
      12'd1953,
      12'd1954,
      12'd1955,
      12'd1968,
      12'd1969,
      12'd1970,
      12'd1971,
      12'd2048,
      12'd2049,
      12'd2816,
      12'd2818,
      12'd3072,
      12'd3073,
      12'd3074,
      12'd3857,
      12'd3858,
      12'd3859,
      12'd3860:
	  CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q289 =
	      coreFix_aluExe_1_rsAlu$dispatchData[134:123];
      default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q289 =
		   12'd2303;
    endcase
  end
  always@(coreFix_aluExe_1_dispToRegQ$first)
  begin
    case (coreFix_aluExe_1_dispToRegQ$first[135:133])
      3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
	  CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q290 =
	      coreFix_aluExe_1_dispToRegQ$first[135:133];
      default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q290 = 3'd7;
    endcase
  end
  always@(coreFix_aluExe_1_dispToRegQ$first or
	  CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q290)
  begin
    case (coreFix_aluExe_1_dispToRegQ$first[152:150])
      3'd0, 3'd1, 3'd2, 3'd3:
	  CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q291 =
	      coreFix_aluExe_1_dispToRegQ$first[152:132];
      3'd4:
	  CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q291 =
	      { coreFix_aluExe_1_dispToRegQ$first[152:150],
		9'h0AA,
		coreFix_aluExe_1_dispToRegQ$first[140:136],
		CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q290,
		coreFix_aluExe_1_dispToRegQ$first[132] };
      default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q291 =
		   21'd1485482;
    endcase
  end
  always@(coreFix_aluExe_1_dispToRegQ$first)
  begin
    case (coreFix_aluExe_1_dispToRegQ$first[130:119])
      12'd1,
      12'd2,
      12'd3,
      12'd256,
      12'd260,
      12'd261,
      12'd262,
      12'd320,
      12'd321,
      12'd322,
      12'd323,
      12'd324,
      12'd384,
      12'd768,
      12'd769,
      12'd770,
      12'd771,
      12'd772,
      12'd773,
      12'd774,
      12'd832,
      12'd833,
      12'd834,
      12'd835,
      12'd836,
      12'd1952,
      12'd1953,
      12'd1954,
      12'd1955,
      12'd1968,
      12'd1969,
      12'd1970,
      12'd1971,
      12'd2048,
      12'd2049,
      12'd2816,
      12'd2818,
      12'd3072,
      12'd3073,
      12'd3074,
      12'd3857,
      12'd3858,
      12'd3859,
      12'd3860:
	  CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q292 =
	      coreFix_aluExe_1_dispToRegQ$first[130:119];
      default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q292 =
		   12'd2303;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData)
  begin
    case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67])
      3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
	  CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q293 =
	      coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67];
      default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q293 = 3'd7;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData or
	  CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q293)
  begin
    case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:84])
      3'd0, 3'd1, 3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q294 =
	      coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:66];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q294 =
	      { coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:84],
		9'h0AA,
		coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[74:70],
		CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q293,
		coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[66] };
      default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q294 =
		   21'd1485482;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9174 or
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10654 or
	  IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10707 or
	  IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10652)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
      5'd0:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q295 =
	      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10654;
      5'd1:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q295 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
		{ !coreFix_fpuMulDivExe_0_regToExeQ$first[139],
		  coreFix_fpuMulDivExe_0_regToExeQ$first[138:76] } :
		{ IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10707,
		  IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10652 };
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q295 =
		   IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9174;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10654)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
      5'd0, 5'd1:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q296 =
	      64'h3FF0000000000000;
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q296 =
		   IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10654;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_dispToRegQ$first)
  begin
    case (coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58])
      3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
	  CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q297 =
	      coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58];
      default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q297 = 3'd7;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_dispToRegQ$first or
	  CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q297)
  begin
    case (coreFix_fpuMulDivExe_0_dispToRegQ$first[77:75])
      3'd0, 3'd1, 3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298 =
	      coreFix_fpuMulDivExe_0_dispToRegQ$first[77:57];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298 =
	      { coreFix_fpuMulDivExe_0_dispToRegQ$first[77:75],
		9'h0AA,
		coreFix_fpuMulDivExe_0_dispToRegQ$first[65:61],
		CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q297,
		coreFix_fpuMulDivExe_0_dispToRegQ$first[57] };
      default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298 =
		   21'd1485482;
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[1:0];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[1:0];
    endcase
  end
  always@(rob$deqPort_1_deq_data)
  begin
    case (rob$deqPort_1_deq_data[180:169])
      12'd1,
      12'd2,
      12'd3,
      12'd256,
      12'd260,
      12'd261,
      12'd262,
      12'd320,
      12'd321,
      12'd322,
      12'd323,
      12'd324,
      12'd384,
      12'd768,
      12'd769,
      12'd770,
      12'd771,
      12'd772,
      12'd773,
      12'd774,
      12'd832,
      12'd833,
      12'd834,
      12'd835,
      12'd836,
      12'd1952,
      12'd1953,
      12'd1954,
      12'd1955,
      12'd1968,
      12'd1969,
      12'd1970,
      12'd1971,
      12'd2048,
      12'd2049,
      12'd2816,
      12'd2818,
      12'd3072,
      12'd3073,
      12'd3074,
      12'd3857,
      12'd3858,
      12'd3859,
      12'd3860:
	  CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q300 =
	      rob$deqPort_1_deq_data[180:169];
      default: CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q300 =
		   12'd2303;
    endcase
  end
  always@(rob$deqPort_1_deq_data)
  begin
    case (rob$deqPort_1_deq_data[97:96])
      2'd0, 2'd1:
	  CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q301 =
	      rob$deqPort_1_deq_data[97:96];
      default: CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q301 = 2'd2;
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        commitStage_commitTrap <= `BSV_ASSIGNMENT_DELAY
	    166'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	commitStage_rg_just_after_reset <= `BSV_ASSIGNMENT_DELAY 1'd1;
	commitStage_rg_old_mip_csr_val <= `BSV_ASSIGNMENT_DELAY 64'd0;
	commitStage_rg_run_state <= `BSV_ASSIGNMENT_DELAY 1'd0;
	commitStage_rg_serial_num <= `BSV_ASSIGNMENT_DELAY 64'd0;
	coreFix_doStatsReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt <= `BSV_ASSIGNMENT_DELAY
	    4'd0;
	coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit <= `BSV_ASSIGNMENT_DELAY
	    2'd3;
	coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 <= `BSV_ASSIGNMENT_DELAY
	    3'd2;
	coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 <= `BSV_ASSIGNMENT_DELAY
	    3'd2;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	    3'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 <= `BSV_ASSIGNMENT_DELAY
	    3'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 <= `BSV_ASSIGNMENT_DELAY
	    3'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 <= `BSV_ASSIGNMENT_DELAY
	    3'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 <= `BSV_ASSIGNMENT_DELAY
	    3'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 <= `BSV_ASSIGNMENT_DELAY
	    3'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 <= `BSV_ASSIGNMENT_DELAY
	    3'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 <= `BSV_ASSIGNMENT_DELAY
	    3'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP <= `BSV_ASSIGNMENT_DELAY
	    3'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty <= `BSV_ASSIGNMENT_DELAY
	    1'd1;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP <= `BSV_ASSIGNMENT_DELAY
	    3'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    4'd2;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	    583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA80000000000000000;
	coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
	    583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA80000000000000000;
	coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty <= `BSV_ASSIGNMENT_DELAY
	    1'd1;
	coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    584'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl <= `BSV_ASSIGNMENT_DELAY
	    59'h2AAAAAAAAAAAAAA;
	coreFix_memExe_dMem_cache_m_banks_0_processAmo <= `BSV_ASSIGNMENT_DELAY
	    161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
	    153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
	    1'd1;
	coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	    72'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
	    72'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY
	    1'd1;
	coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    73'h0AAAAAAAAAAAAAAAAAA;
	coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	    579'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
	    579'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty <= `BSV_ASSIGNMENT_DELAY
	    1'd1;
	coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    580'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 4'd0;
	coreFix_memExe_dMem_perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_dMem_perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	coreFix_memExe_dMem_perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 5'd10;
	coreFix_memExe_dMem_perfReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_forwardQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_forwardQ_data_0 <= `BSV_ASSIGNMENT_DELAY 69'd0;
	coreFix_memExe_forwardQ_data_1 <= `BSV_ASSIGNMENT_DELAY 69'd0;
	coreFix_memExe_forwardQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_forwardQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_forwardQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	coreFix_memExe_forwardQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_forwardQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    70'h0AAAAAAAAAAAAAAAAA;
	coreFix_memExe_forwardQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_memRespLdQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_memRespLdQ_data_0 <= `BSV_ASSIGNMENT_DELAY 69'd0;
	coreFix_memExe_memRespLdQ_data_1 <= `BSV_ASSIGNMENT_DELAY 69'd0;
	coreFix_memExe_memRespLdQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_memRespLdQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_memRespLdQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	coreFix_memExe_memRespLdQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_memRespLdQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    70'h0AAAAAAAAAAAAAAAAA;
	coreFix_memExe_memRespLdQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_reqLdQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
	    69'h0AAAAAAAAAAAAAAAAA;
	coreFix_memExe_reqLdQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
	coreFix_memExe_reqLdQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_reqLrScAmoQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
	    153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	coreFix_memExe_reqLrScAmoQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
	coreFix_memExe_reqLrScAmoQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_reqStQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
	    66'h2AAAAAAAAAAAAAAAA;
	coreFix_memExe_reqStQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
	coreFix_memExe_reqStQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_respLrScAmoQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_respLrScAmoQ_data_0 <= `BSV_ASSIGNMENT_DELAY 64'd0;
	coreFix_memExe_respLrScAmoQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_respLrScAmoQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	coreFix_memExe_respLrScAmoQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    65'h0AAAAAAAAAAAAAAAA;
	coreFix_memExe_respLrScAmoQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_waitLrScAmoMMIOResp <= `BSV_ASSIGNMENT_DELAY 3'd0;
	csrInstOrInterruptInflight_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_external_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_external_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_external_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_external_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_external_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_external_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_fflags_reg <= `BSV_ASSIGNMENT_DELAY 5'd0;
	csrf_frm_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
	csrf_fs_reg <= `BSV_ASSIGNMENT_DELAY 2'b01;
	csrf_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_mcause_code_reg <= `BSV_ASSIGNMENT_DELAY 4'd0;
	csrf_mcause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_mcounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_mcounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_mcounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_mcycle_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY 64'd0;
	csrf_medeleg_13_11_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
	csrf_medeleg_15_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_medeleg_9_0_reg <= `BSV_ASSIGNMENT_DELAY 10'd0;
	csrf_mepc_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
	csrf_mideleg_11_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_mideleg_1_0_reg <= `BSV_ASSIGNMENT_DELAY 2'd0;
	csrf_mideleg_5_3_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
	csrf_mideleg_9_7_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
	csrf_minstret_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY 64'd0;
	csrf_mpp_reg <= `BSV_ASSIGNMENT_DELAY 2'd0;
	csrf_mprv_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_mscratch_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
	csrf_mtval_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
	csrf_mtvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY 62'd0;
	csrf_mtvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_mxr_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_ppn_reg <= `BSV_ASSIGNMENT_DELAY 44'd0;
	csrf_prev_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_prev_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_prev_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_prv_reg <= `BSV_ASSIGNMENT_DELAY 2'd3;
	csrf_rg_dcsr <= `BSV_ASSIGNMENT_DELAY 64'd1073741843;
	csrf_rg_dpc <= `BSV_ASSIGNMENT_DELAY 64'd1879048192;
	csrf_rg_tdata1_data <= `BSV_ASSIGNMENT_DELAY 59'd0;
	csrf_rg_tdata1_dmode <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_rg_tselect <= `BSV_ASSIGNMENT_DELAY 64'd0;
	csrf_scause_code_reg <= `BSV_ASSIGNMENT_DELAY 4'd0;
	csrf_scause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_scounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_scounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_scounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_sepc_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
	csrf_software_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_software_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_software_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_software_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_software_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_software_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_spp_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_sscratch_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
	csrf_stats_module_doStats <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_stval_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
	csrf_stvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY 62'd0;
	csrf_stvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_sum_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_time_reg <= `BSV_ASSIGNMENT_DELAY 64'd0;
	csrf_timer_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_timer_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_timer_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_timer_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_timer_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_timer_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_tsr_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_tvm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_tw_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_vm_mode_sv39_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	flush_brpred <= `BSV_ASSIGNMENT_DELAY 1'd0;
	flush_caches <= `BSV_ASSIGNMENT_DELAY 1'd0;
	flush_reservation <= `BSV_ASSIGNMENT_DELAY 1'd0;
	flush_tlbs <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_cRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_cRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	    142'h000000000000000004000000000000000000;
	mmio_cRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_cRqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	mmio_cRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	mmio_cRqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_cRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_cRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_cRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_cRsQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	mmio_cRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 2'd0;
	mmio_cRsQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_dataPendQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_dataPendQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_dataPendQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	mmio_dataPendQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_dataPendQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_dataReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_dataReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	    142'h000000000000000004000000000000000000;
	mmio_dataReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_dataReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	mmio_dataReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	mmio_dataReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_dataRespQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_dataRespQ_data_0 <= `BSV_ASSIGNMENT_DELAY 65'd0;
	mmio_dataRespQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_dataRespQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	mmio_dataRespQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    66'h0AAAAAAAAAAAAAAAA;
	mmio_dataRespQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_fromHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0;
	mmio_pRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_pRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 39'h0400000000;
	mmio_pRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_pRqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	mmio_pRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 40'h2AAAAAAAAA;
	mmio_pRqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_pRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_pRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY 67'h155555554AAAAAAAA;
	mmio_pRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_pRsQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	mmio_pRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 68'h2AAAAAAAAAAAAAAAA;
	mmio_pRsQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_toHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0;
	outOfReset <= `BSV_ASSIGNMENT_DELAY 1'd0;
	renameStage_rg_m_halt_req <= `BSV_ASSIGNMENT_DELAY 5'd10;
	rg_core_run_state <= `BSV_ASSIGNMENT_DELAY 2'd2;
	started <= `BSV_ASSIGNMENT_DELAY 1'd0;
	update_vm_info <= `BSV_ASSIGNMENT_DELAY 1'd0;
      end
    else
      begin
        if (commitStage_commitTrap$EN)
	  commitStage_commitTrap <= `BSV_ASSIGNMENT_DELAY
	      commitStage_commitTrap$D_IN;
	if (commitStage_rg_just_after_reset$EN)
	  commitStage_rg_just_after_reset <= `BSV_ASSIGNMENT_DELAY
	      commitStage_rg_just_after_reset$D_IN;
	if (commitStage_rg_old_mip_csr_val$EN)
	  commitStage_rg_old_mip_csr_val <= `BSV_ASSIGNMENT_DELAY
	      commitStage_rg_old_mip_csr_val$D_IN;
	if (commitStage_rg_run_state$EN)
	  commitStage_rg_run_state <= `BSV_ASSIGNMENT_DELAY
	      commitStage_rg_run_state$D_IN;
	if (commitStage_rg_serial_num$EN)
	  commitStage_rg_serial_num <= `BSV_ASSIGNMENT_DELAY
	      commitStage_rg_serial_num$D_IN;
	if (coreFix_doStatsReg$EN)
	  coreFix_doStatsReg <= `BSV_ASSIGNMENT_DELAY coreFix_doStatsReg$D_IN;
	if (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$EN)
	  coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt <= `BSV_ASSIGNMENT_DELAY
	      coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$D_IN;
	if (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$EN)
	  coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init <= `BSV_ASSIGNMENT_DELAY
	      coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$D_IN;
	if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN)
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit <= `BSV_ASSIGNMENT_DELAY
	      coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN;
	if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$EN)
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$D_IN;
	if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$EN)
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_processAmo$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_processAmo <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$D_IN;
	if (coreFix_memExe_dMem_perfReqQ_clearReq_rl$EN)
	  coreFix_memExe_dMem_perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_perfReqQ_clearReq_rl$D_IN;
	if (coreFix_memExe_dMem_perfReqQ_data_0$EN)
	  coreFix_memExe_dMem_perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_perfReqQ_data_0$D_IN;
	if (coreFix_memExe_dMem_perfReqQ_deqReq_rl$EN)
	  coreFix_memExe_dMem_perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_perfReqQ_deqReq_rl$D_IN;
	if (coreFix_memExe_dMem_perfReqQ_empty$EN)
	  coreFix_memExe_dMem_perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_perfReqQ_empty$D_IN;
	if (coreFix_memExe_dMem_perfReqQ_enqReq_rl$EN)
	  coreFix_memExe_dMem_perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_perfReqQ_enqReq_rl$D_IN;
	if (coreFix_memExe_dMem_perfReqQ_full$EN)
	  coreFix_memExe_dMem_perfReqQ_full <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_perfReqQ_full$D_IN;
	if (coreFix_memExe_forwardQ_clearReq_rl$EN)
	  coreFix_memExe_forwardQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_forwardQ_clearReq_rl$D_IN;
	if (coreFix_memExe_forwardQ_data_0$EN)
	  coreFix_memExe_forwardQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_forwardQ_data_0$D_IN;
	if (coreFix_memExe_forwardQ_data_1$EN)
	  coreFix_memExe_forwardQ_data_1 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_forwardQ_data_1$D_IN;
	if (coreFix_memExe_forwardQ_deqP$EN)
	  coreFix_memExe_forwardQ_deqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_forwardQ_deqP$D_IN;
	if (coreFix_memExe_forwardQ_deqReq_rl$EN)
	  coreFix_memExe_forwardQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_forwardQ_deqReq_rl$D_IN;
	if (coreFix_memExe_forwardQ_empty$EN)
	  coreFix_memExe_forwardQ_empty <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_forwardQ_empty$D_IN;
	if (coreFix_memExe_forwardQ_enqP$EN)
	  coreFix_memExe_forwardQ_enqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_forwardQ_enqP$D_IN;
	if (coreFix_memExe_forwardQ_enqReq_rl$EN)
	  coreFix_memExe_forwardQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_forwardQ_enqReq_rl$D_IN;
	if (coreFix_memExe_forwardQ_full$EN)
	  coreFix_memExe_forwardQ_full <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_forwardQ_full$D_IN;
	if (coreFix_memExe_memRespLdQ_clearReq_rl$EN)
	  coreFix_memExe_memRespLdQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_memRespLdQ_clearReq_rl$D_IN;
	if (coreFix_memExe_memRespLdQ_data_0$EN)
	  coreFix_memExe_memRespLdQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_memRespLdQ_data_0$D_IN;
	if (coreFix_memExe_memRespLdQ_data_1$EN)
	  coreFix_memExe_memRespLdQ_data_1 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_memRespLdQ_data_1$D_IN;
	if (coreFix_memExe_memRespLdQ_deqP$EN)
	  coreFix_memExe_memRespLdQ_deqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_memRespLdQ_deqP$D_IN;
	if (coreFix_memExe_memRespLdQ_deqReq_rl$EN)
	  coreFix_memExe_memRespLdQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_memRespLdQ_deqReq_rl$D_IN;
	if (coreFix_memExe_memRespLdQ_empty$EN)
	  coreFix_memExe_memRespLdQ_empty <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_memRespLdQ_empty$D_IN;
	if (coreFix_memExe_memRespLdQ_enqP$EN)
	  coreFix_memExe_memRespLdQ_enqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_memRespLdQ_enqP$D_IN;
	if (coreFix_memExe_memRespLdQ_enqReq_rl$EN)
	  coreFix_memExe_memRespLdQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_memRespLdQ_enqReq_rl$D_IN;
	if (coreFix_memExe_memRespLdQ_full$EN)
	  coreFix_memExe_memRespLdQ_full <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_memRespLdQ_full$D_IN;
	if (coreFix_memExe_reqLdQ_data_0_rl$EN)
	  coreFix_memExe_reqLdQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_reqLdQ_data_0_rl$D_IN;
	if (coreFix_memExe_reqLdQ_empty_rl$EN)
	  coreFix_memExe_reqLdQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_reqLdQ_empty_rl$D_IN;
	if (coreFix_memExe_reqLdQ_full_rl$EN)
	  coreFix_memExe_reqLdQ_full_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_reqLdQ_full_rl$D_IN;
	if (coreFix_memExe_reqLrScAmoQ_data_0_rl$EN)
	  coreFix_memExe_reqLrScAmoQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN;
	if (coreFix_memExe_reqLrScAmoQ_empty_rl$EN)
	  coreFix_memExe_reqLrScAmoQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_reqLrScAmoQ_empty_rl$D_IN;
	if (coreFix_memExe_reqLrScAmoQ_full_rl$EN)
	  coreFix_memExe_reqLrScAmoQ_full_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_reqLrScAmoQ_full_rl$D_IN;
	if (coreFix_memExe_reqStQ_data_0_rl$EN)
	  coreFix_memExe_reqStQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_reqStQ_data_0_rl$D_IN;
	if (coreFix_memExe_reqStQ_empty_rl$EN)
	  coreFix_memExe_reqStQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_reqStQ_empty_rl$D_IN;
	if (coreFix_memExe_reqStQ_full_rl$EN)
	  coreFix_memExe_reqStQ_full_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_reqStQ_full_rl$D_IN;
	if (coreFix_memExe_respLrScAmoQ_clearReq_rl$EN)
	  coreFix_memExe_respLrScAmoQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_respLrScAmoQ_clearReq_rl$D_IN;
	if (coreFix_memExe_respLrScAmoQ_data_0$EN)
	  coreFix_memExe_respLrScAmoQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_respLrScAmoQ_data_0$D_IN;
	if (coreFix_memExe_respLrScAmoQ_deqReq_rl$EN)
	  coreFix_memExe_respLrScAmoQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_respLrScAmoQ_deqReq_rl$D_IN;
	if (coreFix_memExe_respLrScAmoQ_empty$EN)
	  coreFix_memExe_respLrScAmoQ_empty <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_respLrScAmoQ_empty$D_IN;
	if (coreFix_memExe_respLrScAmoQ_enqReq_rl$EN)
	  coreFix_memExe_respLrScAmoQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN;
	if (coreFix_memExe_respLrScAmoQ_full$EN)
	  coreFix_memExe_respLrScAmoQ_full <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_respLrScAmoQ_full$D_IN;
	if (coreFix_memExe_waitLrScAmoMMIOResp$EN)
	  coreFix_memExe_waitLrScAmoMMIOResp <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_waitLrScAmoMMIOResp$D_IN;
	if (csrInstOrInterruptInflight_rl$EN)
	  csrInstOrInterruptInflight_rl <= `BSV_ASSIGNMENT_DELAY
	      csrInstOrInterruptInflight_rl$D_IN;
	if (csrf_external_int_en_vec_0$EN)
	  csrf_external_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY
	      csrf_external_int_en_vec_0$D_IN;
	if (csrf_external_int_en_vec_1$EN)
	  csrf_external_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY
	      csrf_external_int_en_vec_1$D_IN;
	if (csrf_external_int_en_vec_3$EN)
	  csrf_external_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY
	      csrf_external_int_en_vec_3$D_IN;
	if (csrf_external_int_pend_vec_0$EN)
	  csrf_external_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY
	      csrf_external_int_pend_vec_0$D_IN;
	if (csrf_external_int_pend_vec_1$EN)
	  csrf_external_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY
	      csrf_external_int_pend_vec_1$D_IN;
	if (csrf_external_int_pend_vec_3$EN)
	  csrf_external_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY
	      csrf_external_int_pend_vec_3$D_IN;
	if (csrf_fflags_reg$EN)
	  csrf_fflags_reg <= `BSV_ASSIGNMENT_DELAY csrf_fflags_reg$D_IN;
	if (csrf_frm_reg$EN)
	  csrf_frm_reg <= `BSV_ASSIGNMENT_DELAY csrf_frm_reg$D_IN;
	if (csrf_fs_reg$EN)
	  csrf_fs_reg <= `BSV_ASSIGNMENT_DELAY csrf_fs_reg$D_IN;
	if (csrf_ie_vec_0$EN)
	  csrf_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY csrf_ie_vec_0$D_IN;
	if (csrf_ie_vec_1$EN)
	  csrf_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY csrf_ie_vec_1$D_IN;
	if (csrf_ie_vec_3$EN)
	  csrf_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY csrf_ie_vec_3$D_IN;
	if (csrf_mcause_code_reg$EN)
	  csrf_mcause_code_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_mcause_code_reg$D_IN;
	if (csrf_mcause_interrupt_reg$EN)
	  csrf_mcause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_mcause_interrupt_reg$D_IN;
	if (csrf_mcounteren_cy_reg$EN)
	  csrf_mcounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_mcounteren_cy_reg$D_IN;
	if (csrf_mcounteren_ir_reg$EN)
	  csrf_mcounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_mcounteren_ir_reg$D_IN;
	if (csrf_mcounteren_tm_reg$EN)
	  csrf_mcounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_mcounteren_tm_reg$D_IN;
	if (csrf_mcycle_ehr_data_rl$EN)
	  csrf_mcycle_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY
	      csrf_mcycle_ehr_data_rl$D_IN;
	if (csrf_medeleg_13_11_reg$EN)
	  csrf_medeleg_13_11_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_medeleg_13_11_reg$D_IN;
	if (csrf_medeleg_15_reg$EN)
	  csrf_medeleg_15_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_medeleg_15_reg$D_IN;
	if (csrf_medeleg_9_0_reg$EN)
	  csrf_medeleg_9_0_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_medeleg_9_0_reg$D_IN;
	if (csrf_mepc_csr$EN)
	  csrf_mepc_csr <= `BSV_ASSIGNMENT_DELAY csrf_mepc_csr$D_IN;
	if (csrf_mideleg_11_reg$EN)
	  csrf_mideleg_11_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_mideleg_11_reg$D_IN;
	if (csrf_mideleg_1_0_reg$EN)
	  csrf_mideleg_1_0_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_mideleg_1_0_reg$D_IN;
	if (csrf_mideleg_5_3_reg$EN)
	  csrf_mideleg_5_3_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_mideleg_5_3_reg$D_IN;
	if (csrf_mideleg_9_7_reg$EN)
	  csrf_mideleg_9_7_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_mideleg_9_7_reg$D_IN;
	if (csrf_minstret_ehr_data_rl$EN)
	  csrf_minstret_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY
	      csrf_minstret_ehr_data_rl$D_IN;
	if (csrf_mpp_reg$EN)
	  csrf_mpp_reg <= `BSV_ASSIGNMENT_DELAY csrf_mpp_reg$D_IN;
	if (csrf_mprv_reg$EN)
	  csrf_mprv_reg <= `BSV_ASSIGNMENT_DELAY csrf_mprv_reg$D_IN;
	if (csrf_mscratch_csr$EN)
	  csrf_mscratch_csr <= `BSV_ASSIGNMENT_DELAY csrf_mscratch_csr$D_IN;
	if (csrf_mtval_csr$EN)
	  csrf_mtval_csr <= `BSV_ASSIGNMENT_DELAY csrf_mtval_csr$D_IN;
	if (csrf_mtvec_base_hi_reg$EN)
	  csrf_mtvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_mtvec_base_hi_reg$D_IN;
	if (csrf_mtvec_mode_low_reg$EN)
	  csrf_mtvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_mtvec_mode_low_reg$D_IN;
	if (csrf_mxr_reg$EN)
	  csrf_mxr_reg <= `BSV_ASSIGNMENT_DELAY csrf_mxr_reg$D_IN;
	if (csrf_ppn_reg$EN)
	  csrf_ppn_reg <= `BSV_ASSIGNMENT_DELAY csrf_ppn_reg$D_IN;
	if (csrf_prev_ie_vec_0$EN)
	  csrf_prev_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY csrf_prev_ie_vec_0$D_IN;
	if (csrf_prev_ie_vec_1$EN)
	  csrf_prev_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY csrf_prev_ie_vec_1$D_IN;
	if (csrf_prev_ie_vec_3$EN)
	  csrf_prev_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY csrf_prev_ie_vec_3$D_IN;
	if (csrf_prv_reg$EN)
	  csrf_prv_reg <= `BSV_ASSIGNMENT_DELAY csrf_prv_reg$D_IN;
	if (csrf_rg_dcsr$EN)
	  csrf_rg_dcsr <= `BSV_ASSIGNMENT_DELAY csrf_rg_dcsr$D_IN;
	if (csrf_rg_dpc$EN)
	  csrf_rg_dpc <= `BSV_ASSIGNMENT_DELAY csrf_rg_dpc$D_IN;
	if (csrf_rg_tdata1_data$EN)
	  csrf_rg_tdata1_data <= `BSV_ASSIGNMENT_DELAY
	      csrf_rg_tdata1_data$D_IN;
	if (csrf_rg_tdata1_dmode$EN)
	  csrf_rg_tdata1_dmode <= `BSV_ASSIGNMENT_DELAY
	      csrf_rg_tdata1_dmode$D_IN;
	if (csrf_rg_tselect$EN)
	  csrf_rg_tselect <= `BSV_ASSIGNMENT_DELAY csrf_rg_tselect$D_IN;
	if (csrf_scause_code_reg$EN)
	  csrf_scause_code_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_scause_code_reg$D_IN;
	if (csrf_scause_interrupt_reg$EN)
	  csrf_scause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_scause_interrupt_reg$D_IN;
	if (csrf_scounteren_cy_reg$EN)
	  csrf_scounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_scounteren_cy_reg$D_IN;
	if (csrf_scounteren_ir_reg$EN)
	  csrf_scounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_scounteren_ir_reg$D_IN;
	if (csrf_scounteren_tm_reg$EN)
	  csrf_scounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_scounteren_tm_reg$D_IN;
	if (csrf_sepc_csr$EN)
	  csrf_sepc_csr <= `BSV_ASSIGNMENT_DELAY csrf_sepc_csr$D_IN;
	if (csrf_software_int_en_vec_0$EN)
	  csrf_software_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY
	      csrf_software_int_en_vec_0$D_IN;
	if (csrf_software_int_en_vec_1$EN)
	  csrf_software_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY
	      csrf_software_int_en_vec_1$D_IN;
	if (csrf_software_int_en_vec_3$EN)
	  csrf_software_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY
	      csrf_software_int_en_vec_3$D_IN;
	if (csrf_software_int_pend_vec_0$EN)
	  csrf_software_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY
	      csrf_software_int_pend_vec_0$D_IN;
	if (csrf_software_int_pend_vec_1$EN)
	  csrf_software_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY
	      csrf_software_int_pend_vec_1$D_IN;
	if (csrf_software_int_pend_vec_3$EN)
	  csrf_software_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY
	      csrf_software_int_pend_vec_3$D_IN;
	if (csrf_spp_reg$EN)
	  csrf_spp_reg <= `BSV_ASSIGNMENT_DELAY csrf_spp_reg$D_IN;
	if (csrf_sscratch_csr$EN)
	  csrf_sscratch_csr <= `BSV_ASSIGNMENT_DELAY csrf_sscratch_csr$D_IN;
	if (csrf_stats_module_doStats$EN)
	  csrf_stats_module_doStats <= `BSV_ASSIGNMENT_DELAY
	      csrf_stats_module_doStats$D_IN;
	if (csrf_stval_csr$EN)
	  csrf_stval_csr <= `BSV_ASSIGNMENT_DELAY csrf_stval_csr$D_IN;
	if (csrf_stvec_base_hi_reg$EN)
	  csrf_stvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_stvec_base_hi_reg$D_IN;
	if (csrf_stvec_mode_low_reg$EN)
	  csrf_stvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_stvec_mode_low_reg$D_IN;
	if (csrf_sum_reg$EN)
	  csrf_sum_reg <= `BSV_ASSIGNMENT_DELAY csrf_sum_reg$D_IN;
	if (csrf_time_reg$EN)
	  csrf_time_reg <= `BSV_ASSIGNMENT_DELAY csrf_time_reg$D_IN;
	if (csrf_timer_int_en_vec_0$EN)
	  csrf_timer_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY
	      csrf_timer_int_en_vec_0$D_IN;
	if (csrf_timer_int_en_vec_1$EN)
	  csrf_timer_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY
	      csrf_timer_int_en_vec_1$D_IN;
	if (csrf_timer_int_en_vec_3$EN)
	  csrf_timer_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY
	      csrf_timer_int_en_vec_3$D_IN;
	if (csrf_timer_int_pend_vec_0$EN)
	  csrf_timer_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY
	      csrf_timer_int_pend_vec_0$D_IN;
	if (csrf_timer_int_pend_vec_1$EN)
	  csrf_timer_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY
	      csrf_timer_int_pend_vec_1$D_IN;
	if (csrf_timer_int_pend_vec_3$EN)
	  csrf_timer_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY
	      csrf_timer_int_pend_vec_3$D_IN;
	if (csrf_tsr_reg$EN)
	  csrf_tsr_reg <= `BSV_ASSIGNMENT_DELAY csrf_tsr_reg$D_IN;
	if (csrf_tvm_reg$EN)
	  csrf_tvm_reg <= `BSV_ASSIGNMENT_DELAY csrf_tvm_reg$D_IN;
	if (csrf_tw_reg$EN)
	  csrf_tw_reg <= `BSV_ASSIGNMENT_DELAY csrf_tw_reg$D_IN;
	if (csrf_vm_mode_sv39_reg$EN)
	  csrf_vm_mode_sv39_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_vm_mode_sv39_reg$D_IN;
	if (flush_brpred$EN)
	  flush_brpred <= `BSV_ASSIGNMENT_DELAY flush_brpred$D_IN;
	if (flush_caches$EN)
	  flush_caches <= `BSV_ASSIGNMENT_DELAY flush_caches$D_IN;
	if (flush_reservation$EN)
	  flush_reservation <= `BSV_ASSIGNMENT_DELAY flush_reservation$D_IN;
	if (flush_tlbs$EN)
	  flush_tlbs <= `BSV_ASSIGNMENT_DELAY flush_tlbs$D_IN;
	if (mmio_cRqQ_clearReq_rl$EN)
	  mmio_cRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_cRqQ_clearReq_rl$D_IN;
	if (mmio_cRqQ_data_0$EN)
	  mmio_cRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_cRqQ_data_0$D_IN;
	if (mmio_cRqQ_deqReq_rl$EN)
	  mmio_cRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_cRqQ_deqReq_rl$D_IN;
	if (mmio_cRqQ_empty$EN)
	  mmio_cRqQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_cRqQ_empty$D_IN;
	if (mmio_cRqQ_enqReq_rl$EN)
	  mmio_cRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_cRqQ_enqReq_rl$D_IN;
	if (mmio_cRqQ_full$EN)
	  mmio_cRqQ_full <= `BSV_ASSIGNMENT_DELAY mmio_cRqQ_full$D_IN;
	if (mmio_cRsQ_clearReq_rl$EN)
	  mmio_cRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_cRsQ_clearReq_rl$D_IN;
	if (mmio_cRsQ_data_0$EN)
	  mmio_cRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_cRsQ_data_0$D_IN;
	if (mmio_cRsQ_deqReq_rl$EN)
	  mmio_cRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_cRsQ_deqReq_rl$D_IN;
	if (mmio_cRsQ_empty$EN)
	  mmio_cRsQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_cRsQ_empty$D_IN;
	if (mmio_cRsQ_enqReq_rl$EN)
	  mmio_cRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_cRsQ_enqReq_rl$D_IN;
	if (mmio_cRsQ_full$EN)
	  mmio_cRsQ_full <= `BSV_ASSIGNMENT_DELAY mmio_cRsQ_full$D_IN;
	if (mmio_dataPendQ_clearReq_rl$EN)
	  mmio_dataPendQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataPendQ_clearReq_rl$D_IN;
	if (mmio_dataPendQ_deqReq_rl$EN)
	  mmio_dataPendQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataPendQ_deqReq_rl$D_IN;
	if (mmio_dataPendQ_empty$EN)
	  mmio_dataPendQ_empty <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataPendQ_empty$D_IN;
	if (mmio_dataPendQ_enqReq_rl$EN)
	  mmio_dataPendQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataPendQ_enqReq_rl$D_IN;
	if (mmio_dataPendQ_full$EN)
	  mmio_dataPendQ_full <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataPendQ_full$D_IN;
	if (mmio_dataReqQ_clearReq_rl$EN)
	  mmio_dataReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataReqQ_clearReq_rl$D_IN;
	if (mmio_dataReqQ_data_0$EN)
	  mmio_dataReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataReqQ_data_0$D_IN;
	if (mmio_dataReqQ_deqReq_rl$EN)
	  mmio_dataReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataReqQ_deqReq_rl$D_IN;
	if (mmio_dataReqQ_empty$EN)
	  mmio_dataReqQ_empty <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataReqQ_empty$D_IN;
	if (mmio_dataReqQ_enqReq_rl$EN)
	  mmio_dataReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataReqQ_enqReq_rl$D_IN;
	if (mmio_dataReqQ_full$EN)
	  mmio_dataReqQ_full <= `BSV_ASSIGNMENT_DELAY mmio_dataReqQ_full$D_IN;
	if (mmio_dataRespQ_clearReq_rl$EN)
	  mmio_dataRespQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataRespQ_clearReq_rl$D_IN;
	if (mmio_dataRespQ_data_0$EN)
	  mmio_dataRespQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataRespQ_data_0$D_IN;
	if (mmio_dataRespQ_deqReq_rl$EN)
	  mmio_dataRespQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataRespQ_deqReq_rl$D_IN;
	if (mmio_dataRespQ_empty$EN)
	  mmio_dataRespQ_empty <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataRespQ_empty$D_IN;
	if (mmio_dataRespQ_enqReq_rl$EN)
	  mmio_dataRespQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataRespQ_enqReq_rl$D_IN;
	if (mmio_dataRespQ_full$EN)
	  mmio_dataRespQ_full <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataRespQ_full$D_IN;
	if (mmio_fromHostAddr$EN)
	  mmio_fromHostAddr <= `BSV_ASSIGNMENT_DELAY mmio_fromHostAddr$D_IN;
	if (mmio_pRqQ_clearReq_rl$EN)
	  mmio_pRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_pRqQ_clearReq_rl$D_IN;
	if (mmio_pRqQ_data_0$EN)
	  mmio_pRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_pRqQ_data_0$D_IN;
	if (mmio_pRqQ_deqReq_rl$EN)
	  mmio_pRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_pRqQ_deqReq_rl$D_IN;
	if (mmio_pRqQ_empty$EN)
	  mmio_pRqQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_pRqQ_empty$D_IN;
	if (mmio_pRqQ_enqReq_rl$EN)
	  mmio_pRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_pRqQ_enqReq_rl$D_IN;
	if (mmio_pRqQ_full$EN)
	  mmio_pRqQ_full <= `BSV_ASSIGNMENT_DELAY mmio_pRqQ_full$D_IN;
	if (mmio_pRsQ_clearReq_rl$EN)
	  mmio_pRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_pRsQ_clearReq_rl$D_IN;
	if (mmio_pRsQ_data_0$EN)
	  mmio_pRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_pRsQ_data_0$D_IN;
	if (mmio_pRsQ_deqReq_rl$EN)
	  mmio_pRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_pRsQ_deqReq_rl$D_IN;
	if (mmio_pRsQ_empty$EN)
	  mmio_pRsQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_pRsQ_empty$D_IN;
	if (mmio_pRsQ_enqReq_rl$EN)
	  mmio_pRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_pRsQ_enqReq_rl$D_IN;
	if (mmio_pRsQ_full$EN)
	  mmio_pRsQ_full <= `BSV_ASSIGNMENT_DELAY mmio_pRsQ_full$D_IN;
	if (mmio_toHostAddr$EN)
	  mmio_toHostAddr <= `BSV_ASSIGNMENT_DELAY mmio_toHostAddr$D_IN;
	if (outOfReset$EN)
	  outOfReset <= `BSV_ASSIGNMENT_DELAY outOfReset$D_IN;
	if (renameStage_rg_m_halt_req$EN)
	  renameStage_rg_m_halt_req <= `BSV_ASSIGNMENT_DELAY
	      renameStage_rg_m_halt_req$D_IN;
	if (rg_core_run_state$EN)
	  rg_core_run_state <= `BSV_ASSIGNMENT_DELAY rg_core_run_state$D_IN;
	if (started$EN) started <= `BSV_ASSIGNMENT_DELAY started$D_IN;
	if (update_vm_info$EN)
	  update_vm_info <= `BSV_ASSIGNMENT_DELAY update_vm_info$D_IN;
      end
    if (csrf_rg_dscratch0$EN)
      csrf_rg_dscratch0 <= `BSV_ASSIGNMENT_DELAY csrf_rg_dscratch0$D_IN;
    if (csrf_rg_dscratch1$EN)
      csrf_rg_dscratch1 <= `BSV_ASSIGNMENT_DELAY csrf_rg_dscratch1$D_IN;
    if (csrf_rg_tdata2$EN)
      csrf_rg_tdata2 <= `BSV_ASSIGNMENT_DELAY csrf_rg_tdata2$D_IN;
    if (csrf_rg_tdata3$EN)
      csrf_rg_tdata3 <= `BSV_ASSIGNMENT_DELAY csrf_rg_tdata3$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    commitStage_commitTrap = 166'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    commitStage_rg_just_after_reset = 1'h0;
    commitStage_rg_old_mip_csr_val = 64'hAAAAAAAAAAAAAAAA;
    commitStage_rg_run_state = 1'h0;
    commitStage_rg_serial_num = 64'hAAAAAAAAAAAAAAAA;
    coreFix_doStatsReg = 1'h0;
    coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt = 4'hA;
    coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init = 1'h0;
    coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit = 2'h2;
    coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 = 3'h2;
    coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 = 3'h2;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 = 3'h2;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 = 3'h2;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 = 3'h2;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 = 3'h2;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 = 3'h2;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 = 3'h2;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 = 3'h2;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 = 3'h2;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP = 3'h2;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP = 3'h2;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl = 4'hA;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 =
	583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 =
	583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl =
	584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl = 59'h2AAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_processAmo =
	161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl =
	153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 =
	72'hAAAAAAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1 =
	72'hAAAAAAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl =
	73'h0AAAAAAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 =
	579'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 =
	579'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl =
	580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full = 1'h0;
    coreFix_memExe_dMem_perfReqQ_clearReq_rl = 1'h0;
    coreFix_memExe_dMem_perfReqQ_data_0 = 4'hA;
    coreFix_memExe_dMem_perfReqQ_deqReq_rl = 1'h0;
    coreFix_memExe_dMem_perfReqQ_empty = 1'h0;
    coreFix_memExe_dMem_perfReqQ_enqReq_rl = 5'h0A;
    coreFix_memExe_dMem_perfReqQ_full = 1'h0;
    coreFix_memExe_forwardQ_clearReq_rl = 1'h0;
    coreFix_memExe_forwardQ_data_0 = 69'h0AAAAAAAAAAAAAAAAA;
    coreFix_memExe_forwardQ_data_1 = 69'h0AAAAAAAAAAAAAAAAA;
    coreFix_memExe_forwardQ_deqP = 1'h0;
    coreFix_memExe_forwardQ_deqReq_rl = 1'h0;
    coreFix_memExe_forwardQ_empty = 1'h0;
    coreFix_memExe_forwardQ_enqP = 1'h0;
    coreFix_memExe_forwardQ_enqReq_rl = 70'h2AAAAAAAAAAAAAAAAA;
    coreFix_memExe_forwardQ_full = 1'h0;
    coreFix_memExe_memRespLdQ_clearReq_rl = 1'h0;
    coreFix_memExe_memRespLdQ_data_0 = 69'h0AAAAAAAAAAAAAAAAA;
    coreFix_memExe_memRespLdQ_data_1 = 69'h0AAAAAAAAAAAAAAAAA;
    coreFix_memExe_memRespLdQ_deqP = 1'h0;
    coreFix_memExe_memRespLdQ_deqReq_rl = 1'h0;
    coreFix_memExe_memRespLdQ_empty = 1'h0;
    coreFix_memExe_memRespLdQ_enqP = 1'h0;
    coreFix_memExe_memRespLdQ_enqReq_rl = 70'h2AAAAAAAAAAAAAAAAA;
    coreFix_memExe_memRespLdQ_full = 1'h0;
    coreFix_memExe_reqLdQ_data_0_rl = 69'h0AAAAAAAAAAAAAAAAA;
    coreFix_memExe_reqLdQ_empty_rl = 1'h0;
    coreFix_memExe_reqLdQ_full_rl = 1'h0;
    coreFix_memExe_reqLrScAmoQ_data_0_rl =
	153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_memExe_reqLrScAmoQ_empty_rl = 1'h0;
    coreFix_memExe_reqLrScAmoQ_full_rl = 1'h0;
    coreFix_memExe_reqStQ_data_0_rl = 66'h2AAAAAAAAAAAAAAAA;
    coreFix_memExe_reqStQ_empty_rl = 1'h0;
    coreFix_memExe_reqStQ_full_rl = 1'h0;
    coreFix_memExe_respLrScAmoQ_clearReq_rl = 1'h0;
    coreFix_memExe_respLrScAmoQ_data_0 = 64'hAAAAAAAAAAAAAAAA;
    coreFix_memExe_respLrScAmoQ_deqReq_rl = 1'h0;
    coreFix_memExe_respLrScAmoQ_empty = 1'h0;
    coreFix_memExe_respLrScAmoQ_enqReq_rl = 65'h0AAAAAAAAAAAAAAAA;
    coreFix_memExe_respLrScAmoQ_full = 1'h0;
    coreFix_memExe_waitLrScAmoMMIOResp = 3'h2;
    csrInstOrInterruptInflight_rl = 1'h0;
    csrf_external_int_en_vec_0 = 1'h0;
    csrf_external_int_en_vec_1 = 1'h0;
    csrf_external_int_en_vec_3 = 1'h0;
    csrf_external_int_pend_vec_0 = 1'h0;
    csrf_external_int_pend_vec_1 = 1'h0;
    csrf_external_int_pend_vec_3 = 1'h0;
    csrf_fflags_reg = 5'h0A;
    csrf_frm_reg = 3'h2;
    csrf_fs_reg = 2'h2;
    csrf_ie_vec_0 = 1'h0;
    csrf_ie_vec_1 = 1'h0;
    csrf_ie_vec_3 = 1'h0;
    csrf_mcause_code_reg = 4'hA;
    csrf_mcause_interrupt_reg = 1'h0;
    csrf_mcounteren_cy_reg = 1'h0;
    csrf_mcounteren_ir_reg = 1'h0;
    csrf_mcounteren_tm_reg = 1'h0;
    csrf_mcycle_ehr_data_rl = 64'hAAAAAAAAAAAAAAAA;
    csrf_medeleg_13_11_reg = 3'h2;
    csrf_medeleg_15_reg = 1'h0;
    csrf_medeleg_9_0_reg = 10'h2AA;
    csrf_mepc_csr = 64'hAAAAAAAAAAAAAAAA;
    csrf_mideleg_11_reg = 1'h0;
    csrf_mideleg_1_0_reg = 2'h2;
    csrf_mideleg_5_3_reg = 3'h2;
    csrf_mideleg_9_7_reg = 3'h2;
    csrf_minstret_ehr_data_rl = 64'hAAAAAAAAAAAAAAAA;
    csrf_mpp_reg = 2'h2;
    csrf_mprv_reg = 1'h0;
    csrf_mscratch_csr = 64'hAAAAAAAAAAAAAAAA;
    csrf_mtval_csr = 64'hAAAAAAAAAAAAAAAA;
    csrf_mtvec_base_hi_reg = 62'h2AAAAAAAAAAAAAAA;
    csrf_mtvec_mode_low_reg = 1'h0;
    csrf_mxr_reg = 1'h0;
    csrf_ppn_reg = 44'hAAAAAAAAAAA;
    csrf_prev_ie_vec_0 = 1'h0;
    csrf_prev_ie_vec_1 = 1'h0;
    csrf_prev_ie_vec_3 = 1'h0;
    csrf_prv_reg = 2'h2;
    csrf_rg_dcsr = 64'hAAAAAAAAAAAAAAAA;
    csrf_rg_dpc = 64'hAAAAAAAAAAAAAAAA;
    csrf_rg_dscratch0 = 64'hAAAAAAAAAAAAAAAA;
    csrf_rg_dscratch1 = 64'hAAAAAAAAAAAAAAAA;
    csrf_rg_tdata1_data = 59'h2AAAAAAAAAAAAAA;
    csrf_rg_tdata1_dmode = 1'h0;
    csrf_rg_tdata2 = 64'hAAAAAAAAAAAAAAAA;
    csrf_rg_tdata3 = 64'hAAAAAAAAAAAAAAAA;
    csrf_rg_tselect = 64'hAAAAAAAAAAAAAAAA;
    csrf_scause_code_reg = 4'hA;
    csrf_scause_interrupt_reg = 1'h0;
    csrf_scounteren_cy_reg = 1'h0;
    csrf_scounteren_ir_reg = 1'h0;
    csrf_scounteren_tm_reg = 1'h0;
    csrf_sepc_csr = 64'hAAAAAAAAAAAAAAAA;
    csrf_software_int_en_vec_0 = 1'h0;
    csrf_software_int_en_vec_1 = 1'h0;
    csrf_software_int_en_vec_3 = 1'h0;
    csrf_software_int_pend_vec_0 = 1'h0;
    csrf_software_int_pend_vec_1 = 1'h0;
    csrf_software_int_pend_vec_3 = 1'h0;
    csrf_spp_reg = 1'h0;
    csrf_sscratch_csr = 64'hAAAAAAAAAAAAAAAA;
    csrf_stats_module_doStats = 1'h0;
    csrf_stval_csr = 64'hAAAAAAAAAAAAAAAA;
    csrf_stvec_base_hi_reg = 62'h2AAAAAAAAAAAAAAA;
    csrf_stvec_mode_low_reg = 1'h0;
    csrf_sum_reg = 1'h0;
    csrf_time_reg = 64'hAAAAAAAAAAAAAAAA;
    csrf_timer_int_en_vec_0 = 1'h0;
    csrf_timer_int_en_vec_1 = 1'h0;
    csrf_timer_int_en_vec_3 = 1'h0;
    csrf_timer_int_pend_vec_0 = 1'h0;
    csrf_timer_int_pend_vec_1 = 1'h0;
    csrf_timer_int_pend_vec_3 = 1'h0;
    csrf_tsr_reg = 1'h0;
    csrf_tvm_reg = 1'h0;
    csrf_tw_reg = 1'h0;
    csrf_vm_mode_sv39_reg = 1'h0;
    flush_brpred = 1'h0;
    flush_caches = 1'h0;
    flush_reservation = 1'h0;
    flush_tlbs = 1'h0;
    mmio_cRqQ_clearReq_rl = 1'h0;
    mmio_cRqQ_data_0 = 142'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    mmio_cRqQ_deqReq_rl = 1'h0;
    mmio_cRqQ_empty = 1'h0;
    mmio_cRqQ_enqReq_rl = 143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    mmio_cRqQ_full = 1'h0;
    mmio_cRsQ_clearReq_rl = 1'h0;
    mmio_cRsQ_data_0 = 1'h0;
    mmio_cRsQ_deqReq_rl = 1'h0;
    mmio_cRsQ_empty = 1'h0;
    mmio_cRsQ_enqReq_rl = 2'h2;
    mmio_cRsQ_full = 1'h0;
    mmio_dataPendQ_clearReq_rl = 1'h0;
    mmio_dataPendQ_deqReq_rl = 1'h0;
    mmio_dataPendQ_empty = 1'h0;
    mmio_dataPendQ_enqReq_rl = 1'h0;
    mmio_dataPendQ_full = 1'h0;
    mmio_dataReqQ_clearReq_rl = 1'h0;
    mmio_dataReqQ_data_0 = 142'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    mmio_dataReqQ_deqReq_rl = 1'h0;
    mmio_dataReqQ_empty = 1'h0;
    mmio_dataReqQ_enqReq_rl = 143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    mmio_dataReqQ_full = 1'h0;
    mmio_dataRespQ_clearReq_rl = 1'h0;
    mmio_dataRespQ_data_0 = 65'h0AAAAAAAAAAAAAAAA;
    mmio_dataRespQ_deqReq_rl = 1'h0;
    mmio_dataRespQ_empty = 1'h0;
    mmio_dataRespQ_enqReq_rl = 66'h2AAAAAAAAAAAAAAAA;
    mmio_dataRespQ_full = 1'h0;
    mmio_fromHostAddr = 61'h0AAAAAAAAAAAAAAA;
    mmio_pRqQ_clearReq_rl = 1'h0;
    mmio_pRqQ_data_0 = 39'h2AAAAAAAAA;
    mmio_pRqQ_deqReq_rl = 1'h0;
    mmio_pRqQ_empty = 1'h0;
    mmio_pRqQ_enqReq_rl = 40'hAAAAAAAAAA;
    mmio_pRqQ_full = 1'h0;
    mmio_pRsQ_clearReq_rl = 1'h0;
    mmio_pRsQ_data_0 = 67'h2AAAAAAAAAAAAAAAA;
    mmio_pRsQ_deqReq_rl = 1'h0;
    mmio_pRsQ_empty = 1'h0;
    mmio_pRsQ_enqReq_rl = 68'hAAAAAAAAAAAAAAAAA;
    mmio_pRsQ_full = 1'h0;
    mmio_toHostAddr = 61'h0AAAAAAAAAAAAAAA;
    outOfReset = 1'h0;
    renameStage_rg_m_halt_req = 5'h0A;
    rg_core_run_state = 2'h2;
    started = 1'h0;
    update_vm_info = 1'h0;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_outOfReset)
	$fwrite(32'h80000002, "mkProc came out of reset\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_csr_write &&
	  f_csr_reqs$D_OUT[75:64] == 12'd2048)
	$display("[Terminate CSR] being written (val = %x), ",
		 "send terminate signal to host",
		 f_csr_reqs$D_OUT[63:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush)
	$write("instret:%0d  PC:0x%0h  instr:0x%08h",
	       commitStage_rg_serial_num,
	       rob$deqPort_0_deq_data[425:362],
	       rob$deqPort_0_deq_data[361:330],
	       "  iType:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[329:325] == 5'd0)
	$write("Unsupported");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[329:325] == 5'd1)
	$write("Nop");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[329:325] == 5'd2)
	$write("Amo");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[329:325] == 5'd3)
	$write("Alu");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[329:325] == 5'd4)
	$write("Ld");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[329:325] == 5'd5)
	$write("St");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[329:325] == 5'd6)
	$write("Lr");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[329:325] == 5'd7)
	$write("Sc");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[329:325] == 5'd8)
	$write("J");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[329:325] == 5'd9)
	$write("Jr");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[329:325] == 5'd10)
	$write("Br");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[329:325] == 5'd11)
	$write("Auipc");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[329:325] == 5'd12)
	$write("Fpu");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[329:325] == 5'd13)
	$write("Csr");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[329:325] == 5'd14)
	$write("Fence");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[329:325] == 5'd15)
	$write("FenceI");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[329:325] == 5'd16)
	$write("SFence");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[329:325] == 5'd17)
	$write("Ecall");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[329:325] == 5'd18)
	$write("Ebreak");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[329:325] == 5'd19)
	$write("Sret");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[329:325] == 5'd20)
	$write("Mret");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[329:325] != 5'd0 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd1 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd2 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd3 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd4 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd5 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd6 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd7 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd8 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd9 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd10 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd11 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd12 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd13 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd14 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd15 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd16 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd17 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd18 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd19 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd20)
	$write("Interrupt");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush)
	$write("    [doCommitTrap]", "\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst)
	$write("instret:%0d  PC:0x%0h  instr:0x%08h",
	       commitStage_rg_serial_num,
	       rob$deqPort_0_deq_data[425:362],
	       rob$deqPort_0_deq_data[361:330],
	       "   iType:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[329:325] == 5'd0)
	$write("Unsupported");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[329:325] == 5'd1)
	$write("Nop");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[329:325] == 5'd2)
	$write("Amo");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[329:325] == 5'd3)
	$write("Alu");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[329:325] == 5'd4)
	$write("Ld");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[329:325] == 5'd5)
	$write("St");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[329:325] == 5'd6)
	$write("Lr");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[329:325] == 5'd7)
	$write("Sc");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[329:325] == 5'd8)
	$write("J");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[329:325] == 5'd9)
	$write("Jr");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[329:325] == 5'd10)
	$write("Br");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[329:325] == 5'd11)
	$write("Auipc");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[329:325] == 5'd12)
	$write("Fpu");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[329:325] == 5'd13)
	$write("Csr");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[329:325] == 5'd14)
	$write("Fence");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[329:325] == 5'd15)
	$write("FenceI");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[329:325] == 5'd16)
	$write("SFence");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[329:325] == 5'd17)
	$write("Ecall");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[329:325] == 5'd18)
	$write("Ebreak");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[329:325] == 5'd19)
	$write("Sret");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[329:325] == 5'd20)
	$write("Mret");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[329:325] != 5'd0 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd1 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd2 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd3 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd4 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd5 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd6 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd7 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd8 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd9 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd10 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd11 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd12 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd13 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd14 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd15 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd16 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd17 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd18 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd19 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd20)
	$write("Interrupt");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst)
	$write("    [doCommitSystemInst]", "\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[329:325] == 5'd13 &&
	  IF_rob_deqPort_0_deq_data__4354_BIT_181_4429_T_ETC___d14998 == 6'd6)
	$display("[Terminate CSR] being written (val = %x), ",
		 "send terminate signal to host",
		 rob$deqPort_0_deq_data[95:32]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq)
	$write("instret:%0d  PC:0x%0h  instr:0x%08h",
	       commitStage_rg_serial_num,
	       rob$deqPort_0_deq_data[425:362],
	       rob$deqPort_0_deq_data[361:330],
	       "   iType:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[329:325] == 5'd1)
	$write("Nop");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[329:325] == 5'd2)
	$write("Amo");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[329:325] == 5'd3)
	$write("Alu");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[329:325] == 5'd4)
	$write("Ld");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[329:325] == 5'd5)
	$write("St");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[329:325] == 5'd6)
	$write("Lr");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[329:325] == 5'd7)
	$write("Sc");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[329:325] == 5'd8)
	$write("J");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[329:325] == 5'd9)
	$write("Jr");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[329:325] == 5'd10)
	$write("Br");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[329:325] == 5'd11)
	$write("Auipc");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[329:325] == 5'd12)
	$write("Fpu");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[329:325] == 5'd14)
	$write("Fence");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[329:325] != 5'd1 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd2 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd3 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd4 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd5 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd6 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd7 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd8 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd9 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd10 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd11 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd12 &&
	  rob$deqPort_0_deq_data[329:325] != 5'd14)
	$write("Interrupt");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq)
	$write("    [doCommitNormalInst [%0d]]", $signed(32'd0), "\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[329:325] != 5'd0 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd21 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd17 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd18 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd13 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd16 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd15 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd19 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd20)
	$write("instret:%0d  PC:0x%0h  instr:0x%08h",
	       commitStage_rg_serial_num_4343_PLUS_IF_rob_deq_ETC___d15467,
	       rob$deqPort_1_deq_data[425:362],
	       rob$deqPort_1_deq_data[361:330],
	       "   iType:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[329:325] == 5'd1)
	$write("Nop");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[329:325] == 5'd2)
	$write("Amo");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[329:325] == 5'd3)
	$write("Alu");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[329:325] == 5'd4)
	$write("Ld");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[329:325] == 5'd5)
	$write("St");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[329:325] == 5'd6)
	$write("Lr");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[329:325] == 5'd7)
	$write("Sc");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[329:325] == 5'd8)
	$write("J");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[329:325] == 5'd9)
	$write("Jr");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[329:325] == 5'd10)
	$write("Br");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[329:325] == 5'd11)
	$write("Auipc");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[329:325] == 5'd12)
	$write("Fpu");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[329:325] == 5'd14)
	$write("Fence");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[329:325] != 5'd0 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd21 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd17 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd18 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd13 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd16 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd15 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd19 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd20 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd1 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd2 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd3 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd4 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd5 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd6 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd7 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd8 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd9 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd10 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd11 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd12 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd14)
	$write("Interrupt");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[329:325] != 5'd0 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd21 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd17 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd18 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd13 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd16 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd15 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd19 &&
	  rob$deqPort_1_deq_data[329:325] != 5'd20)
	$write("    [doCommitNormalInst [%0d]]", $signed(32'd1), "\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas &&
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit == 2'd3)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas &&
	  v__h603885 == 2'd0)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
  end
  // synopsys translate_on
endmodule  // mkCore

