//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name                         I/O  size props
// RDY_request_put                O     1
// response_get                   O    69 reg
// RDY_response_get               O     1 reg
// CLK                            I     1 clock
// RST_N                          I     1 reset
// request_put                    I   196 reg
// EN_request_put                 I     1
// EN_response_get                I     1
//
// Combinational paths from inputs to outputs:
//   EN_response_get -> RDY_request_put
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkDoubleFMA(CLK,
		   RST_N,

		   request_put,
		   EN_request_put,
		   RDY_request_put,

		   EN_response_get,
		   response_get,
		   RDY_response_get);
  input  CLK;
  input  RST_N;

  // action method request_put
  input  [195 : 0] request_put;
  input  EN_request_put;
  output RDY_request_put;

  // actionvalue method response_get
  input  EN_response_get;
  output [68 : 0] response_get;
  output RDY_response_get;

  // signals for module outputs
  wire [68 : 0] response_get;
  wire RDY_request_put, RDY_response_get;

  // ports of submodule fpu_fOperand_S0
  wire [195 : 0] fpu_fOperand_S0$D_IN, fpu_fOperand_S0$D_OUT;
  wire fpu_fOperand_S0$CLR,
       fpu_fOperand_S0$DEQ,
       fpu_fOperand_S0$EMPTY_N,
       fpu_fOperand_S0$ENQ,
       fpu_fOperand_S0$FULL_N;

  // ports of submodule fpu_fProd_S2
  wire [105 : 0] fpu_fProd_S2$D_IN, fpu_fProd_S2$D_OUT;
  wire fpu_fProd_S2$CLR,
       fpu_fProd_S2$DEQ,
       fpu_fProd_S2$EMPTY_N,
       fpu_fProd_S2$ENQ,
       fpu_fProd_S2$FULL_N;

  // ports of submodule fpu_fProd_S3
  wire [105 : 0] fpu_fProd_S3$D_IN, fpu_fProd_S3$D_OUT;
  wire fpu_fProd_S3$CLR,
       fpu_fProd_S3$DEQ,
       fpu_fProd_S3$EMPTY_N,
       fpu_fProd_S3$ENQ,
       fpu_fProd_S3$FULL_N;

  // ports of submodule fpu_fResult_S9
  wire [68 : 0] fpu_fResult_S9$D_IN, fpu_fResult_S9$D_OUT;
  wire fpu_fResult_S9$CLR,
       fpu_fResult_S9$DEQ,
       fpu_fResult_S9$EMPTY_N,
       fpu_fResult_S9$ENQ,
       fpu_fResult_S9$FULL_N;

  // ports of submodule fpu_fState_S1
  wire [257 : 0] fpu_fState_S1$D_IN, fpu_fState_S1$D_OUT;
  wire fpu_fState_S1$CLR,
       fpu_fState_S1$DEQ,
       fpu_fState_S1$EMPTY_N,
       fpu_fState_S1$ENQ,
       fpu_fState_S1$FULL_N;

  // ports of submodule fpu_fState_S2
  wire [151 : 0] fpu_fState_S2$D_IN, fpu_fState_S2$D_OUT;
  wire fpu_fState_S2$CLR,
       fpu_fState_S2$DEQ,
       fpu_fState_S2$EMPTY_N,
       fpu_fState_S2$ENQ,
       fpu_fState_S2$FULL_N;

  // ports of submodule fpu_fState_S3
  wire [151 : 0] fpu_fState_S3$D_IN, fpu_fState_S3$D_OUT;
  wire fpu_fState_S3$CLR,
       fpu_fState_S3$DEQ,
       fpu_fState_S3$EMPTY_N,
       fpu_fState_S3$ENQ,
       fpu_fState_S3$FULL_N;

  // ports of submodule fpu_fState_S4
  wire [203 : 0] fpu_fState_S4$D_IN, fpu_fState_S4$D_OUT;
  wire fpu_fState_S4$CLR,
       fpu_fState_S4$DEQ,
       fpu_fState_S4$EMPTY_N,
       fpu_fState_S4$ENQ,
       fpu_fState_S4$FULL_N;

  // ports of submodule fpu_fState_S5
  wire [215 : 0] fpu_fState_S5$D_IN, fpu_fState_S5$D_OUT;
  wire fpu_fState_S5$CLR,
       fpu_fState_S5$DEQ,
       fpu_fState_S5$EMPTY_N,
       fpu_fState_S5$ENQ,
       fpu_fState_S5$FULL_N;

  // ports of submodule fpu_fState_S6
  wire [202 : 0] fpu_fState_S6$D_IN, fpu_fState_S6$D_OUT;
  wire fpu_fState_S6$CLR,
       fpu_fState_S6$DEQ,
       fpu_fState_S6$EMPTY_N,
       fpu_fState_S6$ENQ,
       fpu_fState_S6$FULL_N;

  // ports of submodule fpu_fState_S7
  wire [202 : 0] fpu_fState_S7$D_IN, fpu_fState_S7$D_OUT;
  wire fpu_fState_S7$CLR,
       fpu_fState_S7$DEQ,
       fpu_fState_S7$EMPTY_N,
       fpu_fState_S7$ENQ,
       fpu_fState_S7$FULL_N;

  // ports of submodule fpu_fState_S8
  wire [140 : 0] fpu_fState_S8$D_IN, fpu_fState_S8$D_OUT;
  wire fpu_fState_S8$CLR,
       fpu_fState_S8$DEQ,
       fpu_fState_S8$EMPTY_N,
       fpu_fState_S8$ENQ,
       fpu_fState_S8$FULL_N;

  // rule scheduling signals
  wire CAN_FIRE_RL_fpu_s1_stage,
       CAN_FIRE_RL_fpu_s2_stage,
       CAN_FIRE_RL_fpu_s3_stage,
       CAN_FIRE_RL_fpu_s4_stage,
       CAN_FIRE_RL_fpu_s5_stage,
       CAN_FIRE_RL_fpu_s6_stage,
       CAN_FIRE_RL_fpu_s7_stage,
       CAN_FIRE_RL_fpu_s8_stage,
       CAN_FIRE_RL_fpu_s9_stage,
       CAN_FIRE_request_put,
       CAN_FIRE_response_get,
       WILL_FIRE_RL_fpu_s1_stage,
       WILL_FIRE_RL_fpu_s2_stage,
       WILL_FIRE_RL_fpu_s3_stage,
       WILL_FIRE_RL_fpu_s4_stage,
       WILL_FIRE_RL_fpu_s5_stage,
       WILL_FIRE_RL_fpu_s6_stage,
       WILL_FIRE_RL_fpu_s7_stage,
       WILL_FIRE_RL_fpu_s8_stage,
       WILL_FIRE_RL_fpu_s9_stage,
       WILL_FIRE_request_put,
       WILL_FIRE_response_get;

  // remaining internal signals
  reg [62 : 0] CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17,
	       CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18,
	       CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19;
  reg [51 : 0] CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1,
	       CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2,
	       _theResult___fst_sfd__h46438;
  reg [10 : 0] CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11,
	       CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12,
	       _theResult___fst_exp__h46437;
  reg CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13,
      CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14;
  wire [139 : 0] IF_NOT_fpu_fState_S4_first__48_BIT_130_54_59_O_ETC___d796;
  wire [118 : 0] IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d160;
  wire [105 : 0] IF_0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_fir_ETC__q4,
		 _theResult___fst__h20642,
		 _theResult___snd__h34781,
		 _theResult___snd__h34795,
		 _theResult___snd__h34797,
		 _theResult___snd__h34809,
		 _theResult___snd__h34815,
		 _theResult___snd__h34833,
		 _theResult___snd__h34838,
		 fpu_fProd_S3_first__10_SRL_IF_7170_MINUS_fpu_f_ETC___d213,
		 sfdBC__h19477,
		 sfdin__h34758,
		 x__h20711;
  wire [68 : 0] IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1282;
  wire [63 : 0] IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d137,
		IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d140,
		IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d139;
  wire [62 : 0] IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266,
		IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d735,
		IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d132,
		IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1153,
		IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d133,
		IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112,
		IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_ETC___d737;
  wire [56 : 0] IF_0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT__ETC__q9,
		_theResult___snd__h45207,
		_theResult___snd__h45221,
		_theResult___snd__h45223,
		_theResult___snd__h45235,
		_theResult___snd__h45241,
		_theResult___snd__h45259,
		_theResult___snd__h45264,
		fpu_fState_S5_first__02_BITS_56_TO_0_11_SRL_IF_ETC___d816,
		guard__h36182,
		result__h36187,
		sfdA__h35392,
		sfdBC__h35393,
		sfd__h36934,
		sfdin__h45184,
		x__h35755,
		x__h35759,
		x__h36174,
		x__h36686,
		x__h36695;
  wire [53 : 0] sfd__h45855;
  wire [52 : 0] x__h18058, x__h18070;
  wire [51 : 0] _theResult___fst_sfd__h396,
		_theResult___sfd__h46360,
		out_sfd__h46363,
		sfd__h3208,
		sfd__h3211,
		sfd__h3214;
  wire [12 : 0] IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769,
		IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764,
		_7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208,
		value__h34698,
		value__h45122,
		x__h20744,
		x__h36286;
  wire [11 : 0] IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232,
		IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d663,
		IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d1104,
		IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869;
  wire [10 : 0] IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1187,
		IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1212,
		_theResult___exp__h46359,
		_theResult___fst_exp__h34764,
		_theResult___fst_exp__h34767,
		_theResult___fst_exp__h34786,
		_theResult___fst_exp__h34801,
		_theResult___fst_exp__h34840,
		_theResult___fst_exp__h34846,
		_theResult___fst_exp__h34849,
		_theResult___fst_exp__h45190,
		_theResult___fst_exp__h45193,
		_theResult___fst_exp__h45212,
		_theResult___fst_exp__h45227,
		_theResult___fst_exp__h45266,
		_theResult___fst_exp__h45272,
		_theResult___fst_exp__h45275,
		din_exp4681_MINUS_1023__q3,
		din_exp__h34681,
		din_inc___2_exp__h46444,
		fpu_fOperand_S0D_OUT_BITS_129_TO_119_MINUS_1023__q15,
		fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q16,
		fpu_fState_S4D_OUT_BITS_128_TO_118_MINUS_1023__q7,
		fpu_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q6,
		out_exp__h46362,
		value5122_BITS_10_TO_0_MINUS_1023__q8,
		x__h327;
  wire [6 : 0] IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661;
  wire [5 : 0] IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102;
  wire [4 : 0] IF_fpu_fState_S3_first__96_BIT_151_97_THEN_fpu_ETC___d726,
	       fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702,
	       fpu_fState_S7_first__52_BITS_137_TO_133_57_OR__ETC___d1143,
	       fpu_fState_S8_first__161_BITS_75_TO_71_236_OR__ETC___d1244;
  wire [2 : 0] NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d724;
  wire [1 : 0] IF_sfdin4758_BIT_53_THEN_2_ELSE_0__q5,
	       IF_sfdin5184_BIT_4_THEN_2_ELSE_0__q10,
	       _theResult___snd_fst__h34866,
	       _theResult___snd_fst__h45292,
	       _theResult___snd_snd__h35186,
	       _theResult___snd_snd_snd__h35184,
	       guardBC__h19481,
	       guard__h36938,
	       x__h35221,
	       x__h45575;
  wire IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d123,
       IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d704,
       IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d707,
       IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d128,
       IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d148,
       IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d62,
       IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d717,
       IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d722,
       IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1261,
       NOT_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu__ETC___d147,
       NOT_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_ETC___d124,
       NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55,
       NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d711,
       NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785,
       _0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_first__ETC___d664,
       _0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT_128_ETC___d1105,
       _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d209,
       fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d127,
       fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d58,
       fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56,
       fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203,
       fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205,
       sfdlsb__h20640;

  // action method request_put
  assign RDY_request_put = fpu_fOperand_S0$FULL_N ;
  assign CAN_FIRE_request_put = fpu_fOperand_S0$FULL_N ;
  assign WILL_FIRE_request_put = EN_request_put ;

  // actionvalue method response_get
  assign response_get = fpu_fResult_S9$D_OUT ;
  assign RDY_response_get = fpu_fResult_S9$EMPTY_N ;
  assign CAN_FIRE_response_get = fpu_fResult_S9$EMPTY_N ;
  assign WILL_FIRE_response_get = EN_response_get ;

  // submodule fpu_fOperand_S0
  FIFOL1 #(.width(32'd196)) fpu_fOperand_S0(.RST(RST_N),
					    .CLK(CLK),
					    .D_IN(fpu_fOperand_S0$D_IN),
					    .ENQ(fpu_fOperand_S0$ENQ),
					    .DEQ(fpu_fOperand_S0$DEQ),
					    .CLR(fpu_fOperand_S0$CLR),
					    .D_OUT(fpu_fOperand_S0$D_OUT),
					    .FULL_N(fpu_fOperand_S0$FULL_N),
					    .EMPTY_N(fpu_fOperand_S0$EMPTY_N));

  // submodule fpu_fProd_S2
  FIFOL1 #(.width(32'd106)) fpu_fProd_S2(.RST(RST_N),
					 .CLK(CLK),
					 .D_IN(fpu_fProd_S2$D_IN),
					 .ENQ(fpu_fProd_S2$ENQ),
					 .DEQ(fpu_fProd_S2$DEQ),
					 .CLR(fpu_fProd_S2$CLR),
					 .D_OUT(fpu_fProd_S2$D_OUT),
					 .FULL_N(fpu_fProd_S2$FULL_N),
					 .EMPTY_N(fpu_fProd_S2$EMPTY_N));

  // submodule fpu_fProd_S3
  FIFOL1 #(.width(32'd106)) fpu_fProd_S3(.RST(RST_N),
					 .CLK(CLK),
					 .D_IN(fpu_fProd_S3$D_IN),
					 .ENQ(fpu_fProd_S3$ENQ),
					 .DEQ(fpu_fProd_S3$DEQ),
					 .CLR(fpu_fProd_S3$CLR),
					 .D_OUT(fpu_fProd_S3$D_OUT),
					 .FULL_N(fpu_fProd_S3$FULL_N),
					 .EMPTY_N(fpu_fProd_S3$EMPTY_N));

  // submodule fpu_fResult_S9
  FIFOL1 #(.width(32'd69)) fpu_fResult_S9(.RST(RST_N),
					  .CLK(CLK),
					  .D_IN(fpu_fResult_S9$D_IN),
					  .ENQ(fpu_fResult_S9$ENQ),
					  .DEQ(fpu_fResult_S9$DEQ),
					  .CLR(fpu_fResult_S9$CLR),
					  .D_OUT(fpu_fResult_S9$D_OUT),
					  .FULL_N(fpu_fResult_S9$FULL_N),
					  .EMPTY_N(fpu_fResult_S9$EMPTY_N));

  // submodule fpu_fState_S1
  FIFOL1 #(.width(32'd258)) fpu_fState_S1(.RST(RST_N),
					  .CLK(CLK),
					  .D_IN(fpu_fState_S1$D_IN),
					  .ENQ(fpu_fState_S1$ENQ),
					  .DEQ(fpu_fState_S1$DEQ),
					  .CLR(fpu_fState_S1$CLR),
					  .D_OUT(fpu_fState_S1$D_OUT),
					  .FULL_N(fpu_fState_S1$FULL_N),
					  .EMPTY_N(fpu_fState_S1$EMPTY_N));

  // submodule fpu_fState_S2
  FIFOL1 #(.width(32'd152)) fpu_fState_S2(.RST(RST_N),
					  .CLK(CLK),
					  .D_IN(fpu_fState_S2$D_IN),
					  .ENQ(fpu_fState_S2$ENQ),
					  .DEQ(fpu_fState_S2$DEQ),
					  .CLR(fpu_fState_S2$CLR),
					  .D_OUT(fpu_fState_S2$D_OUT),
					  .FULL_N(fpu_fState_S2$FULL_N),
					  .EMPTY_N(fpu_fState_S2$EMPTY_N));

  // submodule fpu_fState_S3
  FIFOL1 #(.width(32'd152)) fpu_fState_S3(.RST(RST_N),
					  .CLK(CLK),
					  .D_IN(fpu_fState_S3$D_IN),
					  .ENQ(fpu_fState_S3$ENQ),
					  .DEQ(fpu_fState_S3$DEQ),
					  .CLR(fpu_fState_S3$CLR),
					  .D_OUT(fpu_fState_S3$D_OUT),
					  .FULL_N(fpu_fState_S3$FULL_N),
					  .EMPTY_N(fpu_fState_S3$EMPTY_N));

  // submodule fpu_fState_S4
  FIFOL1 #(.width(32'd204)) fpu_fState_S4(.RST(RST_N),
					  .CLK(CLK),
					  .D_IN(fpu_fState_S4$D_IN),
					  .ENQ(fpu_fState_S4$ENQ),
					  .DEQ(fpu_fState_S4$DEQ),
					  .CLR(fpu_fState_S4$CLR),
					  .D_OUT(fpu_fState_S4$D_OUT),
					  .FULL_N(fpu_fState_S4$FULL_N),
					  .EMPTY_N(fpu_fState_S4$EMPTY_N));

  // submodule fpu_fState_S5
  FIFOL1 #(.width(32'd216)) fpu_fState_S5(.RST(RST_N),
					  .CLK(CLK),
					  .D_IN(fpu_fState_S5$D_IN),
					  .ENQ(fpu_fState_S5$ENQ),
					  .DEQ(fpu_fState_S5$DEQ),
					  .CLR(fpu_fState_S5$CLR),
					  .D_OUT(fpu_fState_S5$D_OUT),
					  .FULL_N(fpu_fState_S5$FULL_N),
					  .EMPTY_N(fpu_fState_S5$EMPTY_N));

  // submodule fpu_fState_S6
  FIFOL1 #(.width(32'd203)) fpu_fState_S6(.RST(RST_N),
					  .CLK(CLK),
					  .D_IN(fpu_fState_S6$D_IN),
					  .ENQ(fpu_fState_S6$ENQ),
					  .DEQ(fpu_fState_S6$DEQ),
					  .CLR(fpu_fState_S6$CLR),
					  .D_OUT(fpu_fState_S6$D_OUT),
					  .FULL_N(fpu_fState_S6$FULL_N),
					  .EMPTY_N(fpu_fState_S6$EMPTY_N));

  // submodule fpu_fState_S7
  FIFOL1 #(.width(32'd203)) fpu_fState_S7(.RST(RST_N),
					  .CLK(CLK),
					  .D_IN(fpu_fState_S7$D_IN),
					  .ENQ(fpu_fState_S7$ENQ),
					  .DEQ(fpu_fState_S7$DEQ),
					  .CLR(fpu_fState_S7$CLR),
					  .D_OUT(fpu_fState_S7$D_OUT),
					  .FULL_N(fpu_fState_S7$FULL_N),
					  .EMPTY_N(fpu_fState_S7$EMPTY_N));

  // submodule fpu_fState_S8
  FIFOL1 #(.width(32'd141)) fpu_fState_S8(.RST(RST_N),
					  .CLK(CLK),
					  .D_IN(fpu_fState_S8$D_IN),
					  .ENQ(fpu_fState_S8$ENQ),
					  .DEQ(fpu_fState_S8$DEQ),
					  .CLR(fpu_fState_S8$CLR),
					  .D_OUT(fpu_fState_S8$D_OUT),
					  .FULL_N(fpu_fState_S8$FULL_N),
					  .EMPTY_N(fpu_fState_S8$EMPTY_N));

  // rule RL_fpu_s9_stage
  assign CAN_FIRE_RL_fpu_s9_stage =
	     fpu_fState_S8$EMPTY_N && fpu_fResult_S9$FULL_N ;
  assign WILL_FIRE_RL_fpu_s9_stage = CAN_FIRE_RL_fpu_s9_stage ;

  // rule RL_fpu_s8_stage
  assign CAN_FIRE_RL_fpu_s8_stage =
	     fpu_fState_S7$EMPTY_N && fpu_fState_S8$FULL_N ;
  assign WILL_FIRE_RL_fpu_s8_stage = CAN_FIRE_RL_fpu_s8_stage ;

  // rule RL_fpu_s7_stage
  assign CAN_FIRE_RL_fpu_s7_stage =
	     fpu_fState_S6$EMPTY_N && fpu_fState_S7$FULL_N ;
  assign WILL_FIRE_RL_fpu_s7_stage = CAN_FIRE_RL_fpu_s7_stage ;

  // rule RL_fpu_s6_stage
  assign CAN_FIRE_RL_fpu_s6_stage =
	     fpu_fState_S5$EMPTY_N && fpu_fState_S6$FULL_N ;
  assign WILL_FIRE_RL_fpu_s6_stage = CAN_FIRE_RL_fpu_s6_stage ;

  // rule RL_fpu_s5_stage
  assign CAN_FIRE_RL_fpu_s5_stage =
	     fpu_fState_S4$EMPTY_N && fpu_fState_S5$FULL_N ;
  assign WILL_FIRE_RL_fpu_s5_stage = CAN_FIRE_RL_fpu_s5_stage ;

  // rule RL_fpu_s4_stage
  assign CAN_FIRE_RL_fpu_s4_stage =
	     fpu_fState_S3$EMPTY_N && fpu_fProd_S3$EMPTY_N &&
	     fpu_fState_S4$FULL_N ;
  assign WILL_FIRE_RL_fpu_s4_stage = CAN_FIRE_RL_fpu_s4_stage ;

  // rule RL_fpu_s3_stage
  assign CAN_FIRE_RL_fpu_s3_stage =
	     fpu_fState_S2$EMPTY_N && fpu_fProd_S2$EMPTY_N &&
	     fpu_fProd_S3$FULL_N &&
	     fpu_fState_S3$FULL_N ;
  assign WILL_FIRE_RL_fpu_s3_stage = CAN_FIRE_RL_fpu_s3_stage ;

  // rule RL_fpu_s2_stage
  assign CAN_FIRE_RL_fpu_s2_stage =
	     fpu_fState_S1$EMPTY_N && fpu_fProd_S2$FULL_N &&
	     fpu_fState_S2$FULL_N ;
  assign WILL_FIRE_RL_fpu_s2_stage = CAN_FIRE_RL_fpu_s2_stage ;

  // rule RL_fpu_s1_stage
  assign CAN_FIRE_RL_fpu_s1_stage =
	     fpu_fOperand_S0$EMPTY_N && fpu_fState_S1$FULL_N ;
  assign WILL_FIRE_RL_fpu_s1_stage = CAN_FIRE_RL_fpu_s1_stage ;

  // submodule fpu_fOperand_S0
  assign fpu_fOperand_S0$D_IN = request_put ;
  assign fpu_fOperand_S0$ENQ = EN_request_put ;
  assign fpu_fOperand_S0$DEQ = CAN_FIRE_RL_fpu_s1_stage ;
  assign fpu_fOperand_S0$CLR = 1'b0 ;

  // submodule fpu_fProd_S2
  assign fpu_fProd_S2$D_IN =
	     fpu_fState_S1$D_OUT[105:53] * fpu_fState_S1$D_OUT[52:0] ;
  assign fpu_fProd_S2$ENQ = CAN_FIRE_RL_fpu_s2_stage ;
  assign fpu_fProd_S2$DEQ = CAN_FIRE_RL_fpu_s3_stage ;
  assign fpu_fProd_S2$CLR = 1'b0 ;

  // submodule fpu_fProd_S3
  assign fpu_fProd_S3$D_IN = fpu_fProd_S2$D_OUT ;
  assign fpu_fProd_S3$ENQ = CAN_FIRE_RL_fpu_s3_stage ;
  assign fpu_fProd_S3$DEQ = CAN_FIRE_RL_fpu_s4_stage ;
  assign fpu_fProd_S3$CLR = 1'b0 ;

  // submodule fpu_fResult_S9
  assign fpu_fResult_S9$D_IN =
	     fpu_fState_S8$D_OUT[140] ?
	       fpu_fState_S8$D_OUT[139:71] :
	       IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1282 ;
  assign fpu_fResult_S9$ENQ = CAN_FIRE_RL_fpu_s9_stage ;
  assign fpu_fResult_S9$DEQ = EN_response_get ;
  assign fpu_fResult_S9$CLR = 1'b0 ;

  // submodule fpu_fState_S1
  assign fpu_fState_S1$D_IN =
	     { x__h327 == 11'd2047 && _theResult___fst_sfd__h396 != 52'd0 &&
	       !_theResult___fst_sfd__h396[51] ||
	       fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
	       fpu_fOperand_S0$D_OUT[118:67] != 52'd0 &&
	       !fpu_fOperand_S0$D_OUT[118] ||
	       fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
	       fpu_fOperand_S0$D_OUT[54:3] != 52'd0 &&
	       !fpu_fOperand_S0$D_OUT[54] ||
	       IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d62,
	       IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d140,
	       IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d148,
	       4'd0,
	       fpu_fOperand_S0$D_OUT[2:0],
	       fpu_fOperand_S0$D_OUT[195],
	       fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194],
	       IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112,
	       NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55,
	       IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d160 } ;
  assign fpu_fState_S1$ENQ = CAN_FIRE_RL_fpu_s1_stage ;
  assign fpu_fState_S1$DEQ = CAN_FIRE_RL_fpu_s2_stage ;
  assign fpu_fState_S1$CLR = 1'b0 ;

  // submodule fpu_fState_S2
  assign fpu_fState_S2$D_IN = fpu_fState_S1$D_OUT[257:106] ;
  assign fpu_fState_S2$ENQ = CAN_FIRE_RL_fpu_s2_stage ;
  assign fpu_fState_S2$DEQ = CAN_FIRE_RL_fpu_s3_stage ;
  assign fpu_fState_S2$CLR = 1'b0 ;

  // submodule fpu_fState_S3
  assign fpu_fState_S3$D_IN = fpu_fState_S2$D_OUT ;
  assign fpu_fState_S3$ENQ = CAN_FIRE_RL_fpu_s3_stage ;
  assign fpu_fState_S3$DEQ = CAN_FIRE_RL_fpu_s4_stage ;
  assign fpu_fState_S3$CLR = 1'b0 ;

  // submodule fpu_fState_S4
  assign fpu_fState_S4$D_IN =
	     { fpu_fState_S3$D_OUT[151:87],
	       IF_fpu_fState_S3_first__96_BIT_151_97_THEN_fpu_ETC___d726,
	       fpu_fState_S3$D_OUT[81:14],
	       !fpu_fState_S3$D_OUT[151] && fpu_fState_S3$D_OUT[13],
	       fpu_fState_S3$D_OUT[151] ?
		 63'd0 :
		 IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_ETC___d737,
	       x__h35221 } ;
  assign fpu_fState_S4$ENQ = CAN_FIRE_RL_fpu_s4_stage ;
  assign fpu_fState_S4$DEQ = CAN_FIRE_RL_fpu_s5_stage ;
  assign fpu_fState_S4$CLR = 1'b0 ;

  // submodule fpu_fState_S5
  assign fpu_fState_S5$D_IN =
	     { fpu_fState_S4$D_OUT[203:130],
	       fpu_fState_S4$D_OUT[129] != fpu_fState_S4$D_OUT[65],
	       NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ?
		 fpu_fState_S4$D_OUT[65] :
		 fpu_fState_S4$D_OUT[129],
	       IF_NOT_fpu_fState_S4_first__48_BIT_130_54_59_O_ETC___d796 } ;
  assign fpu_fState_S5$ENQ = CAN_FIRE_RL_fpu_s5_stage ;
  assign fpu_fState_S5$DEQ = CAN_FIRE_RL_fpu_s6_stage ;
  assign fpu_fState_S5$CLR = 1'b0 ;

  // submodule fpu_fState_S6
  assign fpu_fState_S6$D_IN =
	     { fpu_fState_S5$D_OUT[215:127],
	       fpu_fState_S5$D_OUT[113:57],
	       x__h36174 } ;
  assign fpu_fState_S6$ENQ = CAN_FIRE_RL_fpu_s6_stage ;
  assign fpu_fState_S6$DEQ = CAN_FIRE_RL_fpu_s7_stage ;
  assign fpu_fState_S6$CLR = 1'b0 ;

  // submodule fpu_fState_S7
  assign fpu_fState_S7$D_IN =
	     { fpu_fState_S6$D_OUT[202:114], x__h36686, x__h36695 } ;
  assign fpu_fState_S7$ENQ = CAN_FIRE_RL_fpu_s7_stage ;
  assign fpu_fState_S7$DEQ = CAN_FIRE_RL_fpu_s8_stage ;
  assign fpu_fState_S7$CLR = 1'b0 ;

  // submodule fpu_fState_S8
  assign fpu_fState_S8$D_IN =
	     { fpu_fState_S7$D_OUT[202:138],
	       fpu_fState_S7$D_OUT[202] ?
		 fpu_fState_S7$D_OUT[137:133] :
		 fpu_fState_S7_first__52_BITS_137_TO_133_57_OR__ETC___d1143,
	       fpu_fState_S7$D_OUT[132:129],
	       !fpu_fState_S7$D_OUT[202] && fpu_fState_S7$D_OUT[127],
	       fpu_fState_S7$D_OUT[202] ?
		 63'd0 :
		 IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1153,
	       x__h45575,
	       fpu_fState_S7$D_OUT[128] } ;
  assign fpu_fState_S8$ENQ = CAN_FIRE_RL_fpu_s8_stage ;
  assign fpu_fState_S8$DEQ = CAN_FIRE_RL_fpu_s9_stage ;
  assign fpu_fState_S8$CLR = 1'b0 ;

  // remaining internal signals
  assign IF_0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_fir_ETC__q4 =
	     _0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_first__ETC___d664 ?
	       _theResult___snd__h34838 :
	       _theResult___snd__h34833 ;
  assign IF_0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT__ETC__q9 =
	     _0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT_128_ETC___d1105 ?
	       _theResult___snd__h45264 :
	       _theResult___snd__h45259 ;
  assign IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266 =
	     sfd__h45855[53] ?
	       ((fpu_fState_S8$D_OUT[65:55] == 11'd2046) ?
		  63'h7FF0000000000000 :
		  { din_inc___2_exp__h46444, sfd__h45855[52:1] }) :
	       { IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1187,
		 sfd__h45855[51:0] } ;
  assign IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 =
	     (din_exp__h34681 == 11'd0) ?
	       12'd3074 :
	       { din_exp4681_MINUS_1023__q3[10],
		 din_exp4681_MINUS_1023__q3 } ;
  assign IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661 =
	     (sfdBC__h19477[105] ?
		7'd0 :
		(sfdBC__h19477[104] ?
		   7'd1 :
		   (sfdBC__h19477[103] ?
		      7'd2 :
		      (sfdBC__h19477[102] ?
			 7'd3 :
			 (sfdBC__h19477[101] ?
			    7'd4 :
			    (sfdBC__h19477[100] ?
			       7'd5 :
			       (sfdBC__h19477[99] ?
				  7'd6 :
				  (sfdBC__h19477[98] ?
				     7'd7 :
				     (sfdBC__h19477[97] ?
					7'd8 :
					(sfdBC__h19477[96] ?
					   7'd9 :
					   (sfdBC__h19477[95] ?
					      7'd10 :
					      (sfdBC__h19477[94] ?
						 7'd11 :
						 (sfdBC__h19477[93] ?
						    7'd12 :
						    (sfdBC__h19477[92] ?
						       7'd13 :
						       (sfdBC__h19477[91] ?
							  7'd14 :
							  (sfdBC__h19477[90] ?
							     7'd15 :
							     (sfdBC__h19477[89] ?
								7'd16 :
								(sfdBC__h19477[88] ?
								   7'd17 :
								   (sfdBC__h19477[87] ?
								      7'd18 :
								      (sfdBC__h19477[86] ?
									 7'd19 :
									 (sfdBC__h19477[85] ?
									    7'd20 :
									    (sfdBC__h19477[84] ?
									       7'd21 :
									       (sfdBC__h19477[83] ?
										  7'd22 :
										  (sfdBC__h19477[82] ?
										     7'd23 :
										     (sfdBC__h19477[81] ?
											7'd24 :
											(sfdBC__h19477[80] ?
											   7'd25 :
											   (sfdBC__h19477[79] ?
											      7'd26 :
											      (sfdBC__h19477[78] ?
												 7'd27 :
												 (sfdBC__h19477[77] ?
												    7'd28 :
												    (sfdBC__h19477[76] ?
												       7'd29 :
												       (sfdBC__h19477[75] ?
													  7'd30 :
													  (sfdBC__h19477[74] ?
													     7'd31 :
													     (sfdBC__h19477[73] ?
														7'd32 :
														(sfdBC__h19477[72] ?
														   7'd33 :
														   (sfdBC__h19477[71] ?
														      7'd34 :
														      (sfdBC__h19477[70] ?
															 7'd35 :
															 (sfdBC__h19477[69] ?
															    7'd36 :
															    (sfdBC__h19477[68] ?
															       7'd37 :
															       (sfdBC__h19477[67] ?
																  7'd38 :
																  (sfdBC__h19477[66] ?
																     7'd39 :
																     (sfdBC__h19477[65] ?
																	7'd40 :
																	(sfdBC__h19477[64] ?
																	   7'd41 :
																	   (sfdBC__h19477[63] ?
																	      7'd42 :
																	      (sfdBC__h19477[62] ?
																		 7'd43 :
																		 (sfdBC__h19477[61] ?
																		    7'd44 :
																		    (sfdBC__h19477[60] ?
																		       7'd45 :
																		       (sfdBC__h19477[59] ?
																			  7'd46 :
																			  (sfdBC__h19477[58] ?
																			     7'd47 :
																			     (sfdBC__h19477[57] ?
																				7'd48 :
																				(sfdBC__h19477[56] ?
																				   7'd49 :
																				   (sfdBC__h19477[55] ?
																				      7'd50 :
																				      (sfdBC__h19477[54] ?
																					 7'd51 :
																					 (sfdBC__h19477[53] ?
																					    7'd52 :
																					    (sfdBC__h19477[52] ?
																					       7'd53 :
																					       (sfdBC__h19477[51] ?
																						  7'd54 :
																						  (sfdBC__h19477[50] ?
																						     7'd55 :
																						     (sfdBC__h19477[49] ?
																							7'd56 :
																							(sfdBC__h19477[48] ?
																							   7'd57 :
																							   (sfdBC__h19477[47] ?
																							      7'd58 :
																							      (sfdBC__h19477[46] ?
																								 7'd59 :
																								 (sfdBC__h19477[45] ?
																								    7'd60 :
																								    (sfdBC__h19477[44] ?
																								       7'd61 :
																								       (sfdBC__h19477[43] ?
																									  7'd62 :
																									  (sfdBC__h19477[42] ?
																									     7'd63 :
																									     (sfdBC__h19477[41] ?
																										7'd64 :
																										(sfdBC__h19477[40] ?
																										   7'd65 :
																										   (sfdBC__h19477[39] ?
																										      7'd66 :
																										      (sfdBC__h19477[38] ?
																											 7'd67 :
																											 (sfdBC__h19477[37] ?
																											    7'd68 :
																											    (sfdBC__h19477[36] ?
																											       7'd69 :
																											       (sfdBC__h19477[35] ?
																												  7'd70 :
																												  (sfdBC__h19477[34] ?
																												     7'd71 :
																												     (sfdBC__h19477[33] ?
																													7'd72 :
																													(sfdBC__h19477[32] ?
																													   7'd73 :
																													   (sfdBC__h19477[31] ?
																													      7'd74 :
																													      (sfdBC__h19477[30] ?
																														 7'd75 :
																														 (sfdBC__h19477[29] ?
																														    7'd76 :
																														    (sfdBC__h19477[28] ?
																														       7'd77 :
																														       (sfdBC__h19477[27] ?
																															  7'd78 :
																															  (sfdBC__h19477[26] ?
																															     7'd79 :
																															     (sfdBC__h19477[25] ?
																																7'd80 :
																																(sfdBC__h19477[24] ?
																																   7'd81 :
																																   (sfdBC__h19477[23] ?
																																      7'd82 :
																																      (sfdBC__h19477[22] ?
																																	 7'd83 :
																																	 (sfdBC__h19477[21] ?
																																	    7'd84 :
																																	    (sfdBC__h19477[20] ?
																																	       7'd85 :
																																	       (sfdBC__h19477[19] ?
																																		  7'd86 :
																																		  (sfdBC__h19477[18] ?
																																		     7'd87 :
																																		     (sfdBC__h19477[17] ?
																																			7'd88 :
																																			(sfdBC__h19477[16] ?
																																			   7'd89 :
																																			   (sfdBC__h19477[15] ?
																																			      7'd90 :
																																			      (sfdBC__h19477[14] ?
																																				 7'd91 :
																																				 (sfdBC__h19477[13] ?
																																				    7'd92 :
																																				    (sfdBC__h19477[12] ?
																																				       7'd93 :
																																				       (sfdBC__h19477[11] ?
																																					  7'd94 :
																																					  (sfdBC__h19477[10] ?
																																					     7'd95 :
																																					     (sfdBC__h19477[9] ?
																																						7'd96 :
																																						(sfdBC__h19477[8] ?
																																						   7'd97 :
																																						   (sfdBC__h19477[7] ?
																																						      7'd98 :
																																						      (sfdBC__h19477[6] ?
																																							 7'd99 :
																																							 (sfdBC__h19477[5] ?
																																							    7'd100 :
																																							    (sfdBC__h19477[4] ?
																																							       7'd101 :
																																							       (sfdBC__h19477[3] ?
																																								  7'd102 :
																																								  (sfdBC__h19477[2] ?
																																								     7'd103 :
																																								     (sfdBC__h19477[1] ?
																																									7'd104 :
																																									(sfdBC__h19477[0] ?
																																									   7'd105 :
																																									   7'd106)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     7'd1 ;
  assign IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d663 =
	     IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 -
	     12'd3074 ;
  assign IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d735 =
	     (sfdBC__h19477[105] &&
	      IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 ==
	      12'd1023) ?
	       63'h7FEFFFFFFFFFFFFF :
	       { _theResult___fst_exp__h34764, sfdin__h34758[105:54] } ;
  assign IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d123 =
	     (x__h327 == 11'd2047 && _theResult___fst_sfd__h396 == 52'd0) ?
	       fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194] :
	       ((fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
		 fpu_fOperand_S0$D_OUT[118:67] == 52'd0 ||
		 fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
		 fpu_fOperand_S0$D_OUT[54:3] == 52'd0) ?
		  NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55 :
		  fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194]) ;
  assign IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d132 =
	     (x__h327 == 11'd2047 && _theResult___fst_sfd__h396 == 52'd0) ?
	       IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112 :
	       ((fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
		 fpu_fOperand_S0$D_OUT[118:67] == 52'd0 ||
		 fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
		 fpu_fOperand_S0$D_OUT[54:3] == 52'd0) ?
		  63'h7FF0000000000000 :
		  IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112) ;
  assign IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d137 =
	     (x__h327 == 11'd2047 && _theResult___fst_sfd__h396[51]) ?
	       { fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194],
		 IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112 } :
	       ((fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
		 fpu_fOperand_S0$D_OUT[118]) ?
		  fpu_fOperand_S0$D_OUT[130:67] :
		  ((fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
		    fpu_fOperand_S0$D_OUT[54]) ?
		     fpu_fOperand_S0$D_OUT[66:3] :
		     { NOT_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_ETC___d124,
		       IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d133 })) ;
  assign IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d140 =
	     (x__h327 == 11'd2047 && _theResult___fst_sfd__h396 != 52'd0 &&
	      !_theResult___fst_sfd__h396[51]) ?
	       { fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194],
		 x__h327,
		 sfd__h3208 } :
	       IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d139 ;
  assign IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102 =
	     (sfd__h36934[56] ?
		6'd0 :
		(sfd__h36934[55] ?
		   6'd1 :
		   (sfd__h36934[54] ?
		      6'd2 :
		      (sfd__h36934[53] ?
			 6'd3 :
			 (sfd__h36934[52] ?
			    6'd4 :
			    (sfd__h36934[51] ?
			       6'd5 :
			       (sfd__h36934[50] ?
				  6'd6 :
				  (sfd__h36934[49] ?
				     6'd7 :
				     (sfd__h36934[48] ?
					6'd8 :
					(sfd__h36934[47] ?
					   6'd9 :
					   (sfd__h36934[46] ?
					      6'd10 :
					      (sfd__h36934[45] ?
						 6'd11 :
						 (sfd__h36934[44] ?
						    6'd12 :
						    (sfd__h36934[43] ?
						       6'd13 :
						       (sfd__h36934[42] ?
							  6'd14 :
							  (sfd__h36934[41] ?
							     6'd15 :
							     (sfd__h36934[40] ?
								6'd16 :
								(sfd__h36934[39] ?
								   6'd17 :
								   (sfd__h36934[38] ?
								      6'd18 :
								      (sfd__h36934[37] ?
									 6'd19 :
									 (sfd__h36934[36] ?
									    6'd20 :
									    (sfd__h36934[35] ?
									       6'd21 :
									       (sfd__h36934[34] ?
										  6'd22 :
										  (sfd__h36934[33] ?
										     6'd23 :
										     (sfd__h36934[32] ?
											6'd24 :
											(sfd__h36934[31] ?
											   6'd25 :
											   (sfd__h36934[30] ?
											      6'd26 :
											      (sfd__h36934[29] ?
												 6'd27 :
												 (sfd__h36934[28] ?
												    6'd28 :
												    (sfd__h36934[27] ?
												       6'd29 :
												       (sfd__h36934[26] ?
													  6'd30 :
													  (sfd__h36934[25] ?
													     6'd31 :
													     (sfd__h36934[24] ?
														6'd32 :
														(sfd__h36934[23] ?
														   6'd33 :
														   (sfd__h36934[22] ?
														      6'd34 :
														      (sfd__h36934[21] ?
															 6'd35 :
															 (sfd__h36934[20] ?
															    6'd36 :
															    (sfd__h36934[19] ?
															       6'd37 :
															       (sfd__h36934[18] ?
																  6'd38 :
																  (sfd__h36934[17] ?
																     6'd39 :
																     (sfd__h36934[16] ?
																	6'd40 :
																	(sfd__h36934[15] ?
																	   6'd41 :
																	   (sfd__h36934[14] ?
																	      6'd42 :
																	      (sfd__h36934[13] ?
																		 6'd43 :
																		 (sfd__h36934[12] ?
																		    6'd44 :
																		    (sfd__h36934[11] ?
																		       6'd45 :
																		       (sfd__h36934[10] ?
																			  6'd46 :
																			  (sfd__h36934[9] ?
																			     6'd47 :
																			     (sfd__h36934[8] ?
																				6'd48 :
																				(sfd__h36934[7] ?
																				   6'd49 :
																				   (sfd__h36934[6] ?
																				      6'd50 :
																				      (sfd__h36934[5] ?
																					 6'd51 :
																					 (sfd__h36934[4] ?
																					    6'd52 :
																					    (sfd__h36934[3] ?
																					       6'd53 :
																					       (sfd__h36934[2] ?
																						  6'd54 :
																						  (sfd__h36934[1] ?
																						     6'd55 :
																						     (sfd__h36934[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1153 =
	     (sfd__h36934[56] &&
	      IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 ==
	      12'd1023) ?
	       63'h7FEFFFFFFFFFFFFF :
	       { _theResult___fst_exp__h45190, sfdin__h45184[56:5] } ;
  assign IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d704 =
	     (!fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 ||
	      fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205) ?
	       fpu_fState_S3$D_OUT[86] :
	       fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[4] ;
  assign IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d707 =
	     (!fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 ||
	      fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205) ?
	       fpu_fState_S3$D_OUT[85] :
	       fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[3] ;
  assign IF_NOT_fpu_fState_S4_first__48_BIT_130_54_59_O_ETC___d796 =
	     { NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ?
		 IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 :
		 IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769,
	       NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ?
		 IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 -
		 IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 :
		 IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 -
		 IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764,
	       x__h35755,
	       x__h35759 } ;
  assign IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d133 =
	     (fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d127 ||
	      IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d128 &&
	      !fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56) ?
	       63'h7FF8000000000000 :
	       IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d132 ;
  assign IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d139 =
	     (fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
	      fpu_fOperand_S0$D_OUT[118:67] != 52'd0 &&
	      !fpu_fOperand_S0$D_OUT[118]) ?
	       { fpu_fOperand_S0$D_OUT[130:119], sfd__h3211 } :
	       ((fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
		 fpu_fOperand_S0$D_OUT[54:3] != 52'd0 &&
		 !fpu_fOperand_S0$D_OUT[54]) ?
		  { fpu_fOperand_S0$D_OUT[66:55], sfd__h3214 } :
		  IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d137) ;
  assign IF_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ__ETC___d160 =
	     { ((fpu_fOperand_S0$D_OUT[129:119] == 11'd0) ?
		  13'd7170 :
		  { {2{fpu_fOperand_S0D_OUT_BITS_129_TO_119_MINUS_1023__q15[10]}},
		    fpu_fOperand_S0D_OUT_BITS_129_TO_119_MINUS_1023__q15 }) +
	       ((fpu_fOperand_S0$D_OUT[65:55] == 11'd0) ?
		  13'd7170 :
		  { {2{fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q16[10]}},
		    fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q16 }),
	       x__h18058,
	       x__h18070 } ;
  assign IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d112 =
	     fpu_fOperand_S0$D_OUT[195] ?
	       fpu_fOperand_S0$D_OUT[193:131] :
	       63'd0 ;
  assign IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d128 =
	     x__h327 == 11'd2047 && _theResult___fst_sfd__h396 == 52'd0 &&
	     (fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
	      fpu_fOperand_S0$D_OUT[118:67] == 52'd0 ||
	      fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
	      fpu_fOperand_S0$D_OUT[54:3] == 52'd0) ;
  assign IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d148 =
	     x__h327 == 11'd2047 && _theResult___fst_sfd__h396 != 52'd0 &&
	     !_theResult___fst_sfd__h396[51] ||
	     fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
	     fpu_fOperand_S0$D_OUT[118:67] != 52'd0 &&
	     !fpu_fOperand_S0$D_OUT[118] ||
	     fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
	     fpu_fOperand_S0$D_OUT[54:3] != 52'd0 &&
	     !fpu_fOperand_S0$D_OUT[54] ||
	     NOT_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu__ETC___d147 ;
  assign IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d62 =
	     x__h327 == 11'd2047 && _theResult___fst_sfd__h396[51] ||
	     fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
	     fpu_fOperand_S0$D_OUT[118] ||
	     fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
	     fpu_fOperand_S0$D_OUT[54] ||
	     x__h327 == 11'd2047 && _theResult___fst_sfd__h396 == 52'd0 ||
	     fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d58 ;
  assign IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_ETC___d737 =
	     fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 ?
	       (fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ?
		  63'd0 :
		  IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d735) :
	       63'h7FEFFFFFFFFFFFFF ;
  assign IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d717 =
	     fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ?
	       fpu_fProd_S3$D_OUT != 106'd0 || fpu_fState_S3$D_OUT[83] :
	       fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[1] ;
  assign IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d722 =
	     fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ?
	       fpu_fProd_S3$D_OUT != 106'd0 || fpu_fState_S3$D_OUT[82] :
	       fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[0] ;
  assign IF_fpu_fState_S3_first__96_BIT_151_97_THEN_fpu_ETC___d726 =
	     fpu_fState_S3$D_OUT[151] ?
	       fpu_fState_S3$D_OUT[86:82] :
	       { IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d704,
		 IF_NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_ETC___d707,
		 NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d724 } ;
  assign IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 =
	     (fpu_fState_S4$D_OUT[128:118] == 11'd0) ?
	       13'd7170 :
	       { {2{fpu_fState_S4D_OUT_BITS_128_TO_118_MINUS_1023__q7[10]}},
		 fpu_fState_S4D_OUT_BITS_128_TO_118_MINUS_1023__q7 } ;
  assign IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 =
	     (fpu_fState_S4$D_OUT[64:54] == 11'd0) ?
	       13'd7170 :
	       { {2{fpu_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q6[10]}},
		 fpu_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q6 } ;
  assign IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d1104 =
	     IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 -
	     12'd3074 ;
  assign IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 =
	     (value__h45122[10:0] == 11'd0) ?
	       12'd3074 :
	       { value5122_BITS_10_TO_0_MINUS_1023__q8[10],
		 value5122_BITS_10_TO_0_MINUS_1023__q8 } ;
  assign IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1187 =
	     (fpu_fState_S8$D_OUT[65:55] == 11'd0 &&
	      sfd__h45855[53:52] == 2'b01) ?
	       11'd1 :
	       fpu_fState_S8$D_OUT[65:55] ;
  assign IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1212 =
	     (fpu_fState_S8$D_OUT[65:55] == 11'd2047) ?
	       fpu_fState_S8$D_OUT[65:55] :
	       _theResult___fst_exp__h46437 ;
  assign IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1261 =
	     (fpu_fState_S8$D_OUT[67] &&
	      IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1212 ==
	      11'd0 &&
	      ((fpu_fState_S8$D_OUT[65:55] == 11'd2047) ?
		 fpu_fState_S8$D_OUT[54:3] :
		 _theResult___fst_sfd__h46438) ==
	      52'd0 &&
	      !fpu_fState_S8_first__161_BITS_75_TO_71_236_OR__ETC___d1244[0] &&
	      fpu_fState_S8$D_OUT[0]) ?
	       fpu_fState_S8$D_OUT[70:68] == 3'd3 :
	       ((fpu_fState_S8$D_OUT[65:55] == 11'd2047) ?
		  fpu_fState_S8$D_OUT[66] :
		  CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14) ;
  assign IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1282 =
	     { IF_fpu_fState_S8_first__161_BIT_67_164_AND_IF__ETC___d1261,
	       (fpu_fState_S8$D_OUT[65:55] == 11'd2047) ?
		 fpu_fState_S8$D_OUT[65:3] :
		 CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19,
	       fpu_fState_S8_first__161_BITS_75_TO_71_236_OR__ETC___d1244 } ;
  assign IF_sfdin4758_BIT_53_THEN_2_ELSE_0__q5 =
	     sfdin__h34758[53] ? 2'd2 : 2'd0 ;
  assign IF_sfdin5184_BIT_4_THEN_2_ELSE_0__q10 =
	     sfdin__h45184[4] ? 2'd2 : 2'd0 ;
  assign NOT_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu__ETC___d147 =
	     (x__h327 != 11'd2047 || !_theResult___fst_sfd__h396[51]) &&
	     (fpu_fOperand_S0$D_OUT[129:119] != 11'd2047 ||
	      !fpu_fOperand_S0$D_OUT[118]) &&
	     (fpu_fOperand_S0$D_OUT[65:55] != 11'd2047 ||
	      !fpu_fOperand_S0$D_OUT[54]) &&
	     (fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d127 ||
	      IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_fOpe_ETC___d128 &&
	      !fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56) ;
  assign NOT_fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_ETC___d124 =
	     (fpu_fOperand_S0$D_OUT[129:119] != 11'd2047 ||
	      fpu_fOperand_S0$D_OUT[118:67] != 52'd0 ||
	      fpu_fOperand_S0$D_OUT[65:55] != 11'd0 ||
	      fpu_fOperand_S0$D_OUT[54:3] != 52'd0) &&
	     (fpu_fOperand_S0$D_OUT[129:119] != 11'd0 ||
	      fpu_fOperand_S0$D_OUT[118:67] != 52'd0 ||
	      fpu_fOperand_S0$D_OUT[65:55] != 11'd2047 ||
	      fpu_fOperand_S0$D_OUT[54:3] != 52'd0) &&
	     (x__h327 != 11'd2047 || _theResult___fst_sfd__h396 != 52'd0 ||
	      (fpu_fOperand_S0$D_OUT[129:119] != 11'd2047 ||
	       fpu_fOperand_S0$D_OUT[118:67] != 52'd0) &&
	      (fpu_fOperand_S0$D_OUT[65:55] != 11'd2047 ||
	       fpu_fOperand_S0$D_OUT[54:3] != 52'd0) ||
	      fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56) &&
	     IF_IF_fpu_fOperand_S0_first_BIT_195_THEN_fpu_f_ETC___d123 ;
  assign NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55 =
	     fpu_fOperand_S0$D_OUT[130] != fpu_fOperand_S0$D_OUT[66] ;
  assign NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d711 =
	     !fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 ||
	     (fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ?
		fpu_fState_S3$D_OUT[84] :
		fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702[2]) ;
  assign NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d724 =
	     { NOT_fpu_fState_S3_first__96_BITS_12_TO_0_02_SL_ETC___d711,
	       fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 ?
		 IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d717 :
		 fpu_fState_S3$D_OUT[83],
	       !fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 ||
	       IF_fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_ETC___d722 } ;
  assign NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 =
	     !fpu_fState_S4$D_OUT[130] ||
	     (IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 ^
	      13'h1000) >
	     (IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 ^
	      13'h1000) ||
	     IF_fpu_fState_S4_first__48_BITS_64_TO_54_60_EQ_ETC___d764 ==
	     IF_fpu_fState_S4_first__48_BITS_128_TO_118_65__ETC___d769 &&
	     sfdBC__h35393 > sfdA__h35392 ;
  assign _0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_first__ETC___d664 =
	     ({ 5'd0,
		IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661 } ^
	      12'h800) <=
	     (IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d663 ^
	      12'h800) ;
  assign _0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT_128_ETC___d1105 =
	     ({ 6'd0,
		IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102 } ^
	      12'h800) <=
	     (IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d1104 ^
	      12'h800) ;
  assign _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208 =
	     13'd7170 - fpu_fState_S3$D_OUT[12:0] ;
  assign _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d209 =
	     (_7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208 ^
	      13'h1000) <=
	     13'd4096 ;
  assign _theResult___exp__h46359 =
	     sfd__h45855[53] ?
	       ((fpu_fState_S8$D_OUT[65:55] == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h46444) :
	       IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1187 ;
  assign _theResult___fst__h20642 =
	     { fpu_fProd_S3_first__10_SRL_IF_7170_MINUS_fpu_f_ETC___d213[105:1],
	       fpu_fProd_S3_first__10_SRL_IF_7170_MINUS_fpu_f_ETC___d213[0] |
	       sfdlsb__h20640 } ;
  assign _theResult___fst_exp__h34764 =
	     sfdBC__h19477[105] ?
	       _theResult___fst_exp__h34786 :
	       _theResult___fst_exp__h34849 ;
  assign _theResult___fst_exp__h34767 =
	     (sfdBC__h19477[105] &&
	      IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 ==
	      12'd1023) ?
	       11'd2046 :
	       _theResult___fst_exp__h34764 ;
  assign _theResult___fst_exp__h34786 =
	     (din_exp__h34681 == 11'd0) ? 11'd2 : din_exp__h34681 + 11'd1 ;
  assign _theResult___fst_exp__h34801 =
	     (din_exp__h34681 == 11'd0) ? 11'd1 : din_exp__h34681 ;
  assign _theResult___fst_exp__h34840 =
	     din_exp__h34681 -
	     { 4'd0,
	       IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661 } ;
  assign _theResult___fst_exp__h34846 =
	     (!sfdBC__h19477[105] && !sfdBC__h19477[104] &&
	      !sfdBC__h19477[103] &&
	      !sfdBC__h19477[102] &&
	      !sfdBC__h19477[101] &&
	      !sfdBC__h19477[100] &&
	      !sfdBC__h19477[99] &&
	      !sfdBC__h19477[98] &&
	      !sfdBC__h19477[97] &&
	      !sfdBC__h19477[96] &&
	      !sfdBC__h19477[95] &&
	      !sfdBC__h19477[94] &&
	      !sfdBC__h19477[93] &&
	      !sfdBC__h19477[92] &&
	      !sfdBC__h19477[91] &&
	      !sfdBC__h19477[90] &&
	      !sfdBC__h19477[89] &&
	      !sfdBC__h19477[88] &&
	      !sfdBC__h19477[87] &&
	      !sfdBC__h19477[86] &&
	      !sfdBC__h19477[85] &&
	      !sfdBC__h19477[84] &&
	      !sfdBC__h19477[83] &&
	      !sfdBC__h19477[82] &&
	      !sfdBC__h19477[81] &&
	      !sfdBC__h19477[80] &&
	      !sfdBC__h19477[79] &&
	      !sfdBC__h19477[78] &&
	      !sfdBC__h19477[77] &&
	      !sfdBC__h19477[76] &&
	      !sfdBC__h19477[75] &&
	      !sfdBC__h19477[74] &&
	      !sfdBC__h19477[73] &&
	      !sfdBC__h19477[72] &&
	      !sfdBC__h19477[71] &&
	      !sfdBC__h19477[70] &&
	      !sfdBC__h19477[69] &&
	      !sfdBC__h19477[68] &&
	      !sfdBC__h19477[67] &&
	      !sfdBC__h19477[66] &&
	      !sfdBC__h19477[65] &&
	      !sfdBC__h19477[64] &&
	      !sfdBC__h19477[63] &&
	      !sfdBC__h19477[62] &&
	      !sfdBC__h19477[61] &&
	      !sfdBC__h19477[60] &&
	      !sfdBC__h19477[59] &&
	      !sfdBC__h19477[58] &&
	      !sfdBC__h19477[57] &&
	      !sfdBC__h19477[56] &&
	      !sfdBC__h19477[55] &&
	      !sfdBC__h19477[54] &&
	      !sfdBC__h19477[53] &&
	      !sfdBC__h19477[52] &&
	      !sfdBC__h19477[51] &&
	      !sfdBC__h19477[50] &&
	      !sfdBC__h19477[49] &&
	      !sfdBC__h19477[48] &&
	      !sfdBC__h19477[47] &&
	      !sfdBC__h19477[46] &&
	      !sfdBC__h19477[45] &&
	      !sfdBC__h19477[44] &&
	      !sfdBC__h19477[43] &&
	      !sfdBC__h19477[42] &&
	      !sfdBC__h19477[41] &&
	      !sfdBC__h19477[40] &&
	      !sfdBC__h19477[39] &&
	      !sfdBC__h19477[38] &&
	      !sfdBC__h19477[37] &&
	      !sfdBC__h19477[36] &&
	      !sfdBC__h19477[35] &&
	      !sfdBC__h19477[34] &&
	      !sfdBC__h19477[33] &&
	      !sfdBC__h19477[32] &&
	      !sfdBC__h19477[31] &&
	      !sfdBC__h19477[30] &&
	      !sfdBC__h19477[29] &&
	      !sfdBC__h19477[28] &&
	      !sfdBC__h19477[27] &&
	      !sfdBC__h19477[26] &&
	      !sfdBC__h19477[25] &&
	      !sfdBC__h19477[24] &&
	      !sfdBC__h19477[23] &&
	      !sfdBC__h19477[22] &&
	      !sfdBC__h19477[21] &&
	      !sfdBC__h19477[20] &&
	      !sfdBC__h19477[19] &&
	      !sfdBC__h19477[18] &&
	      !sfdBC__h19477[17] &&
	      !sfdBC__h19477[16] &&
	      !sfdBC__h19477[15] &&
	      !sfdBC__h19477[14] &&
	      !sfdBC__h19477[13] &&
	      !sfdBC__h19477[12] &&
	      !sfdBC__h19477[11] &&
	      !sfdBC__h19477[10] &&
	      !sfdBC__h19477[9] &&
	      !sfdBC__h19477[8] &&
	      !sfdBC__h19477[7] &&
	      !sfdBC__h19477[6] &&
	      !sfdBC__h19477[5] &&
	      !sfdBC__h19477[4] &&
	      !sfdBC__h19477[3] &&
	      !sfdBC__h19477[2] &&
	      !sfdBC__h19477[1] &&
	      !sfdBC__h19477[0] ||
	      !_0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_first__ETC___d664) ?
	       11'd0 :
	       _theResult___fst_exp__h34840 ;
  assign _theResult___fst_exp__h34849 =
	     (!sfdBC__h19477[105] && sfdBC__h19477[104]) ?
	       _theResult___fst_exp__h34801 :
	       _theResult___fst_exp__h34846 ;
  assign _theResult___fst_exp__h45190 =
	     sfd__h36934[56] ?
	       _theResult___fst_exp__h45212 :
	       _theResult___fst_exp__h45275 ;
  assign _theResult___fst_exp__h45193 =
	     (sfd__h36934[56] &&
	      IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 ==
	      12'd1023) ?
	       11'd2046 :
	       _theResult___fst_exp__h45190 ;
  assign _theResult___fst_exp__h45212 =
	     (value__h45122[10:0] == 11'd0) ?
	       11'd2 :
	       value__h45122[10:0] + 11'd1 ;
  assign _theResult___fst_exp__h45227 =
	     (value__h45122[10:0] == 11'd0) ? 11'd1 : value__h45122[10:0] ;
  assign _theResult___fst_exp__h45266 =
	     value__h45122[10:0] -
	     { 5'd0,
	       IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102 } ;
  assign _theResult___fst_exp__h45272 =
	     (!sfd__h36934[56] && !sfd__h36934[55] && !sfd__h36934[54] &&
	      !sfd__h36934[53] &&
	      !sfd__h36934[52] &&
	      !sfd__h36934[51] &&
	      !sfd__h36934[50] &&
	      !sfd__h36934[49] &&
	      !sfd__h36934[48] &&
	      !sfd__h36934[47] &&
	      !sfd__h36934[46] &&
	      !sfd__h36934[45] &&
	      !sfd__h36934[44] &&
	      !sfd__h36934[43] &&
	      !sfd__h36934[42] &&
	      !sfd__h36934[41] &&
	      !sfd__h36934[40] &&
	      !sfd__h36934[39] &&
	      !sfd__h36934[38] &&
	      !sfd__h36934[37] &&
	      !sfd__h36934[36] &&
	      !sfd__h36934[35] &&
	      !sfd__h36934[34] &&
	      !sfd__h36934[33] &&
	      !sfd__h36934[32] &&
	      !sfd__h36934[31] &&
	      !sfd__h36934[30] &&
	      !sfd__h36934[29] &&
	      !sfd__h36934[28] &&
	      !sfd__h36934[27] &&
	      !sfd__h36934[26] &&
	      !sfd__h36934[25] &&
	      !sfd__h36934[24] &&
	      !sfd__h36934[23] &&
	      !sfd__h36934[22] &&
	      !sfd__h36934[21] &&
	      !sfd__h36934[20] &&
	      !sfd__h36934[19] &&
	      !sfd__h36934[18] &&
	      !sfd__h36934[17] &&
	      !sfd__h36934[16] &&
	      !sfd__h36934[15] &&
	      !sfd__h36934[14] &&
	      !sfd__h36934[13] &&
	      !sfd__h36934[12] &&
	      !sfd__h36934[11] &&
	      !sfd__h36934[10] &&
	      !sfd__h36934[9] &&
	      !sfd__h36934[8] &&
	      !sfd__h36934[7] &&
	      !sfd__h36934[6] &&
	      !sfd__h36934[5] &&
	      !sfd__h36934[4] &&
	      !sfd__h36934[3] &&
	      !sfd__h36934[2] &&
	      !sfd__h36934[1] &&
	      !sfd__h36934[0] ||
	      !_0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT_128_ETC___d1105) ?
	       11'd0 :
	       _theResult___fst_exp__h45266 ;
  assign _theResult___fst_exp__h45275 =
	     (!sfd__h36934[56] && sfd__h36934[55]) ?
	       _theResult___fst_exp__h45227 :
	       _theResult___fst_exp__h45272 ;
  assign _theResult___fst_sfd__h396 =
	     fpu_fOperand_S0$D_OUT[195] ?
	       fpu_fOperand_S0$D_OUT[182:131] :
	       52'd0 ;
  assign _theResult___sfd__h46360 =
	     sfd__h45855[53] ?
	       ((fpu_fState_S8$D_OUT[65:55] == 11'd2046) ?
		  52'd0 :
		  sfd__h45855[52:1]) :
	       sfd__h45855[51:0] ;
  assign _theResult___snd__h34781 = { sfdBC__h19477[104:0], 1'd0 } ;
  assign _theResult___snd__h34795 =
	     (!sfdBC__h19477[105] && sfdBC__h19477[104]) ?
	       _theResult___snd__h34797 :
	       _theResult___snd__h34809 ;
  assign _theResult___snd__h34797 = { sfdBC__h19477[103:0], 2'd0 } ;
  assign _theResult___snd__h34809 =
	     (!sfdBC__h19477[105] && !sfdBC__h19477[104] &&
	      !sfdBC__h19477[103] &&
	      !sfdBC__h19477[102] &&
	      !sfdBC__h19477[101] &&
	      !sfdBC__h19477[100] &&
	      !sfdBC__h19477[99] &&
	      !sfdBC__h19477[98] &&
	      !sfdBC__h19477[97] &&
	      !sfdBC__h19477[96] &&
	      !sfdBC__h19477[95] &&
	      !sfdBC__h19477[94] &&
	      !sfdBC__h19477[93] &&
	      !sfdBC__h19477[92] &&
	      !sfdBC__h19477[91] &&
	      !sfdBC__h19477[90] &&
	      !sfdBC__h19477[89] &&
	      !sfdBC__h19477[88] &&
	      !sfdBC__h19477[87] &&
	      !sfdBC__h19477[86] &&
	      !sfdBC__h19477[85] &&
	      !sfdBC__h19477[84] &&
	      !sfdBC__h19477[83] &&
	      !sfdBC__h19477[82] &&
	      !sfdBC__h19477[81] &&
	      !sfdBC__h19477[80] &&
	      !sfdBC__h19477[79] &&
	      !sfdBC__h19477[78] &&
	      !sfdBC__h19477[77] &&
	      !sfdBC__h19477[76] &&
	      !sfdBC__h19477[75] &&
	      !sfdBC__h19477[74] &&
	      !sfdBC__h19477[73] &&
	      !sfdBC__h19477[72] &&
	      !sfdBC__h19477[71] &&
	      !sfdBC__h19477[70] &&
	      !sfdBC__h19477[69] &&
	      !sfdBC__h19477[68] &&
	      !sfdBC__h19477[67] &&
	      !sfdBC__h19477[66] &&
	      !sfdBC__h19477[65] &&
	      !sfdBC__h19477[64] &&
	      !sfdBC__h19477[63] &&
	      !sfdBC__h19477[62] &&
	      !sfdBC__h19477[61] &&
	      !sfdBC__h19477[60] &&
	      !sfdBC__h19477[59] &&
	      !sfdBC__h19477[58] &&
	      !sfdBC__h19477[57] &&
	      !sfdBC__h19477[56] &&
	      !sfdBC__h19477[55] &&
	      !sfdBC__h19477[54] &&
	      !sfdBC__h19477[53] &&
	      !sfdBC__h19477[52] &&
	      !sfdBC__h19477[51] &&
	      !sfdBC__h19477[50] &&
	      !sfdBC__h19477[49] &&
	      !sfdBC__h19477[48] &&
	      !sfdBC__h19477[47] &&
	      !sfdBC__h19477[46] &&
	      !sfdBC__h19477[45] &&
	      !sfdBC__h19477[44] &&
	      !sfdBC__h19477[43] &&
	      !sfdBC__h19477[42] &&
	      !sfdBC__h19477[41] &&
	      !sfdBC__h19477[40] &&
	      !sfdBC__h19477[39] &&
	      !sfdBC__h19477[38] &&
	      !sfdBC__h19477[37] &&
	      !sfdBC__h19477[36] &&
	      !sfdBC__h19477[35] &&
	      !sfdBC__h19477[34] &&
	      !sfdBC__h19477[33] &&
	      !sfdBC__h19477[32] &&
	      !sfdBC__h19477[31] &&
	      !sfdBC__h19477[30] &&
	      !sfdBC__h19477[29] &&
	      !sfdBC__h19477[28] &&
	      !sfdBC__h19477[27] &&
	      !sfdBC__h19477[26] &&
	      !sfdBC__h19477[25] &&
	      !sfdBC__h19477[24] &&
	      !sfdBC__h19477[23] &&
	      !sfdBC__h19477[22] &&
	      !sfdBC__h19477[21] &&
	      !sfdBC__h19477[20] &&
	      !sfdBC__h19477[19] &&
	      !sfdBC__h19477[18] &&
	      !sfdBC__h19477[17] &&
	      !sfdBC__h19477[16] &&
	      !sfdBC__h19477[15] &&
	      !sfdBC__h19477[14] &&
	      !sfdBC__h19477[13] &&
	      !sfdBC__h19477[12] &&
	      !sfdBC__h19477[11] &&
	      !sfdBC__h19477[10] &&
	      !sfdBC__h19477[9] &&
	      !sfdBC__h19477[8] &&
	      !sfdBC__h19477[7] &&
	      !sfdBC__h19477[6] &&
	      !sfdBC__h19477[5] &&
	      !sfdBC__h19477[4] &&
	      !sfdBC__h19477[3] &&
	      !sfdBC__h19477[2] &&
	      !sfdBC__h19477[1] &&
	      !sfdBC__h19477[0]) ?
	       sfdBC__h19477 :
	       _theResult___snd__h34815 ;
  assign _theResult___snd__h34815 =
	     { IF_0_CONCAT_IF_IF_7170_MINUS_fpu_fState_S3_fir_ETC__q4[103:0],
	       2'd0 } ;
  assign _theResult___snd__h34833 =
	     sfdBC__h19477 <<
	     IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d663 ;
  assign _theResult___snd__h34838 =
	     sfdBC__h19477 <<
	     IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d661 ;
  assign _theResult___snd__h45207 = { sfd__h36934[55:0], 1'd0 } ;
  assign _theResult___snd__h45221 =
	     (!sfd__h36934[56] && sfd__h36934[55]) ?
	       _theResult___snd__h45223 :
	       _theResult___snd__h45235 ;
  assign _theResult___snd__h45223 = { sfd__h36934[54:0], 2'd0 } ;
  assign _theResult___snd__h45235 =
	     (!sfd__h36934[56] && !sfd__h36934[55] && !sfd__h36934[54] &&
	      !sfd__h36934[53] &&
	      !sfd__h36934[52] &&
	      !sfd__h36934[51] &&
	      !sfd__h36934[50] &&
	      !sfd__h36934[49] &&
	      !sfd__h36934[48] &&
	      !sfd__h36934[47] &&
	      !sfd__h36934[46] &&
	      !sfd__h36934[45] &&
	      !sfd__h36934[44] &&
	      !sfd__h36934[43] &&
	      !sfd__h36934[42] &&
	      !sfd__h36934[41] &&
	      !sfd__h36934[40] &&
	      !sfd__h36934[39] &&
	      !sfd__h36934[38] &&
	      !sfd__h36934[37] &&
	      !sfd__h36934[36] &&
	      !sfd__h36934[35] &&
	      !sfd__h36934[34] &&
	      !sfd__h36934[33] &&
	      !sfd__h36934[32] &&
	      !sfd__h36934[31] &&
	      !sfd__h36934[30] &&
	      !sfd__h36934[29] &&
	      !sfd__h36934[28] &&
	      !sfd__h36934[27] &&
	      !sfd__h36934[26] &&
	      !sfd__h36934[25] &&
	      !sfd__h36934[24] &&
	      !sfd__h36934[23] &&
	      !sfd__h36934[22] &&
	      !sfd__h36934[21] &&
	      !sfd__h36934[20] &&
	      !sfd__h36934[19] &&
	      !sfd__h36934[18] &&
	      !sfd__h36934[17] &&
	      !sfd__h36934[16] &&
	      !sfd__h36934[15] &&
	      !sfd__h36934[14] &&
	      !sfd__h36934[13] &&
	      !sfd__h36934[12] &&
	      !sfd__h36934[11] &&
	      !sfd__h36934[10] &&
	      !sfd__h36934[9] &&
	      !sfd__h36934[8] &&
	      !sfd__h36934[7] &&
	      !sfd__h36934[6] &&
	      !sfd__h36934[5] &&
	      !sfd__h36934[4] &&
	      !sfd__h36934[3] &&
	      !sfd__h36934[2] &&
	      !sfd__h36934[1] &&
	      !sfd__h36934[0]) ?
	       sfd__h36934 :
	       _theResult___snd__h45241 ;
  assign _theResult___snd__h45241 =
	     { IF_0_CONCAT_IF_IF_fpu_fState_S7_first__52_BIT__ETC__q9[54:0],
	       2'd0 } ;
  assign _theResult___snd__h45259 =
	     sfd__h36934 <<
	     IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d1104 ;
  assign _theResult___snd__h45264 =
	     sfd__h36934 <<
	     IF_IF_fpu_fState_S7_first__52_BIT_128_58_THEN__ETC___d1102 ;
  assign _theResult___snd_fst__h34866 =
	     { IF_sfdin4758_BIT_53_THEN_2_ELSE_0__q5[1],
	       { sfdin__h34758[52:0], 52'd0 } != 105'd0 } ;
  assign _theResult___snd_fst__h45292 =
	     { IF_sfdin5184_BIT_4_THEN_2_ELSE_0__q10[1],
	       { sfdin__h45184[3:0], 52'd0 } != 56'd0 } ;
  assign _theResult___snd_snd__h35186 =
	     (fpu_fProd_S3$D_OUT == 106'd0) ? 2'd0 : 2'd1 ;
  assign _theResult___snd_snd_snd__h35184 =
	     fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 ?
	       _theResult___snd_snd__h35186 :
	       guardBC__h19481 ;
  assign din_exp4681_MINUS_1023__q3 = din_exp__h34681 - 11'd1023 ;
  assign din_exp__h34681 =
	     _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d209 ?
	       value__h34698[10:0] :
	       11'd0 ;
  assign din_inc___2_exp__h46444 = fpu_fState_S8$D_OUT[65:55] + 11'd1 ;
  assign fpu_fOperand_S0D_OUT_BITS_129_TO_119_MINUS_1023__q15 =
	     fpu_fOperand_S0$D_OUT[129:119] - 11'd1023 ;
  assign fpu_fOperand_S0D_OUT_BITS_65_TO_55_MINUS_1023__q16 =
	     fpu_fOperand_S0$D_OUT[65:55] - 11'd1023 ;
  assign fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d127 =
	     fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
	     fpu_fOperand_S0$D_OUT[118:67] == 52'd0 &&
	     fpu_fOperand_S0$D_OUT[65:55] == 11'd0 &&
	     fpu_fOperand_S0$D_OUT[54:3] == 52'd0 ||
	     fpu_fOperand_S0$D_OUT[129:119] == 11'd0 &&
	     fpu_fOperand_S0$D_OUT[118:67] == 52'd0 &&
	     fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
	     fpu_fOperand_S0$D_OUT[54:3] == 52'd0 ;
  assign fpu_fOperand_S0_first_BITS_129_TO_119_7_EQ_204_ETC___d58 =
	     fpu_fOperand_S0$D_OUT[129:119] == 11'd2047 &&
	     fpu_fOperand_S0$D_OUT[118:67] == 52'd0 ||
	     fpu_fOperand_S0$D_OUT[65:55] == 11'd2047 &&
	     fpu_fOperand_S0$D_OUT[54:3] == 52'd0 ||
	     x__h327 == 11'd0 && _theResult___fst_sfd__h396 == 52'd0 &&
	     (fpu_fOperand_S0$D_OUT[129:119] == 11'd0 &&
	      fpu_fOperand_S0$D_OUT[118:67] == 52'd0 ||
	      fpu_fOperand_S0$D_OUT[65:55] == 11'd0 &&
	      fpu_fOperand_S0$D_OUT[54:3] == 52'd0) &&
	     fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56 ;
  assign fpu_fOperand_S0_first_BIT_195_AND_fpu_fOperand_ETC___d56 =
	     (fpu_fOperand_S0$D_OUT[195] && fpu_fOperand_S0$D_OUT[194]) ==
	     NOT_fpu_fOperand_S0_first_BIT_130_2_EQ_fpu_fOp_ETC___d55 ;
  assign fpu_fProd_S3_first__10_SRL_IF_7170_MINUS_fpu_f_ETC___d213 =
	     fpu_fProd_S3$D_OUT >>
	     _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208 ;
  assign fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 =
	     (fpu_fState_S3$D_OUT[12:0] ^ 13'h1000) <= 13'd5119 ;
  assign fpu_fState_S3_first__96_BITS_12_TO_0_02_SLT_7116___d205 =
	     (fpu_fState_S3$D_OUT[12:0] ^ 13'h1000) < 13'd3020 ;
  assign fpu_fState_S3_first__96_BITS_86_TO_82_01_OR_0__ETC___d702 =
	     fpu_fState_S3$D_OUT[86:82] |
	     { 2'd0,
	       sfdBC__h19477[105] &&
	       IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 ==
	       12'd1023,
	       _theResult___fst_exp__h34767 == 11'd0 &&
	       guardBC__h19481 != 2'd0,
	       sfdBC__h19477[105] &&
	       IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 ==
	       12'd1023 } ;
  assign fpu_fState_S4D_OUT_BITS_128_TO_118_MINUS_1023__q7 =
	     fpu_fState_S4$D_OUT[128:118] - 11'd1023 ;
  assign fpu_fState_S4D_OUT_BITS_64_TO_54_MINUS_1023__q6 =
	     fpu_fState_S4$D_OUT[64:54] - 11'd1023 ;
  assign fpu_fState_S5_first__02_BITS_56_TO_0_11_SRL_IF_ETC___d816 =
	     fpu_fState_S5$D_OUT[56:0] >> fpu_fState_S5$D_OUT[126:114] ;
  assign fpu_fState_S7_first__52_BITS_137_TO_133_57_OR__ETC___d1143 =
	     fpu_fState_S7$D_OUT[137:133] |
	     { 2'd0,
	       sfd__h36934[56] &&
	       IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 ==
	       12'd1023,
	       _theResult___fst_exp__h45193 == 11'd0 && guard__h36938 != 2'd0,
	       sfd__h36934[56] &&
	       IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 ==
	       12'd1023 } ;
  assign fpu_fState_S8_first__161_BITS_75_TO_71_236_OR__ETC___d1244 =
	     fpu_fState_S8$D_OUT[75:71] |
	     { 2'd0,
	       IF_fpu_fState_S8_first__161_BITS_65_TO_55_165__ETC___d1212 ==
	       11'd2047 &&
	       ((fpu_fState_S8$D_OUT[65:55] == 11'd2047) ?
		  fpu_fState_S8$D_OUT[54:3] :
		  _theResult___fst_sfd__h46438) ==
	       52'd0,
	       1'd0,
	       fpu_fState_S8$D_OUT[65:55] != 11'd2047 &&
	       fpu_fState_S8$D_OUT[2:1] != 2'b0 } ;
  assign guardBC__h19481 =
	     (sfdBC__h19477[105] &&
	      IF_IF_7170_MINUS_fpu_fState_S3_first__96_BITS__ETC___d232 ==
	      12'd1023) ?
	       2'd3 :
	       _theResult___snd_fst__h34866 ;
  assign guard__h36182 = fpu_fState_S5$D_OUT[56:0] << x__h36286 ;
  assign guard__h36938 =
	     (sfd__h36934[56] &&
	      IF_fpu_fState_S7_first__52_BITS_126_TO_114_63__ETC___d869 ==
	      12'd1023) ?
	       2'd3 :
	       _theResult___snd_fst__h45292 ;
  assign out_exp__h46362 =
	     fpu_fState_S8$D_OUT[3] ?
	       _theResult___exp__h46359 :
	       fpu_fState_S8$D_OUT[65:55] ;
  assign out_sfd__h46363 =
	     fpu_fState_S8$D_OUT[3] ?
	       _theResult___sfd__h46360 :
	       fpu_fState_S8$D_OUT[54:3] ;
  assign result__h36187 =
	     { fpu_fState_S5_first__02_BITS_56_TO_0_11_SRL_IF_ETC___d816[56:1],
	       fpu_fState_S5_first__02_BITS_56_TO_0_11_SRL_IF_ETC___d816[0] |
	       guard__h36182 != 57'd0 } ;
  assign sfdA__h35392 =
	     { 1'b0,
	       fpu_fState_S4$D_OUT[128:118] != 11'd0,
	       fpu_fState_S4$D_OUT[117:66],
	       3'b0 } ;
  assign sfdBC__h19477 =
	     _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d209 ?
	       fpu_fProd_S3$D_OUT :
	       _theResult___fst__h20642 ;
  assign sfdBC__h35393 =
	     { 1'b0,
	       fpu_fState_S4$D_OUT[64:54] != 11'd0,
	       fpu_fState_S4$D_OUT[53:0],
	       1'b0 } ;
  assign sfd__h3208 = { 1'd1, _theResult___fst_sfd__h396[50:0] } ;
  assign sfd__h3211 = { 1'd1, fpu_fOperand_S0$D_OUT[117:67] } ;
  assign sfd__h3214 = { 1'd1, fpu_fOperand_S0$D_OUT[53:3] } ;
  assign sfd__h36934 =
	     fpu_fState_S7$D_OUT[128] ?
	       fpu_fState_S7$D_OUT[56:0] :
	       fpu_fState_S7$D_OUT[113:57] ;
  assign sfd__h45855 =
	     { 1'b0,
	       fpu_fState_S8$D_OUT[65:55] != 11'd0,
	       fpu_fState_S8$D_OUT[54:3] } +
	     54'd1 ;
  assign sfdin__h34758 =
	     sfdBC__h19477[105] ?
	       _theResult___snd__h34781 :
	       _theResult___snd__h34795 ;
  assign sfdin__h45184 =
	     sfd__h36934[56] ?
	       _theResult___snd__h45207 :
	       _theResult___snd__h45221 ;
  assign sfdlsb__h20640 = x__h20711 != 106'd0 ;
  assign value5122_BITS_10_TO_0_MINUS_1023__q8 =
	     value__h45122[10:0] - 11'd1023 ;
  assign value__h34698 = fpu_fState_S3$D_OUT[12:0] + 13'd1023 ;
  assign value__h45122 = fpu_fState_S7$D_OUT[126:114] + 13'd1023 ;
  assign x__h18058 =
	     { fpu_fOperand_S0$D_OUT[129:119] != 11'd0,
	       fpu_fOperand_S0$D_OUT[118:67] } ;
  assign x__h18070 =
	     { fpu_fOperand_S0$D_OUT[65:55] != 11'd0,
	       fpu_fOperand_S0$D_OUT[54:3] } ;
  assign x__h20711 = fpu_fProd_S3$D_OUT << x__h20744 ;
  assign x__h20744 =
	     13'd106 -
	     _7170_MINUS_fpu_fState_S3_first__96_BITS_12_TO__ETC___d208 ;
  assign x__h327 =
	     fpu_fOperand_S0$D_OUT[195] ?
	       fpu_fOperand_S0$D_OUT[193:183] :
	       11'd0 ;
  assign x__h35221 =
	     fpu_fState_S3_first__96_BITS_12_TO_0_02_SLE_1023___d203 ?
	       _theResult___snd_snd_snd__h35184 :
	       2'd3 ;
  assign x__h35755 =
	     { 1'b0,
	       NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ?
		 { fpu_fState_S4$D_OUT[64:54] != 11'd0,
		   fpu_fState_S4$D_OUT[53:0],
		   1'b0 } :
		 { fpu_fState_S4$D_OUT[128:118] != 11'd0,
		   fpu_fState_S4$D_OUT[117:66],
		   3'b0 } } ;
  assign x__h35759 =
	     { 1'b0,
	       NOT_fpu_fState_S4_first__48_BIT_130_54_59_OR_N_ETC___d785 ?
		 { fpu_fState_S4$D_OUT[128:118] != 11'd0,
		   fpu_fState_S4$D_OUT[117:66],
		   3'b0 } :
		 { fpu_fState_S4$D_OUT[64:54] != 11'd0,
		   fpu_fState_S4$D_OUT[53:0],
		   1'b0 } } ;
  assign x__h36174 =
	     fpu_fState_S5$D_OUT[215] ?
	       fpu_fState_S5$D_OUT[56:0] :
	       (((fpu_fState_S5$D_OUT[126:114] ^ 13'h1000) < 13'd4153) ?
		  result__h36187 :
		  ((fpu_fState_S5$D_OUT[56:0] == 57'd0) ?
		     fpu_fState_S5$D_OUT[56:0] :
		     57'd1)) ;
  assign x__h36286 = 13'd57 - fpu_fState_S5$D_OUT[126:114] ;
  assign x__h36686 = fpu_fState_S6$D_OUT[113:57] + fpu_fState_S6$D_OUT[56:0] ;
  assign x__h36695 = fpu_fState_S6$D_OUT[113:57] - fpu_fState_S6$D_OUT[56:0] ;
  assign x__h45575 = fpu_fState_S7$D_OUT[202] ? 2'd0 : guard__h36938 ;
  always@(fpu_fState_S8$D_OUT or out_sfd__h46363 or _theResult___sfd__h46360)
  begin
    case (fpu_fState_S8$D_OUT[2:1])
      2'b0, 2'b01:
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1 =
	      fpu_fState_S8$D_OUT[54:3];
      2'b10:
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1 =
	      out_sfd__h46363;
      2'b11:
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1 =
	      _theResult___sfd__h46360;
    endcase
  end
  always@(fpu_fState_S8$D_OUT or _theResult___sfd__h46360)
  begin
    case (fpu_fState_S8$D_OUT[2:1])
      2'b0:
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2 =
	      fpu_fState_S8$D_OUT[54:3];
      2'b01, 2'b10, 2'b11:
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2 =
	      _theResult___sfd__h46360;
    endcase
  end
  always@(fpu_fState_S8$D_OUT or
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1 or
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2 or
	  _theResult___sfd__h46360)
  begin
    case (fpu_fState_S8$D_OUT[70:68])
      3'd0:
	  _theResult___fst_sfd__h46438 =
	      CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q1;
      3'd1:
	  _theResult___fst_sfd__h46438 =
	      CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q2;
      3'd2:
	  _theResult___fst_sfd__h46438 =
	      (fpu_fState_S8$D_OUT[2:1] == 2'b0 || fpu_fState_S8$D_OUT[66]) ?
		fpu_fState_S8$D_OUT[54:3] :
		_theResult___sfd__h46360;
      3'd3:
	  _theResult___fst_sfd__h46438 =
	      (fpu_fState_S8$D_OUT[2:1] == 2'b0) ?
		fpu_fState_S8$D_OUT[54:3] :
		(fpu_fState_S8$D_OUT[66] ?
		   _theResult___sfd__h46360 :
		   fpu_fState_S8$D_OUT[54:3]);
      3'd4: _theResult___fst_sfd__h46438 = fpu_fState_S8$D_OUT[54:3];
      default: _theResult___fst_sfd__h46438 = 52'd0;
    endcase
  end
  always@(fpu_fState_S8$D_OUT or out_exp__h46362 or _theResult___exp__h46359)
  begin
    case (fpu_fState_S8$D_OUT[2:1])
      2'b0, 2'b01:
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11 =
	      fpu_fState_S8$D_OUT[65:55];
      2'b10:
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11 =
	      out_exp__h46362;
      2'b11:
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11 =
	      _theResult___exp__h46359;
    endcase
  end
  always@(fpu_fState_S8$D_OUT or _theResult___exp__h46359)
  begin
    case (fpu_fState_S8$D_OUT[2:1])
      2'b0:
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12 =
	      fpu_fState_S8$D_OUT[65:55];
      2'b01, 2'b10, 2'b11:
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12 =
	      _theResult___exp__h46359;
    endcase
  end
  always@(fpu_fState_S8$D_OUT or
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11 or
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12 or
	  _theResult___exp__h46359)
  begin
    case (fpu_fState_S8$D_OUT[70:68])
      3'd0:
	  _theResult___fst_exp__h46437 =
	      CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q11;
      3'd1:
	  _theResult___fst_exp__h46437 =
	      CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q12;
      3'd2:
	  _theResult___fst_exp__h46437 =
	      (fpu_fState_S8$D_OUT[2:1] == 2'b0 || fpu_fState_S8$D_OUT[66]) ?
		fpu_fState_S8$D_OUT[65:55] :
		_theResult___exp__h46359;
      3'd3:
	  _theResult___fst_exp__h46437 =
	      (fpu_fState_S8$D_OUT[2:1] == 2'b0) ?
		fpu_fState_S8$D_OUT[65:55] :
		(fpu_fState_S8$D_OUT[66] ?
		   _theResult___exp__h46359 :
		   fpu_fState_S8$D_OUT[65:55]);
      3'd4: _theResult___fst_exp__h46437 = fpu_fState_S8$D_OUT[65:55];
      default: _theResult___fst_exp__h46437 = 11'd0;
    endcase
  end
  always@(fpu_fState_S8$D_OUT)
  begin
    case (fpu_fState_S8$D_OUT[2:1])
      2'b0, 2'b01, 2'b10:
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13 =
	      fpu_fState_S8$D_OUT[66];
      2'd3:
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13 =
	      fpu_fState_S8$D_OUT[2:1] == 2'b11 && fpu_fState_S8$D_OUT[66];
    endcase
  end
  always@(fpu_fState_S8$D_OUT or
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13)
  begin
    case (fpu_fState_S8$D_OUT[70:68])
      3'd0:
	  CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14 =
	      CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q13;
      3'd1:
	  CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14 =
	      (fpu_fState_S8$D_OUT[2:1] == 2'b0) ?
		fpu_fState_S8$D_OUT[66] :
		(fpu_fState_S8$D_OUT[2:1] == 2'b01 ||
		 fpu_fState_S8$D_OUT[2:1] == 2'b10 ||
		 fpu_fState_S8$D_OUT[2:1] == 2'b11) &&
		fpu_fState_S8$D_OUT[66];
      3'd2, 3'd3:
	  CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14 =
	      fpu_fState_S8$D_OUT[66];
      default: CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q14 =
		   fpu_fState_S8$D_OUT[70:68] == 3'd4 &&
		   fpu_fState_S8$D_OUT[66];
    endcase
  end
  always@(fpu_fState_S8$D_OUT or
	  IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266)
  begin
    case (fpu_fState_S8$D_OUT[2:1])
      2'b0, 2'b01:
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17 =
	      fpu_fState_S8$D_OUT[65:3];
      2'b10:
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17 =
	      fpu_fState_S8$D_OUT[3] ?
		IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266 :
		fpu_fState_S8$D_OUT[65:3];
      2'b11:
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17 =
	      IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266;
    endcase
  end
  always@(fpu_fState_S8$D_OUT or
	  IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266)
  begin
    case (fpu_fState_S8$D_OUT[2:1])
      2'b0:
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18 =
	      fpu_fState_S8$D_OUT[65:3];
      2'b01, 2'b10, 2'b11:
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18 =
	      IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266;
    endcase
  end
  always@(fpu_fState_S8$D_OUT or
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17 or
	  CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18 or
	  IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266)
  begin
    case (fpu_fState_S8$D_OUT[70:68])
      3'd0:
	  CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 =
	      CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q17;
      3'd1:
	  CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 =
	      CASE_fpu_fState_S8D_OUT_BITS_2_TO_1_0b0_fpu_f_ETC__q18;
      3'd2:
	  CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 =
	      (fpu_fState_S8$D_OUT[2:1] == 2'b0 || fpu_fState_S8$D_OUT[66]) ?
		fpu_fState_S8$D_OUT[65:3] :
		IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266;
      3'd3:
	  CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 =
	      (fpu_fState_S8$D_OUT[2:1] == 2'b0) ?
		fpu_fState_S8$D_OUT[65:3] :
		(fpu_fState_S8$D_OUT[66] ?
		   IF_0b0_CONCAT_NOT_fpu_fState_S8_first__161_BIT_ETC___d1266 :
		   fpu_fState_S8$D_OUT[65:3]);
      3'd4:
	  CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 =
	      fpu_fState_S8$D_OUT[65:3];
      default: CASE_fpu_fState_S8D_OUT_BITS_70_TO_68_0_CASE__ETC__q19 = 63'd0;
    endcase
  end
endmodule  // mkDoubleFMA

