//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name                         I/O  size props
// to_parent_rsToP_notEmpty       O     1
// RDY_to_parent_rsToP_notEmpty   O     1 const
// RDY_to_parent_rsToP_deq        O     1
// to_parent_rsToP_first          O   579
// RDY_to_parent_rsToP_first      O     1
// to_parent_rqToP_notEmpty       O     1
// RDY_to_parent_rqToP_notEmpty   O     1 const
// RDY_to_parent_rqToP_deq        O     1
// to_parent_rqToP_first          O    72
// RDY_to_parent_rqToP_first      O     1
// to_parent_fromP_notFull        O     1
// RDY_to_parent_fromP_notFull    O     1 const
// RDY_to_parent_fromP_enq        O     1
// RDY_to_proc_req_put            O     1
// to_proc_resp_get               O    66
// RDY_to_proc_resp_get           O     1
// cRqStuck_get                   O    68 const
// RDY_cRqStuck_get               O     1 const
// pRqStuck_get                   O    68 const
// RDY_pRqStuck_get               O     1 const
// RDY_flush                      O     1 const
// flush_done                     O     1 const
// RDY_flush_done                 O     1 const
// RDY_setPerfStatus              O     1 const
// getPerfData                    O    64 const
// RDY_getPerfData                O     1 const
// CLK                            I     1 clock
// RST_N                          I     1 reset
// to_parent_fromP_enq_x          I   583
// to_proc_req_put                I    64
// setPerfStatus_stats            I     1 unused
// getPerfData_t                  I     2 unused
// EN_to_parent_rsToP_deq         I     1
// EN_to_parent_rqToP_deq         I     1
// EN_to_parent_fromP_enq         I     1
// EN_to_proc_req_put             I     1
// EN_flush                       I     1 unused
// EN_setPerfStatus               I     1 unused
// EN_to_proc_resp_get            I     1
// EN_cRqStuck_get                I     1 unused
// EN_pRqStuck_get                I     1 unused
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkIBankWrapper(CLK,
		      RST_N,

		      to_parent_rsToP_notEmpty,
		      RDY_to_parent_rsToP_notEmpty,

		      EN_to_parent_rsToP_deq,
		      RDY_to_parent_rsToP_deq,

		      to_parent_rsToP_first,
		      RDY_to_parent_rsToP_first,

		      to_parent_rqToP_notEmpty,
		      RDY_to_parent_rqToP_notEmpty,

		      EN_to_parent_rqToP_deq,
		      RDY_to_parent_rqToP_deq,

		      to_parent_rqToP_first,
		      RDY_to_parent_rqToP_first,

		      to_parent_fromP_notFull,
		      RDY_to_parent_fromP_notFull,

		      to_parent_fromP_enq_x,
		      EN_to_parent_fromP_enq,
		      RDY_to_parent_fromP_enq,

		      to_proc_req_put,
		      EN_to_proc_req_put,
		      RDY_to_proc_req_put,

		      EN_to_proc_resp_get,
		      to_proc_resp_get,
		      RDY_to_proc_resp_get,

		      EN_cRqStuck_get,
		      cRqStuck_get,
		      RDY_cRqStuck_get,

		      EN_pRqStuck_get,
		      pRqStuck_get,
		      RDY_pRqStuck_get,

		      EN_flush,
		      RDY_flush,

		      flush_done,
		      RDY_flush_done,

		      setPerfStatus_stats,
		      EN_setPerfStatus,
		      RDY_setPerfStatus,

		      getPerfData_t,
		      getPerfData,
		      RDY_getPerfData);
  input  CLK;
  input  RST_N;

  // value method to_parent_rsToP_notEmpty
  output to_parent_rsToP_notEmpty;
  output RDY_to_parent_rsToP_notEmpty;

  // action method to_parent_rsToP_deq
  input  EN_to_parent_rsToP_deq;
  output RDY_to_parent_rsToP_deq;

  // value method to_parent_rsToP_first
  output [578 : 0] to_parent_rsToP_first;
  output RDY_to_parent_rsToP_first;

  // value method to_parent_rqToP_notEmpty
  output to_parent_rqToP_notEmpty;
  output RDY_to_parent_rqToP_notEmpty;

  // action method to_parent_rqToP_deq
  input  EN_to_parent_rqToP_deq;
  output RDY_to_parent_rqToP_deq;

  // value method to_parent_rqToP_first
  output [71 : 0] to_parent_rqToP_first;
  output RDY_to_parent_rqToP_first;

  // value method to_parent_fromP_notFull
  output to_parent_fromP_notFull;
  output RDY_to_parent_fromP_notFull;

  // action method to_parent_fromP_enq
  input  [582 : 0] to_parent_fromP_enq_x;
  input  EN_to_parent_fromP_enq;
  output RDY_to_parent_fromP_enq;

  // action method to_proc_req_put
  input  [63 : 0] to_proc_req_put;
  input  EN_to_proc_req_put;
  output RDY_to_proc_req_put;

  // actionvalue method to_proc_resp_get
  input  EN_to_proc_resp_get;
  output [65 : 0] to_proc_resp_get;
  output RDY_to_proc_resp_get;

  // actionvalue method cRqStuck_get
  input  EN_cRqStuck_get;
  output [67 : 0] cRqStuck_get;
  output RDY_cRqStuck_get;

  // actionvalue method pRqStuck_get
  input  EN_pRqStuck_get;
  output [67 : 0] pRqStuck_get;
  output RDY_pRqStuck_get;

  // action method flush
  input  EN_flush;
  output RDY_flush;

  // value method flush_done
  output flush_done;
  output RDY_flush_done;

  // action method setPerfStatus
  input  setPerfStatus_stats;
  input  EN_setPerfStatus;
  output RDY_setPerfStatus;

  // value method getPerfData
  input  [1 : 0] getPerfData_t;
  output [63 : 0] getPerfData;
  output RDY_getPerfData;

  // signals for module outputs
  wire [578 : 0] to_parent_rsToP_first;
  wire [71 : 0] to_parent_rqToP_first;
  wire [67 : 0] cRqStuck_get, pRqStuck_get;
  wire [65 : 0] to_proc_resp_get;
  wire [63 : 0] getPerfData;
  wire RDY_cRqStuck_get,
       RDY_flush,
       RDY_flush_done,
       RDY_getPerfData,
       RDY_pRqStuck_get,
       RDY_setPerfStatus,
       RDY_to_parent_fromP_enq,
       RDY_to_parent_fromP_notFull,
       RDY_to_parent_rqToP_deq,
       RDY_to_parent_rqToP_first,
       RDY_to_parent_rqToP_notEmpty,
       RDY_to_parent_rsToP_deq,
       RDY_to_parent_rsToP_first,
       RDY_to_parent_rsToP_notEmpty,
       RDY_to_proc_req_put,
       RDY_to_proc_resp_get,
       flush_done,
       to_parent_fromP_notFull,
       to_parent_rqToP_notEmpty,
       to_parent_rsToP_notEmpty;

  // inlined wires
  wire [583 : 0] m_fromPQ_enqReq_lat_0$wget;
  wire [579 : 0] m_rsToPQ_enqReq_lat_0$wget;
  wire [72 : 0] m_rqToPQ_enqReq_lat_0$wget;
  wire m_fromPQ_deqReq_lat_0$whas, m_rsToPQ_enqReq_lat_0$whas;

  // register m_fromPQ_clearReq_rl
  reg m_fromPQ_clearReq_rl;
  wire m_fromPQ_clearReq_rl$D_IN, m_fromPQ_clearReq_rl$EN;

  // register m_fromPQ_data_0
  reg [582 : 0] m_fromPQ_data_0;
  wire [582 : 0] m_fromPQ_data_0$D_IN;
  wire m_fromPQ_data_0$EN;

  // register m_fromPQ_data_1
  reg [582 : 0] m_fromPQ_data_1;
  wire [582 : 0] m_fromPQ_data_1$D_IN;
  wire m_fromPQ_data_1$EN;

  // register m_fromPQ_deqP
  reg m_fromPQ_deqP;
  wire m_fromPQ_deqP$D_IN, m_fromPQ_deqP$EN;

  // register m_fromPQ_deqReq_rl
  reg m_fromPQ_deqReq_rl;
  wire m_fromPQ_deqReq_rl$D_IN, m_fromPQ_deqReq_rl$EN;

  // register m_fromPQ_empty
  reg m_fromPQ_empty;
  wire m_fromPQ_empty$D_IN, m_fromPQ_empty$EN;

  // register m_fromPQ_enqP
  reg m_fromPQ_enqP;
  wire m_fromPQ_enqP$D_IN, m_fromPQ_enqP$EN;

  // register m_fromPQ_enqReq_rl
  reg [583 : 0] m_fromPQ_enqReq_rl;
  wire [583 : 0] m_fromPQ_enqReq_rl$D_IN;
  wire m_fromPQ_enqReq_rl$EN;

  // register m_fromPQ_full
  reg m_fromPQ_full;
  wire m_fromPQ_full$D_IN, m_fromPQ_full$EN;

  // register m_rqFromCQ_data_0_rl
  reg [63 : 0] m_rqFromCQ_data_0_rl;
  wire [63 : 0] m_rqFromCQ_data_0_rl$D_IN;
  wire m_rqFromCQ_data_0_rl$EN;

  // register m_rqFromCQ_empty_rl
  reg m_rqFromCQ_empty_rl;
  wire m_rqFromCQ_empty_rl$D_IN, m_rqFromCQ_empty_rl$EN;

  // register m_rqFromCQ_full_rl
  reg m_rqFromCQ_full_rl;
  wire m_rqFromCQ_full_rl$D_IN, m_rqFromCQ_full_rl$EN;

  // register m_rqToPQ_clearReq_rl
  reg m_rqToPQ_clearReq_rl;
  wire m_rqToPQ_clearReq_rl$D_IN, m_rqToPQ_clearReq_rl$EN;

  // register m_rqToPQ_data_0
  reg [71 : 0] m_rqToPQ_data_0;
  wire [71 : 0] m_rqToPQ_data_0$D_IN;
  wire m_rqToPQ_data_0$EN;

  // register m_rqToPQ_data_1
  reg [71 : 0] m_rqToPQ_data_1;
  wire [71 : 0] m_rqToPQ_data_1$D_IN;
  wire m_rqToPQ_data_1$EN;

  // register m_rqToPQ_deqP
  reg m_rqToPQ_deqP;
  wire m_rqToPQ_deqP$D_IN, m_rqToPQ_deqP$EN;

  // register m_rqToPQ_deqReq_rl
  reg m_rqToPQ_deqReq_rl;
  wire m_rqToPQ_deqReq_rl$D_IN, m_rqToPQ_deqReq_rl$EN;

  // register m_rqToPQ_empty
  reg m_rqToPQ_empty;
  wire m_rqToPQ_empty$D_IN, m_rqToPQ_empty$EN;

  // register m_rqToPQ_enqP
  reg m_rqToPQ_enqP;
  wire m_rqToPQ_enqP$D_IN, m_rqToPQ_enqP$EN;

  // register m_rqToPQ_enqReq_rl
  reg [72 : 0] m_rqToPQ_enqReq_rl;
  wire [72 : 0] m_rqToPQ_enqReq_rl$D_IN;
  wire m_rqToPQ_enqReq_rl$EN;

  // register m_rqToPQ_full
  reg m_rqToPQ_full;
  wire m_rqToPQ_full$D_IN, m_rqToPQ_full$EN;

  // register m_rsToPQ_clearReq_rl
  reg m_rsToPQ_clearReq_rl;
  wire m_rsToPQ_clearReq_rl$D_IN, m_rsToPQ_clearReq_rl$EN;

  // register m_rsToPQ_data_0
  reg [578 : 0] m_rsToPQ_data_0;
  wire [578 : 0] m_rsToPQ_data_0$D_IN;
  wire m_rsToPQ_data_0$EN;

  // register m_rsToPQ_data_1
  reg [578 : 0] m_rsToPQ_data_1;
  wire [578 : 0] m_rsToPQ_data_1$D_IN;
  wire m_rsToPQ_data_1$EN;

  // register m_rsToPQ_deqP
  reg m_rsToPQ_deqP;
  wire m_rsToPQ_deqP$D_IN, m_rsToPQ_deqP$EN;

  // register m_rsToPQ_deqReq_rl
  reg m_rsToPQ_deqReq_rl;
  wire m_rsToPQ_deqReq_rl$D_IN, m_rsToPQ_deqReq_rl$EN;

  // register m_rsToPQ_empty
  reg m_rsToPQ_empty;
  wire m_rsToPQ_empty$D_IN, m_rsToPQ_empty$EN;

  // register m_rsToPQ_enqP
  reg m_rsToPQ_enqP;
  wire m_rsToPQ_enqP$D_IN, m_rsToPQ_enqP$EN;

  // register m_rsToPQ_enqReq_rl
  reg [579 : 0] m_rsToPQ_enqReq_rl;
  wire [579 : 0] m_rsToPQ_enqReq_rl$D_IN;
  wire m_rsToPQ_enqReq_rl$EN;

  // register m_rsToPQ_full
  reg m_rsToPQ_full;
  wire m_rsToPQ_full$D_IN, m_rsToPQ_full$EN;

  // ports of submodule m_cRqIndexQ
  wire [2 : 0] m_cRqIndexQ$D_IN, m_cRqIndexQ$D_OUT;
  wire m_cRqIndexQ$CLR,
       m_cRqIndexQ$DEQ,
       m_cRqIndexQ$EMPTY_N,
       m_cRqIndexQ$ENQ,
       m_cRqIndexQ$FULL_N;

  // ports of submodule m_cRqMshr
  wire [67 : 0] m_cRqMshr$stuck_get;
  wire [66 : 0] m_cRqMshr$sendRsToC_getResult;
  wire [65 : 0] m_cRqMshr$pipelineResp_setResult_r;
  wire [63 : 0] m_cRqMshr$getEmptyEntryInit_r,
		m_cRqMshr$pipelineResp_getRq,
		m_cRqMshr$pipelineResp_searchEndOfChain_addr,
		m_cRqMshr$sendRqToP_getRq,
		m_cRqMshr$sendRsToP_cRq_getRq;
  wire [55 : 0] m_cRqMshr$pipelineResp_setStateSlot_slot,
		m_cRqMshr$sendRqToP_getSlot,
		m_cRqMshr$sendRsToP_cRq_getSlot;
  wire [3 : 0] m_cRqMshr$pipelineResp_getSucc,
	       m_cRqMshr$pipelineResp_searchEndOfChain,
	       m_cRqMshr$pipelineResp_setSucc_succ;
  wire [2 : 0] m_cRqMshr$getEmptyEntryInit,
	       m_cRqMshr$pipelineResp_getRq_n,
	       m_cRqMshr$pipelineResp_getSlot_n,
	       m_cRqMshr$pipelineResp_getState_n,
	       m_cRqMshr$pipelineResp_getSucc_n,
	       m_cRqMshr$pipelineResp_setResult_n,
	       m_cRqMshr$pipelineResp_setStateSlot_n,
	       m_cRqMshr$pipelineResp_setStateSlot_state,
	       m_cRqMshr$pipelineResp_setSucc_n,
	       m_cRqMshr$sendRqToP_getRq_n,
	       m_cRqMshr$sendRqToP_getSlot_n,
	       m_cRqMshr$sendRsToC_getResult_n,
	       m_cRqMshr$sendRsToC_releaseEntry_n,
	       m_cRqMshr$sendRsToP_cRq_getRq_n,
	       m_cRqMshr$sendRsToP_cRq_getSlot_n;
  wire m_cRqMshr$EN_getEmptyEntryInit,
       m_cRqMshr$EN_pipelineResp_setResult,
       m_cRqMshr$EN_pipelineResp_setStateSlot,
       m_cRqMshr$EN_pipelineResp_setSucc,
       m_cRqMshr$EN_sendRsToC_releaseEntry,
       m_cRqMshr$EN_stuck_get,
       m_cRqMshr$RDY_getEmptyEntryInit,
       m_cRqMshr$RDY_sendRsToC_releaseEntry,
       m_cRqMshr$RDY_stuck_get;

  // ports of submodule m_fromPQ_clearReq_dummy2_0
  wire m_fromPQ_clearReq_dummy2_0$D_IN, m_fromPQ_clearReq_dummy2_0$EN;

  // ports of submodule m_fromPQ_clearReq_dummy2_1
  wire m_fromPQ_clearReq_dummy2_1$D_IN,
       m_fromPQ_clearReq_dummy2_1$EN,
       m_fromPQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule m_fromPQ_deqReq_dummy2_0
  wire m_fromPQ_deqReq_dummy2_0$D_IN, m_fromPQ_deqReq_dummy2_0$EN;

  // ports of submodule m_fromPQ_deqReq_dummy2_1
  wire m_fromPQ_deqReq_dummy2_1$D_IN, m_fromPQ_deqReq_dummy2_1$EN;

  // ports of submodule m_fromPQ_deqReq_dummy2_2
  wire m_fromPQ_deqReq_dummy2_2$D_IN,
       m_fromPQ_deqReq_dummy2_2$EN,
       m_fromPQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule m_fromPQ_enqReq_dummy2_0
  wire m_fromPQ_enqReq_dummy2_0$D_IN, m_fromPQ_enqReq_dummy2_0$EN;

  // ports of submodule m_fromPQ_enqReq_dummy2_1
  wire m_fromPQ_enqReq_dummy2_1$D_IN, m_fromPQ_enqReq_dummy2_1$EN;

  // ports of submodule m_fromPQ_enqReq_dummy2_2
  wire m_fromPQ_enqReq_dummy2_2$D_IN,
       m_fromPQ_enqReq_dummy2_2$EN,
       m_fromPQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule m_pRqMshr
  wire [67 : 0] m_pRqMshr$stuck_get;
  wire [65 : 0] m_pRqMshr$getEmptyEntryInit_r, m_pRqMshr$sendRsToP_pRq_getRq;
  wire [1 : 0] m_pRqMshr$getEmptyEntryInit,
	       m_pRqMshr$pipelineResp_getRq_n,
	       m_pRqMshr$pipelineResp_releaseEntry_n,
	       m_pRqMshr$pipelineResp_setDone_n,
	       m_pRqMshr$sendRsToP_pRq_getRq_n,
	       m_pRqMshr$sendRsToP_pRq_releaseEntry_n;
  wire m_pRqMshr$EN_getEmptyEntryInit,
       m_pRqMshr$EN_pipelineResp_releaseEntry,
       m_pRqMshr$EN_pipelineResp_setDone,
       m_pRqMshr$EN_sendRsToP_pRq_releaseEntry,
       m_pRqMshr$EN_stuck_get,
       m_pRqMshr$RDY_getEmptyEntryInit,
       m_pRqMshr$RDY_pipelineResp_releaseEntry,
       m_pRqMshr$RDY_sendRsToP_pRq_releaseEntry,
       m_pRqMshr$RDY_stuck_get;

  // ports of submodule m_pipeline
  reg [583 : 0] m_pipeline$send_r;
  reg [569 : 0] m_pipeline$deqWrite_wrRam;
  reg [3 : 0] m_pipeline$deqWrite_swapRq;
  reg m_pipeline$deqWrite_updateRep;
  wire [578 : 0] m_pipeline$first;
  wire m_pipeline$EN_deqWrite,
       m_pipeline$EN_send,
       m_pipeline$RDY_deqWrite,
       m_pipeline$RDY_first,
       m_pipeline$RDY_send;

  // ports of submodule m_rqFromCQ_data_0_dummy2_0
  wire m_rqFromCQ_data_0_dummy2_0$D_IN, m_rqFromCQ_data_0_dummy2_0$EN;

  // ports of submodule m_rqFromCQ_data_0_dummy2_1
  wire m_rqFromCQ_data_0_dummy2_1$D_IN,
       m_rqFromCQ_data_0_dummy2_1$EN,
       m_rqFromCQ_data_0_dummy2_1$Q_OUT;

  // ports of submodule m_rqFromCQ_deqP_dummy2_0
  wire m_rqFromCQ_deqP_dummy2_0$D_IN, m_rqFromCQ_deqP_dummy2_0$EN;

  // ports of submodule m_rqFromCQ_deqP_dummy2_1
  wire m_rqFromCQ_deqP_dummy2_1$D_IN, m_rqFromCQ_deqP_dummy2_1$EN;

  // ports of submodule m_rqFromCQ_empty_dummy2_0
  wire m_rqFromCQ_empty_dummy2_0$D_IN, m_rqFromCQ_empty_dummy2_0$EN;

  // ports of submodule m_rqFromCQ_empty_dummy2_1
  wire m_rqFromCQ_empty_dummy2_1$D_IN,
       m_rqFromCQ_empty_dummy2_1$EN,
       m_rqFromCQ_empty_dummy2_1$Q_OUT;

  // ports of submodule m_rqFromCQ_empty_dummy2_2
  wire m_rqFromCQ_empty_dummy2_2$D_IN,
       m_rqFromCQ_empty_dummy2_2$EN,
       m_rqFromCQ_empty_dummy2_2$Q_OUT;

  // ports of submodule m_rqFromCQ_enqP_dummy2_0
  wire m_rqFromCQ_enqP_dummy2_0$D_IN, m_rqFromCQ_enqP_dummy2_0$EN;

  // ports of submodule m_rqFromCQ_enqP_dummy2_1
  wire m_rqFromCQ_enqP_dummy2_1$D_IN, m_rqFromCQ_enqP_dummy2_1$EN;

  // ports of submodule m_rqFromCQ_full_dummy2_0
  wire m_rqFromCQ_full_dummy2_0$D_IN,
       m_rqFromCQ_full_dummy2_0$EN,
       m_rqFromCQ_full_dummy2_0$Q_OUT;

  // ports of submodule m_rqFromCQ_full_dummy2_1
  wire m_rqFromCQ_full_dummy2_1$D_IN,
       m_rqFromCQ_full_dummy2_1$EN,
       m_rqFromCQ_full_dummy2_1$Q_OUT;

  // ports of submodule m_rqFromCQ_full_dummy2_2
  wire m_rqFromCQ_full_dummy2_2$D_IN,
       m_rqFromCQ_full_dummy2_2$EN,
       m_rqFromCQ_full_dummy2_2$Q_OUT;

  // ports of submodule m_rqToPIndexQ
  wire [2 : 0] m_rqToPIndexQ$D_IN, m_rqToPIndexQ$D_OUT;
  wire m_rqToPIndexQ$CLR,
       m_rqToPIndexQ$DEQ,
       m_rqToPIndexQ$EMPTY_N,
       m_rqToPIndexQ$ENQ,
       m_rqToPIndexQ$FULL_N;

  // ports of submodule m_rqToPIndexQ_pipelineResp
  wire [2 : 0] m_rqToPIndexQ_pipelineResp$D_IN,
	       m_rqToPIndexQ_pipelineResp$D_OUT;
  wire m_rqToPIndexQ_pipelineResp$CLR,
       m_rqToPIndexQ_pipelineResp$DEQ,
       m_rqToPIndexQ_pipelineResp$EMPTY_N,
       m_rqToPIndexQ_pipelineResp$ENQ,
       m_rqToPIndexQ_pipelineResp$FULL_N;

  // ports of submodule m_rqToPIndexQ_sendRsToP
  wire [2 : 0] m_rqToPIndexQ_sendRsToP$D_IN, m_rqToPIndexQ_sendRsToP$D_OUT;
  wire m_rqToPIndexQ_sendRsToP$CLR,
       m_rqToPIndexQ_sendRsToP$DEQ,
       m_rqToPIndexQ_sendRsToP$EMPTY_N,
       m_rqToPIndexQ_sendRsToP$ENQ,
       m_rqToPIndexQ_sendRsToP$FULL_N;

  // ports of submodule m_rqToPQ_clearReq_dummy2_0
  wire m_rqToPQ_clearReq_dummy2_0$D_IN, m_rqToPQ_clearReq_dummy2_0$EN;

  // ports of submodule m_rqToPQ_clearReq_dummy2_1
  wire m_rqToPQ_clearReq_dummy2_1$D_IN,
       m_rqToPQ_clearReq_dummy2_1$EN,
       m_rqToPQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule m_rqToPQ_deqReq_dummy2_0
  wire m_rqToPQ_deqReq_dummy2_0$D_IN, m_rqToPQ_deqReq_dummy2_0$EN;

  // ports of submodule m_rqToPQ_deqReq_dummy2_1
  wire m_rqToPQ_deqReq_dummy2_1$D_IN, m_rqToPQ_deqReq_dummy2_1$EN;

  // ports of submodule m_rqToPQ_deqReq_dummy2_2
  wire m_rqToPQ_deqReq_dummy2_2$D_IN,
       m_rqToPQ_deqReq_dummy2_2$EN,
       m_rqToPQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule m_rqToPQ_enqReq_dummy2_0
  wire m_rqToPQ_enqReq_dummy2_0$D_IN, m_rqToPQ_enqReq_dummy2_0$EN;

  // ports of submodule m_rqToPQ_enqReq_dummy2_1
  wire m_rqToPQ_enqReq_dummy2_1$D_IN, m_rqToPQ_enqReq_dummy2_1$EN;

  // ports of submodule m_rqToPQ_enqReq_dummy2_2
  wire m_rqToPQ_enqReq_dummy2_2$D_IN,
       m_rqToPQ_enqReq_dummy2_2$EN,
       m_rqToPQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule m_rsToPIndexQ
  wire [3 : 0] m_rsToPIndexQ$D_IN, m_rsToPIndexQ$D_OUT;
  wire m_rsToPIndexQ$CLR,
       m_rsToPIndexQ$DEQ,
       m_rsToPIndexQ$EMPTY_N,
       m_rsToPIndexQ$ENQ,
       m_rsToPIndexQ$FULL_N;

  // ports of submodule m_rsToPQ_clearReq_dummy2_0
  wire m_rsToPQ_clearReq_dummy2_0$D_IN, m_rsToPQ_clearReq_dummy2_0$EN;

  // ports of submodule m_rsToPQ_clearReq_dummy2_1
  wire m_rsToPQ_clearReq_dummy2_1$D_IN,
       m_rsToPQ_clearReq_dummy2_1$EN,
       m_rsToPQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule m_rsToPQ_deqReq_dummy2_0
  wire m_rsToPQ_deqReq_dummy2_0$D_IN, m_rsToPQ_deqReq_dummy2_0$EN;

  // ports of submodule m_rsToPQ_deqReq_dummy2_1
  wire m_rsToPQ_deqReq_dummy2_1$D_IN, m_rsToPQ_deqReq_dummy2_1$EN;

  // ports of submodule m_rsToPQ_deqReq_dummy2_2
  wire m_rsToPQ_deqReq_dummy2_2$D_IN,
       m_rsToPQ_deqReq_dummy2_2$EN,
       m_rsToPQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule m_rsToPQ_enqReq_dummy2_0
  wire m_rsToPQ_enqReq_dummy2_0$D_IN, m_rsToPQ_enqReq_dummy2_0$EN;

  // ports of submodule m_rsToPQ_enqReq_dummy2_1
  wire m_rsToPQ_enqReq_dummy2_1$D_IN, m_rsToPQ_enqReq_dummy2_1$EN;

  // ports of submodule m_rsToPQ_enqReq_dummy2_2
  wire m_rsToPQ_enqReq_dummy2_2$D_IN,
       m_rsToPQ_enqReq_dummy2_2$EN,
       m_rsToPQ_enqReq_dummy2_2$Q_OUT;

  // rule scheduling signals
  wire CAN_FIRE_RL_m_cRqTransfer,
       CAN_FIRE_RL_m_fromPQ_canonicalize,
       CAN_FIRE_RL_m_fromPQ_clearReq_canon,
       CAN_FIRE_RL_m_fromPQ_deqReq_canon,
       CAN_FIRE_RL_m_fromPQ_enqReq_canon,
       CAN_FIRE_RL_m_pRqTransfer,
       CAN_FIRE_RL_m_pRsTransfer,
       CAN_FIRE_RL_m_pipelineResp_cRq,
       CAN_FIRE_RL_m_pipelineResp_pRq,
       CAN_FIRE_RL_m_pipelineResp_pRs,
       CAN_FIRE_RL_m_rqFromCQ_data_0_canon,
       CAN_FIRE_RL_m_rqFromCQ_empty_canon,
       CAN_FIRE_RL_m_rqFromCQ_full_canon,
       CAN_FIRE_RL_m_rqIndexFromPipelineResp,
       CAN_FIRE_RL_m_rqIndexFromSendRsToP,
       CAN_FIRE_RL_m_rqToPQ_canonicalize,
       CAN_FIRE_RL_m_rqToPQ_clearReq_canon,
       CAN_FIRE_RL_m_rqToPQ_deqReq_canon,
       CAN_FIRE_RL_m_rqToPQ_enqReq_canon,
       CAN_FIRE_RL_m_rsToPQ_canonicalize,
       CAN_FIRE_RL_m_rsToPQ_clearReq_canon,
       CAN_FIRE_RL_m_rsToPQ_deqReq_canon,
       CAN_FIRE_RL_m_rsToPQ_enqReq_canon,
       CAN_FIRE_RL_m_sendRqToP,
       CAN_FIRE_RL_m_sendRsToP_cRq,
       CAN_FIRE_RL_m_sendRsToP_pRq,
       CAN_FIRE_cRqStuck_get,
       CAN_FIRE_flush,
       CAN_FIRE_pRqStuck_get,
       CAN_FIRE_setPerfStatus,
       CAN_FIRE_to_parent_fromP_enq,
       CAN_FIRE_to_parent_rqToP_deq,
       CAN_FIRE_to_parent_rsToP_deq,
       CAN_FIRE_to_proc_req_put,
       CAN_FIRE_to_proc_resp_get,
       WILL_FIRE_RL_m_cRqTransfer,
       WILL_FIRE_RL_m_fromPQ_canonicalize,
       WILL_FIRE_RL_m_fromPQ_clearReq_canon,
       WILL_FIRE_RL_m_fromPQ_deqReq_canon,
       WILL_FIRE_RL_m_fromPQ_enqReq_canon,
       WILL_FIRE_RL_m_pRqTransfer,
       WILL_FIRE_RL_m_pRsTransfer,
       WILL_FIRE_RL_m_pipelineResp_cRq,
       WILL_FIRE_RL_m_pipelineResp_pRq,
       WILL_FIRE_RL_m_pipelineResp_pRs,
       WILL_FIRE_RL_m_rqFromCQ_data_0_canon,
       WILL_FIRE_RL_m_rqFromCQ_empty_canon,
       WILL_FIRE_RL_m_rqFromCQ_full_canon,
       WILL_FIRE_RL_m_rqIndexFromPipelineResp,
       WILL_FIRE_RL_m_rqIndexFromSendRsToP,
       WILL_FIRE_RL_m_rqToPQ_canonicalize,
       WILL_FIRE_RL_m_rqToPQ_clearReq_canon,
       WILL_FIRE_RL_m_rqToPQ_deqReq_canon,
       WILL_FIRE_RL_m_rqToPQ_enqReq_canon,
       WILL_FIRE_RL_m_rsToPQ_canonicalize,
       WILL_FIRE_RL_m_rsToPQ_clearReq_canon,
       WILL_FIRE_RL_m_rsToPQ_deqReq_canon,
       WILL_FIRE_RL_m_rsToPQ_enqReq_canon,
       WILL_FIRE_RL_m_sendRqToP,
       WILL_FIRE_RL_m_sendRsToP_cRq,
       WILL_FIRE_RL_m_sendRsToP_pRq,
       WILL_FIRE_cRqStuck_get,
       WILL_FIRE_flush,
       WILL_FIRE_pRqStuck_get,
       WILL_FIRE_setPerfStatus,
       WILL_FIRE_to_parent_fromP_enq,
       WILL_FIRE_to_parent_rqToP_deq,
       WILL_FIRE_to_parent_rsToP_deq,
       WILL_FIRE_to_proc_req_put,
       WILL_FIRE_to_proc_resp_get;

  // inputs to muxes for submodule ports
  wire [583 : 0] MUX_m_pipeline$send_1__VAL_1,
		 MUX_m_pipeline$send_1__VAL_2,
		 MUX_m_pipeline$send_1__VAL_3;
  wire [579 : 0] MUX_m_rsToPQ_enqReq_lat_0$wset_1__VAL_1,
		 MUX_m_rsToPQ_enqReq_lat_0$wset_1__VAL_2;
  wire [569 : 0] MUX_m_pipeline$deqWrite_2__VAL_1,
		 MUX_m_pipeline$deqWrite_2__VAL_2,
		 MUX_m_pipeline$deqWrite_2__VAL_3;
  wire [65 : 0] MUX_m_cRqMshr$pipelineResp_setResult_2__VAL_1;
  wire [55 : 0] MUX_m_cRqMshr$pipelineResp_setStateSlot_3__VAL_2;
  wire [3 : 0] MUX_m_pipeline$deqWrite_1__VAL_2,
	       MUX_m_rsToPIndexQ$enq_1__VAL_1,
	       MUX_m_rsToPIndexQ$enq_1__VAL_2;
  wire [2 : 0] MUX_m_cRqMshr$pipelineResp_setStateSlot_2__VAL_2;
  wire MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1,
       MUX_m_pipeline$deqWrite_3__VAL_2,
       MUX_m_rsToPIndexQ$enq_1__SEL_1,
       MUX_m_rsToPIndexQ$enq_1__SEL_2;

  // remaining internal signals
  reg [63 : 0] CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_130__ETC__q13,
	       CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_194__ETC__q12,
	       CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_258__ETC__q11,
	       CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_322__ETC__q8,
	       CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_386__ETC__q7,
	       CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_450__ETC__q6,
	       CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_514__ETC__q5,
	       CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_66_T_ETC__q14,
	       CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_71_T_ETC__q24,
	       CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_127__ETC__q15,
	       CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_191__ETC__q10,
	       CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_255__ETC__q9,
	       CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_319__ETC__q4,
	       CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_383__ETC__q3,
	       CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_447__ETC__q2,
	       CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_511__ETC__q1,
	       CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_578__ETC__q17,
	       CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_63_T_ETC__q16,
	       SEL_ARR_m_fromPQ_data_0_57_BITS_65_TO_2_66_m_f_ETC___d469,
	       addr__h46129;
  reg [31 : 0] CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q29,
	       CASE_sel1386_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q28;
  reg [2 : 0] CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_2_TO_ETC__q23,
	      x__h47671;
  reg [1 : 0] CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_1_TO_ETC__q30,
	      CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_5_TO_ETC__q21,
	      CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_7_TO_ETC__q25,
	      CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_514__ETC__q18;
  reg CASE_m_fromPQ_deqP_0_NOT_m_fromPQ_data_0_BIT_5_ETC__q20,
      CASE_m_fromPQ_deqP_0_NOT_m_fromPQ_data_0_BIT_5_ETC__q26,
      CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_582_1_ETC__q27,
      CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BIT_3_1_m_ETC__q22,
      CASE_m_rsToPQ_deqP_0_NOT_m_rsToPQ_data_0_BIT_5_ETC__q19;
  wire [581 : 0] IF_m_fromPQ_enqReq_dummy2_2_read__75_AND_IF_m__ETC___d428;
  wire [517 : 0] _1_CONCAT_NOT_SEL_ARR_NOT_m_fromPQ_data_0_57_BI_ETC___d535;
  wire [511 : 0] SEL_ARR_m_fromPQ_data_0_57_BITS_514_TO_451_93__ETC___d528,
		 SEL_ARR_m_rsToPQ_data_0_36_BITS_511_TO_448_53__ETC___d788;
  wire [383 : 0] SEL_ARR_m_fromPQ_data_0_57_BITS_514_TO_451_93__ETC___d519,
		 SEL_ARR_m_rsToPQ_data_0_36_BITS_511_TO_448_53__ETC___d779;
  wire [255 : 0] SEL_ARR_m_fromPQ_data_0_57_BITS_514_TO_451_93__ETC___d510,
		 SEL_ARR_m_rsToPQ_data_0_36_BITS_511_TO_448_53__ETC___d770;
  wire [63 : 0] IF_m_rqFromCQ_data_0_lat_0_whas_THEN_m_rqFromC_ETC___d6,
		resp_addr__h47838,
		v__h43566,
		x_addr__h14493;
  wire [57 : 0] IF_m_cRqMshr_pipelineResp_searchEndOfChain_m_c_ETC___d628,
		IF_m_pipeline_first__73_BITS_514_TO_512_78_EQ__ETC___d621;
  wire [5 : 0] IF_m_pipeline_first__73_BITS_517_TO_516_84_EQ__ETC___d626,
	       SEL_ARR_m_rqToPQ_data_0_92_BITS_5_TO_4_02_m_rq_ETC___d814;
  wire [3 : 0] sel__h51386;
  wire [2 : 0] IF_m_cRqMshr_pipelineResp_searchEndOfChain_m_c_ETC___d641,
	       x__h38966;
  wire IF_m_fromPQ_deqReq_dummy2_2_read__83_AND_IF_m__ETC___d391,
       IF_m_fromPQ_deqReq_lat_1_whas__54_THEN_m_fromP_ETC___d360,
       IF_m_fromPQ_enqReq_lat_1_whas__63_THEN_NOT_m_f_ETC___d279,
       IF_m_fromPQ_enqReq_lat_1_whas__63_THEN_m_fromP_ETC___d272,
       IF_m_pipeline_first__73_BITS_517_TO_516_84_EQ__ETC___d594,
       IF_m_rqToPQ_deqReq_dummy2_2_read__24_AND_IF_m__ETC___d232,
       IF_m_rqToPQ_deqReq_lat_1_whas__95_THEN_m_rqToP_ETC___d201,
       IF_m_rqToPQ_enqReq_lat_1_whas__66_THEN_m_rqToP_ETC___d175,
       IF_m_rsToPQ_deqReq_dummy2_2_read__20_AND_IF_m__ETC___d128,
       IF_m_rsToPQ_deqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d97,
       IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_NOT_m_rs_ETC___d47,
       IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d40,
       NOT_m_fromPQ_clearReq_dummy2_1_read__69_70_OR__ETC___d374,
       NOT_m_fromPQ_enqReq_dummy2_2_read__75_05_OR_IF_ETC___d409,
       NOT_m_rqToPQ_clearReq_dummy2_1_read__10_11_OR__ETC___d215,
       NOT_m_rqToPQ_enqReq_dummy2_2_read__16_46_OR_IF_ETC___d250,
       NOT_m_rsToPQ_clearReq_dummy2_1_read__06_07_OR__ETC___d111,
       NOT_m_rsToPQ_enqReq_dummy2_2_read__12_42_OR_IF_ETC___d146,
       _theResult_____2__h18784,
       _theResult_____2__h26689,
       _theResult_____2__h41332,
       m_fromPQ_enqReq_dummy2_2_read__75_AND_IF_m_fro_ETC___d401,
       m_pipeline_RDY_deqWrite__72_AND_IF_m_pipeline__ETC___d716,
       m_pipeline_first__73_BITS_514_TO_512_78_EQ_m_p_ETC___d600,
       m_pipeline_first__73_BITS_569_TO_518_86_EQ_m_c_ETC___d588,
       m_pipeline_first__73_BIT_515_74_AND_m_pipeline_ETC___d657,
       m_rqToPQ_enqReq_dummy2_2_read__16_AND_IF_m_rqT_ETC___d242,
       m_rsToPQ_enqReq_dummy2_2_read__12_AND_IF_m_rsT_ETC___d138,
       next_deqP___1__h19103,
       next_deqP___1__h27008,
       next_deqP___1__h41651,
       v__h14050,
       v__h14333,
       v__h25933,
       v__h26216,
       v__h36262,
       v__h36545;

  // value method to_parent_rsToP_notEmpty
  assign to_parent_rsToP_notEmpty = !m_rsToPQ_empty ;
  assign RDY_to_parent_rsToP_notEmpty = 1'd1 ;

  // action method to_parent_rsToP_deq
  assign RDY_to_parent_rsToP_deq = !m_rsToPQ_empty ;
  assign CAN_FIRE_to_parent_rsToP_deq = !m_rsToPQ_empty ;
  assign WILL_FIRE_to_parent_rsToP_deq = EN_to_parent_rsToP_deq ;

  // value method to_parent_rsToP_first
  assign to_parent_rsToP_first =
	     { CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_578__ETC__q17,
	       CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_514__ETC__q18,
	       !CASE_m_rsToPQ_deqP_0_NOT_m_rsToPQ_data_0_BIT_5_ETC__q19,
	       SEL_ARR_m_rsToPQ_data_0_36_BITS_511_TO_448_53__ETC___d788 } ;
  assign RDY_to_parent_rsToP_first = !m_rsToPQ_empty ;

  // value method to_parent_rqToP_notEmpty
  assign to_parent_rqToP_notEmpty = !m_rqToPQ_empty ;
  assign RDY_to_parent_rqToP_notEmpty = 1'd1 ;

  // action method to_parent_rqToP_deq
  assign RDY_to_parent_rqToP_deq = !m_rqToPQ_empty ;
  assign CAN_FIRE_to_parent_rqToP_deq = !m_rqToPQ_empty ;
  assign WILL_FIRE_to_parent_rqToP_deq = EN_to_parent_rqToP_deq ;

  // value method to_parent_rqToP_first
  assign to_parent_rqToP_first =
	     { CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_71_T_ETC__q24,
	       CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_7_TO_ETC__q25,
	       SEL_ARR_m_rqToPQ_data_0_92_BITS_5_TO_4_02_m_rq_ETC___d814 } ;
  assign RDY_to_parent_rqToP_first = !m_rqToPQ_empty ;

  // value method to_parent_fromP_notFull
  assign to_parent_fromP_notFull = !m_fromPQ_full ;
  assign RDY_to_parent_fromP_notFull = 1'd1 ;

  // action method to_parent_fromP_enq
  assign RDY_to_parent_fromP_enq = !m_fromPQ_full ;
  assign CAN_FIRE_to_parent_fromP_enq = !m_fromPQ_full ;
  assign WILL_FIRE_to_parent_fromP_enq = EN_to_parent_fromP_enq ;

  // action method to_proc_req_put
  assign RDY_to_proc_req_put =
	     !m_rqFromCQ_full_dummy2_0$Q_OUT ||
	     !m_rqFromCQ_full_dummy2_1$Q_OUT ||
	     !m_rqFromCQ_full_dummy2_2$Q_OUT ||
	     !m_rqFromCQ_full_rl ;
  assign CAN_FIRE_to_proc_req_put =
	     !m_rqFromCQ_full_dummy2_0$Q_OUT ||
	     !m_rqFromCQ_full_dummy2_1$Q_OUT ||
	     !m_rqFromCQ_full_dummy2_2$Q_OUT ||
	     !m_rqFromCQ_full_rl ;
  assign WILL_FIRE_to_proc_req_put = EN_to_proc_req_put ;

  // actionvalue method to_proc_resp_get
  assign to_proc_resp_get = m_cRqMshr$sendRsToC_getResult[65:0] ;
  assign RDY_to_proc_resp_get =
	     m_cRqIndexQ$EMPTY_N && m_cRqMshr$sendRsToC_getResult[66] &&
	     m_cRqMshr$RDY_sendRsToC_releaseEntry ;
  assign CAN_FIRE_to_proc_resp_get =
	     m_cRqIndexQ$EMPTY_N && m_cRqMshr$sendRsToC_getResult[66] &&
	     m_cRqMshr$RDY_sendRsToC_releaseEntry ;
  assign WILL_FIRE_to_proc_resp_get = EN_to_proc_resp_get ;

  // actionvalue method cRqStuck_get
  assign cRqStuck_get = m_cRqMshr$stuck_get ;
  assign RDY_cRqStuck_get = m_cRqMshr$RDY_stuck_get ;
  assign CAN_FIRE_cRqStuck_get = m_cRqMshr$RDY_stuck_get ;
  assign WILL_FIRE_cRqStuck_get = EN_cRqStuck_get ;

  // actionvalue method pRqStuck_get
  assign pRqStuck_get = m_pRqMshr$stuck_get ;
  assign RDY_pRqStuck_get = m_pRqMshr$RDY_stuck_get ;
  assign CAN_FIRE_pRqStuck_get = m_pRqMshr$RDY_stuck_get ;
  assign WILL_FIRE_pRqStuck_get = EN_pRqStuck_get ;

  // action method flush
  assign RDY_flush = 1'd1 ;
  assign CAN_FIRE_flush = 1'd1 ;
  assign WILL_FIRE_flush = EN_flush ;

  // value method flush_done
  assign flush_done = 1'd1 ;
  assign RDY_flush_done = 1'd1 ;

  // action method setPerfStatus
  assign RDY_setPerfStatus = 1'd1 ;
  assign CAN_FIRE_setPerfStatus = 1'd1 ;
  assign WILL_FIRE_setPerfStatus = EN_setPerfStatus ;

  // value method getPerfData
  assign getPerfData = 64'd0 ;
  assign RDY_getPerfData = 1'd1 ;

  // submodule m_cRqIndexQ
  SizedFIFO #(.p1width(32'd3),
	      .p2depth(32'd8),
	      .p3cntr_width(32'd3),
	      .guarded(32'd1)) m_cRqIndexQ(.RST(RST_N),
					   .CLK(CLK),
					   .D_IN(m_cRqIndexQ$D_IN),
					   .ENQ(m_cRqIndexQ$ENQ),
					   .DEQ(m_cRqIndexQ$DEQ),
					   .CLR(m_cRqIndexQ$CLR),
					   .D_OUT(m_cRqIndexQ$D_OUT),
					   .FULL_N(m_cRqIndexQ$FULL_N),
					   .EMPTY_N(m_cRqIndexQ$EMPTY_N));

  // submodule m_cRqMshr
  mkICRqMshrWrapper m_cRqMshr(.CLK(CLK),
			      .RST_N(RST_N),
			      .getEmptyEntryInit_r(m_cRqMshr$getEmptyEntryInit_r),
			      .pipelineResp_getRq_n(m_cRqMshr$pipelineResp_getRq_n),
			      .pipelineResp_getSlot_n(m_cRqMshr$pipelineResp_getSlot_n),
			      .pipelineResp_getState_n(m_cRqMshr$pipelineResp_getState_n),
			      .pipelineResp_getSucc_n(m_cRqMshr$pipelineResp_getSucc_n),
			      .pipelineResp_searchEndOfChain_addr(m_cRqMshr$pipelineResp_searchEndOfChain_addr),
			      .pipelineResp_setResult_n(m_cRqMshr$pipelineResp_setResult_n),
			      .pipelineResp_setResult_r(m_cRqMshr$pipelineResp_setResult_r),
			      .pipelineResp_setStateSlot_n(m_cRqMshr$pipelineResp_setStateSlot_n),
			      .pipelineResp_setStateSlot_slot(m_cRqMshr$pipelineResp_setStateSlot_slot),
			      .pipelineResp_setStateSlot_state(m_cRqMshr$pipelineResp_setStateSlot_state),
			      .pipelineResp_setSucc_n(m_cRqMshr$pipelineResp_setSucc_n),
			      .pipelineResp_setSucc_succ(m_cRqMshr$pipelineResp_setSucc_succ),
			      .sendRqToP_getRq_n(m_cRqMshr$sendRqToP_getRq_n),
			      .sendRqToP_getSlot_n(m_cRqMshr$sendRqToP_getSlot_n),
			      .sendRsToC_getResult_n(m_cRqMshr$sendRsToC_getResult_n),
			      .sendRsToC_releaseEntry_n(m_cRqMshr$sendRsToC_releaseEntry_n),
			      .sendRsToP_cRq_getRq_n(m_cRqMshr$sendRsToP_cRq_getRq_n),
			      .sendRsToP_cRq_getSlot_n(m_cRqMshr$sendRsToP_cRq_getSlot_n),
			      .EN_getEmptyEntryInit(m_cRqMshr$EN_getEmptyEntryInit),
			      .EN_sendRsToC_releaseEntry(m_cRqMshr$EN_sendRsToC_releaseEntry),
			      .EN_pipelineResp_setResult(m_cRqMshr$EN_pipelineResp_setResult),
			      .EN_pipelineResp_setStateSlot(m_cRqMshr$EN_pipelineResp_setStateSlot),
			      .EN_pipelineResp_setSucc(m_cRqMshr$EN_pipelineResp_setSucc),
			      .EN_stuck_get(m_cRqMshr$EN_stuck_get),
			      .getEmptyEntryInit(m_cRqMshr$getEmptyEntryInit),
			      .RDY_getEmptyEntryInit(m_cRqMshr$RDY_getEmptyEntryInit),
			      .RDY_sendRsToC_releaseEntry(m_cRqMshr$RDY_sendRsToC_releaseEntry),
			      .sendRsToC_getResult(m_cRqMshr$sendRsToC_getResult),
			      .RDY_sendRsToC_getResult(),
			      .sendRsToP_cRq_getRq(m_cRqMshr$sendRsToP_cRq_getRq),
			      .RDY_sendRsToP_cRq_getRq(),
			      .sendRsToP_cRq_getSlot(m_cRqMshr$sendRsToP_cRq_getSlot),
			      .RDY_sendRsToP_cRq_getSlot(),
			      .sendRqToP_getRq(m_cRqMshr$sendRqToP_getRq),
			      .RDY_sendRqToP_getRq(),
			      .sendRqToP_getSlot(m_cRqMshr$sendRqToP_getSlot),
			      .RDY_sendRqToP_getSlot(),
			      .pipelineResp_getState(),
			      .RDY_pipelineResp_getState(),
			      .pipelineResp_getRq(m_cRqMshr$pipelineResp_getRq),
			      .RDY_pipelineResp_getRq(),
			      .pipelineResp_getSlot(),
			      .RDY_pipelineResp_getSlot(),
			      .RDY_pipelineResp_setResult(),
			      .RDY_pipelineResp_setStateSlot(),
			      .pipelineResp_getSucc(m_cRqMshr$pipelineResp_getSucc),
			      .RDY_pipelineResp_getSucc(),
			      .RDY_pipelineResp_setSucc(),
			      .pipelineResp_searchEndOfChain(m_cRqMshr$pipelineResp_searchEndOfChain),
			      .RDY_pipelineResp_searchEndOfChain(),
			      .emptyForFlush(),
			      .RDY_emptyForFlush(),
			      .stuck_get(m_cRqMshr$stuck_get),
			      .RDY_stuck_get(m_cRqMshr$RDY_stuck_get));

  // submodule m_fromPQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) m_fromPQ_clearReq_dummy2_0(.CLK(CLK),
						      .D_IN(m_fromPQ_clearReq_dummy2_0$D_IN),
						      .EN(m_fromPQ_clearReq_dummy2_0$EN),
						      .Q_OUT());

  // submodule m_fromPQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) m_fromPQ_clearReq_dummy2_1(.CLK(CLK),
						      .D_IN(m_fromPQ_clearReq_dummy2_1$D_IN),
						      .EN(m_fromPQ_clearReq_dummy2_1$EN),
						      .Q_OUT(m_fromPQ_clearReq_dummy2_1$Q_OUT));

  // submodule m_fromPQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) m_fromPQ_deqReq_dummy2_0(.CLK(CLK),
								   .D_IN(m_fromPQ_deqReq_dummy2_0$D_IN),
								   .EN(m_fromPQ_deqReq_dummy2_0$EN),
								   .Q_OUT());

  // submodule m_fromPQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) m_fromPQ_deqReq_dummy2_1(.CLK(CLK),
								   .D_IN(m_fromPQ_deqReq_dummy2_1$D_IN),
								   .EN(m_fromPQ_deqReq_dummy2_1$EN),
								   .Q_OUT());

  // submodule m_fromPQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) m_fromPQ_deqReq_dummy2_2(.CLK(CLK),
								   .D_IN(m_fromPQ_deqReq_dummy2_2$D_IN),
								   .EN(m_fromPQ_deqReq_dummy2_2$EN),
								   .Q_OUT(m_fromPQ_deqReq_dummy2_2$Q_OUT));

  // submodule m_fromPQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) m_fromPQ_enqReq_dummy2_0(.CLK(CLK),
								   .D_IN(m_fromPQ_enqReq_dummy2_0$D_IN),
								   .EN(m_fromPQ_enqReq_dummy2_0$EN),
								   .Q_OUT());

  // submodule m_fromPQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) m_fromPQ_enqReq_dummy2_1(.CLK(CLK),
								   .D_IN(m_fromPQ_enqReq_dummy2_1$D_IN),
								   .EN(m_fromPQ_enqReq_dummy2_1$EN),
								   .Q_OUT());

  // submodule m_fromPQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) m_fromPQ_enqReq_dummy2_2(.CLK(CLK),
								   .D_IN(m_fromPQ_enqReq_dummy2_2$D_IN),
								   .EN(m_fromPQ_enqReq_dummy2_2$EN),
								   .Q_OUT(m_fromPQ_enqReq_dummy2_2$Q_OUT));

  // submodule m_pRqMshr
  mkIPRqMshrWrapper m_pRqMshr(.CLK(CLK),
			      .RST_N(RST_N),
			      .getEmptyEntryInit_r(m_pRqMshr$getEmptyEntryInit_r),
			      .pipelineResp_getRq_n(m_pRqMshr$pipelineResp_getRq_n),
			      .pipelineResp_releaseEntry_n(m_pRqMshr$pipelineResp_releaseEntry_n),
			      .pipelineResp_setDone_n(m_pRqMshr$pipelineResp_setDone_n),
			      .sendRsToP_pRq_getRq_n(m_pRqMshr$sendRsToP_pRq_getRq_n),
			      .sendRsToP_pRq_releaseEntry_n(m_pRqMshr$sendRsToP_pRq_releaseEntry_n),
			      .EN_getEmptyEntryInit(m_pRqMshr$EN_getEmptyEntryInit),
			      .EN_sendRsToP_pRq_releaseEntry(m_pRqMshr$EN_sendRsToP_pRq_releaseEntry),
			      .EN_pipelineResp_releaseEntry(m_pRqMshr$EN_pipelineResp_releaseEntry),
			      .EN_pipelineResp_setDone(m_pRqMshr$EN_pipelineResp_setDone),
			      .EN_stuck_get(m_pRqMshr$EN_stuck_get),
			      .getEmptyEntryInit(m_pRqMshr$getEmptyEntryInit),
			      .RDY_getEmptyEntryInit(m_pRqMshr$RDY_getEmptyEntryInit),
			      .sendRsToP_pRq_getRq(m_pRqMshr$sendRsToP_pRq_getRq),
			      .RDY_sendRsToP_pRq_getRq(),
			      .RDY_sendRsToP_pRq_releaseEntry(m_pRqMshr$RDY_sendRsToP_pRq_releaseEntry),
			      .pipelineResp_getRq(),
			      .RDY_pipelineResp_getRq(),
			      .RDY_pipelineResp_releaseEntry(m_pRqMshr$RDY_pipelineResp_releaseEntry),
			      .RDY_pipelineResp_setDone(),
			      .stuck_get(m_pRqMshr$stuck_get),
			      .RDY_stuck_get(m_pRqMshr$RDY_stuck_get));

  // submodule m_pipeline
  mkIPipeline m_pipeline(.CLK(CLK),
			 .RST_N(RST_N),
			 .deqWrite_swapRq(m_pipeline$deqWrite_swapRq),
			 .deqWrite_updateRep(m_pipeline$deqWrite_updateRep),
			 .deqWrite_wrRam(m_pipeline$deqWrite_wrRam),
			 .send_r(m_pipeline$send_r),
			 .EN_send(m_pipeline$EN_send),
			 .EN_deqWrite(m_pipeline$EN_deqWrite),
			 .RDY_send(m_pipeline$RDY_send),
			 .first(m_pipeline$first),
			 .RDY_first(m_pipeline$RDY_first),
			 .RDY_deqWrite(m_pipeline$RDY_deqWrite));

  // submodule m_rqFromCQ_data_0_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) m_rqFromCQ_data_0_dummy2_0(.CLK(CLK),
						      .D_IN(m_rqFromCQ_data_0_dummy2_0$D_IN),
						      .EN(m_rqFromCQ_data_0_dummy2_0$EN),
						      .Q_OUT());

  // submodule m_rqFromCQ_data_0_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) m_rqFromCQ_data_0_dummy2_1(.CLK(CLK),
						      .D_IN(m_rqFromCQ_data_0_dummy2_1$D_IN),
						      .EN(m_rqFromCQ_data_0_dummy2_1$EN),
						      .Q_OUT(m_rqFromCQ_data_0_dummy2_1$Q_OUT));

  // submodule m_rqFromCQ_deqP_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) m_rqFromCQ_deqP_dummy2_0(.CLK(CLK),
								   .D_IN(m_rqFromCQ_deqP_dummy2_0$D_IN),
								   .EN(m_rqFromCQ_deqP_dummy2_0$EN),
								   .Q_OUT());

  // submodule m_rqFromCQ_deqP_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) m_rqFromCQ_deqP_dummy2_1(.CLK(CLK),
								   .D_IN(m_rqFromCQ_deqP_dummy2_1$D_IN),
								   .EN(m_rqFromCQ_deqP_dummy2_1$EN),
								   .Q_OUT());

  // submodule m_rqFromCQ_empty_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) m_rqFromCQ_empty_dummy2_0(.CLK(CLK),
								    .D_IN(m_rqFromCQ_empty_dummy2_0$D_IN),
								    .EN(m_rqFromCQ_empty_dummy2_0$EN),
								    .Q_OUT());

  // submodule m_rqFromCQ_empty_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) m_rqFromCQ_empty_dummy2_1(.CLK(CLK),
								    .D_IN(m_rqFromCQ_empty_dummy2_1$D_IN),
								    .EN(m_rqFromCQ_empty_dummy2_1$EN),
								    .Q_OUT(m_rqFromCQ_empty_dummy2_1$Q_OUT));

  // submodule m_rqFromCQ_empty_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) m_rqFromCQ_empty_dummy2_2(.CLK(CLK),
								    .D_IN(m_rqFromCQ_empty_dummy2_2$D_IN),
								    .EN(m_rqFromCQ_empty_dummy2_2$EN),
								    .Q_OUT(m_rqFromCQ_empty_dummy2_2$Q_OUT));

  // submodule m_rqFromCQ_enqP_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) m_rqFromCQ_enqP_dummy2_0(.CLK(CLK),
								   .D_IN(m_rqFromCQ_enqP_dummy2_0$D_IN),
								   .EN(m_rqFromCQ_enqP_dummy2_0$EN),
								   .Q_OUT());

  // submodule m_rqFromCQ_enqP_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) m_rqFromCQ_enqP_dummy2_1(.CLK(CLK),
								   .D_IN(m_rqFromCQ_enqP_dummy2_1$D_IN),
								   .EN(m_rqFromCQ_enqP_dummy2_1$EN),
								   .Q_OUT());

  // submodule m_rqFromCQ_full_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) m_rqFromCQ_full_dummy2_0(.CLK(CLK),
								   .D_IN(m_rqFromCQ_full_dummy2_0$D_IN),
								   .EN(m_rqFromCQ_full_dummy2_0$EN),
								   .Q_OUT(m_rqFromCQ_full_dummy2_0$Q_OUT));

  // submodule m_rqFromCQ_full_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) m_rqFromCQ_full_dummy2_1(.CLK(CLK),
								   .D_IN(m_rqFromCQ_full_dummy2_1$D_IN),
								   .EN(m_rqFromCQ_full_dummy2_1$EN),
								   .Q_OUT(m_rqFromCQ_full_dummy2_1$Q_OUT));

  // submodule m_rqFromCQ_full_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) m_rqFromCQ_full_dummy2_2(.CLK(CLK),
								   .D_IN(m_rqFromCQ_full_dummy2_2$D_IN),
								   .EN(m_rqFromCQ_full_dummy2_2$EN),
								   .Q_OUT(m_rqFromCQ_full_dummy2_2$Q_OUT));

  // submodule m_rqToPIndexQ
  SizedFIFO #(.p1width(32'd3),
	      .p2depth(32'd8),
	      .p3cntr_width(32'd3),
	      .guarded(32'd1)) m_rqToPIndexQ(.RST(RST_N),
					     .CLK(CLK),
					     .D_IN(m_rqToPIndexQ$D_IN),
					     .ENQ(m_rqToPIndexQ$ENQ),
					     .DEQ(m_rqToPIndexQ$DEQ),
					     .CLR(m_rqToPIndexQ$CLR),
					     .D_OUT(m_rqToPIndexQ$D_OUT),
					     .FULL_N(m_rqToPIndexQ$FULL_N),
					     .EMPTY_N(m_rqToPIndexQ$EMPTY_N));

  // submodule m_rqToPIndexQ_pipelineResp
  FIFO2 #(.width(32'd3),
	  .guarded(32'd1)) m_rqToPIndexQ_pipelineResp(.RST(RST_N),
						      .CLK(CLK),
						      .D_IN(m_rqToPIndexQ_pipelineResp$D_IN),
						      .ENQ(m_rqToPIndexQ_pipelineResp$ENQ),
						      .DEQ(m_rqToPIndexQ_pipelineResp$DEQ),
						      .CLR(m_rqToPIndexQ_pipelineResp$CLR),
						      .D_OUT(m_rqToPIndexQ_pipelineResp$D_OUT),
						      .FULL_N(m_rqToPIndexQ_pipelineResp$FULL_N),
						      .EMPTY_N(m_rqToPIndexQ_pipelineResp$EMPTY_N));

  // submodule m_rqToPIndexQ_sendRsToP
  FIFO2 #(.width(32'd3), .guarded(32'd1)) m_rqToPIndexQ_sendRsToP(.RST(RST_N),
								  .CLK(CLK),
								  .D_IN(m_rqToPIndexQ_sendRsToP$D_IN),
								  .ENQ(m_rqToPIndexQ_sendRsToP$ENQ),
								  .DEQ(m_rqToPIndexQ_sendRsToP$DEQ),
								  .CLR(m_rqToPIndexQ_sendRsToP$CLR),
								  .D_OUT(m_rqToPIndexQ_sendRsToP$D_OUT),
								  .FULL_N(m_rqToPIndexQ_sendRsToP$FULL_N),
								  .EMPTY_N(m_rqToPIndexQ_sendRsToP$EMPTY_N));

  // submodule m_rqToPQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) m_rqToPQ_clearReq_dummy2_0(.CLK(CLK),
						      .D_IN(m_rqToPQ_clearReq_dummy2_0$D_IN),
						      .EN(m_rqToPQ_clearReq_dummy2_0$EN),
						      .Q_OUT());

  // submodule m_rqToPQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) m_rqToPQ_clearReq_dummy2_1(.CLK(CLK),
						      .D_IN(m_rqToPQ_clearReq_dummy2_1$D_IN),
						      .EN(m_rqToPQ_clearReq_dummy2_1$EN),
						      .Q_OUT(m_rqToPQ_clearReq_dummy2_1$Q_OUT));

  // submodule m_rqToPQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) m_rqToPQ_deqReq_dummy2_0(.CLK(CLK),
								   .D_IN(m_rqToPQ_deqReq_dummy2_0$D_IN),
								   .EN(m_rqToPQ_deqReq_dummy2_0$EN),
								   .Q_OUT());

  // submodule m_rqToPQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) m_rqToPQ_deqReq_dummy2_1(.CLK(CLK),
								   .D_IN(m_rqToPQ_deqReq_dummy2_1$D_IN),
								   .EN(m_rqToPQ_deqReq_dummy2_1$EN),
								   .Q_OUT());

  // submodule m_rqToPQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) m_rqToPQ_deqReq_dummy2_2(.CLK(CLK),
								   .D_IN(m_rqToPQ_deqReq_dummy2_2$D_IN),
								   .EN(m_rqToPQ_deqReq_dummy2_2$EN),
								   .Q_OUT(m_rqToPQ_deqReq_dummy2_2$Q_OUT));

  // submodule m_rqToPQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) m_rqToPQ_enqReq_dummy2_0(.CLK(CLK),
								   .D_IN(m_rqToPQ_enqReq_dummy2_0$D_IN),
								   .EN(m_rqToPQ_enqReq_dummy2_0$EN),
								   .Q_OUT());

  // submodule m_rqToPQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) m_rqToPQ_enqReq_dummy2_1(.CLK(CLK),
								   .D_IN(m_rqToPQ_enqReq_dummy2_1$D_IN),
								   .EN(m_rqToPQ_enqReq_dummy2_1$EN),
								   .Q_OUT());

  // submodule m_rqToPQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) m_rqToPQ_enqReq_dummy2_2(.CLK(CLK),
								   .D_IN(m_rqToPQ_enqReq_dummy2_2$D_IN),
								   .EN(m_rqToPQ_enqReq_dummy2_2$EN),
								   .Q_OUT(m_rqToPQ_enqReq_dummy2_2$Q_OUT));

  // submodule m_rsToPIndexQ
  SizedFIFO #(.p1width(32'd4),
	      .p2depth(32'd12),
	      .p3cntr_width(32'd4),
	      .guarded(32'd1)) m_rsToPIndexQ(.RST(RST_N),
					     .CLK(CLK),
					     .D_IN(m_rsToPIndexQ$D_IN),
					     .ENQ(m_rsToPIndexQ$ENQ),
					     .DEQ(m_rsToPIndexQ$DEQ),
					     .CLR(m_rsToPIndexQ$CLR),
					     .D_OUT(m_rsToPIndexQ$D_OUT),
					     .FULL_N(m_rsToPIndexQ$FULL_N),
					     .EMPTY_N(m_rsToPIndexQ$EMPTY_N));

  // submodule m_rsToPQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) m_rsToPQ_clearReq_dummy2_0(.CLK(CLK),
						      .D_IN(m_rsToPQ_clearReq_dummy2_0$D_IN),
						      .EN(m_rsToPQ_clearReq_dummy2_0$EN),
						      .Q_OUT());

  // submodule m_rsToPQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) m_rsToPQ_clearReq_dummy2_1(.CLK(CLK),
						      .D_IN(m_rsToPQ_clearReq_dummy2_1$D_IN),
						      .EN(m_rsToPQ_clearReq_dummy2_1$EN),
						      .Q_OUT(m_rsToPQ_clearReq_dummy2_1$Q_OUT));

  // submodule m_rsToPQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) m_rsToPQ_deqReq_dummy2_0(.CLK(CLK),
								   .D_IN(m_rsToPQ_deqReq_dummy2_0$D_IN),
								   .EN(m_rsToPQ_deqReq_dummy2_0$EN),
								   .Q_OUT());

  // submodule m_rsToPQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) m_rsToPQ_deqReq_dummy2_1(.CLK(CLK),
								   .D_IN(m_rsToPQ_deqReq_dummy2_1$D_IN),
								   .EN(m_rsToPQ_deqReq_dummy2_1$EN),
								   .Q_OUT());

  // submodule m_rsToPQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) m_rsToPQ_deqReq_dummy2_2(.CLK(CLK),
								   .D_IN(m_rsToPQ_deqReq_dummy2_2$D_IN),
								   .EN(m_rsToPQ_deqReq_dummy2_2$EN),
								   .Q_OUT(m_rsToPQ_deqReq_dummy2_2$Q_OUT));

  // submodule m_rsToPQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) m_rsToPQ_enqReq_dummy2_0(.CLK(CLK),
								   .D_IN(m_rsToPQ_enqReq_dummy2_0$D_IN),
								   .EN(m_rsToPQ_enqReq_dummy2_0$EN),
								   .Q_OUT());

  // submodule m_rsToPQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) m_rsToPQ_enqReq_dummy2_1(.CLK(CLK),
								   .D_IN(m_rsToPQ_enqReq_dummy2_1$D_IN),
								   .EN(m_rsToPQ_enqReq_dummy2_1$EN),
								   .Q_OUT());

  // submodule m_rsToPQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) m_rsToPQ_enqReq_dummy2_2(.CLK(CLK),
								   .D_IN(m_rsToPQ_enqReq_dummy2_2$D_IN),
								   .EN(m_rsToPQ_enqReq_dummy2_2$EN),
								   .Q_OUT(m_rsToPQ_enqReq_dummy2_2$Q_OUT));

  // rule RL_m_sendRsToP_cRq
  assign CAN_FIRE_RL_m_sendRsToP_cRq =
	     !m_rsToPQ_full && m_rsToPIndexQ$EMPTY_N &&
	     m_rqToPIndexQ_sendRsToP$FULL_N &&
	     !m_rsToPIndexQ$D_OUT[3] ;
  assign WILL_FIRE_RL_m_sendRsToP_cRq = CAN_FIRE_RL_m_sendRsToP_cRq ;

  // rule RL_m_sendRqToP
  assign CAN_FIRE_RL_m_sendRqToP = !m_rqToPQ_full && m_rqToPIndexQ$EMPTY_N ;
  assign WILL_FIRE_RL_m_sendRqToP = CAN_FIRE_RL_m_sendRqToP ;

  // rule RL_m_pipelineResp_cRq
  assign CAN_FIRE_RL_m_pipelineResp_cRq =
	     m_pipeline$RDY_first && m_pipeline$RDY_deqWrite &&
	     (m_pipeline$first[515] ||
	      m_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      IF_m_pipeline_first__73_BITS_517_TO_516_84_EQ__ETC___d594) &&
	     m_pipeline$first[578:577] == 2'd0 ;
  assign WILL_FIRE_RL_m_pipelineResp_cRq = CAN_FIRE_RL_m_pipelineResp_cRq ;

  // rule RL_m_pipelineResp_pRs
  assign CAN_FIRE_RL_m_pipelineResp_pRs =
	     m_pipeline$RDY_first &&
	     (!m_pipeline$first[515] || m_pipeline$RDY_deqWrite) &&
	     m_pipeline$first[578:577] != 2'd0 &&
	     m_pipeline$first[578:577] != 2'd1 ;
  assign WILL_FIRE_RL_m_pipelineResp_pRs = CAN_FIRE_RL_m_pipelineResp_pRs ;

  // rule RL_m_pipelineResp_pRq
  assign CAN_FIRE_RL_m_pipelineResp_pRq =
	     m_pipeline$RDY_first &&
	     m_pipeline_RDY_deqWrite__72_AND_IF_m_pipeline__ETC___d716 &&
	     m_pipeline$first[578:577] == 2'd1 ;
  assign WILL_FIRE_RL_m_pipelineResp_pRq = CAN_FIRE_RL_m_pipelineResp_pRq ;

  // rule RL_m_cRqTransfer
  assign CAN_FIRE_RL_m_cRqTransfer =
	     (!m_rqFromCQ_empty_dummy2_1$Q_OUT ||
	      !m_rqFromCQ_empty_dummy2_2$Q_OUT ||
	      EN_to_proc_req_put ||
	      !m_rqFromCQ_empty_rl) &&
	     m_pipeline$RDY_send &&
	     m_cRqMshr$RDY_getEmptyEntryInit &&
	     m_cRqIndexQ$FULL_N ;
  assign WILL_FIRE_RL_m_cRqTransfer =
	     CAN_FIRE_RL_m_cRqTransfer && !WILL_FIRE_RL_m_pRsTransfer &&
	     !WILL_FIRE_RL_m_pRqTransfer ;

  // rule RL_m_pRsTransfer
  assign CAN_FIRE_RL_m_pRsTransfer =
	     !m_fromPQ_empty && m_pipeline$RDY_send &&
	     CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_582_1_ETC__q27 ;
  assign WILL_FIRE_RL_m_pRsTransfer = CAN_FIRE_RL_m_pRsTransfer ;

  // rule RL_m_sendRsToP_pRq
  assign CAN_FIRE_RL_m_sendRsToP_pRq =
	     !m_rsToPQ_full && m_pRqMshr$RDY_sendRsToP_pRq_releaseEntry &&
	     m_rsToPIndexQ$EMPTY_N &&
	     m_rsToPIndexQ$D_OUT[3] ;
  assign WILL_FIRE_RL_m_sendRsToP_pRq = CAN_FIRE_RL_m_sendRsToP_pRq ;

  // rule RL_m_pRqTransfer
  assign CAN_FIRE_RL_m_pRqTransfer =
	     !m_fromPQ_empty && m_pipeline$RDY_send &&
	     m_pRqMshr$RDY_getEmptyEntryInit &&
	     CASE_m_fromPQ_deqP_0_NOT_m_fromPQ_data_0_BIT_5_ETC__q26 ;
  assign WILL_FIRE_RL_m_pRqTransfer = CAN_FIRE_RL_m_pRqTransfer ;

  // rule RL_m_rqIndexFromPipelineResp
  assign CAN_FIRE_RL_m_rqIndexFromPipelineResp =
	     m_rqToPIndexQ_pipelineResp$EMPTY_N && m_rqToPIndexQ$FULL_N ;
  assign WILL_FIRE_RL_m_rqIndexFromPipelineResp =
	     CAN_FIRE_RL_m_rqIndexFromPipelineResp ;

  // rule RL_m_rqIndexFromSendRsToP
  assign CAN_FIRE_RL_m_rqIndexFromSendRsToP =
	     m_rqToPIndexQ$FULL_N && m_rqToPIndexQ_sendRsToP$EMPTY_N ;
  assign WILL_FIRE_RL_m_rqIndexFromSendRsToP =
	     CAN_FIRE_RL_m_rqIndexFromSendRsToP &&
	     !WILL_FIRE_RL_m_rqIndexFromPipelineResp ;

  // rule RL_m_rqFromCQ_data_0_canon
  assign CAN_FIRE_RL_m_rqFromCQ_data_0_canon = 1'd1 ;
  assign WILL_FIRE_RL_m_rqFromCQ_data_0_canon = 1'd1 ;

  // rule RL_m_rqFromCQ_empty_canon
  assign CAN_FIRE_RL_m_rqFromCQ_empty_canon = 1'd1 ;
  assign WILL_FIRE_RL_m_rqFromCQ_empty_canon = 1'd1 ;

  // rule RL_m_rqFromCQ_full_canon
  assign CAN_FIRE_RL_m_rqFromCQ_full_canon = 1'd1 ;
  assign WILL_FIRE_RL_m_rqFromCQ_full_canon = 1'd1 ;

  // rule RL_m_rsToPQ_canonicalize
  assign CAN_FIRE_RL_m_rsToPQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_m_rsToPQ_canonicalize = 1'd1 ;

  // rule RL_m_rsToPQ_enqReq_canon
  assign CAN_FIRE_RL_m_rsToPQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_m_rsToPQ_enqReq_canon = 1'd1 ;

  // rule RL_m_rsToPQ_deqReq_canon
  assign CAN_FIRE_RL_m_rsToPQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_m_rsToPQ_deqReq_canon = 1'd1 ;

  // rule RL_m_rsToPQ_clearReq_canon
  assign CAN_FIRE_RL_m_rsToPQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_m_rsToPQ_clearReq_canon = 1'd1 ;

  // rule RL_m_rqToPQ_canonicalize
  assign CAN_FIRE_RL_m_rqToPQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_m_rqToPQ_canonicalize = 1'd1 ;

  // rule RL_m_rqToPQ_enqReq_canon
  assign CAN_FIRE_RL_m_rqToPQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_m_rqToPQ_enqReq_canon = 1'd1 ;

  // rule RL_m_rqToPQ_deqReq_canon
  assign CAN_FIRE_RL_m_rqToPQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_m_rqToPQ_deqReq_canon = 1'd1 ;

  // rule RL_m_rqToPQ_clearReq_canon
  assign CAN_FIRE_RL_m_rqToPQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_m_rqToPQ_clearReq_canon = 1'd1 ;

  // rule RL_m_fromPQ_canonicalize
  assign CAN_FIRE_RL_m_fromPQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_m_fromPQ_canonicalize = 1'd1 ;

  // rule RL_m_fromPQ_enqReq_canon
  assign CAN_FIRE_RL_m_fromPQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_m_fromPQ_enqReq_canon = 1'd1 ;

  // rule RL_m_fromPQ_deqReq_canon
  assign CAN_FIRE_RL_m_fromPQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_m_fromPQ_deqReq_canon = 1'd1 ;

  // rule RL_m_fromPQ_clearReq_canon
  assign CAN_FIRE_RL_m_fromPQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_m_fromPQ_clearReq_canon = 1'd1 ;

  // inputs to muxes for submodule ports
  assign MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1 =
	     WILL_FIRE_RL_m_pipelineResp_pRs && m_pipeline$first[515] ;
  assign MUX_m_rsToPIndexQ$enq_1__SEL_1 =
	     WILL_FIRE_RL_m_pipelineResp_cRq && !m_pipeline$first[515] &&
	     !m_cRqMshr$pipelineResp_searchEndOfChain[3] &&
	     m_pipeline$first[517:516] != 2'd0 &&
	     !m_pipeline_first__73_BITS_569_TO_518_86_EQ_m_c_ETC___d588 ;
  assign MUX_m_rsToPIndexQ$enq_1__SEL_2 =
	     WILL_FIRE_RL_m_pipelineResp_pRq && !m_pipeline$first[570] ;
  assign MUX_m_cRqMshr$pipelineResp_setResult_2__VAL_1 =
	     { 4'd15 - m_cRqMshr$pipelineResp_getRq[5:2] != 4'd0,
	       CASE_sel1386_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q28,
	       1'd1,
	       CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q29 } ;
  assign MUX_m_cRqMshr$pipelineResp_setStateSlot_2__VAL_2 =
	     m_pipeline$first[515] ?
	       (m_pipeline_first__73_BITS_514_TO_512_78_EQ_m_p_ETC___d600 ?
		  3'd3 :
		  3'd4) :
	       IF_m_cRqMshr_pipelineResp_searchEndOfChain_m_c_ETC___d641 ;
  assign MUX_m_cRqMshr$pipelineResp_setStateSlot_3__VAL_2 =
	     m_pipeline$first[515] ?
	       56'h55555555555554 :
	       (m_cRqMshr$pipelineResp_searchEndOfChain[3] ?
		  56'h55555555555554 :
		  ((m_pipeline$first[517:516] == 2'd0 ||
		    m_pipeline_first__73_BITS_569_TO_518_86_EQ_m_c_ETC___d588) ?
		     { m_pipeline$first[573:571], 53'h15555555555555 } :
		     { m_pipeline$first[573:571],
		       m_pipeline$first[569:518],
		       1'd1 })) ;
  assign MUX_m_pipeline$deqWrite_1__VAL_2 =
	     m_pipeline$first[515] ?
	       { m_pipeline_first__73_BITS_514_TO_512_78_EQ_m_p_ETC___d600 &&
		 m_cRqMshr$pipelineResp_getSucc[3],
		 m_cRqMshr$pipelineResp_getSucc[2:0] } :
	       { !m_cRqMshr$pipelineResp_searchEndOfChain[3] &&
		 m_pipeline_first__73_BITS_569_TO_518_86_EQ_m_c_ETC___d588 &&
		 m_pipeline$first[517:516] != 2'd0 &&
		 m_cRqMshr$pipelineResp_getSucc[3],
		 m_cRqMshr$pipelineResp_getSucc[2:0] } ;
  assign MUX_m_pipeline$deqWrite_2__VAL_1 =
	     { m_cRqMshr$pipelineResp_getRq[63:12],
	       m_pipeline$first[517:516],
	       m_cRqMshr$pipelineResp_getSucc,
	       m_pipeline$first[511:0] } ;
  assign MUX_m_pipeline$deqWrite_2__VAL_2 =
	     { m_pipeline$first[515] ?
		 IF_m_pipeline_first__73_BITS_514_TO_512_78_EQ__ETC___d621 :
		 IF_m_cRqMshr_pipelineResp_searchEndOfChain_m_c_ETC___d628,
	       m_pipeline$first[511:0] } ;
  assign MUX_m_pipeline$deqWrite_2__VAL_3 =
	     m_pipeline$first[570] ?
	       m_pipeline$first[569:0] :
	       { m_pipeline$first[569:518],
		 518'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
  assign MUX_m_pipeline$deqWrite_3__VAL_2 =
	     m_pipeline$first[515] ?
	       m_pipeline_first__73_BITS_514_TO_512_78_EQ_m_p_ETC___d600 :
	       !m_cRqMshr$pipelineResp_searchEndOfChain[3] &&
	       m_pipeline_first__73_BITS_569_TO_518_86_EQ_m_c_ETC___d588 &&
	       m_pipeline$first[517:516] != 2'd0 ;
  assign MUX_m_pipeline$send_1__VAL_1 =
	     { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
	       v__h43566,
	       m_cRqMshr$getEmptyEntryInit } ;
  assign MUX_m_pipeline$send_1__VAL_2 =
	     { 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
	       SEL_ARR_m_fromPQ_data_0_57_BITS_65_TO_2_66_m_f_ETC___d469,
	       m_pRqMshr$getEmptyEntryInit } ;
  assign MUX_m_pipeline$send_1__VAL_3 =
	     { 2'd2,
	       addr__h46129,
	       _1_CONCAT_NOT_SEL_ARR_NOT_m_fromPQ_data_0_57_BI_ETC___d535 } ;
  assign MUX_m_rsToPIndexQ$enq_1__VAL_1 =
	     { 1'd0, m_pipeline$first[576:574] } ;
  assign MUX_m_rsToPIndexQ$enq_1__VAL_2 =
	     { 1'd1, m_pipeline$first[576:574] } ;
  assign MUX_m_rsToPQ_enqReq_lat_0$wset_1__VAL_1 =
	     { 1'd1,
	       resp_addr__h47838,
	       515'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
  assign MUX_m_rsToPQ_enqReq_lat_0$wset_1__VAL_2 =
	     { 1'd1,
	       m_pRqMshr$sendRsToP_pRq_getRq[65:2],
	       515'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;

  // inlined wires
  assign m_rsToPQ_enqReq_lat_0$wget =
	     WILL_FIRE_RL_m_sendRsToP_cRq ?
	       MUX_m_rsToPQ_enqReq_lat_0$wset_1__VAL_1 :
	       MUX_m_rsToPQ_enqReq_lat_0$wset_1__VAL_2 ;
  assign m_rsToPQ_enqReq_lat_0$whas =
	     WILL_FIRE_RL_m_sendRsToP_cRq || WILL_FIRE_RL_m_sendRsToP_pRq ;
  assign m_rqToPQ_enqReq_lat_0$wget =
	     { 1'd1,
	       m_cRqMshr$sendRqToP_getRq,
	       5'd2,
	       m_cRqMshr$sendRqToP_getSlot[55:53] } ;
  assign m_fromPQ_enqReq_lat_0$wget = { 1'd1, to_parent_fromP_enq_x } ;
  assign m_fromPQ_deqReq_lat_0$whas =
	     WILL_FIRE_RL_m_pRsTransfer || WILL_FIRE_RL_m_pRqTransfer ;

  // register m_fromPQ_clearReq_rl
  assign m_fromPQ_clearReq_rl$D_IN = 1'd0 ;
  assign m_fromPQ_clearReq_rl$EN = 1'd1 ;

  // register m_fromPQ_data_0
  assign m_fromPQ_data_0$D_IN =
	     { !m_fromPQ_enqReq_dummy2_2$Q_OUT ||
	       IF_m_fromPQ_enqReq_lat_1_whas__63_THEN_NOT_m_f_ETC___d279 ||
	       (EN_to_parent_fromP_enq ?
		  m_fromPQ_enqReq_lat_0$wget[582] :
		  m_fromPQ_enqReq_rl[582]),
	       IF_m_fromPQ_enqReq_dummy2_2_read__75_AND_IF_m__ETC___d428 } ;
  assign m_fromPQ_data_0$EN =
	     m_fromPQ_enqP == 1'd0 &&
	     NOT_m_fromPQ_clearReq_dummy2_1_read__69_70_OR__ETC___d374 &&
	     m_fromPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_m_fromPQ_enqReq_lat_1_whas__63_THEN_m_fromP_ETC___d272 ;

  // register m_fromPQ_data_1
  assign m_fromPQ_data_1$D_IN = m_fromPQ_data_0$D_IN ;
  assign m_fromPQ_data_1$EN =
	     m_fromPQ_enqP == 1'd1 &&
	     NOT_m_fromPQ_clearReq_dummy2_1_read__69_70_OR__ETC___d374 &&
	     m_fromPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_m_fromPQ_enqReq_lat_1_whas__63_THEN_m_fromP_ETC___d272 ;

  // register m_fromPQ_deqP
  assign m_fromPQ_deqP$D_IN =
	     NOT_m_fromPQ_clearReq_dummy2_1_read__69_70_OR__ETC___d374 &&
	     _theResult_____2__h41332 ;
  assign m_fromPQ_deqP$EN = 1'd1 ;

  // register m_fromPQ_deqReq_rl
  assign m_fromPQ_deqReq_rl$D_IN = 1'd0 ;
  assign m_fromPQ_deqReq_rl$EN = 1'd1 ;

  // register m_fromPQ_empty
  assign m_fromPQ_empty$D_IN =
	     m_fromPQ_clearReq_dummy2_1$Q_OUT && m_fromPQ_clearReq_rl ||
	     IF_m_fromPQ_deqReq_dummy2_2_read__83_AND_IF_m__ETC___d391 &&
	     NOT_m_fromPQ_enqReq_dummy2_2_read__75_05_OR_IF_ETC___d409 ;
  assign m_fromPQ_empty$EN = 1'd1 ;

  // register m_fromPQ_enqP
  assign m_fromPQ_enqP$D_IN =
	     NOT_m_fromPQ_clearReq_dummy2_1_read__69_70_OR__ETC___d374 &&
	     v__h36262 ;
  assign m_fromPQ_enqP$EN = 1'd1 ;

  // register m_fromPQ_enqReq_rl
  assign m_fromPQ_enqReq_rl$D_IN =
	     584'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
  assign m_fromPQ_enqReq_rl$EN = 1'd1 ;

  // register m_fromPQ_full
  assign m_fromPQ_full$D_IN =
	     NOT_m_fromPQ_clearReq_dummy2_1_read__69_70_OR__ETC___d374 &&
	     IF_m_fromPQ_deqReq_dummy2_2_read__83_AND_IF_m__ETC___d391 &&
	     m_fromPQ_enqReq_dummy2_2_read__75_AND_IF_m_fro_ETC___d401 ;
  assign m_fromPQ_full$EN = 1'd1 ;

  // register m_rqFromCQ_data_0_rl
  assign m_rqFromCQ_data_0_rl$D_IN =
	     IF_m_rqFromCQ_data_0_lat_0_whas_THEN_m_rqFromC_ETC___d6 ;
  assign m_rqFromCQ_data_0_rl$EN = 1'd1 ;

  // register m_rqFromCQ_empty_rl
  assign m_rqFromCQ_empty_rl$D_IN =
	     WILL_FIRE_RL_m_cRqTransfer ||
	     !EN_to_proc_req_put && m_rqFromCQ_empty_rl ;
  assign m_rqFromCQ_empty_rl$EN = 1'd1 ;

  // register m_rqFromCQ_full_rl
  assign m_rqFromCQ_full_rl$D_IN =
	     !WILL_FIRE_RL_m_cRqTransfer &&
	     (EN_to_proc_req_put || m_rqFromCQ_full_rl) ;
  assign m_rqFromCQ_full_rl$EN = 1'd1 ;

  // register m_rqToPQ_clearReq_rl
  assign m_rqToPQ_clearReq_rl$D_IN = 1'd0 ;
  assign m_rqToPQ_clearReq_rl$EN = 1'd1 ;

  // register m_rqToPQ_data_0
  assign m_rqToPQ_data_0$D_IN =
	     CAN_FIRE_RL_m_sendRqToP ?
	       m_rqToPQ_enqReq_lat_0$wget[71:0] :
	       m_rqToPQ_enqReq_rl[71:0] ;
  assign m_rqToPQ_data_0$EN =
	     m_rqToPQ_enqP == 1'd0 &&
	     NOT_m_rqToPQ_clearReq_dummy2_1_read__10_11_OR__ETC___d215 &&
	     m_rqToPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_m_rqToPQ_enqReq_lat_1_whas__66_THEN_m_rqToP_ETC___d175 ;

  // register m_rqToPQ_data_1
  assign m_rqToPQ_data_1$D_IN =
	     CAN_FIRE_RL_m_sendRqToP ?
	       m_rqToPQ_enqReq_lat_0$wget[71:0] :
	       m_rqToPQ_enqReq_rl[71:0] ;
  assign m_rqToPQ_data_1$EN =
	     m_rqToPQ_enqP == 1'd1 &&
	     NOT_m_rqToPQ_clearReq_dummy2_1_read__10_11_OR__ETC___d215 &&
	     m_rqToPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_m_rqToPQ_enqReq_lat_1_whas__66_THEN_m_rqToP_ETC___d175 ;

  // register m_rqToPQ_deqP
  assign m_rqToPQ_deqP$D_IN =
	     NOT_m_rqToPQ_clearReq_dummy2_1_read__10_11_OR__ETC___d215 &&
	     _theResult_____2__h26689 ;
  assign m_rqToPQ_deqP$EN = 1'd1 ;

  // register m_rqToPQ_deqReq_rl
  assign m_rqToPQ_deqReq_rl$D_IN = 1'd0 ;
  assign m_rqToPQ_deqReq_rl$EN = 1'd1 ;

  // register m_rqToPQ_empty
  assign m_rqToPQ_empty$D_IN =
	     m_rqToPQ_clearReq_dummy2_1$Q_OUT && m_rqToPQ_clearReq_rl ||
	     IF_m_rqToPQ_deqReq_dummy2_2_read__24_AND_IF_m__ETC___d232 &&
	     NOT_m_rqToPQ_enqReq_dummy2_2_read__16_46_OR_IF_ETC___d250 ;
  assign m_rqToPQ_empty$EN = 1'd1 ;

  // register m_rqToPQ_enqP
  assign m_rqToPQ_enqP$D_IN =
	     NOT_m_rqToPQ_clearReq_dummy2_1_read__10_11_OR__ETC___d215 &&
	     v__h25933 ;
  assign m_rqToPQ_enqP$EN = 1'd1 ;

  // register m_rqToPQ_enqReq_rl
  assign m_rqToPQ_enqReq_rl$D_IN = 73'h0AAAAAAAAAAAAAAAAAA ;
  assign m_rqToPQ_enqReq_rl$EN = 1'd1 ;

  // register m_rqToPQ_full
  assign m_rqToPQ_full$D_IN =
	     NOT_m_rqToPQ_clearReq_dummy2_1_read__10_11_OR__ETC___d215 &&
	     IF_m_rqToPQ_deqReq_dummy2_2_read__24_AND_IF_m__ETC___d232 &&
	     m_rqToPQ_enqReq_dummy2_2_read__16_AND_IF_m_rqT_ETC___d242 ;
  assign m_rqToPQ_full$EN = 1'd1 ;

  // register m_rsToPQ_clearReq_rl
  assign m_rsToPQ_clearReq_rl$D_IN = 1'd0 ;
  assign m_rsToPQ_clearReq_rl$EN = 1'd1 ;

  // register m_rsToPQ_data_0
  assign m_rsToPQ_data_0$D_IN =
	     { x_addr__h14493,
	       m_rsToPQ_enqReq_lat_0$whas ?
		 m_rsToPQ_enqReq_lat_0$wget[514:513] :
		 m_rsToPQ_enqReq_rl[514:513],
	       !m_rsToPQ_enqReq_dummy2_2$Q_OUT ||
	       IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_NOT_m_rs_ETC___d47 ||
	       (m_rsToPQ_enqReq_lat_0$whas ?
		  m_rsToPQ_enqReq_lat_0$wget[512] :
		  m_rsToPQ_enqReq_rl[512]),
	       m_rsToPQ_enqReq_lat_0$whas ?
		 m_rsToPQ_enqReq_lat_0$wget[511:0] :
		 m_rsToPQ_enqReq_rl[511:0] } ;
  assign m_rsToPQ_data_0$EN =
	     m_rsToPQ_enqP == 1'd0 &&
	     NOT_m_rsToPQ_clearReq_dummy2_1_read__06_07_OR__ETC___d111 &&
	     m_rsToPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d40 ;

  // register m_rsToPQ_data_1
  assign m_rsToPQ_data_1$D_IN = m_rsToPQ_data_0$D_IN ;
  assign m_rsToPQ_data_1$EN =
	     m_rsToPQ_enqP == 1'd1 &&
	     NOT_m_rsToPQ_clearReq_dummy2_1_read__06_07_OR__ETC___d111 &&
	     m_rsToPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d40 ;

  // register m_rsToPQ_deqP
  assign m_rsToPQ_deqP$D_IN =
	     NOT_m_rsToPQ_clearReq_dummy2_1_read__06_07_OR__ETC___d111 &&
	     _theResult_____2__h18784 ;
  assign m_rsToPQ_deqP$EN = 1'd1 ;

  // register m_rsToPQ_deqReq_rl
  assign m_rsToPQ_deqReq_rl$D_IN = 1'd0 ;
  assign m_rsToPQ_deqReq_rl$EN = 1'd1 ;

  // register m_rsToPQ_empty
  assign m_rsToPQ_empty$D_IN =
	     m_rsToPQ_clearReq_dummy2_1$Q_OUT && m_rsToPQ_clearReq_rl ||
	     IF_m_rsToPQ_deqReq_dummy2_2_read__20_AND_IF_m__ETC___d128 &&
	     NOT_m_rsToPQ_enqReq_dummy2_2_read__12_42_OR_IF_ETC___d146 ;
  assign m_rsToPQ_empty$EN = 1'd1 ;

  // register m_rsToPQ_enqP
  assign m_rsToPQ_enqP$D_IN =
	     NOT_m_rsToPQ_clearReq_dummy2_1_read__06_07_OR__ETC___d111 &&
	     v__h14050 ;
  assign m_rsToPQ_enqP$EN = 1'd1 ;

  // register m_rsToPQ_enqReq_rl
  assign m_rsToPQ_enqReq_rl$D_IN =
	     580'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
  assign m_rsToPQ_enqReq_rl$EN = 1'd1 ;

  // register m_rsToPQ_full
  assign m_rsToPQ_full$D_IN =
	     NOT_m_rsToPQ_clearReq_dummy2_1_read__06_07_OR__ETC___d111 &&
	     IF_m_rsToPQ_deqReq_dummy2_2_read__20_AND_IF_m__ETC___d128 &&
	     m_rsToPQ_enqReq_dummy2_2_read__12_AND_IF_m_rsT_ETC___d138 ;
  assign m_rsToPQ_full$EN = 1'd1 ;

  // submodule m_cRqIndexQ
  assign m_cRqIndexQ$D_IN = m_cRqMshr$getEmptyEntryInit ;
  assign m_cRqIndexQ$ENQ = WILL_FIRE_RL_m_cRqTransfer ;
  assign m_cRqIndexQ$DEQ = EN_to_proc_resp_get ;
  assign m_cRqIndexQ$CLR = 1'b0 ;

  // submodule m_cRqMshr
  assign m_cRqMshr$getEmptyEntryInit_r = v__h43566 ;
  assign m_cRqMshr$pipelineResp_getRq_n =
	     (m_pipeline$first[578:577] == 2'd0) ?
	       m_pipeline$first[576:574] :
	       (m_pipeline$first[515] ? m_pipeline$first[514:512] : 3'd0) ;
  assign m_cRqMshr$pipelineResp_getSlot_n = 3'h0 ;
  assign m_cRqMshr$pipelineResp_getState_n = 3'h0 ;
  assign m_cRqMshr$pipelineResp_getSucc_n =
	     WILL_FIRE_RL_m_pipelineResp_pRs ?
	       m_pipeline$first[514:512] :
	       m_pipeline$first[576:574] ;
  assign m_cRqMshr$pipelineResp_searchEndOfChain_addr =
	     m_cRqMshr$pipelineResp_getRq ;
  assign m_cRqMshr$pipelineResp_setResult_n =
	     MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1 ?
	       m_pipeline$first[514:512] :
	       m_pipeline$first[576:574] ;
  assign m_cRqMshr$pipelineResp_setResult_r =
	     MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1 ?
	       MUX_m_cRqMshr$pipelineResp_setResult_2__VAL_1 :
	       MUX_m_cRqMshr$pipelineResp_setResult_2__VAL_1 ;
  assign m_cRqMshr$pipelineResp_setStateSlot_n =
	     MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1 ?
	       m_pipeline$first[514:512] :
	       m_pipeline$first[576:574] ;
  assign m_cRqMshr$pipelineResp_setStateSlot_slot =
	     MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1 ?
	       56'hAAAAAAAAAAAAAA /* unspecified value */  :
	       MUX_m_cRqMshr$pipelineResp_setStateSlot_3__VAL_2 ;
  assign m_cRqMshr$pipelineResp_setStateSlot_state =
	     MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1 ?
	       3'd3 :
	       MUX_m_cRqMshr$pipelineResp_setStateSlot_2__VAL_2 ;
  assign m_cRqMshr$pipelineResp_setSucc_n =
	     m_cRqMshr$pipelineResp_searchEndOfChain[2:0] ;
  assign m_cRqMshr$pipelineResp_setSucc_succ =
	     MUX_m_rsToPIndexQ$enq_1__VAL_2 ;
  assign m_cRqMshr$sendRqToP_getRq_n = m_rqToPIndexQ$D_OUT ;
  assign m_cRqMshr$sendRqToP_getSlot_n = m_rqToPIndexQ$D_OUT ;
  assign m_cRqMshr$sendRsToC_getResult_n = m_cRqIndexQ$D_OUT ;
  assign m_cRqMshr$sendRsToC_releaseEntry_n = m_cRqIndexQ$D_OUT ;
  assign m_cRqMshr$sendRsToP_cRq_getRq_n = m_rsToPIndexQ$D_OUT[2:0] ;
  assign m_cRqMshr$sendRsToP_cRq_getSlot_n = m_rsToPIndexQ$D_OUT[2:0] ;
  assign m_cRqMshr$EN_getEmptyEntryInit = WILL_FIRE_RL_m_cRqTransfer ;
  assign m_cRqMshr$EN_sendRsToC_releaseEntry = EN_to_proc_resp_get ;
  assign m_cRqMshr$EN_pipelineResp_setResult =
	     WILL_FIRE_RL_m_pipelineResp_pRs && m_pipeline$first[515] ||
	     WILL_FIRE_RL_m_pipelineResp_cRq &&
	     m_pipeline_first__73_BIT_515_74_AND_m_pipeline_ETC___d657 ;
  assign m_cRqMshr$EN_pipelineResp_setStateSlot =
	     WILL_FIRE_RL_m_pipelineResp_pRs && m_pipeline$first[515] ||
	     WILL_FIRE_RL_m_pipelineResp_cRq ;
  assign m_cRqMshr$EN_pipelineResp_setSucc =
	     WILL_FIRE_RL_m_pipelineResp_cRq &&
	     (m_pipeline$first[515] &&
	      !m_pipeline_first__73_BITS_514_TO_512_78_EQ_m_p_ETC___d600 ||
	      !m_pipeline$first[515] &&
	      m_cRqMshr$pipelineResp_searchEndOfChain[3]) ;
  assign m_cRqMshr$EN_stuck_get = EN_cRqStuck_get ;

  // submodule m_fromPQ_clearReq_dummy2_0
  assign m_fromPQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign m_fromPQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule m_fromPQ_clearReq_dummy2_1
  assign m_fromPQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign m_fromPQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule m_fromPQ_deqReq_dummy2_0
  assign m_fromPQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign m_fromPQ_deqReq_dummy2_0$EN = m_fromPQ_deqReq_lat_0$whas ;

  // submodule m_fromPQ_deqReq_dummy2_1
  assign m_fromPQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign m_fromPQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule m_fromPQ_deqReq_dummy2_2
  assign m_fromPQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign m_fromPQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule m_fromPQ_enqReq_dummy2_0
  assign m_fromPQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign m_fromPQ_enqReq_dummy2_0$EN = EN_to_parent_fromP_enq ;

  // submodule m_fromPQ_enqReq_dummy2_1
  assign m_fromPQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign m_fromPQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule m_fromPQ_enqReq_dummy2_2
  assign m_fromPQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign m_fromPQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule m_pRqMshr
  assign m_pRqMshr$getEmptyEntryInit_r =
	     { SEL_ARR_m_fromPQ_data_0_57_BITS_65_TO_2_66_m_f_ETC___d469,
	       CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_1_TO_ETC__q30 } ;
  assign m_pRqMshr$pipelineResp_getRq_n = 2'h0 ;
  assign m_pRqMshr$pipelineResp_releaseEntry_n = m_pipeline$first[575:574] ;
  assign m_pRqMshr$pipelineResp_setDone_n = m_pipeline$first[575:574] ;
  assign m_pRqMshr$sendRsToP_pRq_getRq_n = m_rsToPIndexQ$D_OUT[1:0] ;
  assign m_pRqMshr$sendRsToP_pRq_releaseEntry_n = m_rsToPIndexQ$D_OUT[1:0] ;
  assign m_pRqMshr$EN_getEmptyEntryInit = CAN_FIRE_RL_m_pRqTransfer ;
  assign m_pRqMshr$EN_sendRsToP_pRq_releaseEntry =
	     CAN_FIRE_RL_m_sendRsToP_pRq ;
  assign m_pRqMshr$EN_pipelineResp_releaseEntry =
	     WILL_FIRE_RL_m_pipelineResp_pRq && m_pipeline$first[570] ;
  assign m_pRqMshr$EN_pipelineResp_setDone = MUX_m_rsToPIndexQ$enq_1__SEL_2 ;
  assign m_pRqMshr$EN_stuck_get = EN_pRqStuck_get ;

  // submodule m_pipeline
  always@(MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1 or
	  m_cRqMshr$pipelineResp_getSucc or
	  WILL_FIRE_RL_m_pipelineResp_cRq or
	  MUX_m_pipeline$deqWrite_1__VAL_2 or WILL_FIRE_RL_m_pipelineResp_pRq)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1:
	  m_pipeline$deqWrite_swapRq = m_cRqMshr$pipelineResp_getSucc;
      WILL_FIRE_RL_m_pipelineResp_cRq:
	  m_pipeline$deqWrite_swapRq = MUX_m_pipeline$deqWrite_1__VAL_2;
      WILL_FIRE_RL_m_pipelineResp_pRq: m_pipeline$deqWrite_swapRq = 4'd2;
      default: m_pipeline$deqWrite_swapRq = 4'b1010 /* unspecified value */ ;
    endcase
  end
  always@(MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1 or
	  WILL_FIRE_RL_m_pipelineResp_cRq or
	  MUX_m_pipeline$deqWrite_3__VAL_2 or WILL_FIRE_RL_m_pipelineResp_pRq)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1:
	  m_pipeline$deqWrite_updateRep = 1'd1;
      WILL_FIRE_RL_m_pipelineResp_cRq:
	  m_pipeline$deqWrite_updateRep = MUX_m_pipeline$deqWrite_3__VAL_2;
      WILL_FIRE_RL_m_pipelineResp_pRq: m_pipeline$deqWrite_updateRep = 1'd0;
      default: m_pipeline$deqWrite_updateRep = 1'b0 /* unspecified value */ ;
    endcase
  end
  always@(MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1 or
	  MUX_m_pipeline$deqWrite_2__VAL_1 or
	  WILL_FIRE_RL_m_pipelineResp_cRq or
	  MUX_m_pipeline$deqWrite_2__VAL_2 or
	  WILL_FIRE_RL_m_pipelineResp_pRq or MUX_m_pipeline$deqWrite_2__VAL_3)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_m_cRqMshr$pipelineResp_setResult_1__SEL_1:
	  m_pipeline$deqWrite_wrRam = MUX_m_pipeline$deqWrite_2__VAL_1;
      WILL_FIRE_RL_m_pipelineResp_cRq:
	  m_pipeline$deqWrite_wrRam = MUX_m_pipeline$deqWrite_2__VAL_2;
      WILL_FIRE_RL_m_pipelineResp_pRq:
	  m_pipeline$deqWrite_wrRam = MUX_m_pipeline$deqWrite_2__VAL_3;
      default: m_pipeline$deqWrite_wrRam =
		   570'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  always@(WILL_FIRE_RL_m_cRqTransfer or
	  MUX_m_pipeline$send_1__VAL_1 or
	  WILL_FIRE_RL_m_pRqTransfer or
	  MUX_m_pipeline$send_1__VAL_2 or
	  WILL_FIRE_RL_m_pRsTransfer or MUX_m_pipeline$send_1__VAL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_m_cRqTransfer:
	  m_pipeline$send_r = MUX_m_pipeline$send_1__VAL_1;
      WILL_FIRE_RL_m_pRqTransfer:
	  m_pipeline$send_r = MUX_m_pipeline$send_1__VAL_2;
      WILL_FIRE_RL_m_pRsTransfer:
	  m_pipeline$send_r = MUX_m_pipeline$send_1__VAL_3;
      default: m_pipeline$send_r =
		   584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign m_pipeline$EN_send =
	     WILL_FIRE_RL_m_cRqTransfer || WILL_FIRE_RL_m_pRqTransfer ||
	     WILL_FIRE_RL_m_pRsTransfer ;
  assign m_pipeline$EN_deqWrite =
	     WILL_FIRE_RL_m_pipelineResp_pRs && m_pipeline$first[515] ||
	     WILL_FIRE_RL_m_pipelineResp_cRq ||
	     WILL_FIRE_RL_m_pipelineResp_pRq ;

  // submodule m_rqFromCQ_data_0_dummy2_0
  assign m_rqFromCQ_data_0_dummy2_0$D_IN = 1'd1 ;
  assign m_rqFromCQ_data_0_dummy2_0$EN = EN_to_proc_req_put ;

  // submodule m_rqFromCQ_data_0_dummy2_1
  assign m_rqFromCQ_data_0_dummy2_1$D_IN = 1'b0 ;
  assign m_rqFromCQ_data_0_dummy2_1$EN = 1'b0 ;

  // submodule m_rqFromCQ_deqP_dummy2_0
  assign m_rqFromCQ_deqP_dummy2_0$D_IN = 1'd1 ;
  assign m_rqFromCQ_deqP_dummy2_0$EN = WILL_FIRE_RL_m_cRqTransfer ;

  // submodule m_rqFromCQ_deqP_dummy2_1
  assign m_rqFromCQ_deqP_dummy2_1$D_IN = 1'b0 ;
  assign m_rqFromCQ_deqP_dummy2_1$EN = 1'b0 ;

  // submodule m_rqFromCQ_empty_dummy2_0
  assign m_rqFromCQ_empty_dummy2_0$D_IN = 1'd1 ;
  assign m_rqFromCQ_empty_dummy2_0$EN = EN_to_proc_req_put ;

  // submodule m_rqFromCQ_empty_dummy2_1
  assign m_rqFromCQ_empty_dummy2_1$D_IN = 1'd1 ;
  assign m_rqFromCQ_empty_dummy2_1$EN = WILL_FIRE_RL_m_cRqTransfer ;

  // submodule m_rqFromCQ_empty_dummy2_2
  assign m_rqFromCQ_empty_dummy2_2$D_IN = 1'b0 ;
  assign m_rqFromCQ_empty_dummy2_2$EN = 1'b0 ;

  // submodule m_rqFromCQ_enqP_dummy2_0
  assign m_rqFromCQ_enqP_dummy2_0$D_IN = 1'd1 ;
  assign m_rqFromCQ_enqP_dummy2_0$EN = EN_to_proc_req_put ;

  // submodule m_rqFromCQ_enqP_dummy2_1
  assign m_rqFromCQ_enqP_dummy2_1$D_IN = 1'b0 ;
  assign m_rqFromCQ_enqP_dummy2_1$EN = 1'b0 ;

  // submodule m_rqFromCQ_full_dummy2_0
  assign m_rqFromCQ_full_dummy2_0$D_IN = 1'd1 ;
  assign m_rqFromCQ_full_dummy2_0$EN = EN_to_proc_req_put ;

  // submodule m_rqFromCQ_full_dummy2_1
  assign m_rqFromCQ_full_dummy2_1$D_IN = 1'd1 ;
  assign m_rqFromCQ_full_dummy2_1$EN = WILL_FIRE_RL_m_cRqTransfer ;

  // submodule m_rqFromCQ_full_dummy2_2
  assign m_rqFromCQ_full_dummy2_2$D_IN = 1'b0 ;
  assign m_rqFromCQ_full_dummy2_2$EN = 1'b0 ;

  // submodule m_rqToPIndexQ
  assign m_rqToPIndexQ$D_IN =
	     WILL_FIRE_RL_m_rqIndexFromPipelineResp ?
	       m_rqToPIndexQ_pipelineResp$D_OUT :
	       m_rqToPIndexQ_sendRsToP$D_OUT ;
  assign m_rqToPIndexQ$ENQ =
	     WILL_FIRE_RL_m_rqIndexFromPipelineResp ||
	     WILL_FIRE_RL_m_rqIndexFromSendRsToP ;
  assign m_rqToPIndexQ$DEQ = CAN_FIRE_RL_m_sendRqToP ;
  assign m_rqToPIndexQ$CLR = 1'b0 ;

  // submodule m_rqToPIndexQ_pipelineResp
  assign m_rqToPIndexQ_pipelineResp$D_IN = m_pipeline$first[576:574] ;
  assign m_rqToPIndexQ_pipelineResp$ENQ =
	     WILL_FIRE_RL_m_pipelineResp_cRq && !m_pipeline$first[515] &&
	     !m_cRqMshr$pipelineResp_searchEndOfChain[3] &&
	     m_pipeline$first[517:516] == 2'd0 ;
  assign m_rqToPIndexQ_pipelineResp$DEQ =
	     CAN_FIRE_RL_m_rqIndexFromPipelineResp ;
  assign m_rqToPIndexQ_pipelineResp$CLR = 1'b0 ;

  // submodule m_rqToPIndexQ_sendRsToP
  assign m_rqToPIndexQ_sendRsToP$D_IN = m_rsToPIndexQ$D_OUT[2:0] ;
  assign m_rqToPIndexQ_sendRsToP$ENQ = CAN_FIRE_RL_m_sendRsToP_cRq ;
  assign m_rqToPIndexQ_sendRsToP$DEQ = WILL_FIRE_RL_m_rqIndexFromSendRsToP ;
  assign m_rqToPIndexQ_sendRsToP$CLR = 1'b0 ;

  // submodule m_rqToPQ_clearReq_dummy2_0
  assign m_rqToPQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign m_rqToPQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule m_rqToPQ_clearReq_dummy2_1
  assign m_rqToPQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign m_rqToPQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule m_rqToPQ_deqReq_dummy2_0
  assign m_rqToPQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign m_rqToPQ_deqReq_dummy2_0$EN = EN_to_parent_rqToP_deq ;

  // submodule m_rqToPQ_deqReq_dummy2_1
  assign m_rqToPQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign m_rqToPQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule m_rqToPQ_deqReq_dummy2_2
  assign m_rqToPQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign m_rqToPQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule m_rqToPQ_enqReq_dummy2_0
  assign m_rqToPQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign m_rqToPQ_enqReq_dummy2_0$EN = CAN_FIRE_RL_m_sendRqToP ;

  // submodule m_rqToPQ_enqReq_dummy2_1
  assign m_rqToPQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign m_rqToPQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule m_rqToPQ_enqReq_dummy2_2
  assign m_rqToPQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign m_rqToPQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule m_rsToPIndexQ
  assign m_rsToPIndexQ$D_IN =
	     MUX_m_rsToPIndexQ$enq_1__SEL_1 ?
	       MUX_m_rsToPIndexQ$enq_1__VAL_1 :
	       MUX_m_rsToPIndexQ$enq_1__VAL_2 ;
  assign m_rsToPIndexQ$ENQ =
	     WILL_FIRE_RL_m_pipelineResp_cRq && !m_pipeline$first[515] &&
	     !m_cRqMshr$pipelineResp_searchEndOfChain[3] &&
	     m_pipeline$first[517:516] != 2'd0 &&
	     !m_pipeline_first__73_BITS_569_TO_518_86_EQ_m_c_ETC___d588 ||
	     WILL_FIRE_RL_m_pipelineResp_pRq && !m_pipeline$first[570] ;
  assign m_rsToPIndexQ$DEQ =
	     WILL_FIRE_RL_m_sendRsToP_pRq || WILL_FIRE_RL_m_sendRsToP_cRq ;
  assign m_rsToPIndexQ$CLR = 1'b0 ;

  // submodule m_rsToPQ_clearReq_dummy2_0
  assign m_rsToPQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign m_rsToPQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule m_rsToPQ_clearReq_dummy2_1
  assign m_rsToPQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign m_rsToPQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule m_rsToPQ_deqReq_dummy2_0
  assign m_rsToPQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign m_rsToPQ_deqReq_dummy2_0$EN = EN_to_parent_rsToP_deq ;

  // submodule m_rsToPQ_deqReq_dummy2_1
  assign m_rsToPQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign m_rsToPQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule m_rsToPQ_deqReq_dummy2_2
  assign m_rsToPQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign m_rsToPQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule m_rsToPQ_enqReq_dummy2_0
  assign m_rsToPQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign m_rsToPQ_enqReq_dummy2_0$EN =
	     WILL_FIRE_RL_m_sendRsToP_pRq || WILL_FIRE_RL_m_sendRsToP_cRq ;

  // submodule m_rsToPQ_enqReq_dummy2_1
  assign m_rsToPQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign m_rsToPQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule m_rsToPQ_enqReq_dummy2_2
  assign m_rsToPQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign m_rsToPQ_enqReq_dummy2_2$EN = 1'd1 ;

  // remaining internal signals
  assign IF_m_cRqMshr_pipelineResp_searchEndOfChain_m_c_ETC___d628 =
	     m_cRqMshr$pipelineResp_searchEndOfChain[3] ?
	       m_pipeline$first[569:512] :
	       { m_cRqMshr$pipelineResp_getRq[63:12],
		 IF_m_pipeline_first__73_BITS_517_TO_516_84_EQ__ETC___d626 } ;
  assign IF_m_cRqMshr_pipelineResp_searchEndOfChain_m_c_ETC___d641 =
	     m_cRqMshr$pipelineResp_searchEndOfChain[3] ?
	       3'd4 :
	       ((m_pipeline$first[517:516] == 2'd0 ||
		 m_pipeline_first__73_BITS_569_TO_518_86_EQ_m_c_ETC___d588) ?
		  ((m_pipeline$first[517:516] == 2'd0) ? 3'd2 : 3'd3) :
		  3'd2) ;
  assign IF_m_fromPQ_deqReq_dummy2_2_read__83_AND_IF_m__ETC___d391 =
	     _theResult_____2__h41332 == v__h36262 ;
  assign IF_m_fromPQ_deqReq_lat_1_whas__54_THEN_m_fromP_ETC___d360 =
	     m_fromPQ_deqReq_lat_0$whas || m_fromPQ_deqReq_rl ;
  assign IF_m_fromPQ_enqReq_dummy2_2_read__75_AND_IF_m__ETC___d428 =
	     (m_fromPQ_enqReq_dummy2_2$Q_OUT &&
	      IF_m_fromPQ_enqReq_lat_1_whas__63_THEN_m_fromP_ETC___d272 &&
	      (EN_to_parent_fromP_enq ?
		 !m_fromPQ_enqReq_lat_0$wget[582] :
		 !m_fromPQ_enqReq_rl[582])) ?
	       { 516'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
		 EN_to_parent_fromP_enq ?
		   m_fromPQ_enqReq_lat_0$wget[65:0] :
		   m_fromPQ_enqReq_rl[65:0] } :
	       { EN_to_parent_fromP_enq ?
		   m_fromPQ_enqReq_lat_0$wget[581:518] :
		   m_fromPQ_enqReq_rl[581:518],
		 EN_to_parent_fromP_enq ?
		   m_fromPQ_enqReq_lat_0$wget[517:516] :
		   m_fromPQ_enqReq_rl[517:516],
		 !m_fromPQ_enqReq_dummy2_2$Q_OUT ||
		 IF_m_fromPQ_enqReq_lat_1_whas__63_THEN_NOT_m_f_ETC___d279 ||
		 (EN_to_parent_fromP_enq ?
		    m_fromPQ_enqReq_lat_0$wget[515] :
		    m_fromPQ_enqReq_rl[515]),
		 EN_to_parent_fromP_enq ?
		   m_fromPQ_enqReq_lat_0$wget[514:3] :
		   m_fromPQ_enqReq_rl[514:3],
		 x__h38966 } ;
  assign IF_m_fromPQ_enqReq_lat_1_whas__63_THEN_NOT_m_f_ETC___d279 =
	     EN_to_parent_fromP_enq ?
	       !m_fromPQ_enqReq_lat_0$wget[583] :
	       !m_fromPQ_enqReq_rl[583] ;
  assign IF_m_fromPQ_enqReq_lat_1_whas__63_THEN_m_fromP_ETC___d272 =
	     EN_to_parent_fromP_enq ?
	       m_fromPQ_enqReq_lat_0$wget[583] :
	       m_fromPQ_enqReq_rl[583] ;
  assign IF_m_pipeline_first__73_BITS_514_TO_512_78_EQ__ETC___d621 =
	     m_pipeline_first__73_BITS_514_TO_512_78_EQ_m_p_ETC___d600 ?
	       { m_cRqMshr$pipelineResp_getRq[63:12],
		 m_pipeline$first[517:516],
		 m_cRqMshr$pipelineResp_getSucc } :
	       m_pipeline$first[569:512] ;
  assign IF_m_pipeline_first__73_BITS_517_TO_516_84_EQ__ETC___d594 =
	     (m_pipeline$first[517:516] == 2'd0 ||
	      m_pipeline_first__73_BITS_569_TO_518_86_EQ_m_c_ETC___d588) ?
	       m_pipeline$first[517:516] != 2'd0 ||
	       m_rqToPIndexQ_pipelineResp$FULL_N :
	       m_rsToPIndexQ$FULL_N ;
  assign IF_m_pipeline_first__73_BITS_517_TO_516_84_EQ__ETC___d626 =
	     (m_pipeline$first[517:516] == 2'd0 ||
	      m_pipeline_first__73_BITS_569_TO_518_86_EQ_m_c_ETC___d588) ?
	       { m_pipeline$first[517:516],
		 m_pipeline$first[517:516] == 2'd0 ||
		 m_cRqMshr$pipelineResp_getSucc[3],
		 (m_pipeline$first[517:516] == 2'd0) ?
		   m_pipeline$first[576:574] :
		   m_cRqMshr$pipelineResp_getSucc[2:0] } :
	       { 3'd1, m_pipeline$first[576:574] } ;
  assign IF_m_rqFromCQ_data_0_lat_0_whas_THEN_m_rqFromC_ETC___d6 =
	     EN_to_proc_req_put ? to_proc_req_put : m_rqFromCQ_data_0_rl ;
  assign IF_m_rqToPQ_deqReq_dummy2_2_read__24_AND_IF_m__ETC___d232 =
	     _theResult_____2__h26689 == v__h25933 ;
  assign IF_m_rqToPQ_deqReq_lat_1_whas__95_THEN_m_rqToP_ETC___d201 =
	     EN_to_parent_rqToP_deq || m_rqToPQ_deqReq_rl ;
  assign IF_m_rqToPQ_enqReq_lat_1_whas__66_THEN_m_rqToP_ETC___d175 =
	     CAN_FIRE_RL_m_sendRqToP ?
	       m_rqToPQ_enqReq_lat_0$wget[72] :
	       m_rqToPQ_enqReq_rl[72] ;
  assign IF_m_rsToPQ_deqReq_dummy2_2_read__20_AND_IF_m__ETC___d128 =
	     _theResult_____2__h18784 == v__h14050 ;
  assign IF_m_rsToPQ_deqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d97 =
	     EN_to_parent_rsToP_deq || m_rsToPQ_deqReq_rl ;
  assign IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_NOT_m_rs_ETC___d47 =
	     m_rsToPQ_enqReq_lat_0$whas ?
	       !m_rsToPQ_enqReq_lat_0$wget[579] :
	       !m_rsToPQ_enqReq_rl[579] ;
  assign IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d40 =
	     m_rsToPQ_enqReq_lat_0$whas ?
	       m_rsToPQ_enqReq_lat_0$wget[579] :
	       m_rsToPQ_enqReq_rl[579] ;
  assign NOT_m_fromPQ_clearReq_dummy2_1_read__69_70_OR__ETC___d374 =
	     !m_fromPQ_clearReq_dummy2_1$Q_OUT || !m_fromPQ_clearReq_rl ;
  assign NOT_m_fromPQ_enqReq_dummy2_2_read__75_05_OR_IF_ETC___d409 =
	     (!m_fromPQ_enqReq_dummy2_2$Q_OUT ||
	      IF_m_fromPQ_enqReq_lat_1_whas__63_THEN_NOT_m_f_ETC___d279) &&
	     (m_fromPQ_deqReq_dummy2_2$Q_OUT &&
	      IF_m_fromPQ_deqReq_lat_1_whas__54_THEN_m_fromP_ETC___d360 ||
	      m_fromPQ_empty) ;
  assign NOT_m_rqToPQ_clearReq_dummy2_1_read__10_11_OR__ETC___d215 =
	     !m_rqToPQ_clearReq_dummy2_1$Q_OUT || !m_rqToPQ_clearReq_rl ;
  assign NOT_m_rqToPQ_enqReq_dummy2_2_read__16_46_OR_IF_ETC___d250 =
	     (!m_rqToPQ_enqReq_dummy2_2$Q_OUT ||
	      (CAN_FIRE_RL_m_sendRqToP ?
		 !m_rqToPQ_enqReq_lat_0$wget[72] :
		 !m_rqToPQ_enqReq_rl[72])) &&
	     (m_rqToPQ_deqReq_dummy2_2$Q_OUT &&
	      IF_m_rqToPQ_deqReq_lat_1_whas__95_THEN_m_rqToP_ETC___d201 ||
	      m_rqToPQ_empty) ;
  assign NOT_m_rsToPQ_clearReq_dummy2_1_read__06_07_OR__ETC___d111 =
	     !m_rsToPQ_clearReq_dummy2_1$Q_OUT || !m_rsToPQ_clearReq_rl ;
  assign NOT_m_rsToPQ_enqReq_dummy2_2_read__12_42_OR_IF_ETC___d146 =
	     (!m_rsToPQ_enqReq_dummy2_2$Q_OUT ||
	      IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_NOT_m_rs_ETC___d47) &&
	     (m_rsToPQ_deqReq_dummy2_2$Q_OUT &&
	      IF_m_rsToPQ_deqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d97 ||
	      m_rsToPQ_empty) ;
  assign SEL_ARR_m_fromPQ_data_0_57_BITS_514_TO_451_93__ETC___d510 =
	     { CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_514__ETC__q5,
	       CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_450__ETC__q6,
	       CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_386__ETC__q7,
	       CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_322__ETC__q8 } ;
  assign SEL_ARR_m_fromPQ_data_0_57_BITS_514_TO_451_93__ETC___d519 =
	     { SEL_ARR_m_fromPQ_data_0_57_BITS_514_TO_451_93__ETC___d510,
	       CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_258__ETC__q11,
	       CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_194__ETC__q12 } ;
  assign SEL_ARR_m_fromPQ_data_0_57_BITS_514_TO_451_93__ETC___d528 =
	     { SEL_ARR_m_fromPQ_data_0_57_BITS_514_TO_451_93__ETC___d519,
	       CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_130__ETC__q13,
	       CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_66_T_ETC__q14 } ;
  assign SEL_ARR_m_rqToPQ_data_0_92_BITS_5_TO_4_02_m_rq_ETC___d814 =
	     { CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_5_TO_ETC__q21,
	       CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BIT_3_1_m_ETC__q22,
	       CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_2_TO_ETC__q23 } ;
  assign SEL_ARR_m_rsToPQ_data_0_36_BITS_511_TO_448_53__ETC___d770 =
	     { CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_511__ETC__q1,
	       CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_447__ETC__q2,
	       CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_383__ETC__q3,
	       CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_319__ETC__q4 } ;
  assign SEL_ARR_m_rsToPQ_data_0_36_BITS_511_TO_448_53__ETC___d779 =
	     { SEL_ARR_m_rsToPQ_data_0_36_BITS_511_TO_448_53__ETC___d770,
	       CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_255__ETC__q9,
	       CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_191__ETC__q10 } ;
  assign SEL_ARR_m_rsToPQ_data_0_36_BITS_511_TO_448_53__ETC___d788 =
	     { SEL_ARR_m_rsToPQ_data_0_36_BITS_511_TO_448_53__ETC___d779,
	       CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_127__ETC__q15,
	       CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_63_T_ETC__q16 } ;
  assign _1_CONCAT_NOT_SEL_ARR_NOT_m_fromPQ_data_0_57_BI_ETC___d535 =
	     { 2'd1,
	       !CASE_m_fromPQ_deqP_0_NOT_m_fromPQ_data_0_BIT_5_ETC__q20,
	       SEL_ARR_m_fromPQ_data_0_57_BITS_514_TO_451_93__ETC___d528,
	       x__h47671 } ;
  assign _theResult_____2__h18784 =
	     (m_rsToPQ_deqReq_dummy2_2$Q_OUT &&
	      IF_m_rsToPQ_deqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d97) ?
	       next_deqP___1__h19103 :
	       m_rsToPQ_deqP ;
  assign _theResult_____2__h26689 =
	     (m_rqToPQ_deqReq_dummy2_2$Q_OUT &&
	      IF_m_rqToPQ_deqReq_lat_1_whas__95_THEN_m_rqToP_ETC___d201) ?
	       next_deqP___1__h27008 :
	       m_rqToPQ_deqP ;
  assign _theResult_____2__h41332 =
	     (m_fromPQ_deqReq_dummy2_2$Q_OUT &&
	      IF_m_fromPQ_deqReq_lat_1_whas__54_THEN_m_fromP_ETC___d360) ?
	       next_deqP___1__h41651 :
	       m_fromPQ_deqP ;
  assign m_fromPQ_enqReq_dummy2_2_read__75_AND_IF_m_fro_ETC___d401 =
	     m_fromPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_m_fromPQ_enqReq_lat_1_whas__63_THEN_m_fromP_ETC___d272 ||
	     (!m_fromPQ_deqReq_dummy2_2$Q_OUT ||
	      !m_fromPQ_deqReq_lat_0$whas && !m_fromPQ_deqReq_rl) &&
	     m_fromPQ_full ;
  assign m_pipeline_RDY_deqWrite__72_AND_IF_m_pipeline__ETC___d716 =
	     m_pipeline$RDY_deqWrite &&
	     (m_pipeline$first[570] ?
		m_pRqMshr$RDY_pipelineResp_releaseEntry :
		m_rsToPIndexQ$FULL_N) ;
  assign m_pipeline_first__73_BITS_514_TO_512_78_EQ_m_p_ETC___d600 =
	     m_pipeline$first[514:512] == m_pipeline$first[576:574] ;
  assign m_pipeline_first__73_BITS_569_TO_518_86_EQ_m_c_ETC___d588 =
	     m_pipeline$first[569:518] ==
	     m_cRqMshr$pipelineResp_getRq[63:12] ;
  assign m_pipeline_first__73_BIT_515_74_AND_m_pipeline_ETC___d657 =
	     m_pipeline$first[515] &&
	     m_pipeline_first__73_BITS_514_TO_512_78_EQ_m_p_ETC___d600 ||
	     !m_pipeline$first[515] &&
	     !m_cRqMshr$pipelineResp_searchEndOfChain[3] &&
	     m_pipeline_first__73_BITS_569_TO_518_86_EQ_m_c_ETC___d588 &&
	     m_pipeline$first[517:516] != 2'd0 ;
  assign m_rqToPQ_enqReq_dummy2_2_read__16_AND_IF_m_rqT_ETC___d242 =
	     m_rqToPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_m_rqToPQ_enqReq_lat_1_whas__66_THEN_m_rqToP_ETC___d175 ||
	     (!m_rqToPQ_deqReq_dummy2_2$Q_OUT ||
	      !EN_to_parent_rqToP_deq && !m_rqToPQ_deqReq_rl) &&
	     m_rqToPQ_full ;
  assign m_rsToPQ_enqReq_dummy2_2_read__12_AND_IF_m_rsT_ETC___d138 =
	     m_rsToPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d40 ||
	     (!m_rsToPQ_deqReq_dummy2_2$Q_OUT ||
	      !EN_to_parent_rsToP_deq && !m_rsToPQ_deqReq_rl) &&
	     m_rsToPQ_full ;
  assign next_deqP___1__h19103 = m_rsToPQ_deqP + 1'd1 ;
  assign next_deqP___1__h27008 = m_rqToPQ_deqP + 1'd1 ;
  assign next_deqP___1__h41651 = m_fromPQ_deqP + 1'd1 ;
  assign resp_addr__h47838 =
	     { m_cRqMshr$sendRsToP_cRq_getSlot[52:1],
	       m_cRqMshr$sendRsToP_cRq_getRq[11:0] } ;
  assign sel__h51386 = m_cRqMshr$pipelineResp_getRq[5:2] + 4'd1 ;
  assign v__h14050 =
	     (m_rsToPQ_enqReq_dummy2_2$Q_OUT &&
	      IF_m_rsToPQ_enqReq_lat_1_whas__1_THEN_m_rsToPQ_ETC___d40) ?
	       v__h14333 :
	       m_rsToPQ_enqP ;
  assign v__h14333 = m_rsToPQ_enqP + 1'd1 ;
  assign v__h25933 =
	     (m_rqToPQ_enqReq_dummy2_2$Q_OUT &&
	      IF_m_rqToPQ_enqReq_lat_1_whas__66_THEN_m_rqToP_ETC___d175) ?
	       v__h26216 :
	       m_rqToPQ_enqP ;
  assign v__h26216 = m_rqToPQ_enqP + 1'd1 ;
  assign v__h36262 =
	     (m_fromPQ_enqReq_dummy2_2$Q_OUT &&
	      IF_m_fromPQ_enqReq_lat_1_whas__63_THEN_m_fromP_ETC___d272) ?
	       v__h36545 :
	       m_fromPQ_enqP ;
  assign v__h36545 = m_fromPQ_enqP + 1'd1 ;
  assign v__h43566 =
	     m_rqFromCQ_data_0_dummy2_1$Q_OUT ?
	       IF_m_rqFromCQ_data_0_lat_0_whas_THEN_m_rqFromC_ETC___d6 :
	       64'd0 ;
  assign x__h38966 =
	     EN_to_parent_fromP_enq ?
	       m_fromPQ_enqReq_lat_0$wget[2:0] :
	       m_fromPQ_enqReq_rl[2:0] ;
  assign x_addr__h14493 =
	     m_rsToPQ_enqReq_lat_0$whas ?
	       m_rsToPQ_enqReq_lat_0$wget[578:515] :
	       m_rsToPQ_enqReq_rl[578:515] ;
  always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
  begin
    case (m_fromPQ_deqP)
      1'd0: addr__h46129 = m_fromPQ_data_0[581:518];
      1'd1: addr__h46129 = m_fromPQ_data_1[581:518];
    endcase
  end
  always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
  begin
    case (m_fromPQ_deqP)
      1'd0: x__h47671 = m_fromPQ_data_0[2:0];
      1'd1: x__h47671 = m_fromPQ_data_1[2:0];
    endcase
  end
  always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
  begin
    case (m_fromPQ_deqP)
      1'd0:
	  SEL_ARR_m_fromPQ_data_0_57_BITS_65_TO_2_66_m_f_ETC___d469 =
	      m_fromPQ_data_0[65:2];
      1'd1:
	  SEL_ARR_m_fromPQ_data_0_57_BITS_65_TO_2_66_m_f_ETC___d469 =
	      m_fromPQ_data_1[65:2];
    endcase
  end
  always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
  begin
    case (m_rsToPQ_deqP)
      1'd0:
	  CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_511__ETC__q1 =
	      m_rsToPQ_data_0[511:448];
      1'd1:
	  CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_511__ETC__q1 =
	      m_rsToPQ_data_1[511:448];
    endcase
  end
  always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
  begin
    case (m_rsToPQ_deqP)
      1'd0:
	  CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_447__ETC__q2 =
	      m_rsToPQ_data_0[447:384];
      1'd1:
	  CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_447__ETC__q2 =
	      m_rsToPQ_data_1[447:384];
    endcase
  end
  always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
  begin
    case (m_rsToPQ_deqP)
      1'd0:
	  CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_383__ETC__q3 =
	      m_rsToPQ_data_0[383:320];
      1'd1:
	  CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_383__ETC__q3 =
	      m_rsToPQ_data_1[383:320];
    endcase
  end
  always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
  begin
    case (m_rsToPQ_deqP)
      1'd0:
	  CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_319__ETC__q4 =
	      m_rsToPQ_data_0[319:256];
      1'd1:
	  CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_319__ETC__q4 =
	      m_rsToPQ_data_1[319:256];
    endcase
  end
  always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
  begin
    case (m_fromPQ_deqP)
      1'd0:
	  CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_514__ETC__q5 =
	      m_fromPQ_data_0[514:451];
      1'd1:
	  CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_514__ETC__q5 =
	      m_fromPQ_data_1[514:451];
    endcase
  end
  always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
  begin
    case (m_fromPQ_deqP)
      1'd0:
	  CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_450__ETC__q6 =
	      m_fromPQ_data_0[450:387];
      1'd1:
	  CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_450__ETC__q6 =
	      m_fromPQ_data_1[450:387];
    endcase
  end
  always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
  begin
    case (m_fromPQ_deqP)
      1'd0:
	  CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_386__ETC__q7 =
	      m_fromPQ_data_0[386:323];
      1'd1:
	  CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_386__ETC__q7 =
	      m_fromPQ_data_1[386:323];
    endcase
  end
  always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
  begin
    case (m_fromPQ_deqP)
      1'd0:
	  CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_322__ETC__q8 =
	      m_fromPQ_data_0[322:259];
      1'd1:
	  CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_322__ETC__q8 =
	      m_fromPQ_data_1[322:259];
    endcase
  end
  always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
  begin
    case (m_rsToPQ_deqP)
      1'd0:
	  CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_255__ETC__q9 =
	      m_rsToPQ_data_0[255:192];
      1'd1:
	  CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_255__ETC__q9 =
	      m_rsToPQ_data_1[255:192];
    endcase
  end
  always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
  begin
    case (m_rsToPQ_deqP)
      1'd0:
	  CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_191__ETC__q10 =
	      m_rsToPQ_data_0[191:128];
      1'd1:
	  CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_191__ETC__q10 =
	      m_rsToPQ_data_1[191:128];
    endcase
  end
  always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
  begin
    case (m_fromPQ_deqP)
      1'd0:
	  CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_258__ETC__q11 =
	      m_fromPQ_data_0[258:195];
      1'd1:
	  CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_258__ETC__q11 =
	      m_fromPQ_data_1[258:195];
    endcase
  end
  always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
  begin
    case (m_fromPQ_deqP)
      1'd0:
	  CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_194__ETC__q12 =
	      m_fromPQ_data_0[194:131];
      1'd1:
	  CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_194__ETC__q12 =
	      m_fromPQ_data_1[194:131];
    endcase
  end
  always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
  begin
    case (m_fromPQ_deqP)
      1'd0:
	  CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_130__ETC__q13 =
	      m_fromPQ_data_0[130:67];
      1'd1:
	  CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_130__ETC__q13 =
	      m_fromPQ_data_1[130:67];
    endcase
  end
  always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
  begin
    case (m_fromPQ_deqP)
      1'd0:
	  CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_66_T_ETC__q14 =
	      m_fromPQ_data_0[66:3];
      1'd1:
	  CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_66_T_ETC__q14 =
	      m_fromPQ_data_1[66:3];
    endcase
  end
  always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
  begin
    case (m_rsToPQ_deqP)
      1'd0:
	  CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_127__ETC__q15 =
	      m_rsToPQ_data_0[127:64];
      1'd1:
	  CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_127__ETC__q15 =
	      m_rsToPQ_data_1[127:64];
    endcase
  end
  always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
  begin
    case (m_rsToPQ_deqP)
      1'd0:
	  CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_63_T_ETC__q16 =
	      m_rsToPQ_data_0[63:0];
      1'd1:
	  CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_63_T_ETC__q16 =
	      m_rsToPQ_data_1[63:0];
    endcase
  end
  always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
  begin
    case (m_rsToPQ_deqP)
      1'd0:
	  CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_578__ETC__q17 =
	      m_rsToPQ_data_0[578:515];
      1'd1:
	  CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_578__ETC__q17 =
	      m_rsToPQ_data_1[578:515];
    endcase
  end
  always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
  begin
    case (m_rsToPQ_deqP)
      1'd0:
	  CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_514__ETC__q18 =
	      m_rsToPQ_data_0[514:513];
      1'd1:
	  CASE_m_rsToPQ_deqP_0_m_rsToPQ_data_0_BITS_514__ETC__q18 =
	      m_rsToPQ_data_1[514:513];
    endcase
  end
  always@(m_rsToPQ_deqP or m_rsToPQ_data_0 or m_rsToPQ_data_1)
  begin
    case (m_rsToPQ_deqP)
      1'd0:
	  CASE_m_rsToPQ_deqP_0_NOT_m_rsToPQ_data_0_BIT_5_ETC__q19 =
	      !m_rsToPQ_data_0[512];
      1'd1:
	  CASE_m_rsToPQ_deqP_0_NOT_m_rsToPQ_data_0_BIT_5_ETC__q19 =
	      !m_rsToPQ_data_1[512];
    endcase
  end
  always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
  begin
    case (m_fromPQ_deqP)
      1'd0:
	  CASE_m_fromPQ_deqP_0_NOT_m_fromPQ_data_0_BIT_5_ETC__q20 =
	      !m_fromPQ_data_0[515];
      1'd1:
	  CASE_m_fromPQ_deqP_0_NOT_m_fromPQ_data_0_BIT_5_ETC__q20 =
	      !m_fromPQ_data_1[515];
    endcase
  end
  always@(m_rqToPQ_deqP or m_rqToPQ_data_0 or m_rqToPQ_data_1)
  begin
    case (m_rqToPQ_deqP)
      1'd0:
	  CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_5_TO_ETC__q21 =
	      m_rqToPQ_data_0[5:4];
      1'd1:
	  CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_5_TO_ETC__q21 =
	      m_rqToPQ_data_1[5:4];
    endcase
  end
  always@(m_rqToPQ_deqP or m_rqToPQ_data_0 or m_rqToPQ_data_1)
  begin
    case (m_rqToPQ_deqP)
      1'd0:
	  CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BIT_3_1_m_ETC__q22 =
	      m_rqToPQ_data_0[3];
      1'd1:
	  CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BIT_3_1_m_ETC__q22 =
	      m_rqToPQ_data_1[3];
    endcase
  end
  always@(m_rqToPQ_deqP or m_rqToPQ_data_0 or m_rqToPQ_data_1)
  begin
    case (m_rqToPQ_deqP)
      1'd0:
	  CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_2_TO_ETC__q23 =
	      m_rqToPQ_data_0[2:0];
      1'd1:
	  CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_2_TO_ETC__q23 =
	      m_rqToPQ_data_1[2:0];
    endcase
  end
  always@(m_rqToPQ_deqP or m_rqToPQ_data_0 or m_rqToPQ_data_1)
  begin
    case (m_rqToPQ_deqP)
      1'd0:
	  CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_71_T_ETC__q24 =
	      m_rqToPQ_data_0[71:8];
      1'd1:
	  CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_71_T_ETC__q24 =
	      m_rqToPQ_data_1[71:8];
    endcase
  end
  always@(m_rqToPQ_deqP or m_rqToPQ_data_0 or m_rqToPQ_data_1)
  begin
    case (m_rqToPQ_deqP)
      1'd0:
	  CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_7_TO_ETC__q25 =
	      m_rqToPQ_data_0[7:6];
      1'd1:
	  CASE_m_rqToPQ_deqP_0_m_rqToPQ_data_0_BITS_7_TO_ETC__q25 =
	      m_rqToPQ_data_1[7:6];
    endcase
  end
  always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
  begin
    case (m_fromPQ_deqP)
      1'd0:
	  CASE_m_fromPQ_deqP_0_NOT_m_fromPQ_data_0_BIT_5_ETC__q26 =
	      !m_fromPQ_data_0[582];
      1'd1:
	  CASE_m_fromPQ_deqP_0_NOT_m_fromPQ_data_0_BIT_5_ETC__q26 =
	      !m_fromPQ_data_1[582];
    endcase
  end
  always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
  begin
    case (m_fromPQ_deqP)
      1'd0:
	  CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_582_1_ETC__q27 =
	      m_fromPQ_data_0[582];
      1'd1:
	  CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BIT_582_1_ETC__q27 =
	      m_fromPQ_data_1[582];
    endcase
  end
  always@(sel__h51386 or m_pipeline$first)
  begin
    case (sel__h51386)
      4'd0:
	  CASE_sel1386_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q28 =
	      m_pipeline$first[31:0];
      4'd1:
	  CASE_sel1386_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q28 =
	      m_pipeline$first[63:32];
      4'd2:
	  CASE_sel1386_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q28 =
	      m_pipeline$first[95:64];
      4'd3:
	  CASE_sel1386_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q28 =
	      m_pipeline$first[127:96];
      4'd4:
	  CASE_sel1386_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q28 =
	      m_pipeline$first[159:128];
      4'd5:
	  CASE_sel1386_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q28 =
	      m_pipeline$first[191:160];
      4'd6:
	  CASE_sel1386_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q28 =
	      m_pipeline$first[223:192];
      4'd7:
	  CASE_sel1386_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q28 =
	      m_pipeline$first[255:224];
      4'd8:
	  CASE_sel1386_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q28 =
	      m_pipeline$first[287:256];
      4'd9:
	  CASE_sel1386_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q28 =
	      m_pipeline$first[319:288];
      4'd10:
	  CASE_sel1386_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q28 =
	      m_pipeline$first[351:320];
      4'd11:
	  CASE_sel1386_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q28 =
	      m_pipeline$first[383:352];
      4'd12:
	  CASE_sel1386_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q28 =
	      m_pipeline$first[415:384];
      4'd13:
	  CASE_sel1386_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q28 =
	      m_pipeline$first[447:416];
      4'd14:
	  CASE_sel1386_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q28 =
	      m_pipeline$first[479:448];
      4'd15:
	  CASE_sel1386_0_m_pipelinefirst_BITS_31_TO_0_1_ETC__q28 =
	      m_pipeline$first[511:480];
    endcase
  end
  always@(m_cRqMshr$pipelineResp_getRq or m_pipeline$first)
  begin
    case (m_cRqMshr$pipelineResp_getRq[5:2])
      4'd0:
	  CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q29 =
	      m_pipeline$first[31:0];
      4'd1:
	  CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q29 =
	      m_pipeline$first[63:32];
      4'd2:
	  CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q29 =
	      m_pipeline$first[95:64];
      4'd3:
	  CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q29 =
	      m_pipeline$first[127:96];
      4'd4:
	  CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q29 =
	      m_pipeline$first[159:128];
      4'd5:
	  CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q29 =
	      m_pipeline$first[191:160];
      4'd6:
	  CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q29 =
	      m_pipeline$first[223:192];
      4'd7:
	  CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q29 =
	      m_pipeline$first[255:224];
      4'd8:
	  CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q29 =
	      m_pipeline$first[287:256];
      4'd9:
	  CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q29 =
	      m_pipeline$first[319:288];
      4'd10:
	  CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q29 =
	      m_pipeline$first[351:320];
      4'd11:
	  CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q29 =
	      m_pipeline$first[383:352];
      4'd12:
	  CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q29 =
	      m_pipeline$first[415:384];
      4'd13:
	  CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q29 =
	      m_pipeline$first[447:416];
      4'd14:
	  CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q29 =
	      m_pipeline$first[479:448];
      4'd15:
	  CASE_m_cRqMshrpipelineResp_getRq_BITS_5_TO_2__ETC__q29 =
	      m_pipeline$first[511:480];
    endcase
  end
  always@(m_fromPQ_deqP or m_fromPQ_data_0 or m_fromPQ_data_1)
  begin
    case (m_fromPQ_deqP)
      1'd0:
	  CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_1_TO_ETC__q30 =
	      m_fromPQ_data_0[1:0];
      1'd1:
	  CASE_m_fromPQ_deqP_0_m_fromPQ_data_0_BITS_1_TO_ETC__q30 =
	      m_fromPQ_data_1[1:0];
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        m_fromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	m_fromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	    583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA80000000000000000;
	m_fromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
	    583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA80000000000000000;
	m_fromPQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
	m_fromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	m_fromPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	m_fromPQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
	m_fromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    584'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	m_fromPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	m_rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY 64'hAAAAAAAAAAAAAAAA;
	m_rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
	m_rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	m_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	m_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY 72'd0;
	m_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY 72'd0;
	m_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
	m_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	m_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	m_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
	m_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 73'h0AAAAAAAAAAAAAAAAAA;
	m_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	m_rsToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	m_rsToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	    579'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	m_rsToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
	    579'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	m_rsToPQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
	m_rsToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	m_rsToPQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	m_rsToPQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
	m_rsToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    580'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	m_rsToPQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
      end
    else
      begin
        if (m_fromPQ_clearReq_rl$EN)
	  m_fromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      m_fromPQ_clearReq_rl$D_IN;
	if (m_fromPQ_data_0$EN)
	  m_fromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY m_fromPQ_data_0$D_IN;
	if (m_fromPQ_data_1$EN)
	  m_fromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY m_fromPQ_data_1$D_IN;
	if (m_fromPQ_deqP$EN)
	  m_fromPQ_deqP <= `BSV_ASSIGNMENT_DELAY m_fromPQ_deqP$D_IN;
	if (m_fromPQ_deqReq_rl$EN)
	  m_fromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY m_fromPQ_deqReq_rl$D_IN;
	if (m_fromPQ_empty$EN)
	  m_fromPQ_empty <= `BSV_ASSIGNMENT_DELAY m_fromPQ_empty$D_IN;
	if (m_fromPQ_enqP$EN)
	  m_fromPQ_enqP <= `BSV_ASSIGNMENT_DELAY m_fromPQ_enqP$D_IN;
	if (m_fromPQ_enqReq_rl$EN)
	  m_fromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY m_fromPQ_enqReq_rl$D_IN;
	if (m_fromPQ_full$EN)
	  m_fromPQ_full <= `BSV_ASSIGNMENT_DELAY m_fromPQ_full$D_IN;
	if (m_rqFromCQ_data_0_rl$EN)
	  m_rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
	      m_rqFromCQ_data_0_rl$D_IN;
	if (m_rqFromCQ_empty_rl$EN)
	  m_rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
	      m_rqFromCQ_empty_rl$D_IN;
	if (m_rqFromCQ_full_rl$EN)
	  m_rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY m_rqFromCQ_full_rl$D_IN;
	if (m_rqToPQ_clearReq_rl$EN)
	  m_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      m_rqToPQ_clearReq_rl$D_IN;
	if (m_rqToPQ_data_0$EN)
	  m_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_data_0$D_IN;
	if (m_rqToPQ_data_1$EN)
	  m_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_data_1$D_IN;
	if (m_rqToPQ_deqP$EN)
	  m_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_deqP$D_IN;
	if (m_rqToPQ_deqReq_rl$EN)
	  m_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_deqReq_rl$D_IN;
	if (m_rqToPQ_empty$EN)
	  m_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_empty$D_IN;
	if (m_rqToPQ_enqP$EN)
	  m_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_enqP$D_IN;
	if (m_rqToPQ_enqReq_rl$EN)
	  m_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_enqReq_rl$D_IN;
	if (m_rqToPQ_full$EN)
	  m_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY m_rqToPQ_full$D_IN;
	if (m_rsToPQ_clearReq_rl$EN)
	  m_rsToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      m_rsToPQ_clearReq_rl$D_IN;
	if (m_rsToPQ_data_0$EN)
	  m_rsToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY m_rsToPQ_data_0$D_IN;
	if (m_rsToPQ_data_1$EN)
	  m_rsToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY m_rsToPQ_data_1$D_IN;
	if (m_rsToPQ_deqP$EN)
	  m_rsToPQ_deqP <= `BSV_ASSIGNMENT_DELAY m_rsToPQ_deqP$D_IN;
	if (m_rsToPQ_deqReq_rl$EN)
	  m_rsToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY m_rsToPQ_deqReq_rl$D_IN;
	if (m_rsToPQ_empty$EN)
	  m_rsToPQ_empty <= `BSV_ASSIGNMENT_DELAY m_rsToPQ_empty$D_IN;
	if (m_rsToPQ_enqP$EN)
	  m_rsToPQ_enqP <= `BSV_ASSIGNMENT_DELAY m_rsToPQ_enqP$D_IN;
	if (m_rsToPQ_enqReq_rl$EN)
	  m_rsToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY m_rsToPQ_enqReq_rl$D_IN;
	if (m_rsToPQ_full$EN)
	  m_rsToPQ_full <= `BSV_ASSIGNMENT_DELAY m_rsToPQ_full$D_IN;
      end
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    m_fromPQ_clearReq_rl = 1'h0;
    m_fromPQ_data_0 =
	583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    m_fromPQ_data_1 =
	583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    m_fromPQ_deqP = 1'h0;
    m_fromPQ_deqReq_rl = 1'h0;
    m_fromPQ_empty = 1'h0;
    m_fromPQ_enqP = 1'h0;
    m_fromPQ_enqReq_rl =
	584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    m_fromPQ_full = 1'h0;
    m_rqFromCQ_data_0_rl = 64'hAAAAAAAAAAAAAAAA;
    m_rqFromCQ_empty_rl = 1'h0;
    m_rqFromCQ_full_rl = 1'h0;
    m_rqToPQ_clearReq_rl = 1'h0;
    m_rqToPQ_data_0 = 72'hAAAAAAAAAAAAAAAAAA;
    m_rqToPQ_data_1 = 72'hAAAAAAAAAAAAAAAAAA;
    m_rqToPQ_deqP = 1'h0;
    m_rqToPQ_deqReq_rl = 1'h0;
    m_rqToPQ_empty = 1'h0;
    m_rqToPQ_enqP = 1'h0;
    m_rqToPQ_enqReq_rl = 73'h0AAAAAAAAAAAAAAAAAA;
    m_rqToPQ_full = 1'h0;
    m_rsToPQ_clearReq_rl = 1'h0;
    m_rsToPQ_data_0 =
	579'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    m_rsToPQ_data_1 =
	579'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    m_rsToPQ_deqP = 1'h0;
    m_rsToPQ_deqReq_rl = 1'h0;
    m_rsToPQ_empty = 1'h0;
    m_rsToPQ_enqP = 1'h0;
    m_rsToPQ_enqReq_rl =
	580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    m_rsToPQ_full = 1'h0;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // mkIBankWrapper

