//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name                         I/O  size props
// RDY_start                      O     1
// master0_awvalid                O     1
// master0_awid                   O     4 reg
// master0_awaddr                 O    64 reg
// master0_awlen                  O     8 reg
// master0_awsize                 O     3 reg
// master0_awburst                O     2 reg
// master0_awlock                 O     1 reg
// master0_awcache                O     4 reg
// master0_awprot                 O     3 reg
// master0_awqos                  O     4 reg
// master0_awregion               O     4 reg
// master0_wvalid                 O     1
// master0_wdata                  O    64 reg
// master0_wstrb                  O     8 reg
// master0_wlast                  O     1 reg
// master0_bready                 O     1
// master0_arvalid                O     1
// master0_arid                   O     4 reg
// master0_araddr                 O    64 reg
// master0_arlen                  O     8 reg
// master0_arsize                 O     3 reg
// master0_arburst                O     2 reg
// master0_arlock                 O     1 reg
// master0_arcache                O     4 reg
// master0_arprot                 O     3 reg
// master0_arqos                  O     4 reg
// master0_arregion               O     4 reg
// master0_rready                 O     1
// master1_awvalid                O     1
// master1_awid                   O     4 reg
// master1_awaddr                 O    64 reg
// master1_awlen                  O     8 reg
// master1_awsize                 O     3 reg
// master1_awburst                O     2 reg
// master1_awlock                 O     1 reg
// master1_awcache                O     4 reg
// master1_awprot                 O     3 reg
// master1_awqos                  O     4 reg
// master1_awregion               O     4 reg
// master1_wvalid                 O     1
// master1_wdata                  O    64 reg
// master1_wstrb                  O     8 reg
// master1_wlast                  O     1 reg
// master1_bready                 O     1
// master1_arvalid                O     1
// master1_arid                   O     4 reg
// master1_araddr                 O    64 reg
// master1_arlen                  O     8 reg
// master1_arsize                 O     3 reg
// master1_arburst                O     2 reg
// master1_arlock                 O     1 reg
// master1_arcache                O     4 reg
// master1_arprot                 O     3 reg
// master1_arqos                  O     4 reg
// master1_arregion               O     4 reg
// master1_rready                 O     1
// RDY_set_verbosity              O     1 const
// debug_module_mem_server_awready  O     1 reg
// debug_module_mem_server_wready  O     1 reg
// debug_module_mem_server_bvalid  O     1 reg
// debug_module_mem_server_bid    O     4 reg
// debug_module_mem_server_bresp  O     2 reg
// debug_module_mem_server_arready  O     1 reg
// debug_module_mem_server_rvalid  O     1 reg
// debug_module_mem_server_rid    O     4 reg
// debug_module_mem_server_rdata  O    64 reg
// debug_module_mem_server_rresp  O     2 reg
// debug_module_mem_server_rlast  O     1 reg
// CLK                            I     1 clock
// RST_N                          I     1 reset
// start_running                  I     1 unused
// start_startpc                  I    64
// start_tohostAddr               I    64 reg
// start_fromhostAddr             I    64 reg
// master0_awready                I     1
// master0_wready                 I     1
// master0_bvalid                 I     1
// master0_bid                    I     4 reg
// master0_bresp                  I     2 reg
// master0_arready                I     1
// master0_rvalid                 I     1
// master0_rid                    I     4 reg
// master0_rdata                  I    64 reg
// master0_rresp                  I     2 reg
// master0_rlast                  I     1 reg
// master1_awready                I     1
// master1_wready                 I     1
// master1_bvalid                 I     1
// master1_bid                    I     4 reg
// master1_bresp                  I     2 reg
// master1_arready                I     1
// master1_rvalid                 I     1
// master1_rid                    I     4 reg
// master1_rdata                  I    64 reg
// master1_rresp                  I     2 reg
// master1_rlast                  I     1 reg
// m_external_interrupt_req_set_not_clear  I     1 reg
// s_external_interrupt_req_set_not_clear  I     1
// non_maskable_interrupt_req_set_not_clear  I     1 unused
// set_verbosity_verbosity        I     4 reg
// debug_module_mem_server_awvalid  I     1
// debug_module_mem_server_awid   I     4 reg
// debug_module_mem_server_awaddr  I    64 reg
// debug_module_mem_server_awlen  I     8 reg
// debug_module_mem_server_awsize  I     3 reg
// debug_module_mem_server_awburst  I     2 reg
// debug_module_mem_server_awlock  I     1 reg
// debug_module_mem_server_awcache  I     4 reg
// debug_module_mem_server_awprot  I     3 reg
// debug_module_mem_server_awqos  I     4 reg
// debug_module_mem_server_awregion  I     4 reg
// debug_module_mem_server_wvalid  I     1
// debug_module_mem_server_wdata  I    64 reg
// debug_module_mem_server_wstrb  I     8 reg
// debug_module_mem_server_wlast  I     1 reg
// debug_module_mem_server_bready  I     1
// debug_module_mem_server_arvalid  I     1
// debug_module_mem_server_arid   I     4 reg
// debug_module_mem_server_araddr  I    64 reg
// debug_module_mem_server_arlen  I     8 reg
// debug_module_mem_server_arsize  I     3 reg
// debug_module_mem_server_arburst  I     2 reg
// debug_module_mem_server_arlock  I     1 reg
// debug_module_mem_server_arcache  I     4 reg
// debug_module_mem_server_arprot  I     3 reg
// debug_module_mem_server_arqos  I     4 reg
// debug_module_mem_server_arregion  I     4 reg
// debug_module_mem_server_rready  I     1
// EN_start                       I     1
// EN_set_verbosity               I     1
//
// Combinational paths from inputs to outputs:
//   (master0_awready, master0_wready) -> master0_bready
//   (master1_awready, master1_wready) -> master1_bready
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkProc(CLK,
	      RST_N,

	      start_running,
	      start_startpc,
	      start_tohostAddr,
	      start_fromhostAddr,
	      EN_start,
	      RDY_start,

	      master0_awvalid,

	      master0_awid,

	      master0_awaddr,

	      master0_awlen,

	      master0_awsize,

	      master0_awburst,

	      master0_awlock,

	      master0_awcache,

	      master0_awprot,

	      master0_awqos,

	      master0_awregion,

	      master0_awready,

	      master0_wvalid,

	      master0_wdata,

	      master0_wstrb,

	      master0_wlast,

	      master0_wready,

	      master0_bvalid,
	      master0_bid,
	      master0_bresp,

	      master0_bready,

	      master0_arvalid,

	      master0_arid,

	      master0_araddr,

	      master0_arlen,

	      master0_arsize,

	      master0_arburst,

	      master0_arlock,

	      master0_arcache,

	      master0_arprot,

	      master0_arqos,

	      master0_arregion,

	      master0_arready,

	      master0_rvalid,
	      master0_rid,
	      master0_rdata,
	      master0_rresp,
	      master0_rlast,

	      master0_rready,

	      master1_awvalid,

	      master1_awid,

	      master1_awaddr,

	      master1_awlen,

	      master1_awsize,

	      master1_awburst,

	      master1_awlock,

	      master1_awcache,

	      master1_awprot,

	      master1_awqos,

	      master1_awregion,

	      master1_awready,

	      master1_wvalid,

	      master1_wdata,

	      master1_wstrb,

	      master1_wlast,

	      master1_wready,

	      master1_bvalid,
	      master1_bid,
	      master1_bresp,

	      master1_bready,

	      master1_arvalid,

	      master1_arid,

	      master1_araddr,

	      master1_arlen,

	      master1_arsize,

	      master1_arburst,

	      master1_arlock,

	      master1_arcache,

	      master1_arprot,

	      master1_arqos,

	      master1_arregion,

	      master1_arready,

	      master1_rvalid,
	      master1_rid,
	      master1_rdata,
	      master1_rresp,
	      master1_rlast,

	      master1_rready,

	      m_external_interrupt_req_set_not_clear,

	      s_external_interrupt_req_set_not_clear,

	      non_maskable_interrupt_req_set_not_clear,

	      set_verbosity_verbosity,
	      EN_set_verbosity,
	      RDY_set_verbosity,

	      debug_module_mem_server_awvalid,
	      debug_module_mem_server_awid,
	      debug_module_mem_server_awaddr,
	      debug_module_mem_server_awlen,
	      debug_module_mem_server_awsize,
	      debug_module_mem_server_awburst,
	      debug_module_mem_server_awlock,
	      debug_module_mem_server_awcache,
	      debug_module_mem_server_awprot,
	      debug_module_mem_server_awqos,
	      debug_module_mem_server_awregion,

	      debug_module_mem_server_awready,

	      debug_module_mem_server_wvalid,
	      debug_module_mem_server_wdata,
	      debug_module_mem_server_wstrb,
	      debug_module_mem_server_wlast,

	      debug_module_mem_server_wready,

	      debug_module_mem_server_bvalid,

	      debug_module_mem_server_bid,

	      debug_module_mem_server_bresp,

	      debug_module_mem_server_bready,

	      debug_module_mem_server_arvalid,
	      debug_module_mem_server_arid,
	      debug_module_mem_server_araddr,
	      debug_module_mem_server_arlen,
	      debug_module_mem_server_arsize,
	      debug_module_mem_server_arburst,
	      debug_module_mem_server_arlock,
	      debug_module_mem_server_arcache,
	      debug_module_mem_server_arprot,
	      debug_module_mem_server_arqos,
	      debug_module_mem_server_arregion,

	      debug_module_mem_server_arready,

	      debug_module_mem_server_rvalid,

	      debug_module_mem_server_rid,

	      debug_module_mem_server_rdata,

	      debug_module_mem_server_rresp,

	      debug_module_mem_server_rlast,

	      debug_module_mem_server_rready);
  input  CLK;
  input  RST_N;

  // action method start
  input  start_running;
  input  [63 : 0] start_startpc;
  input  [63 : 0] start_tohostAddr;
  input  [63 : 0] start_fromhostAddr;
  input  EN_start;
  output RDY_start;

  // value method master0_m_awvalid
  output master0_awvalid;

  // value method master0_m_awid
  output [3 : 0] master0_awid;

  // value method master0_m_awaddr
  output [63 : 0] master0_awaddr;

  // value method master0_m_awlen
  output [7 : 0] master0_awlen;

  // value method master0_m_awsize
  output [2 : 0] master0_awsize;

  // value method master0_m_awburst
  output [1 : 0] master0_awburst;

  // value method master0_m_awlock
  output master0_awlock;

  // value method master0_m_awcache
  output [3 : 0] master0_awcache;

  // value method master0_m_awprot
  output [2 : 0] master0_awprot;

  // value method master0_m_awqos
  output [3 : 0] master0_awqos;

  // value method master0_m_awregion
  output [3 : 0] master0_awregion;

  // value method master0_m_awuser

  // action method master0_m_awready
  input  master0_awready;

  // value method master0_m_wvalid
  output master0_wvalid;

  // value method master0_m_wdata
  output [63 : 0] master0_wdata;

  // value method master0_m_wstrb
  output [7 : 0] master0_wstrb;

  // value method master0_m_wlast
  output master0_wlast;

  // value method master0_m_wuser

  // action method master0_m_wready
  input  master0_wready;

  // action method master0_m_bvalid
  input  master0_bvalid;
  input  [3 : 0] master0_bid;
  input  [1 : 0] master0_bresp;

  // value method master0_m_bready
  output master0_bready;

  // value method master0_m_arvalid
  output master0_arvalid;

  // value method master0_m_arid
  output [3 : 0] master0_arid;

  // value method master0_m_araddr
  output [63 : 0] master0_araddr;

  // value method master0_m_arlen
  output [7 : 0] master0_arlen;

  // value method master0_m_arsize
  output [2 : 0] master0_arsize;

  // value method master0_m_arburst
  output [1 : 0] master0_arburst;

  // value method master0_m_arlock
  output master0_arlock;

  // value method master0_m_arcache
  output [3 : 0] master0_arcache;

  // value method master0_m_arprot
  output [2 : 0] master0_arprot;

  // value method master0_m_arqos
  output [3 : 0] master0_arqos;

  // value method master0_m_arregion
  output [3 : 0] master0_arregion;

  // value method master0_m_aruser

  // action method master0_m_arready
  input  master0_arready;

  // action method master0_m_rvalid
  input  master0_rvalid;
  input  [3 : 0] master0_rid;
  input  [63 : 0] master0_rdata;
  input  [1 : 0] master0_rresp;
  input  master0_rlast;

  // value method master0_m_rready
  output master0_rready;

  // value method master1_m_awvalid
  output master1_awvalid;

  // value method master1_m_awid
  output [3 : 0] master1_awid;

  // value method master1_m_awaddr
  output [63 : 0] master1_awaddr;

  // value method master1_m_awlen
  output [7 : 0] master1_awlen;

  // value method master1_m_awsize
  output [2 : 0] master1_awsize;

  // value method master1_m_awburst
  output [1 : 0] master1_awburst;

  // value method master1_m_awlock
  output master1_awlock;

  // value method master1_m_awcache
  output [3 : 0] master1_awcache;

  // value method master1_m_awprot
  output [2 : 0] master1_awprot;

  // value method master1_m_awqos
  output [3 : 0] master1_awqos;

  // value method master1_m_awregion
  output [3 : 0] master1_awregion;

  // value method master1_m_awuser

  // action method master1_m_awready
  input  master1_awready;

  // value method master1_m_wvalid
  output master1_wvalid;

  // value method master1_m_wdata
  output [63 : 0] master1_wdata;

  // value method master1_m_wstrb
  output [7 : 0] master1_wstrb;

  // value method master1_m_wlast
  output master1_wlast;

  // value method master1_m_wuser

  // action method master1_m_wready
  input  master1_wready;

  // action method master1_m_bvalid
  input  master1_bvalid;
  input  [3 : 0] master1_bid;
  input  [1 : 0] master1_bresp;

  // value method master1_m_bready
  output master1_bready;

  // value method master1_m_arvalid
  output master1_arvalid;

  // value method master1_m_arid
  output [3 : 0] master1_arid;

  // value method master1_m_araddr
  output [63 : 0] master1_araddr;

  // value method master1_m_arlen
  output [7 : 0] master1_arlen;

  // value method master1_m_arsize
  output [2 : 0] master1_arsize;

  // value method master1_m_arburst
  output [1 : 0] master1_arburst;

  // value method master1_m_arlock
  output master1_arlock;

  // value method master1_m_arcache
  output [3 : 0] master1_arcache;

  // value method master1_m_arprot
  output [2 : 0] master1_arprot;

  // value method master1_m_arqos
  output [3 : 0] master1_arqos;

  // value method master1_m_arregion
  output [3 : 0] master1_arregion;

  // value method master1_m_aruser

  // action method master1_m_arready
  input  master1_arready;

  // action method master1_m_rvalid
  input  master1_rvalid;
  input  [3 : 0] master1_rid;
  input  [63 : 0] master1_rdata;
  input  [1 : 0] master1_rresp;
  input  master1_rlast;

  // value method master1_m_rready
  output master1_rready;

  // action method m_external_interrupt_req
  input  m_external_interrupt_req_set_not_clear;

  // action method s_external_interrupt_req
  input  s_external_interrupt_req_set_not_clear;

  // action method non_maskable_interrupt_req
  input  non_maskable_interrupt_req_set_not_clear;

  // action method set_verbosity
  input  [3 : 0] set_verbosity_verbosity;
  input  EN_set_verbosity;
  output RDY_set_verbosity;

  // action method debug_module_mem_server_m_awvalid
  input  debug_module_mem_server_awvalid;
  input  [3 : 0] debug_module_mem_server_awid;
  input  [63 : 0] debug_module_mem_server_awaddr;
  input  [7 : 0] debug_module_mem_server_awlen;
  input  [2 : 0] debug_module_mem_server_awsize;
  input  [1 : 0] debug_module_mem_server_awburst;
  input  debug_module_mem_server_awlock;
  input  [3 : 0] debug_module_mem_server_awcache;
  input  [2 : 0] debug_module_mem_server_awprot;
  input  [3 : 0] debug_module_mem_server_awqos;
  input  [3 : 0] debug_module_mem_server_awregion;

  // value method debug_module_mem_server_m_awready
  output debug_module_mem_server_awready;

  // action method debug_module_mem_server_m_wvalid
  input  debug_module_mem_server_wvalid;
  input  [63 : 0] debug_module_mem_server_wdata;
  input  [7 : 0] debug_module_mem_server_wstrb;
  input  debug_module_mem_server_wlast;

  // value method debug_module_mem_server_m_wready
  output debug_module_mem_server_wready;

  // value method debug_module_mem_server_m_bvalid
  output debug_module_mem_server_bvalid;

  // value method debug_module_mem_server_m_bid
  output [3 : 0] debug_module_mem_server_bid;

  // value method debug_module_mem_server_m_bresp
  output [1 : 0] debug_module_mem_server_bresp;

  // value method debug_module_mem_server_m_buser

  // action method debug_module_mem_server_m_bready
  input  debug_module_mem_server_bready;

  // action method debug_module_mem_server_m_arvalid
  input  debug_module_mem_server_arvalid;
  input  [3 : 0] debug_module_mem_server_arid;
  input  [63 : 0] debug_module_mem_server_araddr;
  input  [7 : 0] debug_module_mem_server_arlen;
  input  [2 : 0] debug_module_mem_server_arsize;
  input  [1 : 0] debug_module_mem_server_arburst;
  input  debug_module_mem_server_arlock;
  input  [3 : 0] debug_module_mem_server_arcache;
  input  [2 : 0] debug_module_mem_server_arprot;
  input  [3 : 0] debug_module_mem_server_arqos;
  input  [3 : 0] debug_module_mem_server_arregion;

  // value method debug_module_mem_server_m_arready
  output debug_module_mem_server_arready;

  // value method debug_module_mem_server_m_rvalid
  output debug_module_mem_server_rvalid;

  // value method debug_module_mem_server_m_rid
  output [3 : 0] debug_module_mem_server_rid;

  // value method debug_module_mem_server_m_rdata
  output [63 : 0] debug_module_mem_server_rdata;

  // value method debug_module_mem_server_m_rresp
  output [1 : 0] debug_module_mem_server_rresp;

  // value method debug_module_mem_server_m_rlast
  output debug_module_mem_server_rlast;

  // value method debug_module_mem_server_m_ruser

  // action method debug_module_mem_server_m_rready
  input  debug_module_mem_server_rready;

  // signals for module outputs
  wire [63 : 0] debug_module_mem_server_rdata,
		master0_araddr,
		master0_awaddr,
		master0_wdata,
		master1_araddr,
		master1_awaddr,
		master1_wdata;
  wire [7 : 0] master0_arlen,
	       master0_awlen,
	       master0_wstrb,
	       master1_arlen,
	       master1_awlen,
	       master1_wstrb;
  wire [3 : 0] debug_module_mem_server_bid,
	       debug_module_mem_server_rid,
	       master0_arcache,
	       master0_arid,
	       master0_arqos,
	       master0_arregion,
	       master0_awcache,
	       master0_awid,
	       master0_awqos,
	       master0_awregion,
	       master1_arcache,
	       master1_arid,
	       master1_arqos,
	       master1_arregion,
	       master1_awcache,
	       master1_awid,
	       master1_awqos,
	       master1_awregion;
  wire [2 : 0] master0_arprot,
	       master0_arsize,
	       master0_awprot,
	       master0_awsize,
	       master1_arprot,
	       master1_arsize,
	       master1_awprot,
	       master1_awsize;
  wire [1 : 0] debug_module_mem_server_bresp,
	       debug_module_mem_server_rresp,
	       master0_arburst,
	       master0_awburst,
	       master1_arburst,
	       master1_awburst;
  wire RDY_set_verbosity,
       RDY_start,
       debug_module_mem_server_arready,
       debug_module_mem_server_awready,
       debug_module_mem_server_bvalid,
       debug_module_mem_server_rlast,
       debug_module_mem_server_rvalid,
       debug_module_mem_server_wready,
       master0_arlock,
       master0_arvalid,
       master0_awlock,
       master0_awvalid,
       master0_bready,
       master0_rready,
       master0_wlast,
       master0_wvalid,
       master1_arlock,
       master1_arvalid,
       master1_awlock,
       master1_awvalid,
       master1_bready,
       master1_rready,
       master1_wlast,
       master1_wvalid;

  // inlined wires
  wire [580 : 0] enqDst_1_0_lat_0$wget;
  wire [579 : 0] propDstData_1_0_lat_0$wget, propDstData_1_1_lat_0$wget;
  wire [73 : 0] enqDst_0_lat_0$wget;
  wire [72 : 0] propDstData_0_lat_0$wget, propDstData_1_lat_0$wget;
  wire [65 : 0] llc_mem_server_enqDst_0_lat_0$wget;
  wire [64 : 0] mmioPlatform_toHostQ_enqReq_lat_0$wget;
  wire [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1,
	       llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1,
	       llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read,
	       mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1,
	       mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1,
	       mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read;
  wire llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write,
       llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read,
       llc_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read,
       llc_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write,
       llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read,
       llc_axi4_adapter_master_xactor_crg_rd_data_full$port3__read,
       llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write,
       llc_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read,
       llc_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read,
       llc_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write,
       llc_axi4_adapter_master_xactor_crg_wr_data_full$port2__read,
       llc_axi4_adapter_master_xactor_crg_wr_data_full$port3__read,
       llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write,
       llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read,
       llc_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read,
       mmioPlatform_fromHostQ_deqReq_lat_0$whas,
       mmioPlatform_toHostQ_enqReq_lat_0$whas,
       mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write,
       mmio_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write,
       mmio_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port2__write,
       mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read,
       mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read,
       mmio_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write,
       mmio_axi4_adapter_master_xactor_crg_rd_data_full$port2__read,
       mmio_axi4_adapter_master_xactor_crg_rd_data_full$port3__read,
       mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write,
       mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port2__write,
       mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read,
       mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read,
       mmio_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write,
       mmio_axi4_adapter_master_xactor_crg_wr_data_full$EN_port2__write,
       mmio_axi4_adapter_master_xactor_crg_wr_data_full$port2__read,
       mmio_axi4_adapter_master_xactor_crg_wr_data_full$port3__read,
       mmio_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write,
       mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read,
       mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read,
       propDstIdx_0_lat_1$whas,
       propDstIdx_1_0_lat_1$whas,
       propDstIdx_1_1_lat_1$whas,
       propDstIdx_1_lat_1$whas;

  // register cfg_verbosity
  reg [3 : 0] cfg_verbosity;
  wire [3 : 0] cfg_verbosity$D_IN;
  wire cfg_verbosity$EN;

  // register enqDst_0_rl
  reg [73 : 0] enqDst_0_rl;
  wire [73 : 0] enqDst_0_rl$D_IN;
  wire enqDst_0_rl$EN;

  // register enqDst_1_0_rl
  reg [580 : 0] enqDst_1_0_rl;
  wire [580 : 0] enqDst_1_0_rl$D_IN;
  wire enqDst_1_0_rl$EN;

  // register llc_axi4_adapter_cfg_verbosity
  reg [3 : 0] llc_axi4_adapter_cfg_verbosity;
  wire [3 : 0] llc_axi4_adapter_cfg_verbosity$D_IN;
  wire llc_axi4_adapter_cfg_verbosity$EN;

  // register llc_axi4_adapter_ctr_wr_rsps_pending_crg
  reg [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg;
  wire [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN;
  wire llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN;

  // register llc_axi4_adapter_master_xactor_crg_rd_addr_full
  reg llc_axi4_adapter_master_xactor_crg_rd_addr_full;
  wire llc_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN,
       llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN;

  // register llc_axi4_adapter_master_xactor_crg_rd_data_full
  reg llc_axi4_adapter_master_xactor_crg_rd_data_full;
  wire llc_axi4_adapter_master_xactor_crg_rd_data_full$D_IN,
       llc_axi4_adapter_master_xactor_crg_rd_data_full$EN;

  // register llc_axi4_adapter_master_xactor_crg_wr_addr_full
  reg llc_axi4_adapter_master_xactor_crg_wr_addr_full;
  wire llc_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN,
       llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN;

  // register llc_axi4_adapter_master_xactor_crg_wr_data_full
  reg llc_axi4_adapter_master_xactor_crg_wr_data_full;
  wire llc_axi4_adapter_master_xactor_crg_wr_data_full$D_IN,
       llc_axi4_adapter_master_xactor_crg_wr_data_full$EN;

  // register llc_axi4_adapter_master_xactor_crg_wr_resp_full
  reg llc_axi4_adapter_master_xactor_crg_wr_resp_full;
  wire llc_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN,
       llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN;

  // register llc_axi4_adapter_master_xactor_rg_rd_addr
  reg [96 : 0] llc_axi4_adapter_master_xactor_rg_rd_addr;
  wire [96 : 0] llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN;
  wire llc_axi4_adapter_master_xactor_rg_rd_addr$EN;

  // register llc_axi4_adapter_master_xactor_rg_rd_data
  reg [70 : 0] llc_axi4_adapter_master_xactor_rg_rd_data;
  wire [70 : 0] llc_axi4_adapter_master_xactor_rg_rd_data$D_IN;
  wire llc_axi4_adapter_master_xactor_rg_rd_data$EN;

  // register llc_axi4_adapter_master_xactor_rg_wr_addr
  reg [96 : 0] llc_axi4_adapter_master_xactor_rg_wr_addr;
  wire [96 : 0] llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN;
  wire llc_axi4_adapter_master_xactor_rg_wr_addr$EN;

  // register llc_axi4_adapter_master_xactor_rg_wr_data
  reg [72 : 0] llc_axi4_adapter_master_xactor_rg_wr_data;
  wire [72 : 0] llc_axi4_adapter_master_xactor_rg_wr_data$D_IN;
  wire llc_axi4_adapter_master_xactor_rg_wr_data$EN;

  // register llc_axi4_adapter_master_xactor_rg_wr_resp
  reg [5 : 0] llc_axi4_adapter_master_xactor_rg_wr_resp;
  wire [5 : 0] llc_axi4_adapter_master_xactor_rg_wr_resp$D_IN;
  wire llc_axi4_adapter_master_xactor_rg_wr_resp$EN;

  // register llc_axi4_adapter_rg_cline
  reg [511 : 0] llc_axi4_adapter_rg_cline;
  wire [511 : 0] llc_axi4_adapter_rg_cline$D_IN;
  wire llc_axi4_adapter_rg_cline$EN;

  // register llc_axi4_adapter_rg_rd_req_beat
  reg [2 : 0] llc_axi4_adapter_rg_rd_req_beat;
  wire [2 : 0] llc_axi4_adapter_rg_rd_req_beat$D_IN;
  wire llc_axi4_adapter_rg_rd_req_beat$EN;

  // register llc_axi4_adapter_rg_rd_rsp_beat
  reg [2 : 0] llc_axi4_adapter_rg_rd_rsp_beat;
  wire [2 : 0] llc_axi4_adapter_rg_rd_rsp_beat$D_IN;
  wire llc_axi4_adapter_rg_rd_rsp_beat$EN;

  // register llc_axi4_adapter_rg_wr_req_beat
  reg [2 : 0] llc_axi4_adapter_rg_wr_req_beat;
  wire [2 : 0] llc_axi4_adapter_rg_wr_req_beat$D_IN;
  wire llc_axi4_adapter_rg_wr_req_beat$EN;

  // register llc_axi4_adapter_rg_wr_rsp_beat
  reg [2 : 0] llc_axi4_adapter_rg_wr_rsp_beat;
  wire [2 : 0] llc_axi4_adapter_rg_wr_rsp_beat$D_IN;
  wire llc_axi4_adapter_rg_wr_rsp_beat$EN;

  // register llc_mem_server_enqDst_0_rl
  reg [65 : 0] llc_mem_server_enqDst_0_rl;
  wire [65 : 0] llc_mem_server_enqDst_0_rl$D_IN;
  wire llc_mem_server_enqDst_0_rl$EN;

  // register llc_mem_server_propDstData_0_rl
  reg [64 : 0] llc_mem_server_propDstData_0_rl;
  wire [64 : 0] llc_mem_server_propDstData_0_rl$D_IN;
  wire llc_mem_server_propDstData_0_rl$EN;

  // register llc_mem_server_propDstIdx_0_rl
  reg llc_mem_server_propDstIdx_0_rl;
  wire llc_mem_server_propDstIdx_0_rl$D_IN, llc_mem_server_propDstIdx_0_rl$EN;

  // register llc_mem_server_rg_cacheline_cache_addr
  reg [63 : 0] llc_mem_server_rg_cacheline_cache_addr;
  wire [63 : 0] llc_mem_server_rg_cacheline_cache_addr$D_IN;
  wire llc_mem_server_rg_cacheline_cache_addr$EN;

  // register llc_mem_server_rg_cacheline_cache_data
  reg [511 : 0] llc_mem_server_rg_cacheline_cache_data;
  wire [511 : 0] llc_mem_server_rg_cacheline_cache_data$D_IN;
  wire llc_mem_server_rg_cacheline_cache_data$EN;

  // register llc_mem_server_rg_cacheline_cache_dirty_delay
  reg [9 : 0] llc_mem_server_rg_cacheline_cache_dirty_delay;
  wire [9 : 0] llc_mem_server_rg_cacheline_cache_dirty_delay$D_IN;
  wire llc_mem_server_rg_cacheline_cache_dirty_delay$EN;

  // register llc_mem_server_rg_cacheline_cache_state
  reg [2 : 0] llc_mem_server_rg_cacheline_cache_state;
  reg [2 : 0] llc_mem_server_rg_cacheline_cache_state$D_IN;
  wire llc_mem_server_rg_cacheline_cache_state$EN;

  // register mmioPlatform_amoResp
  reg [63 : 0] mmioPlatform_amoResp;
  wire [63 : 0] mmioPlatform_amoResp$D_IN;
  wire mmioPlatform_amoResp$EN;

  // register mmioPlatform_curReq
  reg [66 : 0] mmioPlatform_curReq;
  wire [66 : 0] mmioPlatform_curReq$D_IN;
  wire mmioPlatform_curReq$EN;

  // register mmioPlatform_cycle
  reg [6 : 0] mmioPlatform_cycle;
  wire [6 : 0] mmioPlatform_cycle$D_IN;
  wire mmioPlatform_cycle$EN;

  // register mmioPlatform_fetchedInsts_0
  reg [31 : 0] mmioPlatform_fetchedInsts_0;
  wire [31 : 0] mmioPlatform_fetchedInsts_0$D_IN;
  wire mmioPlatform_fetchedInsts_0$EN;

  // register mmioPlatform_fetchingWay
  reg mmioPlatform_fetchingWay;
  wire mmioPlatform_fetchingWay$D_IN, mmioPlatform_fetchingWay$EN;

  // register mmioPlatform_fromHostAddr
  reg [60 : 0] mmioPlatform_fromHostAddr;
  wire [60 : 0] mmioPlatform_fromHostAddr$D_IN;
  wire mmioPlatform_fromHostAddr$EN;

  // register mmioPlatform_fromHostQ_clearReq_rl
  reg mmioPlatform_fromHostQ_clearReq_rl;
  wire mmioPlatform_fromHostQ_clearReq_rl$D_IN,
       mmioPlatform_fromHostQ_clearReq_rl$EN;

  // register mmioPlatform_fromHostQ_data_0
  reg [63 : 0] mmioPlatform_fromHostQ_data_0;
  wire [63 : 0] mmioPlatform_fromHostQ_data_0$D_IN;
  wire mmioPlatform_fromHostQ_data_0$EN;

  // register mmioPlatform_fromHostQ_deqReq_rl
  reg mmioPlatform_fromHostQ_deqReq_rl;
  wire mmioPlatform_fromHostQ_deqReq_rl$D_IN,
       mmioPlatform_fromHostQ_deqReq_rl$EN;

  // register mmioPlatform_fromHostQ_empty
  reg mmioPlatform_fromHostQ_empty;
  wire mmioPlatform_fromHostQ_empty$D_IN, mmioPlatform_fromHostQ_empty$EN;

  // register mmioPlatform_fromHostQ_enqReq_rl
  reg [64 : 0] mmioPlatform_fromHostQ_enqReq_rl;
  wire [64 : 0] mmioPlatform_fromHostQ_enqReq_rl$D_IN;
  wire mmioPlatform_fromHostQ_enqReq_rl$EN;

  // register mmioPlatform_fromHostQ_full
  reg mmioPlatform_fromHostQ_full;
  wire mmioPlatform_fromHostQ_full$D_IN, mmioPlatform_fromHostQ_full$EN;

  // register mmioPlatform_instSel
  reg mmioPlatform_instSel;
  wire mmioPlatform_instSel$D_IN, mmioPlatform_instSel$EN;

  // register mmioPlatform_mtime
  reg [63 : 0] mmioPlatform_mtime;
  wire [63 : 0] mmioPlatform_mtime$D_IN;
  wire mmioPlatform_mtime$EN;

  // register mmioPlatform_mtimecmp_0
  reg [63 : 0] mmioPlatform_mtimecmp_0;
  wire [63 : 0] mmioPlatform_mtimecmp_0$D_IN;
  wire mmioPlatform_mtimecmp_0$EN;

  // register mmioPlatform_mtip_0
  reg mmioPlatform_mtip_0;
  wire mmioPlatform_mtip_0$D_IN, mmioPlatform_mtip_0$EN;

  // register mmioPlatform_reqAmofunc
  reg [3 : 0] mmioPlatform_reqAmofunc;
  wire [3 : 0] mmioPlatform_reqAmofunc$D_IN;
  wire mmioPlatform_reqAmofunc$EN;

  // register mmioPlatform_reqBE
  reg [7 : 0] mmioPlatform_reqBE;
  wire [7 : 0] mmioPlatform_reqBE$D_IN;
  wire mmioPlatform_reqBE$EN;

  // register mmioPlatform_reqData
  reg [63 : 0] mmioPlatform_reqData;
  wire [63 : 0] mmioPlatform_reqData$D_IN;
  wire mmioPlatform_reqData$EN;

  // register mmioPlatform_reqFunc
  reg [5 : 0] mmioPlatform_reqFunc;
  reg [5 : 0] mmioPlatform_reqFunc$D_IN;
  wire mmioPlatform_reqFunc$EN;

  // register mmioPlatform_reqSz
  reg [1 : 0] mmioPlatform_reqSz;
  wire [1 : 0] mmioPlatform_reqSz$D_IN;
  wire mmioPlatform_reqSz$EN;

  // register mmioPlatform_state
  reg [1 : 0] mmioPlatform_state;
  reg [1 : 0] mmioPlatform_state$D_IN;
  wire mmioPlatform_state$EN;

  // register mmioPlatform_toHostAddr
  reg [60 : 0] mmioPlatform_toHostAddr;
  wire [60 : 0] mmioPlatform_toHostAddr$D_IN;
  wire mmioPlatform_toHostAddr$EN;

  // register mmioPlatform_toHostQ_clearReq_rl
  reg mmioPlatform_toHostQ_clearReq_rl;
  wire mmioPlatform_toHostQ_clearReq_rl$D_IN,
       mmioPlatform_toHostQ_clearReq_rl$EN;

  // register mmioPlatform_toHostQ_data_0
  reg [63 : 0] mmioPlatform_toHostQ_data_0;
  wire [63 : 0] mmioPlatform_toHostQ_data_0$D_IN;
  wire mmioPlatform_toHostQ_data_0$EN;

  // register mmioPlatform_toHostQ_deqReq_rl
  reg mmioPlatform_toHostQ_deqReq_rl;
  wire mmioPlatform_toHostQ_deqReq_rl$D_IN, mmioPlatform_toHostQ_deqReq_rl$EN;

  // register mmioPlatform_toHostQ_empty
  reg mmioPlatform_toHostQ_empty;
  wire mmioPlatform_toHostQ_empty$D_IN, mmioPlatform_toHostQ_empty$EN;

  // register mmioPlatform_toHostQ_enqReq_rl
  reg [64 : 0] mmioPlatform_toHostQ_enqReq_rl;
  wire [64 : 0] mmioPlatform_toHostQ_enqReq_rl$D_IN;
  wire mmioPlatform_toHostQ_enqReq_rl$EN;

  // register mmioPlatform_toHostQ_full
  reg mmioPlatform_toHostQ_full;
  wire mmioPlatform_toHostQ_full$D_IN, mmioPlatform_toHostQ_full$EN;

  // register mmioPlatform_waitLowerMSIPCRs
  reg mmioPlatform_waitLowerMSIPCRs;
  wire mmioPlatform_waitLowerMSIPCRs$D_IN, mmioPlatform_waitLowerMSIPCRs$EN;

  // register mmioPlatform_waitMTIPCRs
  reg mmioPlatform_waitMTIPCRs;
  wire mmioPlatform_waitMTIPCRs$D_IN, mmioPlatform_waitMTIPCRs$EN;

  // register mmioPlatform_waitUpperMSIPCRs
  reg mmioPlatform_waitUpperMSIPCRs;
  wire mmioPlatform_waitUpperMSIPCRs$D_IN, mmioPlatform_waitUpperMSIPCRs$EN;

  // register mmio_axi4_adapter_cfg_verbosity
  reg [3 : 0] mmio_axi4_adapter_cfg_verbosity;
  wire [3 : 0] mmio_axi4_adapter_cfg_verbosity$D_IN;
  wire mmio_axi4_adapter_cfg_verbosity$EN;

  // register mmio_axi4_adapter_ctr_wr_rsps_pending_crg
  reg [3 : 0] mmio_axi4_adapter_ctr_wr_rsps_pending_crg;
  wire [3 : 0] mmio_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN;
  wire mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN;

  // register mmio_axi4_adapter_master_xactor_crg_rd_addr_full
  reg mmio_axi4_adapter_master_xactor_crg_rd_addr_full;
  wire mmio_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN,
       mmio_axi4_adapter_master_xactor_crg_rd_addr_full$EN;

  // register mmio_axi4_adapter_master_xactor_crg_rd_data_full
  reg mmio_axi4_adapter_master_xactor_crg_rd_data_full;
  wire mmio_axi4_adapter_master_xactor_crg_rd_data_full$D_IN,
       mmio_axi4_adapter_master_xactor_crg_rd_data_full$EN;

  // register mmio_axi4_adapter_master_xactor_crg_wr_addr_full
  reg mmio_axi4_adapter_master_xactor_crg_wr_addr_full;
  wire mmio_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN,
       mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN;

  // register mmio_axi4_adapter_master_xactor_crg_wr_data_full
  reg mmio_axi4_adapter_master_xactor_crg_wr_data_full;
  wire mmio_axi4_adapter_master_xactor_crg_wr_data_full$D_IN,
       mmio_axi4_adapter_master_xactor_crg_wr_data_full$EN;

  // register mmio_axi4_adapter_master_xactor_crg_wr_resp_full
  reg mmio_axi4_adapter_master_xactor_crg_wr_resp_full;
  wire mmio_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN,
       mmio_axi4_adapter_master_xactor_crg_wr_resp_full$EN;

  // register mmio_axi4_adapter_master_xactor_rg_rd_addr
  reg [96 : 0] mmio_axi4_adapter_master_xactor_rg_rd_addr;
  wire [96 : 0] mmio_axi4_adapter_master_xactor_rg_rd_addr$D_IN;
  wire mmio_axi4_adapter_master_xactor_rg_rd_addr$EN;

  // register mmio_axi4_adapter_master_xactor_rg_rd_data
  reg [70 : 0] mmio_axi4_adapter_master_xactor_rg_rd_data;
  wire [70 : 0] mmio_axi4_adapter_master_xactor_rg_rd_data$D_IN;
  wire mmio_axi4_adapter_master_xactor_rg_rd_data$EN;

  // register mmio_axi4_adapter_master_xactor_rg_wr_addr
  reg [96 : 0] mmio_axi4_adapter_master_xactor_rg_wr_addr;
  wire [96 : 0] mmio_axi4_adapter_master_xactor_rg_wr_addr$D_IN;
  wire mmio_axi4_adapter_master_xactor_rg_wr_addr$EN;

  // register mmio_axi4_adapter_master_xactor_rg_wr_data
  reg [72 : 0] mmio_axi4_adapter_master_xactor_rg_wr_data;
  wire [72 : 0] mmio_axi4_adapter_master_xactor_rg_wr_data$D_IN;
  wire mmio_axi4_adapter_master_xactor_rg_wr_data$EN;

  // register mmio_axi4_adapter_master_xactor_rg_wr_resp
  reg [5 : 0] mmio_axi4_adapter_master_xactor_rg_wr_resp;
  wire [5 : 0] mmio_axi4_adapter_master_xactor_rg_wr_resp$D_IN;
  wire mmio_axi4_adapter_master_xactor_rg_wr_resp$EN;

  // register propDstData_0_rl
  reg [72 : 0] propDstData_0_rl;
  wire [72 : 0] propDstData_0_rl$D_IN;
  wire propDstData_0_rl$EN;

  // register propDstData_1_0_rl
  reg [579 : 0] propDstData_1_0_rl;
  wire [579 : 0] propDstData_1_0_rl$D_IN;
  wire propDstData_1_0_rl$EN;

  // register propDstData_1_1_rl
  reg [579 : 0] propDstData_1_1_rl;
  wire [579 : 0] propDstData_1_1_rl$D_IN;
  wire propDstData_1_1_rl$EN;

  // register propDstData_1_rl
  reg [72 : 0] propDstData_1_rl;
  wire [72 : 0] propDstData_1_rl$D_IN;
  wire propDstData_1_rl$EN;

  // register propDstIdx_0_rl
  reg propDstIdx_0_rl;
  wire propDstIdx_0_rl$D_IN, propDstIdx_0_rl$EN;

  // register propDstIdx_1_0_rl
  reg propDstIdx_1_0_rl;
  wire propDstIdx_1_0_rl$D_IN, propDstIdx_1_0_rl$EN;

  // register propDstIdx_1_1_rl
  reg propDstIdx_1_1_rl;
  wire propDstIdx_1_1_rl$D_IN, propDstIdx_1_1_rl$EN;

  // register propDstIdx_1_rl
  reg propDstIdx_1_rl;
  wire propDstIdx_1_rl$D_IN, propDstIdx_1_rl$EN;

  // register srcRR_0
  reg srcRR_0;
  wire srcRR_0$D_IN, srcRR_0$EN;

  // register srcRR_1_0
  reg srcRR_1_0;
  wire srcRR_1_0$D_IN, srcRR_1_0$EN;

  // ports of submodule core_0
  reg [66 : 0] core_0$mmioToPlatform_pRs_enq_x;
  reg [38 : 0] core_0$mmioToPlatform_pRq_enq_x;
  wire [582 : 0] core_0$dCacheToParent_fromP_enq_x,
		 core_0$iCacheToParent_fromP_enq_x;
  wire [578 : 0] core_0$dCacheToParent_rsToP_first,
		 core_0$iCacheToParent_rsToP_first;
  wire [141 : 0] core_0$mmioToPlatform_cRq_first;
  wire [71 : 0] core_0$dCacheToParent_rqToP_first,
		core_0$iCacheToParent_rqToP_first;
  wire [64 : 0] core_0$tlbToMem_memReq_first, core_0$tlbToMem_respLd_enq_x;
  wire [63 : 0] core_0$coreReq_start_fromHostAddr,
		core_0$coreReq_start_startpc,
		core_0$coreReq_start_toHostAddr,
		core_0$mmioToPlatform_setTime_t;
  wire [4 : 0] core_0$coreReq_perfReq_t;
  wire [3 : 0] core_0$coreReq_perfReq_loc;
  wire core_0$EN_coreIndInv_perfResp,
       core_0$EN_coreIndInv_terminate,
       core_0$EN_coreReq_perfReq,
       core_0$EN_coreReq_start,
       core_0$EN_dCacheToParent_fromP_enq,
       core_0$EN_dCacheToParent_rqToP_deq,
       core_0$EN_dCacheToParent_rsToP_deq,
       core_0$EN_deadlock_checkStarted_get,
       core_0$EN_deadlock_commitInstStuck_get,
       core_0$EN_deadlock_commitUserInstStuck_get,
       core_0$EN_deadlock_dCacheCRqStuck_get,
       core_0$EN_deadlock_dCachePRqStuck_get,
       core_0$EN_deadlock_iCacheCRqStuck_get,
       core_0$EN_deadlock_iCachePRqStuck_get,
       core_0$EN_deadlock_renameCorrectPathStuck_get,
       core_0$EN_deadlock_renameInstStuck_get,
       core_0$EN_iCacheToParent_fromP_enq,
       core_0$EN_iCacheToParent_rqToP_deq,
       core_0$EN_iCacheToParent_rsToP_deq,
       core_0$EN_mmioToPlatform_cRq_deq,
       core_0$EN_mmioToPlatform_cRs_deq,
       core_0$EN_mmioToPlatform_pRq_enq,
       core_0$EN_mmioToPlatform_pRs_enq,
       core_0$EN_mmioToPlatform_setTime,
       core_0$EN_recvDoStats,
       core_0$EN_renameDebug_renameErr_get,
       core_0$EN_sendDoStats,
       core_0$EN_setMEIP,
       core_0$EN_setSEIP,
       core_0$EN_tlbToMem_memReq_deq,
       core_0$EN_tlbToMem_respLd_enq,
       core_0$RDY_coreIndInv_terminate,
       core_0$RDY_dCacheToParent_fromP_enq,
       core_0$RDY_dCacheToParent_rqToP_deq,
       core_0$RDY_dCacheToParent_rqToP_first,
       core_0$RDY_dCacheToParent_rsToP_deq,
       core_0$RDY_dCacheToParent_rsToP_first,
       core_0$RDY_deadlock_checkStarted_get,
       core_0$RDY_deadlock_commitInstStuck_get,
       core_0$RDY_deadlock_commitUserInstStuck_get,
       core_0$RDY_deadlock_dCacheCRqStuck_get,
       core_0$RDY_deadlock_dCachePRqStuck_get,
       core_0$RDY_deadlock_iCacheCRqStuck_get,
       core_0$RDY_deadlock_iCachePRqStuck_get,
       core_0$RDY_deadlock_renameCorrectPathStuck_get,
       core_0$RDY_deadlock_renameInstStuck_get,
       core_0$RDY_iCacheToParent_fromP_enq,
       core_0$RDY_iCacheToParent_rqToP_deq,
       core_0$RDY_iCacheToParent_rqToP_first,
       core_0$RDY_iCacheToParent_rsToP_deq,
       core_0$RDY_iCacheToParent_rsToP_first,
       core_0$RDY_mmioToPlatform_cRq_deq,
       core_0$RDY_mmioToPlatform_cRq_first,
       core_0$RDY_mmioToPlatform_cRs_deq,
       core_0$RDY_mmioToPlatform_cRs_first,
       core_0$RDY_mmioToPlatform_pRq_enq,
       core_0$RDY_mmioToPlatform_pRs_enq,
       core_0$RDY_renameDebug_renameErr_get,
       core_0$RDY_sendDoStats,
       core_0$RDY_tlbToMem_memReq_deq,
       core_0$RDY_tlbToMem_memReq_first,
       core_0$RDY_tlbToMem_respLd_enq,
       core_0$coreReq_start_running,
       core_0$mmioToPlatform_cRq_notEmpty,
       core_0$mmioToPlatform_cRs_first,
       core_0$recvDoStats_x,
       core_0$sendDoStats,
       core_0$setMEIP_v,
       core_0$setSEIP_v;

  // ports of submodule enqDst_0_dummy2_0
  wire enqDst_0_dummy2_0$D_IN, enqDst_0_dummy2_0$EN, enqDst_0_dummy2_0$Q_OUT;

  // ports of submodule enqDst_0_dummy2_1
  wire enqDst_0_dummy2_1$D_IN, enqDst_0_dummy2_1$EN, enqDst_0_dummy2_1$Q_OUT;

  // ports of submodule enqDst_1_0_dummy2_0
  wire enqDst_1_0_dummy2_0$D_IN,
       enqDst_1_0_dummy2_0$EN,
       enqDst_1_0_dummy2_0$Q_OUT;

  // ports of submodule enqDst_1_0_dummy2_1
  wire enqDst_1_0_dummy2_1$D_IN,
       enqDst_1_0_dummy2_1$EN,
       enqDst_1_0_dummy2_1$Q_OUT;

  // ports of submodule llc
  reg [644 : 0] llc$dma_memReq_enq_x;
  wire [640 : 0] llc$to_mem_toM_first;
  wire [583 : 0] llc$to_child_toC_first;
  wire [579 : 0] llc$to_child_rsFromC_enq_x;
  wire [516 : 0] llc$dma_respLd_first, llc$to_mem_rsFromM_enq_x;
  wire [72 : 0] llc$to_child_rqFromC_enq_x;
  wire [4 : 0] llc$dma_respSt_first;
  wire [3 : 0] llc$perf_req_r;
  wire llc$EN_cRqStuck_get,
       llc$EN_dma_memReq_enq,
       llc$EN_dma_respLd_deq,
       llc$EN_dma_respSt_deq,
       llc$EN_perf_req,
       llc$EN_perf_resp,
       llc$EN_perf_setStatus,
       llc$EN_to_child_rqFromC_enq,
       llc$EN_to_child_rsFromC_enq,
       llc$EN_to_child_toC_deq,
       llc$EN_to_mem_rsFromM_enq,
       llc$EN_to_mem_toM_deq,
       llc$RDY_dma_memReq_enq,
       llc$RDY_dma_respLd_deq,
       llc$RDY_dma_respLd_first,
       llc$RDY_dma_respSt_deq,
       llc$RDY_dma_respSt_first,
       llc$RDY_to_child_rqFromC_enq,
       llc$RDY_to_child_rsFromC_enq,
       llc$RDY_to_child_toC_deq,
       llc$RDY_to_child_toC_first,
       llc$RDY_to_mem_rsFromM_enq,
       llc$RDY_to_mem_toM_deq,
       llc$RDY_to_mem_toM_first,
       llc$perf_setStatus_doStats;

  // ports of submodule llc_axi4_adapter_f_pending_reads
  wire [68 : 0] llc_axi4_adapter_f_pending_reads$D_IN,
		llc_axi4_adapter_f_pending_reads$D_OUT;
  wire llc_axi4_adapter_f_pending_reads$CLR,
       llc_axi4_adapter_f_pending_reads$DEQ,
       llc_axi4_adapter_f_pending_reads$EMPTY_N,
       llc_axi4_adapter_f_pending_reads$ENQ,
       llc_axi4_adapter_f_pending_reads$FULL_N;

  // ports of submodule llc_axi4_adapter_f_pending_writes
  wire [639 : 0] llc_axi4_adapter_f_pending_writes$D_IN;
  wire llc_axi4_adapter_f_pending_writes$CLR,
       llc_axi4_adapter_f_pending_writes$DEQ,
       llc_axi4_adapter_f_pending_writes$EMPTY_N,
       llc_axi4_adapter_f_pending_writes$ENQ,
       llc_axi4_adapter_f_pending_writes$FULL_N;

  // ports of submodule llc_mem_server_axi4_slave_xactor_f_rd_addr
  wire [96 : 0] llc_mem_server_axi4_slave_xactor_f_rd_addr$D_IN,
		llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT;
  wire llc_mem_server_axi4_slave_xactor_f_rd_addr$CLR,
       llc_mem_server_axi4_slave_xactor_f_rd_addr$DEQ,
       llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N,
       llc_mem_server_axi4_slave_xactor_f_rd_addr$ENQ,
       llc_mem_server_axi4_slave_xactor_f_rd_addr$FULL_N;

  // ports of submodule llc_mem_server_axi4_slave_xactor_f_rd_data
  wire [70 : 0] llc_mem_server_axi4_slave_xactor_f_rd_data$D_IN,
		llc_mem_server_axi4_slave_xactor_f_rd_data$D_OUT;
  wire llc_mem_server_axi4_slave_xactor_f_rd_data$CLR,
       llc_mem_server_axi4_slave_xactor_f_rd_data$DEQ,
       llc_mem_server_axi4_slave_xactor_f_rd_data$EMPTY_N,
       llc_mem_server_axi4_slave_xactor_f_rd_data$ENQ,
       llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N;

  // ports of submodule llc_mem_server_axi4_slave_xactor_f_wr_addr
  wire [96 : 0] llc_mem_server_axi4_slave_xactor_f_wr_addr$D_IN,
		llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT;
  wire llc_mem_server_axi4_slave_xactor_f_wr_addr$CLR,
       llc_mem_server_axi4_slave_xactor_f_wr_addr$DEQ,
       llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N,
       llc_mem_server_axi4_slave_xactor_f_wr_addr$ENQ,
       llc_mem_server_axi4_slave_xactor_f_wr_addr$FULL_N;

  // ports of submodule llc_mem_server_axi4_slave_xactor_f_wr_data
  wire [72 : 0] llc_mem_server_axi4_slave_xactor_f_wr_data$D_IN,
		llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT;
  wire llc_mem_server_axi4_slave_xactor_f_wr_data$CLR,
       llc_mem_server_axi4_slave_xactor_f_wr_data$DEQ,
       llc_mem_server_axi4_slave_xactor_f_wr_data$EMPTY_N,
       llc_mem_server_axi4_slave_xactor_f_wr_data$ENQ,
       llc_mem_server_axi4_slave_xactor_f_wr_data$FULL_N;

  // ports of submodule llc_mem_server_axi4_slave_xactor_f_wr_resp
  wire [5 : 0] llc_mem_server_axi4_slave_xactor_f_wr_resp$D_IN,
	       llc_mem_server_axi4_slave_xactor_f_wr_resp$D_OUT;
  wire llc_mem_server_axi4_slave_xactor_f_wr_resp$CLR,
       llc_mem_server_axi4_slave_xactor_f_wr_resp$DEQ,
       llc_mem_server_axi4_slave_xactor_f_wr_resp$EMPTY_N,
       llc_mem_server_axi4_slave_xactor_f_wr_resp$ENQ,
       llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N;

  // ports of submodule llc_mem_server_enqDst_0_dummy2_0
  wire llc_mem_server_enqDst_0_dummy2_0$D_IN,
       llc_mem_server_enqDst_0_dummy2_0$EN,
       llc_mem_server_enqDst_0_dummy2_0$Q_OUT;

  // ports of submodule llc_mem_server_enqDst_0_dummy2_1
  wire llc_mem_server_enqDst_0_dummy2_1$D_IN,
       llc_mem_server_enqDst_0_dummy2_1$EN,
       llc_mem_server_enqDst_0_dummy2_1$Q_OUT;

  // ports of submodule llc_mem_server_f_dword_in_line
  wire [2 : 0] llc_mem_server_f_dword_in_line$D_IN;
  wire llc_mem_server_f_dword_in_line$CLR,
       llc_mem_server_f_dword_in_line$DEQ,
       llc_mem_server_f_dword_in_line$ENQ;

  // ports of submodule llc_mem_server_propDstData_0_dummy2_0
  wire llc_mem_server_propDstData_0_dummy2_0$D_IN,
       llc_mem_server_propDstData_0_dummy2_0$EN;

  // ports of submodule llc_mem_server_propDstData_0_dummy2_1
  wire llc_mem_server_propDstData_0_dummy2_1$D_IN,
       llc_mem_server_propDstData_0_dummy2_1$EN,
       llc_mem_server_propDstData_0_dummy2_1$Q_OUT;

  // ports of submodule llc_mem_server_propDstIdx_0_dummy2_0
  wire llc_mem_server_propDstIdx_0_dummy2_0$D_IN,
       llc_mem_server_propDstIdx_0_dummy2_0$EN,
       llc_mem_server_propDstIdx_0_dummy2_0$Q_OUT;

  // ports of submodule llc_mem_server_propDstIdx_0_dummy2_1
  wire llc_mem_server_propDstIdx_0_dummy2_1$D_IN,
       llc_mem_server_propDstIdx_0_dummy2_1$EN,
       llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT;

  // ports of submodule llc_mem_server_tlbQ
  wire [64 : 0] llc_mem_server_tlbQ$D_IN, llc_mem_server_tlbQ$D_OUT;
  wire llc_mem_server_tlbQ$CLR,
       llc_mem_server_tlbQ$DEQ,
       llc_mem_server_tlbQ$EMPTY_N,
       llc_mem_server_tlbQ$ENQ,
       llc_mem_server_tlbQ$FULL_N;

  // ports of submodule mmioPlatform_fromHostQ_clearReq_dummy2_0
  wire mmioPlatform_fromHostQ_clearReq_dummy2_0$D_IN,
       mmioPlatform_fromHostQ_clearReq_dummy2_0$EN;

  // ports of submodule mmioPlatform_fromHostQ_clearReq_dummy2_1
  wire mmioPlatform_fromHostQ_clearReq_dummy2_1$D_IN,
       mmioPlatform_fromHostQ_clearReq_dummy2_1$EN,
       mmioPlatform_fromHostQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule mmioPlatform_fromHostQ_deqReq_dummy2_0
  wire mmioPlatform_fromHostQ_deqReq_dummy2_0$D_IN,
       mmioPlatform_fromHostQ_deqReq_dummy2_0$EN;

  // ports of submodule mmioPlatform_fromHostQ_deqReq_dummy2_1
  wire mmioPlatform_fromHostQ_deqReq_dummy2_1$D_IN,
       mmioPlatform_fromHostQ_deqReq_dummy2_1$EN;

  // ports of submodule mmioPlatform_fromHostQ_deqReq_dummy2_2
  wire mmioPlatform_fromHostQ_deqReq_dummy2_2$D_IN,
       mmioPlatform_fromHostQ_deqReq_dummy2_2$EN,
       mmioPlatform_fromHostQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule mmioPlatform_fromHostQ_enqReq_dummy2_0
  wire mmioPlatform_fromHostQ_enqReq_dummy2_0$D_IN,
       mmioPlatform_fromHostQ_enqReq_dummy2_0$EN;

  // ports of submodule mmioPlatform_fromHostQ_enqReq_dummy2_1
  wire mmioPlatform_fromHostQ_enqReq_dummy2_1$D_IN,
       mmioPlatform_fromHostQ_enqReq_dummy2_1$EN;

  // ports of submodule mmioPlatform_fromHostQ_enqReq_dummy2_2
  wire mmioPlatform_fromHostQ_enqReq_dummy2_2$D_IN,
       mmioPlatform_fromHostQ_enqReq_dummy2_2$EN,
       mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule mmioPlatform_toHostQ_clearReq_dummy2_0
  wire mmioPlatform_toHostQ_clearReq_dummy2_0$D_IN,
       mmioPlatform_toHostQ_clearReq_dummy2_0$EN;

  // ports of submodule mmioPlatform_toHostQ_clearReq_dummy2_1
  wire mmioPlatform_toHostQ_clearReq_dummy2_1$D_IN,
       mmioPlatform_toHostQ_clearReq_dummy2_1$EN,
       mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule mmioPlatform_toHostQ_deqReq_dummy2_0
  wire mmioPlatform_toHostQ_deqReq_dummy2_0$D_IN,
       mmioPlatform_toHostQ_deqReq_dummy2_0$EN;

  // ports of submodule mmioPlatform_toHostQ_deqReq_dummy2_1
  wire mmioPlatform_toHostQ_deqReq_dummy2_1$D_IN,
       mmioPlatform_toHostQ_deqReq_dummy2_1$EN;

  // ports of submodule mmioPlatform_toHostQ_deqReq_dummy2_2
  wire mmioPlatform_toHostQ_deqReq_dummy2_2$D_IN,
       mmioPlatform_toHostQ_deqReq_dummy2_2$EN,
       mmioPlatform_toHostQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule mmioPlatform_toHostQ_enqReq_dummy2_0
  wire mmioPlatform_toHostQ_enqReq_dummy2_0$D_IN,
       mmioPlatform_toHostQ_enqReq_dummy2_0$EN;

  // ports of submodule mmioPlatform_toHostQ_enqReq_dummy2_1
  wire mmioPlatform_toHostQ_enqReq_dummy2_1$D_IN,
       mmioPlatform_toHostQ_enqReq_dummy2_1$EN;

  // ports of submodule mmioPlatform_toHostQ_enqReq_dummy2_2
  wire mmioPlatform_toHostQ_enqReq_dummy2_2$D_IN,
       mmioPlatform_toHostQ_enqReq_dummy2_2$EN,
       mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_axi4_adapter_f_reqs_from_core
  reg [141 : 0] mmio_axi4_adapter_f_reqs_from_core$D_IN;
  wire [141 : 0] mmio_axi4_adapter_f_reqs_from_core$D_OUT;
  wire mmio_axi4_adapter_f_reqs_from_core$CLR,
       mmio_axi4_adapter_f_reqs_from_core$DEQ,
       mmio_axi4_adapter_f_reqs_from_core$EMPTY_N,
       mmio_axi4_adapter_f_reqs_from_core$ENQ,
       mmio_axi4_adapter_f_reqs_from_core$FULL_N;

  // ports of submodule mmio_axi4_adapter_f_rsps_to_core
  reg [64 : 0] mmio_axi4_adapter_f_rsps_to_core$D_IN;
  wire [64 : 0] mmio_axi4_adapter_f_rsps_to_core$D_OUT;
  wire mmio_axi4_adapter_f_rsps_to_core$CLR,
       mmio_axi4_adapter_f_rsps_to_core$DEQ,
       mmio_axi4_adapter_f_rsps_to_core$EMPTY_N,
       mmio_axi4_adapter_f_rsps_to_core$ENQ,
       mmio_axi4_adapter_f_rsps_to_core$FULL_N;

  // ports of submodule mmio_axi4_adapter_soc_map
  wire [63 : 0] mmio_axi4_adapter_soc_map$m_is_IO_addr_addr,
		mmio_axi4_adapter_soc_map$m_is_mem_addr_addr,
		mmio_axi4_adapter_soc_map$m_is_near_mem_IO_addr_addr;
  wire mmio_axi4_adapter_soc_map$m_is_IO_addr;

  // ports of submodule propDstData_0_dummy2_0
  wire propDstData_0_dummy2_0$D_IN, propDstData_0_dummy2_0$EN;

  // ports of submodule propDstData_0_dummy2_1
  wire propDstData_0_dummy2_1$D_IN,
       propDstData_0_dummy2_1$EN,
       propDstData_0_dummy2_1$Q_OUT;

  // ports of submodule propDstData_1_0_dummy2_0
  wire propDstData_1_0_dummy2_0$D_IN, propDstData_1_0_dummy2_0$EN;

  // ports of submodule propDstData_1_0_dummy2_1
  wire propDstData_1_0_dummy2_1$D_IN,
       propDstData_1_0_dummy2_1$EN,
       propDstData_1_0_dummy2_1$Q_OUT;

  // ports of submodule propDstData_1_1_dummy2_0
  wire propDstData_1_1_dummy2_0$D_IN, propDstData_1_1_dummy2_0$EN;

  // ports of submodule propDstData_1_1_dummy2_1
  wire propDstData_1_1_dummy2_1$D_IN,
       propDstData_1_1_dummy2_1$EN,
       propDstData_1_1_dummy2_1$Q_OUT;

  // ports of submodule propDstData_1_dummy2_0
  wire propDstData_1_dummy2_0$D_IN, propDstData_1_dummy2_0$EN;

  // ports of submodule propDstData_1_dummy2_1
  wire propDstData_1_dummy2_1$D_IN,
       propDstData_1_dummy2_1$EN,
       propDstData_1_dummy2_1$Q_OUT;

  // ports of submodule propDstIdx_0_dummy2_0
  wire propDstIdx_0_dummy2_0$D_IN,
       propDstIdx_0_dummy2_0$EN,
       propDstIdx_0_dummy2_0$Q_OUT;

  // ports of submodule propDstIdx_0_dummy2_1
  wire propDstIdx_0_dummy2_1$D_IN,
       propDstIdx_0_dummy2_1$EN,
       propDstIdx_0_dummy2_1$Q_OUT;

  // ports of submodule propDstIdx_1_0_dummy2_0
  wire propDstIdx_1_0_dummy2_0$D_IN,
       propDstIdx_1_0_dummy2_0$EN,
       propDstIdx_1_0_dummy2_0$Q_OUT;

  // ports of submodule propDstIdx_1_0_dummy2_1
  wire propDstIdx_1_0_dummy2_1$D_IN,
       propDstIdx_1_0_dummy2_1$EN,
       propDstIdx_1_0_dummy2_1$Q_OUT;

  // ports of submodule propDstIdx_1_1_dummy2_0
  wire propDstIdx_1_1_dummy2_0$D_IN,
       propDstIdx_1_1_dummy2_0$EN,
       propDstIdx_1_1_dummy2_0$Q_OUT;

  // ports of submodule propDstIdx_1_1_dummy2_1
  wire propDstIdx_1_1_dummy2_1$D_IN,
       propDstIdx_1_1_dummy2_1$EN,
       propDstIdx_1_1_dummy2_1$Q_OUT;

  // ports of submodule propDstIdx_1_dummy2_0
  wire propDstIdx_1_dummy2_0$D_IN,
       propDstIdx_1_dummy2_0$EN,
       propDstIdx_1_dummy2_0$Q_OUT;

  // ports of submodule propDstIdx_1_dummy2_1
  wire propDstIdx_1_dummy2_1$D_IN,
       propDstIdx_1_dummy2_1$EN,
       propDstIdx_1_dummy2_1$Q_OUT;

  // rule scheduling signals
  wire CAN_FIRE_RL_broadcastStats,
       CAN_FIRE_RL_doEnq,
       CAN_FIRE_RL_doEnq_1,
       CAN_FIRE_RL_dstSelectSrc,
       CAN_FIRE_RL_dstSelectSrc_1,
       CAN_FIRE_RL_enqDst_0_canon,
       CAN_FIRE_RL_enqDst_1_0_canon,
       CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp,
       CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req,
       CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps,
       CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req,
       CAN_FIRE_RL_llc_mem_server_doEnq,
       CAN_FIRE_RL_llc_mem_server_dstSelectSrc,
       CAN_FIRE_RL_llc_mem_server_enqDst_0_canon,
       CAN_FIRE_RL_llc_mem_server_propDstData_0_canon,
       CAN_FIRE_RL_llc_mem_server_propDstIdx_0_canon,
       CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish,
       CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld,
       CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st,
       CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged,
       CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay,
       CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish,
       CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss,
       CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss,
       CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req,
       CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req,
       CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb,
       CAN_FIRE_RL_llc_mem_server_sendStRespToTlb,
       CAN_FIRE_RL_llc_mem_server_sendTlbReqToLLC,
       CAN_FIRE_RL_llc_mem_server_srcPropose,
       CAN_FIRE_RL_mmioPlatform_fromHostQ_canonicalize,
       CAN_FIRE_RL_mmioPlatform_fromHostQ_clearReq_canon,
       CAN_FIRE_RL_mmioPlatform_fromHostQ_deqReq_canon,
       CAN_FIRE_RL_mmioPlatform_fromHostQ_enqReq_canon,
       CAN_FIRE_RL_mmioPlatform_incCycle,
       CAN_FIRE_RL_mmioPlatform_incTime,
       CAN_FIRE_RL_mmioPlatform_processFromHost,
       CAN_FIRE_RL_mmioPlatform_processMSIP,
       CAN_FIRE_RL_mmioPlatform_processMTime,
       CAN_FIRE_RL_mmioPlatform_processMTimeCmp,
       CAN_FIRE_RL_mmioPlatform_processToHost,
       CAN_FIRE_RL_mmioPlatform_propagateTime,
       CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp,
       CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp,
       CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp,
       CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req,
       CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req,
       CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req,
       CAN_FIRE_RL_mmioPlatform_selectReq,
       CAN_FIRE_RL_mmioPlatform_toHostQ_canonicalize,
       CAN_FIRE_RL_mmioPlatform_toHostQ_clearReq_canon,
       CAN_FIRE_RL_mmioPlatform_toHostQ_deqReq_canon,
       CAN_FIRE_RL_mmioPlatform_toHostQ_enqReq_canon,
       CAN_FIRE_RL_mmioPlatform_waitMSIPDone,
       CAN_FIRE_RL_mmioPlatform_waitMTimeCmpDone,
       CAN_FIRE_RL_mmioPlatform_waitMTimeDone,
       CAN_FIRE_RL_mmioPlatform_waitTimerInterruptDone,
       CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp,
       CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St,
       CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req,
       CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps,
       CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req,
       CAN_FIRE_RL_propDstData_0_canon,
       CAN_FIRE_RL_propDstData_1_0_canon,
       CAN_FIRE_RL_propDstData_1_1_canon,
       CAN_FIRE_RL_propDstData_1_canon,
       CAN_FIRE_RL_propDstIdx_0_canon,
       CAN_FIRE_RL_propDstIdx_1_0_canon,
       CAN_FIRE_RL_propDstIdx_1_1_canon,
       CAN_FIRE_RL_propDstIdx_1_canon,
       CAN_FIRE_RL_rl_dummy1,
       CAN_FIRE_RL_rl_dummy2,
       CAN_FIRE_RL_rl_dummy20,
       CAN_FIRE_RL_rl_dummy3,
       CAN_FIRE_RL_rl_dummy4,
       CAN_FIRE_RL_rl_dummy5,
       CAN_FIRE_RL_rl_dummy6,
       CAN_FIRE_RL_rl_dummy7,
       CAN_FIRE_RL_rl_dummy8,
       CAN_FIRE_RL_rl_dummy9,
       CAN_FIRE_RL_rl_terminate,
       CAN_FIRE_RL_rl_tohost,
       CAN_FIRE_RL_sendPRq,
       CAN_FIRE_RL_sendPRq_1,
       CAN_FIRE_RL_sendPRs,
       CAN_FIRE_RL_sendPRs_1,
       CAN_FIRE_RL_srcPropose,
       CAN_FIRE_RL_srcPropose_1,
       CAN_FIRE_RL_srcPropose_2,
       CAN_FIRE_RL_srcPropose_3,
       CAN_FIRE_debug_module_mem_server_m_arvalid,
       CAN_FIRE_debug_module_mem_server_m_awvalid,
       CAN_FIRE_debug_module_mem_server_m_bready,
       CAN_FIRE_debug_module_mem_server_m_rready,
       CAN_FIRE_debug_module_mem_server_m_wvalid,
       CAN_FIRE_m_external_interrupt_req,
       CAN_FIRE_master0_m_arready,
       CAN_FIRE_master0_m_awready,
       CAN_FIRE_master0_m_bvalid,
       CAN_FIRE_master0_m_rvalid,
       CAN_FIRE_master0_m_wready,
       CAN_FIRE_master1_m_arready,
       CAN_FIRE_master1_m_awready,
       CAN_FIRE_master1_m_bvalid,
       CAN_FIRE_master1_m_rvalid,
       CAN_FIRE_master1_m_wready,
       CAN_FIRE_non_maskable_interrupt_req,
       CAN_FIRE_s_external_interrupt_req,
       CAN_FIRE_set_verbosity,
       CAN_FIRE_start,
       WILL_FIRE_RL_broadcastStats,
       WILL_FIRE_RL_doEnq,
       WILL_FIRE_RL_doEnq_1,
       WILL_FIRE_RL_dstSelectSrc,
       WILL_FIRE_RL_dstSelectSrc_1,
       WILL_FIRE_RL_enqDst_0_canon,
       WILL_FIRE_RL_enqDst_1_0_canon,
       WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp,
       WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req,
       WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps,
       WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req,
       WILL_FIRE_RL_llc_mem_server_doEnq,
       WILL_FIRE_RL_llc_mem_server_dstSelectSrc,
       WILL_FIRE_RL_llc_mem_server_enqDst_0_canon,
       WILL_FIRE_RL_llc_mem_server_propDstData_0_canon,
       WILL_FIRE_RL_llc_mem_server_propDstIdx_0_canon,
       WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish,
       WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld,
       WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st,
       WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged,
       WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay,
       WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish,
       WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss,
       WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss,
       WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req,
       WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req,
       WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb,
       WILL_FIRE_RL_llc_mem_server_sendStRespToTlb,
       WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC,
       WILL_FIRE_RL_llc_mem_server_srcPropose,
       WILL_FIRE_RL_mmioPlatform_fromHostQ_canonicalize,
       WILL_FIRE_RL_mmioPlatform_fromHostQ_clearReq_canon,
       WILL_FIRE_RL_mmioPlatform_fromHostQ_deqReq_canon,
       WILL_FIRE_RL_mmioPlatform_fromHostQ_enqReq_canon,
       WILL_FIRE_RL_mmioPlatform_incCycle,
       WILL_FIRE_RL_mmioPlatform_incTime,
       WILL_FIRE_RL_mmioPlatform_processFromHost,
       WILL_FIRE_RL_mmioPlatform_processMSIP,
       WILL_FIRE_RL_mmioPlatform_processMTime,
       WILL_FIRE_RL_mmioPlatform_processMTimeCmp,
       WILL_FIRE_RL_mmioPlatform_processToHost,
       WILL_FIRE_RL_mmioPlatform_propagateTime,
       WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp,
       WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp,
       WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp,
       WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req,
       WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req,
       WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req,
       WILL_FIRE_RL_mmioPlatform_selectReq,
       WILL_FIRE_RL_mmioPlatform_toHostQ_canonicalize,
       WILL_FIRE_RL_mmioPlatform_toHostQ_clearReq_canon,
       WILL_FIRE_RL_mmioPlatform_toHostQ_deqReq_canon,
       WILL_FIRE_RL_mmioPlatform_toHostQ_enqReq_canon,
       WILL_FIRE_RL_mmioPlatform_waitMSIPDone,
       WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone,
       WILL_FIRE_RL_mmioPlatform_waitMTimeDone,
       WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone,
       WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp,
       WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St,
       WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req,
       WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps,
       WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req,
       WILL_FIRE_RL_propDstData_0_canon,
       WILL_FIRE_RL_propDstData_1_0_canon,
       WILL_FIRE_RL_propDstData_1_1_canon,
       WILL_FIRE_RL_propDstData_1_canon,
       WILL_FIRE_RL_propDstIdx_0_canon,
       WILL_FIRE_RL_propDstIdx_1_0_canon,
       WILL_FIRE_RL_propDstIdx_1_1_canon,
       WILL_FIRE_RL_propDstIdx_1_canon,
       WILL_FIRE_RL_rl_dummy1,
       WILL_FIRE_RL_rl_dummy2,
       WILL_FIRE_RL_rl_dummy20,
       WILL_FIRE_RL_rl_dummy3,
       WILL_FIRE_RL_rl_dummy4,
       WILL_FIRE_RL_rl_dummy5,
       WILL_FIRE_RL_rl_dummy6,
       WILL_FIRE_RL_rl_dummy7,
       WILL_FIRE_RL_rl_dummy8,
       WILL_FIRE_RL_rl_dummy9,
       WILL_FIRE_RL_rl_terminate,
       WILL_FIRE_RL_rl_tohost,
       WILL_FIRE_RL_sendPRq,
       WILL_FIRE_RL_sendPRq_1,
       WILL_FIRE_RL_sendPRs,
       WILL_FIRE_RL_sendPRs_1,
       WILL_FIRE_RL_srcPropose,
       WILL_FIRE_RL_srcPropose_1,
       WILL_FIRE_RL_srcPropose_2,
       WILL_FIRE_RL_srcPropose_3,
       WILL_FIRE_debug_module_mem_server_m_arvalid,
       WILL_FIRE_debug_module_mem_server_m_awvalid,
       WILL_FIRE_debug_module_mem_server_m_bready,
       WILL_FIRE_debug_module_mem_server_m_rready,
       WILL_FIRE_debug_module_mem_server_m_wvalid,
       WILL_FIRE_m_external_interrupt_req,
       WILL_FIRE_master0_m_arready,
       WILL_FIRE_master0_m_awready,
       WILL_FIRE_master0_m_bvalid,
       WILL_FIRE_master0_m_rvalid,
       WILL_FIRE_master0_m_wready,
       WILL_FIRE_master1_m_arready,
       WILL_FIRE_master1_m_awready,
       WILL_FIRE_master1_m_bvalid,
       WILL_FIRE_master1_m_rvalid,
       WILL_FIRE_master1_m_wready,
       WILL_FIRE_non_maskable_interrupt_req,
       WILL_FIRE_s_external_interrupt_req,
       WILL_FIRE_set_verbosity,
       WILL_FIRE_start;

  // inputs to muxes for submodule ports
  reg [1 : 0] MUX_mmioPlatform_state$write_1__VAL_3,
	      MUX_mmioPlatform_state$write_1__VAL_4;
  wire [644 : 0] MUX_llc$dma_memReq_enq_1__VAL_1,
		 MUX_llc$dma_memReq_enq_1__VAL_2,
		 MUX_llc$dma_memReq_enq_1__VAL_3,
		 MUX_llc$dma_memReq_enq_1__VAL_4;
  wire [582 : 0] MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1,
		 MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2;
  wire [511 : 0] MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1;
  wire [141 : 0] MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1,
		 MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2,
		 MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3,
		 MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4;
  wire [66 : 0] MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_1,
		MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10,
		MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_2,
		MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3,
		MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4,
		MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5,
		MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6,
		MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7,
		MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8,
		MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9,
		MUX_mmioPlatform_curReq$write_1__VAL_1,
		MUX_mmioPlatform_curReq$write_1__VAL_2;
  wire [64 : 0] MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1,
		MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3;
  wire [63 : 0] MUX_mmioPlatform_amoResp$write_1__VAL_1,
		MUX_mmioPlatform_amoResp$write_1__VAL_2,
		MUX_mmioPlatform_mtime$write_1__VAL_2;
  wire [38 : 0] MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2,
		MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3,
		MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4;
  wire [9 : 0] MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2;
  wire [6 : 0] MUX_mmioPlatform_cycle$write_1__VAL_1;
  wire [1 : 0] MUX_mmioPlatform_state$write_1__VAL_1,
	       MUX_mmioPlatform_state$write_1__VAL_2,
	       MUX_mmioPlatform_state$write_1__VAL_5;
  wire MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1,
       MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2,
       MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3,
       MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4,
       MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1,
       MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2,
       MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3,
       MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4,
       MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5,
       MUX_llc$dma_memReq_enq_1__SEL_1,
       MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2,
       MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3,
       MUX_mmioPlatform_amoResp$write_1__SEL_1,
       MUX_mmioPlatform_amoResp$write_1__SEL_2,
       MUX_mmioPlatform_curReq$write_1__SEL_1,
       MUX_mmioPlatform_fetchingWay$write_1__SEL_1,
       MUX_mmioPlatform_fetchingWay$write_1__VAL_2,
       MUX_mmioPlatform_instSel$write_1__VAL_2,
       MUX_mmioPlatform_mtip_0$write_1__VAL_2,
       MUX_mmioPlatform_state$write_1__SEL_6,
       MUX_mmioPlatform_state$write_1__SEL_7,
       MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2,
       MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__SEL_1,
       MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__PSEL_1,
       MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1,
       MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2;

  // declarations used by system tasks
  // synopsys translate_off
  reg [31 : 0] v__h163696;
  reg [31 : 0] v__h163258;
  reg [31 : 0] v__h5308;
  reg [31 : 0] v__h5481;
  reg [31 : 0] v__h5741;
  reg [31 : 0] v__h7883;
  reg [31 : 0] v__h8098;
  reg [31 : 0] v__h2458;
  reg [31 : 0] v__h4131;
  reg [31 : 0] v__h9268;
  reg [31 : 0] v__h9761;
  reg [31 : 0] v__h9924;
  reg [31 : 0] v__h135215;
  reg [31 : 0] v__h135382;
  reg [31 : 0] v__h137485;
  reg [31 : 0] v__h154829;
  reg [31 : 0] v__h134596;
  reg [31 : 0] v__h161523;
  reg [31 : 0] v__h162031;
  reg [31 : 0] v__h2452;
  reg [31 : 0] v__h4125;
  reg [31 : 0] v__h5302;
  reg [31 : 0] v__h5475;
  reg [31 : 0] v__h5735;
  reg [31 : 0] v__h7877;
  reg [31 : 0] v__h8092;
  reg [31 : 0] v__h9262;
  reg [31 : 0] v__h9755;
  reg [31 : 0] v__h9918;
  reg [31 : 0] v__h134590;
  reg [31 : 0] v__h135209;
  reg [31 : 0] v__h135376;
  reg [31 : 0] v__h137479;
  reg [31 : 0] v__h154823;
  reg [31 : 0] v__h161517;
  reg [31 : 0] v__h162025;
  reg [31 : 0] v__h163252;
  reg [31 : 0] v__h163690;
  // synopsys translate_on

  // remaining internal signals
  reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5,
	       CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6,
	       CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9,
	       CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16,
	       CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17,
	       CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18,
	       CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19,
	       CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20,
	       CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21,
	       CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22,
	       CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23,
	       CASE_x0299_0_n__read_addr0477_1_n__read_addr05_ETC__q26,
	       CASE_x1414_0_n__read_addr1596_1_n__read_addr16_ETC__q15,
	       IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809,
	       IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822,
	       IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861,
	       IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873,
	       IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943,
	       IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952,
	       IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919,
	       IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887,
	       IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889,
	       data64__h148655,
	       dword__h94457,
	       ld_data__h132744,
	       old_dword__h90147,
	       w1__h48014,
	       w1__h48019,
	       w2__h48015,
	       w2__h48021,
	       x__h48010;
  reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987;
  reg [7 : 0] strb8__h148656;
  reg [5 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477;
  reg [2 : 0] x__h61728;
  reg [1 : 0] CASE_x0299_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24,
	      CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13,
	      CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14;
  reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10,
      CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11,
      CASE_x0299_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25,
      CASE_x1414_0_propDstData_0_dummy2_1_read__100__ETC__q12,
      SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093,
      SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367,
      x__h61735,
      x__h82715;
  wire [579 : 0] IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1318;
  wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466;
  wire [513 : 0] IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1317;
  wire [511 : 0] IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309,
		 SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459,
		 new_cline__h135518;
  wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596,
		 SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442;
  wire [255 : 0] IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591,
		 SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425;
  wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408;
  wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401;
  wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680;
  wire [64 : 0] IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d722;
  wire [63 : 0] IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1289,
		IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829,
		IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880,
		IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573,
		IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637,
		IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548,
		IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610,
		IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d714,
		IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574,
		IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638,
		IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203,
		IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241,
		data__h31738,
		failed_testnum__h163301,
		line_addr__h102521,
		line_addr__h102607,
		mask__h90144,
		mem_req_rd_addr_araddr__h134816,
		mem_req_wr_addr_awaddr__h148740,
		mmioPlatform_fromHostQ_data_0__h42585,
		mmioPlatform_mtime__h37052,
		mmioPlatform_reqData__h48606,
		n__read_addr__h61596,
		n__read_addr__h61681,
		n__read_addr__h80477,
		n__read_addr__h80556,
		n__read_snd_addr__h124048,
		newData__h31819,
		newData__h34749,
		new_dword__h90148,
		op_result__h48622,
		op_result__h49152,
		op_result__h49157,
		op_result__h49162,
		op_result__h49167,
		op_result__h49173,
		op_result__h49180,
		op_result__h49186,
		result__h48065,
		result__h48189,
		result__h48217,
		result__h48245,
		result__h48273,
		result__h48301,
		result__h48329,
		result__h48357,
		result__h48385,
		result__h48430,
		result__h48458,
		result__h48486,
		result__h48514,
		result__h48555,
		result__h48583,
		result__h48709,
		result__h48736,
		result__h48763,
		result__h48790,
		result__h48817,
		result__h48844,
		result__h48871,
		result__h48898,
		result__h48942,
		result__h48969,
		result__h48996,
		result__h49023,
		result__h49063,
		result__h49090,
		result__h49207,
		result__h49273,
		result__h49339,
		result__h49405,
		result__h49471,
		result__h49537,
		result__h49603,
		result__h49665,
		result__h49710,
		result__h49776,
		result__h49842,
		result__h49900,
		result__h49945,
		w1___1__h48124,
		w2___1__h48125,
		x1_avValue_data__h40257,
		x1_avValue_data__h44943,
		x__h31930,
		x__h34840,
		x__h37200,
		x__h40775,
		x__h40786,
		x__h42868,
		x__h42879,
		x__h50122,
		x__h91310,
		y__h91311,
		y__h91312;
  wire [47 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540,
		IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605,
		IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d709;
  wire [31 : 0] IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531,
		IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600,
		IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d704,
		IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d995,
		mmioPlatform_mtime_BITS_31_TO_0__q4,
		mmioPlatform_mtime_BITS_63_TO_32__q3,
		mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2,
		mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1,
		v__h31531,
		v__h31568,
		w18014_BITS_31_TO_0__q7,
		w28015_BITS_31_TO_0__q8,
		x_data__h30321;
  wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164;
  wire [5 : 0] x__h134851, x__h148765;
  wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163;
  wire [3 : 0] b__h134523, b__h2352;
  wire [2 : 0] n__read_id__h61600, n__read_id__h61685, x__h7713;
  wire [1 : 0] IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294,
	       IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116,
	       IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126,
	       IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208,
	       IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246,
	       IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120,
	       IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130;
  wire IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555,
       IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452,
       IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550,
       IF_NOT_propDstIdx_0_dummy2_1_read__062_063_OR__ETC___d1097,
       IF_NOT_propDstIdx_1_0_dummy2_1_read__326_327_O_ETC___d1371,
       IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169,
       IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471,
       IF_enqDst_0_lat_0_whas__038_THEN_enqDst_0_lat__ETC___d1043,
       IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1279,
       IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1299,
       IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315,
       IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681,
       IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664,
       IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621,
       IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453,
       IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200,
       IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496,
       IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d974,
       IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d103,
       IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229,
       IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267,
       IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012,
       IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186,
       IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193,
       IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019,
       NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099,
       NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373,
       NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797,
       NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714,
       NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750,
       NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d758,
       NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d763,
       NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d773,
       NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d964,
       NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d977,
       NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d318,
       NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d339,
       NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370,
       NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486,
       NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581,
       NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644,
       NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d240,
       NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d261,
       NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386,
       NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388,
       NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096,
       NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370,
       NOT_propDstIdx_1_1_dummy2_1_read__344_345_OR_I_ETC___d1477,
       NOT_propDstIdx_1_dummy2_1_read__075_076_OR_IF__ETC___d1175,
       llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608,
       llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530,
       mmioPlatform_cycle_47_ULT_99___d348,
       mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979,
       mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331,
       mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612,
       mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357,
       mmioPlatform_reqBE_BIT_0___h29946,
       mmioPlatform_reqBE_BIT_4___h29906,
       mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463,
       mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567,
       mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632,
       mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253,
       mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9,
       n__read_child__h61601,
       n__read_child__h61686,
       n__read_child__h80480,
       n__read_child__h80559,
       n__read_snd_id__h124049,
       propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136,
       propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140,
       x__h61414,
       x__h75228,
       x__h80299;

  // action method start
  assign RDY_start = mmioPlatform_state == 2'd0 ;
  assign CAN_FIRE_start = mmioPlatform_state == 2'd0 ;
  assign WILL_FIRE_start = EN_start ;

  // value method master0_m_awvalid
  assign master0_awvalid = llc_axi4_adapter_master_xactor_crg_wr_addr_full ;

  // value method master0_m_awid
  assign master0_awid = llc_axi4_adapter_master_xactor_rg_wr_addr[96:93] ;

  // value method master0_m_awaddr
  assign master0_awaddr = llc_axi4_adapter_master_xactor_rg_wr_addr[92:29] ;

  // value method master0_m_awlen
  assign master0_awlen = llc_axi4_adapter_master_xactor_rg_wr_addr[28:21] ;

  // value method master0_m_awsize
  assign master0_awsize = llc_axi4_adapter_master_xactor_rg_wr_addr[20:18] ;

  // value method master0_m_awburst
  assign master0_awburst = llc_axi4_adapter_master_xactor_rg_wr_addr[17:16] ;

  // value method master0_m_awlock
  assign master0_awlock = llc_axi4_adapter_master_xactor_rg_wr_addr[15] ;

  // value method master0_m_awcache
  assign master0_awcache = llc_axi4_adapter_master_xactor_rg_wr_addr[14:11] ;

  // value method master0_m_awprot
  assign master0_awprot = llc_axi4_adapter_master_xactor_rg_wr_addr[10:8] ;

  // value method master0_m_awqos
  assign master0_awqos = llc_axi4_adapter_master_xactor_rg_wr_addr[7:4] ;

  // value method master0_m_awregion
  assign master0_awregion = llc_axi4_adapter_master_xactor_rg_wr_addr[3:0] ;

  // action method master0_m_awready
  assign CAN_FIRE_master0_m_awready = 1'd1 ;
  assign WILL_FIRE_master0_m_awready = 1'd1 ;

  // value method master0_m_wvalid
  assign master0_wvalid = llc_axi4_adapter_master_xactor_crg_wr_data_full ;

  // value method master0_m_wdata
  assign master0_wdata = llc_axi4_adapter_master_xactor_rg_wr_data[72:9] ;

  // value method master0_m_wstrb
  assign master0_wstrb = llc_axi4_adapter_master_xactor_rg_wr_data[8:1] ;

  // value method master0_m_wlast
  assign master0_wlast = llc_axi4_adapter_master_xactor_rg_wr_data[0] ;

  // action method master0_m_wready
  assign CAN_FIRE_master0_m_wready = 1'd1 ;
  assign WILL_FIRE_master0_m_wready = 1'd1 ;

  // action method master0_m_bvalid
  assign CAN_FIRE_master0_m_bvalid = 1'd1 ;
  assign WILL_FIRE_master0_m_bvalid = 1'd1 ;

  // value method master0_m_bready
  assign master0_bready =
	     !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;

  // value method master0_m_arvalid
  assign master0_arvalid = llc_axi4_adapter_master_xactor_crg_rd_addr_full ;

  // value method master0_m_arid
  assign master0_arid = llc_axi4_adapter_master_xactor_rg_rd_addr[96:93] ;

  // value method master0_m_araddr
  assign master0_araddr = llc_axi4_adapter_master_xactor_rg_rd_addr[92:29] ;

  // value method master0_m_arlen
  assign master0_arlen = llc_axi4_adapter_master_xactor_rg_rd_addr[28:21] ;

  // value method master0_m_arsize
  assign master0_arsize = llc_axi4_adapter_master_xactor_rg_rd_addr[20:18] ;

  // value method master0_m_arburst
  assign master0_arburst = llc_axi4_adapter_master_xactor_rg_rd_addr[17:16] ;

  // value method master0_m_arlock
  assign master0_arlock = llc_axi4_adapter_master_xactor_rg_rd_addr[15] ;

  // value method master0_m_arcache
  assign master0_arcache = llc_axi4_adapter_master_xactor_rg_rd_addr[14:11] ;

  // value method master0_m_arprot
  assign master0_arprot = llc_axi4_adapter_master_xactor_rg_rd_addr[10:8] ;

  // value method master0_m_arqos
  assign master0_arqos = llc_axi4_adapter_master_xactor_rg_rd_addr[7:4] ;

  // value method master0_m_arregion
  assign master0_arregion = llc_axi4_adapter_master_xactor_rg_rd_addr[3:0] ;

  // action method master0_m_arready
  assign CAN_FIRE_master0_m_arready = 1'd1 ;
  assign WILL_FIRE_master0_m_arready = 1'd1 ;

  // action method master0_m_rvalid
  assign CAN_FIRE_master0_m_rvalid = 1'd1 ;
  assign WILL_FIRE_master0_m_rvalid = 1'd1 ;

  // value method master0_m_rready
  assign master0_rready =
	     !llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ;

  // value method master1_m_awvalid
  assign master1_awvalid = mmio_axi4_adapter_master_xactor_crg_wr_addr_full ;

  // value method master1_m_awid
  assign master1_awid = mmio_axi4_adapter_master_xactor_rg_wr_addr[96:93] ;

  // value method master1_m_awaddr
  assign master1_awaddr = mmio_axi4_adapter_master_xactor_rg_wr_addr[92:29] ;

  // value method master1_m_awlen
  assign master1_awlen = mmio_axi4_adapter_master_xactor_rg_wr_addr[28:21] ;

  // value method master1_m_awsize
  assign master1_awsize = mmio_axi4_adapter_master_xactor_rg_wr_addr[20:18] ;

  // value method master1_m_awburst
  assign master1_awburst = mmio_axi4_adapter_master_xactor_rg_wr_addr[17:16] ;

  // value method master1_m_awlock
  assign master1_awlock = mmio_axi4_adapter_master_xactor_rg_wr_addr[15] ;

  // value method master1_m_awcache
  assign master1_awcache = mmio_axi4_adapter_master_xactor_rg_wr_addr[14:11] ;

  // value method master1_m_awprot
  assign master1_awprot = mmio_axi4_adapter_master_xactor_rg_wr_addr[10:8] ;

  // value method master1_m_awqos
  assign master1_awqos = mmio_axi4_adapter_master_xactor_rg_wr_addr[7:4] ;

  // value method master1_m_awregion
  assign master1_awregion = mmio_axi4_adapter_master_xactor_rg_wr_addr[3:0] ;

  // action method master1_m_awready
  assign CAN_FIRE_master1_m_awready = 1'd1 ;
  assign WILL_FIRE_master1_m_awready = 1'd1 ;

  // value method master1_m_wvalid
  assign master1_wvalid = mmio_axi4_adapter_master_xactor_crg_wr_data_full ;

  // value method master1_m_wdata
  assign master1_wdata = mmio_axi4_adapter_master_xactor_rg_wr_data[72:9] ;

  // value method master1_m_wstrb
  assign master1_wstrb = mmio_axi4_adapter_master_xactor_rg_wr_data[8:1] ;

  // value method master1_m_wlast
  assign master1_wlast = mmio_axi4_adapter_master_xactor_rg_wr_data[0] ;

  // action method master1_m_wready
  assign CAN_FIRE_master1_m_wready = 1'd1 ;
  assign WILL_FIRE_master1_m_wready = 1'd1 ;

  // action method master1_m_bvalid
  assign CAN_FIRE_master1_m_bvalid = 1'd1 ;
  assign WILL_FIRE_master1_m_bvalid = 1'd1 ;

  // value method master1_m_bready
  assign master1_bready =
	     !mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;

  // value method master1_m_arvalid
  assign master1_arvalid = mmio_axi4_adapter_master_xactor_crg_rd_addr_full ;

  // value method master1_m_arid
  assign master1_arid = mmio_axi4_adapter_master_xactor_rg_rd_addr[96:93] ;

  // value method master1_m_araddr
  assign master1_araddr = mmio_axi4_adapter_master_xactor_rg_rd_addr[92:29] ;

  // value method master1_m_arlen
  assign master1_arlen = mmio_axi4_adapter_master_xactor_rg_rd_addr[28:21] ;

  // value method master1_m_arsize
  assign master1_arsize = mmio_axi4_adapter_master_xactor_rg_rd_addr[20:18] ;

  // value method master1_m_arburst
  assign master1_arburst = mmio_axi4_adapter_master_xactor_rg_rd_addr[17:16] ;

  // value method master1_m_arlock
  assign master1_arlock = mmio_axi4_adapter_master_xactor_rg_rd_addr[15] ;

  // value method master1_m_arcache
  assign master1_arcache = mmio_axi4_adapter_master_xactor_rg_rd_addr[14:11] ;

  // value method master1_m_arprot
  assign master1_arprot = mmio_axi4_adapter_master_xactor_rg_rd_addr[10:8] ;

  // value method master1_m_arqos
  assign master1_arqos = mmio_axi4_adapter_master_xactor_rg_rd_addr[7:4] ;

  // value method master1_m_arregion
  assign master1_arregion = mmio_axi4_adapter_master_xactor_rg_rd_addr[3:0] ;

  // action method master1_m_arready
  assign CAN_FIRE_master1_m_arready = 1'd1 ;
  assign WILL_FIRE_master1_m_arready = 1'd1 ;

  // action method master1_m_rvalid
  assign CAN_FIRE_master1_m_rvalid = 1'd1 ;
  assign WILL_FIRE_master1_m_rvalid = 1'd1 ;

  // value method master1_m_rready
  assign master1_rready =
	     !mmio_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ;

  // action method m_external_interrupt_req
  assign CAN_FIRE_m_external_interrupt_req = 1'd1 ;
  assign WILL_FIRE_m_external_interrupt_req = 1'd1 ;

  // action method s_external_interrupt_req
  assign CAN_FIRE_s_external_interrupt_req = 1'd1 ;
  assign WILL_FIRE_s_external_interrupt_req = 1'd1 ;

  // action method non_maskable_interrupt_req
  assign CAN_FIRE_non_maskable_interrupt_req = 1'd1 ;
  assign WILL_FIRE_non_maskable_interrupt_req = 1'd1 ;

  // action method set_verbosity
  assign RDY_set_verbosity = 1'd1 ;
  assign CAN_FIRE_set_verbosity = 1'd1 ;
  assign WILL_FIRE_set_verbosity = EN_set_verbosity ;

  // action method debug_module_mem_server_m_awvalid
  assign CAN_FIRE_debug_module_mem_server_m_awvalid = 1'd1 ;
  assign WILL_FIRE_debug_module_mem_server_m_awvalid = 1'd1 ;

  // value method debug_module_mem_server_m_awready
  assign debug_module_mem_server_awready =
	     llc_mem_server_axi4_slave_xactor_f_wr_addr$FULL_N ;

  // action method debug_module_mem_server_m_wvalid
  assign CAN_FIRE_debug_module_mem_server_m_wvalid = 1'd1 ;
  assign WILL_FIRE_debug_module_mem_server_m_wvalid = 1'd1 ;

  // value method debug_module_mem_server_m_wready
  assign debug_module_mem_server_wready =
	     llc_mem_server_axi4_slave_xactor_f_wr_data$FULL_N ;

  // value method debug_module_mem_server_m_bvalid
  assign debug_module_mem_server_bvalid =
	     llc_mem_server_axi4_slave_xactor_f_wr_resp$EMPTY_N ;

  // value method debug_module_mem_server_m_bid
  assign debug_module_mem_server_bid =
	     llc_mem_server_axi4_slave_xactor_f_wr_resp$D_OUT[5:2] ;

  // value method debug_module_mem_server_m_bresp
  assign debug_module_mem_server_bresp =
	     llc_mem_server_axi4_slave_xactor_f_wr_resp$D_OUT[1:0] ;

  // action method debug_module_mem_server_m_bready
  assign CAN_FIRE_debug_module_mem_server_m_bready = 1'd1 ;
  assign WILL_FIRE_debug_module_mem_server_m_bready = 1'd1 ;

  // action method debug_module_mem_server_m_arvalid
  assign CAN_FIRE_debug_module_mem_server_m_arvalid = 1'd1 ;
  assign WILL_FIRE_debug_module_mem_server_m_arvalid = 1'd1 ;

  // value method debug_module_mem_server_m_arready
  assign debug_module_mem_server_arready =
	     llc_mem_server_axi4_slave_xactor_f_rd_addr$FULL_N ;

  // value method debug_module_mem_server_m_rvalid
  assign debug_module_mem_server_rvalid =
	     llc_mem_server_axi4_slave_xactor_f_rd_data$EMPTY_N ;

  // value method debug_module_mem_server_m_rid
  assign debug_module_mem_server_rid =
	     llc_mem_server_axi4_slave_xactor_f_rd_data$D_OUT[70:67] ;

  // value method debug_module_mem_server_m_rdata
  assign debug_module_mem_server_rdata =
	     llc_mem_server_axi4_slave_xactor_f_rd_data$D_OUT[66:3] ;

  // value method debug_module_mem_server_m_rresp
  assign debug_module_mem_server_rresp =
	     llc_mem_server_axi4_slave_xactor_f_rd_data$D_OUT[2:1] ;

  // value method debug_module_mem_server_m_rlast
  assign debug_module_mem_server_rlast =
	     llc_mem_server_axi4_slave_xactor_f_rd_data$D_OUT[0] ;

  // action method debug_module_mem_server_m_rready
  assign CAN_FIRE_debug_module_mem_server_m_rready = 1'd1 ;
  assign WILL_FIRE_debug_module_mem_server_m_rready = 1'd1 ;

  // submodule core_0
  mkCore core_0(.CLK(CLK),
		.RST_N(RST_N),
		.coreReq_perfReq_loc(core_0$coreReq_perfReq_loc),
		.coreReq_perfReq_t(core_0$coreReq_perfReq_t),
		.coreReq_start_fromHostAddr(core_0$coreReq_start_fromHostAddr),
		.coreReq_start_running(core_0$coreReq_start_running),
		.coreReq_start_startpc(core_0$coreReq_start_startpc),
		.coreReq_start_toHostAddr(core_0$coreReq_start_toHostAddr),
		.dCacheToParent_fromP_enq_x(core_0$dCacheToParent_fromP_enq_x),
		.iCacheToParent_fromP_enq_x(core_0$iCacheToParent_fromP_enq_x),
		.mmioToPlatform_pRq_enq_x(core_0$mmioToPlatform_pRq_enq_x),
		.mmioToPlatform_pRs_enq_x(core_0$mmioToPlatform_pRs_enq_x),
		.mmioToPlatform_setTime_t(core_0$mmioToPlatform_setTime_t),
		.recvDoStats_x(core_0$recvDoStats_x),
		.setMEIP_v(core_0$setMEIP_v),
		.setSEIP_v(core_0$setSEIP_v),
		.tlbToMem_respLd_enq_x(core_0$tlbToMem_respLd_enq_x),
		.EN_coreReq_start(core_0$EN_coreReq_start),
		.EN_coreReq_perfReq(core_0$EN_coreReq_perfReq),
		.EN_coreIndInv_perfResp(core_0$EN_coreIndInv_perfResp),
		.EN_coreIndInv_terminate(core_0$EN_coreIndInv_terminate),
		.EN_dCacheToParent_rsToP_deq(core_0$EN_dCacheToParent_rsToP_deq),
		.EN_dCacheToParent_rqToP_deq(core_0$EN_dCacheToParent_rqToP_deq),
		.EN_dCacheToParent_fromP_enq(core_0$EN_dCacheToParent_fromP_enq),
		.EN_iCacheToParent_rsToP_deq(core_0$EN_iCacheToParent_rsToP_deq),
		.EN_iCacheToParent_rqToP_deq(core_0$EN_iCacheToParent_rqToP_deq),
		.EN_iCacheToParent_fromP_enq(core_0$EN_iCacheToParent_fromP_enq),
		.EN_tlbToMem_memReq_deq(core_0$EN_tlbToMem_memReq_deq),
		.EN_tlbToMem_respLd_enq(core_0$EN_tlbToMem_respLd_enq),
		.EN_mmioToPlatform_cRq_deq(core_0$EN_mmioToPlatform_cRq_deq),
		.EN_mmioToPlatform_pRs_enq(core_0$EN_mmioToPlatform_pRs_enq),
		.EN_mmioToPlatform_pRq_enq(core_0$EN_mmioToPlatform_pRq_enq),
		.EN_mmioToPlatform_cRs_deq(core_0$EN_mmioToPlatform_cRs_deq),
		.EN_mmioToPlatform_setTime(core_0$EN_mmioToPlatform_setTime),
		.EN_sendDoStats(core_0$EN_sendDoStats),
		.EN_recvDoStats(core_0$EN_recvDoStats),
		.EN_deadlock_dCacheCRqStuck_get(core_0$EN_deadlock_dCacheCRqStuck_get),
		.EN_deadlock_dCachePRqStuck_get(core_0$EN_deadlock_dCachePRqStuck_get),
		.EN_deadlock_iCacheCRqStuck_get(core_0$EN_deadlock_iCacheCRqStuck_get),
		.EN_deadlock_iCachePRqStuck_get(core_0$EN_deadlock_iCachePRqStuck_get),
		.EN_deadlock_renameInstStuck_get(core_0$EN_deadlock_renameInstStuck_get),
		.EN_deadlock_renameCorrectPathStuck_get(core_0$EN_deadlock_renameCorrectPathStuck_get),
		.EN_deadlock_commitInstStuck_get(core_0$EN_deadlock_commitInstStuck_get),
		.EN_deadlock_commitUserInstStuck_get(core_0$EN_deadlock_commitUserInstStuck_get),
		.EN_deadlock_checkStarted_get(core_0$EN_deadlock_checkStarted_get),
		.EN_renameDebug_renameErr_get(core_0$EN_renameDebug_renameErr_get),
		.EN_setMEIP(core_0$EN_setMEIP),
		.EN_setSEIP(core_0$EN_setSEIP),
		.RDY_coreReq_start(),
		.RDY_coreReq_perfReq(),
		.coreIndInv_perfResp(),
		.RDY_coreIndInv_perfResp(),
		.RDY_coreIndInv_terminate(core_0$RDY_coreIndInv_terminate),
		.dCacheToParent_rsToP_notEmpty(),
		.RDY_dCacheToParent_rsToP_notEmpty(),
		.RDY_dCacheToParent_rsToP_deq(core_0$RDY_dCacheToParent_rsToP_deq),
		.dCacheToParent_rsToP_first(core_0$dCacheToParent_rsToP_first),
		.RDY_dCacheToParent_rsToP_first(core_0$RDY_dCacheToParent_rsToP_first),
		.dCacheToParent_rqToP_notEmpty(),
		.RDY_dCacheToParent_rqToP_notEmpty(),
		.RDY_dCacheToParent_rqToP_deq(core_0$RDY_dCacheToParent_rqToP_deq),
		.dCacheToParent_rqToP_first(core_0$dCacheToParent_rqToP_first),
		.RDY_dCacheToParent_rqToP_first(core_0$RDY_dCacheToParent_rqToP_first),
		.dCacheToParent_fromP_notFull(),
		.RDY_dCacheToParent_fromP_notFull(),
		.RDY_dCacheToParent_fromP_enq(core_0$RDY_dCacheToParent_fromP_enq),
		.iCacheToParent_rsToP_notEmpty(),
		.RDY_iCacheToParent_rsToP_notEmpty(),
		.RDY_iCacheToParent_rsToP_deq(core_0$RDY_iCacheToParent_rsToP_deq),
		.iCacheToParent_rsToP_first(core_0$iCacheToParent_rsToP_first),
		.RDY_iCacheToParent_rsToP_first(core_0$RDY_iCacheToParent_rsToP_first),
		.iCacheToParent_rqToP_notEmpty(),
		.RDY_iCacheToParent_rqToP_notEmpty(),
		.RDY_iCacheToParent_rqToP_deq(core_0$RDY_iCacheToParent_rqToP_deq),
		.iCacheToParent_rqToP_first(core_0$iCacheToParent_rqToP_first),
		.RDY_iCacheToParent_rqToP_first(core_0$RDY_iCacheToParent_rqToP_first),
		.iCacheToParent_fromP_notFull(),
		.RDY_iCacheToParent_fromP_notFull(),
		.RDY_iCacheToParent_fromP_enq(core_0$RDY_iCacheToParent_fromP_enq),
		.tlbToMem_memReq_notEmpty(),
		.RDY_tlbToMem_memReq_notEmpty(),
		.RDY_tlbToMem_memReq_deq(core_0$RDY_tlbToMem_memReq_deq),
		.tlbToMem_memReq_first(core_0$tlbToMem_memReq_first),
		.RDY_tlbToMem_memReq_first(core_0$RDY_tlbToMem_memReq_first),
		.tlbToMem_respLd_notFull(),
		.RDY_tlbToMem_respLd_notFull(),
		.RDY_tlbToMem_respLd_enq(core_0$RDY_tlbToMem_respLd_enq),
		.mmioToPlatform_cRq_notEmpty(core_0$mmioToPlatform_cRq_notEmpty),
		.RDY_mmioToPlatform_cRq_notEmpty(),
		.RDY_mmioToPlatform_cRq_deq(core_0$RDY_mmioToPlatform_cRq_deq),
		.mmioToPlatform_cRq_first(core_0$mmioToPlatform_cRq_first),
		.RDY_mmioToPlatform_cRq_first(core_0$RDY_mmioToPlatform_cRq_first),
		.mmioToPlatform_pRs_notFull(),
		.RDY_mmioToPlatform_pRs_notFull(),
		.RDY_mmioToPlatform_pRs_enq(core_0$RDY_mmioToPlatform_pRs_enq),
		.mmioToPlatform_pRq_notFull(),
		.RDY_mmioToPlatform_pRq_notFull(),
		.RDY_mmioToPlatform_pRq_enq(core_0$RDY_mmioToPlatform_pRq_enq),
		.mmioToPlatform_cRs_notEmpty(),
		.RDY_mmioToPlatform_cRs_notEmpty(),
		.RDY_mmioToPlatform_cRs_deq(core_0$RDY_mmioToPlatform_cRs_deq),
		.mmioToPlatform_cRs_first(core_0$mmioToPlatform_cRs_first),
		.RDY_mmioToPlatform_cRs_first(core_0$RDY_mmioToPlatform_cRs_first),
		.RDY_mmioToPlatform_setTime(),
		.sendDoStats(core_0$sendDoStats),
		.RDY_sendDoStats(core_0$RDY_sendDoStats),
		.RDY_recvDoStats(),
		.deadlock_dCacheCRqStuck_get(),
		.RDY_deadlock_dCacheCRqStuck_get(core_0$RDY_deadlock_dCacheCRqStuck_get),
		.deadlock_dCachePRqStuck_get(),
		.RDY_deadlock_dCachePRqStuck_get(core_0$RDY_deadlock_dCachePRqStuck_get),
		.deadlock_iCacheCRqStuck_get(),
		.RDY_deadlock_iCacheCRqStuck_get(core_0$RDY_deadlock_iCacheCRqStuck_get),
		.deadlock_iCachePRqStuck_get(),
		.RDY_deadlock_iCachePRqStuck_get(core_0$RDY_deadlock_iCachePRqStuck_get),
		.deadlock_renameInstStuck_get(),
		.RDY_deadlock_renameInstStuck_get(core_0$RDY_deadlock_renameInstStuck_get),
		.deadlock_renameCorrectPathStuck_get(),
		.RDY_deadlock_renameCorrectPathStuck_get(core_0$RDY_deadlock_renameCorrectPathStuck_get),
		.deadlock_commitInstStuck_get(),
		.RDY_deadlock_commitInstStuck_get(core_0$RDY_deadlock_commitInstStuck_get),
		.deadlock_commitUserInstStuck_get(),
		.RDY_deadlock_commitUserInstStuck_get(core_0$RDY_deadlock_commitUserInstStuck_get),
		.RDY_deadlock_checkStarted_get(core_0$RDY_deadlock_checkStarted_get),
		.renameDebug_renameErr_get(),
		.RDY_renameDebug_renameErr_get(core_0$RDY_renameDebug_renameErr_get),
		.RDY_setMEIP(),
		.RDY_setSEIP());

  // submodule enqDst_0_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) enqDst_0_dummy2_0(.CLK(CLK),
							    .D_IN(enqDst_0_dummy2_0$D_IN),
							    .EN(enqDst_0_dummy2_0$EN),
							    .Q_OUT(enqDst_0_dummy2_0$Q_OUT));

  // submodule enqDst_0_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) enqDst_0_dummy2_1(.CLK(CLK),
							    .D_IN(enqDst_0_dummy2_1$D_IN),
							    .EN(enqDst_0_dummy2_1$EN),
							    .Q_OUT(enqDst_0_dummy2_1$Q_OUT));

  // submodule enqDst_1_0_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) enqDst_1_0_dummy2_0(.CLK(CLK),
							      .D_IN(enqDst_1_0_dummy2_0$D_IN),
							      .EN(enqDst_1_0_dummy2_0$EN),
							      .Q_OUT(enqDst_1_0_dummy2_0$Q_OUT));

  // submodule enqDst_1_0_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) enqDst_1_0_dummy2_1(.CLK(CLK),
							      .D_IN(enqDst_1_0_dummy2_1$D_IN),
							      .EN(enqDst_1_0_dummy2_1$EN),
							      .Q_OUT(enqDst_1_0_dummy2_1$Q_OUT));

  // submodule llc
  mkLLCache llc(.CLK(CLK),
		.RST_N(RST_N),
		.dma_memReq_enq_x(llc$dma_memReq_enq_x),
		.perf_req_r(llc$perf_req_r),
		.perf_setStatus_doStats(llc$perf_setStatus_doStats),
		.to_child_rqFromC_enq_x(llc$to_child_rqFromC_enq_x),
		.to_child_rsFromC_enq_x(llc$to_child_rsFromC_enq_x),
		.to_mem_rsFromM_enq_x(llc$to_mem_rsFromM_enq_x),
		.EN_to_child_rsFromC_enq(llc$EN_to_child_rsFromC_enq),
		.EN_to_child_rqFromC_enq(llc$EN_to_child_rqFromC_enq),
		.EN_to_child_toC_deq(llc$EN_to_child_toC_deq),
		.EN_dma_memReq_enq(llc$EN_dma_memReq_enq),
		.EN_dma_respLd_deq(llc$EN_dma_respLd_deq),
		.EN_dma_respSt_deq(llc$EN_dma_respSt_deq),
		.EN_to_mem_toM_deq(llc$EN_to_mem_toM_deq),
		.EN_to_mem_rsFromM_enq(llc$EN_to_mem_rsFromM_enq),
		.EN_cRqStuck_get(llc$EN_cRqStuck_get),
		.EN_perf_setStatus(llc$EN_perf_setStatus),
		.EN_perf_req(llc$EN_perf_req),
		.EN_perf_resp(llc$EN_perf_resp),
		.to_child_rsFromC_notFull(),
		.RDY_to_child_rsFromC_notFull(),
		.RDY_to_child_rsFromC_enq(llc$RDY_to_child_rsFromC_enq),
		.to_child_rqFromC_notFull(),
		.RDY_to_child_rqFromC_notFull(),
		.RDY_to_child_rqFromC_enq(llc$RDY_to_child_rqFromC_enq),
		.to_child_toC_notEmpty(),
		.RDY_to_child_toC_notEmpty(),
		.RDY_to_child_toC_deq(llc$RDY_to_child_toC_deq),
		.to_child_toC_first(llc$to_child_toC_first),
		.RDY_to_child_toC_first(llc$RDY_to_child_toC_first),
		.dma_memReq_notFull(),
		.RDY_dma_memReq_notFull(),
		.RDY_dma_memReq_enq(llc$RDY_dma_memReq_enq),
		.dma_respLd_notEmpty(),
		.RDY_dma_respLd_notEmpty(),
		.RDY_dma_respLd_deq(llc$RDY_dma_respLd_deq),
		.dma_respLd_first(llc$dma_respLd_first),
		.RDY_dma_respLd_first(llc$RDY_dma_respLd_first),
		.dma_respSt_notEmpty(),
		.RDY_dma_respSt_notEmpty(),
		.RDY_dma_respSt_deq(llc$RDY_dma_respSt_deq),
		.dma_respSt_first(llc$dma_respSt_first),
		.RDY_dma_respSt_first(llc$RDY_dma_respSt_first),
		.to_mem_toM_notEmpty(),
		.RDY_to_mem_toM_notEmpty(),
		.RDY_to_mem_toM_deq(llc$RDY_to_mem_toM_deq),
		.to_mem_toM_first(llc$to_mem_toM_first),
		.RDY_to_mem_toM_first(llc$RDY_to_mem_toM_first),
		.to_mem_rsFromM_notFull(),
		.RDY_to_mem_rsFromM_notFull(),
		.RDY_to_mem_rsFromM_enq(llc$RDY_to_mem_rsFromM_enq),
		.cRqStuck_get(),
		.RDY_cRqStuck_get(),
		.RDY_perf_setStatus(),
		.RDY_perf_req(),
		.perf_resp(),
		.RDY_perf_resp(),
		.perf_respValid(),
		.RDY_perf_respValid());

  // submodule llc_axi4_adapter_f_pending_reads
  FIFO2 #(.width(32'd69),
	  .guarded(32'd1)) llc_axi4_adapter_f_pending_reads(.RST(RST_N),
							    .CLK(CLK),
							    .D_IN(llc_axi4_adapter_f_pending_reads$D_IN),
							    .ENQ(llc_axi4_adapter_f_pending_reads$ENQ),
							    .DEQ(llc_axi4_adapter_f_pending_reads$DEQ),
							    .CLR(llc_axi4_adapter_f_pending_reads$CLR),
							    .D_OUT(llc_axi4_adapter_f_pending_reads$D_OUT),
							    .FULL_N(llc_axi4_adapter_f_pending_reads$FULL_N),
							    .EMPTY_N(llc_axi4_adapter_f_pending_reads$EMPTY_N));

  // submodule llc_axi4_adapter_f_pending_writes
  FIFO2 #(.width(32'd640),
	  .guarded(32'd1)) llc_axi4_adapter_f_pending_writes(.RST(RST_N),
							     .CLK(CLK),
							     .D_IN(llc_axi4_adapter_f_pending_writes$D_IN),
							     .ENQ(llc_axi4_adapter_f_pending_writes$ENQ),
							     .DEQ(llc_axi4_adapter_f_pending_writes$DEQ),
							     .CLR(llc_axi4_adapter_f_pending_writes$CLR),
							     .D_OUT(),
							     .FULL_N(llc_axi4_adapter_f_pending_writes$FULL_N),
							     .EMPTY_N(llc_axi4_adapter_f_pending_writes$EMPTY_N));

  // submodule llc_mem_server_axi4_slave_xactor_f_rd_addr
  FIFO2 #(.width(32'd97),
	  .guarded(32'd1)) llc_mem_server_axi4_slave_xactor_f_rd_addr(.RST(RST_N),
								      .CLK(CLK),
								      .D_IN(llc_mem_server_axi4_slave_xactor_f_rd_addr$D_IN),
								      .ENQ(llc_mem_server_axi4_slave_xactor_f_rd_addr$ENQ),
								      .DEQ(llc_mem_server_axi4_slave_xactor_f_rd_addr$DEQ),
								      .CLR(llc_mem_server_axi4_slave_xactor_f_rd_addr$CLR),
								      .D_OUT(llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT),
								      .FULL_N(llc_mem_server_axi4_slave_xactor_f_rd_addr$FULL_N),
								      .EMPTY_N(llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N));

  // submodule llc_mem_server_axi4_slave_xactor_f_rd_data
  FIFO2 #(.width(32'd71),
	  .guarded(32'd1)) llc_mem_server_axi4_slave_xactor_f_rd_data(.RST(RST_N),
								      .CLK(CLK),
								      .D_IN(llc_mem_server_axi4_slave_xactor_f_rd_data$D_IN),
								      .ENQ(llc_mem_server_axi4_slave_xactor_f_rd_data$ENQ),
								      .DEQ(llc_mem_server_axi4_slave_xactor_f_rd_data$DEQ),
								      .CLR(llc_mem_server_axi4_slave_xactor_f_rd_data$CLR),
								      .D_OUT(llc_mem_server_axi4_slave_xactor_f_rd_data$D_OUT),
								      .FULL_N(llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N),
								      .EMPTY_N(llc_mem_server_axi4_slave_xactor_f_rd_data$EMPTY_N));

  // submodule llc_mem_server_axi4_slave_xactor_f_wr_addr
  FIFO2 #(.width(32'd97),
	  .guarded(32'd1)) llc_mem_server_axi4_slave_xactor_f_wr_addr(.RST(RST_N),
								      .CLK(CLK),
								      .D_IN(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_IN),
								      .ENQ(llc_mem_server_axi4_slave_xactor_f_wr_addr$ENQ),
								      .DEQ(llc_mem_server_axi4_slave_xactor_f_wr_addr$DEQ),
								      .CLR(llc_mem_server_axi4_slave_xactor_f_wr_addr$CLR),
								      .D_OUT(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT),
								      .FULL_N(llc_mem_server_axi4_slave_xactor_f_wr_addr$FULL_N),
								      .EMPTY_N(llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N));

  // submodule llc_mem_server_axi4_slave_xactor_f_wr_data
  FIFO2 #(.width(32'd73),
	  .guarded(32'd1)) llc_mem_server_axi4_slave_xactor_f_wr_data(.RST(RST_N),
								      .CLK(CLK),
								      .D_IN(llc_mem_server_axi4_slave_xactor_f_wr_data$D_IN),
								      .ENQ(llc_mem_server_axi4_slave_xactor_f_wr_data$ENQ),
								      .DEQ(llc_mem_server_axi4_slave_xactor_f_wr_data$DEQ),
								      .CLR(llc_mem_server_axi4_slave_xactor_f_wr_data$CLR),
								      .D_OUT(llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT),
								      .FULL_N(llc_mem_server_axi4_slave_xactor_f_wr_data$FULL_N),
								      .EMPTY_N(llc_mem_server_axi4_slave_xactor_f_wr_data$EMPTY_N));

  // submodule llc_mem_server_axi4_slave_xactor_f_wr_resp
  FIFO2 #(.width(32'd6),
	  .guarded(32'd1)) llc_mem_server_axi4_slave_xactor_f_wr_resp(.RST(RST_N),
								      .CLK(CLK),
								      .D_IN(llc_mem_server_axi4_slave_xactor_f_wr_resp$D_IN),
								      .ENQ(llc_mem_server_axi4_slave_xactor_f_wr_resp$ENQ),
								      .DEQ(llc_mem_server_axi4_slave_xactor_f_wr_resp$DEQ),
								      .CLR(llc_mem_server_axi4_slave_xactor_f_wr_resp$CLR),
								      .D_OUT(llc_mem_server_axi4_slave_xactor_f_wr_resp$D_OUT),
								      .FULL_N(llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N),
								      .EMPTY_N(llc_mem_server_axi4_slave_xactor_f_wr_resp$EMPTY_N));

  // submodule llc_mem_server_enqDst_0_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) llc_mem_server_enqDst_0_dummy2_0(.CLK(CLK),
							    .D_IN(llc_mem_server_enqDst_0_dummy2_0$D_IN),
							    .EN(llc_mem_server_enqDst_0_dummy2_0$EN),
							    .Q_OUT(llc_mem_server_enqDst_0_dummy2_0$Q_OUT));

  // submodule llc_mem_server_enqDst_0_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) llc_mem_server_enqDst_0_dummy2_1(.CLK(CLK),
							    .D_IN(llc_mem_server_enqDst_0_dummy2_1$D_IN),
							    .EN(llc_mem_server_enqDst_0_dummy2_1$EN),
							    .Q_OUT(llc_mem_server_enqDst_0_dummy2_1$Q_OUT));

  // submodule llc_mem_server_f_dword_in_line
  FIFO2 #(.width(32'd3),
	  .guarded(32'd1)) llc_mem_server_f_dword_in_line(.RST(RST_N),
							  .CLK(CLK),
							  .D_IN(llc_mem_server_f_dword_in_line$D_IN),
							  .ENQ(llc_mem_server_f_dword_in_line$ENQ),
							  .DEQ(llc_mem_server_f_dword_in_line$DEQ),
							  .CLR(llc_mem_server_f_dword_in_line$CLR),
							  .D_OUT(),
							  .FULL_N(),
							  .EMPTY_N());

  // submodule llc_mem_server_propDstData_0_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) llc_mem_server_propDstData_0_dummy2_0(.CLK(CLK),
								 .D_IN(llc_mem_server_propDstData_0_dummy2_0$D_IN),
								 .EN(llc_mem_server_propDstData_0_dummy2_0$EN),
								 .Q_OUT());

  // submodule llc_mem_server_propDstData_0_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) llc_mem_server_propDstData_0_dummy2_1(.CLK(CLK),
								 .D_IN(llc_mem_server_propDstData_0_dummy2_1$D_IN),
								 .EN(llc_mem_server_propDstData_0_dummy2_1$EN),
								 .Q_OUT(llc_mem_server_propDstData_0_dummy2_1$Q_OUT));

  // submodule llc_mem_server_propDstIdx_0_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) llc_mem_server_propDstIdx_0_dummy2_0(.CLK(CLK),
								.D_IN(llc_mem_server_propDstIdx_0_dummy2_0$D_IN),
								.EN(llc_mem_server_propDstIdx_0_dummy2_0$EN),
								.Q_OUT(llc_mem_server_propDstIdx_0_dummy2_0$Q_OUT));

  // submodule llc_mem_server_propDstIdx_0_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) llc_mem_server_propDstIdx_0_dummy2_1(.CLK(CLK),
								.D_IN(llc_mem_server_propDstIdx_0_dummy2_1$D_IN),
								.EN(llc_mem_server_propDstIdx_0_dummy2_1$EN),
								.Q_OUT(llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT));

  // submodule llc_mem_server_tlbQ
  FIFO2 #(.width(32'd65), .guarded(32'd1)) llc_mem_server_tlbQ(.RST(RST_N),
							       .CLK(CLK),
							       .D_IN(llc_mem_server_tlbQ$D_IN),
							       .ENQ(llc_mem_server_tlbQ$ENQ),
							       .DEQ(llc_mem_server_tlbQ$DEQ),
							       .CLR(llc_mem_server_tlbQ$CLR),
							       .D_OUT(llc_mem_server_tlbQ$D_OUT),
							       .FULL_N(llc_mem_server_tlbQ$FULL_N),
							       .EMPTY_N(llc_mem_server_tlbQ$EMPTY_N));

  // submodule mmioPlatform_fromHostQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmioPlatform_fromHostQ_clearReq_dummy2_0(.CLK(CLK),
								    .D_IN(mmioPlatform_fromHostQ_clearReq_dummy2_0$D_IN),
								    .EN(mmioPlatform_fromHostQ_clearReq_dummy2_0$EN),
								    .Q_OUT());

  // submodule mmioPlatform_fromHostQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmioPlatform_fromHostQ_clearReq_dummy2_1(.CLK(CLK),
								    .D_IN(mmioPlatform_fromHostQ_clearReq_dummy2_1$D_IN),
								    .EN(mmioPlatform_fromHostQ_clearReq_dummy2_1$EN),
								    .Q_OUT(mmioPlatform_fromHostQ_clearReq_dummy2_1$Q_OUT));

  // submodule mmioPlatform_fromHostQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmioPlatform_fromHostQ_deqReq_dummy2_0(.CLK(CLK),
								  .D_IN(mmioPlatform_fromHostQ_deqReq_dummy2_0$D_IN),
								  .EN(mmioPlatform_fromHostQ_deqReq_dummy2_0$EN),
								  .Q_OUT());

  // submodule mmioPlatform_fromHostQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmioPlatform_fromHostQ_deqReq_dummy2_1(.CLK(CLK),
								  .D_IN(mmioPlatform_fromHostQ_deqReq_dummy2_1$D_IN),
								  .EN(mmioPlatform_fromHostQ_deqReq_dummy2_1$EN),
								  .Q_OUT());

  // submodule mmioPlatform_fromHostQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmioPlatform_fromHostQ_deqReq_dummy2_2(.CLK(CLK),
								  .D_IN(mmioPlatform_fromHostQ_deqReq_dummy2_2$D_IN),
								  .EN(mmioPlatform_fromHostQ_deqReq_dummy2_2$EN),
								  .Q_OUT(mmioPlatform_fromHostQ_deqReq_dummy2_2$Q_OUT));

  // submodule mmioPlatform_fromHostQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmioPlatform_fromHostQ_enqReq_dummy2_0(.CLK(CLK),
								  .D_IN(mmioPlatform_fromHostQ_enqReq_dummy2_0$D_IN),
								  .EN(mmioPlatform_fromHostQ_enqReq_dummy2_0$EN),
								  .Q_OUT());

  // submodule mmioPlatform_fromHostQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmioPlatform_fromHostQ_enqReq_dummy2_1(.CLK(CLK),
								  .D_IN(mmioPlatform_fromHostQ_enqReq_dummy2_1$D_IN),
								  .EN(mmioPlatform_fromHostQ_enqReq_dummy2_1$EN),
								  .Q_OUT());

  // submodule mmioPlatform_fromHostQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmioPlatform_fromHostQ_enqReq_dummy2_2(.CLK(CLK),
								  .D_IN(mmioPlatform_fromHostQ_enqReq_dummy2_2$D_IN),
								  .EN(mmioPlatform_fromHostQ_enqReq_dummy2_2$EN),
								  .Q_OUT(mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT));

  // submodule mmioPlatform_toHostQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmioPlatform_toHostQ_clearReq_dummy2_0(.CLK(CLK),
								  .D_IN(mmioPlatform_toHostQ_clearReq_dummy2_0$D_IN),
								  .EN(mmioPlatform_toHostQ_clearReq_dummy2_0$EN),
								  .Q_OUT());

  // submodule mmioPlatform_toHostQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmioPlatform_toHostQ_clearReq_dummy2_1(.CLK(CLK),
								  .D_IN(mmioPlatform_toHostQ_clearReq_dummy2_1$D_IN),
								  .EN(mmioPlatform_toHostQ_clearReq_dummy2_1$EN),
								  .Q_OUT(mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT));

  // submodule mmioPlatform_toHostQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmioPlatform_toHostQ_deqReq_dummy2_0(.CLK(CLK),
								.D_IN(mmioPlatform_toHostQ_deqReq_dummy2_0$D_IN),
								.EN(mmioPlatform_toHostQ_deqReq_dummy2_0$EN),
								.Q_OUT());

  // submodule mmioPlatform_toHostQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmioPlatform_toHostQ_deqReq_dummy2_1(.CLK(CLK),
								.D_IN(mmioPlatform_toHostQ_deqReq_dummy2_1$D_IN),
								.EN(mmioPlatform_toHostQ_deqReq_dummy2_1$EN),
								.Q_OUT());

  // submodule mmioPlatform_toHostQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmioPlatform_toHostQ_deqReq_dummy2_2(.CLK(CLK),
								.D_IN(mmioPlatform_toHostQ_deqReq_dummy2_2$D_IN),
								.EN(mmioPlatform_toHostQ_deqReq_dummy2_2$EN),
								.Q_OUT(mmioPlatform_toHostQ_deqReq_dummy2_2$Q_OUT));

  // submodule mmioPlatform_toHostQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmioPlatform_toHostQ_enqReq_dummy2_0(.CLK(CLK),
								.D_IN(mmioPlatform_toHostQ_enqReq_dummy2_0$D_IN),
								.EN(mmioPlatform_toHostQ_enqReq_dummy2_0$EN),
								.Q_OUT());

  // submodule mmioPlatform_toHostQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmioPlatform_toHostQ_enqReq_dummy2_1(.CLK(CLK),
								.D_IN(mmioPlatform_toHostQ_enqReq_dummy2_1$D_IN),
								.EN(mmioPlatform_toHostQ_enqReq_dummy2_1$EN),
								.Q_OUT());

  // submodule mmioPlatform_toHostQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmioPlatform_toHostQ_enqReq_dummy2_2(.CLK(CLK),
								.D_IN(mmioPlatform_toHostQ_enqReq_dummy2_2$D_IN),
								.EN(mmioPlatform_toHostQ_enqReq_dummy2_2$EN),
								.Q_OUT(mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT));

  // submodule mmio_axi4_adapter_f_reqs_from_core
  FIFO2 #(.width(32'd142),
	  .guarded(32'd1)) mmio_axi4_adapter_f_reqs_from_core(.RST(RST_N),
							      .CLK(CLK),
							      .D_IN(mmio_axi4_adapter_f_reqs_from_core$D_IN),
							      .ENQ(mmio_axi4_adapter_f_reqs_from_core$ENQ),
							      .DEQ(mmio_axi4_adapter_f_reqs_from_core$DEQ),
							      .CLR(mmio_axi4_adapter_f_reqs_from_core$CLR),
							      .D_OUT(mmio_axi4_adapter_f_reqs_from_core$D_OUT),
							      .FULL_N(mmio_axi4_adapter_f_reqs_from_core$FULL_N),
							      .EMPTY_N(mmio_axi4_adapter_f_reqs_from_core$EMPTY_N));

  // submodule mmio_axi4_adapter_f_rsps_to_core
  FIFO2 #(.width(32'd65),
	  .guarded(32'd1)) mmio_axi4_adapter_f_rsps_to_core(.RST(RST_N),
							    .CLK(CLK),
							    .D_IN(mmio_axi4_adapter_f_rsps_to_core$D_IN),
							    .ENQ(mmio_axi4_adapter_f_rsps_to_core$ENQ),
							    .DEQ(mmio_axi4_adapter_f_rsps_to_core$DEQ),
							    .CLR(mmio_axi4_adapter_f_rsps_to_core$CLR),
							    .D_OUT(mmio_axi4_adapter_f_rsps_to_core$D_OUT),
							    .FULL_N(mmio_axi4_adapter_f_rsps_to_core$FULL_N),
							    .EMPTY_N(mmio_axi4_adapter_f_rsps_to_core$EMPTY_N));

  // submodule mmio_axi4_adapter_soc_map
  mkSoC_Map mmio_axi4_adapter_soc_map(.CLK(CLK),
				      .RST_N(RST_N),
				      .m_is_IO_addr_addr(mmio_axi4_adapter_soc_map$m_is_IO_addr_addr),
				      .m_is_mem_addr_addr(mmio_axi4_adapter_soc_map$m_is_mem_addr_addr),
				      .m_is_near_mem_IO_addr_addr(mmio_axi4_adapter_soc_map$m_is_near_mem_IO_addr_addr),
				      .m_near_mem_io_addr_base(),
				      .m_near_mem_io_addr_size(),
				      .m_near_mem_io_addr_lim(),
				      .m_plic_addr_base(),
				      .m_plic_addr_size(),
				      .m_plic_addr_lim(),
				      .m_uart0_addr_base(),
				      .m_uart0_addr_size(),
				      .m_uart0_addr_lim(),
				      .m_boot_rom_addr_base(),
				      .m_boot_rom_addr_size(),
				      .m_boot_rom_addr_lim(),
				      .m_mem0_controller_addr_base(),
				      .m_mem0_controller_addr_size(),
				      .m_mem0_controller_addr_lim(),
				      .m_tcm_addr_base(),
				      .m_tcm_addr_size(),
				      .m_tcm_addr_lim(),
				      .m_is_mem_addr(),
				      .m_is_IO_addr(mmio_axi4_adapter_soc_map$m_is_IO_addr),
				      .m_is_near_mem_IO_addr(),
				      .m_pc_reset_value(),
				      .m_mtvec_reset_value(),
				      .m_nmivec_reset_value());

  // submodule propDstData_0_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) propDstData_0_dummy2_0(.CLK(CLK),
								 .D_IN(propDstData_0_dummy2_0$D_IN),
								 .EN(propDstData_0_dummy2_0$EN),
								 .Q_OUT());

  // submodule propDstData_0_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) propDstData_0_dummy2_1(.CLK(CLK),
								 .D_IN(propDstData_0_dummy2_1$D_IN),
								 .EN(propDstData_0_dummy2_1$EN),
								 .Q_OUT(propDstData_0_dummy2_1$Q_OUT));

  // submodule propDstData_1_0_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_0_dummy2_0(.CLK(CLK),
								   .D_IN(propDstData_1_0_dummy2_0$D_IN),
								   .EN(propDstData_1_0_dummy2_0$EN),
								   .Q_OUT());

  // submodule propDstData_1_0_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_0_dummy2_1(.CLK(CLK),
								   .D_IN(propDstData_1_0_dummy2_1$D_IN),
								   .EN(propDstData_1_0_dummy2_1$EN),
								   .Q_OUT(propDstData_1_0_dummy2_1$Q_OUT));

  // submodule propDstData_1_1_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_1_dummy2_0(.CLK(CLK),
								   .D_IN(propDstData_1_1_dummy2_0$D_IN),
								   .EN(propDstData_1_1_dummy2_0$EN),
								   .Q_OUT());

  // submodule propDstData_1_1_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_1_dummy2_1(.CLK(CLK),
								   .D_IN(propDstData_1_1_dummy2_1$D_IN),
								   .EN(propDstData_1_1_dummy2_1$EN),
								   .Q_OUT(propDstData_1_1_dummy2_1$Q_OUT));

  // submodule propDstData_1_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_dummy2_0(.CLK(CLK),
								 .D_IN(propDstData_1_dummy2_0$D_IN),
								 .EN(propDstData_1_dummy2_0$EN),
								 .Q_OUT());

  // submodule propDstData_1_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_dummy2_1(.CLK(CLK),
								 .D_IN(propDstData_1_dummy2_1$D_IN),
								 .EN(propDstData_1_dummy2_1$EN),
								 .Q_OUT(propDstData_1_dummy2_1$Q_OUT));

  // submodule propDstIdx_0_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_0_dummy2_0(.CLK(CLK),
								.D_IN(propDstIdx_0_dummy2_0$D_IN),
								.EN(propDstIdx_0_dummy2_0$EN),
								.Q_OUT(propDstIdx_0_dummy2_0$Q_OUT));

  // submodule propDstIdx_0_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_0_dummy2_1(.CLK(CLK),
								.D_IN(propDstIdx_0_dummy2_1$D_IN),
								.EN(propDstIdx_0_dummy2_1$EN),
								.Q_OUT(propDstIdx_0_dummy2_1$Q_OUT));

  // submodule propDstIdx_1_0_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_0_dummy2_0(.CLK(CLK),
								  .D_IN(propDstIdx_1_0_dummy2_0$D_IN),
								  .EN(propDstIdx_1_0_dummy2_0$EN),
								  .Q_OUT(propDstIdx_1_0_dummy2_0$Q_OUT));

  // submodule propDstIdx_1_0_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_0_dummy2_1(.CLK(CLK),
								  .D_IN(propDstIdx_1_0_dummy2_1$D_IN),
								  .EN(propDstIdx_1_0_dummy2_1$EN),
								  .Q_OUT(propDstIdx_1_0_dummy2_1$Q_OUT));

  // submodule propDstIdx_1_1_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_1_dummy2_0(.CLK(CLK),
								  .D_IN(propDstIdx_1_1_dummy2_0$D_IN),
								  .EN(propDstIdx_1_1_dummy2_0$EN),
								  .Q_OUT(propDstIdx_1_1_dummy2_0$Q_OUT));

  // submodule propDstIdx_1_1_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_1_dummy2_1(.CLK(CLK),
								  .D_IN(propDstIdx_1_1_dummy2_1$D_IN),
								  .EN(propDstIdx_1_1_dummy2_1$EN),
								  .Q_OUT(propDstIdx_1_1_dummy2_1$Q_OUT));

  // submodule propDstIdx_1_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_dummy2_0(.CLK(CLK),
								.D_IN(propDstIdx_1_dummy2_0$D_IN),
								.EN(propDstIdx_1_dummy2_0$EN),
								.Q_OUT(propDstIdx_1_dummy2_0$Q_OUT));

  // submodule propDstIdx_1_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_dummy2_1(.CLK(CLK),
								.D_IN(propDstIdx_1_dummy2_1$D_IN),
								.EN(propDstIdx_1_dummy2_1$EN),
								.Q_OUT(propDstIdx_1_dummy2_1$Q_OUT));

  // rule RL_srcPropose
  assign CAN_FIRE_RL_srcPropose =
	     core_0$RDY_dCacheToParent_rqToP_first &&
	     core_0$RDY_dCacheToParent_rqToP_deq &&
	     (!propDstIdx_0_dummy2_0$Q_OUT || !propDstIdx_0_dummy2_1$Q_OUT ||
	      !propDstIdx_0_rl) ;
  assign WILL_FIRE_RL_srcPropose = CAN_FIRE_RL_srcPropose ;

  // rule RL_srcPropose_1
  assign CAN_FIRE_RL_srcPropose_1 =
	     core_0$RDY_iCacheToParent_rqToP_first &&
	     core_0$RDY_iCacheToParent_rqToP_deq &&
	     (!propDstIdx_1_dummy2_0$Q_OUT || !propDstIdx_1_dummy2_1$Q_OUT ||
	      !propDstIdx_1_rl) ;
  assign WILL_FIRE_RL_srcPropose_1 = CAN_FIRE_RL_srcPropose_1 ;

  // rule RL_dstSelectSrc
  assign CAN_FIRE_RL_dstSelectSrc = 1'd1 ;
  assign WILL_FIRE_RL_dstSelectSrc = 1'd1 ;

  // rule RL_doEnq
  assign CAN_FIRE_RL_doEnq =
	     llc$RDY_to_child_rqFromC_enq && enqDst_0_dummy2_1$Q_OUT &&
	     IF_enqDst_0_lat_0_whas__038_THEN_enqDst_0_lat__ETC___d1043 ;
  assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ;

  // rule RL_srcPropose_2
  assign CAN_FIRE_RL_srcPropose_2 =
	     core_0$RDY_dCacheToParent_rsToP_first &&
	     core_0$RDY_dCacheToParent_rsToP_deq &&
	     (!propDstIdx_1_0_dummy2_0$Q_OUT ||
	      !propDstIdx_1_0_dummy2_1$Q_OUT ||
	      !propDstIdx_1_0_rl) ;
  assign WILL_FIRE_RL_srcPropose_2 = CAN_FIRE_RL_srcPropose_2 ;

  // rule RL_srcPropose_3
  assign CAN_FIRE_RL_srcPropose_3 =
	     core_0$RDY_iCacheToParent_rsToP_first &&
	     core_0$RDY_iCacheToParent_rsToP_deq &&
	     (!propDstIdx_1_1_dummy2_0$Q_OUT ||
	      !propDstIdx_1_1_dummy2_1$Q_OUT ||
	      !propDstIdx_1_1_rl) ;
  assign WILL_FIRE_RL_srcPropose_3 = CAN_FIRE_RL_srcPropose_3 ;

  // rule RL_dstSelectSrc_1
  assign CAN_FIRE_RL_dstSelectSrc_1 = 1'd1 ;
  assign WILL_FIRE_RL_dstSelectSrc_1 = 1'd1 ;

  // rule RL_doEnq_1
  assign CAN_FIRE_RL_doEnq_1 =
	     llc$RDY_to_child_rsFromC_enq && enqDst_1_0_dummy2_1$Q_OUT &&
	     IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1279 ;
  assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ;

  // rule RL_sendPRq
  assign CAN_FIRE_RL_sendPRq =
	     core_0$RDY_dCacheToParent_fromP_enq &&
	     llc$RDY_to_child_toC_deq &&
	     llc$RDY_to_child_toC_first &&
	     !llc$to_child_toC_first[583] &&
	     !llc$to_child_toC_first[0] ;
  assign WILL_FIRE_RL_sendPRq = CAN_FIRE_RL_sendPRq ;

  // rule RL_sendPRs
  assign CAN_FIRE_RL_sendPRs =
	     core_0$RDY_dCacheToParent_fromP_enq &&
	     llc$RDY_to_child_toC_deq &&
	     llc$RDY_to_child_toC_first &&
	     llc$to_child_toC_first[583] &&
	     !llc$to_child_toC_first[516] ;
  assign WILL_FIRE_RL_sendPRs = CAN_FIRE_RL_sendPRs ;

  // rule RL_sendPRq_1
  assign CAN_FIRE_RL_sendPRq_1 =
	     core_0$RDY_iCacheToParent_fromP_enq &&
	     llc$RDY_to_child_toC_deq &&
	     llc$RDY_to_child_toC_first &&
	     !llc$to_child_toC_first[583] &&
	     llc$to_child_toC_first[0] ;
  assign WILL_FIRE_RL_sendPRq_1 = CAN_FIRE_RL_sendPRq_1 ;

  // rule RL_sendPRs_1
  assign CAN_FIRE_RL_sendPRs_1 =
	     core_0$RDY_iCacheToParent_fromP_enq &&
	     llc$RDY_to_child_toC_deq &&
	     llc$RDY_to_child_toC_first &&
	     llc$to_child_toC_first[583] &&
	     llc$to_child_toC_first[516] ;
  assign WILL_FIRE_RL_sendPRs_1 = CAN_FIRE_RL_sendPRs_1 ;

  // rule RL_broadcastStats
  assign CAN_FIRE_RL_broadcastStats = core_0$RDY_sendDoStats ;
  assign WILL_FIRE_RL_broadcastStats = core_0$RDY_sendDoStats ;

  // rule RL_rl_dummy1
  assign CAN_FIRE_RL_rl_dummy1 = core_0$RDY_deadlock_dCacheCRqStuck_get ;
  assign WILL_FIRE_RL_rl_dummy1 = core_0$RDY_deadlock_dCacheCRqStuck_get ;

  // rule RL_rl_dummy2
  assign CAN_FIRE_RL_rl_dummy2 = core_0$RDY_deadlock_dCachePRqStuck_get ;
  assign WILL_FIRE_RL_rl_dummy2 = core_0$RDY_deadlock_dCachePRqStuck_get ;

  // rule RL_rl_dummy3
  assign CAN_FIRE_RL_rl_dummy3 = core_0$RDY_deadlock_iCacheCRqStuck_get ;
  assign WILL_FIRE_RL_rl_dummy3 = core_0$RDY_deadlock_iCacheCRqStuck_get ;

  // rule RL_rl_dummy4
  assign CAN_FIRE_RL_rl_dummy4 = core_0$RDY_deadlock_iCachePRqStuck_get ;
  assign WILL_FIRE_RL_rl_dummy4 = core_0$RDY_deadlock_iCachePRqStuck_get ;

  // rule RL_rl_dummy5
  assign CAN_FIRE_RL_rl_dummy5 = core_0$RDY_deadlock_renameInstStuck_get ;
  assign WILL_FIRE_RL_rl_dummy5 = core_0$RDY_deadlock_renameInstStuck_get ;

  // rule RL_rl_dummy6
  assign CAN_FIRE_RL_rl_dummy6 =
	     core_0$RDY_deadlock_renameCorrectPathStuck_get ;
  assign WILL_FIRE_RL_rl_dummy6 =
	     core_0$RDY_deadlock_renameCorrectPathStuck_get ;

  // rule RL_rl_dummy7
  assign CAN_FIRE_RL_rl_dummy7 = core_0$RDY_deadlock_commitInstStuck_get ;
  assign WILL_FIRE_RL_rl_dummy7 = core_0$RDY_deadlock_commitInstStuck_get ;

  // rule RL_rl_dummy8
  assign CAN_FIRE_RL_rl_dummy8 = core_0$RDY_deadlock_commitUserInstStuck_get ;
  assign WILL_FIRE_RL_rl_dummy8 =
	     core_0$RDY_deadlock_commitUserInstStuck_get ;

  // rule RL_rl_dummy9
  assign CAN_FIRE_RL_rl_dummy9 = core_0$RDY_deadlock_checkStarted_get ;
  assign WILL_FIRE_RL_rl_dummy9 = core_0$RDY_deadlock_checkStarted_get ;

  // rule RL_rl_dummy20
  assign CAN_FIRE_RL_rl_dummy20 = core_0$RDY_renameDebug_renameErr_get ;
  assign WILL_FIRE_RL_rl_dummy20 = core_0$RDY_renameDebug_renameErr_get ;

  // rule RL_rl_terminate
  assign CAN_FIRE_RL_rl_terminate = core_0$RDY_coreIndInv_terminate ;
  assign WILL_FIRE_RL_rl_terminate = core_0$RDY_coreIndInv_terminate ;

  // rule RL_rl_tohost
  assign CAN_FIRE_RL_rl_tohost = !mmioPlatform_toHostQ_empty ;
  assign WILL_FIRE_RL_rl_tohost = CAN_FIRE_RL_rl_tohost ;

  // rule RL_mmio_axi4_adapter_rl_handle_read_rsps
  assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps =
	     mmio_axi4_adapter_f_rsps_to_core$FULL_N &&
	     mmio_axi4_adapter_master_xactor_crg_rd_data_full ;
  assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps =
	     CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ;

  // rule RL_mmio_axi4_adapter_rl_handle_write_req
  assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req =
	     mmio_axi4_adapter_f_reqs_from_core$EMPTY_N &&
	     IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d103 &&
	     mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd2 ;
  assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req =
	     CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	     !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ;

  // rule RL_mmio_axi4_adapter_rl_handle_read_req
  assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req =
	     mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9 &&
	     mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd1 &&
	     b__h2352 == 4'd0 ;
  assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req =
	     CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	     !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ;

  // rule RL_mmio_axi4_adapter_rl_discard_write_rsp
  assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp =
	     b__h2352 != 4'd0 &&
	     mmio_axi4_adapter_master_xactor_crg_wr_resp_full &&
	     (mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0 ||
	      mmio_axi4_adapter_f_rsps_to_core$FULL_N) ;
  assign WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp =
	     CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	     !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	     !WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ;

  // rule RL_mmio_axi4_adapter_rl_handle_non_Ld_St
  assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St =
	     mmio_axi4_adapter_f_reqs_from_core$EMPTY_N &&
	     mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd1 &&
	     mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd2 ;
  assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St =
	     CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St ;

  // rule RL_mmioPlatform_propagateTime
  assign CAN_FIRE_RL_mmioPlatform_propagateTime = mmioPlatform_state != 2'd0 ;
  assign WILL_FIRE_RL_mmioPlatform_propagateTime =
	     CAN_FIRE_RL_mmioPlatform_propagateTime ;

  // rule RL_mmioPlatform_incCycle
  assign CAN_FIRE_RL_mmioPlatform_incCycle =
	     mmioPlatform_state != 2'd0 &&
	     mmioPlatform_cycle_47_ULT_99___d348 ;
  assign WILL_FIRE_RL_mmioPlatform_incCycle =
	     CAN_FIRE_RL_mmioPlatform_incCycle ;

  // rule RL_mmioPlatform_incTime
  assign CAN_FIRE_RL_mmioPlatform_incTime =
	     mmioPlatform_state == 2'd1 &&
	     !mmioPlatform_cycle_47_ULT_99___d348 ;
  assign WILL_FIRE_RL_mmioPlatform_incTime =
	     CAN_FIRE_RL_mmioPlatform_incTime ;

  // rule RL_mmioPlatform_selectReq
  assign CAN_FIRE_RL_mmioPlatform_selectReq =
	     (mmioPlatform_mtip_0 ||
	      !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 ||
	      core_0$RDY_mmioToPlatform_pRq_enq) &&
	     NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370 &&
	     mmioPlatform_state == 2'd1 ;
  assign WILL_FIRE_RL_mmioPlatform_selectReq =
	     CAN_FIRE_RL_mmioPlatform_selectReq &&
	     !WILL_FIRE_RL_mmioPlatform_incTime ;

  // rule RL_mmioPlatform_waitTimerInterruptDone
  assign CAN_FIRE_RL_mmioPlatform_waitTimerInterruptDone =
	     (!mmioPlatform_waitMTIPCRs ||
	      core_0$RDY_mmioToPlatform_cRs_deq) &&
	     mmioPlatform_state == 2'd3 &&
	     mmioPlatform_curReq[66:64] == 3'd1 ;
  assign WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone =
	     CAN_FIRE_RL_mmioPlatform_waitTimerInterruptDone ;

  // rule RL_mmioPlatform_processMSIP
  assign CAN_FIRE_RL_mmioPlatform_processMSIP =
	     IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453 &&
	     mmioPlatform_curReq[66:64] == 3'd2 &&
	     mmioPlatform_state == 2'd2 ;
  assign WILL_FIRE_RL_mmioPlatform_processMSIP =
	     CAN_FIRE_RL_mmioPlatform_processMSIP ;

  // rule RL_mmioPlatform_waitMSIPDone
  assign CAN_FIRE_RL_mmioPlatform_waitMSIPDone =
	     core_0$RDY_mmioToPlatform_pRs_enq &&
	     IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496 &&
	     mmioPlatform_curReq[66:64] == 3'd2 &&
	     mmioPlatform_state == 2'd3 ;
  assign WILL_FIRE_RL_mmioPlatform_waitMSIPDone =
	     CAN_FIRE_RL_mmioPlatform_waitMSIPDone ;

  // rule RL_mmioPlatform_processMTimeCmp
  assign CAN_FIRE_RL_mmioPlatform_processMTimeCmp =
	     CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 &&
	     mmioPlatform_curReq[66:64] == 3'd3 &&
	     mmioPlatform_state == 2'd2 ;
  assign WILL_FIRE_RL_mmioPlatform_processMTimeCmp =
	     CAN_FIRE_RL_mmioPlatform_processMTimeCmp ;

  // rule RL_mmioPlatform_waitMTimeCmpDone
  assign CAN_FIRE_RL_mmioPlatform_waitMTimeCmpDone =
	     core_0$RDY_mmioToPlatform_cRs_deq &&
	     core_0$RDY_mmioToPlatform_pRs_enq &&
	     mmioPlatform_curReq[66:64] == 3'd3 &&
	     mmioPlatform_state == 2'd3 ;
  assign WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone =
	     CAN_FIRE_RL_mmioPlatform_waitMTimeCmpDone ;

  // rule RL_mmioPlatform_processMTime
  assign CAN_FIRE_RL_mmioPlatform_processMTime =
	     CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11 &&
	     mmioPlatform_state == 2'd2 &&
	     mmioPlatform_curReq[66:64] == 3'd4 ;
  assign WILL_FIRE_RL_mmioPlatform_processMTime =
	     CAN_FIRE_RL_mmioPlatform_processMTime ;

  // rule RL_mmioPlatform_waitMTimeDone
  assign CAN_FIRE_RL_mmioPlatform_waitMTimeDone =
	     core_0$RDY_mmioToPlatform_pRs_enq &&
	     (!mmioPlatform_waitMTIPCRs ||
	      core_0$RDY_mmioToPlatform_cRs_deq) &&
	     mmioPlatform_state == 2'd3 &&
	     mmioPlatform_curReq[66:64] == 3'd4 ;
  assign WILL_FIRE_RL_mmioPlatform_waitMTimeDone =
	     CAN_FIRE_RL_mmioPlatform_waitMTimeDone ;

  // rule RL_mmioPlatform_processToHost
  assign CAN_FIRE_RL_mmioPlatform_processToHost =
	     core_0$RDY_mmioToPlatform_pRs_enq &&
	     (mmioPlatform_reqFunc[5:4] != 2'd2 ||
	      !mmioPlatform_toHostQ_empty ||
	      x__h42868 == 64'd0 ||
	      !mmioPlatform_toHostQ_full) &&
	     mmioPlatform_state == 2'd2 &&
	     mmioPlatform_curReq[66:64] == 3'd5 ;
  assign WILL_FIRE_RL_mmioPlatform_processToHost =
	     CAN_FIRE_RL_mmioPlatform_processToHost ;

  // rule RL_mmioPlatform_processFromHost
  assign CAN_FIRE_RL_mmioPlatform_processFromHost =
	     core_0$RDY_mmioToPlatform_pRs_enq &&
	     mmioPlatform_state == 2'd2 &&
	     mmioPlatform_curReq[66:64] == 3'd6 ;
  assign WILL_FIRE_RL_mmioPlatform_processFromHost =
	     CAN_FIRE_RL_mmioPlatform_processFromHost ;

  // rule RL_mmioPlatform_rl_mmio_to_fabric_req
  assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req =
	     mmio_axi4_adapter_f_reqs_from_core$FULL_N &&
	     NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750 ;
  assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req =
	     CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ;

  // rule RL_mmioPlatform_rl_mmio_from_fabric_rsp
  assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp =
	     core_0$RDY_mmioToPlatform_pRs_enq &&
	     mmio_axi4_adapter_f_rsps_to_core$EMPTY_N &&
	     NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d758 ;
  assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp =
	     CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ;

  // rule RL_mmioPlatform_rl_mmio_to_fabric_amo_req
  assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req =
	     mmio_axi4_adapter_f_reqs_from_core$FULL_N &&
	     NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d763 ;
  assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req =
	     CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ;

  // rule RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp
  assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp =
	     core_0$RDY_mmioToPlatform_pRs_enq &&
	     mmio_axi4_adapter_f_rsps_to_core$EMPTY_N &&
	     (!mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ||
	      mmio_axi4_adapter_f_reqs_from_core$FULL_N) &&
	     NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d773 ;
  assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp =
	     CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ;

  // rule RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req
  assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req =
	     mmio_axi4_adapter_f_reqs_from_core$FULL_N &&
	     NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d964 ;
  assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req =
	     CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ;

  // rule RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp
  assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp =
	     mmio_axi4_adapter_f_rsps_to_core$EMPTY_N &&
	     IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d974 &&
	     NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d977 ;
  assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp =
	     CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ;

  // rule RL_mmioPlatform_toHostQ_canonicalize
  assign CAN_FIRE_RL_mmioPlatform_toHostQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_mmioPlatform_toHostQ_canonicalize = 1'd1 ;

  // rule RL_mmioPlatform_toHostQ_enqReq_canon
  assign CAN_FIRE_RL_mmioPlatform_toHostQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmioPlatform_toHostQ_enqReq_canon = 1'd1 ;

  // rule RL_mmioPlatform_toHostQ_deqReq_canon
  assign CAN_FIRE_RL_mmioPlatform_toHostQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmioPlatform_toHostQ_deqReq_canon = 1'd1 ;

  // rule RL_mmioPlatform_toHostQ_clearReq_canon
  assign CAN_FIRE_RL_mmioPlatform_toHostQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmioPlatform_toHostQ_clearReq_canon = 1'd1 ;

  // rule RL_mmioPlatform_fromHostQ_canonicalize
  assign CAN_FIRE_RL_mmioPlatform_fromHostQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_mmioPlatform_fromHostQ_canonicalize = 1'd1 ;

  // rule RL_mmioPlatform_fromHostQ_enqReq_canon
  assign CAN_FIRE_RL_mmioPlatform_fromHostQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmioPlatform_fromHostQ_enqReq_canon = 1'd1 ;

  // rule RL_mmioPlatform_fromHostQ_deqReq_canon
  assign CAN_FIRE_RL_mmioPlatform_fromHostQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmioPlatform_fromHostQ_deqReq_canon = 1'd1 ;

  // rule RL_mmioPlatform_fromHostQ_clearReq_canon
  assign CAN_FIRE_RL_mmioPlatform_fromHostQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmioPlatform_fromHostQ_clearReq_canon = 1'd1 ;

  // rule RL_propDstIdx_0_canon
  assign CAN_FIRE_RL_propDstIdx_0_canon = 1'd1 ;
  assign WILL_FIRE_RL_propDstIdx_0_canon = 1'd1 ;

  // rule RL_propDstIdx_1_canon
  assign CAN_FIRE_RL_propDstIdx_1_canon = 1'd1 ;
  assign WILL_FIRE_RL_propDstIdx_1_canon = 1'd1 ;

  // rule RL_propDstData_0_canon
  assign CAN_FIRE_RL_propDstData_0_canon = 1'd1 ;
  assign WILL_FIRE_RL_propDstData_0_canon = 1'd1 ;

  // rule RL_propDstData_1_canon
  assign CAN_FIRE_RL_propDstData_1_canon = 1'd1 ;
  assign WILL_FIRE_RL_propDstData_1_canon = 1'd1 ;

  // rule RL_enqDst_0_canon
  assign CAN_FIRE_RL_enqDst_0_canon = 1'd1 ;
  assign WILL_FIRE_RL_enqDst_0_canon = 1'd1 ;

  // rule RL_propDstIdx_1_0_canon
  assign CAN_FIRE_RL_propDstIdx_1_0_canon = 1'd1 ;
  assign WILL_FIRE_RL_propDstIdx_1_0_canon = 1'd1 ;

  // rule RL_propDstIdx_1_1_canon
  assign CAN_FIRE_RL_propDstIdx_1_1_canon = 1'd1 ;
  assign WILL_FIRE_RL_propDstIdx_1_1_canon = 1'd1 ;

  // rule RL_propDstData_1_0_canon
  assign CAN_FIRE_RL_propDstData_1_0_canon = 1'd1 ;
  assign WILL_FIRE_RL_propDstData_1_0_canon = 1'd1 ;

  // rule RL_propDstData_1_1_canon
  assign CAN_FIRE_RL_propDstData_1_1_canon = 1'd1 ;
  assign WILL_FIRE_RL_propDstData_1_1_canon = 1'd1 ;

  // rule RL_enqDst_1_0_canon
  assign CAN_FIRE_RL_enqDst_1_0_canon = 1'd1 ;
  assign WILL_FIRE_RL_enqDst_1_0_canon = 1'd1 ;

  // rule RL_llc_mem_server_rl_handle_MemLoader_ld_req
  assign CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req =
	     llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N &&
	     llc_mem_server_axi4_slave_xactor_f_rd_data$FULL_N &&
	     (llc_mem_server_rg_cacheline_cache_state == 3'd3 ||
	      llc_mem_server_rg_cacheline_cache_state == 3'd4) &&
	     llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 ;
  assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req =
	     CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ;

  // rule RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay
  assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay =
	     llc_mem_server_rg_cacheline_cache_state == 3'd4 &&
	     llc_mem_server_rg_cacheline_cache_dirty_delay != 10'd0 ;
  assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay =
	     CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay ;

  // rule RL_llc_mem_server_rl_handle_MemLoader_st_req
  assign CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req =
	     llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N &&
	     llc_mem_server_axi4_slave_xactor_f_wr_data$EMPTY_N &&
	     llc_mem_server_axi4_slave_xactor_f_wr_resp$FULL_N &&
	     (llc_mem_server_rg_cacheline_cache_state == 3'd3 ||
	      llc_mem_server_rg_cacheline_cache_state == 3'd4) &&
	     llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 ;
  assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req =
	     CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ;

  // rule RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged
  assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged =
	     llc$RDY_dma_memReq_enq &&
	     llc_mem_server_rg_cacheline_cache_state == 3'd4 &&
	     llc_mem_server_rg_cacheline_cache_dirty_delay == 10'd0 ;
  assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged =
	     CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged &&
	     !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ;

  // rule RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss
  assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss =
	     llc$RDY_dma_memReq_enq &&
	     llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N &&
	     llc_mem_server_rg_cacheline_cache_state == 3'd4 &&
	     !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 ;
  assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss =
	     CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss &&
	     !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ;

  // rule RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss
  assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss =
	     llc$RDY_dma_memReq_enq &&
	     llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N &&
	     llc_mem_server_rg_cacheline_cache_state == 3'd4 &&
	     !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 ;
  assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss =
	     CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss &&
	     !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss &&
	     !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged &&
	     !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ;

  // rule RL_llc_mem_server_rl_cacheline_cache_writeback_finish
  assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish =
	     llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first &&
	     !llc$dma_respSt_first[4] &&
	     llc_mem_server_rg_cacheline_cache_state == 3'd1 ;
  assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish =
	     CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish ;

  // rule RL_llc_mem_server_rl_cacheline_cache_reload_req_st
  assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st =
	     llc$RDY_dma_memReq_enq &&
	     llc_mem_server_axi4_slave_xactor_f_wr_addr$EMPTY_N &&
	     llc_mem_server_rg_cacheline_cache_state == 3'd3 &&
	     !llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 ;
  assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st =
	     CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ;

  // rule RL_llc_mem_server_rl_cacheline_cache_reload_req_ld
  assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld =
	     llc$RDY_dma_memReq_enq &&
	     llc_mem_server_axi4_slave_xactor_f_rd_addr$EMPTY_N &&
	     llc_mem_server_rg_cacheline_cache_state == 3'd3 &&
	     !llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 ;
  assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld =
	     CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld &&
	     !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st &&
	     !WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ;

  // rule RL_llc_mem_server_rl_cacheline_cache_reload_finish
  assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish =
	     llc$RDY_dma_respLd_deq && llc$RDY_dma_respLd_first &&
	     !llc$dma_respLd_first[4] &&
	     llc_mem_server_rg_cacheline_cache_state == 3'd2 ;
  assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish =
	     CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ;

  // rule RL_llc_mem_server_srcPropose
  assign CAN_FIRE_RL_llc_mem_server_srcPropose =
	     core_0$RDY_tlbToMem_memReq_first &&
	     core_0$RDY_tlbToMem_memReq_deq &&
	     (!llc_mem_server_propDstIdx_0_dummy2_0$Q_OUT ||
	      !llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT ||
	      !llc_mem_server_propDstIdx_0_rl) ;
  assign WILL_FIRE_RL_llc_mem_server_srcPropose =
	     CAN_FIRE_RL_llc_mem_server_srcPropose ;

  // rule RL_llc_mem_server_dstSelectSrc
  assign CAN_FIRE_RL_llc_mem_server_dstSelectSrc = 1'd1 ;
  assign WILL_FIRE_RL_llc_mem_server_dstSelectSrc = 1'd1 ;

  // rule RL_llc_mem_server_doEnq
  assign CAN_FIRE_RL_llc_mem_server_doEnq =
	     llc_mem_server_tlbQ$FULL_N &&
	     llc_mem_server_enqDst_0_dummy2_1$Q_OUT &&
	     IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681 ;
  assign WILL_FIRE_RL_llc_mem_server_doEnq =
	     CAN_FIRE_RL_llc_mem_server_doEnq ;

  // rule RL_llc_mem_server_sendTlbReqToLLC
  assign CAN_FIRE_RL_llc_mem_server_sendTlbReqToLLC =
	     llc$RDY_dma_memReq_enq && llc_mem_server_tlbQ$EMPTY_N ;
  assign WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC =
	     CAN_FIRE_RL_llc_mem_server_sendTlbReqToLLC &&
	     !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld &&
	     !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st &&
	     !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss &&
	     !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss &&
	     !WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ;

  // rule RL_llc_mem_server_sendLdRespToTlb
  assign CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb =
	     core_0$RDY_tlbToMem_respLd_enq && llc$RDY_dma_respLd_deq &&
	     llc$RDY_dma_respLd_first &&
	     llc$dma_respLd_first[4] ;
  assign WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb =
	     CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb ;

  // rule RL_llc_mem_server_sendStRespToTlb
  assign CAN_FIRE_RL_llc_mem_server_sendStRespToTlb =
	     llc$RDY_dma_respSt_deq && llc$RDY_dma_respSt_first &&
	     llc$dma_respSt_first[4] ;
  assign WILL_FIRE_RL_llc_mem_server_sendStRespToTlb =
	     CAN_FIRE_RL_llc_mem_server_sendStRespToTlb ;

  // rule RL_llc_mem_server_propDstIdx_0_canon
  assign CAN_FIRE_RL_llc_mem_server_propDstIdx_0_canon = 1'd1 ;
  assign WILL_FIRE_RL_llc_mem_server_propDstIdx_0_canon = 1'd1 ;

  // rule RL_llc_mem_server_propDstData_0_canon
  assign CAN_FIRE_RL_llc_mem_server_propDstData_0_canon = 1'd1 ;
  assign WILL_FIRE_RL_llc_mem_server_propDstData_0_canon = 1'd1 ;

  // rule RL_llc_mem_server_enqDst_0_canon
  assign CAN_FIRE_RL_llc_mem_server_enqDst_0_canon = 1'd1 ;
  assign WILL_FIRE_RL_llc_mem_server_enqDst_0_canon = 1'd1 ;

  // rule RL_llc_axi4_adapter_rl_handle_read_rsps
  assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps =
	     llc_axi4_adapter_master_xactor_crg_rd_data_full &&
	     (llc_axi4_adapter_rg_rd_rsp_beat != 3'd7 ||
	      llc$RDY_to_mem_rsFromM_enq &&
	      llc_axi4_adapter_f_pending_reads$EMPTY_N) ;
  assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ;

  // rule RL_llc_axi4_adapter_rl_handle_write_req
  assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req =
	     !llc_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read &&
	     !llc_axi4_adapter_master_xactor_crg_wr_data_full$port2__read &&
	     llc$RDY_to_mem_toM_first &&
	     (llc_axi4_adapter_rg_wr_req_beat != 3'd0 ||
	      llc_axi4_adapter_f_pending_writes$FULL_N) &&
	     (llc_axi4_adapter_rg_wr_req_beat != 3'd7 ||
	      llc$RDY_to_mem_toM_deq) &&
	     llc$to_mem_toM_first[640] ;
  assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ;

  // rule RL_llc_axi4_adapter_rl_handle_read_req
  assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req =
	     !llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read &&
	     llc$RDY_to_mem_toM_first &&
	     (llc_axi4_adapter_rg_rd_req_beat != 3'd0 ||
	      llc_axi4_adapter_f_pending_reads$FULL_N) &&
	     (llc_axi4_adapter_rg_rd_req_beat != 3'd7 ||
	      llc$RDY_to_mem_toM_deq) &&
	     !llc$to_mem_toM_first[640] &&
	     b__h134523 == 4'd0 ;
  assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ;

  // rule RL_llc_axi4_adapter_rl_discard_write_rsp
  assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp =
	     b__h134523 != 4'd0 &&
	     llc_axi4_adapter_master_xactor_crg_wr_resp_full &&
	     (llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 ||
	      llc_axi4_adapter_f_pending_writes$EMPTY_N) ;
  assign WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ;

  // inputs to muxes for submodule ports
  assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 =
	     WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 &&
	     mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 ;
  assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 =
	     WILL_FIRE_RL_mmioPlatform_processMSIP &&
	     mmioPlatform_reqFunc[5:4] != 2'd0 &&
	     !mmioPlatform_reqBE[4] &&
	     mmioPlatform_reqBE[0] ;
  assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 =
	     WILL_FIRE_RL_mmioPlatform_processMTimeCmp &&
	     NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 ;
  assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 =
	     WILL_FIRE_RL_mmioPlatform_processMTime &&
	     NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ;
  assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 =
	     WILL_FIRE_RL_mmioPlatform_processMSIP &&
	     mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 ;
  assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 =
	     WILL_FIRE_RL_mmioPlatform_processMTimeCmp &&
	     mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 ;
  assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 =
	     WILL_FIRE_RL_mmioPlatform_processMTime &&
	     mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 ;
  assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 =
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp &&
	     (!mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 ||
	      !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) ;
  assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 =
	     WILL_FIRE_RL_mmioPlatform_waitMTimeDone ||
	     WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone ;
  assign MUX_llc$dma_memReq_enq_1__SEL_1 =
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss ||
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss ||
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ;
  assign MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2 =
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ||
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ;
  assign MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3 =
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ||
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish ;
  assign MUX_mmioPlatform_amoResp$write_1__SEL_1 =
	     WILL_FIRE_RL_mmioPlatform_processMTimeCmp &&
	     mmioPlatform_reqFunc[5:4] != 2'd0 &&
	     mmioPlatform_reqFunc[5:4] != 2'd1 ;
  assign MUX_mmioPlatform_amoResp$write_1__SEL_2 =
	     WILL_FIRE_RL_mmioPlatform_processMTime &&
	     mmioPlatform_reqFunc[5:4] != 2'd0 &&
	     mmioPlatform_reqFunc[5:4] != 2'd1 ;
  assign MUX_mmioPlatform_curReq$write_1__SEL_1 =
	     WILL_FIRE_RL_mmioPlatform_selectReq &&
	     (!mmioPlatform_mtip_0 &&
	      mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 ||
	      core_0$mmioToPlatform_cRq_notEmpty) ;
  assign MUX_mmioPlatform_fetchingWay$write_1__SEL_1 =
	     WILL_FIRE_RL_mmioPlatform_selectReq &&
	     (mmioPlatform_mtip_0 ||
	      !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) &&
	     core_0$mmioToPlatform_cRq_notEmpty ;
  assign MUX_mmioPlatform_state$write_1__SEL_6 =
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ||
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ||
	     WILL_FIRE_RL_mmioPlatform_processFromHost ||
	     WILL_FIRE_RL_mmioPlatform_processToHost ||
	     WILL_FIRE_RL_mmioPlatform_waitMTimeDone ||
	     WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone ||
	     WILL_FIRE_RL_mmioPlatform_waitMSIPDone ||
	     WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone ||
	     EN_start ;
  assign MUX_mmioPlatform_state$write_1__SEL_7 =
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ||
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ||
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ;
  assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__SEL_1 =
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp &&
	     mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ;
  assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__PSEL_1 =
	     WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ||
	     WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ;
  assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1 =
	     MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__PSEL_1 &&
	     !mmio_axi4_adapter_soc_map$m_is_IO_addr ;
  assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2 =
	     WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	     mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] == 2'b0 ;
  assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 =
	     { 1'd0, llc$to_child_toC_first[582:1] } ;
  assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 =
	     { 1'd1,
	       llc$to_child_toC_first[582:517],
	       llc$to_child_toC_first[515:0] } ;
  assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 =
	     { 1'd0,
	       IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477,
	       (mmioPlatform_reqFunc[5:4] != 2'd1 &&
		mmioPlatform_reqFunc[5:4] != 2'd2) ?
		 mmioPlatform_reqData[31:0] :
		 x_data__h30321 } ;
  assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 =
	     { 7'd106,
	       (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 &&
		!mmioPlatform_mtip_0) ?
		 32'd1 :
		 32'd0 } ;
  assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4 =
	     { 7'd106,
	       (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 &&
		!mmioPlatform_mtip_0) ?
		 32'd1 :
		 32'd0 } ;
  assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_1 =
	     { mmioPlatform_reqFunc[5:4] != 2'd0,
	       (mmioPlatform_reqFunc[5:4] == 2'd0) ?
		 66'h155555554AAAAAAAA :
		 66'h0AAAAAAAAAAAAAAAA } ;
  assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_2 =
	     { mmioPlatform_reqFunc[5:4] != 2'd0,
	       (mmioPlatform_reqFunc[5:4] == 2'd0) ?
		 66'h155555554AAAAAAAA :
		 { 2'h1,
		   IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574 } } ;
  assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3 =
	     { mmioPlatform_reqFunc[5:4] != 2'd0,
	       (mmioPlatform_reqFunc[5:4] == 2'd0) ?
		 66'h155555554AAAAAAAA :
		 { 2'h1,
		   IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638 } } ;
  assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 =
	     { 1'd0,
	       mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] &&
	       mmioPlatform_fetchingWay,
	       SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987,
	       mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ||
	       mmioPlatform_fetchingWay,
	       IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d995 } ;
  assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 =
	     { 3'd5, mmioPlatform_amoResp } ;
  assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h31738 } ;
  assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 =
	     { mmioPlatform_reqFunc[5:4] != 2'd0,
	       (mmioPlatform_reqFunc[5:4] == 2'd0) ?
		 66'h155555554AAAAAAAA :
		 DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 } ;
  assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 =
	     { mmioPlatform_reqFunc[5:4] != 2'd0,
	       (mmioPlatform_reqFunc[5:4] == 2'd0) ?
		 66'h155555554AAAAAAAA :
		 { 1'h0,
		   IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d722 } } ;
  assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 =
	     { 2'd2, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ;
  assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10 =
	     { 2'd2,
	       mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ?
		 { 1'd1, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:0] } :
		 mmio_axi4_adapter_f_rsps_to_core$D_OUT } ;
  assign MUX_llc$dma_memReq_enq_1__VAL_1 =
	     { llc_mem_server_rg_cacheline_cache_addr,
	       64'hFFFFFFFFFFFFFFFF,
	       llc_mem_server_rg_cacheline_cache_data,
	       5'd10 } ;
  assign MUX_llc$dma_memReq_enq_1__VAL_2 =
	     { line_addr__h102521,
	       581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ;
  assign MUX_llc$dma_memReq_enq_1__VAL_3 =
	     { line_addr__h102607,
	       581'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ;
  assign MUX_llc$dma_memReq_enq_1__VAL_4 =
	     { llc_mem_server_tlbQ$D_OUT[64:1],
	       577'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555,
	       llc_mem_server_tlbQ$D_OUT[0],
	       llc_mem_server_tlbQ$D_OUT[6:4] } ;
  assign MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 =
	     { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596,
	       (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] ==
		3'd1) ?
		 new_dword__h90148 :
		 llc_mem_server_rg_cacheline_cache_data[127:64],
	       (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] ==
		3'd0) ?
		 new_dword__h90148 :
		 llc_mem_server_rg_cacheline_cache_data[63:0] } ;
  assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 =
	     llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ;
  assign MUX_mmioPlatform_amoResp$write_1__VAL_1 =
	     (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ?
	       mmioPlatform_mtimecmp_0 :
	       IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 ;
  assign MUX_mmioPlatform_amoResp$write_1__VAL_2 =
	     (mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ?
	       mmioPlatform_mtime :
	       IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 ;
  assign MUX_mmioPlatform_curReq$write_1__VAL_1 =
	     (!mmioPlatform_mtip_0 &&
	      mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) ?
	       67'h1AAAAAAAAAAAAAAAA :
	       ((core_0$mmioToPlatform_cRq_first[141:81] >= 61'd4194304 &&
		 core_0$mmioToPlatform_cRq_first[141:81] < 61'd4194305) ?
		  67'h2AAAAAAAAAAAAAAAA :
		  ((core_0$mmioToPlatform_cRq_first[141:81] >= 61'd4196352 &&
		    core_0$mmioToPlatform_cRq_first[141:81] < 61'd4196353) ?
		     67'h3AAAAAAAAAAAAAAAA :
		     ((core_0$mmioToPlatform_cRq_first[141:81] ==
		       61'd4200447) ?
			67'h4AAAAAAAAAAAAAAAA :
			IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401))) ;
  assign MUX_mmioPlatform_curReq$write_1__VAL_2 =
	     { 3'd7,
	       mmioPlatform_instSel ?
		 mmioPlatform_curReq[63:0] + 64'd8 :
		 mmioPlatform_curReq[63:0] } ;
  assign MUX_mmioPlatform_cycle$write_1__VAL_1 = mmioPlatform_cycle + 7'd1 ;
  assign MUX_mmioPlatform_fetchingWay$write_1__VAL_2 =
	     mmioPlatform_fetchingWay + 1'd1 ;
  assign MUX_mmioPlatform_instSel$write_1__VAL_2 =
	     mmioPlatform_instSel + 1'd1 ;
  assign MUX_mmioPlatform_mtime$write_1__VAL_2 = mmioPlatform_mtime + 64'd1 ;
  assign MUX_mmioPlatform_mtip_0$write_1__VAL_2 =
	     IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 &&
	     !mmioPlatform_mtip_0 ;
  assign MUX_mmioPlatform_state$write_1__VAL_1 =
	     (!mmioPlatform_mtip_0 &&
	      mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) ?
	       2'd3 :
	       2'd2 ;
  assign MUX_mmioPlatform_state$write_1__VAL_2 =
	     (mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ?
	       2'd1 :
	       ((mmioPlatform_reqFunc[5:4] != 2'd1 &&
		 mmioPlatform_reqFunc[5:4] != 2'd2) ?
		  (mmioPlatform_reqBE[0] ? 2'd3 : 2'd1) :
		  2'd3) ;
  always@(mmioPlatform_reqFunc or
	  IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 or
	  mmioPlatform_mtip_0)
  begin
    case (mmioPlatform_reqFunc[5:4])
      2'd0: MUX_mmioPlatform_state$write_1__VAL_3 = 2'd1;
      2'd1: MUX_mmioPlatform_state$write_1__VAL_3 = mmioPlatform_reqFunc[5:4];
      default: MUX_mmioPlatform_state$write_1__VAL_3 =
		   (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 &&
		    !mmioPlatform_mtip_0 ||
		    !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 &&
		    mmioPlatform_mtip_0) ?
		     2'd3 :
		     2'd1;
    endcase
  end
  always@(mmioPlatform_reqFunc or
	  mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 or
	  mmioPlatform_mtip_0)
  begin
    case (mmioPlatform_reqFunc[5:4])
      2'd0: MUX_mmioPlatform_state$write_1__VAL_4 = 2'd1;
      2'd1: MUX_mmioPlatform_state$write_1__VAL_4 = mmioPlatform_reqFunc[5:4];
      default: MUX_mmioPlatform_state$write_1__VAL_4 =
		   (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 &&
		    !mmioPlatform_mtip_0 ||
		    !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 &&
		    mmioPlatform_mtip_0) ?
		     2'd3 :
		     2'd1;
    endcase
  end
  assign MUX_mmioPlatform_state$write_1__VAL_5 =
	     mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ?
	       (mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 ?
		  2'd2 :
		  2'd1) :
	       2'd1 ;
  assign MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 =
	     mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 &&
	     !mmioPlatform_mtip_0 ||
	     !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 &&
	     mmioPlatform_mtip_0 ;
  assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 =
	     { mmioPlatform_curReq[63:0],
	       6'd42,
	       mmioPlatform_reqBE,
	       x__h48010 } ;
  assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 =
	     { mmioPlatform_curReq[63:0],
	       IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477,
	       mmioPlatform_reqBE,
	       mmioPlatform_reqData } ;
  assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 =
	     { mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ;
  assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 =
	     { x__h50122, 78'h1AAAAAAAAAAAAAAAAAAA } ;
  assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 =
	     { 1'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78] } ;
  assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3 =
	     { mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] == 2'b0,
	       mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ;

  // inlined wires
  assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h42868 } ;
  assign mmioPlatform_toHostQ_enqReq_lat_0$whas =
	     WILL_FIRE_RL_mmioPlatform_processToHost &&
	     mmioPlatform_reqFunc[5:4] == 2'd2 &&
	     mmioPlatform_toHostQ_empty &&
	     x__h42868 != 64'd0 ;
  assign mmioPlatform_fromHostQ_deqReq_lat_0$whas =
	     WILL_FIRE_RL_mmioPlatform_processFromHost &&
	     mmioPlatform_reqFunc[5:4] == 2'd2 &&
	     !mmioPlatform_fromHostQ_empty &&
	     x__h40775 == 64'd0 ;
  assign propDstIdx_0_lat_1$whas =
	     NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 &&
	     IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 ;
  assign propDstIdx_1_lat_1$whas =
	     NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 &&
	     x__h61414 ;
  assign propDstData_0_lat_0$wget =
	     { core_0$dCacheToParent_rqToP_first, 1'd0 } ;
  assign propDstData_1_lat_0$wget =
	     { core_0$iCacheToParent_rqToP_first, 1'd1 } ;
  assign enqDst_0_lat_0$wget =
	     { 1'd1,
	       CASE_x1414_0_n__read_addr1596_1_n__read_addr16_ETC__q15,
	       SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164 } ;
  assign propDstIdx_1_0_lat_1$whas =
	     NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 &&
	     IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 ;
  assign propDstIdx_1_1_lat_1$whas =
	     NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 &&
	     x__h80299 ;
  assign propDstData_1_0_lat_0$wget =
	     { core_0$dCacheToParent_rsToP_first, 1'd0 } ;
  assign propDstData_1_1_lat_0$wget =
	     { core_0$iCacheToParent_rsToP_first, 1'd1 } ;
  assign enqDst_1_0_lat_0$wget =
	     { 1'd1,
	       CASE_x0299_0_n__read_addr0477_1_n__read_addr05_ETC__q26,
	       SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466 } ;
  assign llc_mem_server_enqDst_0_lat_0$wget =
	     { 1'd1, n__read_snd_addr__h124048, n__read_snd_id__h124049 } ;
  assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write =
	     mmio_axi4_adapter_master_xactor_crg_wr_addr_full &&
	     master1_awready ;
  assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read =
	     !mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write &&
	     mmio_axi4_adapter_master_xactor_crg_wr_addr_full ;
  assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port2__write =
	     WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	     mmio_axi4_adapter_soc_map$m_is_IO_addr ;
  assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read =
	     mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port2__write ||
	     mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read ;
  assign mmio_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write =
	     mmio_axi4_adapter_master_xactor_crg_wr_data_full &&
	     master1_wready ;
  assign mmio_axi4_adapter_master_xactor_crg_wr_data_full$port2__read =
	     !mmio_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write &&
	     mmio_axi4_adapter_master_xactor_crg_wr_data_full ;
  assign mmio_axi4_adapter_master_xactor_crg_wr_data_full$EN_port2__write =
	     WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	     mmio_axi4_adapter_soc_map$m_is_IO_addr ;
  assign mmio_axi4_adapter_master_xactor_crg_wr_data_full$port3__read =
	     mmio_axi4_adapter_master_xactor_crg_wr_data_full$EN_port2__write ||
	     mmio_axi4_adapter_master_xactor_crg_wr_data_full$port2__read ;
  assign mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read =
	     !WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	     mmio_axi4_adapter_master_xactor_crg_wr_resp_full ;
  assign mmio_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write =
	     master1_bvalid &&
	     !mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;
  assign mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read =
	     mmio_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write ||
	     mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;
  assign mmio_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write =
	     mmio_axi4_adapter_master_xactor_crg_rd_addr_full &&
	     master1_arready ;
  assign mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read =
	     !mmio_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write &&
	     mmio_axi4_adapter_master_xactor_crg_rd_addr_full ;
  assign mmio_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port2__write =
	     WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	     mmio_axi4_adapter_soc_map$m_is_IO_addr ;
  assign mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read =
	     mmio_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port2__write ||
	     mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read ;
  assign mmio_axi4_adapter_master_xactor_crg_rd_data_full$port2__read =
	     !CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	     mmio_axi4_adapter_master_xactor_crg_rd_data_full ;
  assign mmio_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write =
	     master1_rvalid &&
	     !mmio_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ;
  assign mmio_axi4_adapter_master_xactor_crg_rd_data_full$port3__read =
	     mmio_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write ||
	     mmio_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ;
  assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write =
	     WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	     mmio_axi4_adapter_soc_map$m_is_IO_addr ;
  assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 =
	     mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ;
  assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 =
	     b__h2352 - 4'd1 ;
  assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read =
	     WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ?
	       mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 :
	       b__h2352 ;
  assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write =
	     llc_axi4_adapter_master_xactor_crg_wr_addr_full &&
	     master0_awready ;
  assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read =
	     !llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write &&
	     llc_axi4_adapter_master_xactor_crg_wr_addr_full ;
  assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ||
	     llc_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read ;
  assign llc_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write =
	     llc_axi4_adapter_master_xactor_crg_wr_data_full &&
	     master0_wready ;
  assign llc_axi4_adapter_master_xactor_crg_wr_data_full$port2__read =
	     !llc_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write &&
	     llc_axi4_adapter_master_xactor_crg_wr_data_full ;
  assign llc_axi4_adapter_master_xactor_crg_wr_data_full$port3__read =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ||
	     llc_axi4_adapter_master_xactor_crg_wr_data_full$port2__read ;
  assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read =
	     !CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	     llc_axi4_adapter_master_xactor_crg_wr_resp_full ;
  assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write =
	     master0_bvalid &&
	     !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;
  assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read =
	     llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write ||
	     llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;
  assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write =
	     llc_axi4_adapter_master_xactor_crg_rd_addr_full &&
	     master0_arready ;
  assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read =
	     !llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write &&
	     llc_axi4_adapter_master_xactor_crg_rd_addr_full ;
  assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ||
	     llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read ;
  assign llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read =
	     !CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	     llc_axi4_adapter_master_xactor_crg_rd_data_full ;
  assign llc_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write =
	     master0_rvalid &&
	     !llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ;
  assign llc_axi4_adapter_master_xactor_crg_rd_data_full$port3__read =
	     llc_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write ||
	     llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ;
  assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 =
	     llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ;
  assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 =
	     b__h134523 - 4'd1 ;
  assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ?
	       llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 :
	       b__h134523 ;

  // register cfg_verbosity
  assign cfg_verbosity$D_IN = set_verbosity_verbosity ;
  assign cfg_verbosity$EN = EN_set_verbosity ;

  // register enqDst_0_rl
  assign enqDst_0_rl$D_IN =
	     { !CAN_FIRE_RL_doEnq &&
	       IF_enqDst_0_lat_0_whas__038_THEN_enqDst_0_lat__ETC___d1043,
	       CAN_FIRE_RL_doEnq ?
		 73'h0AAAAAAAAAAAAAAAAAA :
		 (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ?
		    enqDst_0_lat_0$wget[72:0] :
		    enqDst_0_rl[72:0]) } ;
  assign enqDst_0_rl$EN = 1'd1 ;

  // register enqDst_1_0_rl
  assign enqDst_1_0_rl$D_IN =
	     { !CAN_FIRE_RL_doEnq_1 &&
	       IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1279,
	       IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1318 } ;
  assign enqDst_1_0_rl$EN = 1'd1 ;

  // register llc_axi4_adapter_cfg_verbosity
  assign llc_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ;
  assign llc_axi4_adapter_cfg_verbosity$EN = 1'b0 ;

  // register llc_axi4_adapter_ctr_wr_rsps_pending_crg
  assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN =
	     llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ;
  assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN = 1'b1 ;

  // register llc_axi4_adapter_master_xactor_crg_rd_addr_full
  assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN =
	     llc_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read ;
  assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN = 1'b1 ;

  // register llc_axi4_adapter_master_xactor_crg_rd_data_full
  assign llc_axi4_adapter_master_xactor_crg_rd_data_full$D_IN =
	     llc_axi4_adapter_master_xactor_crg_rd_data_full$port3__read ;
  assign llc_axi4_adapter_master_xactor_crg_rd_data_full$EN = 1'b1 ;

  // register llc_axi4_adapter_master_xactor_crg_wr_addr_full
  assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN =
	     llc_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read ;
  assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN = 1'b1 ;

  // register llc_axi4_adapter_master_xactor_crg_wr_data_full
  assign llc_axi4_adapter_master_xactor_crg_wr_data_full$D_IN =
	     llc_axi4_adapter_master_xactor_crg_wr_data_full$port3__read ;
  assign llc_axi4_adapter_master_xactor_crg_wr_data_full$EN = 1'b1 ;

  // register llc_axi4_adapter_master_xactor_crg_wr_resp_full
  assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN =
	     llc_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read ;
  assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN = 1'b1 ;

  // register llc_axi4_adapter_master_xactor_rg_rd_addr
  assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN =
	     { 4'd0, mem_req_rd_addr_araddr__h134816, 29'd851968 } ;
  assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ;

  // register llc_axi4_adapter_master_xactor_rg_rd_data
  assign llc_axi4_adapter_master_xactor_rg_rd_data$D_IN =
	     { master0_rid, master0_rdata, master0_rresp, master0_rlast } ;
  assign llc_axi4_adapter_master_xactor_rg_rd_data$EN = 1'd1 ;

  // register llc_axi4_adapter_master_xactor_rg_wr_addr
  assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN =
	     { 4'd0, mem_req_wr_addr_awaddr__h148740, 29'd851968 } ;
  assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ;

  // register llc_axi4_adapter_master_xactor_rg_wr_data
  assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN =
	     { data64__h148655, strb8__h148656, 1'd1 } ;
  assign llc_axi4_adapter_master_xactor_rg_wr_data$EN =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ;

  // register llc_axi4_adapter_master_xactor_rg_wr_resp
  assign llc_axi4_adapter_master_xactor_rg_wr_resp$D_IN =
	     { master0_bid, master0_bresp } ;
  assign llc_axi4_adapter_master_xactor_rg_wr_resp$EN =
	     master0_bvalid &&
	     !llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;

  // register llc_axi4_adapter_rg_cline
  assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h135518 ;
  assign llc_axi4_adapter_rg_cline$EN =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ;

  // register llc_axi4_adapter_rg_rd_req_beat
  assign llc_axi4_adapter_rg_rd_req_beat$D_IN =
	     llc_axi4_adapter_rg_rd_req_beat + 3'd1 ;
  assign llc_axi4_adapter_rg_rd_req_beat$EN =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ;

  // register llc_axi4_adapter_rg_rd_rsp_beat
  assign llc_axi4_adapter_rg_rd_rsp_beat$D_IN =
	     llc_axi4_adapter_rg_rd_rsp_beat + 3'd1 ;
  assign llc_axi4_adapter_rg_rd_rsp_beat$EN =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ;

  // register llc_axi4_adapter_rg_wr_req_beat
  assign llc_axi4_adapter_rg_wr_req_beat$D_IN =
	     llc_axi4_adapter_rg_wr_req_beat + 3'd1 ;
  assign llc_axi4_adapter_rg_wr_req_beat$EN =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ;

  // register llc_axi4_adapter_rg_wr_rsp_beat
  assign llc_axi4_adapter_rg_wr_rsp_beat$D_IN =
	     llc_axi4_adapter_rg_wr_rsp_beat + 3'd1 ;
  assign llc_axi4_adapter_rg_wr_rsp_beat$EN =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ;

  // register llc_mem_server_enqDst_0_rl
  assign llc_mem_server_enqDst_0_rl$D_IN =
	     { !CAN_FIRE_RL_llc_mem_server_doEnq &&
	       IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681,
	       CAN_FIRE_RL_llc_mem_server_doEnq ?
		 65'h0AAAAAAAAAAAAAAAA :
		 (NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ?
		    llc_mem_server_enqDst_0_lat_0$wget[64:0] :
		    llc_mem_server_enqDst_0_rl[64:0]) } ;
  assign llc_mem_server_enqDst_0_rl$EN = 1'd1 ;

  // register llc_mem_server_propDstData_0_rl
  assign llc_mem_server_propDstData_0_rl$D_IN =
	     CAN_FIRE_RL_llc_mem_server_srcPropose ?
	       core_0$tlbToMem_memReq_first :
	       llc_mem_server_propDstData_0_rl ;
  assign llc_mem_server_propDstData_0_rl$EN = 1'd1 ;

  // register llc_mem_server_propDstIdx_0_rl
  assign llc_mem_server_propDstIdx_0_rl$D_IN =
	     !NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 &&
	     IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664 ;
  assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ;

  // register llc_mem_server_rg_cacheline_cache_addr
  assign llc_mem_server_rg_cacheline_cache_addr$D_IN =
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ?
	       line_addr__h102521 :
	       line_addr__h102607 ;
  assign llc_mem_server_rg_cacheline_cache_addr$EN =
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ||
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ;

  // register llc_mem_server_rg_cacheline_cache_data
  assign llc_mem_server_rg_cacheline_cache_data$D_IN =
	     WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ?
	       MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 :
	       llc$dma_respLd_first[516:5] ;
  assign llc_mem_server_rg_cacheline_cache_data$EN =
	     WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ||
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ;

  // register llc_mem_server_rg_cacheline_cache_dirty_delay
  assign llc_mem_server_rg_cacheline_cache_dirty_delay$D_IN =
	     WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ?
	       10'd1023 :
	       MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 ;
  assign llc_mem_server_rg_cacheline_cache_dirty_delay$EN =
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay ||
	     WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ;

  // register llc_mem_server_rg_cacheline_cache_state
  always@(MUX_llc$dma_memReq_enq_1__SEL_1 or
	  MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2 or
	  MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3 or
	  WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_llc$dma_memReq_enq_1__SEL_1:
	  llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd1;
      MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2:
	  llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd2;
      MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3:
	  llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd3;
      WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req:
	  llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd4;
      default: llc_mem_server_rg_cacheline_cache_state$D_IN =
		   3'b010 /* unspecified value */ ;
    endcase
  end
  assign llc_mem_server_rg_cacheline_cache_state$EN =
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss ||
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss ||
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ||
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ||
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ||
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ||
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish ||
	     WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ;

  // register mmioPlatform_amoResp
  assign mmioPlatform_amoResp$D_IN =
	     MUX_mmioPlatform_amoResp$write_1__SEL_1 ?
	       MUX_mmioPlatform_amoResp$write_1__VAL_1 :
	       MUX_mmioPlatform_amoResp$write_1__VAL_2 ;
  assign mmioPlatform_amoResp$EN =
	     WILL_FIRE_RL_mmioPlatform_processMTimeCmp &&
	     mmioPlatform_reqFunc[5:4] != 2'd0 &&
	     mmioPlatform_reqFunc[5:4] != 2'd1 ||
	     WILL_FIRE_RL_mmioPlatform_processMTime &&
	     mmioPlatform_reqFunc[5:4] != 2'd0 &&
	     mmioPlatform_reqFunc[5:4] != 2'd1 ;

  // register mmioPlatform_curReq
  assign mmioPlatform_curReq$D_IN =
	     MUX_mmioPlatform_curReq$write_1__SEL_1 ?
	       MUX_mmioPlatform_curReq$write_1__VAL_1 :
	       MUX_mmioPlatform_curReq$write_1__VAL_2 ;
  assign mmioPlatform_curReq$EN =
	     MUX_mmioPlatform_curReq$write_1__SEL_1 ||
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp &&
	     mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] &&
	     mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 ;

  // register mmioPlatform_cycle
  assign mmioPlatform_cycle$D_IN =
	     WILL_FIRE_RL_mmioPlatform_incCycle ?
	       MUX_mmioPlatform_cycle$write_1__VAL_1 :
	       7'd0 ;
  assign mmioPlatform_cycle$EN =
	     WILL_FIRE_RL_mmioPlatform_incCycle ||
	     WILL_FIRE_RL_mmioPlatform_incTime ;

  // register mmioPlatform_fetchedInsts_0
  assign mmioPlatform_fetchedInsts_0$D_IN =
	     SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987 ;
  assign mmioPlatform_fetchedInsts_0$EN =
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp &&
	     mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] &&
	     mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 &&
	     !mmioPlatform_fetchingWay ;

  // register mmioPlatform_fetchingWay
  assign mmioPlatform_fetchingWay$D_IN =
	     !MUX_mmioPlatform_fetchingWay$write_1__SEL_1 &&
	     MUX_mmioPlatform_fetchingWay$write_1__VAL_2 ;
  assign mmioPlatform_fetchingWay$EN =
	     WILL_FIRE_RL_mmioPlatform_selectReq &&
	     (mmioPlatform_mtip_0 ||
	      !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) &&
	     core_0$mmioToPlatform_cRq_notEmpty ||
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp &&
	     mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] &&
	     mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 ;

  // register mmioPlatform_fromHostAddr
  assign mmioPlatform_fromHostAddr$D_IN = start_fromhostAddr[63:3] ;
  assign mmioPlatform_fromHostAddr$EN = EN_start ;

  // register mmioPlatform_fromHostQ_clearReq_rl
  assign mmioPlatform_fromHostQ_clearReq_rl$D_IN = 1'd0 ;
  assign mmioPlatform_fromHostQ_clearReq_rl$EN = 1'd1 ;

  // register mmioPlatform_fromHostQ_data_0
  assign mmioPlatform_fromHostQ_data_0$D_IN =
	     mmioPlatform_fromHostQ_enqReq_rl[63:0] ;
  assign mmioPlatform_fromHostQ_data_0$EN =
	     NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d318 &&
	     mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT &&
	     mmioPlatform_fromHostQ_enqReq_rl[64] ;

  // register mmioPlatform_fromHostQ_deqReq_rl
  assign mmioPlatform_fromHostQ_deqReq_rl$D_IN = 1'd0 ;
  assign mmioPlatform_fromHostQ_deqReq_rl$EN = 1'd1 ;

  // register mmioPlatform_fromHostQ_empty
  assign mmioPlatform_fromHostQ_empty$D_IN =
	     mmioPlatform_fromHostQ_clearReq_dummy2_1$Q_OUT &&
	     mmioPlatform_fromHostQ_clearReq_rl ||
	     NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d339 ;
  assign mmioPlatform_fromHostQ_empty$EN = 1'd1 ;

  // register mmioPlatform_fromHostQ_enqReq_rl
  assign mmioPlatform_fromHostQ_enqReq_rl$D_IN = 65'h0AAAAAAAAAAAAAAAA ;
  assign mmioPlatform_fromHostQ_enqReq_rl$EN = 1'd1 ;

  // register mmioPlatform_fromHostQ_full
  assign mmioPlatform_fromHostQ_full$D_IN =
	     NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d318 &&
	     mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331 ;
  assign mmioPlatform_fromHostQ_full$EN = 1'd1 ;

  // register mmioPlatform_instSel
  assign mmioPlatform_instSel$D_IN =
	     MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ?
	       core_0$mmioToPlatform_cRq_first[80] :
	       MUX_mmioPlatform_instSel$write_1__VAL_2 ;
  assign mmioPlatform_instSel$EN =
	     WILL_FIRE_RL_mmioPlatform_selectReq &&
	     (mmioPlatform_mtip_0 ||
	      !mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357) &&
	     core_0$mmioToPlatform_cRq_notEmpty ||
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp &&
	     mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] &&
	     mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 ;

  // register mmioPlatform_mtime
  assign mmioPlatform_mtime$D_IN =
	     MUX_mmioPlatform_amoResp$write_1__SEL_2 ?
	       newData__h34749 :
	       MUX_mmioPlatform_mtime$write_1__VAL_2 ;
  assign mmioPlatform_mtime$EN =
	     WILL_FIRE_RL_mmioPlatform_processMTime &&
	     mmioPlatform_reqFunc[5:4] != 2'd0 &&
	     mmioPlatform_reqFunc[5:4] != 2'd1 ||
	     WILL_FIRE_RL_mmioPlatform_incTime ;

  // register mmioPlatform_mtimecmp_0
  assign mmioPlatform_mtimecmp_0$D_IN = newData__h31819 ;
  assign mmioPlatform_mtimecmp_0$EN =
	     MUX_mmioPlatform_amoResp$write_1__SEL_1 ;

  // register mmioPlatform_mtip_0
  assign mmioPlatform_mtip_0$D_IN =
	     MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 ||
	     MUX_mmioPlatform_mtip_0$write_1__VAL_2 ;
  assign mmioPlatform_mtip_0$EN =
	     WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 &&
	     mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 ||
	     WILL_FIRE_RL_mmioPlatform_processMTimeCmp &&
	     NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 ;

  // register mmioPlatform_reqAmofunc
  assign mmioPlatform_reqAmofunc$D_IN =
	     (core_0$mmioToPlatform_cRq_first[77:76] != 2'd0 &&
	      core_0$mmioToPlatform_cRq_first[77:76] != 2'd1 &&
	      core_0$mmioToPlatform_cRq_first[77:76] != 2'd2) ?
	       core_0$mmioToPlatform_cRq_first[75:72] :
	       4'd9 ;
  assign mmioPlatform_reqAmofunc$EN =
	     MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ;

  // register mmioPlatform_reqBE
  assign mmioPlatform_reqBE$D_IN = core_0$mmioToPlatform_cRq_first[71:64] ;
  assign mmioPlatform_reqBE$EN = MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ;

  // register mmioPlatform_reqData
  assign mmioPlatform_reqData$D_IN = core_0$mmioToPlatform_cRq_first[63:0] ;
  assign mmioPlatform_reqData$EN =
	     MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ;

  // register mmioPlatform_reqFunc
  always@(core_0$mmioToPlatform_cRq_first)
  begin
    case (core_0$mmioToPlatform_cRq_first[77:76])
      2'd0, 2'd1, 2'd2:
	  mmioPlatform_reqFunc$D_IN = core_0$mmioToPlatform_cRq_first[77:72];
      2'd3:
	  mmioPlatform_reqFunc$D_IN =
	      { 2'd3, core_0$mmioToPlatform_cRq_first[75:72] };
    endcase
  end
  assign mmioPlatform_reqFunc$EN =
	     MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ;

  // register mmioPlatform_reqSz
  assign mmioPlatform_reqSz$D_IN = 2'b11 ;
  assign mmioPlatform_reqSz$EN = MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ;

  // register mmioPlatform_state
  always@(MUX_mmioPlatform_curReq$write_1__SEL_1 or
	  MUX_mmioPlatform_state$write_1__VAL_1 or
	  WILL_FIRE_RL_mmioPlatform_processMSIP or
	  MUX_mmioPlatform_state$write_1__VAL_2 or
	  WILL_FIRE_RL_mmioPlatform_processMTimeCmp or
	  MUX_mmioPlatform_state$write_1__VAL_3 or
	  WILL_FIRE_RL_mmioPlatform_processMTime or
	  MUX_mmioPlatform_state$write_1__VAL_4 or
	  WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp or
	  MUX_mmioPlatform_state$write_1__VAL_5 or
	  MUX_mmioPlatform_state$write_1__SEL_6 or
	  MUX_mmioPlatform_state$write_1__SEL_7)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_mmioPlatform_curReq$write_1__SEL_1:
	  mmioPlatform_state$D_IN = MUX_mmioPlatform_state$write_1__VAL_1;
      WILL_FIRE_RL_mmioPlatform_processMSIP:
	  mmioPlatform_state$D_IN = MUX_mmioPlatform_state$write_1__VAL_2;
      WILL_FIRE_RL_mmioPlatform_processMTimeCmp:
	  mmioPlatform_state$D_IN = MUX_mmioPlatform_state$write_1__VAL_3;
      WILL_FIRE_RL_mmioPlatform_processMTime:
	  mmioPlatform_state$D_IN = MUX_mmioPlatform_state$write_1__VAL_4;
      WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp:
	  mmioPlatform_state$D_IN = MUX_mmioPlatform_state$write_1__VAL_5;
      MUX_mmioPlatform_state$write_1__SEL_6: mmioPlatform_state$D_IN = 2'd1;
      MUX_mmioPlatform_state$write_1__SEL_7: mmioPlatform_state$D_IN = 2'd3;
      default: mmioPlatform_state$D_IN = 2'b10 /* unspecified value */ ;
    endcase
  end
  assign mmioPlatform_state$EN =
	     MUX_mmioPlatform_curReq$write_1__SEL_1 ||
	     WILL_FIRE_RL_mmioPlatform_processMSIP ||
	     WILL_FIRE_RL_mmioPlatform_processMTimeCmp ||
	     WILL_FIRE_RL_mmioPlatform_processMTime ||
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ||
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ||
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ||
	     WILL_FIRE_RL_mmioPlatform_processFromHost ||
	     WILL_FIRE_RL_mmioPlatform_processToHost ||
	     WILL_FIRE_RL_mmioPlatform_waitMTimeDone ||
	     WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone ||
	     WILL_FIRE_RL_mmioPlatform_waitMSIPDone ||
	     WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone ||
	     EN_start ||
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ||
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ||
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ;

  // register mmioPlatform_toHostAddr
  assign mmioPlatform_toHostAddr$D_IN = start_tohostAddr[63:3] ;
  assign mmioPlatform_toHostAddr$EN = EN_start ;

  // register mmioPlatform_toHostQ_clearReq_rl
  assign mmioPlatform_toHostQ_clearReq_rl$D_IN = 1'd0 ;
  assign mmioPlatform_toHostQ_clearReq_rl$EN = 1'd1 ;

  // register mmioPlatform_toHostQ_data_0
  assign mmioPlatform_toHostQ_data_0$D_IN =
	     mmioPlatform_toHostQ_enqReq_lat_0$whas ?
	       mmioPlatform_toHostQ_enqReq_lat_0$wget[63:0] :
	       mmioPlatform_toHostQ_enqReq_rl[63:0] ;
  assign mmioPlatform_toHostQ_data_0$EN =
	     NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d240 &&
	     mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200 ;

  // register mmioPlatform_toHostQ_deqReq_rl
  assign mmioPlatform_toHostQ_deqReq_rl$D_IN = 1'd0 ;
  assign mmioPlatform_toHostQ_deqReq_rl$EN = 1'd1 ;

  // register mmioPlatform_toHostQ_empty
  assign mmioPlatform_toHostQ_empty$D_IN =
	     mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT &&
	     mmioPlatform_toHostQ_clearReq_rl ||
	     NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d261 ;
  assign mmioPlatform_toHostQ_empty$EN = 1'd1 ;

  // register mmioPlatform_toHostQ_enqReq_rl
  assign mmioPlatform_toHostQ_enqReq_rl$D_IN = 65'h0AAAAAAAAAAAAAAAA ;
  assign mmioPlatform_toHostQ_enqReq_rl$EN = 1'd1 ;

  // register mmioPlatform_toHostQ_full
  assign mmioPlatform_toHostQ_full$D_IN =
	     NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d240 &&
	     mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253 ;
  assign mmioPlatform_toHostQ_full$EN = 1'd1 ;

  // register mmioPlatform_waitLowerMSIPCRs
  assign mmioPlatform_waitLowerMSIPCRs$D_IN =
	     mmioPlatform_reqFunc[5:4] != 2'd1 &&
	     mmioPlatform_reqFunc[5:4] != 2'd2 ||
	     mmioPlatform_reqBE[0] ;
  assign mmioPlatform_waitLowerMSIPCRs$EN =
	     WILL_FIRE_RL_mmioPlatform_processMSIP &&
	     NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 ;

  // register mmioPlatform_waitMTIPCRs
  assign mmioPlatform_waitMTIPCRs$D_IN =
	     MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 ||
	     MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 ;
  assign mmioPlatform_waitMTIPCRs$EN =
	     WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 &&
	     mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 ||
	     WILL_FIRE_RL_mmioPlatform_processMTime &&
	     NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ;

  // register mmioPlatform_waitUpperMSIPCRs
  assign mmioPlatform_waitUpperMSIPCRs$D_IN = 1'd0 ;
  assign mmioPlatform_waitUpperMSIPCRs$EN =
	     WILL_FIRE_RL_mmioPlatform_processMSIP &&
	     NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 ;

  // register mmio_axi4_adapter_cfg_verbosity
  assign mmio_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ;
  assign mmio_axi4_adapter_cfg_verbosity$EN = 1'b0 ;

  // register mmio_axi4_adapter_ctr_wr_rsps_pending_crg
  assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN =
	     mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ;
  assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN = 1'b1 ;

  // register mmio_axi4_adapter_master_xactor_crg_rd_addr_full
  assign mmio_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN =
	     mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read ;
  assign mmio_axi4_adapter_master_xactor_crg_rd_addr_full$EN = 1'b1 ;

  // register mmio_axi4_adapter_master_xactor_crg_rd_data_full
  assign mmio_axi4_adapter_master_xactor_crg_rd_data_full$D_IN =
	     mmio_axi4_adapter_master_xactor_crg_rd_data_full$port3__read ;
  assign mmio_axi4_adapter_master_xactor_crg_rd_data_full$EN = 1'b1 ;

  // register mmio_axi4_adapter_master_xactor_crg_wr_addr_full
  assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN =
	     mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read ;
  assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN = 1'b1 ;

  // register mmio_axi4_adapter_master_xactor_crg_wr_data_full
  assign mmio_axi4_adapter_master_xactor_crg_wr_data_full$D_IN =
	     mmio_axi4_adapter_master_xactor_crg_wr_data_full$port3__read ;
  assign mmio_axi4_adapter_master_xactor_crg_wr_data_full$EN = 1'b1 ;

  // register mmio_axi4_adapter_master_xactor_crg_wr_resp_full
  assign mmio_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN =
	     mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read ;
  assign mmio_axi4_adapter_master_xactor_crg_wr_resp_full$EN = 1'b1 ;

  // register mmio_axi4_adapter_master_xactor_rg_rd_addr
  assign mmio_axi4_adapter_master_xactor_rg_rd_addr$D_IN =
	     { 4'd0,
	       mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78],
	       29'd851968 } ;
  assign mmio_axi4_adapter_master_xactor_rg_rd_addr$EN =
	     WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	     mmio_axi4_adapter_soc_map$m_is_IO_addr ;

  // register mmio_axi4_adapter_master_xactor_rg_rd_data
  assign mmio_axi4_adapter_master_xactor_rg_rd_data$D_IN =
	     { master1_rid, master1_rdata, master1_rresp, master1_rlast } ;
  assign mmio_axi4_adapter_master_xactor_rg_rd_data$EN = 1'd1 ;

  // register mmio_axi4_adapter_master_xactor_rg_wr_addr
  assign mmio_axi4_adapter_master_xactor_rg_wr_addr$D_IN =
	     { 4'd0,
	       mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78],
	       8'd0,
	       x__h7713,
	       18'd65536 } ;
  assign mmio_axi4_adapter_master_xactor_rg_wr_addr$EN =
	     WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	     mmio_axi4_adapter_soc_map$m_is_IO_addr ;

  // register mmio_axi4_adapter_master_xactor_rg_wr_data
  assign mmio_axi4_adapter_master_xactor_rg_wr_data$D_IN =
	     { mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0],
	       mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:64],
	       1'd1 } ;
  assign mmio_axi4_adapter_master_xactor_rg_wr_data$EN =
	     WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	     mmio_axi4_adapter_soc_map$m_is_IO_addr ;

  // register mmio_axi4_adapter_master_xactor_rg_wr_resp
  assign mmio_axi4_adapter_master_xactor_rg_wr_resp$D_IN =
	     { master1_bid, master1_bresp } ;
  assign mmio_axi4_adapter_master_xactor_rg_wr_resp$EN =
	     master1_bvalid &&
	     !mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;

  // register propDstData_0_rl
  assign propDstData_0_rl$D_IN =
	     CAN_FIRE_RL_srcPropose ?
	       propDstData_0_lat_0$wget :
	       propDstData_0_rl ;
  assign propDstData_0_rl$EN = 1'd1 ;

  // register propDstData_1_0_rl
  assign propDstData_1_0_rl$D_IN =
	     { IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203,
	       IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208,
	       CAN_FIRE_RL_srcPropose_2 ?
		 propDstData_1_0_lat_0$wget[513] :
		 propDstData_1_0_rl[513],
	       CAN_FIRE_RL_srcPropose_2 ?
		 propDstData_1_0_lat_0$wget[512:1] :
		 propDstData_1_0_rl[512:1],
	       IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229 } ;
  assign propDstData_1_0_rl$EN = 1'd1 ;

  // register propDstData_1_1_rl
  assign propDstData_1_1_rl$D_IN =
	     { IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241,
	       IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246,
	       CAN_FIRE_RL_srcPropose_3 ?
		 propDstData_1_1_lat_0$wget[513] :
		 propDstData_1_1_rl[513],
	       CAN_FIRE_RL_srcPropose_3 ?
		 propDstData_1_1_lat_0$wget[512:1] :
		 propDstData_1_1_rl[512:1],
	       IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267 } ;
  assign propDstData_1_1_rl$EN = 1'd1 ;

  // register propDstData_1_rl
  assign propDstData_1_rl$D_IN =
	     CAN_FIRE_RL_srcPropose_1 ?
	       propDstData_1_lat_0$wget :
	       propDstData_1_rl ;
  assign propDstData_1_rl$EN = 1'd1 ;

  // register propDstIdx_0_rl
  assign propDstIdx_0_rl$D_IN =
	     !propDstIdx_0_lat_1$whas &&
	     IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 ;
  assign propDstIdx_0_rl$EN = 1'd1 ;

  // register propDstIdx_1_0_rl
  assign propDstIdx_1_0_rl$D_IN =
	     !propDstIdx_1_0_lat_1$whas &&
	     IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 ;
  assign propDstIdx_1_0_rl$EN = 1'd1 ;

  // register propDstIdx_1_1_rl
  assign propDstIdx_1_1_rl$D_IN =
	     !propDstIdx_1_1_lat_1$whas &&
	     IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193 ;
  assign propDstIdx_1_1_rl$EN = 1'd1 ;

  // register propDstIdx_1_rl
  assign propDstIdx_1_rl$D_IN =
	     !propDstIdx_1_lat_1$whas &&
	     IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019 ;
  assign propDstIdx_1_rl$EN = 1'd1 ;

  // register srcRR_0
  assign srcRR_0$D_IN = srcRR_0 + 1'd1 ;
  assign srcRR_0$EN =
	     NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ;

  // register srcRR_1_0
  assign srcRR_1_0$D_IN = srcRR_1_0 + 1'd1 ;
  assign srcRR_1_0$EN =
	     NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ;

  // submodule core_0
  assign core_0$coreReq_perfReq_loc = 4'h0 ;
  assign core_0$coreReq_perfReq_t = 5'h0 ;
  assign core_0$coreReq_start_fromHostAddr = start_fromhostAddr ;
  assign core_0$coreReq_start_running = start_running ;
  assign core_0$coreReq_start_startpc = start_startpc ;
  assign core_0$coreReq_start_toHostAddr = start_tohostAddr ;
  assign core_0$dCacheToParent_fromP_enq_x =
	     WILL_FIRE_RL_sendPRq ?
	       MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 :
	       MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 ;
  assign core_0$iCacheToParent_fromP_enq_x =
	     WILL_FIRE_RL_sendPRq_1 ?
	       MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 :
	       MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 ;
  always@(MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 or
	  MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 or
	  MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 or
	  MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 or
	  MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 or
	  MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 or
	  MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1:
	  core_0$mmioToPlatform_pRq_enq_x = 39'h6A00000001;
      MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2:
	  core_0$mmioToPlatform_pRq_enq_x =
	      MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2;
      MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3:
	  core_0$mmioToPlatform_pRq_enq_x =
	      MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3;
      MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4:
	  core_0$mmioToPlatform_pRq_enq_x =
	      MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4;
      default: core_0$mmioToPlatform_pRq_enq_x =
		   39'h2AAAAAAAAA /* unspecified value */ ;
    endcase
  end
  always@(MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 or
	  MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_1 or
	  MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 or
	  MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_2 or
	  MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 or
	  MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3 or
	  MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 or
	  MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 or
	  MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 or
	  MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 or
	  WILL_FIRE_RL_mmioPlatform_waitMSIPDone or
	  MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 or
	  WILL_FIRE_RL_mmioPlatform_processToHost or
	  MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 or
	  WILL_FIRE_RL_mmioPlatform_processFromHost or
	  MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 or
	  WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp or
	  MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 or
	  WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp or
	  MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1:
	  core_0$mmioToPlatform_pRs_enq_x =
	      MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_1;
      MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2:
	  core_0$mmioToPlatform_pRs_enq_x =
	      MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_2;
      MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3:
	  core_0$mmioToPlatform_pRs_enq_x =
	      MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3;
      MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4:
	  core_0$mmioToPlatform_pRs_enq_x =
	      MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4;
      MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5:
	  core_0$mmioToPlatform_pRs_enq_x =
	      MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5;
      WILL_FIRE_RL_mmioPlatform_waitMSIPDone:
	  core_0$mmioToPlatform_pRs_enq_x =
	      MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6;
      WILL_FIRE_RL_mmioPlatform_processToHost:
	  core_0$mmioToPlatform_pRs_enq_x =
	      MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7;
      WILL_FIRE_RL_mmioPlatform_processFromHost:
	  core_0$mmioToPlatform_pRs_enq_x =
	      MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8;
      WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp:
	  core_0$mmioToPlatform_pRs_enq_x =
	      MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9;
      WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp:
	  core_0$mmioToPlatform_pRs_enq_x =
	      MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10;
      default: core_0$mmioToPlatform_pRs_enq_x =
		   67'h2AAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign core_0$mmioToPlatform_setTime_t = mmioPlatform_mtime ;
  assign core_0$recvDoStats_x = core_0$sendDoStats ;
  assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ;
  assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ;
  assign core_0$tlbToMem_respLd_enq_x =
	     { ld_data__h132744, llc$dma_respLd_first[3] } ;
  assign core_0$EN_coreReq_start = EN_start ;
  assign core_0$EN_coreReq_perfReq = 1'b0 ;
  assign core_0$EN_coreIndInv_perfResp = 1'b0 ;
  assign core_0$EN_coreIndInv_terminate = core_0$RDY_coreIndInv_terminate ;
  assign core_0$EN_dCacheToParent_rsToP_deq = CAN_FIRE_RL_srcPropose_2 ;
  assign core_0$EN_dCacheToParent_rqToP_deq = CAN_FIRE_RL_srcPropose ;
  assign core_0$EN_dCacheToParent_fromP_enq =
	     WILL_FIRE_RL_sendPRq || WILL_FIRE_RL_sendPRs ;
  assign core_0$EN_iCacheToParent_rsToP_deq = CAN_FIRE_RL_srcPropose_3 ;
  assign core_0$EN_iCacheToParent_rqToP_deq = CAN_FIRE_RL_srcPropose_1 ;
  assign core_0$EN_iCacheToParent_fromP_enq =
	     WILL_FIRE_RL_sendPRq_1 || WILL_FIRE_RL_sendPRs_1 ;
  assign core_0$EN_tlbToMem_memReq_deq =
	     CAN_FIRE_RL_llc_mem_server_srcPropose ;
  assign core_0$EN_tlbToMem_respLd_enq =
	     CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb ;
  assign core_0$EN_mmioToPlatform_cRq_deq =
	     MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ;
  assign core_0$EN_mmioToPlatform_pRs_enq =
	     WILL_FIRE_RL_mmioPlatform_processMSIP &&
	     mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 ||
	     WILL_FIRE_RL_mmioPlatform_processMTimeCmp &&
	     mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 ||
	     WILL_FIRE_RL_mmioPlatform_processMTime &&
	     mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 ||
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp &&
	     (!mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 ||
	      !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) ||
	     WILL_FIRE_RL_mmioPlatform_waitMTimeDone ||
	     WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone ||
	     WILL_FIRE_RL_mmioPlatform_waitMSIPDone ||
	     WILL_FIRE_RL_mmioPlatform_processToHost ||
	     WILL_FIRE_RL_mmioPlatform_processFromHost ||
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ||
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ;
  assign core_0$EN_mmioToPlatform_pRq_enq =
	     WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 &&
	     mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 ||
	     WILL_FIRE_RL_mmioPlatform_processMSIP &&
	     mmioPlatform_reqFunc[5:4] != 2'd0 &&
	     !mmioPlatform_reqBE[4] &&
	     mmioPlatform_reqBE[0] ||
	     WILL_FIRE_RL_mmioPlatform_processMTimeCmp &&
	     NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 ||
	     WILL_FIRE_RL_mmioPlatform_processMTime &&
	     NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 ;
  assign core_0$EN_mmioToPlatform_cRs_deq =
	     (WILL_FIRE_RL_mmioPlatform_waitMTimeDone ||
	      WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone) &&
	     mmioPlatform_waitMTIPCRs ||
	     WILL_FIRE_RL_mmioPlatform_waitMSIPDone &&
	     (mmioPlatform_waitLowerMSIPCRs ||
	      mmioPlatform_waitUpperMSIPCRs) ||
	     WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone ;
  assign core_0$EN_mmioToPlatform_setTime =
	     CAN_FIRE_RL_mmioPlatform_propagateTime ;
  assign core_0$EN_sendDoStats = core_0$RDY_sendDoStats ;
  assign core_0$EN_recvDoStats = core_0$RDY_sendDoStats ;
  assign core_0$EN_deadlock_dCacheCRqStuck_get =
	     core_0$RDY_deadlock_dCacheCRqStuck_get ;
  assign core_0$EN_deadlock_dCachePRqStuck_get =
	     core_0$RDY_deadlock_dCachePRqStuck_get ;
  assign core_0$EN_deadlock_iCacheCRqStuck_get =
	     core_0$RDY_deadlock_iCacheCRqStuck_get ;
  assign core_0$EN_deadlock_iCachePRqStuck_get =
	     core_0$RDY_deadlock_iCachePRqStuck_get ;
  assign core_0$EN_deadlock_renameInstStuck_get =
	     core_0$RDY_deadlock_renameInstStuck_get ;
  assign core_0$EN_deadlock_renameCorrectPathStuck_get =
	     core_0$RDY_deadlock_renameCorrectPathStuck_get ;
  assign core_0$EN_deadlock_commitInstStuck_get =
	     core_0$RDY_deadlock_commitInstStuck_get ;
  assign core_0$EN_deadlock_commitUserInstStuck_get =
	     core_0$RDY_deadlock_commitUserInstStuck_get ;
  assign core_0$EN_deadlock_checkStarted_get =
	     core_0$RDY_deadlock_checkStarted_get ;
  assign core_0$EN_renameDebug_renameErr_get =
	     core_0$RDY_renameDebug_renameErr_get ;
  assign core_0$EN_setMEIP = 1'd1 ;
  assign core_0$EN_setSEIP = 1'd1 ;

  // submodule enqDst_0_dummy2_0
  assign enqDst_0_dummy2_0$D_IN = 1'd1 ;
  assign enqDst_0_dummy2_0$EN =
	     NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ;

  // submodule enqDst_0_dummy2_1
  assign enqDst_0_dummy2_1$D_IN = 1'd1 ;
  assign enqDst_0_dummy2_1$EN = CAN_FIRE_RL_doEnq ;

  // submodule enqDst_1_0_dummy2_0
  assign enqDst_1_0_dummy2_0$D_IN = 1'd1 ;
  assign enqDst_1_0_dummy2_0$EN =
	     NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ;

  // submodule enqDst_1_0_dummy2_1
  assign enqDst_1_0_dummy2_1$D_IN = 1'd1 ;
  assign enqDst_1_0_dummy2_1$EN = CAN_FIRE_RL_doEnq_1 ;

  // submodule llc
  always@(MUX_llc$dma_memReq_enq_1__SEL_1 or
	  MUX_llc$dma_memReq_enq_1__VAL_1 or
	  WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st or
	  MUX_llc$dma_memReq_enq_1__VAL_2 or
	  WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld or
	  MUX_llc$dma_memReq_enq_1__VAL_3 or
	  WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC or
	  MUX_llc$dma_memReq_enq_1__VAL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_llc$dma_memReq_enq_1__SEL_1:
	  llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_1;
      WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st:
	  llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_2;
      WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld:
	  llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_3;
      WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC:
	  llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_4;
      default: llc$dma_memReq_enq_x =
		   645'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign llc$perf_req_r = 4'h0 ;
  assign llc$perf_setStatus_doStats = core_0$sendDoStats ;
  assign llc$to_child_rqFromC_enq_x =
	     NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ?
	       enqDst_0_lat_0$wget[72:0] :
	       enqDst_0_rl[72:0] ;
  assign llc$to_child_rsFromC_enq_x =
	     { IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1289,
	       IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294,
	       IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1299,
	       IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309,
	       IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315 } ;
  assign llc$to_mem_rsFromM_enq_x =
	     { new_cline__h135518,
	       llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ;
  assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ;
  assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ;
  assign llc$EN_to_child_toC_deq =
	     WILL_FIRE_RL_sendPRs_1 || WILL_FIRE_RL_sendPRq_1 ||
	     WILL_FIRE_RL_sendPRs ||
	     WILL_FIRE_RL_sendPRq ;
  assign llc$EN_dma_memReq_enq =
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss ||
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss ||
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ||
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ||
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ||
	     WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC ;
  assign llc$EN_dma_respLd_deq =
	     WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb ||
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ;
  assign llc$EN_dma_respSt_deq =
	     WILL_FIRE_RL_llc_mem_server_sendStRespToTlb ||
	     WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish ;
  assign llc$EN_to_mem_toM_deq =
	     WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	     llc_axi4_adapter_rg_rd_req_beat == 3'd7 ||
	     WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	     llc_axi4_adapter_rg_wr_req_beat == 3'd7 ;
  assign llc$EN_to_mem_rsFromM_enq =
	     WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	     llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 ;
  assign llc$EN_cRqStuck_get = 1'b0 ;
  assign llc$EN_perf_setStatus = core_0$RDY_sendDoStats ;
  assign llc$EN_perf_req = 1'b0 ;
  assign llc$EN_perf_resp = 1'b0 ;

  // submodule llc_axi4_adapter_f_pending_reads
  assign llc_axi4_adapter_f_pending_reads$D_IN = llc$to_mem_toM_first[68:0] ;
  assign llc_axi4_adapter_f_pending_reads$ENQ =
	     WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	     llc_axi4_adapter_rg_rd_req_beat == 3'd0 ;
  assign llc_axi4_adapter_f_pending_reads$DEQ =
	     WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	     llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 ;
  assign llc_axi4_adapter_f_pending_reads$CLR = 1'b0 ;

  // submodule llc_axi4_adapter_f_pending_writes
  assign llc_axi4_adapter_f_pending_writes$D_IN =
	     llc$to_mem_toM_first[639:0] ;
  assign llc_axi4_adapter_f_pending_writes$ENQ =
	     WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	     llc_axi4_adapter_rg_wr_req_beat == 3'd0 ;
  assign llc_axi4_adapter_f_pending_writes$DEQ =
	     WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	     llc_axi4_adapter_rg_wr_rsp_beat == 3'd7 ;
  assign llc_axi4_adapter_f_pending_writes$CLR = 1'b0 ;

  // submodule llc_mem_server_axi4_slave_xactor_f_rd_addr
  assign llc_mem_server_axi4_slave_xactor_f_rd_addr$D_IN =
	     { debug_module_mem_server_arid,
	       debug_module_mem_server_araddr,
	       debug_module_mem_server_arlen,
	       debug_module_mem_server_arsize,
	       debug_module_mem_server_arburst,
	       debug_module_mem_server_arlock,
	       debug_module_mem_server_arcache,
	       debug_module_mem_server_arprot,
	       debug_module_mem_server_arqos,
	       debug_module_mem_server_arregion } ;
  assign llc_mem_server_axi4_slave_xactor_f_rd_addr$ENQ =
	     debug_module_mem_server_arvalid &&
	     llc_mem_server_axi4_slave_xactor_f_rd_addr$FULL_N ;
  assign llc_mem_server_axi4_slave_xactor_f_rd_addr$DEQ =
	     CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ;
  assign llc_mem_server_axi4_slave_xactor_f_rd_addr$CLR = 1'b0 ;

  // submodule llc_mem_server_axi4_slave_xactor_f_rd_data
  assign llc_mem_server_axi4_slave_xactor_f_rd_data$D_IN =
	     { 4'd0, dword__h94457, 3'd1 } ;
  assign llc_mem_server_axi4_slave_xactor_f_rd_data$ENQ =
	     CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ;
  assign llc_mem_server_axi4_slave_xactor_f_rd_data$DEQ =
	     debug_module_mem_server_rready &&
	     llc_mem_server_axi4_slave_xactor_f_rd_data$EMPTY_N ;
  assign llc_mem_server_axi4_slave_xactor_f_rd_data$CLR = 1'b0 ;

  // submodule llc_mem_server_axi4_slave_xactor_f_wr_addr
  assign llc_mem_server_axi4_slave_xactor_f_wr_addr$D_IN =
	     { debug_module_mem_server_awid,
	       debug_module_mem_server_awaddr,
	       debug_module_mem_server_awlen,
	       debug_module_mem_server_awsize,
	       debug_module_mem_server_awburst,
	       debug_module_mem_server_awlock,
	       debug_module_mem_server_awcache,
	       debug_module_mem_server_awprot,
	       debug_module_mem_server_awqos,
	       debug_module_mem_server_awregion } ;
  assign llc_mem_server_axi4_slave_xactor_f_wr_addr$ENQ =
	     debug_module_mem_server_awvalid &&
	     llc_mem_server_axi4_slave_xactor_f_wr_addr$FULL_N ;
  assign llc_mem_server_axi4_slave_xactor_f_wr_addr$DEQ =
	     CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ;
  assign llc_mem_server_axi4_slave_xactor_f_wr_addr$CLR = 1'b0 ;

  // submodule llc_mem_server_axi4_slave_xactor_f_wr_data
  assign llc_mem_server_axi4_slave_xactor_f_wr_data$D_IN =
	     { debug_module_mem_server_wdata,
	       debug_module_mem_server_wstrb,
	       debug_module_mem_server_wlast } ;
  assign llc_mem_server_axi4_slave_xactor_f_wr_data$ENQ =
	     debug_module_mem_server_wvalid &&
	     llc_mem_server_axi4_slave_xactor_f_wr_data$FULL_N ;
  assign llc_mem_server_axi4_slave_xactor_f_wr_data$DEQ =
	     CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ;
  assign llc_mem_server_axi4_slave_xactor_f_wr_data$CLR = 1'b0 ;

  // submodule llc_mem_server_axi4_slave_xactor_f_wr_resp
  assign llc_mem_server_axi4_slave_xactor_f_wr_resp$D_IN = 6'd0 ;
  assign llc_mem_server_axi4_slave_xactor_f_wr_resp$ENQ =
	     CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ;
  assign llc_mem_server_axi4_slave_xactor_f_wr_resp$DEQ =
	     debug_module_mem_server_bready &&
	     llc_mem_server_axi4_slave_xactor_f_wr_resp$EMPTY_N ;
  assign llc_mem_server_axi4_slave_xactor_f_wr_resp$CLR = 1'b0 ;

  // submodule llc_mem_server_enqDst_0_dummy2_0
  assign llc_mem_server_enqDst_0_dummy2_0$D_IN = 1'd1 ;
  assign llc_mem_server_enqDst_0_dummy2_0$EN =
	     NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ;

  // submodule llc_mem_server_enqDst_0_dummy2_1
  assign llc_mem_server_enqDst_0_dummy2_1$D_IN = 1'd1 ;
  assign llc_mem_server_enqDst_0_dummy2_1$EN =
	     CAN_FIRE_RL_llc_mem_server_doEnq ;

  // submodule llc_mem_server_f_dword_in_line
  assign llc_mem_server_f_dword_in_line$D_IN = 3'h0 ;
  assign llc_mem_server_f_dword_in_line$ENQ = 1'b0 ;
  assign llc_mem_server_f_dword_in_line$DEQ = 1'b0 ;
  assign llc_mem_server_f_dword_in_line$CLR = 1'b0 ;

  // submodule llc_mem_server_propDstData_0_dummy2_0
  assign llc_mem_server_propDstData_0_dummy2_0$D_IN = 1'd1 ;
  assign llc_mem_server_propDstData_0_dummy2_0$EN =
	     CAN_FIRE_RL_llc_mem_server_srcPropose ;

  // submodule llc_mem_server_propDstData_0_dummy2_1
  assign llc_mem_server_propDstData_0_dummy2_1$D_IN = 1'b0 ;
  assign llc_mem_server_propDstData_0_dummy2_1$EN = 1'b0 ;

  // submodule llc_mem_server_propDstIdx_0_dummy2_0
  assign llc_mem_server_propDstIdx_0_dummy2_0$D_IN = 1'd1 ;
  assign llc_mem_server_propDstIdx_0_dummy2_0$EN =
	     CAN_FIRE_RL_llc_mem_server_srcPropose ;

  // submodule llc_mem_server_propDstIdx_0_dummy2_1
  assign llc_mem_server_propDstIdx_0_dummy2_1$D_IN = 1'd1 ;
  assign llc_mem_server_propDstIdx_0_dummy2_1$EN =
	     NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ;

  // submodule llc_mem_server_tlbQ
  assign llc_mem_server_tlbQ$D_IN =
	     NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ?
	       llc_mem_server_enqDst_0_lat_0$wget[64:0] :
	       llc_mem_server_enqDst_0_rl[64:0] ;
  assign llc_mem_server_tlbQ$ENQ = CAN_FIRE_RL_llc_mem_server_doEnq ;
  assign llc_mem_server_tlbQ$DEQ =
	     WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC ;
  assign llc_mem_server_tlbQ$CLR = 1'b0 ;

  // submodule mmioPlatform_fromHostQ_clearReq_dummy2_0
  assign mmioPlatform_fromHostQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign mmioPlatform_fromHostQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule mmioPlatform_fromHostQ_clearReq_dummy2_1
  assign mmioPlatform_fromHostQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign mmioPlatform_fromHostQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule mmioPlatform_fromHostQ_deqReq_dummy2_0
  assign mmioPlatform_fromHostQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmioPlatform_fromHostQ_deqReq_dummy2_0$EN =
	     mmioPlatform_fromHostQ_deqReq_lat_0$whas ;

  // submodule mmioPlatform_fromHostQ_deqReq_dummy2_1
  assign mmioPlatform_fromHostQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmioPlatform_fromHostQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmioPlatform_fromHostQ_deqReq_dummy2_2
  assign mmioPlatform_fromHostQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmioPlatform_fromHostQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmioPlatform_fromHostQ_enqReq_dummy2_0
  assign mmioPlatform_fromHostQ_enqReq_dummy2_0$D_IN = 1'b0 ;
  assign mmioPlatform_fromHostQ_enqReq_dummy2_0$EN = 1'b0 ;

  // submodule mmioPlatform_fromHostQ_enqReq_dummy2_1
  assign mmioPlatform_fromHostQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmioPlatform_fromHostQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmioPlatform_fromHostQ_enqReq_dummy2_2
  assign mmioPlatform_fromHostQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmioPlatform_fromHostQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmioPlatform_toHostQ_clearReq_dummy2_0
  assign mmioPlatform_toHostQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign mmioPlatform_toHostQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule mmioPlatform_toHostQ_clearReq_dummy2_1
  assign mmioPlatform_toHostQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign mmioPlatform_toHostQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule mmioPlatform_toHostQ_deqReq_dummy2_0
  assign mmioPlatform_toHostQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmioPlatform_toHostQ_deqReq_dummy2_0$EN = CAN_FIRE_RL_rl_tohost ;

  // submodule mmioPlatform_toHostQ_deqReq_dummy2_1
  assign mmioPlatform_toHostQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmioPlatform_toHostQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmioPlatform_toHostQ_deqReq_dummy2_2
  assign mmioPlatform_toHostQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmioPlatform_toHostQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmioPlatform_toHostQ_enqReq_dummy2_0
  assign mmioPlatform_toHostQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmioPlatform_toHostQ_enqReq_dummy2_0$EN =
	     mmioPlatform_toHostQ_enqReq_lat_0$whas ;

  // submodule mmioPlatform_toHostQ_enqReq_dummy2_1
  assign mmioPlatform_toHostQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmioPlatform_toHostQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmioPlatform_toHostQ_enqReq_dummy2_2
  assign mmioPlatform_toHostQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmioPlatform_toHostQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_axi4_adapter_f_reqs_from_core
  always@(MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__SEL_1 or
	  MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 or
	  WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req or
	  MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 or
	  WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req or
	  MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 or
	  WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req or
	  MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__SEL_1:
	  mmio_axi4_adapter_f_reqs_from_core$D_IN =
	      MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1;
      WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req:
	  mmio_axi4_adapter_f_reqs_from_core$D_IN =
	      MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2;
      WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req:
	  mmio_axi4_adapter_f_reqs_from_core$D_IN =
	      MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3;
      WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req:
	  mmio_axi4_adapter_f_reqs_from_core$D_IN =
	      MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4;
      default: mmio_axi4_adapter_f_reqs_from_core$D_IN =
		   142'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign mmio_axi4_adapter_f_reqs_from_core$ENQ =
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp &&
	     mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ||
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ||
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ||
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ;
  assign mmio_axi4_adapter_f_reqs_from_core$DEQ =
	     WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St ||
	     WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ||
	     WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ;
  assign mmio_axi4_adapter_f_reqs_from_core$CLR = 1'b0 ;

  // submodule mmio_axi4_adapter_f_rsps_to_core
  always@(MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1 or
	  MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 or
	  MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2 or
	  WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps or
	  MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1:
	  mmio_axi4_adapter_f_rsps_to_core$D_IN =
	      MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1;
      MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2:
	  mmio_axi4_adapter_f_rsps_to_core$D_IN = 65'h10000000000000000;
      WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps:
	  mmio_axi4_adapter_f_rsps_to_core$D_IN =
	      MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3;
      default: mmio_axi4_adapter_f_rsps_to_core$D_IN =
		   65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign mmio_axi4_adapter_f_rsps_to_core$ENQ =
	     (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ||
	      WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req) &&
	     !mmio_axi4_adapter_soc_map$m_is_IO_addr ||
	     WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	     mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] == 2'b0 ||
	     WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ;
  assign mmio_axi4_adapter_f_rsps_to_core$DEQ =
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ||
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ||
	     WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ;
  assign mmio_axi4_adapter_f_rsps_to_core$CLR = 1'b0 ;

  // submodule mmio_axi4_adapter_soc_map
  assign mmio_axi4_adapter_soc_map$m_is_IO_addr_addr =
	     mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78] ;
  assign mmio_axi4_adapter_soc_map$m_is_mem_addr_addr = 64'h0 ;
  assign mmio_axi4_adapter_soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;

  // submodule propDstData_0_dummy2_0
  assign propDstData_0_dummy2_0$D_IN = 1'd1 ;
  assign propDstData_0_dummy2_0$EN = CAN_FIRE_RL_srcPropose ;

  // submodule propDstData_0_dummy2_1
  assign propDstData_0_dummy2_1$D_IN = 1'b0 ;
  assign propDstData_0_dummy2_1$EN = 1'b0 ;

  // submodule propDstData_1_0_dummy2_0
  assign propDstData_1_0_dummy2_0$D_IN = 1'd1 ;
  assign propDstData_1_0_dummy2_0$EN = CAN_FIRE_RL_srcPropose_2 ;

  // submodule propDstData_1_0_dummy2_1
  assign propDstData_1_0_dummy2_1$D_IN = 1'b0 ;
  assign propDstData_1_0_dummy2_1$EN = 1'b0 ;

  // submodule propDstData_1_1_dummy2_0
  assign propDstData_1_1_dummy2_0$D_IN = 1'd1 ;
  assign propDstData_1_1_dummy2_0$EN = CAN_FIRE_RL_srcPropose_3 ;

  // submodule propDstData_1_1_dummy2_1
  assign propDstData_1_1_dummy2_1$D_IN = 1'b0 ;
  assign propDstData_1_1_dummy2_1$EN = 1'b0 ;

  // submodule propDstData_1_dummy2_0
  assign propDstData_1_dummy2_0$D_IN = 1'd1 ;
  assign propDstData_1_dummy2_0$EN = CAN_FIRE_RL_srcPropose_1 ;

  // submodule propDstData_1_dummy2_1
  assign propDstData_1_dummy2_1$D_IN = 1'b0 ;
  assign propDstData_1_dummy2_1$EN = 1'b0 ;

  // submodule propDstIdx_0_dummy2_0
  assign propDstIdx_0_dummy2_0$D_IN = 1'd1 ;
  assign propDstIdx_0_dummy2_0$EN = CAN_FIRE_RL_srcPropose ;

  // submodule propDstIdx_0_dummy2_1
  assign propDstIdx_0_dummy2_1$D_IN = 1'd1 ;
  assign propDstIdx_0_dummy2_1$EN = propDstIdx_0_lat_1$whas ;

  // submodule propDstIdx_1_0_dummy2_0
  assign propDstIdx_1_0_dummy2_0$D_IN = 1'd1 ;
  assign propDstIdx_1_0_dummy2_0$EN = CAN_FIRE_RL_srcPropose_2 ;

  // submodule propDstIdx_1_0_dummy2_1
  assign propDstIdx_1_0_dummy2_1$D_IN = 1'd1 ;
  assign propDstIdx_1_0_dummy2_1$EN = propDstIdx_1_0_lat_1$whas ;

  // submodule propDstIdx_1_1_dummy2_0
  assign propDstIdx_1_1_dummy2_0$D_IN = 1'd1 ;
  assign propDstIdx_1_1_dummy2_0$EN = CAN_FIRE_RL_srcPropose_3 ;

  // submodule propDstIdx_1_1_dummy2_1
  assign propDstIdx_1_1_dummy2_1$D_IN = 1'd1 ;
  assign propDstIdx_1_1_dummy2_1$EN = propDstIdx_1_1_lat_1$whas ;

  // submodule propDstIdx_1_dummy2_0
  assign propDstIdx_1_dummy2_0$D_IN = 1'd1 ;
  assign propDstIdx_1_dummy2_0$EN = CAN_FIRE_RL_srcPropose_1 ;

  // submodule propDstIdx_1_dummy2_1
  assign propDstIdx_1_dummy2_1$D_IN = 1'd1 ;
  assign propDstIdx_1_dummy2_1$EN = propDstIdx_1_lat_1$whas ;

  // remaining internal signals
  module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0],
							mmioPlatform_reqBE_BIT_4___h29906 &&
							mmioPlatform_reqBE_BIT_0___h29946,
							2'd0 }),
				    .amoExec_current_data(x__h37200),
				    .amoExec_in_data(mmioPlatform_reqData__h48606),
				    .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29906 &&
							   !mmioPlatform_reqBE_BIT_0___h29946),
				    .amoExec(x__h31930));
  module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0],
							mmioPlatform_reqBE_BIT_4___h29906 &&
							mmioPlatform_reqBE_BIT_0___h29946,
							2'd0 }),
				    .amoExec_current_data(mmioPlatform_mtime__h37052),
				    .amoExec_in_data(mmioPlatform_reqData__h48606),
				    .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29906 &&
							   !mmioPlatform_reqBE_BIT_0___h29946),
				    .amoExec(x__h34840));
  module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0],
							mmioPlatform_reqBE_BIT_4___h29906 &&
							mmioPlatform_reqBE_BIT_0___h29946,
							2'd0 }),
				    .amoExec_current_data(mmioPlatform_fromHostQ_data_0__h42585),
				    .amoExec_in_data(mmioPlatform_reqData__h48606),
				    .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29906 &&
							   !mmioPlatform_reqBE_BIT_0___h29946),
				    .amoExec(x__h40786));
  module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0],
							mmioPlatform_reqBE_BIT_4___h29906 &&
							mmioPlatform_reqBE_BIT_0___h29946,
							2'd0 }),
				    .amoExec_current_data(64'd0),
				    .amoExec_in_data(mmioPlatform_reqData__h48606),
				    .amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h29906 &&
							   !mmioPlatform_reqBE_BIT_0___h29946),
				    .amoExec(x__h42879));
  assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_36_BIT_ETC___d680 =
	     { 1'h0,
	       (mmioPlatform_reqFunc[5:4] == 2'd2) ?
		 { mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } :
		 { mmioPlatform_reqFunc[5:4] == 2'd1,
		   x1_avValue_data__h40257 } } ;
  assign IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 =
	     (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 &&
	      !mmioPlatform_mtip_0 ||
	      !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 &&
	      mmioPlatform_mtip_0) ?
	       core_0$RDY_mmioToPlatform_pRq_enq :
	       core_0$RDY_mmioToPlatform_pRs_enq ;
  assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452 =
	     (mmioPlatform_reqFunc[5:4] != 2'd1 &&
	      mmioPlatform_reqFunc[5:4] != 2'd2) ?
	       (mmioPlatform_reqBE[0] ?
		  core_0$RDY_mmioToPlatform_pRq_enq :
		  core_0$RDY_mmioToPlatform_pRs_enq) :
	       !mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ;
  assign IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 =
	     newData__h31819 <= mmioPlatform_mtime ;
  assign IF_NOT_propDstIdx_0_dummy2_1_read__062_063_OR__ETC___d1097 =
	     NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096 ?
	       propDstIdx_1_dummy2_1$Q_OUT &&
	       IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019 :
	       propDstIdx_0_dummy2_1$Q_OUT &&
	       IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 ;
  assign IF_NOT_propDstIdx_1_0_dummy2_1_read__326_327_O_ETC___d1371 =
	     NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370 ?
	       propDstIdx_1_1_dummy2_1$Q_OUT &&
	       IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193 :
	       propDstIdx_1_0_dummy2_1$Q_OUT &&
	       IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 ;
  assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 =
	     SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 ?
	       !srcRR_0 :
	       propDstIdx_0_dummy2_1$Q_OUT &&
	       IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 ;
  assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 =
	     SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 ?
	       !srcRR_1_0 :
	       propDstIdx_1_0_dummy2_1$Q_OUT &&
	       IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 ;
  assign IF_core_0_mmioToPlatform_cRq_first__78_BITS_14_ETC___d401 =
	     (core_0$mmioToPlatform_cRq_first[141:81] ==
	      mmioPlatform_toHostAddr) ?
	       67'h5AAAAAAAAAAAAAAAA :
	       ((core_0$mmioToPlatform_cRq_first[141:81] ==
		 mmioPlatform_fromHostAddr) ?
		  67'h6AAAAAAAAAAAAAAAA :
		  { 3'd7, core_0$mmioToPlatform_cRq_first[141:78] }) ;
  assign IF_enqDst_0_lat_0_whas__038_THEN_enqDst_0_lat__ETC___d1043 =
	     NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 ?
	       enqDst_0_lat_0$wget[73] :
	       enqDst_0_rl[73] ;
  assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1279 =
	     NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ?
	       enqDst_1_0_lat_0$wget[580] :
	       enqDst_1_0_rl[580] ;
  assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1289 =
	     NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ?
	       enqDst_1_0_lat_0$wget[579:516] :
	       enqDst_1_0_rl[579:516] ;
  assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294 =
	     NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ?
	       enqDst_1_0_lat_0$wget[515:514] :
	       enqDst_1_0_rl[515:514] ;
  assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1299 =
	     NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ?
	       enqDst_1_0_lat_0$wget[513] :
	       enqDst_1_0_rl[513] ;
  assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309 =
	     NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ?
	       enqDst_1_0_lat_0$wget[512:1] :
	       enqDst_1_0_rl[512:1] ;
  assign IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315 =
	     NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 ?
	       enqDst_1_0_lat_0$wget[0] :
	       enqDst_1_0_rl[0] ;
  assign IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1317 =
	     { CAN_FIRE_RL_doEnq_1 ||
	       IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1299,
	       CAN_FIRE_RL_doEnq_1 ?
		 512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 :
		 IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1309,
	       x__h75228 } ;
  assign IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1318 =
	     { CAN_FIRE_RL_doEnq_1 ?
		 64'hAAAAAAAAAAAAAAAA :
		 IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1289,
	       CAN_FIRE_RL_doEnq_1 ?
		 2'b10 :
		 IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1294,
	       IF_enqDst_1_0_lat_1_whas__271_THEN_enqDst_1_0__ETC___d1317 } ;
  assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591 =
	     { (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] ==
		3'd7) ?
		 new_dword__h90148 :
		 llc_mem_server_rg_cacheline_cache_data[511:448],
	       (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] ==
		3'd6) ?
		 new_dword__h90148 :
		 llc_mem_server_rg_cacheline_cache_data[447:384],
	       (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] ==
		3'd5) ?
		 new_dword__h90148 :
		 llc_mem_server_rg_cacheline_cache_data[383:320],
	       (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] ==
		3'd4) ?
		 new_dword__h90148 :
		 llc_mem_server_rg_cacheline_cache_data[319:256] } ;
  assign IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1596 =
	     { IF_llc_mem_server_axi4_slave_xactor_f_wr_addr__ETC___d1591,
	       (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] ==
		3'd3) ?
		 new_dword__h90148 :
		 llc_mem_server_rg_cacheline_cache_data[255:192],
	       (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32] ==
		3'd2) ?
		 new_dword__h90148 :
		 llc_mem_server_rg_cacheline_cache_data[191:128] } ;
  assign IF_llc_mem_server_enqDst_0_lat_0_whas__676_THE_ETC___d1681 =
	     NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 ?
	       llc_mem_server_enqDst_0_lat_0$wget[65] :
	       llc_mem_server_enqDst_0_rl[65] ;
  assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664 =
	     CAN_FIRE_RL_llc_mem_server_srcPropose ||
	     llc_mem_server_propDstIdx_0_rl ;
  assign IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829 =
	     (mmioPlatform_curReq[2:0] == 3'h0) ?
	       mmioPlatform_reqData :
	       64'd0 ;
  assign IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880 =
	     (mmioPlatform_curReq[2:0] == 3'h0) ?
	       mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:0] :
	       64'd0 ;
  assign IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621 =
	     ((mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 &&
	       !mmioPlatform_mtip_0) ?
		core_0$RDY_mmioToPlatform_pRq_enq :
		mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 ||
		!mmioPlatform_mtip_0 ||
		core_0$RDY_mmioToPlatform_pRq_enq) &&
	     (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 &&
	      !mmioPlatform_mtip_0 ||
	      !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 &&
	      mmioPlatform_mtip_0 ||
	      core_0$RDY_mmioToPlatform_pRs_enq) ;
  assign IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 =
	     mmioPlatform_reqBE[4] ?
	       { {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1[31]}},
		 mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1 } :
	       { {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2[31]}},
		 mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2 } ;
  assign IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 =
	     mmioPlatform_reqBE[4] ?
	       { {32{mmioPlatform_mtime_BITS_63_TO_32__q3[31]}},
		 mmioPlatform_mtime_BITS_63_TO_32__q3 } :
	       { {32{mmioPlatform_mtime_BITS_31_TO_0__q4[31]}},
		 mmioPlatform_mtime_BITS_31_TO_0__q4 } ;
  assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531 =
	     { mmioPlatform_reqBE[7] ?
		 mmioPlatform_reqData[63:56] :
		 mmioPlatform_mtimecmp_0[63:56],
	       mmioPlatform_reqBE[6] ?
		 mmioPlatform_reqData[55:48] :
		 mmioPlatform_mtimecmp_0[55:48],
	       mmioPlatform_reqBE[5] ?
		 mmioPlatform_reqData[47:40] :
		 mmioPlatform_mtimecmp_0[47:40],
	       mmioPlatform_reqBE[4] ?
		 mmioPlatform_reqData[39:32] :
		 mmioPlatform_mtimecmp_0[39:32] } ;
  assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540 =
	     { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d531,
	       mmioPlatform_reqBE[3] ?
		 mmioPlatform_reqData[31:24] :
		 mmioPlatform_mtimecmp_0[31:24],
	       mmioPlatform_reqBE[2] ?
		 mmioPlatform_reqData[23:16] :
		 mmioPlatform_mtimecmp_0[23:16] } ;
  assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 =
	     { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d540,
	       mmioPlatform_reqBE[1] ?
		 mmioPlatform_reqData[15:8] :
		 mmioPlatform_mtimecmp_0[15:8],
	       mmioPlatform_reqBE[0] ?
		 mmioPlatform_reqData[7:0] :
		 mmioPlatform_mtimecmp_0[7:0] } ;
  assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600 =
	     { mmioPlatform_reqBE[7] ?
		 mmioPlatform_reqData[63:56] :
		 mmioPlatform_mtime[63:56],
	       mmioPlatform_reqBE[6] ?
		 mmioPlatform_reqData[55:48] :
		 mmioPlatform_mtime[55:48],
	       mmioPlatform_reqBE[5] ?
		 mmioPlatform_reqData[47:40] :
		 mmioPlatform_mtime[47:40],
	       mmioPlatform_reqBE[4] ?
		 mmioPlatform_reqData[39:32] :
		 mmioPlatform_mtime[39:32] } ;
  assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605 =
	     { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d600,
	       mmioPlatform_reqBE[3] ?
		 mmioPlatform_reqData[31:24] :
		 mmioPlatform_mtime[31:24],
	       mmioPlatform_reqBE[2] ?
		 mmioPlatform_reqData[23:16] :
		 mmioPlatform_mtime[23:16] } ;
  assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 =
	     { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d605,
	       mmioPlatform_reqBE[1] ?
		 mmioPlatform_reqData[15:8] :
		 mmioPlatform_mtime[15:8],
	       mmioPlatform_reqBE[0] ?
		 mmioPlatform_reqData[7:0] :
		 mmioPlatform_mtime[7:0] } ;
  assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d704 =
	     { mmioPlatform_reqBE[7] ?
		 mmioPlatform_reqData[63:56] :
		 mmioPlatform_fromHostQ_data_0[63:56],
	       mmioPlatform_reqBE[6] ?
		 mmioPlatform_reqData[55:48] :
		 mmioPlatform_fromHostQ_data_0[55:48],
	       mmioPlatform_reqBE[5] ?
		 mmioPlatform_reqData[47:40] :
		 mmioPlatform_fromHostQ_data_0[47:40],
	       mmioPlatform_reqBE[4] ?
		 mmioPlatform_reqData[39:32] :
		 mmioPlatform_fromHostQ_data_0[39:32] } ;
  assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d709 =
	     { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d704,
	       mmioPlatform_reqBE[3] ?
		 mmioPlatform_reqData[31:24] :
		 mmioPlatform_fromHostQ_data_0[31:24],
	       mmioPlatform_reqBE[2] ?
		 mmioPlatform_reqData[23:16] :
		 mmioPlatform_fromHostQ_data_0[23:16] } ;
  assign IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d714 =
	     { IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d709,
	       mmioPlatform_reqBE[1] ?
		 mmioPlatform_reqData[15:8] :
		 mmioPlatform_fromHostQ_data_0[15:8],
	       mmioPlatform_reqBE[0] ?
		 mmioPlatform_reqData[7:0] :
		 mmioPlatform_fromHostQ_data_0[7:0] } ;
  assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d453 =
	     (mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ?
	       core_0$RDY_mmioToPlatform_pRs_enq :
	       IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d452 ;
  assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d574 =
	     (mmioPlatform_reqFunc[5:4] == 2'd1 ||
	      mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ?
	       mmioPlatform_mtimecmp_0 :
	       IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d573 ;
  assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_1_ETC___d638 =
	     (mmioPlatform_reqFunc[5:4] == 2'd1 ||
	      mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ?
	       mmioPlatform_mtime :
	       IF_mmioPlatform_reqBE_39_BIT_4_40_THEN_SEXT_mm_ETC___d637 ;
  assign IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_2_ETC___d722 =
	     (mmioPlatform_reqFunc[5:4] == 2'd2) ?
	       { mmioPlatform_fromHostQ_empty ?
		   x__h42868 == 64'd0 :
		   x__h40775 == 64'd0,
		 64'hAAAAAAAAAAAAAAAA } :
	       { mmioPlatform_reqFunc[5:4] == 2'd1,
		 x1_avValue_data__h44943 } ;
  assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200 =
	     mmioPlatform_toHostQ_enqReq_lat_0$whas ?
	       mmioPlatform_toHostQ_enqReq_lat_0$wget[64] :
	       mmioPlatform_toHostQ_enqReq_rl[64] ;
  assign IF_mmioPlatform_waitLowerMSIPCRs_88_THEN_core__ETC___d496 =
	     mmioPlatform_waitLowerMSIPCRs ?
	       core_0$RDY_mmioToPlatform_cRs_first &&
	       core_0$RDY_mmioToPlatform_cRs_deq :
	       (!mmioPlatform_waitUpperMSIPCRs ||
		core_0$RDY_mmioToPlatform_cRs_first) &&
	       (!mmioPlatform_waitUpperMSIPCRs ||
		core_0$RDY_mmioToPlatform_cRs_deq) ;
  assign IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d974 =
	     mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ?
	       mmioPlatform_fetchingWay <
	       (mmioPlatform_reqFunc[5:4] == 2'd0 &&
		mmioPlatform_reqFunc[0]) ||
	       core_0$RDY_mmioToPlatform_pRs_enq :
	       core_0$RDY_mmioToPlatform_pRs_enq ;
  assign IF_mmio_axi4_adapter_f_rsps_to_core_first__60__ETC___d995 =
	     mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ?
	       (mmioPlatform_fetchingWay ?
		  mmioPlatform_fetchedInsts_0 :
		  SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987) :
	       mmioPlatform_fetchedInsts_0 ;
  assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d103 =
	     mmio_axi4_adapter_soc_map$m_is_IO_addr ?
	       !mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read &&
	       !mmio_axi4_adapter_master_xactor_crg_wr_data_full$port2__read :
	       mmio_axi4_adapter_f_rsps_to_core$FULL_N ;
  assign IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116 =
	     propDstData_0_dummy2_1$Q_OUT ?
	       (CAN_FIRE_RL_srcPropose ?
		  propDstData_0_lat_0$wget[8:7] :
		  propDstData_0_rl[8:7]) :
	       2'd0 ;
  assign IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126 =
	     propDstData_0_dummy2_1$Q_OUT ?
	       (CAN_FIRE_RL_srcPropose ?
		  propDstData_0_lat_0$wget[6:5] :
		  propDstData_0_rl[6:5]) :
	       2'd0 ;
  assign IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203 =
	     CAN_FIRE_RL_srcPropose_2 ?
	       propDstData_1_0_lat_0$wget[579:516] :
	       propDstData_1_0_rl[579:516] ;
  assign IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208 =
	     CAN_FIRE_RL_srcPropose_2 ?
	       propDstData_1_0_lat_0$wget[515:514] :
	       propDstData_1_0_rl[515:514] ;
  assign IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229 =
	     CAN_FIRE_RL_srcPropose_2 ?
	       propDstData_1_0_lat_0$wget[0] :
	       propDstData_1_0_rl[0] ;
  assign IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241 =
	     CAN_FIRE_RL_srcPropose_3 ?
	       propDstData_1_1_lat_0$wget[579:516] :
	       propDstData_1_1_rl[579:516] ;
  assign IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246 =
	     CAN_FIRE_RL_srcPropose_3 ?
	       propDstData_1_1_lat_0$wget[515:514] :
	       propDstData_1_1_rl[515:514] ;
  assign IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267 =
	     CAN_FIRE_RL_srcPropose_3 ?
	       propDstData_1_1_lat_0$wget[0] :
	       propDstData_1_1_rl[0] ;
  assign IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120 =
	     propDstData_1_dummy2_1$Q_OUT ?
	       (CAN_FIRE_RL_srcPropose_1 ?
		  propDstData_1_lat_0$wget[8:7] :
		  propDstData_1_rl[8:7]) :
	       2'd0 ;
  assign IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130 =
	     propDstData_1_dummy2_1$Q_OUT ?
	       (CAN_FIRE_RL_srcPropose_1 ?
		  propDstData_1_lat_0$wget[6:5] :
		  propDstData_1_rl[6:5]) :
	       2'd0 ;
  assign IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 =
	     CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ;
  assign IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 =
	     CAN_FIRE_RL_srcPropose_2 || propDstIdx_1_0_rl ;
  assign IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193 =
	     CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ;
  assign IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019 =
	     CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ;
  assign NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 =
	     (!enqDst_0_dummy2_0$Q_OUT || !enqDst_0_dummy2_1$Q_OUT ||
	      !enqDst_0_rl[73]) &&
	     (SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 ||
	      IF_NOT_propDstIdx_0_dummy2_1_read__062_063_OR__ETC___d1097) ;
  assign NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 =
	     (!enqDst_1_0_dummy2_0$Q_OUT || !enqDst_1_0_dummy2_1$Q_OUT ||
	      !enqDst_1_0_rl[580]) &&
	     (SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 ||
	      IF_NOT_propDstIdx_1_0_dummy2_1_read__326_327_O_ETC___d1371) ;
  assign NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 =
	     llc_axi4_adapter_cfg_verbosity > 4'd1 ;
  assign NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 =
	     (!llc_mem_server_enqDst_0_dummy2_0$Q_OUT ||
	      !llc_mem_server_enqDst_0_dummy2_1$Q_OUT ||
	      !llc_mem_server_enqDst_0_rl[65]) &&
	     llc_mem_server_propDstIdx_0_dummy2_1$Q_OUT &&
	     IF_llc_mem_server_propDstIdx_0_lat_0_whas__661_ETC___d1664 ;
  assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d750 =
	     mmioPlatform_curReq[66:64] != 3'd0 &&
	     mmioPlatform_curReq[66:64] != 3'd1 &&
	     mmioPlatform_curReq[66:64] != 3'd2 &&
	     mmioPlatform_curReq[66:64] != 3'd3 &&
	     mmioPlatform_curReq[66:64] != 3'd4 &&
	     mmioPlatform_curReq[66:64] != 3'd5 &&
	     mmioPlatform_curReq[66:64] != 3'd6 &&
	     mmioPlatform_state == 2'd2 &&
	     (mmioPlatform_reqFunc[5:4] == 2'd1 ||
	      mmioPlatform_reqFunc[5:4] == 2'd2) ;
  assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d758 =
	     mmioPlatform_curReq[66:64] != 3'd0 &&
	     mmioPlatform_curReq[66:64] != 3'd1 &&
	     mmioPlatform_curReq[66:64] != 3'd2 &&
	     mmioPlatform_curReq[66:64] != 3'd3 &&
	     mmioPlatform_curReq[66:64] != 3'd4 &&
	     mmioPlatform_curReq[66:64] != 3'd5 &&
	     mmioPlatform_curReq[66:64] != 3'd6 &&
	     mmioPlatform_state == 2'd3 &&
	     (mmioPlatform_reqFunc[5:4] == 2'd1 ||
	      mmioPlatform_reqFunc[5:4] == 2'd2) ;
  assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d763 =
	     mmioPlatform_curReq[66:64] != 3'd0 &&
	     mmioPlatform_curReq[66:64] != 3'd1 &&
	     mmioPlatform_curReq[66:64] != 3'd2 &&
	     mmioPlatform_curReq[66:64] != 3'd3 &&
	     mmioPlatform_curReq[66:64] != 3'd4 &&
	     mmioPlatform_curReq[66:64] != 3'd5 &&
	     mmioPlatform_curReq[66:64] != 3'd6 &&
	     mmioPlatform_state == 2'd2 &&
	     mmioPlatform_reqFunc[5:4] != 2'd0 &&
	     mmioPlatform_reqFunc[5:4] != 2'd1 &&
	     mmioPlatform_reqFunc[5:4] != 2'd2 ;
  assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d773 =
	     mmioPlatform_curReq[66:64] != 3'd0 &&
	     mmioPlatform_curReq[66:64] != 3'd1 &&
	     mmioPlatform_curReq[66:64] != 3'd2 &&
	     mmioPlatform_curReq[66:64] != 3'd3 &&
	     mmioPlatform_curReq[66:64] != 3'd4 &&
	     mmioPlatform_curReq[66:64] != 3'd5 &&
	     mmioPlatform_curReq[66:64] != 3'd6 &&
	     mmioPlatform_state == 2'd3 &&
	     mmioPlatform_reqFunc[5:4] != 2'd0 &&
	     mmioPlatform_reqFunc[5:4] != 2'd1 &&
	     mmioPlatform_reqFunc[5:4] != 2'd2 ;
  assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d964 =
	     mmioPlatform_curReq[66:64] != 3'd0 &&
	     mmioPlatform_curReq[66:64] != 3'd1 &&
	     mmioPlatform_curReq[66:64] != 3'd2 &&
	     mmioPlatform_curReq[66:64] != 3'd3 &&
	     mmioPlatform_curReq[66:64] != 3'd4 &&
	     mmioPlatform_curReq[66:64] != 3'd5 &&
	     mmioPlatform_curReq[66:64] != 3'd6 &&
	     mmioPlatform_state == 2'd2 &&
	     mmioPlatform_reqFunc[5:4] == 2'd0 ;
  assign NOT_mmioPlatform_curReq_31_BITS_66_TO_64_32_EQ_ETC___d977 =
	     mmioPlatform_curReq[66:64] != 3'd0 &&
	     mmioPlatform_curReq[66:64] != 3'd1 &&
	     mmioPlatform_curReq[66:64] != 3'd2 &&
	     mmioPlatform_curReq[66:64] != 3'd3 &&
	     mmioPlatform_curReq[66:64] != 3'd4 &&
	     mmioPlatform_curReq[66:64] != 3'd5 &&
	     mmioPlatform_curReq[66:64] != 3'd6 &&
	     mmioPlatform_state == 2'd3 &&
	     mmioPlatform_reqFunc[5:4] == 2'd0 ;
  assign NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d318 =
	     !mmioPlatform_fromHostQ_clearReq_dummy2_1$Q_OUT ||
	     !mmioPlatform_fromHostQ_clearReq_rl ;
  assign NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d339 =
	     (!mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT ||
	      !mmioPlatform_fromHostQ_enqReq_rl[64]) &&
	     (mmioPlatform_fromHostQ_deqReq_dummy2_2$Q_OUT &&
	      (mmioPlatform_fromHostQ_deqReq_lat_0$whas ||
	       mmioPlatform_fromHostQ_deqReq_rl) ||
	      mmioPlatform_fromHostQ_empty) ;
  assign NOT_mmioPlatform_mtip_0_55_62_AND_mmioPlatform_ETC___d370 =
	     !mmioPlatform_mtip_0 &&
	     mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 ||
	     !core_0$mmioToPlatform_cRq_notEmpty ||
	     core_0$RDY_mmioToPlatform_cRq_first &&
	     core_0$RDY_mmioToPlatform_cRq_deq ;
  assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d486 =
	     mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] &&
	     (mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 ||
	      mmioPlatform_reqFunc[5:4] == 2'd2) ;
  assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d581 =
	     mmioPlatform_reqFunc[5:4] != 2'd0 &&
	     mmioPlatform_reqFunc[5:4] != 2'd1 &&
	     (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 &&
	      !mmioPlatform_mtip_0 ||
	      !IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 &&
	      mmioPlatform_mtip_0) ;
  assign NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ__ETC___d644 =
	     mmioPlatform_reqFunc[5:4] != 2'd0 &&
	     mmioPlatform_reqFunc[5:4] != 2'd1 &&
	     (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 &&
	      !mmioPlatform_mtip_0 ||
	      !mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 &&
	      mmioPlatform_mtip_0) ;
  assign NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d240 =
	     !mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT ||
	     !mmioPlatform_toHostQ_clearReq_rl ;
  assign NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d261 =
	     (!mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT ||
	      (mmioPlatform_toHostQ_enqReq_lat_0$whas ?
		 !mmioPlatform_toHostQ_enqReq_lat_0$wget[64] :
		 !mmioPlatform_toHostQ_enqReq_rl[64])) &&
	     (mmioPlatform_toHostQ_deqReq_dummy2_2$Q_OUT &&
	      (!mmioPlatform_toHostQ_empty ||
	       mmioPlatform_toHostQ_deqReq_rl) ||
	      mmioPlatform_toHostQ_empty) ;
  assign NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386 =
	     !propDstData_1_0_dummy2_1$Q_OUT ||
	     (CAN_FIRE_RL_srcPropose_2 ?
		!propDstData_1_0_lat_0$wget[513] :
		!propDstData_1_0_rl[513]) ;
  assign NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388 =
	     !propDstData_1_1_dummy2_1$Q_OUT ||
	     (CAN_FIRE_RL_srcPropose_3 ?
		!propDstData_1_1_lat_0$wget[513] :
		!propDstData_1_1_rl[513]) ;
  assign NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096 =
	     !propDstIdx_0_dummy2_1$Q_OUT ||
	     !CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ;
  assign NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370 =
	     !propDstIdx_1_0_dummy2_1$Q_OUT ||
	     !CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ;
  assign NOT_propDstIdx_1_1_dummy2_1_read__344_345_OR_I_ETC___d1477 =
	     !propDstIdx_1_1_dummy2_1$Q_OUT ||
	     !CAN_FIRE_RL_srcPropose_3 && !propDstIdx_1_1_rl ;
  assign NOT_propDstIdx_1_dummy2_1_read__075_076_OR_IF__ETC___d1175 =
	     !propDstIdx_1_dummy2_1$Q_OUT ||
	     !CAN_FIRE_RL_srcPropose_1 && !propDstIdx_1_rl ;
  assign SEL_ARR_IF_propDstData_0_dummy2_1_read__100_TH_ETC___d1164 =
	     { CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13,
	       CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14,
	       SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163 } ;
  assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__374__ETC___d1466 =
	     { CASE_x0299_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24,
	       !CASE_x0299_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25,
	       SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459,
	       x__h82715 } ;
  assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408 =
	     { CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16,
	       CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ;
  assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425 =
	     { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1408,
	       CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18,
	       CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ;
  assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442 =
	     { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1425,
	       CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20,
	       CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ;
  assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1459 =
	     { SEL_ARR_IF_propDstData_1_0_lat_0_whas__198_THE_ETC___d1442,
	       CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22,
	       CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ;
  assign SEL_ARR_propDstData_0_dummy2_1_read__100_AND_I_ETC___d1163 =
	     { CASE_x1414_0_propDstData_0_dummy2_1_read__100__ETC__q12,
	       x__h61728,
	       x__h61735 } ;
  assign b__h134523 =
	     CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ?
	       llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 :
	       llc_axi4_adapter_ctr_wr_rsps_pending_crg ;
  assign b__h2352 =
	     mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ?
	       mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 :
	       mmio_axi4_adapter_ctr_wr_rsps_pending_crg ;
  assign data__h31738 =
	     mmioPlatform_waitLowerMSIPCRs ?
	       { 63'd0, core_0$mmioToPlatform_cRs_first } :
	       { v__h31531, 32'd0 } ;
  assign failed_testnum__h163301 =
	     { 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ;
  assign line_addr__h102521 =
	     { llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[92:35],
	       6'b0 } ;
  assign line_addr__h102607 =
	     { llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[92:35],
	       6'b0 } ;
  assign llc_mem_server_axi4_slave_xactor_f_rd_addr_fir_ETC___d1608 =
	     line_addr__h102607 == llc_mem_server_rg_cacheline_cache_addr ;
  assign llc_mem_server_axi4_slave_xactor_f_wr_addr_fir_ETC___d1530 =
	     line_addr__h102521 == llc_mem_server_rg_cacheline_cache_addr ;
  assign mask__h90144 =
	     { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ?
		 8'hFF :
		 8'h0,
	       llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[7] ?
		 8'hFF :
		 8'h0,
	       llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[6] ?
		 8'hFF :
		 8'h0,
	       llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[5] ?
		 8'hFF :
		 8'h0,
	       llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[4] ?
		 8'hFF :
		 8'h0,
	       llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[3] ?
		 8'hFF :
		 8'h0,
	       llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[2] ?
		 8'hFF :
		 8'h0,
	       llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ?
		 8'hFF :
		 8'h0 } ;
  assign mem_req_rd_addr_araddr__h134816 =
	     { llc$to_mem_toM_first[68:11], x__h134851 } ;
  assign mem_req_wr_addr_awaddr__h148740 =
	     { llc$to_mem_toM_first[639:582], x__h148765 } ;
  assign mmioPlatform_cycle_47_ULT_99___d348 = mmioPlatform_cycle < 7'd99 ;
  assign mmioPlatform_fetchingWay_69_ULT_mmioPlatform_r_ETC___d979 =
	     mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ;
  assign mmioPlatform_fromHostQ_data_0__h42585 =
	     mmioPlatform_fromHostQ_data_0 ;
  assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__1_ETC___d331 =
	     mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT &&
	     mmioPlatform_fromHostQ_enqReq_rl[64] ||
	     (!mmioPlatform_fromHostQ_deqReq_dummy2_2$Q_OUT ||
	      !mmioPlatform_fromHostQ_deqReq_lat_0$whas &&
	      !mmioPlatform_fromHostQ_deqReq_rl) &&
	     mmioPlatform_fromHostQ_full ;
  assign mmioPlatform_mtime_BITS_31_TO_0__q4 = mmioPlatform_mtime[31:0] ;
  assign mmioPlatform_mtime_BITS_63_TO_32__q3 = mmioPlatform_mtime[63:32] ;
  assign mmioPlatform_mtime__h37052 = mmioPlatform_mtime ;
  assign mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 =
	     mmioPlatform_mtimecmp_0 <= newData__h34749 ;
  assign mmioPlatform_mtimecmp_0_56_ULE_mmioPlatform_mt_ETC___d357 =
	     mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ;
  assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2 =
	     mmioPlatform_mtimecmp_0[31:0] ;
  assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1 =
	     mmioPlatform_mtimecmp_0[63:32] ;
  assign mmioPlatform_reqBE_BIT_0___h29946 = mmioPlatform_reqBE[0] ;
  assign mmioPlatform_reqBE_BIT_4___h29906 = mmioPlatform_reqBE[4] ;
  assign mmioPlatform_reqData__h48606 = mmioPlatform_reqData ;
  assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d463 =
	     mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] ||
	     mmioPlatform_reqFunc[5:4] != 2'd1 &&
	     mmioPlatform_reqFunc[5:4] != 2'd2 &&
	     !mmioPlatform_reqBE[0] ;
  assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d567 =
	     mmioPlatform_reqFunc[5:4] == 2'd0 ||
	     mmioPlatform_reqFunc[5:4] == 2'd1 ||
	     (!IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 ||
	      mmioPlatform_mtip_0) &&
	     (IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4_37__ETC___d550 ||
	      !mmioPlatform_mtip_0) ;
  assign mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_38_ETC___d632 =
	     mmioPlatform_reqFunc[5:4] == 2'd0 ||
	     mmioPlatform_reqFunc[5:4] == 2'd1 ||
	     (!mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 ||
	      mmioPlatform_mtip_0) &&
	     (mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioPlat_ETC___d612 ||
	      !mmioPlatform_mtip_0) ;
  assign mmioPlatform_toHostQ_enqReq_dummy2_2_read__41__ETC___d253 =
	     mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__91__ETC___d200 ||
	     (!mmioPlatform_toHostQ_deqReq_dummy2_2$Q_OUT ||
	      !(!mmioPlatform_toHostQ_empty) &&
	      !mmioPlatform_toHostQ_deqReq_rl) &&
	     mmioPlatform_toHostQ_full ;
  assign mmio_axi4_adapter_f_reqs_from_core_i_notEmpty__ETC___d9 =
	     mmio_axi4_adapter_f_reqs_from_core$EMPTY_N &&
	     (mmio_axi4_adapter_soc_map$m_is_IO_addr ?
		!mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read :
		mmio_axi4_adapter_f_rsps_to_core$FULL_N) ;
  assign n__read_addr__h61596 =
	     propDstData_0_dummy2_1$Q_OUT ?
	       (CAN_FIRE_RL_srcPropose ?
		  propDstData_0_lat_0$wget[72:9] :
		  propDstData_0_rl[72:9]) :
	       64'd0 ;
  assign n__read_addr__h61681 =
	     propDstData_1_dummy2_1$Q_OUT ?
	       (CAN_FIRE_RL_srcPropose_1 ?
		  propDstData_1_lat_0$wget[72:9] :
		  propDstData_1_rl[72:9]) :
	       64'd0 ;
  assign n__read_addr__h80477 =
	     propDstData_1_0_dummy2_1$Q_OUT ?
	       IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1203 :
	       64'd0 ;
  assign n__read_addr__h80556 =
	     propDstData_1_1_dummy2_1$Q_OUT ?
	       IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1241 :
	       64'd0 ;
  assign n__read_child__h61601 =
	     propDstData_0_dummy2_1$Q_OUT &&
	     (CAN_FIRE_RL_srcPropose ?
		propDstData_0_lat_0$wget[0] :
		propDstData_0_rl[0]) ;
  assign n__read_child__h61686 =
	     propDstData_1_dummy2_1$Q_OUT &&
	     (CAN_FIRE_RL_srcPropose_1 ?
		propDstData_1_lat_0$wget[0] :
		propDstData_1_rl[0]) ;
  assign n__read_child__h80480 =
	     propDstData_1_0_dummy2_1$Q_OUT &&
	     IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1229 ;
  assign n__read_child__h80559 =
	     propDstData_1_1_dummy2_1$Q_OUT &&
	     IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1267 ;
  assign n__read_id__h61600 =
	     propDstData_0_dummy2_1$Q_OUT ?
	       (CAN_FIRE_RL_srcPropose ?
		  propDstData_0_lat_0$wget[3:1] :
		  propDstData_0_rl[3:1]) :
	       3'd0 ;
  assign n__read_id__h61685 =
	     propDstData_1_dummy2_1$Q_OUT ?
	       (CAN_FIRE_RL_srcPropose_1 ?
		  propDstData_1_lat_0$wget[3:1] :
		  propDstData_1_rl[3:1]) :
	       3'd0 ;
  assign n__read_snd_addr__h124048 =
	     llc_mem_server_propDstData_0_dummy2_1$Q_OUT ?
	       (CAN_FIRE_RL_llc_mem_server_srcPropose ?
		  core_0$tlbToMem_memReq_first[64:1] :
		  llc_mem_server_propDstData_0_rl[64:1]) :
	       64'd0 ;
  assign n__read_snd_id__h124049 =
	     llc_mem_server_propDstData_0_dummy2_1$Q_OUT &&
	     (CAN_FIRE_RL_llc_mem_server_srcPropose ?
		core_0$tlbToMem_memReq_first[0] :
		llc_mem_server_propDstData_0_rl[0]) ;
  assign newData__h31819 =
	     (mmioPlatform_reqFunc[5:4] != 2'd0 &&
	      mmioPlatform_reqFunc[5:4] != 2'd1 &&
	      mmioPlatform_reqFunc[5:4] != 2'd2) ?
	       x__h31930 :
	       IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d548 ;
  assign newData__h34749 =
	     (mmioPlatform_reqFunc[5:4] != 2'd0 &&
	      mmioPlatform_reqFunc[5:4] != 2'd1 &&
	      mmioPlatform_reqFunc[5:4] != 2'd2) ?
	       x__h34840 :
	       IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d610 ;
  assign new_cline__h135518 =
	     { llc_axi4_adapter_master_xactor_rg_rd_data[66:3],
	       llc_axi4_adapter_rg_cline[511:64] } ;
  assign new_dword__h90148 = x__h91310 | y__h91311 ;
  assign op_result__h48622 =
	     IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 +
	     IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ;
  assign op_result__h49152 = w1__h48019 ^ w2__h48021 ;
  assign op_result__h49157 = w1__h48019 & w2__h48021 ;
  assign op_result__h49162 = w1__h48019 | w2__h48021 ;
  assign op_result__h49167 =
	     (w1__h48019 < w2__h48021) ? w1__h48019 : w2__h48021 ;
  assign op_result__h49173 =
	     (w1__h48019 <= w2__h48021) ? w2__h48021 : w1__h48019 ;
  assign op_result__h49180 =
	     ((IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 ^
	       64'h8000000000000000) <
	      (IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ^
	       64'h8000000000000000)) ?
	       w1__h48019 :
	       w2__h48021 ;
  assign op_result__h49186 =
	     ((IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 ^
	       64'h8000000000000000) <=
	      (IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 ^
	       64'h8000000000000000)) ?
	       w2__h48021 :
	       w1__h48019 ;
  assign propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136 =
	     propDstData_0_dummy2_1$Q_OUT &&
	     (CAN_FIRE_RL_srcPropose ?
		propDstData_0_lat_0$wget[4] :
		propDstData_0_rl[4]) ;
  assign propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140 =
	     propDstData_1_dummy2_1$Q_OUT &&
	     (CAN_FIRE_RL_srcPropose_1 ?
		propDstData_1_lat_0$wget[4] :
		propDstData_1_rl[4]) ;
  assign result__h48065 =
	     { mmioPlatform_reqData[63:8],
	       IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0] } ;
  assign result__h48189 = { 56'd0, mmioPlatform_reqData[7:0] } ;
  assign result__h48217 = { 56'd0, mmioPlatform_reqData[15:8] } ;
  assign result__h48245 = { 56'd0, mmioPlatform_reqData[23:16] } ;
  assign result__h48273 = { 56'd0, mmioPlatform_reqData[31:24] } ;
  assign result__h48301 = { 56'd0, mmioPlatform_reqData[39:32] } ;
  assign result__h48329 = { 56'd0, mmioPlatform_reqData[47:40] } ;
  assign result__h48357 = { 56'd0, mmioPlatform_reqData[55:48] } ;
  assign result__h48385 = { 56'd0, mmioPlatform_reqData[63:56] } ;
  assign result__h48430 = { 48'd0, mmioPlatform_reqData[15:0] } ;
  assign result__h48458 = { 48'd0, mmioPlatform_reqData[31:16] } ;
  assign result__h48486 = { 48'd0, mmioPlatform_reqData[47:32] } ;
  assign result__h48514 = { 48'd0, mmioPlatform_reqData[63:48] } ;
  assign result__h48555 = { 32'd0, mmioPlatform_reqData[31:0] } ;
  assign result__h48583 = { 32'd0, mmioPlatform_reqData[63:32] } ;
  assign result__h48709 =
	     { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ;
  assign result__h48736 =
	     { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ;
  assign result__h48763 =
	     { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ;
  assign result__h48790 =
	     { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ;
  assign result__h48817 =
	     { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ;
  assign result__h48844 =
	     { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ;
  assign result__h48871 =
	     { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ;
  assign result__h48898 =
	     { 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ;
  assign result__h48942 =
	     { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ;
  assign result__h48969 =
	     { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ;
  assign result__h48996 =
	     { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ;
  assign result__h49023 =
	     { 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ;
  assign result__h49063 =
	     { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ;
  assign result__h49090 =
	     { 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ;
  assign result__h49207 =
	     { mmioPlatform_reqData[63:16],
	       IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0],
	       mmioPlatform_reqData[7:0] } ;
  assign result__h49273 =
	     { mmioPlatform_reqData[63:24],
	       IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0],
	       mmioPlatform_reqData[15:0] } ;
  assign result__h49339 =
	     { mmioPlatform_reqData[63:32],
	       IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0],
	       mmioPlatform_reqData[23:0] } ;
  assign result__h49405 =
	     { mmioPlatform_reqData[63:40],
	       IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0],
	       mmioPlatform_reqData[31:0] } ;
  assign result__h49471 =
	     { mmioPlatform_reqData[63:48],
	       IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0],
	       mmioPlatform_reqData[39:0] } ;
  assign result__h49537 =
	     { mmioPlatform_reqData[63:56],
	       IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0],
	       mmioPlatform_reqData[47:0] } ;
  assign result__h49603 =
	     { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[7:0],
	       mmioPlatform_reqData[55:0] } ;
  assign result__h49665 =
	     { mmioPlatform_reqData[63:16],
	       IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0] } ;
  assign result__h49710 =
	     { mmioPlatform_reqData[63:32],
	       IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0],
	       mmioPlatform_reqData[15:0] } ;
  assign result__h49776 =
	     { mmioPlatform_reqData[63:48],
	       IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0],
	       mmioPlatform_reqData[31:0] } ;
  assign result__h49842 =
	     { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[15:0],
	       mmioPlatform_reqData[47:0] } ;
  assign result__h49900 =
	     { mmioPlatform_reqData[63:32],
	       IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[31:0] } ;
  assign result__h49945 =
	     { IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919[31:0],
	       mmioPlatform_reqData[31:0] } ;
  assign v__h31531 = mmioPlatform_waitUpperMSIPCRs ? v__h31568 : 32'd0 ;
  assign v__h31568 = { 31'd0, core_0$mmioToPlatform_cRs_first } ;
  assign w18014_BITS_31_TO_0__q7 = w1__h48014[31:0] ;
  assign w1___1__h48124 = { 32'd0, w1__h48014[31:0] } ;
  assign w28015_BITS_31_TO_0__q8 = w2__h48015[31:0] ;
  assign w2___1__h48125 = { 32'd0, w2__h48015[31:0] } ;
  assign x1_avValue_data__h40257 =
	     mmioPlatform_toHostQ_empty ?
	       64'd0 :
	       mmioPlatform_toHostQ_data_0 ;
  assign x1_avValue_data__h44943 =
	     mmioPlatform_fromHostQ_empty ?
	       64'd0 :
	       mmioPlatform_fromHostQ_data_0 ;
  assign x__h134851 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ;
  assign x__h148765 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ;
  assign x__h37200 = mmioPlatform_mtimecmp_0 ;
  assign x__h40775 =
	     (mmioPlatform_reqFunc[5:4] != 2'd0 &&
	      mmioPlatform_reqFunc[5:4] != 2'd1 &&
	      mmioPlatform_reqFunc[5:4] != 2'd2) ?
	       x__h40786 :
	       IF_mmioPlatform_reqBE_39_BIT_7_15_THEN_mmioPla_ETC___d714 ;
  assign x__h42868 =
	     (mmioPlatform_reqFunc[5:4] != 2'd0 &&
	      mmioPlatform_reqFunc[5:4] != 2'd1 &&
	      mmioPlatform_reqFunc[5:4] != 2'd2) ?
	       x__h42879 :
	       { mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0,
		 mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0,
		 mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0,
		 mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : 8'd0,
		 mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : 8'd0,
		 mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0,
		 mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0,
		 mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ;
  assign x__h50122 = { mmioPlatform_curReq[63:3], 3'b0 } ;
  assign x__h61414 =
	     SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 ?
	       srcRR_0 :
	       NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096 ;
  assign x__h75228 =
	     !CAN_FIRE_RL_doEnq_1 &&
	     IF_enqDst_1_0_lat_0_whas__274_THEN_enqDst_1_0__ETC___d1315 ;
  assign x__h7713 =
	     (mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:68] == 4'd0 ||
	      mmio_axi4_adapter_f_reqs_from_core$D_OUT[67:64] == 4'd0) ?
	       3'b010 :
	       3'b011 ;
  assign x__h80299 =
	     SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 ?
	       srcRR_1_0 :
	       NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370 ;
  assign x__h91310 = old_dword__h90147 & y__h91312 ;
  assign x_data__h30321 = { 31'd0, mmioPlatform_reqData[0] } ;
  assign y__h91311 =
	     llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[72:9] &
	     mask__h90144 ;
  assign y__h91312 =
	     { llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[8] ?
		 8'd0 :
		 8'd255,
	       llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[7] ?
		 8'd0 :
		 8'd255,
	       llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[6] ?
		 8'd0 :
		 8'd255,
	       llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[5] ?
		 8'd0 :
		 8'd255,
	       llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[4] ?
		 8'd0 :
		 8'd255,
	       llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[3] ?
		 8'd0 :
		 8'd255,
	       llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[2] ?
		 8'd0 :
		 8'd255,
	       llc_mem_server_axi4_slave_xactor_f_wr_data$D_OUT[1] ?
		 8'd0 :
		 8'd255 } ;
  always@(llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT or
	  llc_mem_server_rg_cacheline_cache_data)
  begin
    case (llc_mem_server_axi4_slave_xactor_f_rd_addr$D_OUT[34:32])
      3'd0: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[63:0];
      3'd1: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[127:64];
      3'd2: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[191:128];
      3'd3: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[255:192];
      3'd4: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[319:256];
      3'd5: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[383:320];
      3'd6: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[447:384];
      3'd7: dword__h94457 = llc_mem_server_rg_cacheline_cache_data[511:448];
    endcase
  end
  always@(llc$dma_respLd_first)
  begin
    case (llc$dma_respLd_first[2:0])
      3'd0: ld_data__h132744 = llc$dma_respLd_first[68:5];
      3'd1: ld_data__h132744 = llc$dma_respLd_first[132:69];
      3'd2: ld_data__h132744 = llc$dma_respLd_first[196:133];
      3'd3: ld_data__h132744 = llc$dma_respLd_first[260:197];
      3'd4: ld_data__h132744 = llc$dma_respLd_first[324:261];
      3'd5: ld_data__h132744 = llc$dma_respLd_first[388:325];
      3'd6: ld_data__h132744 = llc$dma_respLd_first[452:389];
      3'd7: ld_data__h132744 = llc$dma_respLd_first[516:453];
    endcase
  end
  always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first)
  begin
    case (llc_axi4_adapter_rg_wr_req_beat)
      3'd0: data64__h148655 = llc$to_mem_toM_first[63:0];
      3'd1: data64__h148655 = llc$to_mem_toM_first[127:64];
      3'd2: data64__h148655 = llc$to_mem_toM_first[191:128];
      3'd3: data64__h148655 = llc$to_mem_toM_first[255:192];
      3'd4: data64__h148655 = llc$to_mem_toM_first[319:256];
      3'd5: data64__h148655 = llc$to_mem_toM_first[383:320];
      3'd6: data64__h148655 = llc$to_mem_toM_first[447:384];
      3'd7: data64__h148655 = llc$to_mem_toM_first[511:448];
    endcase
  end
  always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first)
  begin
    case (llc_axi4_adapter_rg_wr_req_beat)
      3'd0: strb8__h148656 = llc$to_mem_toM_first[519:512];
      3'd1: strb8__h148656 = llc$to_mem_toM_first[527:520];
      3'd2: strb8__h148656 = llc$to_mem_toM_first[535:528];
      3'd3: strb8__h148656 = llc$to_mem_toM_first[543:536];
      3'd4: strb8__h148656 = llc$to_mem_toM_first[551:544];
      3'd5: strb8__h148656 = llc$to_mem_toM_first[559:552];
      3'd6: strb8__h148656 = llc$to_mem_toM_first[567:560];
      3'd7: strb8__h148656 = llc$to_mem_toM_first[575:568];
    endcase
  end
  always@(llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT or
	  llc_mem_server_rg_cacheline_cache_data)
  begin
    case (llc_mem_server_axi4_slave_xactor_f_wr_addr$D_OUT[34:32])
      3'd0: old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[63:0];
      3'd1:
	  old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[127:64];
      3'd2:
	  old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[191:128];
      3'd3:
	  old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[255:192];
      3'd4:
	  old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[319:256];
      3'd5:
	  old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[383:320];
      3'd6:
	  old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[447:384];
      3'd7:
	  old_dword__h90147 = llc_mem_server_rg_cacheline_cache_data[511:448];
    endcase
  end
  always@(mmioPlatform_curReq or
	  result__h48189 or
	  result__h48217 or
	  result__h48245 or
	  result__h48273 or
	  result__h48301 or
	  result__h48329 or result__h48357 or result__h48385)
  begin
    case (mmioPlatform_curReq[2:0])
      3'h0:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 =
	      result__h48189;
      3'h1:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 =
	      result__h48217;
      3'h2:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 =
	      result__h48245;
      3'h3:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 =
	      result__h48273;
      3'h4:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 =
	      result__h48301;
      3'h5:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 =
	      result__h48329;
      3'h6:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 =
	      result__h48357;
      3'h7:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 =
	      result__h48385;
    endcase
  end
  always@(mmioPlatform_curReq or
	  result__h48430 or
	  result__h48458 or result__h48486 or result__h48514)
  begin
    case (mmioPlatform_curReq[2:0])
      3'h0:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 =
	      result__h48430;
      3'h2:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 =
	      result__h48458;
      3'h4:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 =
	      result__h48486;
      3'h6:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 =
	      result__h48514;
      default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 =
		   64'd0;
    endcase
  end
  always@(mmioPlatform_curReq or result__h48555 or result__h48583)
  begin
    case (mmioPlatform_curReq[2:0])
      3'h0:
	  CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 =
	      result__h48555;
      3'h4:
	  CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 =
	      result__h48583;
      default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = 64'd0;
    endcase
  end
  always@(mmioPlatform_reqSz or
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 or
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 or
	  CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 or
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829)
  begin
    case (mmioPlatform_reqSz)
      2'b0:
	  w2__h48015 =
	      IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809;
      2'b01:
	  w2__h48015 =
	      IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822;
      2'b10:
	  w2__h48015 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5;
      2'b11:
	  w2__h48015 =
	      IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829;
    endcase
  end
  always@(mmioPlatform_reqSz or
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 or
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 or
	  w2___1__h48125 or
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829)
  begin
    case (mmioPlatform_reqSz)
      2'b0:
	  w2__h48021 =
	      IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809;
      2'b01:
	  w2__h48021 =
	      IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822;
      2'b10: w2__h48021 = w2___1__h48125;
      2'b11:
	  w2__h48021 =
	      IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829;
    endcase
  end
  always@(mmioPlatform_curReq or
	  result__h48942 or
	  result__h48969 or result__h48996 or result__h49023)
  begin
    case (mmioPlatform_curReq[2:0])
      3'h0:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 =
	      result__h48942;
      3'h2:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 =
	      result__h48969;
      3'h4:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 =
	      result__h48996;
      3'h6:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 =
	      result__h49023;
      default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 =
		   64'd0;
    endcase
  end
  always@(mmioPlatform_curReq or
	  result__h48709 or
	  result__h48736 or
	  result__h48763 or
	  result__h48790 or
	  result__h48817 or
	  result__h48844 or result__h48871 or result__h48898)
  begin
    case (mmioPlatform_curReq[2:0])
      3'h0:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 =
	      result__h48709;
      3'h1:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 =
	      result__h48736;
      3'h2:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 =
	      result__h48763;
      3'h3:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 =
	      result__h48790;
      3'h4:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 =
	      result__h48817;
      3'h5:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 =
	      result__h48844;
      3'h6:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 =
	      result__h48871;
      3'h7:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 =
	      result__h48898;
    endcase
  end
  always@(mmioPlatform_curReq or result__h49063 or result__h49090)
  begin
    case (mmioPlatform_curReq[2:0])
      3'h0:
	  CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 =
	      result__h49063;
      3'h4:
	  CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 =
	      result__h49090;
      default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = 64'd0;
    endcase
  end
  always@(mmioPlatform_reqSz or
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 or
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 or
	  CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 or
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880)
  begin
    case (mmioPlatform_reqSz)
      2'b0:
	  w1__h48014 =
	      IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861;
      2'b01:
	  w1__h48014 =
	      IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873;
      2'b10:
	  w1__h48014 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6;
      2'b11:
	  w1__h48014 =
	      IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880;
    endcase
  end
  always@(mmioPlatform_reqSz or
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 or
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 or
	  w1___1__h48124 or
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880)
  begin
    case (mmioPlatform_reqSz)
      2'b0:
	  w1__h48019 =
	      IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861;
      2'b01:
	  w1__h48019 =
	      IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873;
      2'b10: w1__h48019 = w1___1__h48124;
      2'b11:
	  w1__h48019 =
	      IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880;
    endcase
  end
  always@(mmioPlatform_reqSz or
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861 or
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873 or
	  w18014_BITS_31_TO_0__q7 or
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880)
  begin
    case (mmioPlatform_reqSz)
      2'b0:
	  IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 =
	      IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d861;
      2'b01:
	  IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 =
	      IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d873;
      2'b10:
	  IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 =
	      { {32{w18014_BITS_31_TO_0__q7[31]}}, w18014_BITS_31_TO_0__q7 };
      2'b11:
	  IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d887 =
	      IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d880;
    endcase
  end
  always@(mmioPlatform_reqSz or
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809 or
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822 or
	  w28015_BITS_31_TO_0__q8 or
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829)
  begin
    case (mmioPlatform_reqSz)
      2'b0:
	  IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 =
	      IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d809;
      2'b01:
	  IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 =
	      IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d822;
      2'b10:
	  IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 =
	      { {32{w28015_BITS_31_TO_0__q8[31]}}, w28015_BITS_31_TO_0__q8 };
      2'b11:
	  IF_mmioPlatform_reqSz_79_EQ_0b10_86_THEN_SEXT__ETC___d889 =
	      IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829;
    endcase
  end
  always@(mmioPlatform_reqAmofunc or
	  op_result__h49186 or
	  w2__h48021 or
	  op_result__h48622 or
	  op_result__h49152 or
	  op_result__h49157 or
	  op_result__h49162 or
	  op_result__h49180 or op_result__h49167 or op_result__h49173)
  begin
    case (mmioPlatform_reqAmofunc)
      4'd0:
	  IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 =
	      w2__h48021;
      4'd1:
	  IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 =
	      op_result__h48622;
      4'd2:
	  IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 =
	      op_result__h49152;
      4'd3:
	  IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 =
	      op_result__h49157;
      4'd4:
	  IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 =
	      op_result__h49162;
      4'd5:
	  IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 =
	      op_result__h49180;
      4'd7:
	  IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 =
	      op_result__h49167;
      4'd8:
	  IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 =
	      op_result__h49173;
      default: IF_mmioPlatform_reqAmofunc_84_EQ_0_85_THEN_IF__ETC___d919 =
		   op_result__h49186;
    endcase
  end
  always@(mmioPlatform_curReq or
	  result__h49665 or
	  result__h49710 or result__h49776 or result__h49842)
  begin
    case (mmioPlatform_curReq[2:0])
      3'h0:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 =
	      result__h49665;
      3'h2:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 =
	      result__h49710;
      3'h4:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 =
	      result__h49776;
      3'h6:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 =
	      result__h49842;
      default: IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 =
		   64'd0;
    endcase
  end
  always@(mmioPlatform_curReq or
	  result__h48065 or
	  result__h49207 or
	  result__h49273 or
	  result__h49339 or
	  result__h49405 or
	  result__h49471 or result__h49537 or result__h49603)
  begin
    case (mmioPlatform_curReq[2:0])
      3'h0:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 =
	      result__h48065;
      3'h1:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 =
	      result__h49207;
      3'h2:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 =
	      result__h49273;
      3'h3:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 =
	      result__h49339;
      3'h4:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 =
	      result__h49405;
      3'h5:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 =
	      result__h49471;
      3'h6:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 =
	      result__h49537;
      3'h7:
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 =
	      result__h49603;
    endcase
  end
  always@(mmioPlatform_curReq or result__h49900 or result__h49945)
  begin
    case (mmioPlatform_curReq[2:0])
      3'h0:
	  CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 =
	      result__h49900;
      3'h4:
	  CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 =
	      result__h49945;
      default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = 64'd0;
    endcase
  end
  always@(mmioPlatform_reqSz or
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943 or
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952 or
	  CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 or
	  IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829)
  begin
    case (mmioPlatform_reqSz)
      2'b0:
	  x__h48010 =
	      IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d943;
      2'b01:
	  x__h48010 =
	      IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d952;
      2'b10:
	  x__h48010 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9;
      2'b11:
	  x__h48010 =
	      IF_mmioPlatform_curReq_31_BITS_2_TO_0_81_EQ_0x_ETC___d829;
    endcase
  end
  always@(mmioPlatform_reqFunc)
  begin
    case (mmioPlatform_reqFunc[5:4])
      2'd0, 2'd1, 2'd2:
	  IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477 =
	      mmioPlatform_reqFunc;
      2'd3:
	  IF_mmioPlatform_reqFunc_36_BITS_5_TO_4_37_EQ_0_ETC___d477 =
	      { 2'd3, mmioPlatform_reqFunc[3:0] };
    endcase
  end
  always@(mmioPlatform_instSel or mmio_axi4_adapter_f_rsps_to_core$D_OUT)
  begin
    case (mmioPlatform_instSel)
      1'd0:
	  SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987 =
	      mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0];
      1'd1:
	  SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d987 =
	      mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32];
    endcase
  end
  always@(mmioPlatform_reqFunc or
	  IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555 or
	  core_0$RDY_mmioToPlatform_pRs_enq)
  begin
    case (mmioPlatform_reqFunc[5:4])
      2'd0, 2'd1:
	  CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 =
	      core_0$RDY_mmioToPlatform_pRs_enq;
      default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 =
		   IF_IF_NOT_mmioPlatform_reqFunc_36_BITS_5_TO_4__ETC___d555;
    endcase
  end
  always@(mmioPlatform_reqFunc or
	  IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621 or
	  core_0$RDY_mmioToPlatform_pRs_enq)
  begin
    case (mmioPlatform_reqFunc[5:4])
      2'd0, 2'd1:
	  CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11 =
	      core_0$RDY_mmioToPlatform_pRs_enq;
      default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11 =
		   IF_mmioPlatform_mtimecmp_0_56_ULE_IF_NOT_mmioP_ETC___d621;
    endcase
  end
  always@(srcRR_0 or
	  propDstIdx_0_dummy2_1$Q_OUT or
	  IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012 or
	  propDstIdx_1_dummy2_1$Q_OUT or
	  IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019)
  begin
    case (srcRR_0)
      1'd0:
	  SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 =
	      propDstIdx_0_dummy2_1$Q_OUT &&
	      IF_propDstIdx_0_lat_0_whas__009_THEN_propDstId_ETC___d1012;
      1'd1:
	  SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_IF_ETC___d1093 =
	      propDstIdx_1_dummy2_1$Q_OUT &&
	      IF_propDstIdx_1_lat_0_whas__016_THEN_propDstId_ETC___d1019;
    endcase
  end
  always@(srcRR_1_0 or
	  propDstIdx_1_0_dummy2_1$Q_OUT or
	  IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186 or
	  propDstIdx_1_1_dummy2_1$Q_OUT or
	  IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193)
  begin
    case (srcRR_1_0)
      1'd0:
	  SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 =
	      propDstIdx_1_0_dummy2_1$Q_OUT &&
	      IF_propDstIdx_1_0_lat_0_whas__183_THEN_propDst_ETC___d1186;
      1'd1:
	  SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_AND__ETC___d1367 =
	      propDstIdx_1_1_dummy2_1$Q_OUT &&
	      IF_propDstIdx_1_1_lat_0_whas__190_THEN_propDst_ETC___d1193;
    endcase
  end
  always@(x__h61414 or n__read_id__h61600 or n__read_id__h61685)
  begin
    case (x__h61414)
      1'd0: x__h61728 = n__read_id__h61600;
      1'd1: x__h61728 = n__read_id__h61685;
    endcase
  end
  always@(x__h61414 or n__read_child__h61601 or n__read_child__h61686)
  begin
    case (x__h61414)
      1'd0: x__h61735 = n__read_child__h61601;
      1'd1: x__h61735 = n__read_child__h61686;
    endcase
  end
  always@(x__h61414 or
	  propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136 or
	  propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140)
  begin
    case (x__h61414)
      1'd0:
	  CASE_x1414_0_propDstData_0_dummy2_1_read__100__ETC__q12 =
	      propDstData_0_dummy2_1_read__100_AND_IF_propDs_ETC___d1136;
      1'd1:
	  CASE_x1414_0_propDstData_0_dummy2_1_read__100__ETC__q12 =
	      propDstData_1_dummy2_1_read__105_AND_IF_propDs_ETC___d1140;
    endcase
  end
  always@(x__h61414 or
	  IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116 or
	  IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120)
  begin
    case (x__h61414)
      1'd0:
	  CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13 =
	      IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1116;
      1'd1:
	  CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q13 =
	      IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1120;
    endcase
  end
  always@(x__h61414 or
	  IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126 or
	  IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130)
  begin
    case (x__h61414)
      1'd0:
	  CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14 =
	      IF_propDstData_0_dummy2_1_read__100_THEN_IF_pr_ETC___d1126;
      1'd1:
	  CASE_x1414_0_IF_propDstData_0_dummy2_1_read__1_ETC__q14 =
	      IF_propDstData_1_dummy2_1_read__105_THEN_IF_pr_ETC___d1130;
    endcase
  end
  always@(x__h61414 or n__read_addr__h61596 or n__read_addr__h61681)
  begin
    case (x__h61414)
      1'd0:
	  CASE_x1414_0_n__read_addr1596_1_n__read_addr16_ETC__q15 =
	      n__read_addr__h61596;
      1'd1:
	  CASE_x1414_0_n__read_addr1596_1_n__read_addr16_ETC__q15 =
	      n__read_addr__h61681;
    endcase
  end
  always@(x__h80299 or n__read_child__h80480 or n__read_child__h80559)
  begin
    case (x__h80299)
      1'd0: x__h82715 = n__read_child__h80480;
      1'd1: x__h82715 = n__read_child__h80559;
    endcase
  end
  always@(x__h80299 or
	  CAN_FIRE_RL_srcPropose_2 or
	  propDstData_1_0_lat_0$wget or
	  propDstData_1_0_rl or
	  CAN_FIRE_RL_srcPropose_3 or
	  propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
  begin
    case (x__h80299)
      1'd0:
	  CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 =
	      CAN_FIRE_RL_srcPropose_2 ?
		propDstData_1_0_lat_0$wget[512:449] :
		propDstData_1_0_rl[512:449];
      1'd1:
	  CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 =
	      CAN_FIRE_RL_srcPropose_3 ?
		propDstData_1_1_lat_0$wget[512:449] :
		propDstData_1_1_rl[512:449];
    endcase
  end
  always@(x__h80299 or
	  CAN_FIRE_RL_srcPropose_2 or
	  propDstData_1_0_lat_0$wget or
	  propDstData_1_0_rl or
	  CAN_FIRE_RL_srcPropose_3 or
	  propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
  begin
    case (x__h80299)
      1'd0:
	  CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 =
	      CAN_FIRE_RL_srcPropose_2 ?
		propDstData_1_0_lat_0$wget[448:385] :
		propDstData_1_0_rl[448:385];
      1'd1:
	  CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 =
	      CAN_FIRE_RL_srcPropose_3 ?
		propDstData_1_1_lat_0$wget[448:385] :
		propDstData_1_1_rl[448:385];
    endcase
  end
  always@(x__h80299 or
	  CAN_FIRE_RL_srcPropose_2 or
	  propDstData_1_0_lat_0$wget or
	  propDstData_1_0_rl or
	  CAN_FIRE_RL_srcPropose_3 or
	  propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
  begin
    case (x__h80299)
      1'd0:
	  CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 =
	      CAN_FIRE_RL_srcPropose_2 ?
		propDstData_1_0_lat_0$wget[384:321] :
		propDstData_1_0_rl[384:321];
      1'd1:
	  CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 =
	      CAN_FIRE_RL_srcPropose_3 ?
		propDstData_1_1_lat_0$wget[384:321] :
		propDstData_1_1_rl[384:321];
    endcase
  end
  always@(x__h80299 or
	  CAN_FIRE_RL_srcPropose_2 or
	  propDstData_1_0_lat_0$wget or
	  propDstData_1_0_rl or
	  CAN_FIRE_RL_srcPropose_3 or
	  propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
  begin
    case (x__h80299)
      1'd0:
	  CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 =
	      CAN_FIRE_RL_srcPropose_2 ?
		propDstData_1_0_lat_0$wget[320:257] :
		propDstData_1_0_rl[320:257];
      1'd1:
	  CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 =
	      CAN_FIRE_RL_srcPropose_3 ?
		propDstData_1_1_lat_0$wget[320:257] :
		propDstData_1_1_rl[320:257];
    endcase
  end
  always@(x__h80299 or
	  CAN_FIRE_RL_srcPropose_2 or
	  propDstData_1_0_lat_0$wget or
	  propDstData_1_0_rl or
	  CAN_FIRE_RL_srcPropose_3 or
	  propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
  begin
    case (x__h80299)
      1'd0:
	  CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 =
	      CAN_FIRE_RL_srcPropose_2 ?
		propDstData_1_0_lat_0$wget[256:193] :
		propDstData_1_0_rl[256:193];
      1'd1:
	  CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 =
	      CAN_FIRE_RL_srcPropose_3 ?
		propDstData_1_1_lat_0$wget[256:193] :
		propDstData_1_1_rl[256:193];
    endcase
  end
  always@(x__h80299 or
	  CAN_FIRE_RL_srcPropose_2 or
	  propDstData_1_0_lat_0$wget or
	  propDstData_1_0_rl or
	  CAN_FIRE_RL_srcPropose_3 or
	  propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
  begin
    case (x__h80299)
      1'd0:
	  CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 =
	      CAN_FIRE_RL_srcPropose_2 ?
		propDstData_1_0_lat_0$wget[192:129] :
		propDstData_1_0_rl[192:129];
      1'd1:
	  CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 =
	      CAN_FIRE_RL_srcPropose_3 ?
		propDstData_1_1_lat_0$wget[192:129] :
		propDstData_1_1_rl[192:129];
    endcase
  end
  always@(x__h80299 or
	  CAN_FIRE_RL_srcPropose_2 or
	  propDstData_1_0_lat_0$wget or
	  propDstData_1_0_rl or
	  CAN_FIRE_RL_srcPropose_3 or
	  propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
  begin
    case (x__h80299)
      1'd0:
	  CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 =
	      CAN_FIRE_RL_srcPropose_2 ?
		propDstData_1_0_lat_0$wget[128:65] :
		propDstData_1_0_rl[128:65];
      1'd1:
	  CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 =
	      CAN_FIRE_RL_srcPropose_3 ?
		propDstData_1_1_lat_0$wget[128:65] :
		propDstData_1_1_rl[128:65];
    endcase
  end
  always@(x__h80299 or
	  CAN_FIRE_RL_srcPropose_2 or
	  propDstData_1_0_lat_0$wget or
	  propDstData_1_0_rl or
	  CAN_FIRE_RL_srcPropose_3 or
	  propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
  begin
    case (x__h80299)
      1'd0:
	  CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 =
	      CAN_FIRE_RL_srcPropose_2 ?
		propDstData_1_0_lat_0$wget[64:1] :
		propDstData_1_0_rl[64:1];
      1'd1:
	  CASE_x0299_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 =
	      CAN_FIRE_RL_srcPropose_3 ?
		propDstData_1_1_lat_0$wget[64:1] :
		propDstData_1_1_rl[64:1];
    endcase
  end
  always@(x__h80299 or
	  propDstData_1_0_dummy2_1$Q_OUT or
	  IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208 or
	  propDstData_1_1_dummy2_1$Q_OUT or
	  IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246)
  begin
    case (x__h80299)
      1'd0:
	  CASE_x0299_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 =
	      propDstData_1_0_dummy2_1$Q_OUT ?
		IF_propDstData_1_0_lat_0_whas__198_THEN_propDs_ETC___d1208 :
		2'd0;
      1'd1:
	  CASE_x0299_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 =
	      propDstData_1_1_dummy2_1$Q_OUT ?
		IF_propDstData_1_1_lat_0_whas__236_THEN_propDs_ETC___d1246 :
		2'd0;
    endcase
  end
  always@(x__h80299 or
	  NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386 or
	  NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388)
  begin
    case (x__h80299)
      1'd0:
	  CASE_x0299_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 =
	      NOT_propDstData_1_0_dummy2_1_read__374_385_OR__ETC___d1386;
      1'd1:
	  CASE_x0299_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 =
	      NOT_propDstData_1_1_dummy2_1_read__376_387_OR__ETC___d1388;
    endcase
  end
  always@(x__h80299 or n__read_addr__h80477 or n__read_addr__h80556)
  begin
    case (x__h80299)
      1'd0:
	  CASE_x0299_0_n__read_addr0477_1_n__read_addr05_ETC__q26 =
	      n__read_addr__h80477;
      1'd1:
	  CASE_x0299_0_n__read_addr0477_1_n__read_addr05_ETC__q26 =
	      n__read_addr__h80556;
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
	enqDst_0_rl <= `BSV_ASSIGNMENT_DELAY 74'h0AAAAAAAAAAAAAAAAAA;
	enqDst_1_0_rl <= `BSV_ASSIGNMENT_DELAY
	    581'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	llc_axi4_adapter_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
	llc_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
	    4'd0;
	llc_axi4_adapter_master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	llc_axi4_adapter_master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	llc_axi4_adapter_master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	llc_axi4_adapter_master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	llc_axi4_adapter_master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	llc_axi4_adapter_rg_rd_req_beat <= `BSV_ASSIGNMENT_DELAY 3'd0;
	llc_axi4_adapter_rg_rd_rsp_beat <= `BSV_ASSIGNMENT_DELAY 3'd0;
	llc_axi4_adapter_rg_wr_req_beat <= `BSV_ASSIGNMENT_DELAY 3'd0;
	llc_axi4_adapter_rg_wr_rsp_beat <= `BSV_ASSIGNMENT_DELAY 3'd0;
	llc_mem_server_enqDst_0_rl <= `BSV_ASSIGNMENT_DELAY
	    66'h0AAAAAAAAAAAAAAAA;
	llc_mem_server_propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY
	    65'h0AAAAAAAAAAAAAAAA;
	llc_mem_server_propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	llc_mem_server_rg_cacheline_cache_addr <= `BSV_ASSIGNMENT_DELAY 64'd1;
	llc_mem_server_rg_cacheline_cache_dirty_delay <= `BSV_ASSIGNMENT_DELAY
	    10'd0;
	llc_mem_server_rg_cacheline_cache_state <= `BSV_ASSIGNMENT_DELAY 3'd3;
	mmioPlatform_cycle <= `BSV_ASSIGNMENT_DELAY 7'd0;
	mmioPlatform_fromHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0;
	mmioPlatform_fromHostQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmioPlatform_fromHostQ_data_0 <= `BSV_ASSIGNMENT_DELAY 64'd0;
	mmioPlatform_fromHostQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmioPlatform_fromHostQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	mmioPlatform_fromHostQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    65'h0AAAAAAAAAAAAAAAA;
	mmioPlatform_fromHostQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmioPlatform_mtime <= `BSV_ASSIGNMENT_DELAY 64'd0;
	mmioPlatform_mtimecmp_0 <= `BSV_ASSIGNMENT_DELAY 64'd0;
	mmioPlatform_mtip_0 <= `BSV_ASSIGNMENT_DELAY 1'd1;
	mmioPlatform_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
	mmioPlatform_toHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0;
	mmioPlatform_toHostQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmioPlatform_toHostQ_data_0 <= `BSV_ASSIGNMENT_DELAY 64'd0;
	mmioPlatform_toHostQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmioPlatform_toHostQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	mmioPlatform_toHostQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    65'h0AAAAAAAAAAAAAAAA;
	mmioPlatform_toHostQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_axi4_adapter_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
	mmio_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
	    4'd0;
	mmio_axi4_adapter_master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	mmio_axi4_adapter_master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	mmio_axi4_adapter_master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	mmio_axi4_adapter_master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	mmio_axi4_adapter_master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY 73'h0AAAAAAAAAAAAAAAAAA;
	propDstData_1_0_rl <= `BSV_ASSIGNMENT_DELAY
	    580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	propDstData_1_1_rl <= `BSV_ASSIGNMENT_DELAY
	    580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	propDstData_1_rl <= `BSV_ASSIGNMENT_DELAY 73'h0AAAAAAAAAAAAAAAAAA;
	propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	propDstIdx_1_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	propDstIdx_1_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	propDstIdx_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	srcRR_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	srcRR_1_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
      end
    else
      begin
        if (cfg_verbosity$EN)
	  cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
	if (enqDst_0_rl$EN)
	  enqDst_0_rl <= `BSV_ASSIGNMENT_DELAY enqDst_0_rl$D_IN;
	if (enqDst_1_0_rl$EN)
	  enqDst_1_0_rl <= `BSV_ASSIGNMENT_DELAY enqDst_1_0_rl$D_IN;
	if (llc_axi4_adapter_cfg_verbosity$EN)
	  llc_axi4_adapter_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY
	      llc_axi4_adapter_cfg_verbosity$D_IN;
	if (llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN)
	  llc_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
	      llc_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN;
	if (llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN)
	  llc_axi4_adapter_master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY
	      llc_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN;
	if (llc_axi4_adapter_master_xactor_crg_rd_data_full$EN)
	  llc_axi4_adapter_master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY
	      llc_axi4_adapter_master_xactor_crg_rd_data_full$D_IN;
	if (llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN)
	  llc_axi4_adapter_master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY
	      llc_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN;
	if (llc_axi4_adapter_master_xactor_crg_wr_data_full$EN)
	  llc_axi4_adapter_master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY
	      llc_axi4_adapter_master_xactor_crg_wr_data_full$D_IN;
	if (llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN)
	  llc_axi4_adapter_master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY
	      llc_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN;
	if (llc_axi4_adapter_rg_rd_req_beat$EN)
	  llc_axi4_adapter_rg_rd_req_beat <= `BSV_ASSIGNMENT_DELAY
	      llc_axi4_adapter_rg_rd_req_beat$D_IN;
	if (llc_axi4_adapter_rg_rd_rsp_beat$EN)
	  llc_axi4_adapter_rg_rd_rsp_beat <= `BSV_ASSIGNMENT_DELAY
	      llc_axi4_adapter_rg_rd_rsp_beat$D_IN;
	if (llc_axi4_adapter_rg_wr_req_beat$EN)
	  llc_axi4_adapter_rg_wr_req_beat <= `BSV_ASSIGNMENT_DELAY
	      llc_axi4_adapter_rg_wr_req_beat$D_IN;
	if (llc_axi4_adapter_rg_wr_rsp_beat$EN)
	  llc_axi4_adapter_rg_wr_rsp_beat <= `BSV_ASSIGNMENT_DELAY
	      llc_axi4_adapter_rg_wr_rsp_beat$D_IN;
	if (llc_mem_server_enqDst_0_rl$EN)
	  llc_mem_server_enqDst_0_rl <= `BSV_ASSIGNMENT_DELAY
	      llc_mem_server_enqDst_0_rl$D_IN;
	if (llc_mem_server_propDstData_0_rl$EN)
	  llc_mem_server_propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY
	      llc_mem_server_propDstData_0_rl$D_IN;
	if (llc_mem_server_propDstIdx_0_rl$EN)
	  llc_mem_server_propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY
	      llc_mem_server_propDstIdx_0_rl$D_IN;
	if (llc_mem_server_rg_cacheline_cache_addr$EN)
	  llc_mem_server_rg_cacheline_cache_addr <= `BSV_ASSIGNMENT_DELAY
	      llc_mem_server_rg_cacheline_cache_addr$D_IN;
	if (llc_mem_server_rg_cacheline_cache_dirty_delay$EN)
	  llc_mem_server_rg_cacheline_cache_dirty_delay <= `BSV_ASSIGNMENT_DELAY
	      llc_mem_server_rg_cacheline_cache_dirty_delay$D_IN;
	if (llc_mem_server_rg_cacheline_cache_state$EN)
	  llc_mem_server_rg_cacheline_cache_state <= `BSV_ASSIGNMENT_DELAY
	      llc_mem_server_rg_cacheline_cache_state$D_IN;
	if (mmioPlatform_cycle$EN)
	  mmioPlatform_cycle <= `BSV_ASSIGNMENT_DELAY mmioPlatform_cycle$D_IN;
	if (mmioPlatform_fromHostAddr$EN)
	  mmioPlatform_fromHostAddr <= `BSV_ASSIGNMENT_DELAY
	      mmioPlatform_fromHostAddr$D_IN;
	if (mmioPlatform_fromHostQ_clearReq_rl$EN)
	  mmioPlatform_fromHostQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmioPlatform_fromHostQ_clearReq_rl$D_IN;
	if (mmioPlatform_fromHostQ_data_0$EN)
	  mmioPlatform_fromHostQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	      mmioPlatform_fromHostQ_data_0$D_IN;
	if (mmioPlatform_fromHostQ_deqReq_rl$EN)
	  mmioPlatform_fromHostQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmioPlatform_fromHostQ_deqReq_rl$D_IN;
	if (mmioPlatform_fromHostQ_empty$EN)
	  mmioPlatform_fromHostQ_empty <= `BSV_ASSIGNMENT_DELAY
	      mmioPlatform_fromHostQ_empty$D_IN;
	if (mmioPlatform_fromHostQ_enqReq_rl$EN)
	  mmioPlatform_fromHostQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmioPlatform_fromHostQ_enqReq_rl$D_IN;
	if (mmioPlatform_fromHostQ_full$EN)
	  mmioPlatform_fromHostQ_full <= `BSV_ASSIGNMENT_DELAY
	      mmioPlatform_fromHostQ_full$D_IN;
	if (mmioPlatform_mtime$EN)
	  mmioPlatform_mtime <= `BSV_ASSIGNMENT_DELAY mmioPlatform_mtime$D_IN;
	if (mmioPlatform_mtimecmp_0$EN)
	  mmioPlatform_mtimecmp_0 <= `BSV_ASSIGNMENT_DELAY
	      mmioPlatform_mtimecmp_0$D_IN;
	if (mmioPlatform_mtip_0$EN)
	  mmioPlatform_mtip_0 <= `BSV_ASSIGNMENT_DELAY
	      mmioPlatform_mtip_0$D_IN;
	if (mmioPlatform_state$EN)
	  mmioPlatform_state <= `BSV_ASSIGNMENT_DELAY mmioPlatform_state$D_IN;
	if (mmioPlatform_toHostAddr$EN)
	  mmioPlatform_toHostAddr <= `BSV_ASSIGNMENT_DELAY
	      mmioPlatform_toHostAddr$D_IN;
	if (mmioPlatform_toHostQ_clearReq_rl$EN)
	  mmioPlatform_toHostQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmioPlatform_toHostQ_clearReq_rl$D_IN;
	if (mmioPlatform_toHostQ_data_0$EN)
	  mmioPlatform_toHostQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	      mmioPlatform_toHostQ_data_0$D_IN;
	if (mmioPlatform_toHostQ_deqReq_rl$EN)
	  mmioPlatform_toHostQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmioPlatform_toHostQ_deqReq_rl$D_IN;
	if (mmioPlatform_toHostQ_empty$EN)
	  mmioPlatform_toHostQ_empty <= `BSV_ASSIGNMENT_DELAY
	      mmioPlatform_toHostQ_empty$D_IN;
	if (mmioPlatform_toHostQ_enqReq_rl$EN)
	  mmioPlatform_toHostQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmioPlatform_toHostQ_enqReq_rl$D_IN;
	if (mmioPlatform_toHostQ_full$EN)
	  mmioPlatform_toHostQ_full <= `BSV_ASSIGNMENT_DELAY
	      mmioPlatform_toHostQ_full$D_IN;
	if (mmio_axi4_adapter_cfg_verbosity$EN)
	  mmio_axi4_adapter_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY
	      mmio_axi4_adapter_cfg_verbosity$D_IN;
	if (mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN)
	  mmio_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
	      mmio_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN;
	if (mmio_axi4_adapter_master_xactor_crg_rd_addr_full$EN)
	  mmio_axi4_adapter_master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY
	      mmio_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN;
	if (mmio_axi4_adapter_master_xactor_crg_rd_data_full$EN)
	  mmio_axi4_adapter_master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY
	      mmio_axi4_adapter_master_xactor_crg_rd_data_full$D_IN;
	if (mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN)
	  mmio_axi4_adapter_master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY
	      mmio_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN;
	if (mmio_axi4_adapter_master_xactor_crg_wr_data_full$EN)
	  mmio_axi4_adapter_master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY
	      mmio_axi4_adapter_master_xactor_crg_wr_data_full$D_IN;
	if (mmio_axi4_adapter_master_xactor_crg_wr_resp_full$EN)
	  mmio_axi4_adapter_master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY
	      mmio_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN;
	if (propDstData_0_rl$EN)
	  propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY propDstData_0_rl$D_IN;
	if (propDstData_1_0_rl$EN)
	  propDstData_1_0_rl <= `BSV_ASSIGNMENT_DELAY propDstData_1_0_rl$D_IN;
	if (propDstData_1_1_rl$EN)
	  propDstData_1_1_rl <= `BSV_ASSIGNMENT_DELAY propDstData_1_1_rl$D_IN;
	if (propDstData_1_rl$EN)
	  propDstData_1_rl <= `BSV_ASSIGNMENT_DELAY propDstData_1_rl$D_IN;
	if (propDstIdx_0_rl$EN)
	  propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_0_rl$D_IN;
	if (propDstIdx_1_0_rl$EN)
	  propDstIdx_1_0_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_1_0_rl$D_IN;
	if (propDstIdx_1_1_rl$EN)
	  propDstIdx_1_1_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_1_1_rl$D_IN;
	if (propDstIdx_1_rl$EN)
	  propDstIdx_1_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_1_rl$D_IN;
	if (srcRR_0$EN) srcRR_0 <= `BSV_ASSIGNMENT_DELAY srcRR_0$D_IN;
	if (srcRR_1_0$EN) srcRR_1_0 <= `BSV_ASSIGNMENT_DELAY srcRR_1_0$D_IN;
      end
    if (llc_axi4_adapter_master_xactor_rg_rd_addr$EN)
      llc_axi4_adapter_master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY
	  llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN;
    if (llc_axi4_adapter_master_xactor_rg_rd_data$EN)
      llc_axi4_adapter_master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY
	  llc_axi4_adapter_master_xactor_rg_rd_data$D_IN;
    if (llc_axi4_adapter_master_xactor_rg_wr_addr$EN)
      llc_axi4_adapter_master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY
	  llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN;
    if (llc_axi4_adapter_master_xactor_rg_wr_data$EN)
      llc_axi4_adapter_master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY
	  llc_axi4_adapter_master_xactor_rg_wr_data$D_IN;
    if (llc_axi4_adapter_master_xactor_rg_wr_resp$EN)
      llc_axi4_adapter_master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY
	  llc_axi4_adapter_master_xactor_rg_wr_resp$D_IN;
    if (llc_axi4_adapter_rg_cline$EN)
      llc_axi4_adapter_rg_cline <= `BSV_ASSIGNMENT_DELAY
	  llc_axi4_adapter_rg_cline$D_IN;
    if (llc_mem_server_rg_cacheline_cache_data$EN)
      llc_mem_server_rg_cacheline_cache_data <= `BSV_ASSIGNMENT_DELAY
	  llc_mem_server_rg_cacheline_cache_data$D_IN;
    if (mmioPlatform_amoResp$EN)
      mmioPlatform_amoResp <= `BSV_ASSIGNMENT_DELAY mmioPlatform_amoResp$D_IN;
    if (mmioPlatform_curReq$EN)
      mmioPlatform_curReq <= `BSV_ASSIGNMENT_DELAY mmioPlatform_curReq$D_IN;
    if (mmioPlatform_fetchedInsts_0$EN)
      mmioPlatform_fetchedInsts_0 <= `BSV_ASSIGNMENT_DELAY
	  mmioPlatform_fetchedInsts_0$D_IN;
    if (mmioPlatform_fetchingWay$EN)
      mmioPlatform_fetchingWay <= `BSV_ASSIGNMENT_DELAY
	  mmioPlatform_fetchingWay$D_IN;
    if (mmioPlatform_instSel$EN)
      mmioPlatform_instSel <= `BSV_ASSIGNMENT_DELAY mmioPlatform_instSel$D_IN;
    if (mmioPlatform_reqAmofunc$EN)
      mmioPlatform_reqAmofunc <= `BSV_ASSIGNMENT_DELAY
	  mmioPlatform_reqAmofunc$D_IN;
    if (mmioPlatform_reqBE$EN)
      mmioPlatform_reqBE <= `BSV_ASSIGNMENT_DELAY mmioPlatform_reqBE$D_IN;
    if (mmioPlatform_reqData$EN)
      mmioPlatform_reqData <= `BSV_ASSIGNMENT_DELAY mmioPlatform_reqData$D_IN;
    if (mmioPlatform_reqFunc$EN)
      mmioPlatform_reqFunc <= `BSV_ASSIGNMENT_DELAY mmioPlatform_reqFunc$D_IN;
    if (mmioPlatform_reqSz$EN)
      mmioPlatform_reqSz <= `BSV_ASSIGNMENT_DELAY mmioPlatform_reqSz$D_IN;
    if (mmioPlatform_waitLowerMSIPCRs$EN)
      mmioPlatform_waitLowerMSIPCRs <= `BSV_ASSIGNMENT_DELAY
	  mmioPlatform_waitLowerMSIPCRs$D_IN;
    if (mmioPlatform_waitMTIPCRs$EN)
      mmioPlatform_waitMTIPCRs <= `BSV_ASSIGNMENT_DELAY
	  mmioPlatform_waitMTIPCRs$D_IN;
    if (mmioPlatform_waitUpperMSIPCRs$EN)
      mmioPlatform_waitUpperMSIPCRs <= `BSV_ASSIGNMENT_DELAY
	  mmioPlatform_waitUpperMSIPCRs$D_IN;
    if (mmio_axi4_adapter_master_xactor_rg_rd_addr$EN)
      mmio_axi4_adapter_master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY
	  mmio_axi4_adapter_master_xactor_rg_rd_addr$D_IN;
    if (mmio_axi4_adapter_master_xactor_rg_rd_data$EN)
      mmio_axi4_adapter_master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY
	  mmio_axi4_adapter_master_xactor_rg_rd_data$D_IN;
    if (mmio_axi4_adapter_master_xactor_rg_wr_addr$EN)
      mmio_axi4_adapter_master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY
	  mmio_axi4_adapter_master_xactor_rg_wr_addr$D_IN;
    if (mmio_axi4_adapter_master_xactor_rg_wr_data$EN)
      mmio_axi4_adapter_master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY
	  mmio_axi4_adapter_master_xactor_rg_wr_data$D_IN;
    if (mmio_axi4_adapter_master_xactor_rg_wr_resp$EN)
      mmio_axi4_adapter_master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY
	  mmio_axi4_adapter_master_xactor_rg_wr_resp$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    cfg_verbosity = 4'hA;
    enqDst_0_rl = 74'h2AAAAAAAAAAAAAAAAAA;
    enqDst_1_0_rl =
	581'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    llc_axi4_adapter_cfg_verbosity = 4'hA;
    llc_axi4_adapter_ctr_wr_rsps_pending_crg = 4'hA;
    llc_axi4_adapter_master_xactor_crg_rd_addr_full = 1'h0;
    llc_axi4_adapter_master_xactor_crg_rd_data_full = 1'h0;
    llc_axi4_adapter_master_xactor_crg_wr_addr_full = 1'h0;
    llc_axi4_adapter_master_xactor_crg_wr_data_full = 1'h0;
    llc_axi4_adapter_master_xactor_crg_wr_resp_full = 1'h0;
    llc_axi4_adapter_master_xactor_rg_rd_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA;
    llc_axi4_adapter_master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA;
    llc_axi4_adapter_master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA;
    llc_axi4_adapter_master_xactor_rg_wr_data = 73'h0AAAAAAAAAAAAAAAAAA;
    llc_axi4_adapter_master_xactor_rg_wr_resp = 6'h2A;
    llc_axi4_adapter_rg_cline =
	512'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    llc_axi4_adapter_rg_rd_req_beat = 3'h2;
    llc_axi4_adapter_rg_rd_rsp_beat = 3'h2;
    llc_axi4_adapter_rg_wr_req_beat = 3'h2;
    llc_axi4_adapter_rg_wr_rsp_beat = 3'h2;
    llc_mem_server_enqDst_0_rl = 66'h2AAAAAAAAAAAAAAAA;
    llc_mem_server_propDstData_0_rl = 65'h0AAAAAAAAAAAAAAAA;
    llc_mem_server_propDstIdx_0_rl = 1'h0;
    llc_mem_server_rg_cacheline_cache_addr = 64'hAAAAAAAAAAAAAAAA;
    llc_mem_server_rg_cacheline_cache_data =
	512'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    llc_mem_server_rg_cacheline_cache_dirty_delay = 10'h2AA;
    llc_mem_server_rg_cacheline_cache_state = 3'h2;
    mmioPlatform_amoResp = 64'hAAAAAAAAAAAAAAAA;
    mmioPlatform_curReq = 67'h2AAAAAAAAAAAAAAAA;
    mmioPlatform_cycle = 7'h2A;
    mmioPlatform_fetchedInsts_0 = 32'hAAAAAAAA;
    mmioPlatform_fetchingWay = 1'h0;
    mmioPlatform_fromHostAddr = 61'h0AAAAAAAAAAAAAAA;
    mmioPlatform_fromHostQ_clearReq_rl = 1'h0;
    mmioPlatform_fromHostQ_data_0 = 64'hAAAAAAAAAAAAAAAA;
    mmioPlatform_fromHostQ_deqReq_rl = 1'h0;
    mmioPlatform_fromHostQ_empty = 1'h0;
    mmioPlatform_fromHostQ_enqReq_rl = 65'h0AAAAAAAAAAAAAAAA;
    mmioPlatform_fromHostQ_full = 1'h0;
    mmioPlatform_instSel = 1'h0;
    mmioPlatform_mtime = 64'hAAAAAAAAAAAAAAAA;
    mmioPlatform_mtimecmp_0 = 64'hAAAAAAAAAAAAAAAA;
    mmioPlatform_mtip_0 = 1'h0;
    mmioPlatform_reqAmofunc = 4'hA;
    mmioPlatform_reqBE = 8'hAA;
    mmioPlatform_reqData = 64'hAAAAAAAAAAAAAAAA;
    mmioPlatform_reqFunc = 6'h2A;
    mmioPlatform_reqSz = 2'h2;
    mmioPlatform_state = 2'h2;
    mmioPlatform_toHostAddr = 61'h0AAAAAAAAAAAAAAA;
    mmioPlatform_toHostQ_clearReq_rl = 1'h0;
    mmioPlatform_toHostQ_data_0 = 64'hAAAAAAAAAAAAAAAA;
    mmioPlatform_toHostQ_deqReq_rl = 1'h0;
    mmioPlatform_toHostQ_empty = 1'h0;
    mmioPlatform_toHostQ_enqReq_rl = 65'h0AAAAAAAAAAAAAAAA;
    mmioPlatform_toHostQ_full = 1'h0;
    mmioPlatform_waitLowerMSIPCRs = 1'h0;
    mmioPlatform_waitMTIPCRs = 1'h0;
    mmioPlatform_waitUpperMSIPCRs = 1'h0;
    mmio_axi4_adapter_cfg_verbosity = 4'hA;
    mmio_axi4_adapter_ctr_wr_rsps_pending_crg = 4'hA;
    mmio_axi4_adapter_master_xactor_crg_rd_addr_full = 1'h0;
    mmio_axi4_adapter_master_xactor_crg_rd_data_full = 1'h0;
    mmio_axi4_adapter_master_xactor_crg_wr_addr_full = 1'h0;
    mmio_axi4_adapter_master_xactor_crg_wr_data_full = 1'h0;
    mmio_axi4_adapter_master_xactor_crg_wr_resp_full = 1'h0;
    mmio_axi4_adapter_master_xactor_rg_rd_addr =
	97'h0AAAAAAAAAAAAAAAAAAAAAAAA;
    mmio_axi4_adapter_master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA;
    mmio_axi4_adapter_master_xactor_rg_wr_addr =
	97'h0AAAAAAAAAAAAAAAAAAAAAAAA;
    mmio_axi4_adapter_master_xactor_rg_wr_data = 73'h0AAAAAAAAAAAAAAAAAA;
    mmio_axi4_adapter_master_xactor_rg_wr_resp = 6'h2A;
    propDstData_0_rl = 73'h0AAAAAAAAAAAAAAAAAA;
    propDstData_1_0_rl =
	580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    propDstData_1_1_rl =
	580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    propDstData_1_rl = 73'h0AAAAAAAAAAAAAAAAAA;
    propDstIdx_0_rl = 1'h0;
    propDstIdx_1_0_rl = 1'h0;
    propDstIdx_1_1_rl = 1'h0;
    propDstIdx_1_rl = 1'h0;
    srcRR_0 = 1'h0;
    srcRR_1_0 = 1'h0;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_start)
	begin
	  v__h163696 = $stime;
	  #0;
	end
    v__h163690 = v__h163696 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_start)
	$display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h",
		 v__h163690,
		 start_startpc,
		 start_tohostAddr,
		 start_fromhostAddr);
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 &&
	  IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 &&
	  NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 &&
	  IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 &&
	  NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing");
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 &&
	  IF_SEL_ARR_propDstIdx_0_dummy2_1_read__062_AND_ETC___d1169 &&
	  NOT_propDstIdx_0_dummy2_1_read__062_063_OR_IF__ETC___d1096)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 &&
	  x__h61414 &&
	  NOT_propDstIdx_1_dummy2_1_read__075_076_OR_IF__ETC___d1175)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 &&
	  x__h61414 &&
	  NOT_propDstIdx_1_dummy2_1_read__075_076_OR_IF__ETC___d1175)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing");
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_enqDst_0_dummy2_0_read__083_084_OR_NOT_enq_ETC___d1099 &&
	  x__h61414 &&
	  NOT_propDstIdx_1_dummy2_1_read__075_076_OR_IF__ETC___d1175)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 &&
	  IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 &&
	  NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 &&
	  IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 &&
	  NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing");
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 &&
	  IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__326_A_ETC___d1471 &&
	  NOT_propDstIdx_1_0_dummy2_1_read__326_327_OR_I_ETC___d1370)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 &&
	  x__h80299 &&
	  NOT_propDstIdx_1_1_dummy2_1_read__344_345_OR_I_ETC___d1477)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 &&
	  x__h80299 &&
	  NOT_propDstIdx_1_1_dummy2_1_read__344_345_OR_I_ETC___d1477)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing");
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_enqDst_1_0_dummy2_0_read__357_358_OR_NOT_e_ETC___d1373 &&
	  x__h80299 &&
	  NOT_propDstIdx_1_1_dummy2_1_read__344_345_OR_I_ETC___d1477)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (core_0$RDY_coreIndInv_terminate)
	$display("Core %d terminated", $signed(32'd0));
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_tohost)
	begin
	  v__h163258 = $stime;
	  #0;
	end
    v__h163252 = v__h163258 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_tohost)
	$display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)",
		 v__h163252,
		 mmioPlatform_toHostQ_data_0,
		 mmioPlatform_toHostQ_data_0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 &&
	  mmioPlatform_toHostQ_data_0[63:1] == 63'd0)
	$display("PASS");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 &&
	  mmioPlatform_toHostQ_data_0[63:1] != 63'd0)
	$display("FAIL %0d", failed_testnum__h163301);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	begin
	  v__h5308 = $stime;
	  #0;
	end
    v__h5302 = v__h5308 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$display("%0d: %m.rl_handle_read_rsps ", v__h5302);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("AXI4_Rd_Data { ", "rid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", mmio_axi4_adapter_master_xactor_rg_rd_data[70:67]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "rdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", mmio_axi4_adapter_master_xactor_rg_rd_data[66:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "rresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", mmio_axi4_adapter_master_xactor_rg_rd_data[2:1]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "rlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_master_xactor_rg_rd_data[0])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_master_xactor_rg_rd_data[0])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "ruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	begin
	  v__h5481 = $stime;
	  #0;
	end
    v__h5475 = v__h5481 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$display("%0d: %m.rl_handle_read_rsp: fabric response error",
		 v__h5475);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write("AXI4_Rd_Data { ", "rid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write("'h%h", mmio_axi4_adapter_master_xactor_rg_rd_data[70:67]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write(", ", "rdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write("'h%h", mmio_axi4_adapter_master_xactor_rg_rd_data[66:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write(", ", "rresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write("'h%h", mmio_axi4_adapter_master_xactor_rg_rd_data[2:1]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write(", ", "rlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0 &&
	  mmio_axi4_adapter_master_xactor_rg_rd_data[0])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0 &&
	  !mmio_axi4_adapter_master_xactor_rg_rd_data[0])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write(", ", "ruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("    Response MMIO to core: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("MMIODataPRs { ", "valid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] == 2'b0)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "data: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h",
	       mmio_axi4_adapter_master_xactor_rg_rd_data[66:3],
	       " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	begin
	  v__h5741 = $stime;
	  #0;
	end
    v__h5735 = v__h5741 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$display("%d: %m.rl_handle_write_req: St request:", v__h5735);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("MMIOCRq { ", "addr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "func: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("tagged St ", "");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "byteEn: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("<V ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[64])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[64])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[65])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[65])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[66])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[66])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[67])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[67])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[68])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[68])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[69])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[69])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[70])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[70])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[71])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[71])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" >");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "data: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15)
	begin
	  v__h7883 = $stime;
	  #0;
	end
    v__h7877 = v__h7883 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15)
	$display("%0d: ERROR: CreditCounter: overflow", v__h7877);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15)
	$finish(32'd1);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("    To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("AXI4_Wr_Addr { ", "awid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "awaddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "awlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "awsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", x__h7713);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "awburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "awlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", 1'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "awcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "awprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "awqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "awregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "awuser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("               ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("AXI4_Wr_Data { ", "wdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "wstrb: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "wlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "wuser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	begin
	  v__h8098 = $stime;
	  #0;
	end
    v__h8092 = v__h8098 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$display("%0d: %m.rl_handle_write_req: unmapped IO address; returning error response",
		 v__h8092);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("MMIOCRq { ", "addr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "func: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("tagged St ", "");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "byteEn: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("<V ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[64])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[64])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[65])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[65])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[66])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[66])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[67])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[67])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[68])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[68])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[69])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[69])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[70])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[70])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[71])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[71])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" >");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "data: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	begin
	  v__h2458 = $stime;
	  #0;
	end
    v__h2452 = v__h2458 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$display("%0d: %m.rl_handle_read_req: Ld request", v__h2452);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("MMIOCRq { ", "addr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "func: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("tagged Ld ", "");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "byteEn: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("<V ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[64])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[64])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[65])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[65])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[66])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[66])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[67])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[67])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[68])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[68])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[69])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[69])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[70])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[70])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[71])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[71])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" >");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "data: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("AXI4_Rd_Addr { ", "arid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "araddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "arlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "arsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", 3'b011);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "arburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "arlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "arcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "arprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "arqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "arregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "aruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	begin
	  v__h4131 = $stime;
	  #0;
	end
    v__h4125 = v__h4131 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$display("%0d: %m.rl_handle_read_req: unmapped IO address; returning error response",
		 v__h4125);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("MMIOCRq { ", "addr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "func: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("tagged Ld ", "");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "byteEn: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("<V ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[64])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[64])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[65])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[65])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[66])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[66])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[67])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[67])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[68])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[68])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[69])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[69])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[70])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[70])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[71])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[71])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(" >");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "data: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
	  !mmio_axi4_adapter_soc_map$m_is_IO_addr &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	begin
	  v__h9268 = $stime;
	  #0;
	end
    v__h9262 = v__h9268 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$display("%0d: %m.rl_discard_write_rsp", v__h9262);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("AXI4_Wr_Resp { ", "bid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", mmio_axi4_adapter_master_xactor_rg_wr_resp[5:2]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "bresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write(", ", "buser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	  mmio_axi4_adapter_cfg_verbosity != 4'd0)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	  mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	begin
	  v__h9761 = $stime;
	  #0;
	end
    v__h9755 = v__h9761 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	  mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$display("%0d:%m.rl_discard_write_rsp: ERROR: fabric response error: exit.",
		 v__h9755);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	  mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	  mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("AXI4_Wr_Resp { ", "bid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	  mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("'h%h", mmio_axi4_adapter_master_xactor_rg_wr_resp[5:2]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	  mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write(", ", "bresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	  mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("'h%h", mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	  mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write(", ", "buser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	  mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	  mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
	  mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$finish(32'd1);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
	begin
	  v__h9924 = $stime;
	  #0;
	end
    v__h9918 = v__h9924 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
	$display("%0d:%m.rl_handle_non_Ld_St: ERROR: neither Ld nor St? exit.",
		 v__h9918);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
	$write("MMIOCRq { ", "addr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
	$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
	$write(", ", "func: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd0)
	$write("tagged Inst ",
	       "'h%h",
	       mmio_axi4_adapter_f_reqs_from_core$D_OUT[72]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0)
	$write("tagged Amo ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd0)
	$write("Swap");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd1)
	$write("Add");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd2)
	$write("Xor");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd3)
	$write("And");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd4)
	$write("Or");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd5)
	$write("Min");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd6)
	$write("Max");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd7)
	$write("Minu");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd8)
	$write("Maxu");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd0 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd1 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd2 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd3 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd4 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd5 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd6 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd7 &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd8)
	$write("None");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
	$write(", ", "byteEn: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write("<V ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[64])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[64])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[65])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[65])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[66])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[66])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[67])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[67])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[68])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[68])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[69])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[69])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[70])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[70])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  mmio_axi4_adapter_f_reqs_from_core$D_OUT[71])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
	  !mmio_axi4_adapter_f_reqs_from_core$D_OUT[71])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" >");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
	$write(", ", "data: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
	$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $finish(32'd1);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmioPlatform_processToHost &&
	  mmioPlatform_reqFunc[5:4] == 2'd2 &&
	  !mmioPlatform_toHostQ_empty)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmioPlatform_processToHost &&
	  mmioPlatform_reqFunc[5:4] == 2'd2 &&
	  !mmioPlatform_toHostQ_empty)
	$display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 798, column 30\nCannot write tohost when toHostQ not empty");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmioPlatform_processToHost &&
	  mmioPlatform_reqFunc[5:4] == 2'd2 &&
	  !mmioPlatform_toHostQ_empty)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmioPlatform_processToHost &&
	  mmioPlatform_reqFunc[5:4] != 2'd0 &&
	  mmioPlatform_reqFunc[5:4] != 2'd2 &&
	  mmioPlatform_reqFunc[5:4] != 2'd1)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmioPlatform_processToHost &&
	  mmioPlatform_reqFunc[5:4] != 2'd0 &&
	  mmioPlatform_reqFunc[5:4] != 2'd2 &&
	  mmioPlatform_reqFunc[5:4] != 2'd1)
	$display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 820, column 33\nCannot do AMO on toHost");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmioPlatform_processToHost &&
	  mmioPlatform_reqFunc[5:4] != 2'd0 &&
	  mmioPlatform_reqFunc[5:4] != 2'd2 &&
	  mmioPlatform_reqFunc[5:4] != 2'd1)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmioPlatform_processFromHost &&
	  mmioPlatform_reqFunc[5:4] == 2'd2 &&
	  mmioPlatform_fromHostQ_empty &&
	  x__h42868 != 64'd0)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmioPlatform_processFromHost &&
	  mmioPlatform_reqFunc[5:4] == 2'd2 &&
	  mmioPlatform_fromHostQ_empty &&
	  x__h42868 != 64'd0)
	$display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 856, column 41\nCan only write 0 to fromhost");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmioPlatform_processFromHost &&
	  mmioPlatform_reqFunc[5:4] == 2'd2 &&
	  mmioPlatform_fromHostQ_empty &&
	  x__h42868 != 64'd0)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmioPlatform_processFromHost &&
	  mmioPlatform_reqFunc[5:4] == 2'd2 &&
	  !mmioPlatform_fromHostQ_empty &&
	  x__h40775 != 64'd0)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmioPlatform_processFromHost &&
	  mmioPlatform_reqFunc[5:4] == 2'd2 &&
	  !mmioPlatform_fromHostQ_empty &&
	  x__h40775 != 64'd0)
	$display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 848, column 41\nCan only write 0 to fromhost");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmioPlatform_processFromHost &&
	  mmioPlatform_reqFunc[5:4] == 2'd2 &&
	  !mmioPlatform_fromHostQ_empty &&
	  x__h40775 != 64'd0)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmioPlatform_processFromHost &&
	  mmioPlatform_reqFunc[5:4] != 2'd0 &&
	  mmioPlatform_reqFunc[5:4] != 2'd2 &&
	  mmioPlatform_reqFunc[5:4] != 2'd1)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmioPlatform_processFromHost &&
	  mmioPlatform_reqFunc[5:4] != 2'd0 &&
	  mmioPlatform_reqFunc[5:4] != 2'd2 &&
	  mmioPlatform_reqFunc[5:4] != 2'd1)
	$display("Dynamic assertion failed: \"../../src_Core/CPU/MMIOPlatform.bsv\", line 871, column 33\nCannot do AMO on fromHost");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmioPlatform_processFromHost &&
	  mmioPlatform_reqFunc[5:4] != 2'd0 &&
	  mmioPlatform_reqFunc[5:4] != 2'd2 &&
	  mmioPlatform_reqFunc[5:4] != 2'd1)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (NOT_llc_mem_server_enqDst_0_dummy2_0_read__707_ETC___d1714 &&
	  !CAN_FIRE_RL_llc_mem_server_srcPropose &&
	  !llc_mem_server_propDstIdx_0_rl)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_mem_server_sendStRespToTlb)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_mem_server_sendStRespToTlb)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/LLCDmaConnect.bsv\", line 423, column 25\nNo TLB st");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_mem_server_sendStRespToTlb) $finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	begin
	  v__h135215 = $stime;
	  #0;
	end
    v__h135209 = v__h135215 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ",
		 v__h135209,
		 llc_axi4_adapter_rg_rd_rsp_beat);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("AXI4_Rd_Data { ", "rid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "rdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "rresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "rlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[0])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 &&
	  !llc_axi4_adapter_master_xactor_rg_rd_data[0])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "ruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	begin
	  v__h135382 = $stime;
	  #0;
	end
    v__h135376 = v__h135382 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit",
		 v__h135376);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write("AXI4_Rd_Data { ", "rid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write(", ", "rdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write(", ", "rresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write(", ", "rlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0 &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[0])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0 &&
	  !llc_axi4_adapter_master_xactor_rg_rd_data[0])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write(", ", "ruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
	$finish(32'd1);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("    Response to LLC: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("MemRsMsg { ", "data: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("<V ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", llc_axi4_adapter_rg_cline[127:64], " ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", llc_axi4_adapter_rg_cline[191:128], " ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", llc_axi4_adapter_rg_cline[255:192], " ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", llc_axi4_adapter_rg_cline[319:256], " ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", llc_axi4_adapter_rg_cline[383:320], " ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", llc_axi4_adapter_rg_cline[447:384], " ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", llc_axi4_adapter_rg_cline[511:448], " ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3], " ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(" >");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "child: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "id: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("LdMemRqId { ", "refill: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 &&
	  llc_axi4_adapter_f_pending_reads$D_OUT[4])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797 &&
	  !llc_axi4_adapter_f_pending_reads$D_OUT[4])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "mshrIdx: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(" }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
	  llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	begin
	  v__h137485 = $stime;
	  #0;
	end
    v__h137479 = v__h137485 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:",
		 v__h137479);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write("WbMemRs { ", "addr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write("'h%h", llc$to_mem_toM_first[639:576]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(", ", "byteEn: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write("<V ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[512])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[512])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[513])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[513])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[514])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[514])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[515])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[515])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[516])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[516])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[517])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[517])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[518])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[518])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[519])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[519])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[520])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[520])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[521])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[521])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[522])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[522])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[523])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[523])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[524])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[524])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[525])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[525])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[526])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[526])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[527])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[527])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[528])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[528])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[529])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[529])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[530])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[530])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[531])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[531])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[532])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[532])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[533])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[533])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[534])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[534])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[535])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[535])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[536])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[536])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[537])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[537])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[538])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[538])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[539])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[539])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[540])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[540])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[541])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[541])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[542])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[542])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[543])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[543])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[544])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[544])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[545])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[545])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[546])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[546])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[547])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[547])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[548])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[548])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[549])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[549])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[550])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[550])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[551])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[551])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[552])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[552])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[553])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[553])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[554])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[554])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[555])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[555])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[556])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[556])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[557])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[557])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[558])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[558])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[559])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[559])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[560])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[560])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[561])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[561])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[562])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[562])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[563])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[563])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[564])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[564])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[565])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[565])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[566])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[566])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[567])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[567])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[568])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[568])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[569])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[569])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[570])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[570])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[571])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[571])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[572])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[572])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[573])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[573])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[574])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[574])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[575])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[575])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" >");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(", ", "data: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write("<V ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write("'h%h", llc$to_mem_toM_first[63:0], " ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write("'h%h", llc$to_mem_toM_first[127:64], " ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write("'h%h", llc$to_mem_toM_first[191:128], " ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write("'h%h", llc$to_mem_toM_first[255:192], " ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write("'h%h", llc$to_mem_toM_first[319:256], " ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write("'h%h", llc$to_mem_toM_first[383:320], " ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write("'h%h", llc$to_mem_toM_first[447:384], " ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write("'h%h", llc$to_mem_toM_first[511:448], " ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" >");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write(" }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_wr_req_beat == 3'd0)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15)
	begin
	  v__h154829 = $stime;
	  #0;
	end
    v__h154823 = v__h154829 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15)
	$display("%0d: ERROR: CreditCounter: overflow", v__h154823);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15)
	$finish(32'd1);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("AXI4_Wr_Addr { ", "awid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "awaddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", mem_req_wr_addr_awaddr__h148740);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "awlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "awsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", 3'b011);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "awburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "awlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "awcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "awprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "awqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "awregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "awuser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("                       ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("AXI4_Wr_Data { ", "wdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", data64__h148655);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "wstrb: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", strb8__h148656);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "wlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "wuser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_rd_req_beat == 3'd0)
	begin
	  v__h134596 = $stime;
	  #0;
	end
    v__h134590 = v__h134596 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_rd_req_beat == 3'd0)
	$display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d",
		 v__h134590,
		 llc_axi4_adapter_rg_rd_req_beat);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_rd_req_beat == 3'd0)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_rd_req_beat == 3'd0)
	$write("LdMemRq { ", "addr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_rd_req_beat == 3'd0)
	$write("'h%h", llc$to_mem_toM_first[68:5]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_rd_req_beat == 3'd0)
	$write(", ", "child: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_rd_req_beat == 3'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_rd_req_beat == 3'd0)
	$write(", ", "id: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_rd_req_beat == 3'd0)
	$write("LdMemRqId { ", "refill: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_rd_req_beat == 3'd0 &&
	  llc$to_mem_toM_first[4])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_rd_req_beat == 3'd0 &&
	  !llc$to_mem_toM_first[4])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_rd_req_beat == 3'd0)
	$write(", ", "mshrIdx: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_rd_req_beat == 3'd0)
	$write("'h%h", llc$to_mem_toM_first[3:0], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_rd_req_beat == 3'd0)
	$write(" }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  llc_axi4_adapter_cfg_verbosity != 4'd0 &&
	  llc_axi4_adapter_rg_rd_req_beat == 3'd0)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("AXI4_Rd_Addr { ", "arid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "araddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", mem_req_rd_addr_araddr__h134816);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "arlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "arsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", 3'b011);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "arburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "arlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "arcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "arprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "arqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "arregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "aruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	begin
	  v__h161523 = $stime;
	  #0;
	end
    v__h161517 = v__h161523 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ",
		 v__h161517,
		 llc_axi4_adapter_rg_wr_rsp_beat);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("AXI4_Wr_Resp { ", "bid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "bresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write(", ", "buser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  NOT_llc_axi4_adapter_cfg_verbosity_read__780_U_ETC___d1797)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	begin
	  v__h162031 = $stime;
	  #0;
	end
    v__h162025 = v__h162031 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit",
		 v__h162025);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("AXI4_Wr_Resp { ", "bid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write(", ", "bresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write(", ", "buser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
	  llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
	$finish(32'd1);
  end
  // synopsys translate_on
endmodule  // mkProc

