//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name                         I/O  size props
// RDY_coreReq_start              O     1 const
// RDY_coreReq_perfReq            O     1 reg
// coreIndInv_perfResp            O    73
// RDY_coreIndInv_perfResp        O     1 reg
// RDY_coreIndInv_terminate       O     1 reg
// dCacheToParent_rsToP_notEmpty  O     1
// RDY_dCacheToParent_rsToP_notEmpty  O     1 const
// RDY_dCacheToParent_rsToP_deq   O     1
// dCacheToParent_rsToP_first     O   579
// RDY_dCacheToParent_rsToP_first  O     1
// dCacheToParent_rqToP_notEmpty  O     1
// RDY_dCacheToParent_rqToP_notEmpty  O     1 const
// RDY_dCacheToParent_rqToP_deq   O     1
// dCacheToParent_rqToP_first     O    72
// RDY_dCacheToParent_rqToP_first  O     1
// dCacheToParent_fromP_notFull   O     1
// RDY_dCacheToParent_fromP_notFull  O     1 const
// RDY_dCacheToParent_fromP_enq   O     1
// iCacheToParent_rsToP_notEmpty  O     1
// RDY_iCacheToParent_rsToP_notEmpty  O     1 const
// RDY_iCacheToParent_rsToP_deq   O     1
// iCacheToParent_rsToP_first     O   579
// RDY_iCacheToParent_rsToP_first  O     1
// iCacheToParent_rqToP_notEmpty  O     1
// RDY_iCacheToParent_rqToP_notEmpty  O     1 const
// RDY_iCacheToParent_rqToP_deq   O     1
// iCacheToParent_rqToP_first     O    72
// RDY_iCacheToParent_rqToP_first  O     1
// iCacheToParent_fromP_notFull   O     1
// RDY_iCacheToParent_fromP_notFull  O     1 const
// RDY_iCacheToParent_fromP_enq   O     1
// tlbToMem_memReq_notEmpty       O     1
// RDY_tlbToMem_memReq_notEmpty   O     1 const
// RDY_tlbToMem_memReq_deq        O     1
// tlbToMem_memReq_first          O    65
// RDY_tlbToMem_memReq_first      O     1
// tlbToMem_respLd_notFull        O     1
// RDY_tlbToMem_respLd_notFull    O     1 const
// RDY_tlbToMem_respLd_enq        O     1
// mmioToPlatform_cRq_notEmpty    O     1
// RDY_mmioToPlatform_cRq_notEmpty  O     1 const
// RDY_mmioToPlatform_cRq_deq     O     1
// mmioToPlatform_cRq_first       O   142
// RDY_mmioToPlatform_cRq_first   O     1
// mmioToPlatform_pRs_notFull     O     1
// RDY_mmioToPlatform_pRs_notFull  O     1 const
// RDY_mmioToPlatform_pRs_enq     O     1
// mmioToPlatform_pRq_notFull     O     1
// RDY_mmioToPlatform_pRq_notFull  O     1 const
// RDY_mmioToPlatform_pRq_enq     O     1
// mmioToPlatform_cRs_notEmpty    O     1
// RDY_mmioToPlatform_cRs_notEmpty  O     1 const
// RDY_mmioToPlatform_cRs_deq     O     1
// mmioToPlatform_cRs_first       O     1 reg
// RDY_mmioToPlatform_cRs_first   O     1
// RDY_mmioToPlatform_setTime     O     1 const
// sendDoStats                    O     1 reg
// RDY_sendDoStats                O     1 reg
// RDY_recvDoStats                O     1 const
// deadlock_dCacheCRqStuck_get    O    73 const
// RDY_deadlock_dCacheCRqStuck_get  O     1 const
// deadlock_dCachePRqStuck_get    O    68 const
// RDY_deadlock_dCachePRqStuck_get  O     1 const
// deadlock_iCacheCRqStuck_get    O    68 const
// RDY_deadlock_iCacheCRqStuck_get  O     1 const
// deadlock_iCachePRqStuck_get    O    68 const
// RDY_deadlock_iCachePRqStuck_get  O     1 const
// deadlock_renameInstStuck_get   O    78 const
// RDY_deadlock_renameInstStuck_get  O     1 const
// deadlock_renameCorrectPathStuck_get  O    78 const
// RDY_deadlock_renameCorrectPathStuck_get  O     1 const
// deadlock_commitInstStuck_get   O   163 const
// RDY_deadlock_commitInstStuck_get  O     1 const
// deadlock_commitUserInstStuck_get  O   163 const
// RDY_deadlock_commitUserInstStuck_get  O     1 const
// RDY_deadlock_checkStarted_get  O     1 const
// renameDebug_renameErr_get      O    89 const
// RDY_renameDebug_renameErr_get  O     1 const
// RDY_setMEIP                    O     1 const
// RDY_setSEIP                    O     1 const
// CLK                            I     1 clock
// RST_N                          I     1 reset
// coreReq_start_running          I     1 unused
// coreReq_start_startpc          I    64
// coreReq_start_toHostAddr       I    64 reg
// coreReq_start_fromHostAddr     I    64 reg
// coreReq_perfReq_loc            I     4 reg
// coreReq_perfReq_t              I     5 reg
// dCacheToParent_fromP_enq_x     I   583
// iCacheToParent_fromP_enq_x     I   583
// tlbToMem_respLd_enq_x          I    65
// mmioToPlatform_pRs_enq_x       I    67
// mmioToPlatform_pRq_enq_x       I    39
// mmioToPlatform_setTime_t       I    64 reg
// recvDoStats_x                  I     1 reg
// setMEIP_v                      I     1 reg
// setSEIP_v                      I     1
// EN_coreReq_start               I     1
// EN_coreReq_perfReq             I     1
// EN_coreIndInv_terminate        I     1
// EN_dCacheToParent_rsToP_deq    I     1
// EN_dCacheToParent_rqToP_deq    I     1
// EN_dCacheToParent_fromP_enq    I     1
// EN_iCacheToParent_rsToP_deq    I     1
// EN_iCacheToParent_rqToP_deq    I     1
// EN_iCacheToParent_fromP_enq    I     1
// EN_tlbToMem_memReq_deq         I     1
// EN_tlbToMem_respLd_enq         I     1
// EN_mmioToPlatform_cRq_deq      I     1
// EN_mmioToPlatform_pRs_enq      I     1
// EN_mmioToPlatform_pRq_enq      I     1
// EN_mmioToPlatform_cRs_deq      I     1
// EN_mmioToPlatform_setTime      I     1
// EN_recvDoStats                 I     1
// EN_deadlock_checkStarted_get   I     1 unused
// EN_setMEIP                     I     1
// EN_setSEIP                     I     1
// EN_coreIndInv_perfResp         I     1
// EN_sendDoStats                 I     1
// EN_deadlock_dCacheCRqStuck_get  I     1 unused
// EN_deadlock_dCachePRqStuck_get  I     1 unused
// EN_deadlock_iCacheCRqStuck_get  I     1 unused
// EN_deadlock_iCachePRqStuck_get  I     1 unused
// EN_deadlock_renameInstStuck_get  I     1 unused
// EN_deadlock_renameCorrectPathStuck_get  I     1 unused
// EN_deadlock_commitInstStuck_get  I     1 unused
// EN_deadlock_commitUserInstStuck_get  I     1 unused
// EN_renameDebug_renameErr_get   I     1 unused
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkCore(CLK,
	      RST_N,

	      coreReq_start_running,
	      coreReq_start_startpc,
	      coreReq_start_toHostAddr,
	      coreReq_start_fromHostAddr,
	      EN_coreReq_start,
	      RDY_coreReq_start,

	      coreReq_perfReq_loc,
	      coreReq_perfReq_t,
	      EN_coreReq_perfReq,
	      RDY_coreReq_perfReq,

	      EN_coreIndInv_perfResp,
	      coreIndInv_perfResp,
	      RDY_coreIndInv_perfResp,

	      EN_coreIndInv_terminate,
	      RDY_coreIndInv_terminate,

	      dCacheToParent_rsToP_notEmpty,
	      RDY_dCacheToParent_rsToP_notEmpty,

	      EN_dCacheToParent_rsToP_deq,
	      RDY_dCacheToParent_rsToP_deq,

	      dCacheToParent_rsToP_first,
	      RDY_dCacheToParent_rsToP_first,

	      dCacheToParent_rqToP_notEmpty,
	      RDY_dCacheToParent_rqToP_notEmpty,

	      EN_dCacheToParent_rqToP_deq,
	      RDY_dCacheToParent_rqToP_deq,

	      dCacheToParent_rqToP_first,
	      RDY_dCacheToParent_rqToP_first,

	      dCacheToParent_fromP_notFull,
	      RDY_dCacheToParent_fromP_notFull,

	      dCacheToParent_fromP_enq_x,
	      EN_dCacheToParent_fromP_enq,
	      RDY_dCacheToParent_fromP_enq,

	      iCacheToParent_rsToP_notEmpty,
	      RDY_iCacheToParent_rsToP_notEmpty,

	      EN_iCacheToParent_rsToP_deq,
	      RDY_iCacheToParent_rsToP_deq,

	      iCacheToParent_rsToP_first,
	      RDY_iCacheToParent_rsToP_first,

	      iCacheToParent_rqToP_notEmpty,
	      RDY_iCacheToParent_rqToP_notEmpty,

	      EN_iCacheToParent_rqToP_deq,
	      RDY_iCacheToParent_rqToP_deq,

	      iCacheToParent_rqToP_first,
	      RDY_iCacheToParent_rqToP_first,

	      iCacheToParent_fromP_notFull,
	      RDY_iCacheToParent_fromP_notFull,

	      iCacheToParent_fromP_enq_x,
	      EN_iCacheToParent_fromP_enq,
	      RDY_iCacheToParent_fromP_enq,

	      tlbToMem_memReq_notEmpty,
	      RDY_tlbToMem_memReq_notEmpty,

	      EN_tlbToMem_memReq_deq,
	      RDY_tlbToMem_memReq_deq,

	      tlbToMem_memReq_first,
	      RDY_tlbToMem_memReq_first,

	      tlbToMem_respLd_notFull,
	      RDY_tlbToMem_respLd_notFull,

	      tlbToMem_respLd_enq_x,
	      EN_tlbToMem_respLd_enq,
	      RDY_tlbToMem_respLd_enq,

	      mmioToPlatform_cRq_notEmpty,
	      RDY_mmioToPlatform_cRq_notEmpty,

	      EN_mmioToPlatform_cRq_deq,
	      RDY_mmioToPlatform_cRq_deq,

	      mmioToPlatform_cRq_first,
	      RDY_mmioToPlatform_cRq_first,

	      mmioToPlatform_pRs_notFull,
	      RDY_mmioToPlatform_pRs_notFull,

	      mmioToPlatform_pRs_enq_x,
	      EN_mmioToPlatform_pRs_enq,
	      RDY_mmioToPlatform_pRs_enq,

	      mmioToPlatform_pRq_notFull,
	      RDY_mmioToPlatform_pRq_notFull,

	      mmioToPlatform_pRq_enq_x,
	      EN_mmioToPlatform_pRq_enq,
	      RDY_mmioToPlatform_pRq_enq,

	      mmioToPlatform_cRs_notEmpty,
	      RDY_mmioToPlatform_cRs_notEmpty,

	      EN_mmioToPlatform_cRs_deq,
	      RDY_mmioToPlatform_cRs_deq,

	      mmioToPlatform_cRs_first,
	      RDY_mmioToPlatform_cRs_first,

	      mmioToPlatform_setTime_t,
	      EN_mmioToPlatform_setTime,
	      RDY_mmioToPlatform_setTime,

	      EN_sendDoStats,
	      sendDoStats,
	      RDY_sendDoStats,

	      recvDoStats_x,
	      EN_recvDoStats,
	      RDY_recvDoStats,

	      EN_deadlock_dCacheCRqStuck_get,
	      deadlock_dCacheCRqStuck_get,
	      RDY_deadlock_dCacheCRqStuck_get,

	      EN_deadlock_dCachePRqStuck_get,
	      deadlock_dCachePRqStuck_get,
	      RDY_deadlock_dCachePRqStuck_get,

	      EN_deadlock_iCacheCRqStuck_get,
	      deadlock_iCacheCRqStuck_get,
	      RDY_deadlock_iCacheCRqStuck_get,

	      EN_deadlock_iCachePRqStuck_get,
	      deadlock_iCachePRqStuck_get,
	      RDY_deadlock_iCachePRqStuck_get,

	      EN_deadlock_renameInstStuck_get,
	      deadlock_renameInstStuck_get,
	      RDY_deadlock_renameInstStuck_get,

	      EN_deadlock_renameCorrectPathStuck_get,
	      deadlock_renameCorrectPathStuck_get,
	      RDY_deadlock_renameCorrectPathStuck_get,

	      EN_deadlock_commitInstStuck_get,
	      deadlock_commitInstStuck_get,
	      RDY_deadlock_commitInstStuck_get,

	      EN_deadlock_commitUserInstStuck_get,
	      deadlock_commitUserInstStuck_get,
	      RDY_deadlock_commitUserInstStuck_get,

	      EN_deadlock_checkStarted_get,
	      RDY_deadlock_checkStarted_get,

	      EN_renameDebug_renameErr_get,
	      renameDebug_renameErr_get,
	      RDY_renameDebug_renameErr_get,

	      setMEIP_v,
	      EN_setMEIP,
	      RDY_setMEIP,

	      setSEIP_v,
	      EN_setSEIP,
	      RDY_setSEIP);
  input  CLK;
  input  RST_N;

  // action method coreReq_start
  input  coreReq_start_running;
  input  [63 : 0] coreReq_start_startpc;
  input  [63 : 0] coreReq_start_toHostAddr;
  input  [63 : 0] coreReq_start_fromHostAddr;
  input  EN_coreReq_start;
  output RDY_coreReq_start;

  // action method coreReq_perfReq
  input  [3 : 0] coreReq_perfReq_loc;
  input  [4 : 0] coreReq_perfReq_t;
  input  EN_coreReq_perfReq;
  output RDY_coreReq_perfReq;

  // actionvalue method coreIndInv_perfResp
  input  EN_coreIndInv_perfResp;
  output [72 : 0] coreIndInv_perfResp;
  output RDY_coreIndInv_perfResp;

  // action method coreIndInv_terminate
  input  EN_coreIndInv_terminate;
  output RDY_coreIndInv_terminate;

  // value method dCacheToParent_rsToP_notEmpty
  output dCacheToParent_rsToP_notEmpty;
  output RDY_dCacheToParent_rsToP_notEmpty;

  // action method dCacheToParent_rsToP_deq
  input  EN_dCacheToParent_rsToP_deq;
  output RDY_dCacheToParent_rsToP_deq;

  // value method dCacheToParent_rsToP_first
  output [578 : 0] dCacheToParent_rsToP_first;
  output RDY_dCacheToParent_rsToP_first;

  // value method dCacheToParent_rqToP_notEmpty
  output dCacheToParent_rqToP_notEmpty;
  output RDY_dCacheToParent_rqToP_notEmpty;

  // action method dCacheToParent_rqToP_deq
  input  EN_dCacheToParent_rqToP_deq;
  output RDY_dCacheToParent_rqToP_deq;

  // value method dCacheToParent_rqToP_first
  output [71 : 0] dCacheToParent_rqToP_first;
  output RDY_dCacheToParent_rqToP_first;

  // value method dCacheToParent_fromP_notFull
  output dCacheToParent_fromP_notFull;
  output RDY_dCacheToParent_fromP_notFull;

  // action method dCacheToParent_fromP_enq
  input  [582 : 0] dCacheToParent_fromP_enq_x;
  input  EN_dCacheToParent_fromP_enq;
  output RDY_dCacheToParent_fromP_enq;

  // value method iCacheToParent_rsToP_notEmpty
  output iCacheToParent_rsToP_notEmpty;
  output RDY_iCacheToParent_rsToP_notEmpty;

  // action method iCacheToParent_rsToP_deq
  input  EN_iCacheToParent_rsToP_deq;
  output RDY_iCacheToParent_rsToP_deq;

  // value method iCacheToParent_rsToP_first
  output [578 : 0] iCacheToParent_rsToP_first;
  output RDY_iCacheToParent_rsToP_first;

  // value method iCacheToParent_rqToP_notEmpty
  output iCacheToParent_rqToP_notEmpty;
  output RDY_iCacheToParent_rqToP_notEmpty;

  // action method iCacheToParent_rqToP_deq
  input  EN_iCacheToParent_rqToP_deq;
  output RDY_iCacheToParent_rqToP_deq;

  // value method iCacheToParent_rqToP_first
  output [71 : 0] iCacheToParent_rqToP_first;
  output RDY_iCacheToParent_rqToP_first;

  // value method iCacheToParent_fromP_notFull
  output iCacheToParent_fromP_notFull;
  output RDY_iCacheToParent_fromP_notFull;

  // action method iCacheToParent_fromP_enq
  input  [582 : 0] iCacheToParent_fromP_enq_x;
  input  EN_iCacheToParent_fromP_enq;
  output RDY_iCacheToParent_fromP_enq;

  // value method tlbToMem_memReq_notEmpty
  output tlbToMem_memReq_notEmpty;
  output RDY_tlbToMem_memReq_notEmpty;

  // action method tlbToMem_memReq_deq
  input  EN_tlbToMem_memReq_deq;
  output RDY_tlbToMem_memReq_deq;

  // value method tlbToMem_memReq_first
  output [64 : 0] tlbToMem_memReq_first;
  output RDY_tlbToMem_memReq_first;

  // value method tlbToMem_respLd_notFull
  output tlbToMem_respLd_notFull;
  output RDY_tlbToMem_respLd_notFull;

  // action method tlbToMem_respLd_enq
  input  [64 : 0] tlbToMem_respLd_enq_x;
  input  EN_tlbToMem_respLd_enq;
  output RDY_tlbToMem_respLd_enq;

  // value method mmioToPlatform_cRq_notEmpty
  output mmioToPlatform_cRq_notEmpty;
  output RDY_mmioToPlatform_cRq_notEmpty;

  // action method mmioToPlatform_cRq_deq
  input  EN_mmioToPlatform_cRq_deq;
  output RDY_mmioToPlatform_cRq_deq;

  // value method mmioToPlatform_cRq_first
  output [141 : 0] mmioToPlatform_cRq_first;
  output RDY_mmioToPlatform_cRq_first;

  // value method mmioToPlatform_pRs_notFull
  output mmioToPlatform_pRs_notFull;
  output RDY_mmioToPlatform_pRs_notFull;

  // action method mmioToPlatform_pRs_enq
  input  [66 : 0] mmioToPlatform_pRs_enq_x;
  input  EN_mmioToPlatform_pRs_enq;
  output RDY_mmioToPlatform_pRs_enq;

  // value method mmioToPlatform_pRq_notFull
  output mmioToPlatform_pRq_notFull;
  output RDY_mmioToPlatform_pRq_notFull;

  // action method mmioToPlatform_pRq_enq
  input  [38 : 0] mmioToPlatform_pRq_enq_x;
  input  EN_mmioToPlatform_pRq_enq;
  output RDY_mmioToPlatform_pRq_enq;

  // value method mmioToPlatform_cRs_notEmpty
  output mmioToPlatform_cRs_notEmpty;
  output RDY_mmioToPlatform_cRs_notEmpty;

  // action method mmioToPlatform_cRs_deq
  input  EN_mmioToPlatform_cRs_deq;
  output RDY_mmioToPlatform_cRs_deq;

  // value method mmioToPlatform_cRs_first
  output mmioToPlatform_cRs_first;
  output RDY_mmioToPlatform_cRs_first;

  // action method mmioToPlatform_setTime
  input  [63 : 0] mmioToPlatform_setTime_t;
  input  EN_mmioToPlatform_setTime;
  output RDY_mmioToPlatform_setTime;

  // actionvalue method sendDoStats
  input  EN_sendDoStats;
  output sendDoStats;
  output RDY_sendDoStats;

  // action method recvDoStats
  input  recvDoStats_x;
  input  EN_recvDoStats;
  output RDY_recvDoStats;

  // actionvalue method deadlock_dCacheCRqStuck_get
  input  EN_deadlock_dCacheCRqStuck_get;
  output [72 : 0] deadlock_dCacheCRqStuck_get;
  output RDY_deadlock_dCacheCRqStuck_get;

  // actionvalue method deadlock_dCachePRqStuck_get
  input  EN_deadlock_dCachePRqStuck_get;
  output [67 : 0] deadlock_dCachePRqStuck_get;
  output RDY_deadlock_dCachePRqStuck_get;

  // actionvalue method deadlock_iCacheCRqStuck_get
  input  EN_deadlock_iCacheCRqStuck_get;
  output [67 : 0] deadlock_iCacheCRqStuck_get;
  output RDY_deadlock_iCacheCRqStuck_get;

  // actionvalue method deadlock_iCachePRqStuck_get
  input  EN_deadlock_iCachePRqStuck_get;
  output [67 : 0] deadlock_iCachePRqStuck_get;
  output RDY_deadlock_iCachePRqStuck_get;

  // actionvalue method deadlock_renameInstStuck_get
  input  EN_deadlock_renameInstStuck_get;
  output [77 : 0] deadlock_renameInstStuck_get;
  output RDY_deadlock_renameInstStuck_get;

  // actionvalue method deadlock_renameCorrectPathStuck_get
  input  EN_deadlock_renameCorrectPathStuck_get;
  output [77 : 0] deadlock_renameCorrectPathStuck_get;
  output RDY_deadlock_renameCorrectPathStuck_get;

  // actionvalue method deadlock_commitInstStuck_get
  input  EN_deadlock_commitInstStuck_get;
  output [162 : 0] deadlock_commitInstStuck_get;
  output RDY_deadlock_commitInstStuck_get;

  // actionvalue method deadlock_commitUserInstStuck_get
  input  EN_deadlock_commitUserInstStuck_get;
  output [162 : 0] deadlock_commitUserInstStuck_get;
  output RDY_deadlock_commitUserInstStuck_get;

  // action method deadlock_checkStarted_get
  input  EN_deadlock_checkStarted_get;
  output RDY_deadlock_checkStarted_get;

  // actionvalue method renameDebug_renameErr_get
  input  EN_renameDebug_renameErr_get;
  output [88 : 0] renameDebug_renameErr_get;
  output RDY_renameDebug_renameErr_get;

  // action method setMEIP
  input  setMEIP_v;
  input  EN_setMEIP;
  output RDY_setMEIP;

  // action method setSEIP
  input  setSEIP_v;
  input  EN_setSEIP;
  output RDY_setSEIP;

  // signals for module outputs
  wire [578 : 0] dCacheToParent_rsToP_first, iCacheToParent_rsToP_first;
  wire [162 : 0] deadlock_commitInstStuck_get,
		 deadlock_commitUserInstStuck_get;
  wire [141 : 0] mmioToPlatform_cRq_first;
  wire [88 : 0] renameDebug_renameErr_get;
  wire [77 : 0] deadlock_renameCorrectPathStuck_get,
		deadlock_renameInstStuck_get;
  wire [72 : 0] coreIndInv_perfResp, deadlock_dCacheCRqStuck_get;
  wire [71 : 0] dCacheToParent_rqToP_first, iCacheToParent_rqToP_first;
  wire [67 : 0] deadlock_dCachePRqStuck_get,
		deadlock_iCacheCRqStuck_get,
		deadlock_iCachePRqStuck_get;
  wire [64 : 0] tlbToMem_memReq_first;
  wire RDY_coreIndInv_perfResp,
       RDY_coreIndInv_terminate,
       RDY_coreReq_perfReq,
       RDY_coreReq_start,
       RDY_dCacheToParent_fromP_enq,
       RDY_dCacheToParent_fromP_notFull,
       RDY_dCacheToParent_rqToP_deq,
       RDY_dCacheToParent_rqToP_first,
       RDY_dCacheToParent_rqToP_notEmpty,
       RDY_dCacheToParent_rsToP_deq,
       RDY_dCacheToParent_rsToP_first,
       RDY_dCacheToParent_rsToP_notEmpty,
       RDY_deadlock_checkStarted_get,
       RDY_deadlock_commitInstStuck_get,
       RDY_deadlock_commitUserInstStuck_get,
       RDY_deadlock_dCacheCRqStuck_get,
       RDY_deadlock_dCachePRqStuck_get,
       RDY_deadlock_iCacheCRqStuck_get,
       RDY_deadlock_iCachePRqStuck_get,
       RDY_deadlock_renameCorrectPathStuck_get,
       RDY_deadlock_renameInstStuck_get,
       RDY_iCacheToParent_fromP_enq,
       RDY_iCacheToParent_fromP_notFull,
       RDY_iCacheToParent_rqToP_deq,
       RDY_iCacheToParent_rqToP_first,
       RDY_iCacheToParent_rqToP_notEmpty,
       RDY_iCacheToParent_rsToP_deq,
       RDY_iCacheToParent_rsToP_first,
       RDY_iCacheToParent_rsToP_notEmpty,
       RDY_mmioToPlatform_cRq_deq,
       RDY_mmioToPlatform_cRq_first,
       RDY_mmioToPlatform_cRq_notEmpty,
       RDY_mmioToPlatform_cRs_deq,
       RDY_mmioToPlatform_cRs_first,
       RDY_mmioToPlatform_cRs_notEmpty,
       RDY_mmioToPlatform_pRq_enq,
       RDY_mmioToPlatform_pRq_notFull,
       RDY_mmioToPlatform_pRs_enq,
       RDY_mmioToPlatform_pRs_notFull,
       RDY_mmioToPlatform_setTime,
       RDY_recvDoStats,
       RDY_renameDebug_renameErr_get,
       RDY_sendDoStats,
       RDY_setMEIP,
       RDY_setSEIP,
       RDY_tlbToMem_memReq_deq,
       RDY_tlbToMem_memReq_first,
       RDY_tlbToMem_memReq_notEmpty,
       RDY_tlbToMem_respLd_enq,
       RDY_tlbToMem_respLd_notFull,
       dCacheToParent_fromP_notFull,
       dCacheToParent_rqToP_notEmpty,
       dCacheToParent_rsToP_notEmpty,
       iCacheToParent_fromP_notFull,
       iCacheToParent_rqToP_notEmpty,
       iCacheToParent_rsToP_notEmpty,
       mmioToPlatform_cRq_notEmpty,
       mmioToPlatform_cRs_first,
       mmioToPlatform_cRs_notEmpty,
       mmioToPlatform_pRq_notFull,
       mmioToPlatform_pRs_notFull,
       sendDoStats,
       tlbToMem_memReq_notEmpty,
       tlbToMem_respLd_notFull;

  // inlined wires
  reg [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget;
  reg [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget;
  reg [58 : 0] coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget;
  reg [1 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget;
  wire [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget;
  wire [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget;
  wire [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget;
  wire [142 : 0] mmio_cRqQ_enqReq_lat_0$wget, mmio_dataReqQ_enqReq_lat_0$wget;
  wire [76 : 0] coreFix_memExe_issueLd$wget;
  wire [72 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget;
  wire [70 : 0] coreFix_aluExe_0_bypassWire_0$wget,
		coreFix_aluExe_0_bypassWire_1$wget,
		coreFix_aluExe_0_bypassWire_2$wget,
		coreFix_aluExe_0_bypassWire_3$wget;
  wire [69 : 0] coreFix_memExe_forwardQ_enqReq_lat_0$wget,
		coreFix_memExe_memRespLdQ_enqReq_lat_0$wget;
  wire [68 : 0] coreFix_memExe_reqLdQ_data_0_lat_0$wget;
  wire [67 : 0] mmio_pRsQ_enqReq_lat_0$wget;
  wire [65 : 0] coreFix_memExe_reqStQ_data_0_lat_0$wget,
		mmio_dataRespQ_enqReq_lat_0$wget;
  wire [63 : 0] csrf_mcycle_ehr_data_lat_0$wget;
  wire [39 : 0] mmio_pRqQ_enqReq_lat_0$wget;
  wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget;
  wire [1 : 0] mmio_cRsQ_enqReq_lat_0$wget;
  wire coreFix_aluExe_0_bypassWire_0$whas,
       coreFix_aluExe_0_bypassWire_1$whas,
       coreFix_aluExe_0_bypassWire_2$whas,
       coreFix_aluExe_0_bypassWire_3$whas,
       coreFix_aluExe_1_bypassWire_2$whas,
       coreFix_aluExe_1_bypassWire_3$whas,
       coreFix_fpuMulDivExe_0_bypassWire_2$whas,
       coreFix_fpuMulDivExe_0_bypassWire_3$whas,
       coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas,
       coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_newReq$whas,
       coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_newReq$whas,
       coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_newReq$whas,
       coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas,
       coreFix_globalSpecUpdate_correctSpecTag_0$whas,
       coreFix_globalSpecUpdate_correctSpecTag_1$whas,
       coreFix_memExe_bypassWire_2$whas,
       coreFix_memExe_bypassWire_3$whas,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas,
       coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas,
       coreFix_memExe_forwardQ_enqReq_lat_0$whas,
       coreFix_memExe_issueLd$whas,
       coreFix_memExe_memRespLdQ_enqReq_lat_0$whas,
       coreFix_memExe_reqLdQ_data_0_lat_0$whas,
       coreFix_memExe_reqLdQ_empty_lat_0$whas,
       coreFix_memExe_reqLdQ_full_lat_0$whas,
       coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas,
       coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas,
       coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas,
       coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas,
       csrInstOrInterruptInflight_lat_1$whas,
       csrf_mcycle_ehr_data_lat_0$whas,
       csrf_minstret_ehr_data_dummy_1_0$whas,
       csrf_minstret_ehr_data_lat_0$whas,
       csrf_minstret_ehr_data_lat_1$whas,
       mmio_cRqQ_enqReq_lat_0$whas,
       mmio_dataPendQ_enqReq_lat_0$whas,
       mmio_dataReqQ_enqReq_lat_0$whas,
       mmio_dataRespQ_deqReq_lat_0$whas,
       mmio_pRsQ_deqReq_lat_0$whas;

  // register commitStage_commitTrap
  reg [165 : 0] commitStage_commitTrap;
  wire [165 : 0] commitStage_commitTrap$D_IN;
  wire commitStage_commitTrap$EN;

  // register commitStage_rg_serial_num
  reg [63 : 0] commitStage_rg_serial_num;
  wire [63 : 0] commitStage_rg_serial_num$D_IN;
  wire commitStage_rg_serial_num$EN;

  // register coreFix_doStatsReg
  reg coreFix_doStatsReg;
  wire coreFix_doStatsReg$D_IN, coreFix_doStatsReg$EN;

  // register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt
  reg [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt;
  wire [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$D_IN;
  wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$EN;

  // register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init
  reg coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init;
  wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$D_IN,
       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$EN;

  // register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready
  reg coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready;
  wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready$D_IN,
       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready$EN;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit
  reg [1 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit;
  wire [1 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN;
  wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0
  reg [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0;
  wire [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0$D_IN;
  wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0$EN;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1
  reg [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1;
  wire [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1$D_IN;
  wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1$EN;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0
  reg [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0;
  wire [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0$D_IN;
  wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0$EN;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1
  reg [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1;
  wire [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1$D_IN;
  wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1$EN;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0
  reg [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0;
  wire [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0$D_IN;
  wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0$EN;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1
  reg [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1;
  wire [128 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1$D_IN;
  wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1$EN;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0
  reg [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0;
  wire [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$D_IN;
  wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$EN;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1
  reg [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1;
  wire [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$D_IN;
  wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl
  reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0
  reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0;
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1
  reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1;
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2
  reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2;
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3
  reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3;
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4
  reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4;
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5
  reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5;
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6
  reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6;
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7
  reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7;
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP
  reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP;
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl
  reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty
  reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP
  reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP;
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl
  reg [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl;
  wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full
  reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl
  reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl;
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0
  reg [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0;
  wire [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1
  reg [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1;
  wire [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP
  reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP;
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl
  reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl;
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty
  reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty;
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP
  reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP;
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl
  reg [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl;
  wire [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full
  reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full;
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl
  reg [58 : 0] coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl;
  wire [58 : 0] coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_processAmo
  reg [160 : 0] coreFix_memExe_dMem_cache_m_banks_0_processAmo;
  reg [160 : 0] coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_processAmo$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl
  reg [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl;
  wire [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl
  reg coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl
  reg coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl
  reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0
  reg [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0;
  wire [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1
  reg [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1;
  wire [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP
  reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl
  reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty
  reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP
  reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl
  reg [72 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl;
  wire [72 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full
  reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl
  reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl;
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0
  reg [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0;
  wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1
  reg [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1;
  wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP
  reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP;
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl
  reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl;
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty
  reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty;
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP
  reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP;
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl
  reg [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl;
  wire [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN;
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$EN;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full
  reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full;
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$EN;

  // register coreFix_memExe_dMem_perfReqQ_clearReq_rl
  reg coreFix_memExe_dMem_perfReqQ_clearReq_rl;
  wire coreFix_memExe_dMem_perfReqQ_clearReq_rl$D_IN,
       coreFix_memExe_dMem_perfReqQ_clearReq_rl$EN;

  // register coreFix_memExe_dMem_perfReqQ_data_0
  reg [3 : 0] coreFix_memExe_dMem_perfReqQ_data_0;
  wire [3 : 0] coreFix_memExe_dMem_perfReqQ_data_0$D_IN;
  wire coreFix_memExe_dMem_perfReqQ_data_0$EN;

  // register coreFix_memExe_dMem_perfReqQ_deqReq_rl
  reg coreFix_memExe_dMem_perfReqQ_deqReq_rl;
  wire coreFix_memExe_dMem_perfReqQ_deqReq_rl$D_IN,
       coreFix_memExe_dMem_perfReqQ_deqReq_rl$EN;

  // register coreFix_memExe_dMem_perfReqQ_empty
  reg coreFix_memExe_dMem_perfReqQ_empty;
  wire coreFix_memExe_dMem_perfReqQ_empty$D_IN,
       coreFix_memExe_dMem_perfReqQ_empty$EN;

  // register coreFix_memExe_dMem_perfReqQ_enqReq_rl
  reg [4 : 0] coreFix_memExe_dMem_perfReqQ_enqReq_rl;
  wire [4 : 0] coreFix_memExe_dMem_perfReqQ_enqReq_rl$D_IN;
  wire coreFix_memExe_dMem_perfReqQ_enqReq_rl$EN;

  // register coreFix_memExe_dMem_perfReqQ_full
  reg coreFix_memExe_dMem_perfReqQ_full;
  wire coreFix_memExe_dMem_perfReqQ_full$D_IN,
       coreFix_memExe_dMem_perfReqQ_full$EN;

  // register coreFix_memExe_forwardQ_clearReq_rl
  reg coreFix_memExe_forwardQ_clearReq_rl;
  wire coreFix_memExe_forwardQ_clearReq_rl$D_IN,
       coreFix_memExe_forwardQ_clearReq_rl$EN;

  // register coreFix_memExe_forwardQ_data_0
  reg [68 : 0] coreFix_memExe_forwardQ_data_0;
  wire [68 : 0] coreFix_memExe_forwardQ_data_0$D_IN;
  wire coreFix_memExe_forwardQ_data_0$EN;

  // register coreFix_memExe_forwardQ_data_1
  reg [68 : 0] coreFix_memExe_forwardQ_data_1;
  wire [68 : 0] coreFix_memExe_forwardQ_data_1$D_IN;
  wire coreFix_memExe_forwardQ_data_1$EN;

  // register coreFix_memExe_forwardQ_deqP
  reg coreFix_memExe_forwardQ_deqP;
  wire coreFix_memExe_forwardQ_deqP$D_IN, coreFix_memExe_forwardQ_deqP$EN;

  // register coreFix_memExe_forwardQ_deqReq_rl
  reg coreFix_memExe_forwardQ_deqReq_rl;
  wire coreFix_memExe_forwardQ_deqReq_rl$D_IN,
       coreFix_memExe_forwardQ_deqReq_rl$EN;

  // register coreFix_memExe_forwardQ_empty
  reg coreFix_memExe_forwardQ_empty;
  wire coreFix_memExe_forwardQ_empty$D_IN, coreFix_memExe_forwardQ_empty$EN;

  // register coreFix_memExe_forwardQ_enqP
  reg coreFix_memExe_forwardQ_enqP;
  wire coreFix_memExe_forwardQ_enqP$D_IN, coreFix_memExe_forwardQ_enqP$EN;

  // register coreFix_memExe_forwardQ_enqReq_rl
  reg [69 : 0] coreFix_memExe_forwardQ_enqReq_rl;
  wire [69 : 0] coreFix_memExe_forwardQ_enqReq_rl$D_IN;
  wire coreFix_memExe_forwardQ_enqReq_rl$EN;

  // register coreFix_memExe_forwardQ_full
  reg coreFix_memExe_forwardQ_full;
  wire coreFix_memExe_forwardQ_full$D_IN, coreFix_memExe_forwardQ_full$EN;

  // register coreFix_memExe_memRespLdQ_clearReq_rl
  reg coreFix_memExe_memRespLdQ_clearReq_rl;
  wire coreFix_memExe_memRespLdQ_clearReq_rl$D_IN,
       coreFix_memExe_memRespLdQ_clearReq_rl$EN;

  // register coreFix_memExe_memRespLdQ_data_0
  reg [68 : 0] coreFix_memExe_memRespLdQ_data_0;
  wire [68 : 0] coreFix_memExe_memRespLdQ_data_0$D_IN;
  wire coreFix_memExe_memRespLdQ_data_0$EN;

  // register coreFix_memExe_memRespLdQ_data_1
  reg [68 : 0] coreFix_memExe_memRespLdQ_data_1;
  wire [68 : 0] coreFix_memExe_memRespLdQ_data_1$D_IN;
  wire coreFix_memExe_memRespLdQ_data_1$EN;

  // register coreFix_memExe_memRespLdQ_deqP
  reg coreFix_memExe_memRespLdQ_deqP;
  wire coreFix_memExe_memRespLdQ_deqP$D_IN, coreFix_memExe_memRespLdQ_deqP$EN;

  // register coreFix_memExe_memRespLdQ_deqReq_rl
  reg coreFix_memExe_memRespLdQ_deqReq_rl;
  wire coreFix_memExe_memRespLdQ_deqReq_rl$D_IN,
       coreFix_memExe_memRespLdQ_deqReq_rl$EN;

  // register coreFix_memExe_memRespLdQ_empty
  reg coreFix_memExe_memRespLdQ_empty;
  wire coreFix_memExe_memRespLdQ_empty$D_IN,
       coreFix_memExe_memRespLdQ_empty$EN;

  // register coreFix_memExe_memRespLdQ_enqP
  reg coreFix_memExe_memRespLdQ_enqP;
  wire coreFix_memExe_memRespLdQ_enqP$D_IN, coreFix_memExe_memRespLdQ_enqP$EN;

  // register coreFix_memExe_memRespLdQ_enqReq_rl
  reg [69 : 0] coreFix_memExe_memRespLdQ_enqReq_rl;
  wire [69 : 0] coreFix_memExe_memRespLdQ_enqReq_rl$D_IN;
  wire coreFix_memExe_memRespLdQ_enqReq_rl$EN;

  // register coreFix_memExe_memRespLdQ_full
  reg coreFix_memExe_memRespLdQ_full;
  wire coreFix_memExe_memRespLdQ_full$D_IN, coreFix_memExe_memRespLdQ_full$EN;

  // register coreFix_memExe_reqLdQ_data_0_rl
  reg [68 : 0] coreFix_memExe_reqLdQ_data_0_rl;
  wire [68 : 0] coreFix_memExe_reqLdQ_data_0_rl$D_IN;
  wire coreFix_memExe_reqLdQ_data_0_rl$EN;

  // register coreFix_memExe_reqLdQ_empty_rl
  reg coreFix_memExe_reqLdQ_empty_rl;
  wire coreFix_memExe_reqLdQ_empty_rl$D_IN, coreFix_memExe_reqLdQ_empty_rl$EN;

  // register coreFix_memExe_reqLdQ_full_rl
  reg coreFix_memExe_reqLdQ_full_rl;
  wire coreFix_memExe_reqLdQ_full_rl$D_IN, coreFix_memExe_reqLdQ_full_rl$EN;

  // register coreFix_memExe_reqLrScAmoQ_data_0_rl
  reg [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_rl;
  wire [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN;
  wire coreFix_memExe_reqLrScAmoQ_data_0_rl$EN;

  // register coreFix_memExe_reqLrScAmoQ_empty_rl
  reg coreFix_memExe_reqLrScAmoQ_empty_rl;
  wire coreFix_memExe_reqLrScAmoQ_empty_rl$D_IN,
       coreFix_memExe_reqLrScAmoQ_empty_rl$EN;

  // register coreFix_memExe_reqLrScAmoQ_full_rl
  reg coreFix_memExe_reqLrScAmoQ_full_rl;
  wire coreFix_memExe_reqLrScAmoQ_full_rl$D_IN,
       coreFix_memExe_reqLrScAmoQ_full_rl$EN;

  // register coreFix_memExe_reqStQ_data_0_rl
  reg [65 : 0] coreFix_memExe_reqStQ_data_0_rl;
  wire [65 : 0] coreFix_memExe_reqStQ_data_0_rl$D_IN;
  wire coreFix_memExe_reqStQ_data_0_rl$EN;

  // register coreFix_memExe_reqStQ_empty_rl
  reg coreFix_memExe_reqStQ_empty_rl;
  wire coreFix_memExe_reqStQ_empty_rl$D_IN, coreFix_memExe_reqStQ_empty_rl$EN;

  // register coreFix_memExe_reqStQ_full_rl
  reg coreFix_memExe_reqStQ_full_rl;
  wire coreFix_memExe_reqStQ_full_rl$D_IN, coreFix_memExe_reqStQ_full_rl$EN;

  // register coreFix_memExe_respLrScAmoQ_clearReq_rl
  reg coreFix_memExe_respLrScAmoQ_clearReq_rl;
  wire coreFix_memExe_respLrScAmoQ_clearReq_rl$D_IN,
       coreFix_memExe_respLrScAmoQ_clearReq_rl$EN;

  // register coreFix_memExe_respLrScAmoQ_data_0
  reg [63 : 0] coreFix_memExe_respLrScAmoQ_data_0;
  wire [63 : 0] coreFix_memExe_respLrScAmoQ_data_0$D_IN;
  wire coreFix_memExe_respLrScAmoQ_data_0$EN;

  // register coreFix_memExe_respLrScAmoQ_deqReq_rl
  reg coreFix_memExe_respLrScAmoQ_deqReq_rl;
  wire coreFix_memExe_respLrScAmoQ_deqReq_rl$D_IN,
       coreFix_memExe_respLrScAmoQ_deqReq_rl$EN;

  // register coreFix_memExe_respLrScAmoQ_empty
  reg coreFix_memExe_respLrScAmoQ_empty;
  wire coreFix_memExe_respLrScAmoQ_empty$D_IN,
       coreFix_memExe_respLrScAmoQ_empty$EN;

  // register coreFix_memExe_respLrScAmoQ_enqReq_rl
  reg [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_rl;
  wire [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN;
  wire coreFix_memExe_respLrScAmoQ_enqReq_rl$EN;

  // register coreFix_memExe_respLrScAmoQ_full
  reg coreFix_memExe_respLrScAmoQ_full;
  wire coreFix_memExe_respLrScAmoQ_full$D_IN,
       coreFix_memExe_respLrScAmoQ_full$EN;

  // register coreFix_memExe_waitLrScAmoMMIOResp
  reg [2 : 0] coreFix_memExe_waitLrScAmoMMIOResp;
  reg [2 : 0] coreFix_memExe_waitLrScAmoMMIOResp$D_IN;
  wire coreFix_memExe_waitLrScAmoMMIOResp$EN;

  // register csrInstOrInterruptInflight_rl
  reg csrInstOrInterruptInflight_rl;
  wire csrInstOrInterruptInflight_rl$D_IN, csrInstOrInterruptInflight_rl$EN;

  // register csrf_external_int_en_vec_0
  reg csrf_external_int_en_vec_0;
  wire csrf_external_int_en_vec_0$D_IN, csrf_external_int_en_vec_0$EN;

  // register csrf_external_int_en_vec_1
  reg csrf_external_int_en_vec_1;
  wire csrf_external_int_en_vec_1$D_IN, csrf_external_int_en_vec_1$EN;

  // register csrf_external_int_en_vec_3
  reg csrf_external_int_en_vec_3;
  wire csrf_external_int_en_vec_3$D_IN, csrf_external_int_en_vec_3$EN;

  // register csrf_external_int_pend_vec_0
  reg csrf_external_int_pend_vec_0;
  wire csrf_external_int_pend_vec_0$D_IN, csrf_external_int_pend_vec_0$EN;

  // register csrf_external_int_pend_vec_1
  reg csrf_external_int_pend_vec_1;
  wire csrf_external_int_pend_vec_1$D_IN, csrf_external_int_pend_vec_1$EN;

  // register csrf_external_int_pend_vec_3
  reg csrf_external_int_pend_vec_3;
  wire csrf_external_int_pend_vec_3$D_IN, csrf_external_int_pend_vec_3$EN;

  // register csrf_fflags_reg
  reg [4 : 0] csrf_fflags_reg;
  wire [4 : 0] csrf_fflags_reg$D_IN;
  wire csrf_fflags_reg$EN;

  // register csrf_frm_reg
  reg [2 : 0] csrf_frm_reg;
  wire [2 : 0] csrf_frm_reg$D_IN;
  wire csrf_frm_reg$EN;

  // register csrf_fs_reg
  reg [1 : 0] csrf_fs_reg;
  wire [1 : 0] csrf_fs_reg$D_IN;
  wire csrf_fs_reg$EN;

  // register csrf_ie_vec_0
  reg csrf_ie_vec_0;
  wire csrf_ie_vec_0$D_IN, csrf_ie_vec_0$EN;

  // register csrf_ie_vec_1
  reg csrf_ie_vec_1;
  wire csrf_ie_vec_1$D_IN, csrf_ie_vec_1$EN;

  // register csrf_ie_vec_3
  reg csrf_ie_vec_3;
  wire csrf_ie_vec_3$D_IN, csrf_ie_vec_3$EN;

  // register csrf_mcause_code_reg
  reg [3 : 0] csrf_mcause_code_reg;
  wire [3 : 0] csrf_mcause_code_reg$D_IN;
  wire csrf_mcause_code_reg$EN;

  // register csrf_mcause_interrupt_reg
  reg csrf_mcause_interrupt_reg;
  wire csrf_mcause_interrupt_reg$D_IN, csrf_mcause_interrupt_reg$EN;

  // register csrf_mcounteren_cy_reg
  reg csrf_mcounteren_cy_reg;
  wire csrf_mcounteren_cy_reg$D_IN, csrf_mcounteren_cy_reg$EN;

  // register csrf_mcounteren_ir_reg
  reg csrf_mcounteren_ir_reg;
  wire csrf_mcounteren_ir_reg$D_IN, csrf_mcounteren_ir_reg$EN;

  // register csrf_mcounteren_tm_reg
  reg csrf_mcounteren_tm_reg;
  wire csrf_mcounteren_tm_reg$D_IN, csrf_mcounteren_tm_reg$EN;

  // register csrf_mcycle_ehr_data_rl
  reg [63 : 0] csrf_mcycle_ehr_data_rl;
  wire [63 : 0] csrf_mcycle_ehr_data_rl$D_IN;
  wire csrf_mcycle_ehr_data_rl$EN;

  // register csrf_medeleg_13_11_reg
  reg [2 : 0] csrf_medeleg_13_11_reg;
  wire [2 : 0] csrf_medeleg_13_11_reg$D_IN;
  wire csrf_medeleg_13_11_reg$EN;

  // register csrf_medeleg_15_reg
  reg csrf_medeleg_15_reg;
  wire csrf_medeleg_15_reg$D_IN, csrf_medeleg_15_reg$EN;

  // register csrf_medeleg_9_0_reg
  reg [9 : 0] csrf_medeleg_9_0_reg;
  wire [9 : 0] csrf_medeleg_9_0_reg$D_IN;
  wire csrf_medeleg_9_0_reg$EN;

  // register csrf_mepc_csr
  reg [63 : 0] csrf_mepc_csr;
  wire [63 : 0] csrf_mepc_csr$D_IN;
  wire csrf_mepc_csr$EN;

  // register csrf_mideleg_11_reg
  reg csrf_mideleg_11_reg;
  wire csrf_mideleg_11_reg$D_IN, csrf_mideleg_11_reg$EN;

  // register csrf_mideleg_1_0_reg
  reg [1 : 0] csrf_mideleg_1_0_reg;
  wire [1 : 0] csrf_mideleg_1_0_reg$D_IN;
  wire csrf_mideleg_1_0_reg$EN;

  // register csrf_mideleg_5_3_reg
  reg [2 : 0] csrf_mideleg_5_3_reg;
  wire [2 : 0] csrf_mideleg_5_3_reg$D_IN;
  wire csrf_mideleg_5_3_reg$EN;

  // register csrf_mideleg_9_7_reg
  reg [2 : 0] csrf_mideleg_9_7_reg;
  wire [2 : 0] csrf_mideleg_9_7_reg$D_IN;
  wire csrf_mideleg_9_7_reg$EN;

  // register csrf_minstret_ehr_data_rl
  reg [63 : 0] csrf_minstret_ehr_data_rl;
  wire [63 : 0] csrf_minstret_ehr_data_rl$D_IN;
  wire csrf_minstret_ehr_data_rl$EN;

  // register csrf_mpp_reg
  reg [1 : 0] csrf_mpp_reg;
  wire [1 : 0] csrf_mpp_reg$D_IN;
  wire csrf_mpp_reg$EN;

  // register csrf_mprv_reg
  reg csrf_mprv_reg;
  wire csrf_mprv_reg$D_IN, csrf_mprv_reg$EN;

  // register csrf_mscratch_csr
  reg [63 : 0] csrf_mscratch_csr;
  wire [63 : 0] csrf_mscratch_csr$D_IN;
  wire csrf_mscratch_csr$EN;

  // register csrf_mtval_csr
  reg [63 : 0] csrf_mtval_csr;
  wire [63 : 0] csrf_mtval_csr$D_IN;
  wire csrf_mtval_csr$EN;

  // register csrf_mtvec_base_hi_reg
  reg [61 : 0] csrf_mtvec_base_hi_reg;
  wire [61 : 0] csrf_mtvec_base_hi_reg$D_IN;
  wire csrf_mtvec_base_hi_reg$EN;

  // register csrf_mtvec_mode_low_reg
  reg csrf_mtvec_mode_low_reg;
  wire csrf_mtvec_mode_low_reg$D_IN, csrf_mtvec_mode_low_reg$EN;

  // register csrf_mxr_reg
  reg csrf_mxr_reg;
  wire csrf_mxr_reg$D_IN, csrf_mxr_reg$EN;

  // register csrf_ppn_reg
  reg [43 : 0] csrf_ppn_reg;
  wire [43 : 0] csrf_ppn_reg$D_IN;
  wire csrf_ppn_reg$EN;

  // register csrf_prev_ie_vec_0
  reg csrf_prev_ie_vec_0;
  wire csrf_prev_ie_vec_0$D_IN, csrf_prev_ie_vec_0$EN;

  // register csrf_prev_ie_vec_1
  reg csrf_prev_ie_vec_1;
  wire csrf_prev_ie_vec_1$D_IN, csrf_prev_ie_vec_1$EN;

  // register csrf_prev_ie_vec_3
  reg csrf_prev_ie_vec_3;
  wire csrf_prev_ie_vec_3$D_IN, csrf_prev_ie_vec_3$EN;

  // register csrf_prv_reg
  reg [1 : 0] csrf_prv_reg;
  wire [1 : 0] csrf_prv_reg$D_IN;
  wire csrf_prv_reg$EN;

  // register csrf_rg_tdata1_data
  reg [58 : 0] csrf_rg_tdata1_data;
  wire [58 : 0] csrf_rg_tdata1_data$D_IN;
  wire csrf_rg_tdata1_data$EN;

  // register csrf_rg_tdata1_dmode
  reg csrf_rg_tdata1_dmode;
  wire csrf_rg_tdata1_dmode$D_IN, csrf_rg_tdata1_dmode$EN;

  // register csrf_rg_tdata2
  reg [63 : 0] csrf_rg_tdata2;
  wire [63 : 0] csrf_rg_tdata2$D_IN;
  wire csrf_rg_tdata2$EN;

  // register csrf_rg_tdata3
  reg [63 : 0] csrf_rg_tdata3;
  wire [63 : 0] csrf_rg_tdata3$D_IN;
  wire csrf_rg_tdata3$EN;

  // register csrf_rg_tselect
  reg [63 : 0] csrf_rg_tselect;
  wire [63 : 0] csrf_rg_tselect$D_IN;
  wire csrf_rg_tselect$EN;

  // register csrf_scause_code_reg
  reg [3 : 0] csrf_scause_code_reg;
  wire [3 : 0] csrf_scause_code_reg$D_IN;
  wire csrf_scause_code_reg$EN;

  // register csrf_scause_interrupt_reg
  reg csrf_scause_interrupt_reg;
  wire csrf_scause_interrupt_reg$D_IN, csrf_scause_interrupt_reg$EN;

  // register csrf_scounteren_cy_reg
  reg csrf_scounteren_cy_reg;
  wire csrf_scounteren_cy_reg$D_IN, csrf_scounteren_cy_reg$EN;

  // register csrf_scounteren_ir_reg
  reg csrf_scounteren_ir_reg;
  wire csrf_scounteren_ir_reg$D_IN, csrf_scounteren_ir_reg$EN;

  // register csrf_scounteren_tm_reg
  reg csrf_scounteren_tm_reg;
  wire csrf_scounteren_tm_reg$D_IN, csrf_scounteren_tm_reg$EN;

  // register csrf_sepc_csr
  reg [63 : 0] csrf_sepc_csr;
  wire [63 : 0] csrf_sepc_csr$D_IN;
  wire csrf_sepc_csr$EN;

  // register csrf_software_int_en_vec_0
  reg csrf_software_int_en_vec_0;
  wire csrf_software_int_en_vec_0$D_IN, csrf_software_int_en_vec_0$EN;

  // register csrf_software_int_en_vec_1
  reg csrf_software_int_en_vec_1;
  wire csrf_software_int_en_vec_1$D_IN, csrf_software_int_en_vec_1$EN;

  // register csrf_software_int_en_vec_3
  reg csrf_software_int_en_vec_3;
  wire csrf_software_int_en_vec_3$D_IN, csrf_software_int_en_vec_3$EN;

  // register csrf_software_int_pend_vec_0
  reg csrf_software_int_pend_vec_0;
  wire csrf_software_int_pend_vec_0$D_IN, csrf_software_int_pend_vec_0$EN;

  // register csrf_software_int_pend_vec_1
  reg csrf_software_int_pend_vec_1;
  wire csrf_software_int_pend_vec_1$D_IN, csrf_software_int_pend_vec_1$EN;

  // register csrf_software_int_pend_vec_3
  reg csrf_software_int_pend_vec_3;
  wire csrf_software_int_pend_vec_3$D_IN, csrf_software_int_pend_vec_3$EN;

  // register csrf_spp_reg
  reg csrf_spp_reg;
  wire csrf_spp_reg$D_IN, csrf_spp_reg$EN;

  // register csrf_sscratch_csr
  reg [63 : 0] csrf_sscratch_csr;
  wire [63 : 0] csrf_sscratch_csr$D_IN;
  wire csrf_sscratch_csr$EN;

  // register csrf_stats_module_doStats
  reg csrf_stats_module_doStats;
  wire csrf_stats_module_doStats$D_IN, csrf_stats_module_doStats$EN;

  // register csrf_stval_csr
  reg [63 : 0] csrf_stval_csr;
  wire [63 : 0] csrf_stval_csr$D_IN;
  wire csrf_stval_csr$EN;

  // register csrf_stvec_base_hi_reg
  reg [61 : 0] csrf_stvec_base_hi_reg;
  wire [61 : 0] csrf_stvec_base_hi_reg$D_IN;
  wire csrf_stvec_base_hi_reg$EN;

  // register csrf_stvec_mode_low_reg
  reg csrf_stvec_mode_low_reg;
  wire csrf_stvec_mode_low_reg$D_IN, csrf_stvec_mode_low_reg$EN;

  // register csrf_sum_reg
  reg csrf_sum_reg;
  wire csrf_sum_reg$D_IN, csrf_sum_reg$EN;

  // register csrf_time_reg
  reg [63 : 0] csrf_time_reg;
  wire [63 : 0] csrf_time_reg$D_IN;
  wire csrf_time_reg$EN;

  // register csrf_timer_int_en_vec_0
  reg csrf_timer_int_en_vec_0;
  wire csrf_timer_int_en_vec_0$D_IN, csrf_timer_int_en_vec_0$EN;

  // register csrf_timer_int_en_vec_1
  reg csrf_timer_int_en_vec_1;
  wire csrf_timer_int_en_vec_1$D_IN, csrf_timer_int_en_vec_1$EN;

  // register csrf_timer_int_en_vec_3
  reg csrf_timer_int_en_vec_3;
  wire csrf_timer_int_en_vec_3$D_IN, csrf_timer_int_en_vec_3$EN;

  // register csrf_timer_int_pend_vec_0
  reg csrf_timer_int_pend_vec_0;
  wire csrf_timer_int_pend_vec_0$D_IN, csrf_timer_int_pend_vec_0$EN;

  // register csrf_timer_int_pend_vec_1
  reg csrf_timer_int_pend_vec_1;
  wire csrf_timer_int_pend_vec_1$D_IN, csrf_timer_int_pend_vec_1$EN;

  // register csrf_timer_int_pend_vec_3
  reg csrf_timer_int_pend_vec_3;
  wire csrf_timer_int_pend_vec_3$D_IN, csrf_timer_int_pend_vec_3$EN;

  // register csrf_tsr_reg
  reg csrf_tsr_reg;
  wire csrf_tsr_reg$D_IN, csrf_tsr_reg$EN;

  // register csrf_tvm_reg
  reg csrf_tvm_reg;
  wire csrf_tvm_reg$D_IN, csrf_tvm_reg$EN;

  // register csrf_tw_reg
  reg csrf_tw_reg;
  wire csrf_tw_reg$D_IN, csrf_tw_reg$EN;

  // register csrf_vm_mode_sv39_reg
  reg csrf_vm_mode_sv39_reg;
  wire csrf_vm_mode_sv39_reg$D_IN, csrf_vm_mode_sv39_reg$EN;

  // register flush_reservation
  reg flush_reservation;
  wire flush_reservation$D_IN, flush_reservation$EN;

  // register flush_tlbs
  reg flush_tlbs;
  wire flush_tlbs$D_IN, flush_tlbs$EN;

  // register mmio_cRqQ_clearReq_rl
  reg mmio_cRqQ_clearReq_rl;
  wire mmio_cRqQ_clearReq_rl$D_IN, mmio_cRqQ_clearReq_rl$EN;

  // register mmio_cRqQ_data_0
  reg [141 : 0] mmio_cRqQ_data_0;
  wire [141 : 0] mmio_cRqQ_data_0$D_IN;
  wire mmio_cRqQ_data_0$EN;

  // register mmio_cRqQ_deqReq_rl
  reg mmio_cRqQ_deqReq_rl;
  wire mmio_cRqQ_deqReq_rl$D_IN, mmio_cRqQ_deqReq_rl$EN;

  // register mmio_cRqQ_empty
  reg mmio_cRqQ_empty;
  wire mmio_cRqQ_empty$D_IN, mmio_cRqQ_empty$EN;

  // register mmio_cRqQ_enqReq_rl
  reg [142 : 0] mmio_cRqQ_enqReq_rl;
  wire [142 : 0] mmio_cRqQ_enqReq_rl$D_IN;
  wire mmio_cRqQ_enqReq_rl$EN;

  // register mmio_cRqQ_full
  reg mmio_cRqQ_full;
  wire mmio_cRqQ_full$D_IN, mmio_cRqQ_full$EN;

  // register mmio_cRsQ_clearReq_rl
  reg mmio_cRsQ_clearReq_rl;
  wire mmio_cRsQ_clearReq_rl$D_IN, mmio_cRsQ_clearReq_rl$EN;

  // register mmio_cRsQ_data_0
  reg mmio_cRsQ_data_0;
  wire mmio_cRsQ_data_0$D_IN, mmio_cRsQ_data_0$EN;

  // register mmio_cRsQ_deqReq_rl
  reg mmio_cRsQ_deqReq_rl;
  wire mmio_cRsQ_deqReq_rl$D_IN, mmio_cRsQ_deqReq_rl$EN;

  // register mmio_cRsQ_empty
  reg mmio_cRsQ_empty;
  wire mmio_cRsQ_empty$D_IN, mmio_cRsQ_empty$EN;

  // register mmio_cRsQ_enqReq_rl
  reg [1 : 0] mmio_cRsQ_enqReq_rl;
  wire [1 : 0] mmio_cRsQ_enqReq_rl$D_IN;
  wire mmio_cRsQ_enqReq_rl$EN;

  // register mmio_cRsQ_full
  reg mmio_cRsQ_full;
  wire mmio_cRsQ_full$D_IN, mmio_cRsQ_full$EN;

  // register mmio_dataPendQ_clearReq_rl
  reg mmio_dataPendQ_clearReq_rl;
  wire mmio_dataPendQ_clearReq_rl$D_IN, mmio_dataPendQ_clearReq_rl$EN;

  // register mmio_dataPendQ_deqReq_rl
  reg mmio_dataPendQ_deqReq_rl;
  wire mmio_dataPendQ_deqReq_rl$D_IN, mmio_dataPendQ_deqReq_rl$EN;

  // register mmio_dataPendQ_empty
  reg mmio_dataPendQ_empty;
  wire mmio_dataPendQ_empty$D_IN, mmio_dataPendQ_empty$EN;

  // register mmio_dataPendQ_enqReq_rl
  reg mmio_dataPendQ_enqReq_rl;
  wire mmio_dataPendQ_enqReq_rl$D_IN, mmio_dataPendQ_enqReq_rl$EN;

  // register mmio_dataPendQ_full
  reg mmio_dataPendQ_full;
  wire mmio_dataPendQ_full$D_IN, mmio_dataPendQ_full$EN;

  // register mmio_dataReqQ_clearReq_rl
  reg mmio_dataReqQ_clearReq_rl;
  wire mmio_dataReqQ_clearReq_rl$D_IN, mmio_dataReqQ_clearReq_rl$EN;

  // register mmio_dataReqQ_data_0
  reg [141 : 0] mmio_dataReqQ_data_0;
  wire [141 : 0] mmio_dataReqQ_data_0$D_IN;
  wire mmio_dataReqQ_data_0$EN;

  // register mmio_dataReqQ_deqReq_rl
  reg mmio_dataReqQ_deqReq_rl;
  wire mmio_dataReqQ_deqReq_rl$D_IN, mmio_dataReqQ_deqReq_rl$EN;

  // register mmio_dataReqQ_empty
  reg mmio_dataReqQ_empty;
  wire mmio_dataReqQ_empty$D_IN, mmio_dataReqQ_empty$EN;

  // register mmio_dataReqQ_enqReq_rl
  reg [142 : 0] mmio_dataReqQ_enqReq_rl;
  wire [142 : 0] mmio_dataReqQ_enqReq_rl$D_IN;
  wire mmio_dataReqQ_enqReq_rl$EN;

  // register mmio_dataReqQ_full
  reg mmio_dataReqQ_full;
  wire mmio_dataReqQ_full$D_IN, mmio_dataReqQ_full$EN;

  // register mmio_dataRespQ_clearReq_rl
  reg mmio_dataRespQ_clearReq_rl;
  wire mmio_dataRespQ_clearReq_rl$D_IN, mmio_dataRespQ_clearReq_rl$EN;

  // register mmio_dataRespQ_data_0
  reg [64 : 0] mmio_dataRespQ_data_0;
  wire [64 : 0] mmio_dataRespQ_data_0$D_IN;
  wire mmio_dataRespQ_data_0$EN;

  // register mmio_dataRespQ_deqReq_rl
  reg mmio_dataRespQ_deqReq_rl;
  wire mmio_dataRespQ_deqReq_rl$D_IN, mmio_dataRespQ_deqReq_rl$EN;

  // register mmio_dataRespQ_empty
  reg mmio_dataRespQ_empty;
  wire mmio_dataRespQ_empty$D_IN, mmio_dataRespQ_empty$EN;

  // register mmio_dataRespQ_enqReq_rl
  reg [65 : 0] mmio_dataRespQ_enqReq_rl;
  wire [65 : 0] mmio_dataRespQ_enqReq_rl$D_IN;
  wire mmio_dataRespQ_enqReq_rl$EN;

  // register mmio_dataRespQ_full
  reg mmio_dataRespQ_full;
  wire mmio_dataRespQ_full$D_IN, mmio_dataRespQ_full$EN;

  // register mmio_fromHostAddr
  reg [60 : 0] mmio_fromHostAddr;
  wire [60 : 0] mmio_fromHostAddr$D_IN;
  wire mmio_fromHostAddr$EN;

  // register mmio_pRqQ_clearReq_rl
  reg mmio_pRqQ_clearReq_rl;
  wire mmio_pRqQ_clearReq_rl$D_IN, mmio_pRqQ_clearReq_rl$EN;

  // register mmio_pRqQ_data_0
  reg [38 : 0] mmio_pRqQ_data_0;
  wire [38 : 0] mmio_pRqQ_data_0$D_IN;
  wire mmio_pRqQ_data_0$EN;

  // register mmio_pRqQ_deqReq_rl
  reg mmio_pRqQ_deqReq_rl;
  wire mmio_pRqQ_deqReq_rl$D_IN, mmio_pRqQ_deqReq_rl$EN;

  // register mmio_pRqQ_empty
  reg mmio_pRqQ_empty;
  wire mmio_pRqQ_empty$D_IN, mmio_pRqQ_empty$EN;

  // register mmio_pRqQ_enqReq_rl
  reg [39 : 0] mmio_pRqQ_enqReq_rl;
  wire [39 : 0] mmio_pRqQ_enqReq_rl$D_IN;
  wire mmio_pRqQ_enqReq_rl$EN;

  // register mmio_pRqQ_full
  reg mmio_pRqQ_full;
  wire mmio_pRqQ_full$D_IN, mmio_pRqQ_full$EN;

  // register mmio_pRsQ_clearReq_rl
  reg mmio_pRsQ_clearReq_rl;
  wire mmio_pRsQ_clearReq_rl$D_IN, mmio_pRsQ_clearReq_rl$EN;

  // register mmio_pRsQ_data_0
  reg [66 : 0] mmio_pRsQ_data_0;
  wire [66 : 0] mmio_pRsQ_data_0$D_IN;
  wire mmio_pRsQ_data_0$EN;

  // register mmio_pRsQ_deqReq_rl
  reg mmio_pRsQ_deqReq_rl;
  wire mmio_pRsQ_deqReq_rl$D_IN, mmio_pRsQ_deqReq_rl$EN;

  // register mmio_pRsQ_empty
  reg mmio_pRsQ_empty;
  wire mmio_pRsQ_empty$D_IN, mmio_pRsQ_empty$EN;

  // register mmio_pRsQ_enqReq_rl
  reg [67 : 0] mmio_pRsQ_enqReq_rl;
  wire [67 : 0] mmio_pRsQ_enqReq_rl$D_IN;
  wire mmio_pRsQ_enqReq_rl$EN;

  // register mmio_pRsQ_full
  reg mmio_pRsQ_full;
  wire mmio_pRsQ_full$D_IN, mmio_pRsQ_full$EN;

  // register mmio_toHostAddr
  reg [60 : 0] mmio_toHostAddr;
  wire [60 : 0] mmio_toHostAddr$D_IN;
  wire mmio_toHostAddr$EN;

  // register outOfReset
  reg outOfReset;
  wire outOfReset$D_IN, outOfReset$EN;

  // register started
  reg started;
  wire started$D_IN, started$EN;

  // register update_vm_info
  reg update_vm_info;
  wire update_vm_info$D_IN, update_vm_info$EN;

  // ports of submodule coreFix_aluExe_0_dispToRegQ
  reg [3 : 0] coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [157 : 0] coreFix_aluExe_0_dispToRegQ$enq_x,
		 coreFix_aluExe_0_dispToRegQ$first;
  wire [11 : 0] coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask;
  wire coreFix_aluExe_0_dispToRegQ$EN_deq,
       coreFix_aluExe_0_dispToRegQ$EN_enq,
       coreFix_aluExe_0_dispToRegQ$EN_specUpdate_correctSpeculation,
       coreFix_aluExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation,
       coreFix_aluExe_0_dispToRegQ$RDY_deq,
       coreFix_aluExe_0_dispToRegQ$RDY_enq,
       coreFix_aluExe_0_dispToRegQ$RDY_first,
       coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_aluExe_0_exeToFinQ
  reg [3 : 0] coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [326 : 0] coreFix_aluExe_0_exeToFinQ$enq_x,
		 coreFix_aluExe_0_exeToFinQ$first;
  wire [11 : 0] coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask;
  wire coreFix_aluExe_0_exeToFinQ$EN_deq,
       coreFix_aluExe_0_exeToFinQ$EN_enq,
       coreFix_aluExe_0_exeToFinQ$EN_specUpdate_correctSpeculation,
       coreFix_aluExe_0_exeToFinQ$EN_specUpdate_incorrectSpeculation,
       coreFix_aluExe_0_exeToFinQ$RDY_deq,
       coreFix_aluExe_0_exeToFinQ$RDY_enq,
       coreFix_aluExe_0_exeToFinQ$RDY_first,
       coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_aluExe_0_regToExeQ
  reg [3 : 0] coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [421 : 0] coreFix_aluExe_0_regToExeQ$enq_x,
		 coreFix_aluExe_0_regToExeQ$first;
  wire [11 : 0] coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask;
  wire coreFix_aluExe_0_regToExeQ$EN_deq,
       coreFix_aluExe_0_regToExeQ$EN_enq,
       coreFix_aluExe_0_regToExeQ$EN_specUpdate_correctSpeculation,
       coreFix_aluExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation,
       coreFix_aluExe_0_regToExeQ$RDY_deq,
       coreFix_aluExe_0_regToExeQ$RDY_enq,
       coreFix_aluExe_0_regToExeQ$RDY_first,
       coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_aluExe_0_rsAlu
  reg [7 : 0] coreFix_aluExe_0_rsAlu$setRegReady_2_put,
	      coreFix_aluExe_0_rsAlu$setRegReady_4_put;
  reg [3 : 0] coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag;
  wire [161 : 0] coreFix_aluExe_0_rsAlu$dispatchData,
		 coreFix_aluExe_0_rsAlu$enq_x;
  wire [11 : 0] coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask;
  wire [7 : 0] coreFix_aluExe_0_rsAlu$setRegReady_0_put,
	       coreFix_aluExe_0_rsAlu$setRegReady_1_put,
	       coreFix_aluExe_0_rsAlu$setRegReady_3_put;
  wire [5 : 0] coreFix_aluExe_0_rsAlu$setRobEnqTime_t;
  wire [4 : 0] coreFix_aluExe_0_rsAlu$approximateCount;
  wire coreFix_aluExe_0_rsAlu$EN_doDispatch,
       coreFix_aluExe_0_rsAlu$EN_enq,
       coreFix_aluExe_0_rsAlu$EN_setRegReady_0_put,
       coreFix_aluExe_0_rsAlu$EN_setRegReady_1_put,
       coreFix_aluExe_0_rsAlu$EN_setRegReady_2_put,
       coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put,
       coreFix_aluExe_0_rsAlu$EN_setRegReady_4_put,
       coreFix_aluExe_0_rsAlu$EN_setRobEnqTime,
       coreFix_aluExe_0_rsAlu$EN_specUpdate_correctSpeculation,
       coreFix_aluExe_0_rsAlu$EN_specUpdate_incorrectSpeculation,
       coreFix_aluExe_0_rsAlu$RDY_dispatchData,
       coreFix_aluExe_0_rsAlu$RDY_doDispatch,
       coreFix_aluExe_0_rsAlu$RDY_enq,
       coreFix_aluExe_0_rsAlu$canEnq,
       coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_aluExe_1_dispToRegQ
  reg [3 : 0] coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [157 : 0] coreFix_aluExe_1_dispToRegQ$enq_x,
		 coreFix_aluExe_1_dispToRegQ$first;
  wire [11 : 0] coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask;
  wire coreFix_aluExe_1_dispToRegQ$EN_deq,
       coreFix_aluExe_1_dispToRegQ$EN_enq,
       coreFix_aluExe_1_dispToRegQ$EN_specUpdate_correctSpeculation,
       coreFix_aluExe_1_dispToRegQ$EN_specUpdate_incorrectSpeculation,
       coreFix_aluExe_1_dispToRegQ$RDY_deq,
       coreFix_aluExe_1_dispToRegQ$RDY_enq,
       coreFix_aluExe_1_dispToRegQ$RDY_first,
       coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_aluExe_1_exeToFinQ
  reg [3 : 0] coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [326 : 0] coreFix_aluExe_1_exeToFinQ$enq_x,
		 coreFix_aluExe_1_exeToFinQ$first;
  wire [11 : 0] coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask;
  wire coreFix_aluExe_1_exeToFinQ$EN_deq,
       coreFix_aluExe_1_exeToFinQ$EN_enq,
       coreFix_aluExe_1_exeToFinQ$EN_specUpdate_correctSpeculation,
       coreFix_aluExe_1_exeToFinQ$EN_specUpdate_incorrectSpeculation,
       coreFix_aluExe_1_exeToFinQ$RDY_deq,
       coreFix_aluExe_1_exeToFinQ$RDY_enq,
       coreFix_aluExe_1_exeToFinQ$RDY_first,
       coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_aluExe_1_regToExeQ
  reg [3 : 0] coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [421 : 0] coreFix_aluExe_1_regToExeQ$enq_x,
		 coreFix_aluExe_1_regToExeQ$first;
  wire [11 : 0] coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask;
  wire coreFix_aluExe_1_regToExeQ$EN_deq,
       coreFix_aluExe_1_regToExeQ$EN_enq,
       coreFix_aluExe_1_regToExeQ$EN_specUpdate_correctSpeculation,
       coreFix_aluExe_1_regToExeQ$EN_specUpdate_incorrectSpeculation,
       coreFix_aluExe_1_regToExeQ$RDY_deq,
       coreFix_aluExe_1_regToExeQ$RDY_enq,
       coreFix_aluExe_1_regToExeQ$RDY_first,
       coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_aluExe_1_rsAlu
  reg [7 : 0] coreFix_aluExe_1_rsAlu$setRegReady_2_put,
	      coreFix_aluExe_1_rsAlu$setRegReady_4_put;
  reg [3 : 0] coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag;
  wire [161 : 0] coreFix_aluExe_1_rsAlu$dispatchData,
		 coreFix_aluExe_1_rsAlu$enq_x;
  wire [11 : 0] coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask;
  wire [7 : 0] coreFix_aluExe_1_rsAlu$setRegReady_0_put,
	       coreFix_aluExe_1_rsAlu$setRegReady_1_put,
	       coreFix_aluExe_1_rsAlu$setRegReady_3_put;
  wire [5 : 0] coreFix_aluExe_1_rsAlu$setRobEnqTime_t;
  wire [4 : 0] coreFix_aluExe_1_rsAlu$approximateCount;
  wire coreFix_aluExe_1_rsAlu$EN_doDispatch,
       coreFix_aluExe_1_rsAlu$EN_enq,
       coreFix_aluExe_1_rsAlu$EN_setRegReady_0_put,
       coreFix_aluExe_1_rsAlu$EN_setRegReady_1_put,
       coreFix_aluExe_1_rsAlu$EN_setRegReady_2_put,
       coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put,
       coreFix_aluExe_1_rsAlu$EN_setRegReady_4_put,
       coreFix_aluExe_1_rsAlu$EN_setRobEnqTime,
       coreFix_aluExe_1_rsAlu$EN_specUpdate_correctSpeculation,
       coreFix_aluExe_1_rsAlu$EN_specUpdate_incorrectSpeculation,
       coreFix_aluExe_1_rsAlu$RDY_dispatchData,
       coreFix_aluExe_1_rsAlu$RDY_doDispatch,
       coreFix_aluExe_1_rsAlu$RDY_enq,
       coreFix_aluExe_1_rsAlu$canEnq,
       coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_fpuMulDivExe_0_dispToRegQ
  reg [3 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [77 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$enq_x,
		coreFix_fpuMulDivExe_0_dispToRegQ$first;
  wire [11 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask;
  wire coreFix_fpuMulDivExe_0_dispToRegQ$EN_deq,
       coreFix_fpuMulDivExe_0_dispToRegQ$EN_enq,
       coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_correctSpeculation,
       coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation,
       coreFix_fpuMulDivExe_0_dispToRegQ$RDY_deq,
       coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq,
       coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first,
       coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_fpuMulDivExe_0_fpuExec_divQ
  reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [42 : 0] coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x,
		coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data;
  wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask;
  wire coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_deq,
       coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_enq,
       coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_correctSpeculation,
       coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_incorrectSpeculation,
       coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq,
       coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq,
       coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_data,
       coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned,
       coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned,
       coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_fpuMulDivExe_0_fpuExec_double_div
  wire [130 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_div$request_put;
  wire [68 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get;
  wire coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_request_put,
       coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_response_get,
       coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put,
       coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get;

  // ports of submodule coreFix_fpuMulDivExe_0_fpuExec_double_fma
  wire [195 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put;
  wire [68 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get;
  wire coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put,
       coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_response_get,
       coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put,
       coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get;

  // ports of submodule coreFix_fpuMulDivExe_0_fpuExec_double_sqrt
  wire [68 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get;
  wire [66 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$request_put;
  wire coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_request_put,
       coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_response_get,
       coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put,
       coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get;

  // ports of submodule coreFix_fpuMulDivExe_0_fpuExec_fmaQ
  reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [42 : 0] coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x,
		coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data;
  wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask;
  wire coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_deq,
       coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_enq,
       coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_correctSpeculation,
       coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_incorrectSpeculation,
       coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq,
       coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq,
       coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_data,
       coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned,
       coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned,
       coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_fpuMulDivExe_0_fpuExec_simpleQ
  reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [101 : 0] coreFix_fpuMulDivExe_0_fpuExec_simpleQ$enq_x,
		 coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first;
  wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask;
  wire coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_deq,
       coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_enq,
       coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_correctSpeculation,
       coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_incorrectSpeculation,
       coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_deq,
       coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq,
       coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_first,
       coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_fpuMulDivExe_0_fpuExec_sqrtQ
  reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [42 : 0] coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x,
		coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data;
  wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask;
  wire coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_deq,
       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_enq,
       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_correctSpeculation,
       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_incorrectSpeculation,
       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq,
       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq,
       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_data,
       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned,
       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned,
       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divQ
  reg [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [35 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divQ$enq_x,
		coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data;
  wire [11 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask;
  wire coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_deq,
       coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_enq,
       coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_correctSpeculation,
       coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_incorrectSpeculation,
       coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq,
       coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq,
       coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_data,
       coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned,
       coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned,
       coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ
  wire [139 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_IN,
		 coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT;
  wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$CLR,
       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$DEQ,
       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$EMPTY_N,
       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$ENQ,
       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$FULL_N;

  // ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ
  wire [63 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_IN,
		coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT;
  wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$CLR,
       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$DEQ,
       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$EMPTY_N,
       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$ENQ,
       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$FULL_N;

  // ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ
  wire [203 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_IN,
		 coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT;
  wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$CLR,
       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$DEQ,
       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$EMPTY_N,
       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$ENQ,
       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$FULL_N;

  // ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulQ
  reg [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [35 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulQ$enq_x,
		coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data;
  wire [11 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask;
  wire coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_deq,
       coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_enq,
       coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_correctSpeculation,
       coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_incorrectSpeculation,
       coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq,
       coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq,
       coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_data,
       coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned,
       coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned,
       coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ
  reg [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN;
  wire [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT;
  wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$CLR,
       coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$DEQ,
       coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N,
       coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$ENQ;

  // ports of submodule coreFix_fpuMulDivExe_0_regToExeQ
  reg [3 : 0] coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [245 : 0] coreFix_fpuMulDivExe_0_regToExeQ$enq_x,
		 coreFix_fpuMulDivExe_0_regToExeQ$first;
  wire [11 : 0] coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask;
  wire coreFix_fpuMulDivExe_0_regToExeQ$EN_deq,
       coreFix_fpuMulDivExe_0_regToExeQ$EN_enq,
       coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_correctSpeculation,
       coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation,
       coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq,
       coreFix_fpuMulDivExe_0_regToExeQ$RDY_enq,
       coreFix_fpuMulDivExe_0_regToExeQ$RDY_first,
       coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv
  reg [7 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put,
	      coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put;
  reg [3 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag;
  wire [86 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData,
		coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x;
  wire [11 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask;
  wire [7 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_0_put,
	       coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_1_put,
	       coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_3_put;
  wire [5 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t;
  wire coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_0_put,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_1_put,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_2_put,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_4_put,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_correctSpeculation,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_incorrectSpeculation,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr
  reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n;
  wire [512 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d,
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData;
  wire [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r,
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq,
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq,
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq,
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq;
  wire [63 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain_addr;
  wire [57 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot,
		coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot,
		coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot,
		coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot,
		coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_slot;
  wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_succ;
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_state,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState_n,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_n;
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_cRqTransfer_getEmptyEntryInit,
       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_releaseEntry,
       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setData,
       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setStateSlot,
       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setSucc,
       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_sendRsToP_cRq_setWaitSt_setSlot_clearData,
       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_stuck_get,
       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_cRqTransfer_getEmptyEntryInit,
       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2
  wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2
  wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN,
       coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN,
       coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr
  wire [512 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d,
		 coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData;
  wire [65 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r,
		coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq,
		coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq;
  wire [1 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit,
	       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n,
	       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n,
	       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_releaseEntry_n,
	       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_n,
	       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData_n,
	       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq_n,
	       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_releaseEntry_n;
  wire coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_getEmptyEntryInit,
       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_releaseEntry,
       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_setDone_setData,
       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_sendRsToP_pRq_releaseEntry,
       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_stuck_get,
       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit,
       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_pipelineResp_releaseEntry,
       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_pipeline
  reg [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r;
  reg [569 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam;
  reg [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq;
  reg coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep;
  wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$first;
  wire coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_deqWrite,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_send,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2
  wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_IN,
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$CLR,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$DEQ,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$EMPTY_N,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$ENQ,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_IN,
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_OUT;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$CLR,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$DEQ,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$EMPTY_N,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$ENQ,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP
  wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_IN,
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_OUT;
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$CLR,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$DEQ,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$EMPTY_N,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$ENQ,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$FULL_N;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2
  wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ
  wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_IN,
	       coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT;
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$CLR,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$DEQ,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$ENQ,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2
  wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0
  wire coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1
  wire coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN,
       coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0
  wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1
  wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2
  wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN,
       coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN,
       coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0
  wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN,
       coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1
  wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN,
       coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2
  wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN,
       coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN,
       coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_dTlb
  reg [3 : 0] coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag;
  wire [174 : 0] coreFix_memExe_dTlb$procResp;
  wire [105 : 0] coreFix_memExe_dTlb$procReq_req;
  wire [82 : 0] coreFix_memExe_dTlb$toParent_ldTransRsFromP_enq_x;
  wire [48 : 0] coreFix_memExe_dTlb$updateVMInfo_vm;
  wire [28 : 0] coreFix_memExe_dTlb$toParent_rqToP_first;
  wire [11 : 0] coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask;
  wire [2 : 0] coreFix_memExe_dTlb$perf_req_r;
  wire coreFix_memExe_dTlb$EN_deqProcResp,
       coreFix_memExe_dTlb$EN_flush,
       coreFix_memExe_dTlb$EN_perf_req,
       coreFix_memExe_dTlb$EN_perf_resp,
       coreFix_memExe_dTlb$EN_perf_setStatus,
       coreFix_memExe_dTlb$EN_procReq,
       coreFix_memExe_dTlb$EN_specUpdate_correctSpeculation,
       coreFix_memExe_dTlb$EN_specUpdate_incorrectSpeculation,
       coreFix_memExe_dTlb$EN_toParent_flush_request_get,
       coreFix_memExe_dTlb$EN_toParent_flush_response_put,
       coreFix_memExe_dTlb$EN_toParent_ldTransRsFromP_enq,
       coreFix_memExe_dTlb$EN_toParent_rqToP_deq,
       coreFix_memExe_dTlb$EN_updateVMInfo,
       coreFix_memExe_dTlb$RDY_deqProcResp,
       coreFix_memExe_dTlb$RDY_flush,
       coreFix_memExe_dTlb$RDY_procReq,
       coreFix_memExe_dTlb$RDY_procResp,
       coreFix_memExe_dTlb$RDY_toParent_flush_request_get,
       coreFix_memExe_dTlb$RDY_toParent_flush_response_put,
       coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq,
       coreFix_memExe_dTlb$RDY_toParent_rqToP_deq,
       coreFix_memExe_dTlb$RDY_toParent_rqToP_first,
       coreFix_memExe_dTlb$flush_done,
       coreFix_memExe_dTlb$noPendingReq,
       coreFix_memExe_dTlb$perf_setStatus_doStats,
       coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_memExe_dispToRegQ
  reg [3 : 0] coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [97 : 0] coreFix_memExe_dispToRegQ$enq_x,
		coreFix_memExe_dispToRegQ$first;
  wire [11 : 0] coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask;
  wire coreFix_memExe_dispToRegQ$EN_deq,
       coreFix_memExe_dispToRegQ$EN_enq,
       coreFix_memExe_dispToRegQ$EN_specUpdate_correctSpeculation,
       coreFix_memExe_dispToRegQ$EN_specUpdate_incorrectSpeculation,
       coreFix_memExe_dispToRegQ$RDY_deq,
       coreFix_memExe_dispToRegQ$RDY_enq,
       coreFix_memExe_dispToRegQ$RDY_first,
       coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_memExe_forwardQ_clearReq_dummy2_0
  wire coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN,
       coreFix_memExe_forwardQ_clearReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_forwardQ_clearReq_dummy2_1
  wire coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN,
       coreFix_memExe_forwardQ_clearReq_dummy2_1$EN,
       coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_0
  wire coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN,
       coreFix_memExe_forwardQ_deqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_1
  wire coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN,
       coreFix_memExe_forwardQ_deqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_2
  wire coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN,
       coreFix_memExe_forwardQ_deqReq_dummy2_2$EN,
       coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_0
  wire coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN,
       coreFix_memExe_forwardQ_enqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_1
  wire coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN,
       coreFix_memExe_forwardQ_enqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_2
  wire coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN,
       coreFix_memExe_forwardQ_enqReq_dummy2_2$EN,
       coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_lsq
  reg [3 : 0] coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag;
  wire [170 : 0] coreFix_memExe_lsq$firstSt;
  wire [113 : 0] coreFix_memExe_lsq$firstLd;
  wire [76 : 0] coreFix_memExe_lsq$getIssueLd;
  wire [74 : 0] coreFix_memExe_lsq$issueLd;
  wire [73 : 0] coreFix_memExe_lsq$respLd;
  wire [67 : 0] coreFix_memExe_lsq$issueLd_sbRes;
  wire [63 : 0] coreFix_memExe_lsq$issueLd_paddr,
		coreFix_memExe_lsq$respLd_alignedData,
		coreFix_memExe_lsq$updateAddr_paddr,
		coreFix_memExe_lsq$updateData_d;
  wire [17 : 0] coreFix_memExe_lsq$enqLd_mem_inst,
		coreFix_memExe_lsq$enqSt_mem_inst;
  wire [11 : 0] coreFix_memExe_lsq$enqLd_inst_tag,
		coreFix_memExe_lsq$enqLd_spec_bits,
		coreFix_memExe_lsq$enqSt_inst_tag,
		coreFix_memExe_lsq$enqSt_spec_bits,
		coreFix_memExe_lsq$specUpdate_correctSpeculation_mask;
  wire [9 : 0] coreFix_memExe_lsq$getHit;
  wire [8 : 0] coreFix_memExe_lsq$enqLd_dst, coreFix_memExe_lsq$enqSt_dst;
  wire [7 : 0] coreFix_memExe_lsq$getOrigBE,
	       coreFix_memExe_lsq$issueLd_shiftedBE,
	       coreFix_memExe_lsq$updateAddr_shiftedBE;
  wire [6 : 0] coreFix_memExe_lsq$enqLdTag, coreFix_memExe_lsq$enqStTag;
  wire [5 : 0] coreFix_memExe_lsq$getHit_t,
	       coreFix_memExe_lsq$getOrigBE_t,
	       coreFix_memExe_lsq$setAtCommit_0_put,
	       coreFix_memExe_lsq$setAtCommit_1_put,
	       coreFix_memExe_lsq$updateAddr_lsqTag;
  wire [4 : 0] coreFix_memExe_lsq$issueLd_lsqTag,
	       coreFix_memExe_lsq$respLd_t,
	       coreFix_memExe_lsq$updateAddr_fault;
  wire [3 : 0] coreFix_memExe_lsq$updateData_t;
  wire [1 : 0] coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx;
  wire coreFix_memExe_lsq$EN_deqLd,
       coreFix_memExe_lsq$EN_deqSt,
       coreFix_memExe_lsq$EN_enqLd,
       coreFix_memExe_lsq$EN_enqSt,
       coreFix_memExe_lsq$EN_getHit,
       coreFix_memExe_lsq$EN_getIssueLd,
       coreFix_memExe_lsq$EN_issueLd,
       coreFix_memExe_lsq$EN_respLd,
       coreFix_memExe_lsq$EN_setAtCommit_0_put,
       coreFix_memExe_lsq$EN_setAtCommit_1_put,
       coreFix_memExe_lsq$EN_specUpdate_correctSpeculation,
       coreFix_memExe_lsq$EN_specUpdate_incorrectSpeculation,
       coreFix_memExe_lsq$EN_updateAddr,
       coreFix_memExe_lsq$EN_updateData,
       coreFix_memExe_lsq$EN_wakeupLdStalledBySB,
       coreFix_memExe_lsq$RDY_deqLd,
       coreFix_memExe_lsq$RDY_deqSt,
       coreFix_memExe_lsq$RDY_enqLd,
       coreFix_memExe_lsq$RDY_enqSt,
       coreFix_memExe_lsq$RDY_firstLd,
       coreFix_memExe_lsq$RDY_firstSt,
       coreFix_memExe_lsq$RDY_getIssueLd,
       coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all,
       coreFix_memExe_lsq$stqEmpty,
       coreFix_memExe_lsq$updateAddr,
       coreFix_memExe_lsq$updateAddr_isMMIO;

  // ports of submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0
  wire coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN,
       coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1
  wire coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN,
       coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN,
       coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0
  wire coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN,
       coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1
  wire coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN,
       coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2
  wire coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN,
       coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN,
       coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0
  wire coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN,
       coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1
  wire coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN,
       coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2
  wire coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN,
       coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN,
       coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_regToExeQ
  reg [3 : 0] coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
  wire [192 : 0] coreFix_memExe_regToExeQ$enq_x,
		 coreFix_memExe_regToExeQ$first;
  wire [11 : 0] coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask;
  wire coreFix_memExe_regToExeQ$EN_deq,
       coreFix_memExe_regToExeQ$EN_enq,
       coreFix_memExe_regToExeQ$EN_specUpdate_correctSpeculation,
       coreFix_memExe_regToExeQ$EN_specUpdate_incorrectSpeculation,
       coreFix_memExe_regToExeQ$RDY_deq,
       coreFix_memExe_regToExeQ$RDY_enq,
       coreFix_memExe_regToExeQ$RDY_first,
       coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_memExe_reqLdQ_data_0_dummy2_0
  wire coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN,
       coreFix_memExe_reqLdQ_data_0_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqLdQ_data_0_dummy2_1
  wire coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN,
       coreFix_memExe_reqLdQ_data_0_dummy2_1$EN,
       coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_reqLdQ_deqP_dummy2_0
  wire coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN,
       coreFix_memExe_reqLdQ_deqP_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqLdQ_deqP_dummy2_1
  wire coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN,
       coreFix_memExe_reqLdQ_deqP_dummy2_1$EN;

  // ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_0
  wire coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN,
       coreFix_memExe_reqLdQ_empty_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_1
  wire coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN,
       coreFix_memExe_reqLdQ_empty_dummy2_1$EN,
       coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_2
  wire coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN,
       coreFix_memExe_reqLdQ_empty_dummy2_2$EN,
       coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_reqLdQ_enqP_dummy2_0
  wire coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN,
       coreFix_memExe_reqLdQ_enqP_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqLdQ_enqP_dummy2_1
  wire coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN,
       coreFix_memExe_reqLdQ_enqP_dummy2_1$EN;

  // ports of submodule coreFix_memExe_reqLdQ_full_dummy2_0
  wire coreFix_memExe_reqLdQ_full_dummy2_0$D_IN,
       coreFix_memExe_reqLdQ_full_dummy2_0$EN,
       coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT;

  // ports of submodule coreFix_memExe_reqLdQ_full_dummy2_1
  wire coreFix_memExe_reqLdQ_full_dummy2_1$D_IN,
       coreFix_memExe_reqLdQ_full_dummy2_1$EN,
       coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_reqLdQ_full_dummy2_2
  wire coreFix_memExe_reqLdQ_full_dummy2_2$D_IN,
       coreFix_memExe_reqLdQ_full_dummy2_2$EN,
       coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0
  wire coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1
  wire coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0
  wire coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN,
       coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1
  wire coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN,
       coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0
  wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN,
       coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1
  wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN,
       coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN,
       coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2
  wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN,
       coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN,
       coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0
  wire coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN,
       coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1
  wire coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN,
       coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0
  wire coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN,
       coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN,
       coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1
  wire coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN,
       coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN,
       coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2
  wire coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN,
       coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN,
       coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_reqStQ_data_0_dummy2_0
  wire coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN,
       coreFix_memExe_reqStQ_data_0_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqStQ_data_0_dummy2_1
  wire coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN,
       coreFix_memExe_reqStQ_data_0_dummy2_1$EN,
       coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_reqStQ_deqP_dummy2_0
  wire coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN,
       coreFix_memExe_reqStQ_deqP_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqStQ_deqP_dummy2_1
  wire coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN,
       coreFix_memExe_reqStQ_deqP_dummy2_1$EN;

  // ports of submodule coreFix_memExe_reqStQ_empty_dummy2_0
  wire coreFix_memExe_reqStQ_empty_dummy2_0$D_IN,
       coreFix_memExe_reqStQ_empty_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqStQ_empty_dummy2_1
  wire coreFix_memExe_reqStQ_empty_dummy2_1$D_IN,
       coreFix_memExe_reqStQ_empty_dummy2_1$EN,
       coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_reqStQ_empty_dummy2_2
  wire coreFix_memExe_reqStQ_empty_dummy2_2$D_IN,
       coreFix_memExe_reqStQ_empty_dummy2_2$EN,
       coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_reqStQ_enqP_dummy2_0
  wire coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN,
       coreFix_memExe_reqStQ_enqP_dummy2_0$EN;

  // ports of submodule coreFix_memExe_reqStQ_enqP_dummy2_1
  wire coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN,
       coreFix_memExe_reqStQ_enqP_dummy2_1$EN;

  // ports of submodule coreFix_memExe_reqStQ_full_dummy2_0
  wire coreFix_memExe_reqStQ_full_dummy2_0$D_IN,
       coreFix_memExe_reqStQ_full_dummy2_0$EN,
       coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT;

  // ports of submodule coreFix_memExe_reqStQ_full_dummy2_1
  wire coreFix_memExe_reqStQ_full_dummy2_1$D_IN,
       coreFix_memExe_reqStQ_full_dummy2_1$EN,
       coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_reqStQ_full_dummy2_2
  wire coreFix_memExe_reqStQ_full_dummy2_2$D_IN,
       coreFix_memExe_reqStQ_full_dummy2_2$EN,
       coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0
  wire coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN,
       coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1
  wire coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN,
       coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN,
       coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0
  wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN,
       coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1
  wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN,
       coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2
  wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN,
       coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN,
       coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0
  wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN,
       coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN;

  // ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1
  wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN,
       coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN;

  // ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2
  wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN,
       coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN,
       coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule coreFix_memExe_rsMem
  reg [7 : 0] coreFix_memExe_rsMem$setRegReady_2_put,
	      coreFix_memExe_rsMem$setRegReady_4_put;
  reg [3 : 0] coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag;
  wire [106 : 0] coreFix_memExe_rsMem$dispatchData,
		 coreFix_memExe_rsMem$enq_x;
  wire [11 : 0] coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask;
  wire [7 : 0] coreFix_memExe_rsMem$setRegReady_0_put,
	       coreFix_memExe_rsMem$setRegReady_1_put,
	       coreFix_memExe_rsMem$setRegReady_3_put;
  wire [5 : 0] coreFix_memExe_rsMem$setRobEnqTime_t;
  wire coreFix_memExe_rsMem$EN_doDispatch,
       coreFix_memExe_rsMem$EN_enq,
       coreFix_memExe_rsMem$EN_setRegReady_0_put,
       coreFix_memExe_rsMem$EN_setRegReady_1_put,
       coreFix_memExe_rsMem$EN_setRegReady_2_put,
       coreFix_memExe_rsMem$EN_setRegReady_3_put,
       coreFix_memExe_rsMem$EN_setRegReady_4_put,
       coreFix_memExe_rsMem$EN_setRobEnqTime,
       coreFix_memExe_rsMem$EN_specUpdate_correctSpeculation,
       coreFix_memExe_rsMem$EN_specUpdate_incorrectSpeculation,
       coreFix_memExe_rsMem$RDY_dispatchData,
       coreFix_memExe_rsMem$RDY_doDispatch,
       coreFix_memExe_rsMem$RDY_enq,
       coreFix_memExe_rsMem$canEnq,
       coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule coreFix_memExe_stb
  wire [635 : 0] coreFix_memExe_stb$issue;
  wire [633 : 0] coreFix_memExe_stb$deq;
  wire [67 : 0] coreFix_memExe_stb$search;
  wire [63 : 0] coreFix_memExe_stb$enq_data,
		coreFix_memExe_stb$enq_paddr,
		coreFix_memExe_stb$getEnqIndex_paddr,
		coreFix_memExe_stb$noMatchLdQ_paddr,
		coreFix_memExe_stb$noMatchStQ_paddr,
		coreFix_memExe_stb$search_paddr;
  wire [7 : 0] coreFix_memExe_stb$enq_be,
	       coreFix_memExe_stb$noMatchLdQ_be,
	       coreFix_memExe_stb$noMatchStQ_be,
	       coreFix_memExe_stb$search_be;
  wire [2 : 0] coreFix_memExe_stb$getEnqIndex;
  wire [1 : 0] coreFix_memExe_stb$deq_idx, coreFix_memExe_stb$enq_idx;
  wire coreFix_memExe_stb$EN_deq,
       coreFix_memExe_stb$EN_enq,
       coreFix_memExe_stb$EN_issue,
       coreFix_memExe_stb$RDY_deq,
       coreFix_memExe_stb$RDY_enq,
       coreFix_memExe_stb$RDY_issue,
       coreFix_memExe_stb$isEmpty,
       coreFix_memExe_stb$noMatchLdQ,
       coreFix_memExe_stb$noMatchStQ;

  // ports of submodule coreFix_trainBPQ_0
  wire [159 : 0] coreFix_trainBPQ_0$D_IN, coreFix_trainBPQ_0$D_OUT;
  wire coreFix_trainBPQ_0$CLR,
       coreFix_trainBPQ_0$DEQ,
       coreFix_trainBPQ_0$EMPTY_N,
       coreFix_trainBPQ_0$ENQ,
       coreFix_trainBPQ_0$FULL_N;

  // ports of submodule coreFix_trainBPQ_1
  wire [159 : 0] coreFix_trainBPQ_1$D_IN, coreFix_trainBPQ_1$D_OUT;
  wire coreFix_trainBPQ_1$CLR,
       coreFix_trainBPQ_1$DEQ,
       coreFix_trainBPQ_1$EMPTY_N,
       coreFix_trainBPQ_1$ENQ,
       coreFix_trainBPQ_1$FULL_N;

  // ports of submodule csrInstOrInterruptInflight_dummy2_0
  wire csrInstOrInterruptInflight_dummy2_0$D_IN,
       csrInstOrInterruptInflight_dummy2_0$EN,
       csrInstOrInterruptInflight_dummy2_0$Q_OUT;

  // ports of submodule csrInstOrInterruptInflight_dummy2_1
  wire csrInstOrInterruptInflight_dummy2_1$D_IN,
       csrInstOrInterruptInflight_dummy2_1$EN,
       csrInstOrInterruptInflight_dummy2_1$Q_OUT;

  // ports of submodule csrf_mcycle_ehr_data_dummy2_0
  wire csrf_mcycle_ehr_data_dummy2_0$D_IN,
       csrf_mcycle_ehr_data_dummy2_0$EN,
       csrf_mcycle_ehr_data_dummy2_0$Q_OUT;

  // ports of submodule csrf_mcycle_ehr_data_dummy2_1
  wire csrf_mcycle_ehr_data_dummy2_1$D_IN,
       csrf_mcycle_ehr_data_dummy2_1$EN,
       csrf_mcycle_ehr_data_dummy2_1$Q_OUT;

  // ports of submodule csrf_minstret_ehr_data_dummy2_0
  wire csrf_minstret_ehr_data_dummy2_0$D_IN,
       csrf_minstret_ehr_data_dummy2_0$EN,
       csrf_minstret_ehr_data_dummy2_0$Q_OUT;

  // ports of submodule csrf_minstret_ehr_data_dummy2_1
  wire csrf_minstret_ehr_data_dummy2_1$D_IN,
       csrf_minstret_ehr_data_dummy2_1$EN,
       csrf_minstret_ehr_data_dummy2_1$Q_OUT;

  // ports of submodule csrf_stats_module_writeQ
  wire csrf_stats_module_writeQ$CLR,
       csrf_stats_module_writeQ$DEQ,
       csrf_stats_module_writeQ$D_IN,
       csrf_stats_module_writeQ$D_OUT,
       csrf_stats_module_writeQ$EMPTY_N,
       csrf_stats_module_writeQ$ENQ,
       csrf_stats_module_writeQ$FULL_N;

  // ports of submodule csrf_terminate_module_terminateQ
  wire csrf_terminate_module_terminateQ$CLR,
       csrf_terminate_module_terminateQ$DEQ,
       csrf_terminate_module_terminateQ$EMPTY_N,
       csrf_terminate_module_terminateQ$ENQ,
       csrf_terminate_module_terminateQ$FULL_N;

  // ports of submodule epochManager
  wire [3 : 0] epochManager$checkEpoch_0_check_e,
	       epochManager$checkEpoch_1_check_e,
	       epochManager$updatePrevEpoch_0_update_e,
	       epochManager$updatePrevEpoch_1_update_e;
  wire epochManager$EN_incrementEpoch,
       epochManager$EN_updatePrevEpoch_0_update,
       epochManager$EN_updatePrevEpoch_1_update,
       epochManager$RDY_incrementEpoch,
       epochManager$checkEpoch_0_check,
       epochManager$checkEpoch_1_check;

  // ports of submodule fetchStage
  reg [63 : 0] fetchStage$redirect_pc;
  wire [582 : 0] fetchStage$iMemIfc_to_parent_fromP_enq_x;
  wire [578 : 0] fetchStage$iMemIfc_to_parent_rsToP_first;
  wire [387 : 0] fetchStage$pipelines_0_first, fetchStage$pipelines_1_first;
  wire [80 : 0] fetchStage$iTlbIfc_toParent_rsFromP_enq_x;
  wire [71 : 0] fetchStage$iMemIfc_to_parent_rqToP_first;
  wire [67 : 0] fetchStage$iMemIfc_cRqStuck_get,
		fetchStage$iMemIfc_pRqStuck_get;
  wire [65 : 0] fetchStage$mmioIfc_instResp_enq_x;
  wire [63 : 0] fetchStage$iMemIfc_to_proc_request_put,
		fetchStage$iTlbIfc_to_proc_request_put,
		fetchStage$mmioIfc_instReq_first_fst,
		fetchStage$mmioIfc_setHtifAddrs_fromHost,
		fetchStage$mmioIfc_setHtifAddrs_toHost,
		fetchStage$start_pc,
		fetchStage$train_predictors_next_pc,
		fetchStage$train_predictors_pc;
  wire [48 : 0] fetchStage$iTlbIfc_updateVMInfo_vm;
  wire [26 : 0] fetchStage$iTlbIfc_toParent_rqToP_first;
  wire [23 : 0] fetchStage$train_predictors_dpTrain;
  wire [4 : 0] fetchStage$train_predictors_iType;
  wire [2 : 0] fetchStage$iTlbIfc_perf_req_r;
  wire [1 : 0] fetchStage$iMemIfc_perf_req_r, fetchStage$perf_req_r;
  wire fetchStage$EN_done_flushing,
       fetchStage$EN_flush_predictors,
       fetchStage$EN_iMemIfc_cRqStuck_get,
       fetchStage$EN_iMemIfc_flush,
       fetchStage$EN_iMemIfc_pRqStuck_get,
       fetchStage$EN_iMemIfc_perf_req,
       fetchStage$EN_iMemIfc_perf_resp,
       fetchStage$EN_iMemIfc_perf_setStatus,
       fetchStage$EN_iMemIfc_to_parent_fromP_enq,
       fetchStage$EN_iMemIfc_to_parent_rqToP_deq,
       fetchStage$EN_iMemIfc_to_parent_rsToP_deq,
       fetchStage$EN_iMemIfc_to_proc_request_put,
       fetchStage$EN_iMemIfc_to_proc_response_get,
       fetchStage$EN_iTlbIfc_flush,
       fetchStage$EN_iTlbIfc_perf_req,
       fetchStage$EN_iTlbIfc_perf_resp,
       fetchStage$EN_iTlbIfc_perf_setStatus,
       fetchStage$EN_iTlbIfc_toParent_flush_request_get,
       fetchStage$EN_iTlbIfc_toParent_flush_response_put,
       fetchStage$EN_iTlbIfc_toParent_rqToP_deq,
       fetchStage$EN_iTlbIfc_toParent_rsFromP_enq,
       fetchStage$EN_iTlbIfc_to_proc_request_put,
       fetchStage$EN_iTlbIfc_to_proc_response_get,
       fetchStage$EN_iTlbIfc_updateVMInfo,
       fetchStage$EN_mmioIfc_instReq_deq,
       fetchStage$EN_mmioIfc_instResp_enq,
       fetchStage$EN_mmioIfc_setHtifAddrs,
       fetchStage$EN_perf_req,
       fetchStage$EN_perf_resp,
       fetchStage$EN_perf_setStatus,
       fetchStage$EN_pipelines_0_deq,
       fetchStage$EN_pipelines_1_deq,
       fetchStage$EN_redirect,
       fetchStage$EN_setWaitRedirect,
       fetchStage$EN_start,
       fetchStage$EN_stop,
       fetchStage$EN_train_predictors,
       fetchStage$RDY_done_flushing,
       fetchStage$RDY_iMemIfc_cRqStuck_get,
       fetchStage$RDY_iMemIfc_pRqStuck_get,
       fetchStage$RDY_iMemIfc_to_parent_fromP_enq,
       fetchStage$RDY_iMemIfc_to_parent_rqToP_deq,
       fetchStage$RDY_iMemIfc_to_parent_rqToP_first,
       fetchStage$RDY_iMemIfc_to_parent_rsToP_deq,
       fetchStage$RDY_iMemIfc_to_parent_rsToP_first,
       fetchStage$RDY_iTlbIfc_flush,
       fetchStage$RDY_iTlbIfc_toParent_flush_request_get,
       fetchStage$RDY_iTlbIfc_toParent_flush_response_put,
       fetchStage$RDY_iTlbIfc_toParent_rqToP_deq,
       fetchStage$RDY_iTlbIfc_toParent_rqToP_first,
       fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq,
       fetchStage$RDY_mmioIfc_instReq_deq,
       fetchStage$RDY_mmioIfc_instReq_first_fst,
       fetchStage$RDY_mmioIfc_instReq_first_snd,
       fetchStage$RDY_mmioIfc_instResp_enq,
       fetchStage$RDY_pipelines_0_deq,
       fetchStage$RDY_pipelines_0_first,
       fetchStage$RDY_pipelines_1_deq,
       fetchStage$RDY_pipelines_1_first,
       fetchStage$iMemIfc_perf_setStatus_doStats,
       fetchStage$iMemIfc_to_parent_fromP_notFull,
       fetchStage$iMemIfc_to_parent_rqToP_notEmpty,
       fetchStage$iMemIfc_to_parent_rsToP_notEmpty,
       fetchStage$iTlbIfc_flush_done,
       fetchStage$iTlbIfc_noPendingReq,
       fetchStage$iTlbIfc_perf_setStatus_doStats,
       fetchStage$mmioIfc_instReq_first_snd,
       fetchStage$perf_setStatus_doStats,
       fetchStage$pipelines_0_canDeq,
       fetchStage$pipelines_1_canDeq,
       fetchStage$train_predictors_isCompressed,
       fetchStage$train_predictors_mispred,
       fetchStage$train_predictors_taken;

  // ports of submodule l2Tlb
  wire [83 : 0] l2Tlb$toChildren_rsToC_first;
  wire [64 : 0] l2Tlb$toMem_memReq_first, l2Tlb$toMem_respLd_enq_x;
  wire [48 : 0] l2Tlb$updateVMInfo_vmD, l2Tlb$updateVMInfo_vmI;
  wire [29 : 0] l2Tlb$toChildren_rqFromC_put;
  wire [3 : 0] l2Tlb$perf_req_r;
  wire l2Tlb$EN_perf_req,
       l2Tlb$EN_perf_resp,
       l2Tlb$EN_perf_setStatus,
       l2Tlb$EN_toChildren_dTlbReqFlush_put,
       l2Tlb$EN_toChildren_flushDone_get,
       l2Tlb$EN_toChildren_iTlbReqFlush_put,
       l2Tlb$EN_toChildren_rqFromC_put,
       l2Tlb$EN_toChildren_rsToC_deq,
       l2Tlb$EN_toMem_memReq_deq,
       l2Tlb$EN_toMem_respLd_enq,
       l2Tlb$EN_updateVMInfo,
       l2Tlb$RDY_toChildren_dTlbReqFlush_put,
       l2Tlb$RDY_toChildren_flushDone_get,
       l2Tlb$RDY_toChildren_iTlbReqFlush_put,
       l2Tlb$RDY_toChildren_rqFromC_put,
       l2Tlb$RDY_toChildren_rsToC_deq,
       l2Tlb$RDY_toChildren_rsToC_first,
       l2Tlb$RDY_toMem_memReq_deq,
       l2Tlb$RDY_toMem_memReq_first,
       l2Tlb$RDY_toMem_respLd_enq,
       l2Tlb$perf_setStatus_doStats,
       l2Tlb$toMem_memReq_notEmpty,
       l2Tlb$toMem_respLd_notFull;

  // ports of submodule mmio_cRqQ_clearReq_dummy2_0
  wire mmio_cRqQ_clearReq_dummy2_0$D_IN, mmio_cRqQ_clearReq_dummy2_0$EN;

  // ports of submodule mmio_cRqQ_clearReq_dummy2_1
  wire mmio_cRqQ_clearReq_dummy2_1$D_IN,
       mmio_cRqQ_clearReq_dummy2_1$EN,
       mmio_cRqQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule mmio_cRqQ_deqReq_dummy2_0
  wire mmio_cRqQ_deqReq_dummy2_0$D_IN, mmio_cRqQ_deqReq_dummy2_0$EN;

  // ports of submodule mmio_cRqQ_deqReq_dummy2_1
  wire mmio_cRqQ_deqReq_dummy2_1$D_IN, mmio_cRqQ_deqReq_dummy2_1$EN;

  // ports of submodule mmio_cRqQ_deqReq_dummy2_2
  wire mmio_cRqQ_deqReq_dummy2_2$D_IN,
       mmio_cRqQ_deqReq_dummy2_2$EN,
       mmio_cRqQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_cRqQ_enqReq_dummy2_0
  wire mmio_cRqQ_enqReq_dummy2_0$D_IN, mmio_cRqQ_enqReq_dummy2_0$EN;

  // ports of submodule mmio_cRqQ_enqReq_dummy2_1
  wire mmio_cRqQ_enqReq_dummy2_1$D_IN, mmio_cRqQ_enqReq_dummy2_1$EN;

  // ports of submodule mmio_cRqQ_enqReq_dummy2_2
  wire mmio_cRqQ_enqReq_dummy2_2$D_IN,
       mmio_cRqQ_enqReq_dummy2_2$EN,
       mmio_cRqQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_cRsQ_clearReq_dummy2_0
  wire mmio_cRsQ_clearReq_dummy2_0$D_IN, mmio_cRsQ_clearReq_dummy2_0$EN;

  // ports of submodule mmio_cRsQ_clearReq_dummy2_1
  wire mmio_cRsQ_clearReq_dummy2_1$D_IN,
       mmio_cRsQ_clearReq_dummy2_1$EN,
       mmio_cRsQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule mmio_cRsQ_deqReq_dummy2_0
  wire mmio_cRsQ_deqReq_dummy2_0$D_IN, mmio_cRsQ_deqReq_dummy2_0$EN;

  // ports of submodule mmio_cRsQ_deqReq_dummy2_1
  wire mmio_cRsQ_deqReq_dummy2_1$D_IN, mmio_cRsQ_deqReq_dummy2_1$EN;

  // ports of submodule mmio_cRsQ_deqReq_dummy2_2
  wire mmio_cRsQ_deqReq_dummy2_2$D_IN,
       mmio_cRsQ_deqReq_dummy2_2$EN,
       mmio_cRsQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_cRsQ_enqReq_dummy2_0
  wire mmio_cRsQ_enqReq_dummy2_0$D_IN, mmio_cRsQ_enqReq_dummy2_0$EN;

  // ports of submodule mmio_cRsQ_enqReq_dummy2_1
  wire mmio_cRsQ_enqReq_dummy2_1$D_IN, mmio_cRsQ_enqReq_dummy2_1$EN;

  // ports of submodule mmio_cRsQ_enqReq_dummy2_2
  wire mmio_cRsQ_enqReq_dummy2_2$D_IN,
       mmio_cRsQ_enqReq_dummy2_2$EN,
       mmio_cRsQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_dataPendQ_clearReq_dummy2_0
  wire mmio_dataPendQ_clearReq_dummy2_0$D_IN,
       mmio_dataPendQ_clearReq_dummy2_0$EN;

  // ports of submodule mmio_dataPendQ_clearReq_dummy2_1
  wire mmio_dataPendQ_clearReq_dummy2_1$D_IN,
       mmio_dataPendQ_clearReq_dummy2_1$EN,
       mmio_dataPendQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule mmio_dataPendQ_deqReq_dummy2_0
  wire mmio_dataPendQ_deqReq_dummy2_0$D_IN, mmio_dataPendQ_deqReq_dummy2_0$EN;

  // ports of submodule mmio_dataPendQ_deqReq_dummy2_1
  wire mmio_dataPendQ_deqReq_dummy2_1$D_IN, mmio_dataPendQ_deqReq_dummy2_1$EN;

  // ports of submodule mmio_dataPendQ_deqReq_dummy2_2
  wire mmio_dataPendQ_deqReq_dummy2_2$D_IN,
       mmio_dataPendQ_deqReq_dummy2_2$EN,
       mmio_dataPendQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_dataPendQ_enqReq_dummy2_0
  wire mmio_dataPendQ_enqReq_dummy2_0$D_IN, mmio_dataPendQ_enqReq_dummy2_0$EN;

  // ports of submodule mmio_dataPendQ_enqReq_dummy2_1
  wire mmio_dataPendQ_enqReq_dummy2_1$D_IN, mmio_dataPendQ_enqReq_dummy2_1$EN;

  // ports of submodule mmio_dataPendQ_enqReq_dummy2_2
  wire mmio_dataPendQ_enqReq_dummy2_2$D_IN,
       mmio_dataPendQ_enqReq_dummy2_2$EN,
       mmio_dataPendQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_dataReqQ_clearReq_dummy2_0
  wire mmio_dataReqQ_clearReq_dummy2_0$D_IN,
       mmio_dataReqQ_clearReq_dummy2_0$EN;

  // ports of submodule mmio_dataReqQ_clearReq_dummy2_1
  wire mmio_dataReqQ_clearReq_dummy2_1$D_IN,
       mmio_dataReqQ_clearReq_dummy2_1$EN,
       mmio_dataReqQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule mmio_dataReqQ_deqReq_dummy2_0
  wire mmio_dataReqQ_deqReq_dummy2_0$D_IN, mmio_dataReqQ_deqReq_dummy2_0$EN;

  // ports of submodule mmio_dataReqQ_deqReq_dummy2_1
  wire mmio_dataReqQ_deqReq_dummy2_1$D_IN, mmio_dataReqQ_deqReq_dummy2_1$EN;

  // ports of submodule mmio_dataReqQ_deqReq_dummy2_2
  wire mmio_dataReqQ_deqReq_dummy2_2$D_IN,
       mmio_dataReqQ_deqReq_dummy2_2$EN,
       mmio_dataReqQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_dataReqQ_enqReq_dummy2_0
  wire mmio_dataReqQ_enqReq_dummy2_0$D_IN, mmio_dataReqQ_enqReq_dummy2_0$EN;

  // ports of submodule mmio_dataReqQ_enqReq_dummy2_1
  wire mmio_dataReqQ_enqReq_dummy2_1$D_IN, mmio_dataReqQ_enqReq_dummy2_1$EN;

  // ports of submodule mmio_dataReqQ_enqReq_dummy2_2
  wire mmio_dataReqQ_enqReq_dummy2_2$D_IN,
       mmio_dataReqQ_enqReq_dummy2_2$EN,
       mmio_dataReqQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_dataRespQ_clearReq_dummy2_0
  wire mmio_dataRespQ_clearReq_dummy2_0$D_IN,
       mmio_dataRespQ_clearReq_dummy2_0$EN;

  // ports of submodule mmio_dataRespQ_clearReq_dummy2_1
  wire mmio_dataRespQ_clearReq_dummy2_1$D_IN,
       mmio_dataRespQ_clearReq_dummy2_1$EN,
       mmio_dataRespQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule mmio_dataRespQ_deqReq_dummy2_0
  wire mmio_dataRespQ_deqReq_dummy2_0$D_IN, mmio_dataRespQ_deqReq_dummy2_0$EN;

  // ports of submodule mmio_dataRespQ_deqReq_dummy2_1
  wire mmio_dataRespQ_deqReq_dummy2_1$D_IN, mmio_dataRespQ_deqReq_dummy2_1$EN;

  // ports of submodule mmio_dataRespQ_deqReq_dummy2_2
  wire mmio_dataRespQ_deqReq_dummy2_2$D_IN,
       mmio_dataRespQ_deqReq_dummy2_2$EN,
       mmio_dataRespQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_dataRespQ_enqReq_dummy2_0
  wire mmio_dataRespQ_enqReq_dummy2_0$D_IN, mmio_dataRespQ_enqReq_dummy2_0$EN;

  // ports of submodule mmio_dataRespQ_enqReq_dummy2_1
  wire mmio_dataRespQ_enqReq_dummy2_1$D_IN, mmio_dataRespQ_enqReq_dummy2_1$EN;

  // ports of submodule mmio_dataRespQ_enqReq_dummy2_2
  wire mmio_dataRespQ_enqReq_dummy2_2$D_IN,
       mmio_dataRespQ_enqReq_dummy2_2$EN,
       mmio_dataRespQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_pRqQ_clearReq_dummy2_0
  wire mmio_pRqQ_clearReq_dummy2_0$D_IN, mmio_pRqQ_clearReq_dummy2_0$EN;

  // ports of submodule mmio_pRqQ_clearReq_dummy2_1
  wire mmio_pRqQ_clearReq_dummy2_1$D_IN,
       mmio_pRqQ_clearReq_dummy2_1$EN,
       mmio_pRqQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule mmio_pRqQ_deqReq_dummy2_0
  wire mmio_pRqQ_deqReq_dummy2_0$D_IN, mmio_pRqQ_deqReq_dummy2_0$EN;

  // ports of submodule mmio_pRqQ_deqReq_dummy2_1
  wire mmio_pRqQ_deqReq_dummy2_1$D_IN, mmio_pRqQ_deqReq_dummy2_1$EN;

  // ports of submodule mmio_pRqQ_deqReq_dummy2_2
  wire mmio_pRqQ_deqReq_dummy2_2$D_IN,
       mmio_pRqQ_deqReq_dummy2_2$EN,
       mmio_pRqQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_pRqQ_enqReq_dummy2_0
  wire mmio_pRqQ_enqReq_dummy2_0$D_IN, mmio_pRqQ_enqReq_dummy2_0$EN;

  // ports of submodule mmio_pRqQ_enqReq_dummy2_1
  wire mmio_pRqQ_enqReq_dummy2_1$D_IN, mmio_pRqQ_enqReq_dummy2_1$EN;

  // ports of submodule mmio_pRqQ_enqReq_dummy2_2
  wire mmio_pRqQ_enqReq_dummy2_2$D_IN,
       mmio_pRqQ_enqReq_dummy2_2$EN,
       mmio_pRqQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_pRsQ_clearReq_dummy2_0
  wire mmio_pRsQ_clearReq_dummy2_0$D_IN, mmio_pRsQ_clearReq_dummy2_0$EN;

  // ports of submodule mmio_pRsQ_clearReq_dummy2_1
  wire mmio_pRsQ_clearReq_dummy2_1$D_IN,
       mmio_pRsQ_clearReq_dummy2_1$EN,
       mmio_pRsQ_clearReq_dummy2_1$Q_OUT;

  // ports of submodule mmio_pRsQ_deqReq_dummy2_0
  wire mmio_pRsQ_deqReq_dummy2_0$D_IN, mmio_pRsQ_deqReq_dummy2_0$EN;

  // ports of submodule mmio_pRsQ_deqReq_dummy2_1
  wire mmio_pRsQ_deqReq_dummy2_1$D_IN, mmio_pRsQ_deqReq_dummy2_1$EN;

  // ports of submodule mmio_pRsQ_deqReq_dummy2_2
  wire mmio_pRsQ_deqReq_dummy2_2$D_IN,
       mmio_pRsQ_deqReq_dummy2_2$EN,
       mmio_pRsQ_deqReq_dummy2_2$Q_OUT;

  // ports of submodule mmio_pRsQ_enqReq_dummy2_0
  wire mmio_pRsQ_enqReq_dummy2_0$D_IN, mmio_pRsQ_enqReq_dummy2_0$EN;

  // ports of submodule mmio_pRsQ_enqReq_dummy2_1
  wire mmio_pRsQ_enqReq_dummy2_1$D_IN, mmio_pRsQ_enqReq_dummy2_1$EN;

  // ports of submodule mmio_pRsQ_enqReq_dummy2_2
  wire mmio_pRsQ_enqReq_dummy2_2$D_IN,
       mmio_pRsQ_enqReq_dummy2_2$EN,
       mmio_pRsQ_enqReq_dummy2_2$Q_OUT;

  // ports of submodule perfReqQ
  wire [8 : 0] perfReqQ$D_IN, perfReqQ$D_OUT;
  wire perfReqQ$CLR,
       perfReqQ$DEQ,
       perfReqQ$EMPTY_N,
       perfReqQ$ENQ,
       perfReqQ$FULL_N;

  // ports of submodule regRenamingTable
  reg [3 : 0] regRenamingTable$specUpdate_incorrectSpeculation_kill_tag;
  wire [32 : 0] regRenamingTable$rename_0_getRename,
		regRenamingTable$rename_1_getRename;
  wire [26 : 0] regRenamingTable$rename_0_claimRename_r,
		regRenamingTable$rename_0_getRename_r,
		regRenamingTable$rename_1_claimRename_r,
		regRenamingTable$rename_1_getRename_r;
  wire [11 : 0] regRenamingTable$rename_0_claimRename_sb,
		regRenamingTable$rename_1_claimRename_sb,
		regRenamingTable$specUpdate_correctSpeculation_mask;
  wire regRenamingTable$EN_commit_0_commit,
       regRenamingTable$EN_commit_1_commit,
       regRenamingTable$EN_rename_0_claimRename,
       regRenamingTable$EN_rename_1_claimRename,
       regRenamingTable$EN_specUpdate_correctSpeculation,
       regRenamingTable$EN_specUpdate_incorrectSpeculation,
       regRenamingTable$RDY_commit_0_commit,
       regRenamingTable$RDY_commit_1_commit,
       regRenamingTable$RDY_rename_0_claimRename,
       regRenamingTable$RDY_rename_0_getRename,
       regRenamingTable$RDY_rename_1_claimRename,
       regRenamingTable$RDY_rename_1_getRename,
       regRenamingTable$rename_0_canRename,
       regRenamingTable$rename_1_canRename,
       regRenamingTable$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule rf
  reg [63 : 0] rf$write_2_wr_data, rf$write_3_wr_data;
  reg [6 : 0] rf$write_2_wr_rindx, rf$write_3_wr_rindx;
  wire [63 : 0] rf$read_0_rd1,
		rf$read_0_rd2,
		rf$read_1_rd1,
		rf$read_1_rd2,
		rf$read_2_rd1,
		rf$read_2_rd2,
		rf$read_2_rd3,
		rf$read_3_rd1,
		rf$read_3_rd2,
		rf$write_0_wr_data,
		rf$write_1_wr_data,
		rf$write_4_wr_data;
  wire [6 : 0] rf$read_0_rd1_rindx,
	       rf$read_0_rd2_rindx,
	       rf$read_0_rd3_rindx,
	       rf$read_1_rd1_rindx,
	       rf$read_1_rd2_rindx,
	       rf$read_1_rd3_rindx,
	       rf$read_2_rd1_rindx,
	       rf$read_2_rd2_rindx,
	       rf$read_2_rd3_rindx,
	       rf$read_3_rd1_rindx,
	       rf$read_3_rd2_rindx,
	       rf$read_3_rd3_rindx,
	       rf$read_4_rd1_rindx,
	       rf$read_4_rd2_rindx,
	       rf$read_4_rd3_rindx,
	       rf$write_0_wr_rindx,
	       rf$write_1_wr_rindx,
	       rf$write_4_wr_rindx;
  wire rf$EN_write_0_wr,
       rf$EN_write_1_wr,
       rf$EN_write_2_wr,
       rf$EN_write_3_wr,
       rf$EN_write_4_wr;

  // ports of submodule rob
  reg [353 : 0] rob$enqPort_0_enq_x;
  reg [63 : 0] rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data;
  reg [11 : 0] rob$setExecuted_doFinishFpuMulDiv_0_set_x,
	       rob$specUpdate_incorrectSpeculation_inst_tag;
  reg [4 : 0] rob$setExecuted_deqLSQ_cause,
	      rob$setExecuted_doFinishFpuMulDiv_0_set_fflags;
  reg [3 : 0] rob$specUpdate_incorrectSpeculation_spec_tag;
  wire [353 : 0] rob$deqPort_0_deq_data,
		 rob$deqPort_1_deq_data,
		 rob$enqPort_1_enq_x;
  wire [129 : 0] rob$setExecuted_doFinishAlu_0_set_cf,
		 rob$setExecuted_doFinishAlu_1_set_cf;
  wire [64 : 0] rob$setExecuted_doFinishAlu_0_set_csrData,
		rob$setExecuted_doFinishAlu_1_set_csrData;
  wire [63 : 0] rob$getOrigPC_0_get,
		rob$getOrigPC_1_get,
		rob$getOrigPredPC_0_get,
		rob$getOrigPredPC_1_get,
		rob$setExecuted_doFinishAlu_0_set_dst_data,
		rob$setExecuted_doFinishAlu_1_set_dst_data,
		rob$setExecuted_doFinishMem_store_data,
		rob$setExecuted_doFinishMem_vaddr;
  wire [31 : 0] rob$getOrig_Inst_0_get, rob$getOrig_Inst_1_get;
  wire [11 : 0] rob$deqPort_0_getDeqInstTag,
		rob$enqPort_0_getEnqInstTag,
		rob$enqPort_1_getEnqInstTag,
		rob$getOrigPC_0_get_x,
		rob$getOrigPC_1_get_x,
		rob$getOrigPC_2_get_x,
		rob$getOrigPredPC_0_get_x,
		rob$getOrigPredPC_1_get_x,
		rob$getOrig_Inst_0_get_x,
		rob$getOrig_Inst_1_get_x,
		rob$setExecuted_deqLSQ_x,
		rob$setExecuted_doFinishAlu_0_set_x,
		rob$setExecuted_doFinishAlu_1_set_x,
		rob$setExecuted_doFinishMem_x,
		rob$setLSQAtCommitNotified_x,
		rob$specUpdate_correctSpeculation_mask;
  wire [7 : 0] rob$setExecuted_doFinishMem_store_data_BE;
  wire [5 : 0] rob$getEnqTime;
  wire [2 : 0] rob$setExecuted_deqLSQ_ld_killed;
  wire rob$EN_deqPort_0_deq,
       rob$EN_deqPort_1_deq,
       rob$EN_enqPort_0_enq,
       rob$EN_enqPort_1_enq,
       rob$EN_setExecuted_deqLSQ,
       rob$EN_setExecuted_doFinishAlu_0_set,
       rob$EN_setExecuted_doFinishAlu_1_set,
       rob$EN_setExecuted_doFinishFpuMulDiv_0_set,
       rob$EN_setExecuted_doFinishMem,
       rob$EN_setLSQAtCommitNotified,
       rob$EN_specUpdate_correctSpeculation,
       rob$EN_specUpdate_incorrectSpeculation,
       rob$RDY_deqPort_0_deq,
       rob$RDY_deqPort_0_deq_data,
       rob$RDY_deqPort_1_deq,
       rob$RDY_deqPort_1_deq_data,
       rob$RDY_enqPort_0_enq,
       rob$RDY_enqPort_1_enq,
       rob$RDY_setExecuted_deqLSQ,
       rob$RDY_setExecuted_doFinishAlu_0_set,
       rob$RDY_setExecuted_doFinishAlu_1_set,
       rob$RDY_setExecuted_doFinishFpuMulDiv_0_set,
       rob$RDY_setExecuted_doFinishMem,
       rob$RDY_setLSQAtCommitNotified,
       rob$deqPort_0_canDeq,
       rob$deqPort_1_canDeq,
       rob$enqPort_0_canEnq,
       rob$enqPort_1_canEnq,
       rob$isEmpty,
       rob$setExecuted_doFinishMem_access_at_commit,
       rob$setExecuted_doFinishMem_non_mmio_st_done,
       rob$specUpdate_incorrectSpeculation_kill_all;

  // ports of submodule sbAggr
  reg [6 : 0] sbAggr$setReady_2_put, sbAggr$setReady_4_put;
  wire [32 : 0] sbAggr$eagerLookup_0_get_r, sbAggr$eagerLookup_1_get_r;
  wire [8 : 0] sbAggr$setBusy_0_set_dst, sbAggr$setBusy_1_set_dst;
  wire [6 : 0] sbAggr$setReady_0_put,
	       sbAggr$setReady_1_put,
	       sbAggr$setReady_3_put;
  wire [3 : 0] sbAggr$eagerLookup_0_get, sbAggr$eagerLookup_1_get;
  wire sbAggr$EN_setBusy_0_set,
       sbAggr$EN_setBusy_1_set,
       sbAggr$EN_setReady_0_put,
       sbAggr$EN_setReady_1_put,
       sbAggr$EN_setReady_2_put,
       sbAggr$EN_setReady_3_put,
       sbAggr$EN_setReady_4_put;

  // ports of submodule sbCons
  reg [6 : 0] sbCons$setReady_2_put, sbCons$setReady_3_put;
  wire [32 : 0] sbCons$eagerLookup_0_get_r,
		sbCons$eagerLookup_1_get_r,
		sbCons$lazyLookup_0_get_r,
		sbCons$lazyLookup_1_get_r,
		sbCons$lazyLookup_2_get_r,
		sbCons$lazyLookup_3_get_r,
		sbCons$lazyLookup_4_get_r;
  wire [8 : 0] sbCons$setBusy_0_set_dst, sbCons$setBusy_1_set_dst;
  wire [6 : 0] sbCons$setReady_0_put,
	       sbCons$setReady_1_put,
	       sbCons$setReady_4_put;
  wire [3 : 0] sbCons$lazyLookup_0_get,
	       sbCons$lazyLookup_1_get,
	       sbCons$lazyLookup_2_get,
	       sbCons$lazyLookup_3_get;
  wire sbCons$EN_setBusy_0_set,
       sbCons$EN_setBusy_1_set,
       sbCons$EN_setReady_0_put,
       sbCons$EN_setReady_1_put,
       sbCons$EN_setReady_2_put,
       sbCons$EN_setReady_3_put,
       sbCons$EN_setReady_4_put;

  // ports of submodule specTagManager
  reg [3 : 0] specTagManager$specUpdate_incorrectSpeculation_kill_tag;
  wire [11 : 0] specTagManager$currentSpecBits,
		specTagManager$specUpdate_correctSpeculation_mask;
  wire [3 : 0] specTagManager$nextSpecTag;
  wire specTagManager$EN_claimSpecTag,
       specTagManager$EN_specUpdate_correctSpeculation,
       specTagManager$EN_specUpdate_incorrectSpeculation,
       specTagManager$RDY_claimSpecTag,
       specTagManager$RDY_nextSpecTag,
       specTagManager$canClaim,
       specTagManager$specUpdate_incorrectSpeculation_kill_all;

  // rule scheduling signals
  wire CAN_FIRE_RL_commitStage_doCommitKilledLd,
       CAN_FIRE_RL_commitStage_doCommitNormalInst,
       CAN_FIRE_RL_commitStage_doCommitSystemInst,
       CAN_FIRE_RL_commitStage_doCommitTrap_flush,
       CAN_FIRE_RL_commitStage_doCommitTrap_handle,
       CAN_FIRE_RL_commitStage_doSetLSQAtCommit,
       CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1,
       CAN_FIRE_RL_commitStage_notifyLSQCommit,
       CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu,
       CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu,
       CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F,
       CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T,
       CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu,
       CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu,
       CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu,
       CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F,
       CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T,
       CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu,
       CAN_FIRE_RL_coreFix_doFetchTrainBP,
       CAN_FIRE_RL_coreFix_doFetchTrainBP_1,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_rl_ready,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_canon,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_canon,
       CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_canon,
       CAN_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq,
       CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq,
       CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize,
       CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem,
       CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq,
       CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue,
       CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq,
       CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault,
       CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue,
       CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault,
       CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence,
       CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq,
       CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault,
       CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue,
       CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq,
       CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue,
       CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem,
       CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault,
       CAN_FIRE_RL_coreFix_memExe_doDispatchMem,
       CAN_FIRE_RL_coreFix_memExe_doExeMem,
       CAN_FIRE_RL_coreFix_memExe_doFinishMem,
       CAN_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ,
       CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate,
       CAN_FIRE_RL_coreFix_memExe_doIssueSB,
       CAN_FIRE_RL_coreFix_memExe_doRegReadMem,
       CAN_FIRE_RL_coreFix_memExe_doRespLdForward,
       CAN_FIRE_RL_coreFix_memExe_doRespLdMem,
       CAN_FIRE_RL_coreFix_memExe_forwardQ_canonicalize,
       CAN_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon,
       CAN_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize,
       CAN_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon,
       CAN_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon,
       CAN_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon,
       CAN_FIRE_RL_coreFix_memExe_reqLdQ_full_canon,
       CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon,
       CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon,
       CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon,
       CAN_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon,
       CAN_FIRE_RL_coreFix_memExe_reqStQ_empty_canon,
       CAN_FIRE_RL_coreFix_memExe_reqStQ_full_canon,
       CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize,
       CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon,
       CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon,
       CAN_FIRE_RL_coreFix_memExe_sendLdToMem,
       CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem,
       CAN_FIRE_RL_coreFix_memExe_sendStToMem,
       CAN_FIRE_RL_csrInstOrInterruptInflight_canon,
       CAN_FIRE_RL_csrf_incCycle,
       CAN_FIRE_RL_csrf_mcycle_ehr_data_canon,
       CAN_FIRE_RL_csrf_mcycle_ehr_setRead,
       CAN_FIRE_RL_csrf_minstret_ehr_data_canon,
       CAN_FIRE_RL_csrf_minstret_ehr_setRead,
       CAN_FIRE_RL_mkConnectionGetPut,
       CAN_FIRE_RL_mkConnectionGetPut_1,
       CAN_FIRE_RL_mmio_cRqQ_canonicalize,
       CAN_FIRE_RL_mmio_cRqQ_clearReq_canon,
       CAN_FIRE_RL_mmio_cRqQ_deqReq_canon,
       CAN_FIRE_RL_mmio_cRqQ_enqReq_canon,
       CAN_FIRE_RL_mmio_cRsQ_canonicalize,
       CAN_FIRE_RL_mmio_cRsQ_clearReq_canon,
       CAN_FIRE_RL_mmio_cRsQ_deqReq_canon,
       CAN_FIRE_RL_mmio_cRsQ_enqReq_canon,
       CAN_FIRE_RL_mmio_dataPendQ_canonicalize,
       CAN_FIRE_RL_mmio_dataPendQ_clearReq_canon,
       CAN_FIRE_RL_mmio_dataPendQ_deqReq_canon,
       CAN_FIRE_RL_mmio_dataPendQ_enqReq_canon,
       CAN_FIRE_RL_mmio_dataReqQ_canonicalize,
       CAN_FIRE_RL_mmio_dataReqQ_clearReq_canon,
       CAN_FIRE_RL_mmio_dataReqQ_deqReq_canon,
       CAN_FIRE_RL_mmio_dataReqQ_enqReq_canon,
       CAN_FIRE_RL_mmio_dataRespQ_canonicalize,
       CAN_FIRE_RL_mmio_dataRespQ_clearReq_canon,
       CAN_FIRE_RL_mmio_dataRespQ_deqReq_canon,
       CAN_FIRE_RL_mmio_dataRespQ_enqReq_canon,
       CAN_FIRE_RL_mmio_handlePRq,
       CAN_FIRE_RL_mmio_pRqQ_canonicalize,
       CAN_FIRE_RL_mmio_pRqQ_clearReq_canon,
       CAN_FIRE_RL_mmio_pRqQ_deqReq_canon,
       CAN_FIRE_RL_mmio_pRqQ_enqReq_canon,
       CAN_FIRE_RL_mmio_pRsQ_canonicalize,
       CAN_FIRE_RL_mmio_pRsQ_clearReq_canon,
       CAN_FIRE_RL_mmio_pRsQ_deqReq_canon,
       CAN_FIRE_RL_mmio_pRsQ_enqReq_canon,
       CAN_FIRE_RL_mmio_sendDataReq,
       CAN_FIRE_RL_mmio_sendDataResp,
       CAN_FIRE_RL_mmio_sendInstReq,
       CAN_FIRE_RL_mmio_sendInstResp,
       CAN_FIRE_RL_prepareCachesAndTlbs,
       CAN_FIRE_RL_readyToFetch,
       CAN_FIRE_RL_renameStage_doRenaming,
       CAN_FIRE_RL_renameStage_doRenaming_SystemInst,
       CAN_FIRE_RL_renameStage_doRenaming_Trap,
       CAN_FIRE_RL_renameStage_doRenaming_wrongPath,
       CAN_FIRE_RL_rl_outOfReset,
       CAN_FIRE_RL_sendDTlbReq,
       CAN_FIRE_RL_sendFlushDone,
       CAN_FIRE_RL_sendITlbReq,
       CAN_FIRE_RL_sendRobEnqTime,
       CAN_FIRE_RL_sendRsToDTlb,
       CAN_FIRE_RL_sendRsToITlb,
       CAN_FIRE_coreIndInv_perfResp,
       CAN_FIRE_coreIndInv_terminate,
       CAN_FIRE_coreReq_perfReq,
       CAN_FIRE_coreReq_start,
       CAN_FIRE_dCacheToParent_fromP_enq,
       CAN_FIRE_dCacheToParent_rqToP_deq,
       CAN_FIRE_dCacheToParent_rsToP_deq,
       CAN_FIRE_deadlock_checkStarted_get,
       CAN_FIRE_deadlock_commitInstStuck_get,
       CAN_FIRE_deadlock_commitUserInstStuck_get,
       CAN_FIRE_deadlock_dCacheCRqStuck_get,
       CAN_FIRE_deadlock_dCachePRqStuck_get,
       CAN_FIRE_deadlock_iCacheCRqStuck_get,
       CAN_FIRE_deadlock_iCachePRqStuck_get,
       CAN_FIRE_deadlock_renameCorrectPathStuck_get,
       CAN_FIRE_deadlock_renameInstStuck_get,
       CAN_FIRE_iCacheToParent_fromP_enq,
       CAN_FIRE_iCacheToParent_rqToP_deq,
       CAN_FIRE_iCacheToParent_rsToP_deq,
       CAN_FIRE_mmioToPlatform_cRq_deq,
       CAN_FIRE_mmioToPlatform_cRs_deq,
       CAN_FIRE_mmioToPlatform_pRq_enq,
       CAN_FIRE_mmioToPlatform_pRs_enq,
       CAN_FIRE_mmioToPlatform_setTime,
       CAN_FIRE_recvDoStats,
       CAN_FIRE_renameDebug_renameErr_get,
       CAN_FIRE_sendDoStats,
       CAN_FIRE_setMEIP,
       CAN_FIRE_setSEIP,
       CAN_FIRE_tlbToMem_memReq_deq,
       CAN_FIRE_tlbToMem_respLd_enq,
       WILL_FIRE_RL_commitStage_doCommitKilledLd,
       WILL_FIRE_RL_commitStage_doCommitNormalInst,
       WILL_FIRE_RL_commitStage_doCommitSystemInst,
       WILL_FIRE_RL_commitStage_doCommitTrap_flush,
       WILL_FIRE_RL_commitStage_doCommitTrap_handle,
       WILL_FIRE_RL_commitStage_doSetLSQAtCommit,
       WILL_FIRE_RL_commitStage_doSetLSQAtCommit_1,
       WILL_FIRE_RL_commitStage_notifyLSQCommit,
       WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu,
       WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu,
       WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F,
       WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T,
       WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu,
       WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu,
       WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu,
       WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F,
       WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T,
       WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu,
       WILL_FIRE_RL_coreFix_doFetchTrainBP,
       WILL_FIRE_RL_coreFix_doFetchTrainBP_1,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_rl_ready,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_canon,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_canon,
       WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_canon,
       WILL_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq,
       WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq,
       WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize,
       WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem,
       WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq,
       WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue,
       WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq,
       WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault,
       WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue,
       WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault,
       WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence,
       WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq,
       WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault,
       WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue,
       WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq,
       WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue,
       WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem,
       WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault,
       WILL_FIRE_RL_coreFix_memExe_doDispatchMem,
       WILL_FIRE_RL_coreFix_memExe_doExeMem,
       WILL_FIRE_RL_coreFix_memExe_doFinishMem,
       WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ,
       WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate,
       WILL_FIRE_RL_coreFix_memExe_doIssueSB,
       WILL_FIRE_RL_coreFix_memExe_doRegReadMem,
       WILL_FIRE_RL_coreFix_memExe_doRespLdForward,
       WILL_FIRE_RL_coreFix_memExe_doRespLdMem,
       WILL_FIRE_RL_coreFix_memExe_forwardQ_canonicalize,
       WILL_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon,
       WILL_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize,
       WILL_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon,
       WILL_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon,
       WILL_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon,
       WILL_FIRE_RL_coreFix_memExe_reqLdQ_full_canon,
       WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon,
       WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon,
       WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon,
       WILL_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon,
       WILL_FIRE_RL_coreFix_memExe_reqStQ_empty_canon,
       WILL_FIRE_RL_coreFix_memExe_reqStQ_full_canon,
       WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize,
       WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon,
       WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon,
       WILL_FIRE_RL_coreFix_memExe_sendLdToMem,
       WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem,
       WILL_FIRE_RL_coreFix_memExe_sendStToMem,
       WILL_FIRE_RL_csrInstOrInterruptInflight_canon,
       WILL_FIRE_RL_csrf_incCycle,
       WILL_FIRE_RL_csrf_mcycle_ehr_data_canon,
       WILL_FIRE_RL_csrf_mcycle_ehr_setRead,
       WILL_FIRE_RL_csrf_minstret_ehr_data_canon,
       WILL_FIRE_RL_csrf_minstret_ehr_setRead,
       WILL_FIRE_RL_mkConnectionGetPut,
       WILL_FIRE_RL_mkConnectionGetPut_1,
       WILL_FIRE_RL_mmio_cRqQ_canonicalize,
       WILL_FIRE_RL_mmio_cRqQ_clearReq_canon,
       WILL_FIRE_RL_mmio_cRqQ_deqReq_canon,
       WILL_FIRE_RL_mmio_cRqQ_enqReq_canon,
       WILL_FIRE_RL_mmio_cRsQ_canonicalize,
       WILL_FIRE_RL_mmio_cRsQ_clearReq_canon,
       WILL_FIRE_RL_mmio_cRsQ_deqReq_canon,
       WILL_FIRE_RL_mmio_cRsQ_enqReq_canon,
       WILL_FIRE_RL_mmio_dataPendQ_canonicalize,
       WILL_FIRE_RL_mmio_dataPendQ_clearReq_canon,
       WILL_FIRE_RL_mmio_dataPendQ_deqReq_canon,
       WILL_FIRE_RL_mmio_dataPendQ_enqReq_canon,
       WILL_FIRE_RL_mmio_dataReqQ_canonicalize,
       WILL_FIRE_RL_mmio_dataReqQ_clearReq_canon,
       WILL_FIRE_RL_mmio_dataReqQ_deqReq_canon,
       WILL_FIRE_RL_mmio_dataReqQ_enqReq_canon,
       WILL_FIRE_RL_mmio_dataRespQ_canonicalize,
       WILL_FIRE_RL_mmio_dataRespQ_clearReq_canon,
       WILL_FIRE_RL_mmio_dataRespQ_deqReq_canon,
       WILL_FIRE_RL_mmio_dataRespQ_enqReq_canon,
       WILL_FIRE_RL_mmio_handlePRq,
       WILL_FIRE_RL_mmio_pRqQ_canonicalize,
       WILL_FIRE_RL_mmio_pRqQ_clearReq_canon,
       WILL_FIRE_RL_mmio_pRqQ_deqReq_canon,
       WILL_FIRE_RL_mmio_pRqQ_enqReq_canon,
       WILL_FIRE_RL_mmio_pRsQ_canonicalize,
       WILL_FIRE_RL_mmio_pRsQ_clearReq_canon,
       WILL_FIRE_RL_mmio_pRsQ_deqReq_canon,
       WILL_FIRE_RL_mmio_pRsQ_enqReq_canon,
       WILL_FIRE_RL_mmio_sendDataReq,
       WILL_FIRE_RL_mmio_sendDataResp,
       WILL_FIRE_RL_mmio_sendInstReq,
       WILL_FIRE_RL_mmio_sendInstResp,
       WILL_FIRE_RL_prepareCachesAndTlbs,
       WILL_FIRE_RL_readyToFetch,
       WILL_FIRE_RL_renameStage_doRenaming,
       WILL_FIRE_RL_renameStage_doRenaming_SystemInst,
       WILL_FIRE_RL_renameStage_doRenaming_Trap,
       WILL_FIRE_RL_renameStage_doRenaming_wrongPath,
       WILL_FIRE_RL_rl_outOfReset,
       WILL_FIRE_RL_sendDTlbReq,
       WILL_FIRE_RL_sendFlushDone,
       WILL_FIRE_RL_sendITlbReq,
       WILL_FIRE_RL_sendRobEnqTime,
       WILL_FIRE_RL_sendRsToDTlb,
       WILL_FIRE_RL_sendRsToITlb,
       WILL_FIRE_coreIndInv_perfResp,
       WILL_FIRE_coreIndInv_terminate,
       WILL_FIRE_coreReq_perfReq,
       WILL_FIRE_coreReq_start,
       WILL_FIRE_dCacheToParent_fromP_enq,
       WILL_FIRE_dCacheToParent_rqToP_deq,
       WILL_FIRE_dCacheToParent_rsToP_deq,
       WILL_FIRE_deadlock_checkStarted_get,
       WILL_FIRE_deadlock_commitInstStuck_get,
       WILL_FIRE_deadlock_commitUserInstStuck_get,
       WILL_FIRE_deadlock_dCacheCRqStuck_get,
       WILL_FIRE_deadlock_dCachePRqStuck_get,
       WILL_FIRE_deadlock_iCacheCRqStuck_get,
       WILL_FIRE_deadlock_iCachePRqStuck_get,
       WILL_FIRE_deadlock_renameCorrectPathStuck_get,
       WILL_FIRE_deadlock_renameInstStuck_get,
       WILL_FIRE_iCacheToParent_fromP_enq,
       WILL_FIRE_iCacheToParent_rqToP_deq,
       WILL_FIRE_iCacheToParent_rsToP_deq,
       WILL_FIRE_mmioToPlatform_cRq_deq,
       WILL_FIRE_mmioToPlatform_cRs_deq,
       WILL_FIRE_mmioToPlatform_pRq_enq,
       WILL_FIRE_mmioToPlatform_pRs_enq,
       WILL_FIRE_mmioToPlatform_setTime,
       WILL_FIRE_recvDoStats,
       WILL_FIRE_renameDebug_renameErr_get,
       WILL_FIRE_sendDoStats,
       WILL_FIRE_setMEIP,
       WILL_FIRE_setSEIP,
       WILL_FIRE_tlbToMem_memReq_deq,
       WILL_FIRE_tlbToMem_respLd_enq;

  // inputs to muxes for submodule ports
  reg [63 : 0] MUX_coreFix_memExe_lsq$respLd_2__VAL_1,
	       MUX_coreFix_memExe_lsq$respLd_2__VAL_2,
	       MUX_fetchStage$redirect_1__VAL_5;
  reg [4 : 0] MUX_coreFix_memExe_lsq$respLd_1__VAL_1,
	      MUX_coreFix_memExe_lsq$respLd_1__VAL_2;
  reg [1 : 0] MUX_csrf_fs_reg$write_1__VAL_1;
  wire [583 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1,
		 MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2,
		 MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3,
		 MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4;
  wire [579 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1,
		 MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2;
  wire [569 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1,
		 MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2,
		 MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3,
		 MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4;
  wire [353 : 0] MUX_rob$enqPort_0_enq_1__VAL_1,
		 MUX_rob$enqPort_0_enq_1__VAL_2,
		 MUX_rob$enqPort_0_enq_1__VAL_3;
  wire [165 : 0] MUX_commitStage_commitTrap$write_1__VAL_2;
  wire [161 : 0] MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1,
		 MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2;
  wire [160 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1,
		 MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2;
  wire [159 : 0] MUX_coreFix_trainBPQ_0$enq_1__VAL_1,
		 MUX_coreFix_trainBPQ_0$enq_1__VAL_2,
		 MUX_coreFix_trainBPQ_1$enq_1__VAL_1,
		 MUX_coreFix_trainBPQ_1$enq_1__VAL_2;
  wire [152 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1,
		 MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2,
		 MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3,
		 MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1,
		 MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_2;
  wire [142 : 0] MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1,
		 MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2,
		 MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1,
		 MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_2;
  wire [69 : 0] MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1,
		MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2,
		MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1;
  wire [67 : 0] MUX_coreFix_memExe_lsq$issueLd_4__VAL_1;
  wire [64 : 0] MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1,
		MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2,
		MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3;
  wire [63 : 0] MUX_commitStage_rg_serial_num$write_1__VAL_1,
		MUX_commitStage_rg_serial_num$write_1__VAL_2,
		MUX_csrf_mepc_csr$write_1__VAL_2,
		MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1,
		MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2,
		MUX_csrf_mtval_csr$write_1__VAL_1,
		MUX_csrf_mtval_csr$write_1__VAL_2,
		MUX_csrf_sepc_csr$write_1__VAL_2,
		MUX_fetchStage$redirect_1__VAL_4,
		MUX_rf$write_2_wr_2__VAL_2,
		MUX_rf$write_2_wr_2__VAL_3,
		MUX_rf$write_2_wr_2__VAL_4,
		MUX_rf$write_2_wr_2__VAL_5,
		MUX_rf$write_2_wr_2__VAL_6,
		MUX_rf$write_3_wr_2__VAL_4,
		MUX_rf$write_3_wr_2__VAL_5;
  wire [58 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1,
		MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2;
  wire [57 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1,
		MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2;
  wire [29 : 0] MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1,
		MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2;
  wire [7 : 0] MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1,
	       MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2,
	       MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3,
	       MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4,
	       MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5,
	       MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6,
	       MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1,
	       MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2,
	       MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
  wire [5 : 0] MUX_coreFix_memExe_lsq$getHit_1__VAL_1;
  wire [4 : 0] MUX_csrf_fflags_reg$write_1__VAL_2,
	       MUX_rob$setExecuted_deqLSQ_2__VAL_2,
	       MUX_rob$setExecuted_deqLSQ_2__VAL_6,
	       MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2,
	       MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3,
	       MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4;
  wire [3 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1,
	       MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1,
	       MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2;
  wire [2 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1;
  wire [1 : 0] MUX_csrf_mpp_reg$write_1__VAL_2,
	       MUX_csrf_prv_reg$write_1__VAL_1,
	       MUX_csrf_prv_reg$write_1__VAL_2;
  wire MUX_commitStage_rg_serial_num$write_1__SEL_1,
       MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1,
       MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3,
       MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3,
       MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4,
       MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1,
       MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2,
       MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1,
       MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1,
       MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2,
       MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1,
       MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2,
       MUX_coreFix_memExe_lsq$getHit_1__SEL_1,
       MUX_coreFix_memExe_lsq$getHit_1__SEL_2,
       MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1,
       MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1,
       MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1,
       MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1,
       MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2,
       MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1,
       MUX_coreFix_trainBPQ_0$enq_1__SEL_1,
       MUX_coreFix_trainBPQ_1$enq_1__SEL_1,
       MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1,
       MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2,
       MUX_csrInstOrInterruptInflight_dummy2_1$write_1__SEL_2,
       MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1,
       MUX_csrf_external_int_pend_vec_1$write_1__SEL_1,
       MUX_csrf_fflags_reg$write_1__SEL_1,
       MUX_csrf_fs_reg$write_1__SEL_1,
       MUX_csrf_ie_vec_1$write_1__SEL_1,
       MUX_csrf_ie_vec_1$write_1__VAL_2,
       MUX_csrf_ie_vec_3$write_1__SEL_1,
       MUX_csrf_ie_vec_3$write_1__VAL_2,
       MUX_csrf_prev_ie_vec_1$write_1__VAL_2,
       MUX_csrf_prev_ie_vec_3$write_1__VAL_2,
       MUX_csrf_prv_reg$write_1__SEL_1,
       MUX_csrf_spp_reg$write_1__VAL_2,
       MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2,
       MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2,
       MUX_flush_reservation$write_1__SEL_1,
       MUX_flush_tlbs$write_1__SEL_1,
       MUX_rf$write_3_wr_1__PSEL_1,
       MUX_rf$write_3_wr_1__SEL_1,
       MUX_rf$write_3_wr_1__SEL_2,
       MUX_rf$write_3_wr_1__SEL_3,
       MUX_rf$write_3_wr_1__SEL_4,
       MUX_rf$write_3_wr_1__SEL_5,
       MUX_rf$write_3_wr_2__SEL_1,
       MUX_rob$setExecuted_deqLSQ_1__SEL_1,
       MUX_sbAggr$setReady_4_put_1__SEL_1,
       MUX_sbAggr$setReady_4_put_1__SEL_2,
       MUX_sbCons$setReady_3_put_1__SEL_1,
       MUX_sbCons$setReady_3_put_1__SEL_2,
       MUX_sbCons$setReady_3_put_1__SEL_3,
       MUX_update_vm_info$write_1__SEL_1;

  // remaining internal signals
  reg [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2528;
  reg [63 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281,
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q282,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q15,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q16,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q17,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q18,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q19,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q20,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q243,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q244,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q256,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q236,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q237,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q238,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q239,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q240,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q241,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10055,
	       SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2968,
	       addr__h294614,
	       curData__h195304,
	       rVal1__h615933,
	       rVal1__h640782,
	       trap_val__h709721,
	       x__h200347;
  reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10,
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q12,
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8,
	       CASE_guard08267_0b0_sfdin16487_BITS_56_TO_5_0b_ETC__q209,
	       CASE_guard08267_0b0_sfdin16487_BITS_56_TO_5_0b_ETC__q210,
	       CASE_guard17336_0b0_theResult___snd25272_BITS__ETC__q211,
	       CASE_guard17336_0b0_theResult___snd25272_BITS__ETC__q212,
	       CASE_guard37808_0b0_theResult___snd45720_BITS__ETC__q197,
	       CASE_guard37808_0b0_theResult___snd45720_BITS__ETC__q198,
	       CASE_guard47120_0b0_sfdin55340_BITS_56_TO_5_0b_ETC__q199,
	       CASE_guard47120_0b0_sfdin55340_BITS_56_TO_5_0b_ETC__q200,
	       CASE_guard56189_0b0_theResult___snd64125_BITS__ETC__q201,
	       CASE_guard56189_0b0_theResult___snd64125_BITS__ETC__q202,
	       CASE_guard77112_0b0_theResult___snd85024_BITS__ETC__q213,
	       CASE_guard77112_0b0_theResult___snd85024_BITS__ETC__q214,
	       CASE_guard86424_0b0_sfdin94644_BITS_56_TO_5_0b_ETC__q215,
	       CASE_guard86424_0b0_sfdin94644_BITS_56_TO_5_0b_ETC__q216,
	       CASE_guard95493_0b0_theResult___snd03429_BITS__ETC__q217,
	       CASE_guard95493_0b0_theResult___snd03429_BITS__ETC__q218,
	       CASE_guard98955_0b0_theResult___snd06867_BITS__ETC__q205,
	       CASE_guard98955_0b0_theResult___snd06867_BITS__ETC__q206,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985;
  reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1356,
	       SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408;
  reg [22 : 0] CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q75,
	       CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q76,
	       CASE_guard14083_0b0_sfdin22305_BITS_56_TO_34_0_ETC__q79,
	       CASE_guard14083_0b0_sfdin22305_BITS_56_TO_34_0_ETC__q80,
	       CASE_guard22919_0b0_theResult___snd30942_BITS__ETC__q81,
	       CASE_guard22919_0b0_theResult___snd30942_BITS__ETC__q82,
	       CASE_guard42141_0b0_sfdin50234_BITS_56_TO_34_0_ETC__q112,
	       CASE_guard42141_0b0_sfdin50234_BITS_56_TO_34_0_ETC__q113,
	       CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q42,
	       CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q43,
	       CASE_guard50848_0b0_theResult___snd58847_BITS__ETC__q110,
	       CASE_guard50848_0b0_theResult___snd58847_BITS__ETC__q111,
	       CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q40,
	       CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q41,
	       CASE_guard59778_0b0_sfdin68000_BITS_56_TO_34_0_ETC__q114,
	       CASE_guard59778_0b0_sfdin68000_BITS_56_TO_34_0_ETC__q115,
	       CASE_guard68386_0b0_sfdin76608_BITS_56_TO_34_0_ETC__q44,
	       CASE_guard68386_0b0_sfdin76608_BITS_56_TO_34_0_ETC__q45,
	       CASE_guard68614_0b0_theResult___snd76637_BITS__ETC__q116,
	       CASE_guard68614_0b0_theResult___snd76637_BITS__ETC__q117,
	       CASE_guard77222_0b0_theResult___snd85245_BITS__ETC__q46,
	       CASE_guard77222_0b0_theResult___snd85245_BITS__ETC__q47,
	       CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q77,
	       CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q78,
	       _theResult___fst_sfd__h350720,
	       _theResult___fst_sfd__h359443,
	       _theResult___fst_sfd__h368025,
	       _theResult___fst_sfd__h377209,
	       _theResult___fst_sfd__h385845,
	       _theResult___fst_sfd__h396419,
	       _theResult___fst_sfd__h405140,
	       _theResult___fst_sfd__h413722,
	       _theResult___fst_sfd__h422906,
	       _theResult___fst_sfd__h431542,
	       _theResult___fst_sfd__h442114,
	       _theResult___fst_sfd__h450835,
	       _theResult___fst_sfd__h459417,
	       _theResult___fst_sfd__h468601,
	       _theResult___fst_sfd__h477237;
  reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q271,
	       CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223,
	       CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268,
	       CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q277,
	       CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220,
	       CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274,
	       CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q284,
	       CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q280,
	       IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043,
	       IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13701;
  reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367,
	       SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417;
  reg [11 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q272,
	       CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q224,
	       CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q269,
	       CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q278,
	       CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221,
	       CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q275,
	       CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228,
	       IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125;
  reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11,
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7,
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9,
	       CASE_guard08267_0b0_theResult___fst_exp16493_0_ETC__q203,
	       CASE_guard08267_0b0_theResult___fst_exp16493_0_ETC__q204,
	       CASE_guard17336_0b0_theResult___fst_exp25326_0_ETC__q207,
	       CASE_guard17336_0b0_theResult___fst_exp25326_0_ETC__q208,
	       CASE_guard37808_0b0_theResult___fst_exp45769_0_ETC__q175,
	       CASE_guard37808_0b0_theResult___fst_exp45769_0_ETC__q176,
	       CASE_guard47120_0b0_theResult___fst_exp55346_0_ETC__q177,
	       CASE_guard47120_0b0_theResult___fst_exp55346_0_ETC__q178,
	       CASE_guard56189_0b0_theResult___fst_exp64179_0_ETC__q179,
	       CASE_guard56189_0b0_theResult___fst_exp64179_0_ETC__q180,
	       CASE_guard77112_0b0_theResult___fst_exp85073_0_ETC__q152,
	       CASE_guard77112_0b0_theResult___fst_exp85073_0_ETC__q153,
	       CASE_guard86424_0b0_theResult___fst_exp94650_0_ETC__q181,
	       CASE_guard86424_0b0_theResult___fst_exp94650_0_ETC__q182,
	       CASE_guard95493_0b0_theResult___fst_exp03483_0_ETC__q183,
	       CASE_guard95493_0b0_theResult___fst_exp03483_0_ETC__q184,
	       CASE_guard98955_0b0_theResult___fst_exp06916_0_ETC__q135,
	       CASE_guard98955_0b0_theResult___fst_exp06916_0_ETC__q136,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914;
  reg [7 : 0] CASE_guard05153_0b0_theResult___fst_exp13201_0_ETC__q60,
	      CASE_guard05153_0b0_theResult___fst_exp13201_0_ETC__q61,
	      CASE_guard14083_0b0_theResult___fst_exp22311_0_ETC__q68,
	      CASE_guard14083_0b0_theResult___fst_exp22311_0_ETC__q69,
	      CASE_guard22919_0b0_theResult___fst_exp30996_0_ETC__q73,
	      CASE_guard22919_0b0_theResult___fst_exp30996_0_ETC__q74,
	      CASE_guard42141_0b0_theResult___fst_exp50240_0_ETC__q97,
	      CASE_guard42141_0b0_theResult___fst_exp50240_0_ETC__q98,
	      CASE_guard50747_0b0_theResult___fst_exp58848_0_ETC__q27,
	      CASE_guard50747_0b0_theResult___fst_exp58848_0_ETC__q28,
	      CASE_guard50848_0b0_theResult___fst_exp58896_0_ETC__q95,
	      CASE_guard50848_0b0_theResult___fst_exp58896_0_ETC__q96,
	      CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q25,
	      CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q26,
	      CASE_guard59778_0b0_theResult___fst_exp68006_0_ETC__q103,
	      CASE_guard59778_0b0_theResult___fst_exp68006_0_ETC__q104,
	      CASE_guard68386_0b0_theResult___fst_exp76614_0_ETC__q33,
	      CASE_guard68386_0b0_theResult___fst_exp76614_0_ETC__q34,
	      CASE_guard68614_0b0_theResult___fst_exp76691_0_ETC__q108,
	      CASE_guard68614_0b0_theResult___fst_exp76691_0_ETC__q109,
	      CASE_guard77222_0b0_theResult___fst_exp85299_0_ETC__q38,
	      CASE_guard77222_0b0_theResult___fst_exp85299_0_ETC__q39,
	      CASE_guard96446_0b0_theResult___fst_exp04545_0_ETC__q62,
	      CASE_guard96446_0b0_theResult___fst_exp04545_0_ETC__q63,
	      SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381,
	      SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430,
	      _theResult___fst_exp__h350719,
	      _theResult___fst_exp__h359442,
	      _theResult___fst_exp__h368024,
	      _theResult___fst_exp__h377208,
	      _theResult___fst_exp__h385844,
	      _theResult___fst_exp__h396418,
	      _theResult___fst_exp__h405139,
	      _theResult___fst_exp__h413721,
	      _theResult___fst_exp__h422905,
	      _theResult___fst_exp__h431541,
	      _theResult___fst_exp__h442113,
	      _theResult___fst_exp__h450834,
	      _theResult___fst_exp__h459416,
	      _theResult___fst_exp__h468600,
	      _theResult___fst_exp__h477236;
  reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q266,
	      CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1,
	      CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q263,
	      IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778;
  reg [4 : 0] IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14231,
	      IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14394;
  reg [3 : 0] CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2956__ETC__q227,
	      CASE_checkForException_3160_BITS_3_TO_0_0_chec_ETC__q226,
	      CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q13,
	      CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q14,
	      CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q265,
	      CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264,
	      CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q260,
	      CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q261,
	      IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14234,
	      IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13266,
	      IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14395,
	      i__h708713,
	      i__h708873;
  reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q270,
	      CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222,
	      CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267,
	      CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q276,
	      CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219,
	      CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q273,
	      CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283,
	      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242,
	      CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279,
	      CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255,
	      CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225,
	      CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229,
	      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828,
	      x__h290393,
	      x__h296163;
  reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250,
	      CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q285,
	      CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253,
	      CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q257,
	      CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248;
  reg CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196,
      CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q252,
      CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251,
      CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258,
      CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259,
      CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254,
      CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249,
      CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q234,
      CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233,
      CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230,
      CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231,
      CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235,
      CASE_guard05153_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86,
      CASE_guard05153_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85,
      CASE_guard08267_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139,
      CASE_guard14083_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88,
      CASE_guard14083_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87,
      CASE_guard17336_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141,
      CASE_guard22919_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90,
      CASE_guard22919_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89,
      CASE_guard37808_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193,
      CASE_guard37808_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187,
      CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118,
      CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119,
      CASE_guard47120_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191,
      CASE_guard47120_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185,
      CASE_guard50747_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49,
      CASE_guard50747_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48,
      CASE_guard50848_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121,
      CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120,
      CASE_guard56189_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195,
      CASE_guard56189_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189,
      CASE_guard59456_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51,
      CASE_guard59456_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50,
      CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123,
      CASE_guard59778_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122,
      CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53,
      CASE_guard68386_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52,
      CASE_guard68614_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125,
      CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124,
      CASE_guard77112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162,
      CASE_guard77112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156,
      CASE_guard77222_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55,
      CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54,
      CASE_guard86424_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160,
      CASE_guard86424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154,
      CASE_guard95493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164,
      CASE_guard95493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158,
      CASE_guard96446_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84,
      CASE_guard96446_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83,
      CASE_guard98955_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137,
      CASE_k75032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232,
      IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542,
      IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555,
      IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559,
      IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572,
      IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585,
      IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598,
      IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605,
      IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6608,
      IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615,
      IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622,
      IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150,
      IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163,
      IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5167,
      IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180,
      IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193,
      IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206,
      IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213,
      IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216,
      IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223,
      IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230,
      IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934,
      IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947,
      IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7951,
      IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964,
      IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977,
      IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990,
      IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997,
      IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8000,
      IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007,
      IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014,
      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10965,
      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d11001,
      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d11049,
      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d11091,
      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d11133,
      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8507,
      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8520,
      IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580,
      IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636,
      IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14225,
      IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14228,
      IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13584,
      IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608,
      IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13641,
      IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13950,
      IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13971,
      IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13988,
      IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14041,
      IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14043,
      IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14057,
      IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14064,
      IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14133,
      IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14144,
      IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14392,
      IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14393,
      IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13999,
      IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14130,
      IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14155,
      SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601,
      SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14091,
      SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568,
      SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13877;
  wire [581 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3343;
  wire [569 : 0] IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2538,
		 IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2549,
		 IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2551,
		 IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2550;
  wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3038;
  wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2236,
		 SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3031,
		 SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15309;
  wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2033;
  wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2231,
		 SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3022,
		 SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15300;
  wire [321 : 0] basicExec___d12101, basicExec___d12775;
  wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2028;
  wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2226,
		 SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3013,
		 SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15291,
		 SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11187,
		 SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11200,
		 _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11193;
  wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2023;
  wire [181 : 0] fetchStage_pipelines_0_first__2928_BIT_173_304_ETC___d13522;
  wire [127 : 0] b__h608522, b__h608598, b__h608699, b__h608711, x__h609551;
  wire [68 : 0] execFpuSimple___d11167;
  wire [65 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627;
  wire [64 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2598;
  wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9284,
		IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12616,
		IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12617,
		IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12625,
		IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12626,
		IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11942,
		IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11943,
		IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11951,
		IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11952,
		IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8453,
		IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8454,
		IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8461,
		IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8462,
		IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8469,
		IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8470,
		IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1678,
		IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1679,
		IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1686,
		IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1687,
		IF_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_d_ETC___d11255,
		IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10051,
		IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10765,
		IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9285,
		IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9995,
		IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2595,
		IF_coreFix_memExe_lsq_firstLd__285_BIT_94_360__ETC___d1385,
		IF_coreFix_memExe_lsq_firstLd__285_BIT_94_360__ETC___d1434,
		IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1386,
		IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1435,
		IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8,
		IF_rob_deqPort_0_canDeq__4995_THEN_IF_NOT_rob__ETC___d15104,
		_theResult___fst__h608922,
		_theResult___snd__h608923,
		a___1__h608536,
		a___1__h608927,
		a__h608374,
		amoExec___d882,
		b___1__h608537,
		b___1__h608988,
		b__h608375,
		base__h711621,
		base__h711641,
		coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11256,
		coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11257,
		data___1__h479775,
		data___1__h480707,
		data__h479263,
		data__h480195,
		fallthrough_pc__h671324,
		fallthrough_pc__h687070,
		fcsr_csr__read__h616235,
		fflags_csr__read__h616210,
		frm_csr__read__h616221,
		mcause_csr__read__h617877,
		mcounteren_csr__read__h617622,
		medeleg_csr__read__h617229,
		mideleg_csr__read__h617324,
		mie_csr__read__h617448,
		mip_csr__read__h618110,
		mstatus_csr__read__h617081,
		mtvec_csr__read__h617530,
		n___1__h201750,
		n__h196842,
		n__read__h618214,
		n__read__h618405,
		n__read__h6331,
		n__read__h720316,
		next_pc__h719526,
		q___1__h480782,
		rVal1__h487144,
		rVal2__h487145,
		r___1__h480809,
		res_data__h342521,
		res_data__h342526,
		res_data__h388223,
		res_data__h388228,
		res_data__h433918,
		res_data__h433923,
		resp_addr__h296629,
		rg_tdata1__read__h619065,
		rob_deqPort_0_deq_data__4466_BITS_353_TO_290_4_ETC___d14968,
		robdeqPort_0_deq_data_BITS_95_TO_32__q262,
		satp_csr__read__h616938,
		scause_csr__read__h616735,
		scounteren_csr__read__h616597,
		shiftData__h184743,
		sie_csr__read__h616501,
		sip_csr__read__h616875,
		sstatus_csr__read__h616431,
		stvec_csr__read__h616544,
		upd__h3681,
		upd__h4998,
		v__h614705,
		v__h639708,
		vaddr__h184738,
		x__h155098,
		x__h158645,
		x__h161459,
		x__h163307,
		x__h17933,
		x__h184650,
		x__h184651,
		x__h20471,
		x__h291838,
		x__h293692,
		x__h45840,
		x__h48376,
		x__h487050,
		x__h487051,
		x__h487052,
		x__h608911,
		x__h623649,
		x__h623650,
		x__h646279,
		x__h646280,
		x__h705027,
		x_addr__h318726,
		x_quotient__h479959,
		x_reg_ifc__read__h616340,
		x_remainder__h479960,
		y__h626451,
		y__h648788,
		y__h723410,
		y_avValue__h183778,
		y_avValue__h184497,
		y_avValue__h484113,
		y_avValue__h484834,
		y_avValue__h485549,
		y_avValue__h615876,
		y_avValue__h621659,
		y_avValue__h640727,
		y_avValue__h644299,
		y_avValue_new_pc__h711402,
		y_avValue_new_pc__h711588,
		y_avValue_snd_snd_snd_snd_snd__h722804,
		y_avValue_snd_snd_snd_snd_snd__h723463,
		y_avValue_snd_snd_snd_snd_snd__h723492;
  wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10763,
		IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9993,
		r1__read__h619390,
		r1__read__h619794,
		r1__read__h620304,
		r1__read__h620309,
		r1__read__h620328,
		r1__read__h620561,
		r1__read__h620727,
		r1__read__h620820,
		r1__read__h620825,
		r1__read__h620844;
  wire [61 : 0] r1__read__h619392,
		r1__read__h619796,
		r1__read__h620311,
		r1__read__h620330,
		r1__read__h620563,
		r1__read__h620703,
		r1__read__h620729,
		r1__read__h620827,
		r1__read__h620846;
  wire [60 : 0] r1__read__h620565,
		r1__read__h620705,
		r1__read__h620731,
		r1__read__h620848;
  wire [59 : 0] r1__read__h619394,
		r1__read__h619798,
		r1__read__h620322,
		r1__read__h620332,
		r1__read__h620567,
		r1__read__h620733,
		r1__read__h620838,
		r1__read__h620850;
  wire [58 : 0] r1__read__h619396,
		r1__read__h619800,
		r1__read__h620334,
		r1__read__h620569,
		r1__read__h620735,
		r1__read__h620852;
  wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2578,
		IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3108,
		IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2787,
		r1__read__h619398,
		r1__read__h619802,
		r1__read__h620336,
		r1__read__h620571,
		r1__read__h620707,
		r1__read__h620737,
		r1__read__h620854,
		y__h258435;
  wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21,
		IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q56,
		IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q91,
		IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q130,
		IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q147,
		IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q170,
		IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q101,
		IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q31,
		IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q66,
		IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q126,
		IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q133,
		IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q143,
		IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q150,
		IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q166,
		IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q173,
		IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q106,
		IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q23,
		IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q36,
		IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q58,
		IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q71,
		IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q93,
		_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10249,
		_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8764,
		_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9479,
		_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4654,
		_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6046,
		_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7438,
		_theResult____h350737,
		_theResult____h368376,
		_theResult____h396436,
		_theResult____h414073,
		_theResult____h442131,
		_theResult____h459768,
		_theResult____h508257,
		_theResult____h547110,
		_theResult____h586414,
		_theResult___snd__h358859,
		_theResult___snd__h358870,
		_theResult___snd__h358872,
		_theResult___snd__h358882,
		_theResult___snd__h358888,
		_theResult___snd__h358911,
		_theResult___snd__h367455,
		_theResult___snd__h367457,
		_theResult___snd__h367464,
		_theResult___snd__h367470,
		_theResult___snd__h367493,
		_theResult___snd__h376625,
		_theResult___snd__h376636,
		_theResult___snd__h376638,
		_theResult___snd__h376648,
		_theResult___snd__h376654,
		_theResult___snd__h376677,
		_theResult___snd__h385245,
		_theResult___snd__h385259,
		_theResult___snd__h385265,
		_theResult___snd__h385283,
		_theResult___snd__h404556,
		_theResult___snd__h404567,
		_theResult___snd__h404569,
		_theResult___snd__h404579,
		_theResult___snd__h404585,
		_theResult___snd__h404608,
		_theResult___snd__h413152,
		_theResult___snd__h413154,
		_theResult___snd__h413161,
		_theResult___snd__h413167,
		_theResult___snd__h413190,
		_theResult___snd__h422322,
		_theResult___snd__h422333,
		_theResult___snd__h422335,
		_theResult___snd__h422345,
		_theResult___snd__h422351,
		_theResult___snd__h422374,
		_theResult___snd__h430942,
		_theResult___snd__h430956,
		_theResult___snd__h430962,
		_theResult___snd__h430980,
		_theResult___snd__h450251,
		_theResult___snd__h450262,
		_theResult___snd__h450264,
		_theResult___snd__h450274,
		_theResult___snd__h450280,
		_theResult___snd__h450303,
		_theResult___snd__h458847,
		_theResult___snd__h458849,
		_theResult___snd__h458856,
		_theResult___snd__h458862,
		_theResult___snd__h458885,
		_theResult___snd__h468017,
		_theResult___snd__h468028,
		_theResult___snd__h468030,
		_theResult___snd__h468040,
		_theResult___snd__h468046,
		_theResult___snd__h468069,
		_theResult___snd__h476637,
		_theResult___snd__h476651,
		_theResult___snd__h476657,
		_theResult___snd__h476675,
		_theResult___snd__h506867,
		_theResult___snd__h506869,
		_theResult___snd__h506876,
		_theResult___snd__h506882,
		_theResult___snd__h506905,
		_theResult___snd__h516504,
		_theResult___snd__h516515,
		_theResult___snd__h516517,
		_theResult___snd__h516527,
		_theResult___snd__h516533,
		_theResult___snd__h516556,
		_theResult___snd__h525272,
		_theResult___snd__h525286,
		_theResult___snd__h525292,
		_theResult___snd__h525310,
		_theResult___snd__h545720,
		_theResult___snd__h545722,
		_theResult___snd__h545729,
		_theResult___snd__h545735,
		_theResult___snd__h545758,
		_theResult___snd__h555357,
		_theResult___snd__h555368,
		_theResult___snd__h555370,
		_theResult___snd__h555380,
		_theResult___snd__h555386,
		_theResult___snd__h555409,
		_theResult___snd__h564125,
		_theResult___snd__h564139,
		_theResult___snd__h564145,
		_theResult___snd__h564163,
		_theResult___snd__h585024,
		_theResult___snd__h585026,
		_theResult___snd__h585033,
		_theResult___snd__h585039,
		_theResult___snd__h585062,
		_theResult___snd__h594661,
		_theResult___snd__h594672,
		_theResult___snd__h594674,
		_theResult___snd__h594684,
		_theResult___snd__h594690,
		_theResult___snd__h594713,
		_theResult___snd__h603429,
		_theResult___snd__h603443,
		_theResult___snd__h603449,
		_theResult___snd__h603467,
		r1__read__h620573,
		r1__read__h620709,
		r1__read__h620739,
		r1__read__h620856,
		result__h368989,
		result__h414686,
		result__h460381,
		result__h508870,
		result__h547723,
		result__h587027,
		sfd__h343132,
		sfd__h388834,
		sfd__h434529,
		sfd__h487890,
		sfd__h526884,
		sfd__h566188,
		sfdin__h358842,
		sfdin__h376608,
		sfdin__h404539,
		sfdin__h422305,
		sfdin__h450234,
		sfdin__h468000,
		sfdin__h516487,
		sfdin__h555340,
		sfdin__h594644,
		x__h369086,
		x__h414783,
		x__h460478,
		x__h508965,
		x__h547818,
		x__h587122;
  wire [55 : 0] r1__read__h619400,
		r1__read__h619804,
		r1__read__h620338,
		r1__read__h620575,
		r1__read__h620741,
		r1__read__h620858;
  wire [54 : 0] r1__read__h619402,
		r1__read__h619806,
		r1__read__h620340,
		r1__read__h620577,
		r1__read__h620743,
		r1__read__h620860;
  wire [53 : 0] r1__read__h620686,
		r1__read__h620711,
		r1__read__h620745,
		r1__read__h620862,
		sfd__h506934,
		sfd__h516585,
		sfd__h525345,
		sfd__h545787,
		sfd__h555438,
		sfd__h564198,
		sfd__h585091,
		sfd__h594742,
		sfd__h603502,
		value__h351359,
		value__h397056,
		value__h442751;
  wire [52 : 0] r1__read__h620579,
		r1__read__h620688,
		r1__read__h620713,
		r1__read__h620747,
		r1__read__h620864;
  wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10730,
		IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10732,
		IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251,
		IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9253,
		IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9960,
		IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9962,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10704,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10706,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10749,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10751,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9224,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9226,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9270,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9272,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9934,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9936,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9979,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9981,
		IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762,
		IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9283,
		IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9992,
		_theResult___fst_sfd__h491844,
		_theResult___fst_sfd__h507672,
		_theResult___fst_sfd__h507675,
		_theResult___fst_sfd__h517323,
		_theResult___fst_sfd__h517326,
		_theResult___fst_sfd__h526107,
		_theResult___fst_sfd__h526110,
		_theResult___fst_sfd__h526119,
		_theResult___fst_sfd__h526125,
		_theResult___fst_sfd__h530697,
		_theResult___fst_sfd__h546525,
		_theResult___fst_sfd__h546528,
		_theResult___fst_sfd__h556176,
		_theResult___fst_sfd__h556179,
		_theResult___fst_sfd__h564960,
		_theResult___fst_sfd__h564963,
		_theResult___fst_sfd__h564972,
		_theResult___fst_sfd__h564978,
		_theResult___fst_sfd__h570001,
		_theResult___fst_sfd__h585829,
		_theResult___fst_sfd__h585832,
		_theResult___fst_sfd__h595480,
		_theResult___fst_sfd__h595483,
		_theResult___fst_sfd__h604264,
		_theResult___fst_sfd__h604267,
		_theResult___fst_sfd__h604276,
		_theResult___fst_sfd__h604282,
		_theResult___sfd__h507572,
		_theResult___sfd__h517223,
		_theResult___sfd__h526007,
		_theResult___sfd__h546425,
		_theResult___sfd__h556076,
		_theResult___sfd__h564860,
		_theResult___sfd__h585729,
		_theResult___sfd__h595380,
		_theResult___sfd__h604164,
		_theResult___snd_fst_sfd__h487844,
		_theResult___snd_fst_sfd__h507678,
		_theResult___snd_fst_sfd__h526113,
		_theResult___snd_fst_sfd__h526838,
		_theResult___snd_fst_sfd__h546531,
		_theResult___snd_fst_sfd__h564966,
		_theResult___snd_fst_sfd__h566142,
		_theResult___snd_fst_sfd__h585835,
		_theResult___snd_fst_sfd__h604270,
		out___1_sfd__h487592,
		out___1_sfd__h526586,
		out___1_sfd__h565890,
		out_sfd__h507575,
		out_sfd__h517226,
		out_sfd__h526010,
		out_sfd__h546428,
		out_sfd__h556079,
		out_sfd__h564863,
		out_sfd__h585732,
		out_sfd__h595383,
		out_sfd__h604167;
  wire [50 : 0] r1__read__h619404, r1__read__h620581;
  wire [49 : 0] r1__read__h620690;
  wire [48 : 0] r1__read__h619406, r1__read__h620583, r1__read__h620692;
  wire [46 : 0] r1__read__h619408, r1__read__h620585;
  wire [45 : 0] r1__read__h619410, r1__read__h620587;
  wire [44 : 0] r1__read__h619412, r1__read__h620589;
  wire [43 : 0] r1__read__h619414, r1__read__h620591;
  wire [42 : 0] r1__read__h620593;
  wire [41 : 0] r1__read__h620595;
  wire [40 : 0] r1__read__h620597;
  wire [37 : 0] IF_fetchStage_pipelines_0_first__2928_BIT_160__ETC___d14237,
		IF_fetchStage_pipelines_1_first__2937_BIT_160__ETC___d14398;
  wire [31 : 0] coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4,
		coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q3,
		coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q5,
		data79263_BITS_31_TO_0__q2,
		data80195_BITS_31_TO_0__q6,
		imm__h661845,
		r1__read__h619416,
		r1__read__h620599,
		x__h196067,
		x__h342536,
		x__h388238,
		x__h433933,
		x__h75785,
		x_data__h65634,
		x_data_imm__h682377,
		x_data_imm__h698281;
  wire [29 : 0] r1__read__h619418, r1__read__h620601;
  wire [27 : 0] r1__read__h620603;
  wire [24 : 0] NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14283,
		sfd__h358940,
		sfd__h367522,
		sfd__h376706,
		sfd__h385318,
		sfd__h404637,
		sfd__h413219,
		sfd__h422403,
		sfd__h431015,
		sfd__h450332,
		sfd__h458914,
		sfd__h468098,
		sfd__h476710,
		value__h492473,
		value__h531326,
		value__h570630;
  wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053,
		IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055,
		IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445,
		IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447,
		IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7837,
		IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7839,
		IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5099,
		IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5101,
		IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6491,
		IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6493,
		IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7883,
		IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7885,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6466,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6510,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6512,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7856,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902,
		IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904,
		_theResult___fst_sfd__h359446,
		_theResult___fst_sfd__h368028,
		_theResult___fst_sfd__h377212,
		_theResult___fst_sfd__h385848,
		_theResult___fst_sfd__h385857,
		_theResult___fst_sfd__h385863,
		_theResult___fst_sfd__h405143,
		_theResult___fst_sfd__h413725,
		_theResult___fst_sfd__h422909,
		_theResult___fst_sfd__h431545,
		_theResult___fst_sfd__h431554,
		_theResult___fst_sfd__h431560,
		_theResult___fst_sfd__h450838,
		_theResult___fst_sfd__h459420,
		_theResult___fst_sfd__h468604,
		_theResult___fst_sfd__h477240,
		_theResult___fst_sfd__h477249,
		_theResult___fst_sfd__h477255,
		_theResult___sfd__h359365,
		_theResult___sfd__h367947,
		_theResult___sfd__h377131,
		_theResult___sfd__h385767,
		_theResult___sfd__h385869,
		_theResult___sfd__h405062,
		_theResult___sfd__h413644,
		_theResult___sfd__h422828,
		_theResult___sfd__h431464,
		_theResult___sfd__h431566,
		_theResult___sfd__h450757,
		_theResult___sfd__h459339,
		_theResult___sfd__h468523,
		_theResult___sfd__h477159,
		_theResult___sfd__h477261,
		_theResult___snd_fst_sfd__h343082,
		_theResult___snd_fst_sfd__h368031,
		_theResult___snd_fst_sfd__h385851,
		_theResult___snd_fst_sfd__h388784,
		_theResult___snd_fst_sfd__h413728,
		_theResult___snd_fst_sfd__h431548,
		_theResult___snd_fst_sfd__h434479,
		_theResult___snd_fst_sfd__h459423,
		_theResult___snd_fst_sfd__h477243,
		f1_sfd__h487529,
		f2_sfd__h526523,
		f3_sfd__h565827,
		out_f_sfd__h386146,
		out_f_sfd__h431843,
		out_f_sfd__h477538,
		out_sfd__h359368,
		out_sfd__h367950,
		out_sfd__h377134,
		out_sfd__h385770,
		out_sfd__h405065,
		out_sfd__h413647,
		out_sfd__h422831,
		out_sfd__h431467,
		out_sfd__h450760,
		out_sfd__h459342,
		out_sfd__h468526,
		out_sfd__h477162;
  wire [19 : 0] r1__read__h620538;
  wire [12 : 0] fetchStage_pipelines_1_first__2937_BIT_173_370_ETC___d13785;
  wire [11 : 0] IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992,
		IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10542,
		IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9057,
		IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9772,
		IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869,
		SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10242,
		SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8757,
		SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9472,
		SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129,
		SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q146,
		SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169,
		SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6039,
		SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65,
		SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4647,
		SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30,
		SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7431,
		SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100,
		_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4107,
		_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5499,
		_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6891,
		_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10245,
		_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8760,
		_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9475,
		_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10120,
		_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8620,
		_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9350,
		_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650,
		_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042,
		_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434,
		_theResult____h658034,
		csr_addr__h661843,
		enabled_ints___1__h658447,
		enabled_ints__h658493,
		pend_ints__h658032,
		renaming_spec_bits__h690496,
		result__h653741,
		result__h653792,
		spec_bits__h693623,
		w__h653736,
		x__h369119,
		x__h414816,
		x__h460511,
		x__h508998,
		x__h547851,
		x__h587155,
		x__h653740,
		x__h653791,
		y__h653770,
		y__h658459,
		y__h693636,
		y_avValue_fst__h686920,
		y_avValue_snd_fst__h687194,
		y_avValue_snd_fst__h687229;
  wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10647,
		IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10649,
		IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9167,
		IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9169,
		IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9877,
		IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9879,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10609,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10611,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10678,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10680,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9124,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9126,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9198,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9200,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9839,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9841,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9908,
		IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9910,
		SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q132,
		SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q149,
		SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q172,
		_theResult___exp__h507571,
		_theResult___exp__h517222,
		_theResult___exp__h526006,
		_theResult___exp__h546424,
		_theResult___exp__h556075,
		_theResult___exp__h564859,
		_theResult___exp__h585728,
		_theResult___exp__h595379,
		_theResult___exp__h604163,
		_theResult___fst_exp__h491843,
		_theResult___fst_exp__h506907,
		_theResult___fst_exp__h506913,
		_theResult___fst_exp__h506916,
		_theResult___fst_exp__h507671,
		_theResult___fst_exp__h507674,
		_theResult___fst_exp__h516493,
		_theResult___fst_exp__h516558,
		_theResult___fst_exp__h516564,
		_theResult___fst_exp__h516567,
		_theResult___fst_exp__h517322,
		_theResult___fst_exp__h517325,
		_theResult___fst_exp__h525278,
		_theResult___fst_exp__h525317,
		_theResult___fst_exp__h525323,
		_theResult___fst_exp__h525326,
		_theResult___fst_exp__h526106,
		_theResult___fst_exp__h526109,
		_theResult___fst_exp__h526118,
		_theResult___fst_exp__h526121,
		_theResult___fst_exp__h530696,
		_theResult___fst_exp__h545760,
		_theResult___fst_exp__h545766,
		_theResult___fst_exp__h545769,
		_theResult___fst_exp__h546524,
		_theResult___fst_exp__h546527,
		_theResult___fst_exp__h555346,
		_theResult___fst_exp__h555411,
		_theResult___fst_exp__h555417,
		_theResult___fst_exp__h555420,
		_theResult___fst_exp__h556175,
		_theResult___fst_exp__h556178,
		_theResult___fst_exp__h564131,
		_theResult___fst_exp__h564170,
		_theResult___fst_exp__h564176,
		_theResult___fst_exp__h564179,
		_theResult___fst_exp__h564959,
		_theResult___fst_exp__h564962,
		_theResult___fst_exp__h564971,
		_theResult___fst_exp__h564974,
		_theResult___fst_exp__h570000,
		_theResult___fst_exp__h585064,
		_theResult___fst_exp__h585070,
		_theResult___fst_exp__h585073,
		_theResult___fst_exp__h585828,
		_theResult___fst_exp__h585831,
		_theResult___fst_exp__h594650,
		_theResult___fst_exp__h594715,
		_theResult___fst_exp__h594721,
		_theResult___fst_exp__h594724,
		_theResult___fst_exp__h595479,
		_theResult___fst_exp__h595482,
		_theResult___fst_exp__h603435,
		_theResult___fst_exp__h603474,
		_theResult___fst_exp__h603480,
		_theResult___fst_exp__h603483,
		_theResult___fst_exp__h604263,
		_theResult___fst_exp__h604266,
		_theResult___fst_exp__h604275,
		_theResult___fst_exp__h604278,
		_theResult___snd_fst_exp__h507677,
		_theResult___snd_fst_exp__h526112,
		_theResult___snd_fst_exp__h546530,
		_theResult___snd_fst_exp__h564965,
		_theResult___snd_fst_exp__h585834,
		_theResult___snd_fst_exp__h604269,
		coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q64,
		coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q29,
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q99,
		din_inc___2_exp__h526166,
		din_inc___2_exp__h526201,
		din_inc___2_exp__h526227,
		din_inc___2_exp__h565019,
		din_inc___2_exp__h565054,
		din_inc___2_exp__h565080,
		din_inc___2_exp__h604323,
		din_inc___2_exp__h604358,
		din_inc___2_exp__h604384,
		out_exp__h507574,
		out_exp__h517225,
		out_exp__h526009,
		out_exp__h546427,
		out_exp__h556078,
		out_exp__h564862,
		out_exp__h585731,
		out_exp__h595382,
		out_exp__h604166;
  wire [9 : 0] r1__read_BITS_9_TO_0___h658469;
  wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4968,
	       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360,
	       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752;
  wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4406,
	       IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4409,
	       IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5798,
	       IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5801,
	       IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7190,
	       IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7193,
	       IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4953,
	       IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4955,
	       IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6345,
	       IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6347,
	       IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7737,
	       IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7739,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6020,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6022,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7412,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7414,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806,
	       IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808,
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q70,
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q35,
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q105,
	       _theResult___exp__h359364,
	       _theResult___exp__h367946,
	       _theResult___exp__h377130,
	       _theResult___exp__h385766,
	       _theResult___exp__h385868,
	       _theResult___exp__h405061,
	       _theResult___exp__h413643,
	       _theResult___exp__h422827,
	       _theResult___exp__h431463,
	       _theResult___exp__h431565,
	       _theResult___exp__h450756,
	       _theResult___exp__h459338,
	       _theResult___exp__h468522,
	       _theResult___exp__h477158,
	       _theResult___exp__h477260,
	       _theResult___fst_exp__h358848,
	       _theResult___fst_exp__h358913,
	       _theResult___fst_exp__h358919,
	       _theResult___fst_exp__h358922,
	       _theResult___fst_exp__h359445,
	       _theResult___fst_exp__h367495,
	       _theResult___fst_exp__h367501,
	       _theResult___fst_exp__h367504,
	       _theResult___fst_exp__h368027,
	       _theResult___fst_exp__h376614,
	       _theResult___fst_exp__h376679,
	       _theResult___fst_exp__h376685,
	       _theResult___fst_exp__h376688,
	       _theResult___fst_exp__h377211,
	       _theResult___fst_exp__h385251,
	       _theResult___fst_exp__h385290,
	       _theResult___fst_exp__h385296,
	       _theResult___fst_exp__h385299,
	       _theResult___fst_exp__h385847,
	       _theResult___fst_exp__h385856,
	       _theResult___fst_exp__h385859,
	       _theResult___fst_exp__h404545,
	       _theResult___fst_exp__h404610,
	       _theResult___fst_exp__h404616,
	       _theResult___fst_exp__h404619,
	       _theResult___fst_exp__h405142,
	       _theResult___fst_exp__h413192,
	       _theResult___fst_exp__h413198,
	       _theResult___fst_exp__h413201,
	       _theResult___fst_exp__h413724,
	       _theResult___fst_exp__h422311,
	       _theResult___fst_exp__h422376,
	       _theResult___fst_exp__h422382,
	       _theResult___fst_exp__h422385,
	       _theResult___fst_exp__h422908,
	       _theResult___fst_exp__h430948,
	       _theResult___fst_exp__h430987,
	       _theResult___fst_exp__h430993,
	       _theResult___fst_exp__h430996,
	       _theResult___fst_exp__h431544,
	       _theResult___fst_exp__h431553,
	       _theResult___fst_exp__h431556,
	       _theResult___fst_exp__h450240,
	       _theResult___fst_exp__h450305,
	       _theResult___fst_exp__h450311,
	       _theResult___fst_exp__h450314,
	       _theResult___fst_exp__h450837,
	       _theResult___fst_exp__h458887,
	       _theResult___fst_exp__h458893,
	       _theResult___fst_exp__h458896,
	       _theResult___fst_exp__h459419,
	       _theResult___fst_exp__h468006,
	       _theResult___fst_exp__h468071,
	       _theResult___fst_exp__h468077,
	       _theResult___fst_exp__h468080,
	       _theResult___fst_exp__h468603,
	       _theResult___fst_exp__h476643,
	       _theResult___fst_exp__h476682,
	       _theResult___fst_exp__h476688,
	       _theResult___fst_exp__h476691,
	       _theResult___fst_exp__h477239,
	       _theResult___fst_exp__h477248,
	       _theResult___fst_exp__h477251,
	       _theResult___snd_fst_exp__h368030,
	       _theResult___snd_fst_exp__h385850,
	       _theResult___snd_fst_exp__h413727,
	       _theResult___snd_fst_exp__h431547,
	       _theResult___snd_fst_exp__h459422,
	       _theResult___snd_fst_exp__h477242,
	       csrf_external_int_en_vec_3_read__1844_AND_csrf_ETC___d12967,
	       din_inc___2_exp__h385881,
	       din_inc___2_exp__h385905,
	       din_inc___2_exp__h385935,
	       din_inc___2_exp__h385959,
	       din_inc___2_exp__h431578,
	       din_inc___2_exp__h431602,
	       din_inc___2_exp__h431632,
	       din_inc___2_exp__h431656,
	       din_inc___2_exp__h477273,
	       din_inc___2_exp__h477297,
	       din_inc___2_exp__h477327,
	       din_inc___2_exp__h477351,
	       f1_exp87528_MINUS_127__q128,
	       f1_exp__h487528,
	       f2_exp26522_MINUS_127__q168,
	       f2_exp__h526522,
	       f3_exp65826_MINUS_127__q145,
	       f3_exp__h565826,
	       out_exp__h359367,
	       out_exp__h367949,
	       out_exp__h377133,
	       out_exp__h385769,
	       out_exp__h405064,
	       out_exp__h413646,
	       out_exp__h422830,
	       out_exp__h431466,
	       out_exp__h450759,
	       out_exp__h459341,
	       out_exp__h468525,
	       out_exp__h477161,
	       out_f_exp__h386145,
	       out_f_exp__h431842,
	       out_f_exp__h477537,
	       x__h619375;
  wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343,
	       IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735,
	       IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127,
	       IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10491,
	       IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9006,
	       IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9721,
	       IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4894,
	       IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286,
	       IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9424,
	       IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463,
	       IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172,
	       IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766,
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966,
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574,
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358,
	       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2172,
	       SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15335,
	       x__h184872,
	       x__h711636;
  wire [4 : 0] IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14451,
	       IF_rob_deqPort_0_canDeq__4995_THEN_IF_NOT_rob__ETC___d15194,
	       _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5265,
	       _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6657,
	       _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8049,
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869,
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910,
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954,
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294,
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686,
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078,
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852,
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893,
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937,
	       _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5277,
	       _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6669,
	       _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8061,
	       checkForException___d13160,
	       checkForException___d13807,
	       fflags__h723387,
	       r1__read__h620945,
	       res_fflags__h342522,
	       res_fflags__h388224,
	       res_fflags__h433919,
	       rs1__h661844,
	       x__h155092,
	       x__h158639,
	       x__h161455,
	       x__h291826,
	       y_avValue_fst__h722364,
	       y_avValue_fst__h723306,
	       y_avValue_fst__h723334;
  wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1875,
	       IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1877,
	       IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1879,
	       IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1881,
	       IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1883,
	       IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1885,
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13334,
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13335,
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13336,
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13337,
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13338,
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13339,
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13340,
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13341,
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13342,
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13343,
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13344,
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13345,
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13346,
	       IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3__ETC___d13368,
	       IF_NOT_coreFix_memExe_dTlb_procResp__740_BIT_1_ETC___d1819,
	       IF_checkForException_3160_BIT_4_3161_THEN_IF_c_ETC___d13295,
	       IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2929,
	       IF_coreFix_memExe_dTlb_procResp__740_BITS_105__ETC___d1820,
	       IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1263,
	       IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13385,
	       cause_code__h708698,
	       vm_mode_reg__read__h620544;
  wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567,
	       IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2886,
	       IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1220,
	       _theResult_____2__h301173,
	       next_deqP___1__h301452,
	       v__h300593,
	       v__h300824,
	       x__h306803,
	       x_decodeInfo_frm__h661528;
  wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2882,
	       IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1216,
	       IF_rob_deqPort_0_canDeq__4995_THEN_IF_NOT_rob__ETC___d15216,
	       IF_sfdin04539_BIT_33_THEN_2_ELSE_0__q57,
	       IF_sfdin16487_BIT_4_THEN_2_ELSE_0__q131,
	       IF_sfdin22305_BIT_33_THEN_2_ELSE_0__q67,
	       IF_sfdin50234_BIT_33_THEN_2_ELSE_0__q92,
	       IF_sfdin55340_BIT_4_THEN_2_ELSE_0__q171,
	       IF_sfdin58842_BIT_33_THEN_2_ELSE_0__q22,
	       IF_sfdin68000_BIT_33_THEN_2_ELSE_0__q102,
	       IF_sfdin76608_BIT_33_THEN_2_ELSE_0__q32,
	       IF_sfdin94644_BIT_4_THEN_2_ELSE_0__q148,
	       IF_theResult___snd03429_BIT_4_THEN_2_ELSE_0__q151,
	       IF_theResult___snd06867_BIT_4_THEN_2_ELSE_0__q127,
	       IF_theResult___snd13152_BIT_33_THEN_2_ELSE_0__q59,
	       IF_theResult___snd25272_BIT_4_THEN_2_ELSE_0__q134,
	       IF_theResult___snd30942_BIT_33_THEN_2_ELSE_0__q72,
	       IF_theResult___snd45720_BIT_4_THEN_2_ELSE_0__q167,
	       IF_theResult___snd58847_BIT_33_THEN_2_ELSE_0__q94,
	       IF_theResult___snd64125_BIT_4_THEN_2_ELSE_0__q174,
	       IF_theResult___snd67455_BIT_33_THEN_2_ELSE_0__q24,
	       IF_theResult___snd76637_BIT_33_THEN_2_ELSE_0__q107,
	       IF_theResult___snd85024_BIT_4_THEN_2_ELSE_0__q144,
	       IF_theResult___snd85245_BIT_33_THEN_2_ELSE_0__q37,
	       guard__h350747,
	       guard__h359456,
	       guard__h368386,
	       guard__h377222,
	       guard__h396446,
	       guard__h405153,
	       guard__h414083,
	       guard__h422919,
	       guard__h442141,
	       guard__h450848,
	       guard__h459778,
	       guard__h468614,
	       guard__h498955,
	       guard__h508267,
	       guard__h517336,
	       guard__h537808,
	       guard__h547120,
	       guard__h556189,
	       guard__h577112,
	       guard__h586424,
	       guard__h595493,
	       prv__h724902,
	       prv__h724946,
	       r1__read_BITS_13_TO_12___h661713,
	       sbIdx__h158518,
	       v__h609621,
	       v__h609631,
	       v__h610689,
	       x__h719695,
	       x__h723635,
	       y_avValue_snd_snd_snd_fst__h722798,
	       y_avValue_snd_snd_snd_fst__h723457,
	       y_avValue_snd_snd_snd_fst__h723486;
  wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5165,
       IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5215,
       IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6557,
       IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6607,
       IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7949,
       IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7999,
       IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10033,
       IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10535,
       IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10802,
       IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9050,
       IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9765,
       IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10018,
       IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10045,
       IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10581,
       IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10787,
       IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10814,
       IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9096,
       IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9811,
       IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13204,
       IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13862,
       IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13898,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10048,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10049,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10585,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10817,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10818,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10873,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10914,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10958,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10983,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10994,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11013,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11027,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11042,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11059,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11071,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11084,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11101,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11113,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11126,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9100,
       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9815,
       IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10240,
       IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8755,
       IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9470,
       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12401,
       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12402,
       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12403,
       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12428,
       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12429,
       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12430,
       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12444,
       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12452,
       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11545,
       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11546,
       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11547,
       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11572,
       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11573,
       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11574,
       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11588,
       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11596,
       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8335,
       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8336,
       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8337,
       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8361,
       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8362,
       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8363,
       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8387,
       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8388,
       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8389,
       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8403,
       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8410,
       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8417,
       IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1619,
       IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1620,
       IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1621,
       IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1645,
       IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1646,
       IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1647,
       IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1660,
       IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1667,
       IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2114,
       IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2131,
       IF_NOT_fetchStage_pipelines_0_canDeq__2926_292_ETC___d14005,
       IF_NOT_fetchStage_pipelines_0_canDeq__2926_292_ETC___d14013,
       IF_NOT_fetchStage_pipelines_1_first__2937_BITS_ETC___d13935,
       IF_NOT_fetchStage_pipelines_1_first__2937_BITS_ETC___d14012,
       IF_NOT_rob_deqPort_1_deq_data__5002_BIT_25_500_ETC___d15207,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10047,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10583,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10816,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11011,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11025,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11040,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11057,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11069,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11082,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11099,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11111,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11124,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9098,
       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9813,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5195,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5232,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5323,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5336,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5349,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6587,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6624,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6715,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6728,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6741,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7979,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8016,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8107,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8120,
       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8133,
       IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2344_ETC___d12377,
       IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2344_ETC___d12413,
       IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1488_ETC___d11521,
       IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1488_ETC___d11557,
       IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8311,
       IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8346,
       IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8372,
       IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6628,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6589,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6626,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6690,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6701,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6717,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6730,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6743,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5197,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5234,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5298,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5309,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5325,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5338,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5351,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7981,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8018,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8082,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8093,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8109,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8122,
       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8135,
       IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5236,
       IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8020,
       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10020,
       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10789,
       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8541,
       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2112,
       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2132,
       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2135,
       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3127,
       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3142,
       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3154,
       IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3234,
       IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3249,
       IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3256,
       IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3276,
       IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3100,
       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2075,
       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2077,
       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2078,
       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2086,
       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2134,
       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2136,
       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2778,
       IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3405,
       IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3420,
       IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3428,
       IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3501,
       IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3516,
       IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3524,
       IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3543,
       IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1768,
       IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1824,
       IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1828,
       IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1832,
       IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1836,
       IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1840,
       IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1844,
       IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1848,
       IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1852,
       IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1856,
       IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1860,
       IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1864,
       IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1868,
       IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1872,
       IF_coreFix_memExe_dispToRegQ_RDY_first__564_AN_ETC___d1595,
       IF_coreFix_memExe_dispToRegQ_RDY_first__564_AN_ETC___d1630,
       IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3846,
       IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3839,
       IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3824,
       IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3752,
       IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3745,
       IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3730,
       IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3654,
       IF_fetchStage_RDY_pipelines_0_first__2925_AND__ETC___d13555,
       IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d13937,
       IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d14002,
       IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14050,
       IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14171,
       IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339,
       IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783,
       IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46,
       IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201,
       IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642,
       IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491,
       IF_rob_deqPort_1_canDeq__4999_THEN_IF_NOT_rob__ETC___d15208,
       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5317,
       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5345,
       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6709,
       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6737,
       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8101,
       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8129,
       NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13442,
       NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13543,
       NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13834,
       NOT_IF_NOT_rob_deqPort_0_canDeq__4995_4996_OR__ETC___d15213,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10918,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10976,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10987,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11016,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11031,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11062,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11075,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11104,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11117,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667,
       NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397,
       NOT_IF_rob_deqPort_0_deq_data__4466_BITS_97_TO_ETC___d14971,
       NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13603,
       NOT_coreFix_aluExe_0_bypassWire_0_whas__2366_2_ETC___d12393,
       NOT_coreFix_aluExe_0_bypassWire_0_whas__2366_2_ETC___d12423,
       NOT_coreFix_aluExe_1_bypassWire_0_whas__1510_1_ETC___d11537,
       NOT_coreFix_aluExe_1_bypassWire_0_whas__1510_1_ETC___d11567,
       NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8327,
       NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8356,
       NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8382,
       NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911,
       NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519,
       NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303,
       NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d8540,
       NOT_coreFix_fpuMulDivExe_0_rsFpuMulDiv_canEnq__ETC___d13946,
       NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1611,
       NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1640,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2554,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2730,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3153,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3174,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3223,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3279,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2100,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2151,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2561,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2563,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2585,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2589,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2592,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2606,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2609,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2620,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2626,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2633,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2658,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2666,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2674,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2683,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2708,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2725,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2728,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2739,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2741,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2747,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2815,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1141,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3394,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3451,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3490,
       NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3547,
       NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1908,
       NOT_coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_ETC___d1952,
       NOT_coreFix_memExe_dTlb_procResp__740_BITS_174_ETC___d1779,
       NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3813,
       NOT_coreFix_memExe_forwardQ_enqReq_dummy2_2_re_ETC___d3868,
       NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3719,
       NOT_coreFix_memExe_memRespLdQ_enqReq_dummy2_2__ETC___d3774,
       NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1486,
       NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1026,
       NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3643,
       NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3685,
       NOT_coreFix_memExe_respLrScAmoQ_full_977_978_A_ETC___d2110,
       NOT_coreFix_memExe_rsMem_canEnq__3571_3633_OR__ETC___d13947,
       NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13435,
       NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13541,
       NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13832,
       NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675,
       NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13918,
       NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13929,
       NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13968,
       NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13985,
       NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14106,
       NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14125,
       NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14177,
       NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309,
       NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14311,
       NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14322,
       NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14358,
       NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14378,
       NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14386,
       NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14407,
       NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14430,
       NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13429,
       NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548,
       NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13585,
       NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13852,
       NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13858,
       NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14010,
       NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183,
       NOT_fetchStage_pipelines_0_first__2928_BITS_32_ETC___d14207,
       NOT_fetchStage_pipelines_0_first__2928_BIT_68__ETC___d13596,
       NOT_fetchStage_pipelines_1_canDeq__2934_2935_O_ETC___d12943,
       NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13843,
       NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13845,
       NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13956,
       NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13977,
       NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13994,
       NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14319,
       NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14381,
       NOT_fetchStage_pipelines_1_first__2937_BITS_32_ETC___d14373,
       NOT_fetchStage_pipelines_1_first__2937_BIT_68__ETC___d14316,
       NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431,
       NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452,
       NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823,
       NOT_mmio_cRsQ_enqReq_dummy2_2_read__24_39_OR_I_ETC___d844,
       NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1099,
       NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1400,
       NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325,
       NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140,
       NOT_mmio_dataReqQ_enqReq_dummy2_2_read__41_56__ETC___d161,
       NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241,
       NOT_mmio_dataRespQ_enqReq_dummy2_2_read__42_57_ETC___d262,
       NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734,
       NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755,
       NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593,
       NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614,
       NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13627,
       NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13962,
       NOT_regRenamingTable_rename_0_canRename__3528__ETC___d14017,
       NOT_regRenamingTable_rename_1_canRename__3647__ETC___d14075,
       NOT_rob_deqPort_0_canDeq__4995_4996_OR_regRena_ETC___d15034,
       NOT_rob_deqPort_0_canDeq__4995_4996_OR_rob_deq_ETC___d15187,
       NOT_rob_deqPort_0_deq_data__4466_BITS_257_TO_2_ETC___d14788,
       NOT_rob_deqPort_0_deq_data__4466_BITS_257_TO_2_ETC___d14981,
       NOT_rob_deqPort_1_deq_data__5002_BIT_25_5003_5_ETC___d15031,
       NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14096,
       NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14161,
       SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13907,
       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243,
       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244,
       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758,
       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759,
       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473,
       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474,
       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040,
       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041,
       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648,
       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649,
       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432,
       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433,
       _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4345,
       _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5737,
       _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7129,
       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10493,
       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9008,
       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9723,
       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4896,
       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6288,
       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7680,
       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10196,
       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10543,
       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8696,
       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9058,
       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9426,
       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9773,
       _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4576,
       _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4969,
       _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5968,
       _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6361,
       _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7360,
       _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7753,
       _0_OR_NOT_fetchStage_pipelines_0_first__2928_BI_ETC___d14024,
       _0_OR_NOT_fetchStage_pipelines_1_first__2937_BI_ETC___d14109,
       _0_OR_fetchStage_RDY_pipelines_0_first__2925_39_ETC___d13932,
       _0b0_CONCAT_csrf_medeleg_15_reg_read__1825_1826_ETC___d14644,
       _0b0_CONCAT_csrf_mideleg_11_reg_read__1833_1834_ETC___d14625,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5280,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5305,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5332,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6672,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6697,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6724,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8064,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8089,
       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8116,
       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121,
       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123,
       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621,
       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623,
       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351,
       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353,
       _dfoo12,
       _dfoo18,
       _dfoo2,
       _dfoo20,
       _dfoo26,
       _dfoo7,
       _dor1coreFix_aluExe_0_bypassWire_2$EN_wset,
       _dor1coreFix_aluExe_0_bypassWire_3$EN_wset,
       _dor1coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put,
       _dor1coreFix_aluExe_1_bypassWire_2$EN_wset,
       _dor1coreFix_aluExe_1_bypassWire_3$EN_wset,
       _dor1coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put,
       _dor1coreFix_fpuMulDivExe_0_bypassWire_2$EN_wset,
       _dor1coreFix_fpuMulDivExe_0_bypassWire_3$EN_wset,
       _dor1coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put,
       _dor1coreFix_memExe_bypassWire_2$EN_wset,
       _dor1coreFix_memExe_bypassWire_3$EN_wset,
       _dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write,
       _dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write,
       _dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write,
       _dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset,
       _dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write,
       _dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write,
       _dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset,
       _dor1coreFix_memExe_rsMem$EN_setRegReady_3_put,
       _dor1rf$EN_write_0_wr,
       _dor1rf$EN_write_1_wr,
       _dor1sbAggr$EN_setReady_3_put,
       _dor1sbCons$EN_setReady_0_put,
       _dor1sbCons$EN_setReady_1_put,
       _theResult_____2__h309169,
       _theResult_____2__h315163,
       _theResult_____2__h323017,
       _theResult_____2__h333361,
       _theResult_____2__h336586,
       coreFix_aluExe_0_bypassWire_0_wget__2367_BITS__ETC___d12369,
       coreFix_aluExe_0_bypassWire_0_wget__2367_BITS__ETC___d12410,
       coreFix_aluExe_0_bypassWire_1_wget__2380_BITS__ETC___d12382,
       coreFix_aluExe_0_bypassWire_1_wget__2380_BITS__ETC___d12416,
       coreFix_aluExe_0_bypassWire_2_wget__2388_BITS__ETC___d12390,
       coreFix_aluExe_0_bypassWire_2_wget__2388_BITS__ETC___d12420,
       coreFix_aluExe_0_bypassWire_3_wget__2395_BITS__ETC___d12397,
       coreFix_aluExe_0_bypassWire_3_wget__2395_BITS__ETC___d12424,
       coreFix_aluExe_0_dispToRegQ_RDY_first__2344_AN_ETC___d12435,
       coreFix_aluExe_0_exeToFinQ_RDY_first__2811_AND_ETC___d12851,
       coreFix_aluExe_0_rsAlu_approximateCount__3562__ETC___d13564,
       coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11513,
       coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11554,
       coreFix_aluExe_1_bypassWire_1_wget__1524_BITS__ETC___d11526,
       coreFix_aluExe_1_bypassWire_1_wget__1524_BITS__ETC___d11560,
       coreFix_aluExe_1_bypassWire_2_wget__1532_BITS__ETC___d11534,
       coreFix_aluExe_1_bypassWire_2_wget__1532_BITS__ETC___d11564,
       coreFix_aluExe_1_bypassWire_3_wget__1539_BITS__ETC___d11541,
       coreFix_aluExe_1_bypassWire_3_wget__1539_BITS__ETC___d11568,
       coreFix_aluExe_1_dispToRegQ_RDY_first__1488_AN_ETC___d11579,
       coreFix_aluExe_1_exeToFinQ_RDY_first__2137_AND_ETC___d12178,
       coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8303,
       coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8343,
       coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8369,
       coreFix_fpuMulDivExe_0_bypassWire_1_wget__314__ETC___d8316,
       coreFix_fpuMulDivExe_0_bypassWire_1_wget__314__ETC___d8349,
       coreFix_fpuMulDivExe_0_bypassWire_1_wget__314__ETC___d8375,
       coreFix_fpuMulDivExe_0_bypassWire_2_wget__322__ETC___d8324,
       coreFix_fpuMulDivExe_0_bypassWire_2_wget__322__ETC___d8353,
       coreFix_fpuMulDivExe_0_bypassWire_2_wget__322__ETC___d8379,
       coreFix_fpuMulDivExe_0_bypassWire_3_wget__329__ETC___d8331,
       coreFix_fpuMulDivExe_0_bypassWire_3_wget__329__ETC___d8357,
       coreFix_fpuMulDivExe_0_bypassWire_3_wget__329__ETC___d8383,
       coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first__2_ETC___d8395,
       coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5368,
       coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3976,
       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6760,
       coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_enq_ETC___d8538,
       coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8152,
       coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d10963,
       coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d10999,
       coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11047,
       coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11089,
       coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11131,
       coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14116,
       coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1587,
       coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1627,
       coreFix_memExe_bypassWire_1_wget__598_BITS_70__ETC___d1600,
       coreFix_memExe_bypassWire_1_wget__598_BITS_70__ETC___d1633,
       coreFix_memExe_bypassWire_2_wget__606_BITS_70__ETC___d1608,
       coreFix_memExe_bypassWire_2_wget__606_BITS_70__ETC___d1637,
       coreFix_memExe_bypassWire_3_wget__613_BITS_70__ETC___d1615,
       coreFix_memExe_bypassWire_3_wget__613_BITS_70__ETC___d1641,
       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2605,
       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3163,
       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3266,
       coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2098,
       coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2178,
       coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2821,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2559,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2588,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2593,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2610,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2627,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2647,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2650,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2671,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2677,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2679,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2701,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2714,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2726,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2737,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2757,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2771,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2774,
       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2797,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2890,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2894,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2898,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2903,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2907,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2912,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2916,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2921,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2933,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2937,
       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2941,
       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enq_ETC___d3437,
       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enq_ETC___d3533,
       coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2_r_ETC___d1936,
       coreFix_memExe_dTlb_procResp__740_BITS_105_TO__ETC___d1894,
       coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1750,
       coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1751,
       coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1755,
       coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1758,
       coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1759,
       coreFix_memExe_forwardQ_enqReq_dummy2_2_read___ETC___d3855,
       coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3761,
       coreFix_memExe_regToExeQ_RDY_enq__563_AND_core_ETC___d1653,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1228,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1232,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1237,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1241,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1246,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1250,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1255,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1271,
       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1275,
       coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3670,
       coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14793,
       csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13197,
       csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13620,
       csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13896,
       csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646,
       csrf_prv_reg_read__2956_ULE_1___d14607,
       csrf_prv_reg_read__2956_ULT_IF_fetchStage_pipe_ETC___d13192,
       fetchStage_RDY_pipelines_0_first__2925_AND_NOT_ETC___d13551,
       fetchStage_RDY_pipelines_0_first__2925_AND_epo_ETC___d13407,
       fetchStage_RDY_pipelines_0_first__2925_AND_fet_ETC___d13617,
       fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14107,
       fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14186,
       fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14305,
       fetchStage_pipelines_0_canDeq__2926_AND_fetchS_ETC___d14175,
       fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14113,
       fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14120,
       fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14141,
       fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14152,
       fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14441,
       fetchStage_pipelines_0_canDeq__2926_AND_specTa_ETC___d14269,
       fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13190,
       fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13851,
       fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13872,
       fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13944,
       fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14052,
       fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14058,
       fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14080,
       fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14087,
       fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14300,
       fetchStage_pipelines_0_first__2928_BITS_199_TO_ETC___d13865,
       fetchStage_pipelines_0_first__2928_BIT_68_2955_ETC___d13625,
       fetchStage_pipelines_1_first__2937_BITS_194_TO_ETC___d14069,
       fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13904,
       fetchStage_pipelines_1_first__2937_BIT_68_3675_ETC___d14073,
       guard__h368984,
       guard__h414681,
       guard__h460376,
       guard__h508865,
       guard__h547718,
       guard__h587022,
       idx__h690627,
       k__h675032,
       mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444,
       mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836,
       mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312,
       mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153,
       mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254,
       mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13208,
       mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13461,
       mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14180,
       mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747,
       mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606,
       next_deqP___1__h309448,
       next_deqP___1__h315729,
       next_deqP___1__h323583,
       next_deqP___1__h333640,
       next_deqP___1__h336865,
       r1__read_BIT_20___h662377,
       r__h619422,
       r__h620919,
       regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14037,
       regRenamingTable_RDY_rename_1_getRename__4093__ETC___d14111,
       regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598,
       regRenamingTable_rename_0_canRename__3528_AND__ETC___d13612,
       regRenamingTable_rename_0_canRename__3528_AND__ETC___d13927,
       regRenamingTable_rename_0_canRename__3528_AND__ETC___d14066,
       regRenamingTable_rename_0_canRename__3528_AND__ETC___d14198,
       regRenamingTable_rename_0_canRename__3528_AND__ETC___d14211,
       regRenamingTable_rename_0_canRename__3528_AND__ETC___d14216,
       regRenamingTable_rename_0_canRename__3528_AND__ETC___d14221,
       regRenamingTable_rename_0_canRename__3528_AND__ETC___d14241,
       regRenamingTable_rename_0_canRename__3528_AND__ETC___d14245,
       regRenamingTable_rename_0_canRename__3528_AND__ETC___d14251,
       regRenamingTable_rename_0_canRename__3528_AND__ETC___d14255,
       regRenamingTable_rename_0_canRename__3528_AND__ETC___d14263,
       regRenamingTable_rename_0_canRename__3528_AND__ETC___d14439,
       regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318,
       regRenamingTable_rename_1_canRename__3647_AND__ETC___d14402,
       regRenamingTable_rename_1_canRename__3647_AND__ETC___d14412,
       rob_RDY_enqPort_1_enq__4157_AND_NOT_fetchStage_ETC___d14165,
       rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13841,
       rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13975,
       rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13992,
       v__h303938,
       v__h304456,
       v__h314452,
       v__h314683,
       v__h318328,
       v__h318559,
       v__h332929,
       v__h333160,
       v__h336154,
       v__h336385,
       x__h608937;

  // action method coreReq_start
  assign RDY_coreReq_start = 1'd1 ;
  assign CAN_FIRE_coreReq_start = 1'd1 ;
  assign WILL_FIRE_coreReq_start = EN_coreReq_start ;

  // action method coreReq_perfReq
  assign RDY_coreReq_perfReq = perfReqQ$FULL_N ;
  assign CAN_FIRE_coreReq_perfReq = perfReqQ$FULL_N ;
  assign WILL_FIRE_coreReq_perfReq = EN_coreReq_perfReq ;

  // actionvalue method coreIndInv_perfResp
  assign coreIndInv_perfResp = { perfReqQ$D_OUT, 64'd0 } ;
  assign RDY_coreIndInv_perfResp = perfReqQ$EMPTY_N ;
  assign CAN_FIRE_coreIndInv_perfResp = perfReqQ$EMPTY_N ;
  assign WILL_FIRE_coreIndInv_perfResp = EN_coreIndInv_perfResp ;

  // action method coreIndInv_terminate
  assign RDY_coreIndInv_terminate = csrf_terminate_module_terminateQ$EMPTY_N ;
  assign CAN_FIRE_coreIndInv_terminate =
	     csrf_terminate_module_terminateQ$EMPTY_N ;
  assign WILL_FIRE_coreIndInv_terminate = EN_coreIndInv_terminate ;

  // value method dCacheToParent_rsToP_notEmpty
  assign dCacheToParent_rsToP_notEmpty =
	     !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
  assign RDY_dCacheToParent_rsToP_notEmpty = 1'd1 ;

  // action method dCacheToParent_rsToP_deq
  assign RDY_dCacheToParent_rsToP_deq =
	     !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
  assign CAN_FIRE_dCacheToParent_rsToP_deq =
	     !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
  assign WILL_FIRE_dCacheToParent_rsToP_deq = EN_dCacheToParent_rsToP_deq ;

  // value method dCacheToParent_rsToP_first
  assign dCacheToParent_rsToP_first =
	     { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248,
	       !CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249,
	       SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15309 } ;
  assign RDY_dCacheToParent_rsToP_first =
	     !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;

  // value method dCacheToParent_rqToP_notEmpty
  assign dCacheToParent_rqToP_notEmpty =
	     !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
  assign RDY_dCacheToParent_rqToP_notEmpty = 1'd1 ;

  // action method dCacheToParent_rqToP_deq
  assign RDY_dCacheToParent_rqToP_deq =
	     !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
  assign CAN_FIRE_dCacheToParent_rqToP_deq =
	     !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
  assign WILL_FIRE_dCacheToParent_rqToP_deq = EN_dCacheToParent_rqToP_deq ;

  // value method dCacheToParent_rqToP_first
  assign dCacheToParent_rqToP_first =
	     { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q256,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q257,
	       SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15335 } ;
  assign RDY_dCacheToParent_rqToP_first =
	     !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;

  // value method dCacheToParent_fromP_notFull
  assign dCacheToParent_fromP_notFull =
	     !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
  assign RDY_dCacheToParent_fromP_notFull = 1'd1 ;

  // action method dCacheToParent_fromP_enq
  assign RDY_dCacheToParent_fromP_enq =
	     !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
  assign CAN_FIRE_dCacheToParent_fromP_enq =
	     !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
  assign WILL_FIRE_dCacheToParent_fromP_enq = EN_dCacheToParent_fromP_enq ;

  // value method iCacheToParent_rsToP_notEmpty
  assign iCacheToParent_rsToP_notEmpty =
	     fetchStage$iMemIfc_to_parent_rsToP_notEmpty ;
  assign RDY_iCacheToParent_rsToP_notEmpty = 1'd1 ;

  // action method iCacheToParent_rsToP_deq
  assign RDY_iCacheToParent_rsToP_deq =
	     fetchStage$RDY_iMemIfc_to_parent_rsToP_deq ;
  assign CAN_FIRE_iCacheToParent_rsToP_deq =
	     fetchStage$RDY_iMemIfc_to_parent_rsToP_deq ;
  assign WILL_FIRE_iCacheToParent_rsToP_deq = EN_iCacheToParent_rsToP_deq ;

  // value method iCacheToParent_rsToP_first
  assign iCacheToParent_rsToP_first =
	     fetchStage$iMemIfc_to_parent_rsToP_first ;
  assign RDY_iCacheToParent_rsToP_first =
	     fetchStage$RDY_iMemIfc_to_parent_rsToP_first ;

  // value method iCacheToParent_rqToP_notEmpty
  assign iCacheToParent_rqToP_notEmpty =
	     fetchStage$iMemIfc_to_parent_rqToP_notEmpty ;
  assign RDY_iCacheToParent_rqToP_notEmpty = 1'd1 ;

  // action method iCacheToParent_rqToP_deq
  assign RDY_iCacheToParent_rqToP_deq =
	     fetchStage$RDY_iMemIfc_to_parent_rqToP_deq ;
  assign CAN_FIRE_iCacheToParent_rqToP_deq =
	     fetchStage$RDY_iMemIfc_to_parent_rqToP_deq ;
  assign WILL_FIRE_iCacheToParent_rqToP_deq = EN_iCacheToParent_rqToP_deq ;

  // value method iCacheToParent_rqToP_first
  assign iCacheToParent_rqToP_first =
	     fetchStage$iMemIfc_to_parent_rqToP_first ;
  assign RDY_iCacheToParent_rqToP_first =
	     fetchStage$RDY_iMemIfc_to_parent_rqToP_first ;

  // value method iCacheToParent_fromP_notFull
  assign iCacheToParent_fromP_notFull =
	     fetchStage$iMemIfc_to_parent_fromP_notFull ;
  assign RDY_iCacheToParent_fromP_notFull = 1'd1 ;

  // action method iCacheToParent_fromP_enq
  assign RDY_iCacheToParent_fromP_enq =
	     fetchStage$RDY_iMemIfc_to_parent_fromP_enq ;
  assign CAN_FIRE_iCacheToParent_fromP_enq =
	     fetchStage$RDY_iMemIfc_to_parent_fromP_enq ;
  assign WILL_FIRE_iCacheToParent_fromP_enq = EN_iCacheToParent_fromP_enq ;

  // value method tlbToMem_memReq_notEmpty
  assign tlbToMem_memReq_notEmpty = l2Tlb$toMem_memReq_notEmpty ;
  assign RDY_tlbToMem_memReq_notEmpty = 1'd1 ;

  // action method tlbToMem_memReq_deq
  assign RDY_tlbToMem_memReq_deq = l2Tlb$RDY_toMem_memReq_deq ;
  assign CAN_FIRE_tlbToMem_memReq_deq = l2Tlb$RDY_toMem_memReq_deq ;
  assign WILL_FIRE_tlbToMem_memReq_deq = EN_tlbToMem_memReq_deq ;

  // value method tlbToMem_memReq_first
  assign tlbToMem_memReq_first = l2Tlb$toMem_memReq_first ;
  assign RDY_tlbToMem_memReq_first = l2Tlb$RDY_toMem_memReq_first ;

  // value method tlbToMem_respLd_notFull
  assign tlbToMem_respLd_notFull = l2Tlb$toMem_respLd_notFull ;
  assign RDY_tlbToMem_respLd_notFull = 1'd1 ;

  // action method tlbToMem_respLd_enq
  assign RDY_tlbToMem_respLd_enq = l2Tlb$RDY_toMem_respLd_enq ;
  assign CAN_FIRE_tlbToMem_respLd_enq = l2Tlb$RDY_toMem_respLd_enq ;
  assign WILL_FIRE_tlbToMem_respLd_enq = EN_tlbToMem_respLd_enq ;

  // value method mmioToPlatform_cRq_notEmpty
  assign mmioToPlatform_cRq_notEmpty = !mmio_cRqQ_empty ;
  assign RDY_mmioToPlatform_cRq_notEmpty = 1'd1 ;

  // action method mmioToPlatform_cRq_deq
  assign RDY_mmioToPlatform_cRq_deq = !mmio_cRqQ_empty ;
  assign CAN_FIRE_mmioToPlatform_cRq_deq = !mmio_cRqQ_empty ;
  assign WILL_FIRE_mmioToPlatform_cRq_deq = EN_mmioToPlatform_cRq_deq ;

  // value method mmioToPlatform_cRq_first
  assign mmioToPlatform_cRq_first =
	     { mmio_cRqQ_data_0[141:78],
	       CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1,
	       mmio_cRqQ_data_0[71:0] } ;
  assign RDY_mmioToPlatform_cRq_first = !mmio_cRqQ_empty ;

  // value method mmioToPlatform_pRs_notFull
  assign mmioToPlatform_pRs_notFull = !mmio_pRsQ_full ;
  assign RDY_mmioToPlatform_pRs_notFull = 1'd1 ;

  // action method mmioToPlatform_pRs_enq
  assign RDY_mmioToPlatform_pRs_enq = !mmio_pRsQ_full ;
  assign CAN_FIRE_mmioToPlatform_pRs_enq = !mmio_pRsQ_full ;
  assign WILL_FIRE_mmioToPlatform_pRs_enq = EN_mmioToPlatform_pRs_enq ;

  // value method mmioToPlatform_pRq_notFull
  assign mmioToPlatform_pRq_notFull = !mmio_pRqQ_full ;
  assign RDY_mmioToPlatform_pRq_notFull = 1'd1 ;

  // action method mmioToPlatform_pRq_enq
  assign RDY_mmioToPlatform_pRq_enq = !mmio_pRqQ_full ;
  assign CAN_FIRE_mmioToPlatform_pRq_enq = !mmio_pRqQ_full ;
  assign WILL_FIRE_mmioToPlatform_pRq_enq = EN_mmioToPlatform_pRq_enq ;

  // value method mmioToPlatform_cRs_notEmpty
  assign mmioToPlatform_cRs_notEmpty = !mmio_cRsQ_empty ;
  assign RDY_mmioToPlatform_cRs_notEmpty = 1'd1 ;

  // action method mmioToPlatform_cRs_deq
  assign RDY_mmioToPlatform_cRs_deq = !mmio_cRsQ_empty ;
  assign CAN_FIRE_mmioToPlatform_cRs_deq = !mmio_cRsQ_empty ;
  assign WILL_FIRE_mmioToPlatform_cRs_deq = EN_mmioToPlatform_cRs_deq ;

  // value method mmioToPlatform_cRs_first
  assign mmioToPlatform_cRs_first = mmio_cRsQ_data_0 ;
  assign RDY_mmioToPlatform_cRs_first = !mmio_cRsQ_empty ;

  // action method mmioToPlatform_setTime
  assign RDY_mmioToPlatform_setTime = 1'd1 ;
  assign CAN_FIRE_mmioToPlatform_setTime = 1'd1 ;
  assign WILL_FIRE_mmioToPlatform_setTime = EN_mmioToPlatform_setTime ;

  // actionvalue method sendDoStats
  assign sendDoStats = csrf_stats_module_writeQ$D_OUT ;
  assign RDY_sendDoStats = csrf_stats_module_writeQ$EMPTY_N ;
  assign CAN_FIRE_sendDoStats = csrf_stats_module_writeQ$EMPTY_N ;
  assign WILL_FIRE_sendDoStats = EN_sendDoStats ;

  // action method recvDoStats
  assign RDY_recvDoStats = 1'd1 ;
  assign CAN_FIRE_recvDoStats = 1'd1 ;
  assign WILL_FIRE_recvDoStats = EN_recvDoStats ;

  // actionvalue method deadlock_dCacheCRqStuck_get
  assign deadlock_dCacheCRqStuck_get = 73'h0AAAAAAAAAAAAAAAAAA ;
  assign RDY_deadlock_dCacheCRqStuck_get = 1'd0 ;
  assign CAN_FIRE_deadlock_dCacheCRqStuck_get = 1'd0 ;
  assign WILL_FIRE_deadlock_dCacheCRqStuck_get =
	     EN_deadlock_dCacheCRqStuck_get ;

  // actionvalue method deadlock_dCachePRqStuck_get
  assign deadlock_dCachePRqStuck_get = 68'hAAAAAAAAAAAAAAAAA ;
  assign RDY_deadlock_dCachePRqStuck_get = 1'd0 ;
  assign CAN_FIRE_deadlock_dCachePRqStuck_get = 1'd0 ;
  assign WILL_FIRE_deadlock_dCachePRqStuck_get =
	     EN_deadlock_dCachePRqStuck_get ;

  // actionvalue method deadlock_iCacheCRqStuck_get
  assign deadlock_iCacheCRqStuck_get = fetchStage$iMemIfc_cRqStuck_get ;
  assign RDY_deadlock_iCacheCRqStuck_get =
	     fetchStage$RDY_iMemIfc_cRqStuck_get ;
  assign CAN_FIRE_deadlock_iCacheCRqStuck_get =
	     fetchStage$RDY_iMemIfc_cRqStuck_get ;
  assign WILL_FIRE_deadlock_iCacheCRqStuck_get =
	     EN_deadlock_iCacheCRqStuck_get ;

  // actionvalue method deadlock_iCachePRqStuck_get
  assign deadlock_iCachePRqStuck_get = fetchStage$iMemIfc_pRqStuck_get ;
  assign RDY_deadlock_iCachePRqStuck_get =
	     fetchStage$RDY_iMemIfc_pRqStuck_get ;
  assign CAN_FIRE_deadlock_iCachePRqStuck_get =
	     fetchStage$RDY_iMemIfc_pRqStuck_get ;
  assign WILL_FIRE_deadlock_iCachePRqStuck_get =
	     EN_deadlock_iCachePRqStuck_get ;

  // actionvalue method deadlock_renameInstStuck_get
  assign deadlock_renameInstStuck_get = 78'h2AAAAAAAAAAAAAAAAAAA ;
  assign RDY_deadlock_renameInstStuck_get = 1'd0 ;
  assign CAN_FIRE_deadlock_renameInstStuck_get = 1'd0 ;
  assign WILL_FIRE_deadlock_renameInstStuck_get =
	     EN_deadlock_renameInstStuck_get ;

  // actionvalue method deadlock_renameCorrectPathStuck_get
  assign deadlock_renameCorrectPathStuck_get = 78'h2AAAAAAAAAAAAAAAAAAA ;
  assign RDY_deadlock_renameCorrectPathStuck_get = 1'd0 ;
  assign CAN_FIRE_deadlock_renameCorrectPathStuck_get = 1'd0 ;
  assign WILL_FIRE_deadlock_renameCorrectPathStuck_get =
	     EN_deadlock_renameCorrectPathStuck_get ;

  // actionvalue method deadlock_commitInstStuck_get
  assign deadlock_commitInstStuck_get =
	     163'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
  assign RDY_deadlock_commitInstStuck_get = 1'd0 ;
  assign CAN_FIRE_deadlock_commitInstStuck_get = 1'd0 ;
  assign WILL_FIRE_deadlock_commitInstStuck_get =
	     EN_deadlock_commitInstStuck_get ;

  // actionvalue method deadlock_commitUserInstStuck_get
  assign deadlock_commitUserInstStuck_get =
	     163'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
  assign RDY_deadlock_commitUserInstStuck_get = 1'd0 ;
  assign CAN_FIRE_deadlock_commitUserInstStuck_get = 1'd0 ;
  assign WILL_FIRE_deadlock_commitUserInstStuck_get =
	     EN_deadlock_commitUserInstStuck_get ;

  // action method deadlock_checkStarted_get
  assign RDY_deadlock_checkStarted_get = 1'd0 ;
  assign CAN_FIRE_deadlock_checkStarted_get = 1'd0 ;
  assign WILL_FIRE_deadlock_checkStarted_get = EN_deadlock_checkStarted_get ;

  // actionvalue method renameDebug_renameErr_get
  assign renameDebug_renameErr_get = 89'h0AAAAAAAAAAAAAAAAAAAAAA ;
  assign RDY_renameDebug_renameErr_get = 1'd0 ;
  assign CAN_FIRE_renameDebug_renameErr_get = 1'd0 ;
  assign WILL_FIRE_renameDebug_renameErr_get = EN_renameDebug_renameErr_get ;

  // action method setMEIP
  assign RDY_setMEIP = 1'd1 ;
  assign CAN_FIRE_setMEIP = 1'd1 ;
  assign WILL_FIRE_setMEIP = EN_setMEIP ;

  // action method setSEIP
  assign RDY_setSEIP = 1'd1 ;
  assign CAN_FIRE_setSEIP = 1'd1 ;
  assign WILL_FIRE_setSEIP = EN_setSEIP ;

  // submodule coreFix_aluExe_0_dispToRegQ
  mkAluDispToRegFifo coreFix_aluExe_0_dispToRegQ(.CLK(CLK),
						 .RST_N(RST_N),
						 .enq_x(coreFix_aluExe_0_dispToRegQ$enq_x),
						 .specUpdate_correctSpeculation_mask(coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask),
						 .specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
						 .specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
						 .EN_enq(coreFix_aluExe_0_dispToRegQ$EN_enq),
						 .EN_deq(coreFix_aluExe_0_dispToRegQ$EN_deq),
						 .EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation),
						 .EN_specUpdate_correctSpeculation(coreFix_aluExe_0_dispToRegQ$EN_specUpdate_correctSpeculation),
						 .RDY_enq(coreFix_aluExe_0_dispToRegQ$RDY_enq),
						 .RDY_deq(coreFix_aluExe_0_dispToRegQ$RDY_deq),
						 .first(coreFix_aluExe_0_dispToRegQ$first),
						 .RDY_first(coreFix_aluExe_0_dispToRegQ$RDY_first),
						 .RDY_specUpdate_incorrectSpeculation(),
						 .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_aluExe_0_exeToFinQ
  mkAluExeToFinFifo coreFix_aluExe_0_exeToFinQ(.CLK(CLK),
					       .RST_N(RST_N),
					       .enq_x(coreFix_aluExe_0_exeToFinQ$enq_x),
					       .specUpdate_correctSpeculation_mask(coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask),
					       .specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all),
					       .specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag),
					       .EN_enq(coreFix_aluExe_0_exeToFinQ$EN_enq),
					       .EN_deq(coreFix_aluExe_0_exeToFinQ$EN_deq),
					       .EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_exeToFinQ$EN_specUpdate_incorrectSpeculation),
					       .EN_specUpdate_correctSpeculation(coreFix_aluExe_0_exeToFinQ$EN_specUpdate_correctSpeculation),
					       .RDY_enq(coreFix_aluExe_0_exeToFinQ$RDY_enq),
					       .RDY_deq(coreFix_aluExe_0_exeToFinQ$RDY_deq),
					       .first(coreFix_aluExe_0_exeToFinQ$first),
					       .RDY_first(coreFix_aluExe_0_exeToFinQ$RDY_first),
					       .RDY_specUpdate_incorrectSpeculation(),
					       .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_aluExe_0_regToExeQ
  mkAluRegToExeFifo coreFix_aluExe_0_regToExeQ(.CLK(CLK),
					       .RST_N(RST_N),
					       .enq_x(coreFix_aluExe_0_regToExeQ$enq_x),
					       .specUpdate_correctSpeculation_mask(coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask),
					       .specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
					       .specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
					       .EN_enq(coreFix_aluExe_0_regToExeQ$EN_enq),
					       .EN_deq(coreFix_aluExe_0_regToExeQ$EN_deq),
					       .EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation),
					       .EN_specUpdate_correctSpeculation(coreFix_aluExe_0_regToExeQ$EN_specUpdate_correctSpeculation),
					       .RDY_enq(coreFix_aluExe_0_regToExeQ$RDY_enq),
					       .RDY_deq(coreFix_aluExe_0_regToExeQ$RDY_deq),
					       .first(coreFix_aluExe_0_regToExeQ$first),
					       .RDY_first(coreFix_aluExe_0_regToExeQ$RDY_first),
					       .RDY_specUpdate_incorrectSpeculation(),
					       .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_aluExe_0_rsAlu
  mkReservationStationAlu coreFix_aluExe_0_rsAlu(.CLK(CLK),
						 .RST_N(RST_N),
						 .enq_x(coreFix_aluExe_0_rsAlu$enq_x),
						 .setRegReady_0_put(coreFix_aluExe_0_rsAlu$setRegReady_0_put),
						 .setRegReady_1_put(coreFix_aluExe_0_rsAlu$setRegReady_1_put),
						 .setRegReady_2_put(coreFix_aluExe_0_rsAlu$setRegReady_2_put),
						 .setRegReady_3_put(coreFix_aluExe_0_rsAlu$setRegReady_3_put),
						 .setRegReady_4_put(coreFix_aluExe_0_rsAlu$setRegReady_4_put),
						 .setRobEnqTime_t(coreFix_aluExe_0_rsAlu$setRobEnqTime_t),
						 .specUpdate_correctSpeculation_mask(coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask),
						 .specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all),
						 .specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag),
						 .EN_enq(coreFix_aluExe_0_rsAlu$EN_enq),
						 .EN_setRobEnqTime(coreFix_aluExe_0_rsAlu$EN_setRobEnqTime),
						 .EN_doDispatch(coreFix_aluExe_0_rsAlu$EN_doDispatch),
						 .EN_setRegReady_0_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_0_put),
						 .EN_setRegReady_1_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_1_put),
						 .EN_setRegReady_2_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_2_put),
						 .EN_setRegReady_3_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put),
						 .EN_setRegReady_4_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_4_put),
						 .EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_rsAlu$EN_specUpdate_incorrectSpeculation),
						 .EN_specUpdate_correctSpeculation(coreFix_aluExe_0_rsAlu$EN_specUpdate_correctSpeculation),
						 .RDY_enq(coreFix_aluExe_0_rsAlu$RDY_enq),
						 .canEnq(coreFix_aluExe_0_rsAlu$canEnq),
						 .RDY_canEnq(),
						 .RDY_setRobEnqTime(),
						 .dispatchData(coreFix_aluExe_0_rsAlu$dispatchData),
						 .RDY_dispatchData(coreFix_aluExe_0_rsAlu$RDY_dispatchData),
						 .RDY_doDispatch(coreFix_aluExe_0_rsAlu$RDY_doDispatch),
						 .RDY_setRegReady_0_put(),
						 .RDY_setRegReady_1_put(),
						 .RDY_setRegReady_2_put(),
						 .RDY_setRegReady_3_put(),
						 .RDY_setRegReady_4_put(),
						 .approximateCount(coreFix_aluExe_0_rsAlu$approximateCount),
						 .RDY_approximateCount(),
						 .isFull_ehrPort0(),
						 .RDY_isFull_ehrPort0(),
						 .RDY_specUpdate_incorrectSpeculation(),
						 .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_aluExe_1_dispToRegQ
  mkAluDispToRegFifo coreFix_aluExe_1_dispToRegQ(.CLK(CLK),
						 .RST_N(RST_N),
						 .enq_x(coreFix_aluExe_1_dispToRegQ$enq_x),
						 .specUpdate_correctSpeculation_mask(coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask),
						 .specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
						 .specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
						 .EN_enq(coreFix_aluExe_1_dispToRegQ$EN_enq),
						 .EN_deq(coreFix_aluExe_1_dispToRegQ$EN_deq),
						 .EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_dispToRegQ$EN_specUpdate_incorrectSpeculation),
						 .EN_specUpdate_correctSpeculation(coreFix_aluExe_1_dispToRegQ$EN_specUpdate_correctSpeculation),
						 .RDY_enq(coreFix_aluExe_1_dispToRegQ$RDY_enq),
						 .RDY_deq(coreFix_aluExe_1_dispToRegQ$RDY_deq),
						 .first(coreFix_aluExe_1_dispToRegQ$first),
						 .RDY_first(coreFix_aluExe_1_dispToRegQ$RDY_first),
						 .RDY_specUpdate_incorrectSpeculation(),
						 .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_aluExe_1_exeToFinQ
  mkAluExeToFinFifo coreFix_aluExe_1_exeToFinQ(.CLK(CLK),
					       .RST_N(RST_N),
					       .enq_x(coreFix_aluExe_1_exeToFinQ$enq_x),
					       .specUpdate_correctSpeculation_mask(coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask),
					       .specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all),
					       .specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag),
					       .EN_enq(coreFix_aluExe_1_exeToFinQ$EN_enq),
					       .EN_deq(coreFix_aluExe_1_exeToFinQ$EN_deq),
					       .EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_exeToFinQ$EN_specUpdate_incorrectSpeculation),
					       .EN_specUpdate_correctSpeculation(coreFix_aluExe_1_exeToFinQ$EN_specUpdate_correctSpeculation),
					       .RDY_enq(coreFix_aluExe_1_exeToFinQ$RDY_enq),
					       .RDY_deq(coreFix_aluExe_1_exeToFinQ$RDY_deq),
					       .first(coreFix_aluExe_1_exeToFinQ$first),
					       .RDY_first(coreFix_aluExe_1_exeToFinQ$RDY_first),
					       .RDY_specUpdate_incorrectSpeculation(),
					       .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_aluExe_1_regToExeQ
  mkAluRegToExeFifo coreFix_aluExe_1_regToExeQ(.CLK(CLK),
					       .RST_N(RST_N),
					       .enq_x(coreFix_aluExe_1_regToExeQ$enq_x),
					       .specUpdate_correctSpeculation_mask(coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask),
					       .specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
					       .specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
					       .EN_enq(coreFix_aluExe_1_regToExeQ$EN_enq),
					       .EN_deq(coreFix_aluExe_1_regToExeQ$EN_deq),
					       .EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_regToExeQ$EN_specUpdate_incorrectSpeculation),
					       .EN_specUpdate_correctSpeculation(coreFix_aluExe_1_regToExeQ$EN_specUpdate_correctSpeculation),
					       .RDY_enq(coreFix_aluExe_1_regToExeQ$RDY_enq),
					       .RDY_deq(coreFix_aluExe_1_regToExeQ$RDY_deq),
					       .first(coreFix_aluExe_1_regToExeQ$first),
					       .RDY_first(coreFix_aluExe_1_regToExeQ$RDY_first),
					       .RDY_specUpdate_incorrectSpeculation(),
					       .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_aluExe_1_rsAlu
  mkReservationStationAlu coreFix_aluExe_1_rsAlu(.CLK(CLK),
						 .RST_N(RST_N),
						 .enq_x(coreFix_aluExe_1_rsAlu$enq_x),
						 .setRegReady_0_put(coreFix_aluExe_1_rsAlu$setRegReady_0_put),
						 .setRegReady_1_put(coreFix_aluExe_1_rsAlu$setRegReady_1_put),
						 .setRegReady_2_put(coreFix_aluExe_1_rsAlu$setRegReady_2_put),
						 .setRegReady_3_put(coreFix_aluExe_1_rsAlu$setRegReady_3_put),
						 .setRegReady_4_put(coreFix_aluExe_1_rsAlu$setRegReady_4_put),
						 .setRobEnqTime_t(coreFix_aluExe_1_rsAlu$setRobEnqTime_t),
						 .specUpdate_correctSpeculation_mask(coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask),
						 .specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all),
						 .specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag),
						 .EN_enq(coreFix_aluExe_1_rsAlu$EN_enq),
						 .EN_setRobEnqTime(coreFix_aluExe_1_rsAlu$EN_setRobEnqTime),
						 .EN_doDispatch(coreFix_aluExe_1_rsAlu$EN_doDispatch),
						 .EN_setRegReady_0_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_0_put),
						 .EN_setRegReady_1_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_1_put),
						 .EN_setRegReady_2_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_2_put),
						 .EN_setRegReady_3_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put),
						 .EN_setRegReady_4_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_4_put),
						 .EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_rsAlu$EN_specUpdate_incorrectSpeculation),
						 .EN_specUpdate_correctSpeculation(coreFix_aluExe_1_rsAlu$EN_specUpdate_correctSpeculation),
						 .RDY_enq(coreFix_aluExe_1_rsAlu$RDY_enq),
						 .canEnq(coreFix_aluExe_1_rsAlu$canEnq),
						 .RDY_canEnq(),
						 .RDY_setRobEnqTime(),
						 .dispatchData(coreFix_aluExe_1_rsAlu$dispatchData),
						 .RDY_dispatchData(coreFix_aluExe_1_rsAlu$RDY_dispatchData),
						 .RDY_doDispatch(coreFix_aluExe_1_rsAlu$RDY_doDispatch),
						 .RDY_setRegReady_0_put(),
						 .RDY_setRegReady_1_put(),
						 .RDY_setRegReady_2_put(),
						 .RDY_setRegReady_3_put(),
						 .RDY_setRegReady_4_put(),
						 .approximateCount(coreFix_aluExe_1_rsAlu$approximateCount),
						 .RDY_approximateCount(),
						 .isFull_ehrPort0(),
						 .RDY_isFull_ehrPort0(),
						 .RDY_specUpdate_incorrectSpeculation(),
						 .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_fpuMulDivExe_0_dispToRegQ
  mkFpuMulDivDispToRegFifo coreFix_fpuMulDivExe_0_dispToRegQ(.CLK(CLK),
							     .RST_N(RST_N),
							     .enq_x(coreFix_fpuMulDivExe_0_dispToRegQ$enq_x),
							     .specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask),
							     .specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
							     .specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
							     .EN_enq(coreFix_fpuMulDivExe_0_dispToRegQ$EN_enq),
							     .EN_deq(coreFix_fpuMulDivExe_0_dispToRegQ$EN_deq),
							     .EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation),
							     .EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_correctSpeculation),
							     .RDY_enq(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq),
							     .RDY_deq(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_deq),
							     .first(coreFix_fpuMulDivExe_0_dispToRegQ$first),
							     .RDY_first(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first),
							     .RDY_specUpdate_incorrectSpeculation(),
							     .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_fpuMulDivExe_0_fpuExec_divQ
  mkMinimumExecQ coreFix_fpuMulDivExe_0_fpuExec_divQ(.CLK(CLK),
						     .RST_N(RST_N),
						     .enq_x(coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x),
						     .specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask),
						     .specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all),
						     .specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag),
						     .EN_enq(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_enq),
						     .EN_deq(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_deq),
						     .EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_incorrectSpeculation),
						     .EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_correctSpeculation),
						     .RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq),
						     .RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq),
						     .first_data(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data),
						     .RDY_first_data(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_data),
						     .first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned),
						     .RDY_first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned),
						     .RDY_specUpdate_incorrectSpeculation(),
						     .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_fpuMulDivExe_0_fpuExec_double_div
  mkDoubleDiv coreFix_fpuMulDivExe_0_fpuExec_double_div(.CLK(CLK),
							.RST_N(RST_N),
							.request_put(coreFix_fpuMulDivExe_0_fpuExec_double_div$request_put),
							.EN_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_request_put),
							.EN_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_response_get),
							.RDY_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put),
							.response_get(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get),
							.RDY_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get));

  // submodule coreFix_fpuMulDivExe_0_fpuExec_double_fma
  mkDoubleFMA coreFix_fpuMulDivExe_0_fpuExec_double_fma(.CLK(CLK),
							.RST_N(RST_N),
							.request_put(coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put),
							.EN_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put),
							.EN_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_response_get),
							.RDY_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put),
							.response_get(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get),
							.RDY_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get));

  // submodule coreFix_fpuMulDivExe_0_fpuExec_double_sqrt
  mkDoubleSqrt coreFix_fpuMulDivExe_0_fpuExec_double_sqrt(.CLK(CLK),
							  .RST_N(RST_N),
							  .request_put(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$request_put),
							  .EN_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_request_put),
							  .EN_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_response_get),
							  .RDY_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put),
							  .response_get(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get),
							  .RDY_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get));

  // submodule coreFix_fpuMulDivExe_0_fpuExec_fmaQ
  mkFmaExecQ coreFix_fpuMulDivExe_0_fpuExec_fmaQ(.CLK(CLK),
						 .RST_N(RST_N),
						 .enq_x(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x),
						 .specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask),
						 .specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all),
						 .specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag),
						 .EN_enq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_enq),
						 .EN_deq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_deq),
						 .EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_incorrectSpeculation),
						 .EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_correctSpeculation),
						 .RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq),
						 .RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq),
						 .first_data(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data),
						 .RDY_first_data(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_data),
						 .first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned),
						 .RDY_first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned),
						 .RDY_specUpdate_incorrectSpeculation(),
						 .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_fpuMulDivExe_0_fpuExec_simpleQ
  mkSimpleRespQ coreFix_fpuMulDivExe_0_fpuExec_simpleQ(.CLK(CLK),
						       .RST_N(RST_N),
						       .enq_x(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$enq_x),
						       .specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask),
						       .specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all),
						       .specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag),
						       .EN_enq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_enq),
						       .EN_deq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_deq),
						       .EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_incorrectSpeculation),
						       .EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_correctSpeculation),
						       .RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq),
						       .RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_deq),
						       .first(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first),
						       .RDY_first(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_first),
						       .RDY_specUpdate_incorrectSpeculation(),
						       .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_fpuMulDivExe_0_fpuExec_sqrtQ
  mkMinimumExecQ coreFix_fpuMulDivExe_0_fpuExec_sqrtQ(.CLK(CLK),
						      .RST_N(RST_N),
						      .enq_x(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x),
						      .specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask),
						      .specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all),
						      .specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag),
						      .EN_enq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_enq),
						      .EN_deq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_deq),
						      .EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_incorrectSpeculation),
						      .EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_correctSpeculation),
						      .RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq),
						      .RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq),
						      .first_data(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data),
						      .RDY_first_data(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_data),
						      .first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned),
						      .RDY_first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned),
						      .RDY_specUpdate_incorrectSpeculation(),
						      .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_divQ
  mkDivExecQ coreFix_fpuMulDivExe_0_mulDivExec_divQ(.CLK(CLK),
						    .RST_N(RST_N),
						    .enq_x(coreFix_fpuMulDivExe_0_mulDivExec_divQ$enq_x),
						    .specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask),
						    .specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all),
						    .specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag),
						    .EN_enq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_enq),
						    .EN_deq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_deq),
						    .EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_incorrectSpeculation),
						    .EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_correctSpeculation),
						    .RDY_enq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq),
						    .RDY_deq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq),
						    .first_data(coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data),
						    .RDY_first_data(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_data),
						    .first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned),
						    .RDY_first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned),
						    .RDY_specUpdate_incorrectSpeculation(),
						    .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ
  FIFO2 #(.width(32'd140),
	  .guarded(32'd1)) coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ(.RST(RST_N),
										      .CLK(CLK),
										      .D_IN(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_IN),
										      .ENQ(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$ENQ),
										      .DEQ(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$DEQ),
										      .CLR(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$CLR),
										      .D_OUT(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT),
										      .FULL_N(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$FULL_N),
										      .EMPTY_N(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$EMPTY_N));

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ
  FIFO2 #(.width(32'd64),
	  .guarded(32'd1)) coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ(.RST(RST_N),
										     .CLK(CLK),
										     .D_IN(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_IN),
										     .ENQ(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$ENQ),
										     .DEQ(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$DEQ),
										     .CLR(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$CLR),
										     .D_OUT(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT),
										     .FULL_N(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$FULL_N),
										     .EMPTY_N(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$EMPTY_N));

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ
  FIFO2 #(.width(32'd204),
	  .guarded(32'd1)) coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ(.RST(RST_N),
										  .CLK(CLK),
										  .D_IN(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_IN),
										  .ENQ(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$ENQ),
										  .DEQ(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$DEQ),
										  .CLR(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$CLR),
										  .D_OUT(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT),
										  .FULL_N(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$FULL_N),
										  .EMPTY_N(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$EMPTY_N));

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulQ
  mkMulExecQ coreFix_fpuMulDivExe_0_mulDivExec_mulQ(.CLK(CLK),
						    .RST_N(RST_N),
						    .enq_x(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$enq_x),
						    .specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask),
						    .specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all),
						    .specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag),
						    .EN_enq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_enq),
						    .EN_deq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_deq),
						    .EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_incorrectSpeculation),
						    .EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_correctSpeculation),
						    .RDY_enq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq),
						    .RDY_deq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq),
						    .first_data(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data),
						    .RDY_first_data(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_data),
						    .first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned),
						    .RDY_first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned),
						    .RDY_specUpdate_incorrectSpeculation(),
						    .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ
  SizedFIFO #(.p1width(32'd128),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(32'd0)) coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ(.RST(RST_N),
									       .CLK(CLK),
									       .D_IN(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN),
									       .ENQ(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$ENQ),
									       .DEQ(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$DEQ),
									       .CLR(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$CLR),
									       .D_OUT(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT),
									       .FULL_N(),
									       .EMPTY_N(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N));

  // submodule coreFix_fpuMulDivExe_0_regToExeQ
  mkFpuMulDivRegToExeFifo coreFix_fpuMulDivExe_0_regToExeQ(.CLK(CLK),
							   .RST_N(RST_N),
							   .enq_x(coreFix_fpuMulDivExe_0_regToExeQ$enq_x),
							   .specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask),
							   .specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
							   .specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
							   .EN_enq(coreFix_fpuMulDivExe_0_regToExeQ$EN_enq),
							   .EN_deq(coreFix_fpuMulDivExe_0_regToExeQ$EN_deq),
							   .EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation),
							   .EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_correctSpeculation),
							   .RDY_enq(coreFix_fpuMulDivExe_0_regToExeQ$RDY_enq),
							   .RDY_deq(coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq),
							   .first(coreFix_fpuMulDivExe_0_regToExeQ$first),
							   .RDY_first(coreFix_fpuMulDivExe_0_regToExeQ$RDY_first),
							   .RDY_specUpdate_incorrectSpeculation(),
							   .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv
  mkReservationStationFpuMulDiv coreFix_fpuMulDivExe_0_rsFpuMulDiv(.CLK(CLK),
								   .RST_N(RST_N),
								   .enq_x(coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x),
								   .setRegReady_0_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_0_put),
								   .setRegReady_1_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_1_put),
								   .setRegReady_2_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put),
								   .setRegReady_3_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_3_put),
								   .setRegReady_4_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put),
								   .setRobEnqTime_t(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t),
								   .specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask),
								   .specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all),
								   .specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag),
								   .EN_enq(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq),
								   .EN_setRobEnqTime(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime),
								   .EN_doDispatch(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch),
								   .EN_setRegReady_0_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_0_put),
								   .EN_setRegReady_1_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_1_put),
								   .EN_setRegReady_2_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_2_put),
								   .EN_setRegReady_3_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put),
								   .EN_setRegReady_4_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_4_put),
								   .EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_incorrectSpeculation),
								   .EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_correctSpeculation),
								   .RDY_enq(coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq),
								   .canEnq(coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq),
								   .RDY_canEnq(),
								   .RDY_setRobEnqTime(),
								   .dispatchData(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData),
								   .RDY_dispatchData(coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData),
								   .RDY_doDispatch(coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch),
								   .RDY_setRegReady_0_put(),
								   .RDY_setRegReady_1_put(),
								   .RDY_setRegReady_2_put(),
								   .RDY_setRegReady_3_put(),
								   .RDY_setRegReady_4_put(),
								   .approximateCount(),
								   .RDY_approximateCount(),
								   .isFull_ehrPort0(),
								   .RDY_isFull_ehrPort0(),
								   .RDY_specUpdate_incorrectSpeculation(),
								   .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr
  mkDCRqMshrWrapper coreFix_memExe_dMem_cache_m_banks_0_cRqMshr(.CLK(CLK),
								.RST_N(RST_N),
								.cRqTransfer_getEmptyEntryInit_r(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r),
								.cRqTransfer_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n),
								.pipelineResp_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n),
								.pipelineResp_getSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n),
								.pipelineResp_getState_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n),
								.pipelineResp_getSucc_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n),
								.pipelineResp_releaseEntry_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n),
								.pipelineResp_searchEndOfChain_addr(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain_addr),
								.pipelineResp_setData_d(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d),
								.pipelineResp_setData_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_n),
								.pipelineResp_setStateSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_n),
								.pipelineResp_setStateSlot_slot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot),
								.pipelineResp_setStateSlot_state(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_state),
								.pipelineResp_setSucc_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_n),
								.pipelineResp_setSucc_succ(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_succ),
								.sendRqToP_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq_n),
								.sendRqToP_getSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot_n),
								.sendRsToP_cRq_getData_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData_n),
								.sendRsToP_cRq_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq_n),
								.sendRsToP_cRq_getSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot_n),
								.sendRsToP_cRq_getState_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState_n),
								.sendRsToP_cRq_setWaitSt_setSlot_clearData_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_n),
								.sendRsToP_cRq_setWaitSt_setSlot_clearData_slot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_slot),
								.EN_cRqTransfer_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_cRqTransfer_getEmptyEntryInit),
								.EN_sendRsToP_cRq_setWaitSt_setSlot_clearData(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_sendRsToP_cRq_setWaitSt_setSlot_clearData),
								.EN_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_releaseEntry),
								.EN_pipelineResp_setData(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setData),
								.EN_pipelineResp_setStateSlot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setStateSlot),
								.EN_pipelineResp_setSucc(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setSucc),
								.EN_stuck_get(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_stuck_get),
								.cRqTransfer_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq),
								.RDY_cRqTransfer_getRq(),
								.cRqTransfer_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit),
								.RDY_cRqTransfer_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_cRqTransfer_getEmptyEntryInit),
								.sendRsToP_cRq_getState(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState),
								.RDY_sendRsToP_cRq_getState(),
								.sendRsToP_cRq_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq),
								.RDY_sendRsToP_cRq_getRq(),
								.sendRsToP_cRq_getSlot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot),
								.RDY_sendRsToP_cRq_getSlot(),
								.sendRsToP_cRq_getData(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData),
								.RDY_sendRsToP_cRq_getData(),
								.RDY_sendRsToP_cRq_setWaitSt_setSlot_clearData(),
								.sendRqToP_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq),
								.RDY_sendRqToP_getRq(),
								.sendRqToP_getSlot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot),
								.RDY_sendRqToP_getSlot(),
								.RDY_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry),
								.pipelineResp_getState(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState),
								.RDY_pipelineResp_getState(),
								.pipelineResp_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq),
								.RDY_pipelineResp_getRq(),
								.pipelineResp_getSlot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot),
								.RDY_pipelineResp_getSlot(),
								.RDY_pipelineResp_setData(),
								.RDY_pipelineResp_setStateSlot(),
								.pipelineResp_getSucc(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc),
								.RDY_pipelineResp_getSucc(),
								.RDY_pipelineResp_setSucc(),
								.pipelineResp_searchEndOfChain(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain),
								.RDY_pipelineResp_searchEndOfChain(),
								.emptyForFlush(),
								.RDY_emptyForFlush(),
								.stuck_get(),
								.RDY_stuck_get());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0(.CLK(CLK),
												.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN),
												.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN),
												.Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1(.CLK(CLK),
												.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN),
												.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN),
												.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0(.CLK(CLK),
											      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN),
											      .EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN),
											      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1(.CLK(CLK),
											      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN),
											      .EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN),
											      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2(.CLK(CLK),
											      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN),
											      .EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN),
											      .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0(.CLK(CLK),
											      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN),
											      .EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN),
											      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1(.CLK(CLK),
											      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN),
											      .EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN),
											      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2(.CLK(CLK),
											      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN),
											      .EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN),
											      .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0(.CLK(CLK),
											.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN),
											.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN),
											.Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1(.CLK(CLK),
											.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN),
											.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN),
											.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN),
										      .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN),
										      .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0(.CLK(CLK),
										    .D_IN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN),
										    .EN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN),
										    .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1(.CLK(CLK),
										    .D_IN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN),
										    .EN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN),
										    .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr
  mkDPRqMshrWrapper coreFix_memExe_dMem_cache_m_banks_0_pRqMshr(.CLK(CLK),
								.RST_N(RST_N),
								.getEmptyEntryInit_r(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r),
								.pipelineResp_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n),
								.pipelineResp_getState_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n),
								.pipelineResp_releaseEntry_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_releaseEntry_n),
								.pipelineResp_setDone_setData_d(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d),
								.pipelineResp_setDone_setData_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_n),
								.sendRsToP_pRq_getData_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData_n),
								.sendRsToP_pRq_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq_n),
								.sendRsToP_pRq_releaseEntry_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_releaseEntry_n),
								.EN_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_getEmptyEntryInit),
								.EN_sendRsToP_pRq_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_sendRsToP_pRq_releaseEntry),
								.EN_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_releaseEntry),
								.EN_pipelineResp_setDone_setData(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_setDone_setData),
								.EN_stuck_get(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_stuck_get),
								.getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit),
								.RDY_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit),
								.sendRsToP_pRq_getRq(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq),
								.RDY_sendRsToP_pRq_getRq(),
								.sendRsToP_pRq_getData(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData),
								.RDY_sendRsToP_pRq_getData(),
								.RDY_sendRsToP_pRq_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry),
								.pipelineResp_getRq(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq),
								.RDY_pipelineResp_getRq(),
								.pipelineResp_getState(),
								.RDY_pipelineResp_getState(),
								.RDY_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_pipelineResp_releaseEntry),
								.RDY_pipelineResp_setDone_setData(),
								.stuck_get(),
								.RDY_stuck_get());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_pipeline
  mkDPipeline coreFix_memExe_dMem_cache_m_banks_0_pipeline(.CLK(CLK),
							   .RST_N(RST_N),
							   .deqWrite_swapRq(coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq),
							   .deqWrite_updateRep(coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep),
							   .deqWrite_wrRam(coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam),
							   .send_r(coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r),
							   .EN_send(coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_send),
							   .EN_deqWrite(coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_deqWrite),
							   .RDY_send(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send),
							   .first(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first),
							   .RDY_first(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first),
							   .RDY_deqWrite(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0(.CLK(CLK),
											.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN),
											.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN),
											.Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1(.CLK(CLK),
											.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN),
											.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN),
											.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0(.CLK(CLK),
										       .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN),
										       .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN),
										       .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1(.CLK(CLK),
										       .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN),
										       .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN),
										       .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2(.CLK(CLK),
										       .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN),
										       .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN),
										       .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN),
										      .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN),
										      .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN),
										      .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ
  SizedFIFO #(.p1width(32'd3),
	      .p2depth(32'd8),
	      .p3cntr_width(32'd3),
	      .guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ(.RST(RST_N),
									       .CLK(CLK),
									       .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_IN),
									       .ENQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$ENQ),
									       .DEQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$DEQ),
									       .CLR(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$CLR),
									       .D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT),
									       .FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N),
									       .EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$EMPTY_N));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp
  FIFO2 #(.width(32'd3),
	  .guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp(.RST(RST_N),
											.CLK(CLK),
											.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_IN),
											.ENQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$ENQ),
											.DEQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$DEQ),
											.CLR(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$CLR),
											.D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_OUT),
											.FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N),
											.EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$EMPTY_N));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP
  FIFO2 #(.width(32'd3),
	  .guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP(.RST(RST_N),
										     .CLK(CLK),
										     .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_IN),
										     .ENQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$ENQ),
										     .DEQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$DEQ),
										     .CLR(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$CLR),
										     .D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_OUT),
										     .FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$FULL_N),
										     .EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$EMPTY_N));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0(.CLK(CLK),
											.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN),
											.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN),
											.Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1(.CLK(CLK),
											.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN),
											.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN),
											.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN),
										      .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN),
										      .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ
  SizedFIFO #(.p1width(32'd4),
	      .p2depth(32'd12),
	      .p3cntr_width(32'd4),
	      .guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ(.RST(RST_N),
									       .CLK(CLK),
									       .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_IN),
									       .ENQ(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$ENQ),
									       .DEQ(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$DEQ),
									       .CLR(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$CLR),
									       .D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT),
									       .FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N),
									       .EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0(.CLK(CLK),
											.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN),
											.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN),
											.Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1(.CLK(CLK),
											.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN),
											.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN),
											.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN),
										      .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN),
										      .Q_OUT());

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2(.CLK(CLK),
										      .D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN),
										      .EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN),
										      .Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0(.CLK(CLK),
									  .D_IN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN),
									  .EN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN),
									  .Q_OUT());

  // submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1(.CLK(CLK),
									  .D_IN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN),
									  .EN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN),
									  .Q_OUT(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0(.CLK(CLK),
									.D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN),
									.EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN),
									.Q_OUT());

  // submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1(.CLK(CLK),
									.D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN),
									.EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN),
									.Q_OUT());

  // submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2(.CLK(CLK),
									.D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN),
									.EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN),
									.Q_OUT(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0(.CLK(CLK),
									.D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN),
									.EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN),
									.Q_OUT());

  // submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1(.CLK(CLK),
									.D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN),
									.EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN),
									.Q_OUT());

  // submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2(.CLK(CLK),
									.D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN),
									.EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN),
									.Q_OUT(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_dTlb
  mkDTlbSynth coreFix_memExe_dTlb(.CLK(CLK),
				  .RST_N(RST_N),
				  .perf_req_r(coreFix_memExe_dTlb$perf_req_r),
				  .perf_setStatus_doStats(coreFix_memExe_dTlb$perf_setStatus_doStats),
				  .procReq_req(coreFix_memExe_dTlb$procReq_req),
				  .specUpdate_correctSpeculation_mask(coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask),
				  .specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all),
				  .specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag),
				  .toParent_ldTransRsFromP_enq_x(coreFix_memExe_dTlb$toParent_ldTransRsFromP_enq_x),
				  .updateVMInfo_vm(coreFix_memExe_dTlb$updateVMInfo_vm),
				  .EN_flush(coreFix_memExe_dTlb$EN_flush),
				  .EN_updateVMInfo(coreFix_memExe_dTlb$EN_updateVMInfo),
				  .EN_procReq(coreFix_memExe_dTlb$EN_procReq),
				  .EN_deqProcResp(coreFix_memExe_dTlb$EN_deqProcResp),
				  .EN_toParent_rqToP_deq(coreFix_memExe_dTlb$EN_toParent_rqToP_deq),
				  .EN_toParent_ldTransRsFromP_enq(coreFix_memExe_dTlb$EN_toParent_ldTransRsFromP_enq),
				  .EN_toParent_flush_request_get(coreFix_memExe_dTlb$EN_toParent_flush_request_get),
				  .EN_toParent_flush_response_put(coreFix_memExe_dTlb$EN_toParent_flush_response_put),
				  .EN_specUpdate_incorrectSpeculation(coreFix_memExe_dTlb$EN_specUpdate_incorrectSpeculation),
				  .EN_specUpdate_correctSpeculation(coreFix_memExe_dTlb$EN_specUpdate_correctSpeculation),
				  .EN_perf_setStatus(coreFix_memExe_dTlb$EN_perf_setStatus),
				  .EN_perf_req(coreFix_memExe_dTlb$EN_perf_req),
				  .EN_perf_resp(coreFix_memExe_dTlb$EN_perf_resp),
				  .flush_done(coreFix_memExe_dTlb$flush_done),
				  .RDY_flush_done(),
				  .RDY_flush(coreFix_memExe_dTlb$RDY_flush),
				  .RDY_updateVMInfo(),
				  .noPendingReq(coreFix_memExe_dTlb$noPendingReq),
				  .RDY_noPendingReq(),
				  .RDY_procReq(coreFix_memExe_dTlb$RDY_procReq),
				  .procResp(coreFix_memExe_dTlb$procResp),
				  .RDY_procResp(coreFix_memExe_dTlb$RDY_procResp),
				  .RDY_deqProcResp(coreFix_memExe_dTlb$RDY_deqProcResp),
				  .toParent_rqToP_notEmpty(),
				  .RDY_toParent_rqToP_notEmpty(),
				  .RDY_toParent_rqToP_deq(coreFix_memExe_dTlb$RDY_toParent_rqToP_deq),
				  .toParent_rqToP_first(coreFix_memExe_dTlb$toParent_rqToP_first),
				  .RDY_toParent_rqToP_first(coreFix_memExe_dTlb$RDY_toParent_rqToP_first),
				  .toParent_ldTransRsFromP_notFull(),
				  .RDY_toParent_ldTransRsFromP_notFull(),
				  .RDY_toParent_ldTransRsFromP_enq(coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq),
				  .RDY_toParent_flush_request_get(coreFix_memExe_dTlb$RDY_toParent_flush_request_get),
				  .RDY_toParent_flush_response_put(coreFix_memExe_dTlb$RDY_toParent_flush_response_put),
				  .RDY_specUpdate_incorrectSpeculation(),
				  .RDY_specUpdate_correctSpeculation(),
				  .RDY_perf_setStatus(),
				  .RDY_perf_req(),
				  .perf_resp(),
				  .RDY_perf_resp(),
				  .perf_respValid(),
				  .RDY_perf_respValid());

  // submodule coreFix_memExe_dispToRegQ
  mkMemDispToRegFifo coreFix_memExe_dispToRegQ(.CLK(CLK),
					       .RST_N(RST_N),
					       .enq_x(coreFix_memExe_dispToRegQ$enq_x),
					       .specUpdate_correctSpeculation_mask(coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask),
					       .specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
					       .specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
					       .EN_enq(coreFix_memExe_dispToRegQ$EN_enq),
					       .EN_deq(coreFix_memExe_dispToRegQ$EN_deq),
					       .EN_specUpdate_incorrectSpeculation(coreFix_memExe_dispToRegQ$EN_specUpdate_incorrectSpeculation),
					       .EN_specUpdate_correctSpeculation(coreFix_memExe_dispToRegQ$EN_specUpdate_correctSpeculation),
					       .RDY_enq(coreFix_memExe_dispToRegQ$RDY_enq),
					       .RDY_deq(coreFix_memExe_dispToRegQ$RDY_deq),
					       .first(coreFix_memExe_dispToRegQ$first),
					       .RDY_first(coreFix_memExe_dispToRegQ$RDY_first),
					       .RDY_specUpdate_incorrectSpeculation(),
					       .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_memExe_forwardQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_forwardQ_clearReq_dummy2_0(.CLK(CLK),
								     .D_IN(coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN),
								     .EN(coreFix_memExe_forwardQ_clearReq_dummy2_0$EN),
								     .Q_OUT());

  // submodule coreFix_memExe_forwardQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_forwardQ_clearReq_dummy2_1(.CLK(CLK),
								     .D_IN(coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN),
								     .EN(coreFix_memExe_forwardQ_clearReq_dummy2_1$EN),
								     .Q_OUT(coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_forwardQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_0(.CLK(CLK),
								   .D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN),
								   .EN(coreFix_memExe_forwardQ_deqReq_dummy2_0$EN),
								   .Q_OUT());

  // submodule coreFix_memExe_forwardQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_1(.CLK(CLK),
								   .D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN),
								   .EN(coreFix_memExe_forwardQ_deqReq_dummy2_1$EN),
								   .Q_OUT());

  // submodule coreFix_memExe_forwardQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_2(.CLK(CLK),
								   .D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN),
								   .EN(coreFix_memExe_forwardQ_deqReq_dummy2_2$EN),
								   .Q_OUT(coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_forwardQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_0(.CLK(CLK),
								   .D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN),
								   .EN(coreFix_memExe_forwardQ_enqReq_dummy2_0$EN),
								   .Q_OUT());

  // submodule coreFix_memExe_forwardQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_1(.CLK(CLK),
								   .D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN),
								   .EN(coreFix_memExe_forwardQ_enqReq_dummy2_1$EN),
								   .Q_OUT());

  // submodule coreFix_memExe_forwardQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_2(.CLK(CLK),
								   .D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN),
								   .EN(coreFix_memExe_forwardQ_enqReq_dummy2_2$EN),
								   .Q_OUT(coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_lsq
  mkSplitLSQ coreFix_memExe_lsq(.CLK(CLK),
				.RST_N(RST_N),
				.enqLd_dst(coreFix_memExe_lsq$enqLd_dst),
				.enqLd_inst_tag(coreFix_memExe_lsq$enqLd_inst_tag),
				.enqLd_mem_inst(coreFix_memExe_lsq$enqLd_mem_inst),
				.enqLd_spec_bits(coreFix_memExe_lsq$enqLd_spec_bits),
				.enqSt_dst(coreFix_memExe_lsq$enqSt_dst),
				.enqSt_inst_tag(coreFix_memExe_lsq$enqSt_inst_tag),
				.enqSt_mem_inst(coreFix_memExe_lsq$enqSt_mem_inst),
				.enqSt_spec_bits(coreFix_memExe_lsq$enqSt_spec_bits),
				.getHit_t(coreFix_memExe_lsq$getHit_t),
				.getOrigBE_t(coreFix_memExe_lsq$getOrigBE_t),
				.issueLd_lsqTag(coreFix_memExe_lsq$issueLd_lsqTag),
				.issueLd_paddr(coreFix_memExe_lsq$issueLd_paddr),
				.issueLd_sbRes(coreFix_memExe_lsq$issueLd_sbRes),
				.issueLd_shiftedBE(coreFix_memExe_lsq$issueLd_shiftedBE),
				.respLd_alignedData(coreFix_memExe_lsq$respLd_alignedData),
				.respLd_t(coreFix_memExe_lsq$respLd_t),
				.setAtCommit_0_put(coreFix_memExe_lsq$setAtCommit_0_put),
				.setAtCommit_1_put(coreFix_memExe_lsq$setAtCommit_1_put),
				.specUpdate_correctSpeculation_mask(coreFix_memExe_lsq$specUpdate_correctSpeculation_mask),
				.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all),
				.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag),
				.updateAddr_fault(coreFix_memExe_lsq$updateAddr_fault),
				.updateAddr_isMMIO(coreFix_memExe_lsq$updateAddr_isMMIO),
				.updateAddr_lsqTag(coreFix_memExe_lsq$updateAddr_lsqTag),
				.updateAddr_paddr(coreFix_memExe_lsq$updateAddr_paddr),
				.updateAddr_shiftedBE(coreFix_memExe_lsq$updateAddr_shiftedBE),
				.updateData_d(coreFix_memExe_lsq$updateData_d),
				.updateData_t(coreFix_memExe_lsq$updateData_t),
				.wakeupLdStalledBySB_sbIdx(coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx),
				.EN_enqLd(coreFix_memExe_lsq$EN_enqLd),
				.EN_enqSt(coreFix_memExe_lsq$EN_enqSt),
				.EN_getHit(coreFix_memExe_lsq$EN_getHit),
				.EN_updateData(coreFix_memExe_lsq$EN_updateData),
				.EN_updateAddr(coreFix_memExe_lsq$EN_updateAddr),
				.EN_issueLd(coreFix_memExe_lsq$EN_issueLd),
				.EN_getIssueLd(coreFix_memExe_lsq$EN_getIssueLd),
				.EN_respLd(coreFix_memExe_lsq$EN_respLd),
				.EN_deqLd(coreFix_memExe_lsq$EN_deqLd),
				.EN_deqSt(coreFix_memExe_lsq$EN_deqSt),
				.EN_wakeupLdStalledBySB(coreFix_memExe_lsq$EN_wakeupLdStalledBySB),
				.EN_setAtCommit_0_put(coreFix_memExe_lsq$EN_setAtCommit_0_put),
				.EN_setAtCommit_1_put(coreFix_memExe_lsq$EN_setAtCommit_1_put),
				.EN_specUpdate_incorrectSpeculation(coreFix_memExe_lsq$EN_specUpdate_incorrectSpeculation),
				.EN_specUpdate_correctSpeculation(coreFix_memExe_lsq$EN_specUpdate_correctSpeculation),
				.enqLdTag(coreFix_memExe_lsq$enqLdTag),
				.RDY_enqLdTag(),
				.enqStTag(coreFix_memExe_lsq$enqStTag),
				.RDY_enqStTag(),
				.RDY_enqLd(coreFix_memExe_lsq$RDY_enqLd),
				.RDY_enqSt(coreFix_memExe_lsq$RDY_enqSt),
				.getOrigBE(coreFix_memExe_lsq$getOrigBE),
				.RDY_getOrigBE(),
				.getHit(coreFix_memExe_lsq$getHit),
				.RDY_getHit(),
				.RDY_updateData(),
				.updateAddr(coreFix_memExe_lsq$updateAddr),
				.RDY_updateAddr(),
				.issueLd(coreFix_memExe_lsq$issueLd),
				.RDY_issueLd(),
				.getIssueLd(coreFix_memExe_lsq$getIssueLd),
				.RDY_getIssueLd(coreFix_memExe_lsq$RDY_getIssueLd),
				.respLd(coreFix_memExe_lsq$respLd),
				.RDY_respLd(),
				.firstLd(coreFix_memExe_lsq$firstLd),
				.RDY_firstLd(coreFix_memExe_lsq$RDY_firstLd),
				.RDY_deqLd(coreFix_memExe_lsq$RDY_deqLd),
				.firstSt(coreFix_memExe_lsq$firstSt),
				.RDY_firstSt(coreFix_memExe_lsq$RDY_firstSt),
				.RDY_deqSt(coreFix_memExe_lsq$RDY_deqSt),
				.RDY_wakeupLdStalledBySB(),
				.stqEmpty(coreFix_memExe_lsq$stqEmpty),
				.RDY_stqEmpty(),
				.RDY_setAtCommit_0_put(),
				.RDY_setAtCommit_1_put(),
				.RDY_specUpdate_incorrectSpeculation(),
				.RDY_specUpdate_correctSpeculation(),
				.stqFull_ehrPort0(),
				.RDY_stqFull_ehrPort0(),
				.ldqFull_ehrPort0(),
				.RDY_ldqFull_ehrPort0(),
				.noWrongPathLoads(),
				.RDY_noWrongPathLoads());

  // submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_memRespLdQ_clearReq_dummy2_0(.CLK(CLK),
								       .D_IN(coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN),
								       .EN(coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN),
								       .Q_OUT());

  // submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_memRespLdQ_clearReq_dummy2_1(.CLK(CLK),
								       .D_IN(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN),
								       .EN(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN),
								       .Q_OUT(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_0(.CLK(CLK),
								     .D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN),
								     .EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN),
								     .Q_OUT());

  // submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_1(.CLK(CLK),
								     .D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN),
								     .EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN),
								     .Q_OUT());

  // submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_2(.CLK(CLK),
								     .D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN),
								     .EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN),
								     .Q_OUT(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_0(.CLK(CLK),
								     .D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN),
								     .EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN),
								     .Q_OUT());

  // submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_1(.CLK(CLK),
								     .D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN),
								     .EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN),
								     .Q_OUT());

  // submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_2(.CLK(CLK),
								     .D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN),
								     .EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN),
								     .Q_OUT(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_regToExeQ
  mkMemRegToExeFifo coreFix_memExe_regToExeQ(.CLK(CLK),
					     .RST_N(RST_N),
					     .enq_x(coreFix_memExe_regToExeQ$enq_x),
					     .specUpdate_correctSpeculation_mask(coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask),
					     .specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
					     .specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
					     .EN_enq(coreFix_memExe_regToExeQ$EN_enq),
					     .EN_deq(coreFix_memExe_regToExeQ$EN_deq),
					     .EN_specUpdate_incorrectSpeculation(coreFix_memExe_regToExeQ$EN_specUpdate_incorrectSpeculation),
					     .EN_specUpdate_correctSpeculation(coreFix_memExe_regToExeQ$EN_specUpdate_correctSpeculation),
					     .RDY_enq(coreFix_memExe_regToExeQ$RDY_enq),
					     .RDY_deq(coreFix_memExe_regToExeQ$RDY_deq),
					     .first(coreFix_memExe_regToExeQ$first),
					     .RDY_first(coreFix_memExe_regToExeQ$RDY_first),
					     .RDY_specUpdate_incorrectSpeculation(),
					     .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_memExe_reqLdQ_data_0_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_data_0_dummy2_0(.CLK(CLK),
								 .D_IN(coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN),
								 .EN(coreFix_memExe_reqLdQ_data_0_dummy2_0$EN),
								 .Q_OUT());

  // submodule coreFix_memExe_reqLdQ_data_0_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_data_0_dummy2_1(.CLK(CLK),
								 .D_IN(coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN),
								 .EN(coreFix_memExe_reqLdQ_data_0_dummy2_1$EN),
								 .Q_OUT(coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_reqLdQ_deqP_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_deqP_dummy2_0(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN),
							       .EN(coreFix_memExe_reqLdQ_deqP_dummy2_0$EN),
							       .Q_OUT());

  // submodule coreFix_memExe_reqLdQ_deqP_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_deqP_dummy2_1(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN),
							       .EN(coreFix_memExe_reqLdQ_deqP_dummy2_1$EN),
							       .Q_OUT());

  // submodule coreFix_memExe_reqLdQ_empty_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_0(.CLK(CLK),
								.D_IN(coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN),
								.EN(coreFix_memExe_reqLdQ_empty_dummy2_0$EN),
								.Q_OUT());

  // submodule coreFix_memExe_reqLdQ_empty_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_1(.CLK(CLK),
								.D_IN(coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN),
								.EN(coreFix_memExe_reqLdQ_empty_dummy2_1$EN),
								.Q_OUT(coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_reqLdQ_empty_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_2(.CLK(CLK),
								.D_IN(coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN),
								.EN(coreFix_memExe_reqLdQ_empty_dummy2_2$EN),
								.Q_OUT(coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_reqLdQ_enqP_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_enqP_dummy2_0(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN),
							       .EN(coreFix_memExe_reqLdQ_enqP_dummy2_0$EN),
							       .Q_OUT());

  // submodule coreFix_memExe_reqLdQ_enqP_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_enqP_dummy2_1(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN),
							       .EN(coreFix_memExe_reqLdQ_enqP_dummy2_1$EN),
							       .Q_OUT());

  // submodule coreFix_memExe_reqLdQ_full_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_0(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqLdQ_full_dummy2_0$D_IN),
							       .EN(coreFix_memExe_reqLdQ_full_dummy2_0$EN),
							       .Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT));

  // submodule coreFix_memExe_reqLdQ_full_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_1(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqLdQ_full_dummy2_1$D_IN),
							       .EN(coreFix_memExe_reqLdQ_full_dummy2_1$EN),
							       .Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_reqLdQ_full_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_2(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqLdQ_full_dummy2_2$D_IN),
							       .EN(coreFix_memExe_reqLdQ_full_dummy2_2$EN),
							       .Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0(.CLK(CLK),
								      .D_IN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN),
								      .EN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN),
								      .Q_OUT());

  // submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1(.CLK(CLK),
								      .D_IN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN),
								      .EN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN),
								      .Q_OUT(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0(.CLK(CLK),
								    .D_IN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN),
								    .EN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN),
								    .Q_OUT());

  // submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1(.CLK(CLK),
								    .D_IN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN),
								    .EN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN),
								    .Q_OUT());

  // submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_0(.CLK(CLK),
								     .D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN),
								     .EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN),
								     .Q_OUT());

  // submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_1(.CLK(CLK),
								     .D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN),
								     .EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN),
								     .Q_OUT(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_2(.CLK(CLK),
								     .D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN),
								     .EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN),
								     .Q_OUT(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0(.CLK(CLK),
								    .D_IN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN),
								    .EN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN),
								    .Q_OUT());

  // submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1(.CLK(CLK),
								    .D_IN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN),
								    .EN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN),
								    .Q_OUT());

  // submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_0(.CLK(CLK),
								    .D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN),
								    .EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN),
								    .Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT));

  // submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_1(.CLK(CLK),
								    .D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN),
								    .EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN),
								    .Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_2(.CLK(CLK),
								    .D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN),
								    .EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN),
								    .Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_reqStQ_data_0_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_data_0_dummy2_0(.CLK(CLK),
								 .D_IN(coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN),
								 .EN(coreFix_memExe_reqStQ_data_0_dummy2_0$EN),
								 .Q_OUT());

  // submodule coreFix_memExe_reqStQ_data_0_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_data_0_dummy2_1(.CLK(CLK),
								 .D_IN(coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN),
								 .EN(coreFix_memExe_reqStQ_data_0_dummy2_1$EN),
								 .Q_OUT(coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_reqStQ_deqP_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_deqP_dummy2_0(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN),
							       .EN(coreFix_memExe_reqStQ_deqP_dummy2_0$EN),
							       .Q_OUT());

  // submodule coreFix_memExe_reqStQ_deqP_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_deqP_dummy2_1(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN),
							       .EN(coreFix_memExe_reqStQ_deqP_dummy2_1$EN),
							       .Q_OUT());

  // submodule coreFix_memExe_reqStQ_empty_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_0(.CLK(CLK),
								.D_IN(coreFix_memExe_reqStQ_empty_dummy2_0$D_IN),
								.EN(coreFix_memExe_reqStQ_empty_dummy2_0$EN),
								.Q_OUT());

  // submodule coreFix_memExe_reqStQ_empty_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_1(.CLK(CLK),
								.D_IN(coreFix_memExe_reqStQ_empty_dummy2_1$D_IN),
								.EN(coreFix_memExe_reqStQ_empty_dummy2_1$EN),
								.Q_OUT(coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_reqStQ_empty_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_2(.CLK(CLK),
								.D_IN(coreFix_memExe_reqStQ_empty_dummy2_2$D_IN),
								.EN(coreFix_memExe_reqStQ_empty_dummy2_2$EN),
								.Q_OUT(coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_reqStQ_enqP_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_enqP_dummy2_0(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN),
							       .EN(coreFix_memExe_reqStQ_enqP_dummy2_0$EN),
							       .Q_OUT());

  // submodule coreFix_memExe_reqStQ_enqP_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_enqP_dummy2_1(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN),
							       .EN(coreFix_memExe_reqStQ_enqP_dummy2_1$EN),
							       .Q_OUT());

  // submodule coreFix_memExe_reqStQ_full_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_0(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqStQ_full_dummy2_0$D_IN),
							       .EN(coreFix_memExe_reqStQ_full_dummy2_0$EN),
							       .Q_OUT(coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT));

  // submodule coreFix_memExe_reqStQ_full_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_1(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqStQ_full_dummy2_1$D_IN),
							       .EN(coreFix_memExe_reqStQ_full_dummy2_1$EN),
							       .Q_OUT(coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_reqStQ_full_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_2(.CLK(CLK),
							       .D_IN(coreFix_memExe_reqStQ_full_dummy2_2$D_IN),
							       .EN(coreFix_memExe_reqStQ_full_dummy2_2$EN),
							       .Q_OUT(coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0(.CLK(CLK),
									 .D_IN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN),
									 .EN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN),
									 .Q_OUT());

  // submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1(.CLK(CLK),
									 .D_IN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN),
									 .EN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN),
									 .Q_OUT(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT));

  // submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0(.CLK(CLK),
								       .D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN),
								       .EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN),
								       .Q_OUT());

  // submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1(.CLK(CLK),
								       .D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN),
								       .EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN),
								       .Q_OUT());

  // submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2(.CLK(CLK),
								       .D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN),
								       .EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN),
								       .Q_OUT(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0(.CLK(CLK),
								       .D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN),
								       .EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN),
								       .Q_OUT());

  // submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1(.CLK(CLK),
								       .D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN),
								       .EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN),
								       .Q_OUT());

  // submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2(.CLK(CLK),
								       .D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN),
								       .EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN),
								       .Q_OUT(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT));

  // submodule coreFix_memExe_rsMem
  mkReservationStationMem coreFix_memExe_rsMem(.CLK(CLK),
					       .RST_N(RST_N),
					       .enq_x(coreFix_memExe_rsMem$enq_x),
					       .setRegReady_0_put(coreFix_memExe_rsMem$setRegReady_0_put),
					       .setRegReady_1_put(coreFix_memExe_rsMem$setRegReady_1_put),
					       .setRegReady_2_put(coreFix_memExe_rsMem$setRegReady_2_put),
					       .setRegReady_3_put(coreFix_memExe_rsMem$setRegReady_3_put),
					       .setRegReady_4_put(coreFix_memExe_rsMem$setRegReady_4_put),
					       .setRobEnqTime_t(coreFix_memExe_rsMem$setRobEnqTime_t),
					       .specUpdate_correctSpeculation_mask(coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask),
					       .specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all),
					       .specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag),
					       .EN_enq(coreFix_memExe_rsMem$EN_enq),
					       .EN_setRobEnqTime(coreFix_memExe_rsMem$EN_setRobEnqTime),
					       .EN_doDispatch(coreFix_memExe_rsMem$EN_doDispatch),
					       .EN_setRegReady_0_put(coreFix_memExe_rsMem$EN_setRegReady_0_put),
					       .EN_setRegReady_1_put(coreFix_memExe_rsMem$EN_setRegReady_1_put),
					       .EN_setRegReady_2_put(coreFix_memExe_rsMem$EN_setRegReady_2_put),
					       .EN_setRegReady_3_put(coreFix_memExe_rsMem$EN_setRegReady_3_put),
					       .EN_setRegReady_4_put(coreFix_memExe_rsMem$EN_setRegReady_4_put),
					       .EN_specUpdate_incorrectSpeculation(coreFix_memExe_rsMem$EN_specUpdate_incorrectSpeculation),
					       .EN_specUpdate_correctSpeculation(coreFix_memExe_rsMem$EN_specUpdate_correctSpeculation),
					       .RDY_enq(coreFix_memExe_rsMem$RDY_enq),
					       .canEnq(coreFix_memExe_rsMem$canEnq),
					       .RDY_canEnq(),
					       .RDY_setRobEnqTime(),
					       .dispatchData(coreFix_memExe_rsMem$dispatchData),
					       .RDY_dispatchData(coreFix_memExe_rsMem$RDY_dispatchData),
					       .RDY_doDispatch(coreFix_memExe_rsMem$RDY_doDispatch),
					       .RDY_setRegReady_0_put(),
					       .RDY_setRegReady_1_put(),
					       .RDY_setRegReady_2_put(),
					       .RDY_setRegReady_3_put(),
					       .RDY_setRegReady_4_put(),
					       .approximateCount(),
					       .RDY_approximateCount(),
					       .isFull_ehrPort0(),
					       .RDY_isFull_ehrPort0(),
					       .RDY_specUpdate_incorrectSpeculation(),
					       .RDY_specUpdate_correctSpeculation());

  // submodule coreFix_memExe_stb
  mkStoreBufferEhr coreFix_memExe_stb(.CLK(CLK),
				      .RST_N(RST_N),
				      .deq_idx(coreFix_memExe_stb$deq_idx),
				      .enq_be(coreFix_memExe_stb$enq_be),
				      .enq_data(coreFix_memExe_stb$enq_data),
				      .enq_idx(coreFix_memExe_stb$enq_idx),
				      .enq_paddr(coreFix_memExe_stb$enq_paddr),
				      .getEnqIndex_paddr(coreFix_memExe_stb$getEnqIndex_paddr),
				      .noMatchLdQ_be(coreFix_memExe_stb$noMatchLdQ_be),
				      .noMatchLdQ_paddr(coreFix_memExe_stb$noMatchLdQ_paddr),
				      .noMatchStQ_be(coreFix_memExe_stb$noMatchStQ_be),
				      .noMatchStQ_paddr(coreFix_memExe_stb$noMatchStQ_paddr),
				      .search_be(coreFix_memExe_stb$search_be),
				      .search_paddr(coreFix_memExe_stb$search_paddr),
				      .EN_enq(coreFix_memExe_stb$EN_enq),
				      .EN_deq(coreFix_memExe_stb$EN_deq),
				      .EN_issue(coreFix_memExe_stb$EN_issue),
				      .isEmpty(coreFix_memExe_stb$isEmpty),
				      .RDY_isEmpty(),
				      .getEnqIndex(coreFix_memExe_stb$getEnqIndex),
				      .RDY_getEnqIndex(),
				      .RDY_enq(coreFix_memExe_stb$RDY_enq),
				      .deq(coreFix_memExe_stb$deq),
				      .RDY_deq(coreFix_memExe_stb$RDY_deq),
				      .issue(coreFix_memExe_stb$issue),
				      .RDY_issue(coreFix_memExe_stb$RDY_issue),
				      .search(coreFix_memExe_stb$search),
				      .RDY_search(),
				      .noMatchLdQ(coreFix_memExe_stb$noMatchLdQ),
				      .RDY_noMatchLdQ(),
				      .noMatchStQ(coreFix_memExe_stb$noMatchStQ),
				      .RDY_noMatchStQ());

  // submodule coreFix_trainBPQ_0
  FIFO2 #(.width(32'd160), .guarded(32'd1)) coreFix_trainBPQ_0(.RST(RST_N),
							       .CLK(CLK),
							       .D_IN(coreFix_trainBPQ_0$D_IN),
							       .ENQ(coreFix_trainBPQ_0$ENQ),
							       .DEQ(coreFix_trainBPQ_0$DEQ),
							       .CLR(coreFix_trainBPQ_0$CLR),
							       .D_OUT(coreFix_trainBPQ_0$D_OUT),
							       .FULL_N(coreFix_trainBPQ_0$FULL_N),
							       .EMPTY_N(coreFix_trainBPQ_0$EMPTY_N));

  // submodule coreFix_trainBPQ_1
  FIFO2 #(.width(32'd160), .guarded(32'd1)) coreFix_trainBPQ_1(.RST(RST_N),
							       .CLK(CLK),
							       .D_IN(coreFix_trainBPQ_1$D_IN),
							       .ENQ(coreFix_trainBPQ_1$ENQ),
							       .DEQ(coreFix_trainBPQ_1$DEQ),
							       .CLR(coreFix_trainBPQ_1$CLR),
							       .D_OUT(coreFix_trainBPQ_1$D_OUT),
							       .FULL_N(coreFix_trainBPQ_1$FULL_N),
							       .EMPTY_N(coreFix_trainBPQ_1$EMPTY_N));

  // submodule csrInstOrInterruptInflight_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) csrInstOrInterruptInflight_dummy2_0(.CLK(CLK),
							       .D_IN(csrInstOrInterruptInflight_dummy2_0$D_IN),
							       .EN(csrInstOrInterruptInflight_dummy2_0$EN),
							       .Q_OUT(csrInstOrInterruptInflight_dummy2_0$Q_OUT));

  // submodule csrInstOrInterruptInflight_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) csrInstOrInterruptInflight_dummy2_1(.CLK(CLK),
							       .D_IN(csrInstOrInterruptInflight_dummy2_1$D_IN),
							       .EN(csrInstOrInterruptInflight_dummy2_1$EN),
							       .Q_OUT(csrInstOrInterruptInflight_dummy2_1$Q_OUT));

  // submodule csrf_mcycle_ehr_data_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) csrf_mcycle_ehr_data_dummy2_0(.CLK(CLK),
							 .D_IN(csrf_mcycle_ehr_data_dummy2_0$D_IN),
							 .EN(csrf_mcycle_ehr_data_dummy2_0$EN),
							 .Q_OUT(csrf_mcycle_ehr_data_dummy2_0$Q_OUT));

  // submodule csrf_mcycle_ehr_data_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) csrf_mcycle_ehr_data_dummy2_1(.CLK(CLK),
							 .D_IN(csrf_mcycle_ehr_data_dummy2_1$D_IN),
							 .EN(csrf_mcycle_ehr_data_dummy2_1$EN),
							 .Q_OUT(csrf_mcycle_ehr_data_dummy2_1$Q_OUT));

  // submodule csrf_minstret_ehr_data_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) csrf_minstret_ehr_data_dummy2_0(.CLK(CLK),
							   .D_IN(csrf_minstret_ehr_data_dummy2_0$D_IN),
							   .EN(csrf_minstret_ehr_data_dummy2_0$EN),
							   .Q_OUT(csrf_minstret_ehr_data_dummy2_0$Q_OUT));

  // submodule csrf_minstret_ehr_data_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) csrf_minstret_ehr_data_dummy2_1(.CLK(CLK),
							   .D_IN(csrf_minstret_ehr_data_dummy2_1$D_IN),
							   .EN(csrf_minstret_ehr_data_dummy2_1$EN),
							   .Q_OUT(csrf_minstret_ehr_data_dummy2_1$Q_OUT));

  // submodule csrf_stats_module_writeQ
  FIFO1 #(.width(32'd1),
	  .guarded(32'd1)) csrf_stats_module_writeQ(.RST(RST_N),
						    .CLK(CLK),
						    .D_IN(csrf_stats_module_writeQ$D_IN),
						    .ENQ(csrf_stats_module_writeQ$ENQ),
						    .DEQ(csrf_stats_module_writeQ$DEQ),
						    .CLR(csrf_stats_module_writeQ$CLR),
						    .D_OUT(csrf_stats_module_writeQ$D_OUT),
						    .FULL_N(csrf_stats_module_writeQ$FULL_N),
						    .EMPTY_N(csrf_stats_module_writeQ$EMPTY_N));

  // submodule csrf_terminate_module_terminateQ
  FIFO10 #(.guarded(32'd1)) csrf_terminate_module_terminateQ(.RST(RST_N),
							     .CLK(CLK),
							     .ENQ(csrf_terminate_module_terminateQ$ENQ),
							     .DEQ(csrf_terminate_module_terminateQ$DEQ),
							     .CLR(csrf_terminate_module_terminateQ$CLR),
							     .FULL_N(csrf_terminate_module_terminateQ$FULL_N),
							     .EMPTY_N(csrf_terminate_module_terminateQ$EMPTY_N));

  // submodule epochManager
  mkEpochManager epochManager(.CLK(CLK),
			      .RST_N(RST_N),
			      .checkEpoch_0_check_e(epochManager$checkEpoch_0_check_e),
			      .checkEpoch_1_check_e(epochManager$checkEpoch_1_check_e),
			      .updatePrevEpoch_0_update_e(epochManager$updatePrevEpoch_0_update_e),
			      .updatePrevEpoch_1_update_e(epochManager$updatePrevEpoch_1_update_e),
			      .EN_updatePrevEpoch_0_update(epochManager$EN_updatePrevEpoch_0_update),
			      .EN_updatePrevEpoch_1_update(epochManager$EN_updatePrevEpoch_1_update),
			      .EN_incrementEpoch(epochManager$EN_incrementEpoch),
			      .checkEpoch_0_check(epochManager$checkEpoch_0_check),
			      .RDY_checkEpoch_0_check(),
			      .checkEpoch_1_check(epochManager$checkEpoch_1_check),
			      .RDY_checkEpoch_1_check(),
			      .RDY_updatePrevEpoch_0_update(),
			      .RDY_updatePrevEpoch_1_update(),
			      .getEpoch(),
			      .RDY_getEpoch(),
			      .RDY_incrementEpoch(epochManager$RDY_incrementEpoch),
			      .getEpochState(),
			      .RDY_getEpochState(),
			      .isFull_ehrPort0(),
			      .RDY_isFull_ehrPort0());

  // submodule fetchStage
  mkFetchStage fetchStage(.CLK(CLK),
			  .RST_N(RST_N),
			  .iMemIfc_perf_req_r(fetchStage$iMemIfc_perf_req_r),
			  .iMemIfc_perf_setStatus_doStats(fetchStage$iMemIfc_perf_setStatus_doStats),
			  .iMemIfc_to_parent_fromP_enq_x(fetchStage$iMemIfc_to_parent_fromP_enq_x),
			  .iMemIfc_to_proc_request_put(fetchStage$iMemIfc_to_proc_request_put),
			  .iTlbIfc_perf_req_r(fetchStage$iTlbIfc_perf_req_r),
			  .iTlbIfc_perf_setStatus_doStats(fetchStage$iTlbIfc_perf_setStatus_doStats),
			  .iTlbIfc_toParent_rsFromP_enq_x(fetchStage$iTlbIfc_toParent_rsFromP_enq_x),
			  .iTlbIfc_to_proc_request_put(fetchStage$iTlbIfc_to_proc_request_put),
			  .iTlbIfc_updateVMInfo_vm(fetchStage$iTlbIfc_updateVMInfo_vm),
			  .mmioIfc_instResp_enq_x(fetchStage$mmioIfc_instResp_enq_x),
			  .mmioIfc_setHtifAddrs_fromHost(fetchStage$mmioIfc_setHtifAddrs_fromHost),
			  .mmioIfc_setHtifAddrs_toHost(fetchStage$mmioIfc_setHtifAddrs_toHost),
			  .perf_req_r(fetchStage$perf_req_r),
			  .perf_setStatus_doStats(fetchStage$perf_setStatus_doStats),
			  .redirect_pc(fetchStage$redirect_pc),
			  .start_pc(fetchStage$start_pc),
			  .train_predictors_dpTrain(fetchStage$train_predictors_dpTrain),
			  .train_predictors_iType(fetchStage$train_predictors_iType),
			  .train_predictors_isCompressed(fetchStage$train_predictors_isCompressed),
			  .train_predictors_mispred(fetchStage$train_predictors_mispred),
			  .train_predictors_next_pc(fetchStage$train_predictors_next_pc),
			  .train_predictors_pc(fetchStage$train_predictors_pc),
			  .train_predictors_taken(fetchStage$train_predictors_taken),
			  .EN_pipelines_0_deq(fetchStage$EN_pipelines_0_deq),
			  .EN_pipelines_1_deq(fetchStage$EN_pipelines_1_deq),
			  .EN_iTlbIfc_flush(fetchStage$EN_iTlbIfc_flush),
			  .EN_iTlbIfc_updateVMInfo(fetchStage$EN_iTlbIfc_updateVMInfo),
			  .EN_iTlbIfc_to_proc_request_put(fetchStage$EN_iTlbIfc_to_proc_request_put),
			  .EN_iTlbIfc_to_proc_response_get(fetchStage$EN_iTlbIfc_to_proc_response_get),
			  .EN_iTlbIfc_toParent_rqToP_deq(fetchStage$EN_iTlbIfc_toParent_rqToP_deq),
			  .EN_iTlbIfc_toParent_rsFromP_enq(fetchStage$EN_iTlbIfc_toParent_rsFromP_enq),
			  .EN_iTlbIfc_toParent_flush_request_get(fetchStage$EN_iTlbIfc_toParent_flush_request_get),
			  .EN_iTlbIfc_toParent_flush_response_put(fetchStage$EN_iTlbIfc_toParent_flush_response_put),
			  .EN_iTlbIfc_perf_setStatus(fetchStage$EN_iTlbIfc_perf_setStatus),
			  .EN_iTlbIfc_perf_req(fetchStage$EN_iTlbIfc_perf_req),
			  .EN_iTlbIfc_perf_resp(fetchStage$EN_iTlbIfc_perf_resp),
			  .EN_iMemIfc_to_proc_request_put(fetchStage$EN_iMemIfc_to_proc_request_put),
			  .EN_iMemIfc_to_proc_response_get(fetchStage$EN_iMemIfc_to_proc_response_get),
			  .EN_iMemIfc_flush(fetchStage$EN_iMemIfc_flush),
			  .EN_iMemIfc_perf_setStatus(fetchStage$EN_iMemIfc_perf_setStatus),
			  .EN_iMemIfc_perf_req(fetchStage$EN_iMemIfc_perf_req),
			  .EN_iMemIfc_perf_resp(fetchStage$EN_iMemIfc_perf_resp),
			  .EN_iMemIfc_to_parent_rsToP_deq(fetchStage$EN_iMemIfc_to_parent_rsToP_deq),
			  .EN_iMemIfc_to_parent_rqToP_deq(fetchStage$EN_iMemIfc_to_parent_rqToP_deq),
			  .EN_iMemIfc_to_parent_fromP_enq(fetchStage$EN_iMemIfc_to_parent_fromP_enq),
			  .EN_iMemIfc_cRqStuck_get(fetchStage$EN_iMemIfc_cRqStuck_get),
			  .EN_iMemIfc_pRqStuck_get(fetchStage$EN_iMemIfc_pRqStuck_get),
			  .EN_mmioIfc_instReq_deq(fetchStage$EN_mmioIfc_instReq_deq),
			  .EN_mmioIfc_instResp_enq(fetchStage$EN_mmioIfc_instResp_enq),
			  .EN_mmioIfc_setHtifAddrs(fetchStage$EN_mmioIfc_setHtifAddrs),
			  .EN_start(fetchStage$EN_start),
			  .EN_stop(fetchStage$EN_stop),
			  .EN_setWaitRedirect(fetchStage$EN_setWaitRedirect),
			  .EN_redirect(fetchStage$EN_redirect),
			  .EN_done_flushing(fetchStage$EN_done_flushing),
			  .EN_train_predictors(fetchStage$EN_train_predictors),
			  .EN_flush_predictors(fetchStage$EN_flush_predictors),
			  .EN_perf_setStatus(fetchStage$EN_perf_setStatus),
			  .EN_perf_req(fetchStage$EN_perf_req),
			  .EN_perf_resp(fetchStage$EN_perf_resp),
			  .pipelines_0_canDeq(fetchStage$pipelines_0_canDeq),
			  .RDY_pipelines_0_canDeq(),
			  .RDY_pipelines_0_deq(fetchStage$RDY_pipelines_0_deq),
			  .pipelines_0_first(fetchStage$pipelines_0_first),
			  .RDY_pipelines_0_first(fetchStage$RDY_pipelines_0_first),
			  .pipelines_1_canDeq(fetchStage$pipelines_1_canDeq),
			  .RDY_pipelines_1_canDeq(),
			  .RDY_pipelines_1_deq(fetchStage$RDY_pipelines_1_deq),
			  .pipelines_1_first(fetchStage$pipelines_1_first),
			  .RDY_pipelines_1_first(fetchStage$RDY_pipelines_1_first),
			  .iTlbIfc_flush_done(fetchStage$iTlbIfc_flush_done),
			  .RDY_iTlbIfc_flush_done(),
			  .RDY_iTlbIfc_flush(fetchStage$RDY_iTlbIfc_flush),
			  .RDY_iTlbIfc_updateVMInfo(),
			  .iTlbIfc_noPendingReq(fetchStage$iTlbIfc_noPendingReq),
			  .RDY_iTlbIfc_noPendingReq(),
			  .RDY_iTlbIfc_to_proc_request_put(),
			  .iTlbIfc_to_proc_response_get(),
			  .RDY_iTlbIfc_to_proc_response_get(),
			  .iTlbIfc_toParent_rqToP_notEmpty(),
			  .RDY_iTlbIfc_toParent_rqToP_notEmpty(),
			  .RDY_iTlbIfc_toParent_rqToP_deq(fetchStage$RDY_iTlbIfc_toParent_rqToP_deq),
			  .iTlbIfc_toParent_rqToP_first(fetchStage$iTlbIfc_toParent_rqToP_first),
			  .RDY_iTlbIfc_toParent_rqToP_first(fetchStage$RDY_iTlbIfc_toParent_rqToP_first),
			  .iTlbIfc_toParent_rsFromP_notFull(),
			  .RDY_iTlbIfc_toParent_rsFromP_notFull(),
			  .RDY_iTlbIfc_toParent_rsFromP_enq(fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq),
			  .RDY_iTlbIfc_toParent_flush_request_get(fetchStage$RDY_iTlbIfc_toParent_flush_request_get),
			  .RDY_iTlbIfc_toParent_flush_response_put(fetchStage$RDY_iTlbIfc_toParent_flush_response_put),
			  .RDY_iTlbIfc_perf_setStatus(),
			  .RDY_iTlbIfc_perf_req(),
			  .iTlbIfc_perf_resp(),
			  .RDY_iTlbIfc_perf_resp(),
			  .iTlbIfc_perf_respValid(),
			  .RDY_iTlbIfc_perf_respValid(),
			  .RDY_iMemIfc_to_proc_request_put(),
			  .iMemIfc_to_proc_response_get(),
			  .RDY_iMemIfc_to_proc_response_get(),
			  .RDY_iMemIfc_flush(),
			  .iMemIfc_flush_done(),
			  .RDY_iMemIfc_flush_done(),
			  .RDY_iMemIfc_perf_setStatus(),
			  .RDY_iMemIfc_perf_req(),
			  .iMemIfc_perf_resp(),
			  .RDY_iMemIfc_perf_resp(),
			  .iMemIfc_perf_respValid(),
			  .RDY_iMemIfc_perf_respValid(),
			  .iMemIfc_to_parent_rsToP_notEmpty(fetchStage$iMemIfc_to_parent_rsToP_notEmpty),
			  .RDY_iMemIfc_to_parent_rsToP_notEmpty(),
			  .RDY_iMemIfc_to_parent_rsToP_deq(fetchStage$RDY_iMemIfc_to_parent_rsToP_deq),
			  .iMemIfc_to_parent_rsToP_first(fetchStage$iMemIfc_to_parent_rsToP_first),
			  .RDY_iMemIfc_to_parent_rsToP_first(fetchStage$RDY_iMemIfc_to_parent_rsToP_first),
			  .iMemIfc_to_parent_rqToP_notEmpty(fetchStage$iMemIfc_to_parent_rqToP_notEmpty),
			  .RDY_iMemIfc_to_parent_rqToP_notEmpty(),
			  .RDY_iMemIfc_to_parent_rqToP_deq(fetchStage$RDY_iMemIfc_to_parent_rqToP_deq),
			  .iMemIfc_to_parent_rqToP_first(fetchStage$iMemIfc_to_parent_rqToP_first),
			  .RDY_iMemIfc_to_parent_rqToP_first(fetchStage$RDY_iMemIfc_to_parent_rqToP_first),
			  .iMemIfc_to_parent_fromP_notFull(fetchStage$iMemIfc_to_parent_fromP_notFull),
			  .RDY_iMemIfc_to_parent_fromP_notFull(),
			  .RDY_iMemIfc_to_parent_fromP_enq(fetchStage$RDY_iMemIfc_to_parent_fromP_enq),
			  .iMemIfc_cRqStuck_get(fetchStage$iMemIfc_cRqStuck_get),
			  .RDY_iMemIfc_cRqStuck_get(fetchStage$RDY_iMemIfc_cRqStuck_get),
			  .iMemIfc_pRqStuck_get(fetchStage$iMemIfc_pRqStuck_get),
			  .RDY_iMemIfc_pRqStuck_get(fetchStage$RDY_iMemIfc_pRqStuck_get),
			  .mmioIfc_instReq_notEmpty(),
			  .RDY_mmioIfc_instReq_notEmpty(),
			  .RDY_mmioIfc_instReq_deq(fetchStage$RDY_mmioIfc_instReq_deq),
			  .mmioIfc_instReq_first_fst(fetchStage$mmioIfc_instReq_first_fst),
			  .RDY_mmioIfc_instReq_first_fst(fetchStage$RDY_mmioIfc_instReq_first_fst),
			  .mmioIfc_instReq_first_snd(fetchStage$mmioIfc_instReq_first_snd),
			  .RDY_mmioIfc_instReq_first_snd(fetchStage$RDY_mmioIfc_instReq_first_snd),
			  .mmioIfc_instResp_notFull(),
			  .RDY_mmioIfc_instResp_notFull(),
			  .RDY_mmioIfc_instResp_enq(fetchStage$RDY_mmioIfc_instResp_enq),
			  .RDY_mmioIfc_setHtifAddrs(),
			  .RDY_start(),
			  .RDY_stop(),
			  .RDY_setWaitRedirect(),
			  .RDY_redirect(),
			  .RDY_done_flushing(fetchStage$RDY_done_flushing),
			  .RDY_train_predictors(),
			  .emptyForFlush(),
			  .RDY_emptyForFlush(),
			  .RDY_flush_predictors(),
			  .flush_predictors_done(),
			  .RDY_flush_predictors_done(),
			  .getFetchState(),
			  .RDY_getFetchState(),
			  .RDY_perf_setStatus(),
			  .RDY_perf_req(),
			  .perf_resp(),
			  .RDY_perf_resp(),
			  .perf_respValid(),
			  .RDY_perf_respValid());

  // submodule l2Tlb
  mkL2Tlb l2Tlb(.CLK(CLK),
		.RST_N(RST_N),
		.perf_req_r(l2Tlb$perf_req_r),
		.perf_setStatus_doStats(l2Tlb$perf_setStatus_doStats),
		.toChildren_rqFromC_put(l2Tlb$toChildren_rqFromC_put),
		.toMem_respLd_enq_x(l2Tlb$toMem_respLd_enq_x),
		.updateVMInfo_vmD(l2Tlb$updateVMInfo_vmD),
		.updateVMInfo_vmI(l2Tlb$updateVMInfo_vmI),
		.EN_updateVMInfo(l2Tlb$EN_updateVMInfo),
		.EN_toChildren_rqFromC_put(l2Tlb$EN_toChildren_rqFromC_put),
		.EN_toChildren_rsToC_deq(l2Tlb$EN_toChildren_rsToC_deq),
		.EN_toChildren_iTlbReqFlush_put(l2Tlb$EN_toChildren_iTlbReqFlush_put),
		.EN_toChildren_dTlbReqFlush_put(l2Tlb$EN_toChildren_dTlbReqFlush_put),
		.EN_toChildren_flushDone_get(l2Tlb$EN_toChildren_flushDone_get),
		.EN_toMem_memReq_deq(l2Tlb$EN_toMem_memReq_deq),
		.EN_toMem_respLd_enq(l2Tlb$EN_toMem_respLd_enq),
		.EN_perf_setStatus(l2Tlb$EN_perf_setStatus),
		.EN_perf_req(l2Tlb$EN_perf_req),
		.EN_perf_resp(l2Tlb$EN_perf_resp),
		.RDY_updateVMInfo(),
		.RDY_toChildren_rqFromC_put(l2Tlb$RDY_toChildren_rqFromC_put),
		.toChildren_rsToC_notEmpty(),
		.RDY_toChildren_rsToC_notEmpty(),
		.RDY_toChildren_rsToC_deq(l2Tlb$RDY_toChildren_rsToC_deq),
		.toChildren_rsToC_first(l2Tlb$toChildren_rsToC_first),
		.RDY_toChildren_rsToC_first(l2Tlb$RDY_toChildren_rsToC_first),
		.RDY_toChildren_iTlbReqFlush_put(l2Tlb$RDY_toChildren_iTlbReqFlush_put),
		.RDY_toChildren_dTlbReqFlush_put(l2Tlb$RDY_toChildren_dTlbReqFlush_put),
		.RDY_toChildren_flushDone_get(l2Tlb$RDY_toChildren_flushDone_get),
		.toMem_memReq_notEmpty(l2Tlb$toMem_memReq_notEmpty),
		.RDY_toMem_memReq_notEmpty(),
		.RDY_toMem_memReq_deq(l2Tlb$RDY_toMem_memReq_deq),
		.toMem_memReq_first(l2Tlb$toMem_memReq_first),
		.RDY_toMem_memReq_first(l2Tlb$RDY_toMem_memReq_first),
		.toMem_respLd_notFull(l2Tlb$toMem_respLd_notFull),
		.RDY_toMem_respLd_notFull(),
		.RDY_toMem_respLd_enq(l2Tlb$RDY_toMem_respLd_enq),
		.RDY_perf_setStatus(),
		.RDY_perf_req(),
		.perf_resp(),
		.RDY_perf_resp(),
		.perf_respValid(),
		.RDY_perf_respValid());

  // submodule mmio_cRqQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_cRqQ_clearReq_dummy2_0(.CLK(CLK),
						       .D_IN(mmio_cRqQ_clearReq_dummy2_0$D_IN),
						       .EN(mmio_cRqQ_clearReq_dummy2_0$EN),
						       .Q_OUT());

  // submodule mmio_cRqQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_cRqQ_clearReq_dummy2_1(.CLK(CLK),
						       .D_IN(mmio_cRqQ_clearReq_dummy2_1$D_IN),
						       .EN(mmio_cRqQ_clearReq_dummy2_1$EN),
						       .Q_OUT(mmio_cRqQ_clearReq_dummy2_1$Q_OUT));

  // submodule mmio_cRqQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_0(.CLK(CLK),
								    .D_IN(mmio_cRqQ_deqReq_dummy2_0$D_IN),
								    .EN(mmio_cRqQ_deqReq_dummy2_0$EN),
								    .Q_OUT());

  // submodule mmio_cRqQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_1(.CLK(CLK),
								    .D_IN(mmio_cRqQ_deqReq_dummy2_1$D_IN),
								    .EN(mmio_cRqQ_deqReq_dummy2_1$EN),
								    .Q_OUT());

  // submodule mmio_cRqQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_2(.CLK(CLK),
								    .D_IN(mmio_cRqQ_deqReq_dummy2_2$D_IN),
								    .EN(mmio_cRqQ_deqReq_dummy2_2$EN),
								    .Q_OUT(mmio_cRqQ_deqReq_dummy2_2$Q_OUT));

  // submodule mmio_cRqQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_0(.CLK(CLK),
								    .D_IN(mmio_cRqQ_enqReq_dummy2_0$D_IN),
								    .EN(mmio_cRqQ_enqReq_dummy2_0$EN),
								    .Q_OUT());

  // submodule mmio_cRqQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_1(.CLK(CLK),
								    .D_IN(mmio_cRqQ_enqReq_dummy2_1$D_IN),
								    .EN(mmio_cRqQ_enqReq_dummy2_1$EN),
								    .Q_OUT());

  // submodule mmio_cRqQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_2(.CLK(CLK),
								    .D_IN(mmio_cRqQ_enqReq_dummy2_2$D_IN),
								    .EN(mmio_cRqQ_enqReq_dummy2_2$EN),
								    .Q_OUT(mmio_cRqQ_enqReq_dummy2_2$Q_OUT));

  // submodule mmio_cRsQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_cRsQ_clearReq_dummy2_0(.CLK(CLK),
						       .D_IN(mmio_cRsQ_clearReq_dummy2_0$D_IN),
						       .EN(mmio_cRsQ_clearReq_dummy2_0$EN),
						       .Q_OUT());

  // submodule mmio_cRsQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_cRsQ_clearReq_dummy2_1(.CLK(CLK),
						       .D_IN(mmio_cRsQ_clearReq_dummy2_1$D_IN),
						       .EN(mmio_cRsQ_clearReq_dummy2_1$EN),
						       .Q_OUT(mmio_cRsQ_clearReq_dummy2_1$Q_OUT));

  // submodule mmio_cRsQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_0(.CLK(CLK),
								    .D_IN(mmio_cRsQ_deqReq_dummy2_0$D_IN),
								    .EN(mmio_cRsQ_deqReq_dummy2_0$EN),
								    .Q_OUT());

  // submodule mmio_cRsQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_1(.CLK(CLK),
								    .D_IN(mmio_cRsQ_deqReq_dummy2_1$D_IN),
								    .EN(mmio_cRsQ_deqReq_dummy2_1$EN),
								    .Q_OUT());

  // submodule mmio_cRsQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_2(.CLK(CLK),
								    .D_IN(mmio_cRsQ_deqReq_dummy2_2$D_IN),
								    .EN(mmio_cRsQ_deqReq_dummy2_2$EN),
								    .Q_OUT(mmio_cRsQ_deqReq_dummy2_2$Q_OUT));

  // submodule mmio_cRsQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_0(.CLK(CLK),
								    .D_IN(mmio_cRsQ_enqReq_dummy2_0$D_IN),
								    .EN(mmio_cRsQ_enqReq_dummy2_0$EN),
								    .Q_OUT());

  // submodule mmio_cRsQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_1(.CLK(CLK),
								    .D_IN(mmio_cRsQ_enqReq_dummy2_1$D_IN),
								    .EN(mmio_cRsQ_enqReq_dummy2_1$EN),
								    .Q_OUT());

  // submodule mmio_cRsQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_2(.CLK(CLK),
								    .D_IN(mmio_cRsQ_enqReq_dummy2_2$D_IN),
								    .EN(mmio_cRsQ_enqReq_dummy2_2$EN),
								    .Q_OUT(mmio_cRsQ_enqReq_dummy2_2$Q_OUT));

  // submodule mmio_dataPendQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataPendQ_clearReq_dummy2_0(.CLK(CLK),
							    .D_IN(mmio_dataPendQ_clearReq_dummy2_0$D_IN),
							    .EN(mmio_dataPendQ_clearReq_dummy2_0$EN),
							    .Q_OUT());

  // submodule mmio_dataPendQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataPendQ_clearReq_dummy2_1(.CLK(CLK),
							    .D_IN(mmio_dataPendQ_clearReq_dummy2_1$D_IN),
							    .EN(mmio_dataPendQ_clearReq_dummy2_1$EN),
							    .Q_OUT(mmio_dataPendQ_clearReq_dummy2_1$Q_OUT));

  // submodule mmio_dataPendQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataPendQ_deqReq_dummy2_0(.CLK(CLK),
							  .D_IN(mmio_dataPendQ_deqReq_dummy2_0$D_IN),
							  .EN(mmio_dataPendQ_deqReq_dummy2_0$EN),
							  .Q_OUT());

  // submodule mmio_dataPendQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataPendQ_deqReq_dummy2_1(.CLK(CLK),
							  .D_IN(mmio_dataPendQ_deqReq_dummy2_1$D_IN),
							  .EN(mmio_dataPendQ_deqReq_dummy2_1$EN),
							  .Q_OUT());

  // submodule mmio_dataPendQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataPendQ_deqReq_dummy2_2(.CLK(CLK),
							  .D_IN(mmio_dataPendQ_deqReq_dummy2_2$D_IN),
							  .EN(mmio_dataPendQ_deqReq_dummy2_2$EN),
							  .Q_OUT(mmio_dataPendQ_deqReq_dummy2_2$Q_OUT));

  // submodule mmio_dataPendQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataPendQ_enqReq_dummy2_0(.CLK(CLK),
							  .D_IN(mmio_dataPendQ_enqReq_dummy2_0$D_IN),
							  .EN(mmio_dataPendQ_enqReq_dummy2_0$EN),
							  .Q_OUT());

  // submodule mmio_dataPendQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataPendQ_enqReq_dummy2_1(.CLK(CLK),
							  .D_IN(mmio_dataPendQ_enqReq_dummy2_1$D_IN),
							  .EN(mmio_dataPendQ_enqReq_dummy2_1$EN),
							  .Q_OUT());

  // submodule mmio_dataPendQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataPendQ_enqReq_dummy2_2(.CLK(CLK),
							  .D_IN(mmio_dataPendQ_enqReq_dummy2_2$D_IN),
							  .EN(mmio_dataPendQ_enqReq_dummy2_2$EN),
							  .Q_OUT(mmio_dataPendQ_enqReq_dummy2_2$Q_OUT));

  // submodule mmio_dataReqQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataReqQ_clearReq_dummy2_0(.CLK(CLK),
							   .D_IN(mmio_dataReqQ_clearReq_dummy2_0$D_IN),
							   .EN(mmio_dataReqQ_clearReq_dummy2_0$EN),
							   .Q_OUT());

  // submodule mmio_dataReqQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataReqQ_clearReq_dummy2_1(.CLK(CLK),
							   .D_IN(mmio_dataReqQ_clearReq_dummy2_1$D_IN),
							   .EN(mmio_dataReqQ_clearReq_dummy2_1$EN),
							   .Q_OUT(mmio_dataReqQ_clearReq_dummy2_1$Q_OUT));

  // submodule mmio_dataReqQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataReqQ_deqReq_dummy2_0(.CLK(CLK),
							 .D_IN(mmio_dataReqQ_deqReq_dummy2_0$D_IN),
							 .EN(mmio_dataReqQ_deqReq_dummy2_0$EN),
							 .Q_OUT());

  // submodule mmio_dataReqQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataReqQ_deqReq_dummy2_1(.CLK(CLK),
							 .D_IN(mmio_dataReqQ_deqReq_dummy2_1$D_IN),
							 .EN(mmio_dataReqQ_deqReq_dummy2_1$EN),
							 .Q_OUT());

  // submodule mmio_dataReqQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataReqQ_deqReq_dummy2_2(.CLK(CLK),
							 .D_IN(mmio_dataReqQ_deqReq_dummy2_2$D_IN),
							 .EN(mmio_dataReqQ_deqReq_dummy2_2$EN),
							 .Q_OUT(mmio_dataReqQ_deqReq_dummy2_2$Q_OUT));

  // submodule mmio_dataReqQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataReqQ_enqReq_dummy2_0(.CLK(CLK),
							 .D_IN(mmio_dataReqQ_enqReq_dummy2_0$D_IN),
							 .EN(mmio_dataReqQ_enqReq_dummy2_0$EN),
							 .Q_OUT());

  // submodule mmio_dataReqQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataReqQ_enqReq_dummy2_1(.CLK(CLK),
							 .D_IN(mmio_dataReqQ_enqReq_dummy2_1$D_IN),
							 .EN(mmio_dataReqQ_enqReq_dummy2_1$EN),
							 .Q_OUT());

  // submodule mmio_dataReqQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataReqQ_enqReq_dummy2_2(.CLK(CLK),
							 .D_IN(mmio_dataReqQ_enqReq_dummy2_2$D_IN),
							 .EN(mmio_dataReqQ_enqReq_dummy2_2$EN),
							 .Q_OUT(mmio_dataReqQ_enqReq_dummy2_2$Q_OUT));

  // submodule mmio_dataRespQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataRespQ_clearReq_dummy2_0(.CLK(CLK),
							    .D_IN(mmio_dataRespQ_clearReq_dummy2_0$D_IN),
							    .EN(mmio_dataRespQ_clearReq_dummy2_0$EN),
							    .Q_OUT());

  // submodule mmio_dataRespQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataRespQ_clearReq_dummy2_1(.CLK(CLK),
							    .D_IN(mmio_dataRespQ_clearReq_dummy2_1$D_IN),
							    .EN(mmio_dataRespQ_clearReq_dummy2_1$EN),
							    .Q_OUT(mmio_dataRespQ_clearReq_dummy2_1$Q_OUT));

  // submodule mmio_dataRespQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataRespQ_deqReq_dummy2_0(.CLK(CLK),
							  .D_IN(mmio_dataRespQ_deqReq_dummy2_0$D_IN),
							  .EN(mmio_dataRespQ_deqReq_dummy2_0$EN),
							  .Q_OUT());

  // submodule mmio_dataRespQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataRespQ_deqReq_dummy2_1(.CLK(CLK),
							  .D_IN(mmio_dataRespQ_deqReq_dummy2_1$D_IN),
							  .EN(mmio_dataRespQ_deqReq_dummy2_1$EN),
							  .Q_OUT());

  // submodule mmio_dataRespQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataRespQ_deqReq_dummy2_2(.CLK(CLK),
							  .D_IN(mmio_dataRespQ_deqReq_dummy2_2$D_IN),
							  .EN(mmio_dataRespQ_deqReq_dummy2_2$EN),
							  .Q_OUT(mmio_dataRespQ_deqReq_dummy2_2$Q_OUT));

  // submodule mmio_dataRespQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataRespQ_enqReq_dummy2_0(.CLK(CLK),
							  .D_IN(mmio_dataRespQ_enqReq_dummy2_0$D_IN),
							  .EN(mmio_dataRespQ_enqReq_dummy2_0$EN),
							  .Q_OUT());

  // submodule mmio_dataRespQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataRespQ_enqReq_dummy2_1(.CLK(CLK),
							  .D_IN(mmio_dataRespQ_enqReq_dummy2_1$D_IN),
							  .EN(mmio_dataRespQ_enqReq_dummy2_1$EN),
							  .Q_OUT());

  // submodule mmio_dataRespQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_dataRespQ_enqReq_dummy2_2(.CLK(CLK),
							  .D_IN(mmio_dataRespQ_enqReq_dummy2_2$D_IN),
							  .EN(mmio_dataRespQ_enqReq_dummy2_2$EN),
							  .Q_OUT(mmio_dataRespQ_enqReq_dummy2_2$Q_OUT));

  // submodule mmio_pRqQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_pRqQ_clearReq_dummy2_0(.CLK(CLK),
						       .D_IN(mmio_pRqQ_clearReq_dummy2_0$D_IN),
						       .EN(mmio_pRqQ_clearReq_dummy2_0$EN),
						       .Q_OUT());

  // submodule mmio_pRqQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_pRqQ_clearReq_dummy2_1(.CLK(CLK),
						       .D_IN(mmio_pRqQ_clearReq_dummy2_1$D_IN),
						       .EN(mmio_pRqQ_clearReq_dummy2_1$EN),
						       .Q_OUT(mmio_pRqQ_clearReq_dummy2_1$Q_OUT));

  // submodule mmio_pRqQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_0(.CLK(CLK),
								    .D_IN(mmio_pRqQ_deqReq_dummy2_0$D_IN),
								    .EN(mmio_pRqQ_deqReq_dummy2_0$EN),
								    .Q_OUT());

  // submodule mmio_pRqQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_1(.CLK(CLK),
								    .D_IN(mmio_pRqQ_deqReq_dummy2_1$D_IN),
								    .EN(mmio_pRqQ_deqReq_dummy2_1$EN),
								    .Q_OUT());

  // submodule mmio_pRqQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_2(.CLK(CLK),
								    .D_IN(mmio_pRqQ_deqReq_dummy2_2$D_IN),
								    .EN(mmio_pRqQ_deqReq_dummy2_2$EN),
								    .Q_OUT(mmio_pRqQ_deqReq_dummy2_2$Q_OUT));

  // submodule mmio_pRqQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_0(.CLK(CLK),
								    .D_IN(mmio_pRqQ_enqReq_dummy2_0$D_IN),
								    .EN(mmio_pRqQ_enqReq_dummy2_0$EN),
								    .Q_OUT());

  // submodule mmio_pRqQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_1(.CLK(CLK),
								    .D_IN(mmio_pRqQ_enqReq_dummy2_1$D_IN),
								    .EN(mmio_pRqQ_enqReq_dummy2_1$EN),
								    .Q_OUT());

  // submodule mmio_pRqQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_2(.CLK(CLK),
								    .D_IN(mmio_pRqQ_enqReq_dummy2_2$D_IN),
								    .EN(mmio_pRqQ_enqReq_dummy2_2$EN),
								    .Q_OUT(mmio_pRqQ_enqReq_dummy2_2$Q_OUT));

  // submodule mmio_pRsQ_clearReq_dummy2_0
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_pRsQ_clearReq_dummy2_0(.CLK(CLK),
						       .D_IN(mmio_pRsQ_clearReq_dummy2_0$D_IN),
						       .EN(mmio_pRsQ_clearReq_dummy2_0$EN),
						       .Q_OUT());

  // submodule mmio_pRsQ_clearReq_dummy2_1
  RevertReg #(.width(32'd1),
	      .init(1'd1)) mmio_pRsQ_clearReq_dummy2_1(.CLK(CLK),
						       .D_IN(mmio_pRsQ_clearReq_dummy2_1$D_IN),
						       .EN(mmio_pRsQ_clearReq_dummy2_1$EN),
						       .Q_OUT(mmio_pRsQ_clearReq_dummy2_1$Q_OUT));

  // submodule mmio_pRsQ_deqReq_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_0(.CLK(CLK),
								    .D_IN(mmio_pRsQ_deqReq_dummy2_0$D_IN),
								    .EN(mmio_pRsQ_deqReq_dummy2_0$EN),
								    .Q_OUT());

  // submodule mmio_pRsQ_deqReq_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_1(.CLK(CLK),
								    .D_IN(mmio_pRsQ_deqReq_dummy2_1$D_IN),
								    .EN(mmio_pRsQ_deqReq_dummy2_1$EN),
								    .Q_OUT());

  // submodule mmio_pRsQ_deqReq_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_2(.CLK(CLK),
								    .D_IN(mmio_pRsQ_deqReq_dummy2_2$D_IN),
								    .EN(mmio_pRsQ_deqReq_dummy2_2$EN),
								    .Q_OUT(mmio_pRsQ_deqReq_dummy2_2$Q_OUT));

  // submodule mmio_pRsQ_enqReq_dummy2_0
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_0(.CLK(CLK),
								    .D_IN(mmio_pRsQ_enqReq_dummy2_0$D_IN),
								    .EN(mmio_pRsQ_enqReq_dummy2_0$EN),
								    .Q_OUT());

  // submodule mmio_pRsQ_enqReq_dummy2_1
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_1(.CLK(CLK),
								    .D_IN(mmio_pRsQ_enqReq_dummy2_1$D_IN),
								    .EN(mmio_pRsQ_enqReq_dummy2_1$EN),
								    .Q_OUT());

  // submodule mmio_pRsQ_enqReq_dummy2_2
  RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_2(.CLK(CLK),
								    .D_IN(mmio_pRsQ_enqReq_dummy2_2$D_IN),
								    .EN(mmio_pRsQ_enqReq_dummy2_2$EN),
								    .Q_OUT(mmio_pRsQ_enqReq_dummy2_2$Q_OUT));

  // submodule perfReqQ
  FIFO1 #(.width(32'd9), .guarded(32'd1)) perfReqQ(.RST(RST_N),
						   .CLK(CLK),
						   .D_IN(perfReqQ$D_IN),
						   .ENQ(perfReqQ$ENQ),
						   .DEQ(perfReqQ$DEQ),
						   .CLR(perfReqQ$CLR),
						   .D_OUT(perfReqQ$D_OUT),
						   .FULL_N(perfReqQ$FULL_N),
						   .EMPTY_N(perfReqQ$EMPTY_N));

  // submodule regRenamingTable
  mkRegRenamingTable regRenamingTable(.CLK(CLK),
				      .RST_N(RST_N),
				      .rename_0_claimRename_r(regRenamingTable$rename_0_claimRename_r),
				      .rename_0_claimRename_sb(regRenamingTable$rename_0_claimRename_sb),
				      .rename_0_getRename_r(regRenamingTable$rename_0_getRename_r),
				      .rename_1_claimRename_r(regRenamingTable$rename_1_claimRename_r),
				      .rename_1_claimRename_sb(regRenamingTable$rename_1_claimRename_sb),
				      .rename_1_getRename_r(regRenamingTable$rename_1_getRename_r),
				      .specUpdate_correctSpeculation_mask(regRenamingTable$specUpdate_correctSpeculation_mask),
				      .specUpdate_incorrectSpeculation_kill_all(regRenamingTable$specUpdate_incorrectSpeculation_kill_all),
				      .specUpdate_incorrectSpeculation_kill_tag(regRenamingTable$specUpdate_incorrectSpeculation_kill_tag),
				      .EN_rename_0_claimRename(regRenamingTable$EN_rename_0_claimRename),
				      .EN_rename_1_claimRename(regRenamingTable$EN_rename_1_claimRename),
				      .EN_commit_0_commit(regRenamingTable$EN_commit_0_commit),
				      .EN_commit_1_commit(regRenamingTable$EN_commit_1_commit),
				      .EN_specUpdate_incorrectSpeculation(regRenamingTable$EN_specUpdate_incorrectSpeculation),
				      .EN_specUpdate_correctSpeculation(regRenamingTable$EN_specUpdate_correctSpeculation),
				      .rename_0_getRename(regRenamingTable$rename_0_getRename),
				      .RDY_rename_0_getRename(regRenamingTable$RDY_rename_0_getRename),
				      .RDY_rename_0_claimRename(regRenamingTable$RDY_rename_0_claimRename),
				      .rename_0_canRename(regRenamingTable$rename_0_canRename),
				      .RDY_rename_0_canRename(),
				      .rename_1_getRename(regRenamingTable$rename_1_getRename),
				      .RDY_rename_1_getRename(regRenamingTable$RDY_rename_1_getRename),
				      .RDY_rename_1_claimRename(regRenamingTable$RDY_rename_1_claimRename),
				      .rename_1_canRename(regRenamingTable$rename_1_canRename),
				      .RDY_rename_1_canRename(),
				      .RDY_commit_0_commit(regRenamingTable$RDY_commit_0_commit),
				      .commit_0_canCommit(),
				      .RDY_commit_0_canCommit(),
				      .RDY_commit_1_commit(regRenamingTable$RDY_commit_1_commit),
				      .commit_1_canCommit(),
				      .RDY_commit_1_canCommit(),
				      .RDY_specUpdate_incorrectSpeculation(),
				      .RDY_specUpdate_correctSpeculation());

  // submodule rf
  mkRFileSynth rf(.CLK(CLK),
		  .RST_N(RST_N),
		  .read_0_rd1_rindx(rf$read_0_rd1_rindx),
		  .read_0_rd2_rindx(rf$read_0_rd2_rindx),
		  .read_0_rd3_rindx(rf$read_0_rd3_rindx),
		  .read_1_rd1_rindx(rf$read_1_rd1_rindx),
		  .read_1_rd2_rindx(rf$read_1_rd2_rindx),
		  .read_1_rd3_rindx(rf$read_1_rd3_rindx),
		  .read_2_rd1_rindx(rf$read_2_rd1_rindx),
		  .read_2_rd2_rindx(rf$read_2_rd2_rindx),
		  .read_2_rd3_rindx(rf$read_2_rd3_rindx),
		  .read_3_rd1_rindx(rf$read_3_rd1_rindx),
		  .read_3_rd2_rindx(rf$read_3_rd2_rindx),
		  .read_3_rd3_rindx(rf$read_3_rd3_rindx),
		  .read_4_rd1_rindx(rf$read_4_rd1_rindx),
		  .read_4_rd2_rindx(rf$read_4_rd2_rindx),
		  .read_4_rd3_rindx(rf$read_4_rd3_rindx),
		  .write_0_wr_data(rf$write_0_wr_data),
		  .write_0_wr_rindx(rf$write_0_wr_rindx),
		  .write_1_wr_data(rf$write_1_wr_data),
		  .write_1_wr_rindx(rf$write_1_wr_rindx),
		  .write_2_wr_data(rf$write_2_wr_data),
		  .write_2_wr_rindx(rf$write_2_wr_rindx),
		  .write_3_wr_data(rf$write_3_wr_data),
		  .write_3_wr_rindx(rf$write_3_wr_rindx),
		  .write_4_wr_data(rf$write_4_wr_data),
		  .write_4_wr_rindx(rf$write_4_wr_rindx),
		  .EN_write_0_wr(rf$EN_write_0_wr),
		  .EN_write_1_wr(rf$EN_write_1_wr),
		  .EN_write_2_wr(rf$EN_write_2_wr),
		  .EN_write_3_wr(rf$EN_write_3_wr),
		  .EN_write_4_wr(rf$EN_write_4_wr),
		  .RDY_write_0_wr(),
		  .RDY_write_1_wr(),
		  .RDY_write_2_wr(),
		  .RDY_write_3_wr(),
		  .RDY_write_4_wr(),
		  .read_0_rd1(rf$read_0_rd1),
		  .RDY_read_0_rd1(),
		  .read_0_rd2(rf$read_0_rd2),
		  .RDY_read_0_rd2(),
		  .read_0_rd3(),
		  .RDY_read_0_rd3(),
		  .read_1_rd1(rf$read_1_rd1),
		  .RDY_read_1_rd1(),
		  .read_1_rd2(rf$read_1_rd2),
		  .RDY_read_1_rd2(),
		  .read_1_rd3(),
		  .RDY_read_1_rd3(),
		  .read_2_rd1(rf$read_2_rd1),
		  .RDY_read_2_rd1(),
		  .read_2_rd2(rf$read_2_rd2),
		  .RDY_read_2_rd2(),
		  .read_2_rd3(rf$read_2_rd3),
		  .RDY_read_2_rd3(),
		  .read_3_rd1(rf$read_3_rd1),
		  .RDY_read_3_rd1(),
		  .read_3_rd2(rf$read_3_rd2),
		  .RDY_read_3_rd2(),
		  .read_3_rd3(),
		  .RDY_read_3_rd3(),
		  .read_4_rd1(),
		  .RDY_read_4_rd1(),
		  .read_4_rd2(),
		  .RDY_read_4_rd2(),
		  .read_4_rd3(),
		  .RDY_read_4_rd3());

  // submodule rob
  mkReorderBufferSynth rob(.CLK(CLK),
			   .RST_N(RST_N),
			   .enqPort_0_enq_x(rob$enqPort_0_enq_x),
			   .enqPort_1_enq_x(rob$enqPort_1_enq_x),
			   .getOrigPC_0_get_x(rob$getOrigPC_0_get_x),
			   .getOrigPC_1_get_x(rob$getOrigPC_1_get_x),
			   .getOrigPC_2_get_x(rob$getOrigPC_2_get_x),
			   .getOrigPredPC_0_get_x(rob$getOrigPredPC_0_get_x),
			   .getOrigPredPC_1_get_x(rob$getOrigPredPC_1_get_x),
			   .getOrig_Inst_0_get_x(rob$getOrig_Inst_0_get_x),
			   .getOrig_Inst_1_get_x(rob$getOrig_Inst_1_get_x),
			   .setExecuted_deqLSQ_cause(rob$setExecuted_deqLSQ_cause),
			   .setExecuted_deqLSQ_ld_killed(rob$setExecuted_deqLSQ_ld_killed),
			   .setExecuted_deqLSQ_x(rob$setExecuted_deqLSQ_x),
			   .setExecuted_doFinishAlu_0_set_cf(rob$setExecuted_doFinishAlu_0_set_cf),
			   .setExecuted_doFinishAlu_0_set_csrData(rob$setExecuted_doFinishAlu_0_set_csrData),
			   .setExecuted_doFinishAlu_0_set_dst_data(rob$setExecuted_doFinishAlu_0_set_dst_data),
			   .setExecuted_doFinishAlu_0_set_x(rob$setExecuted_doFinishAlu_0_set_x),
			   .setExecuted_doFinishAlu_1_set_cf(rob$setExecuted_doFinishAlu_1_set_cf),
			   .setExecuted_doFinishAlu_1_set_csrData(rob$setExecuted_doFinishAlu_1_set_csrData),
			   .setExecuted_doFinishAlu_1_set_dst_data(rob$setExecuted_doFinishAlu_1_set_dst_data),
			   .setExecuted_doFinishAlu_1_set_x(rob$setExecuted_doFinishAlu_1_set_x),
			   .setExecuted_doFinishFpuMulDiv_0_set_dst_data(rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data),
			   .setExecuted_doFinishFpuMulDiv_0_set_fflags(rob$setExecuted_doFinishFpuMulDiv_0_set_fflags),
			   .setExecuted_doFinishFpuMulDiv_0_set_x(rob$setExecuted_doFinishFpuMulDiv_0_set_x),
			   .setExecuted_doFinishMem_access_at_commit(rob$setExecuted_doFinishMem_access_at_commit),
			   .setExecuted_doFinishMem_non_mmio_st_done(rob$setExecuted_doFinishMem_non_mmio_st_done),
			   .setExecuted_doFinishMem_store_data(rob$setExecuted_doFinishMem_store_data),
			   .setExecuted_doFinishMem_store_data_BE(rob$setExecuted_doFinishMem_store_data_BE),
			   .setExecuted_doFinishMem_vaddr(rob$setExecuted_doFinishMem_vaddr),
			   .setExecuted_doFinishMem_x(rob$setExecuted_doFinishMem_x),
			   .setLSQAtCommitNotified_x(rob$setLSQAtCommitNotified_x),
			   .specUpdate_correctSpeculation_mask(rob$specUpdate_correctSpeculation_mask),
			   .specUpdate_incorrectSpeculation_inst_tag(rob$specUpdate_incorrectSpeculation_inst_tag),
			   .specUpdate_incorrectSpeculation_kill_all(rob$specUpdate_incorrectSpeculation_kill_all),
			   .specUpdate_incorrectSpeculation_spec_tag(rob$specUpdate_incorrectSpeculation_spec_tag),
			   .EN_enqPort_0_enq(rob$EN_enqPort_0_enq),
			   .EN_enqPort_1_enq(rob$EN_enqPort_1_enq),
			   .EN_deqPort_0_deq(rob$EN_deqPort_0_deq),
			   .EN_deqPort_1_deq(rob$EN_deqPort_1_deq),
			   .EN_setLSQAtCommitNotified(rob$EN_setLSQAtCommitNotified),
			   .EN_setExecuted_deqLSQ(rob$EN_setExecuted_deqLSQ),
			   .EN_setExecuted_doFinishAlu_0_set(rob$EN_setExecuted_doFinishAlu_0_set),
			   .EN_setExecuted_doFinishAlu_1_set(rob$EN_setExecuted_doFinishAlu_1_set),
			   .EN_setExecuted_doFinishFpuMulDiv_0_set(rob$EN_setExecuted_doFinishFpuMulDiv_0_set),
			   .EN_setExecuted_doFinishMem(rob$EN_setExecuted_doFinishMem),
			   .EN_specUpdate_incorrectSpeculation(rob$EN_specUpdate_incorrectSpeculation),
			   .EN_specUpdate_correctSpeculation(rob$EN_specUpdate_correctSpeculation),
			   .enqPort_0_canEnq(rob$enqPort_0_canEnq),
			   .RDY_enqPort_0_canEnq(),
			   .RDY_enqPort_0_enq(rob$RDY_enqPort_0_enq),
			   .enqPort_0_getEnqInstTag(rob$enqPort_0_getEnqInstTag),
			   .RDY_enqPort_0_getEnqInstTag(),
			   .enqPort_1_canEnq(rob$enqPort_1_canEnq),
			   .RDY_enqPort_1_canEnq(),
			   .RDY_enqPort_1_enq(rob$RDY_enqPort_1_enq),
			   .enqPort_1_getEnqInstTag(rob$enqPort_1_getEnqInstTag),
			   .RDY_enqPort_1_getEnqInstTag(),
			   .isEmpty(rob$isEmpty),
			   .RDY_isEmpty(),
			   .deqPort_0_canDeq(rob$deqPort_0_canDeq),
			   .RDY_deqPort_0_canDeq(),
			   .RDY_deqPort_0_deq(rob$RDY_deqPort_0_deq),
			   .deqPort_0_getDeqInstTag(rob$deqPort_0_getDeqInstTag),
			   .RDY_deqPort_0_getDeqInstTag(),
			   .deqPort_0_deq_data(rob$deqPort_0_deq_data),
			   .RDY_deqPort_0_deq_data(rob$RDY_deqPort_0_deq_data),
			   .deqPort_1_canDeq(rob$deqPort_1_canDeq),
			   .RDY_deqPort_1_canDeq(),
			   .RDY_deqPort_1_deq(rob$RDY_deqPort_1_deq),
			   .deqPort_1_getDeqInstTag(),
			   .RDY_deqPort_1_getDeqInstTag(),
			   .deqPort_1_deq_data(rob$deqPort_1_deq_data),
			   .RDY_deqPort_1_deq_data(rob$RDY_deqPort_1_deq_data),
			   .RDY_setLSQAtCommitNotified(rob$RDY_setLSQAtCommitNotified),
			   .RDY_setExecuted_deqLSQ(rob$RDY_setExecuted_deqLSQ),
			   .RDY_setExecuted_doFinishAlu_0_set(rob$RDY_setExecuted_doFinishAlu_0_set),
			   .RDY_setExecuted_doFinishAlu_1_set(rob$RDY_setExecuted_doFinishAlu_1_set),
			   .RDY_setExecuted_doFinishFpuMulDiv_0_set(rob$RDY_setExecuted_doFinishFpuMulDiv_0_set),
			   .RDY_setExecuted_doFinishMem(rob$RDY_setExecuted_doFinishMem),
			   .getOrigPC_0_get(rob$getOrigPC_0_get),
			   .RDY_getOrigPC_0_get(),
			   .getOrigPC_1_get(rob$getOrigPC_1_get),
			   .RDY_getOrigPC_1_get(),
			   .getOrigPC_2_get(),
			   .RDY_getOrigPC_2_get(),
			   .getOrigPredPC_0_get(rob$getOrigPredPC_0_get),
			   .RDY_getOrigPredPC_0_get(),
			   .getOrigPredPC_1_get(rob$getOrigPredPC_1_get),
			   .RDY_getOrigPredPC_1_get(),
			   .getOrig_Inst_0_get(rob$getOrig_Inst_0_get),
			   .RDY_getOrig_Inst_0_get(),
			   .getOrig_Inst_1_get(rob$getOrig_Inst_1_get),
			   .RDY_getOrig_Inst_1_get(),
			   .getEnqTime(rob$getEnqTime),
			   .RDY_getEnqTime(),
			   .isEmpty_ehrPort0(),
			   .RDY_isEmpty_ehrPort0(),
			   .isFull_ehrPort0(),
			   .RDY_isFull_ehrPort0(),
			   .RDY_specUpdate_incorrectSpeculation(),
			   .RDY_specUpdate_correctSpeculation());

  // submodule sbAggr
  mkScoreboardAggr sbAggr(.CLK(CLK),
			  .RST_N(RST_N),
			  .eagerLookup_0_get_r(sbAggr$eagerLookup_0_get_r),
			  .eagerLookup_1_get_r(sbAggr$eagerLookup_1_get_r),
			  .setBusy_0_set_dst(sbAggr$setBusy_0_set_dst),
			  .setBusy_1_set_dst(sbAggr$setBusy_1_set_dst),
			  .setReady_0_put(sbAggr$setReady_0_put),
			  .setReady_1_put(sbAggr$setReady_1_put),
			  .setReady_2_put(sbAggr$setReady_2_put),
			  .setReady_3_put(sbAggr$setReady_3_put),
			  .setReady_4_put(sbAggr$setReady_4_put),
			  .EN_setBusy_0_set(sbAggr$EN_setBusy_0_set),
			  .EN_setBusy_1_set(sbAggr$EN_setBusy_1_set),
			  .EN_setReady_0_put(sbAggr$EN_setReady_0_put),
			  .EN_setReady_1_put(sbAggr$EN_setReady_1_put),
			  .EN_setReady_2_put(sbAggr$EN_setReady_2_put),
			  .EN_setReady_3_put(sbAggr$EN_setReady_3_put),
			  .EN_setReady_4_put(sbAggr$EN_setReady_4_put),
			  .eagerLookup_0_get(sbAggr$eagerLookup_0_get),
			  .RDY_eagerLookup_0_get(),
			  .eagerLookup_1_get(sbAggr$eagerLookup_1_get),
			  .RDY_eagerLookup_1_get(),
			  .RDY_setBusy_0_set(),
			  .RDY_setBusy_1_set(),
			  .RDY_setReady_0_put(),
			  .RDY_setReady_1_put(),
			  .RDY_setReady_2_put(),
			  .RDY_setReady_3_put(),
			  .RDY_setReady_4_put());

  // submodule sbCons
  mkScoreboardCons sbCons(.CLK(CLK),
			  .RST_N(RST_N),
			  .eagerLookup_0_get_r(sbCons$eagerLookup_0_get_r),
			  .eagerLookup_1_get_r(sbCons$eagerLookup_1_get_r),
			  .lazyLookup_0_get_r(sbCons$lazyLookup_0_get_r),
			  .lazyLookup_1_get_r(sbCons$lazyLookup_1_get_r),
			  .lazyLookup_2_get_r(sbCons$lazyLookup_2_get_r),
			  .lazyLookup_3_get_r(sbCons$lazyLookup_3_get_r),
			  .lazyLookup_4_get_r(sbCons$lazyLookup_4_get_r),
			  .setBusy_0_set_dst(sbCons$setBusy_0_set_dst),
			  .setBusy_1_set_dst(sbCons$setBusy_1_set_dst),
			  .setReady_0_put(sbCons$setReady_0_put),
			  .setReady_1_put(sbCons$setReady_1_put),
			  .setReady_2_put(sbCons$setReady_2_put),
			  .setReady_3_put(sbCons$setReady_3_put),
			  .setReady_4_put(sbCons$setReady_4_put),
			  .EN_setBusy_0_set(sbCons$EN_setBusy_0_set),
			  .EN_setBusy_1_set(sbCons$EN_setBusy_1_set),
			  .EN_setReady_0_put(sbCons$EN_setReady_0_put),
			  .EN_setReady_1_put(sbCons$EN_setReady_1_put),
			  .EN_setReady_2_put(sbCons$EN_setReady_2_put),
			  .EN_setReady_3_put(sbCons$EN_setReady_3_put),
			  .EN_setReady_4_put(sbCons$EN_setReady_4_put),
			  .eagerLookup_0_get(),
			  .RDY_eagerLookup_0_get(),
			  .eagerLookup_1_get(),
			  .RDY_eagerLookup_1_get(),
			  .RDY_setBusy_0_set(),
			  .RDY_setBusy_1_set(),
			  .RDY_setReady_0_put(),
			  .RDY_setReady_1_put(),
			  .RDY_setReady_2_put(),
			  .RDY_setReady_3_put(),
			  .RDY_setReady_4_put(),
			  .lazyLookup_0_get(sbCons$lazyLookup_0_get),
			  .RDY_lazyLookup_0_get(),
			  .lazyLookup_1_get(sbCons$lazyLookup_1_get),
			  .RDY_lazyLookup_1_get(),
			  .lazyLookup_2_get(sbCons$lazyLookup_2_get),
			  .RDY_lazyLookup_2_get(),
			  .lazyLookup_3_get(sbCons$lazyLookup_3_get),
			  .RDY_lazyLookup_3_get(),
			  .lazyLookup_4_get(),
			  .RDY_lazyLookup_4_get());

  // submodule specTagManager
  mkSpecTagManager specTagManager(.CLK(CLK),
				  .RST_N(RST_N),
				  .specUpdate_correctSpeculation_mask(specTagManager$specUpdate_correctSpeculation_mask),
				  .specUpdate_incorrectSpeculation_kill_all(specTagManager$specUpdate_incorrectSpeculation_kill_all),
				  .specUpdate_incorrectSpeculation_kill_tag(specTagManager$specUpdate_incorrectSpeculation_kill_tag),
				  .EN_claimSpecTag(specTagManager$EN_claimSpecTag),
				  .EN_specUpdate_incorrectSpeculation(specTagManager$EN_specUpdate_incorrectSpeculation),
				  .EN_specUpdate_correctSpeculation(specTagManager$EN_specUpdate_correctSpeculation),
				  .currentSpecBits(specTagManager$currentSpecBits),
				  .RDY_currentSpecBits(),
				  .nextSpecTag(specTagManager$nextSpecTag),
				  .RDY_nextSpecTag(specTagManager$RDY_nextSpecTag),
				  .RDY_claimSpecTag(specTagManager$RDY_claimSpecTag),
				  .canClaim(specTagManager$canClaim),
				  .RDY_canClaim(),
				  .RDY_specUpdate_incorrectSpeculation(),
				  .RDY_specUpdate_correctSpeculation(),
				  .isFull_ehrPort0(),
				  .RDY_isFull_ehrPort0());

  // rule RL_rl_outOfReset
  assign CAN_FIRE_RL_rl_outOfReset = !outOfReset ;
  assign WILL_FIRE_RL_rl_outOfReset = CAN_FIRE_RL_rl_outOfReset ;

  // rule RL_sendDTlbReq
  assign CAN_FIRE_RL_sendDTlbReq =
	     coreFix_memExe_dTlb$RDY_toParent_rqToP_deq &&
	     coreFix_memExe_dTlb$RDY_toParent_rqToP_first &&
	     l2Tlb$RDY_toChildren_rqFromC_put ;
  assign WILL_FIRE_RL_sendDTlbReq = CAN_FIRE_RL_sendDTlbReq ;

  // rule RL_sendITlbReq
  assign CAN_FIRE_RL_sendITlbReq =
	     fetchStage$RDY_iTlbIfc_toParent_rqToP_deq &&
	     fetchStage$RDY_iTlbIfc_toParent_rqToP_first &&
	     l2Tlb$RDY_toChildren_rqFromC_put ;
  assign WILL_FIRE_RL_sendITlbReq =
	     CAN_FIRE_RL_sendITlbReq && !WILL_FIRE_RL_sendDTlbReq ;

  // rule RL_sendRsToDTlb
  assign CAN_FIRE_RL_sendRsToDTlb =
	     l2Tlb$RDY_toChildren_rsToC_deq &&
	     l2Tlb$RDY_toChildren_rsToC_first &&
	     coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq &&
	     l2Tlb$toChildren_rsToC_first[83] ;
  assign WILL_FIRE_RL_sendRsToDTlb = CAN_FIRE_RL_sendRsToDTlb ;

  // rule RL_sendRsToITlb
  assign CAN_FIRE_RL_sendRsToITlb =
	     fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq &&
	     l2Tlb$RDY_toChildren_rsToC_deq &&
	     l2Tlb$RDY_toChildren_rsToC_first &&
	     !l2Tlb$toChildren_rsToC_first[83] ;
  assign WILL_FIRE_RL_sendRsToITlb = CAN_FIRE_RL_sendRsToITlb ;

  // rule RL_mkConnectionGetPut
  assign CAN_FIRE_RL_mkConnectionGetPut =
	     coreFix_memExe_dTlb$RDY_toParent_flush_request_get &&
	     l2Tlb$RDY_toChildren_dTlbReqFlush_put ;
  assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ;

  // rule RL_mkConnectionGetPut_1
  assign CAN_FIRE_RL_mkConnectionGetPut_1 =
	     fetchStage$RDY_iTlbIfc_toParent_flush_request_get &&
	     l2Tlb$RDY_toChildren_iTlbReqFlush_put ;
  assign WILL_FIRE_RL_mkConnectionGetPut_1 =
	     CAN_FIRE_RL_mkConnectionGetPut_1 ;

  // rule RL_sendFlushDone
  assign CAN_FIRE_RL_sendFlushDone =
	     fetchStage$RDY_iTlbIfc_toParent_flush_response_put &&
	     coreFix_memExe_dTlb$RDY_toParent_flush_response_put &&
	     l2Tlb$RDY_toChildren_flushDone_get ;
  assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ;

  // rule RL_sendRobEnqTime
  assign CAN_FIRE_RL_sendRobEnqTime = 1'd1 ;
  assign WILL_FIRE_RL_sendRobEnqTime = 1'd1 ;

  // rule RL_readyToFetch
  assign CAN_FIRE_RL_readyToFetch =
	     fetchStage$RDY_done_flushing && !flush_reservation &&
	     !flush_tlbs &&
	     !update_vm_info &&
	     fetchStage$iTlbIfc_flush_done &&
	     coreFix_memExe_dTlb$flush_done ;
  assign WILL_FIRE_RL_readyToFetch = CAN_FIRE_RL_readyToFetch ;

  // rule RL_csrf_minstret_ehr_setRead
  assign CAN_FIRE_RL_csrf_minstret_ehr_setRead = 1'd1 ;
  assign WILL_FIRE_RL_csrf_minstret_ehr_setRead = 1'd1 ;

  // rule RL_csrf_mcycle_ehr_setRead
  assign CAN_FIRE_RL_csrf_mcycle_ehr_setRead = 1'd1 ;
  assign WILL_FIRE_RL_csrf_mcycle_ehr_setRead = 1'd1 ;

  // rule RL_mmio_handlePRq
  assign CAN_FIRE_RL_mmio_handlePRq =
	     !mmio_pRqQ_empty && !mmio_cRsQ_full &&
	     (!csrInstOrInterruptInflight_dummy2_0$Q_OUT ||
	      !csrInstOrInterruptInflight_dummy2_1$Q_OUT ||
	      !csrInstOrInterruptInflight_rl) ;
  assign WILL_FIRE_RL_mmio_handlePRq = CAN_FIRE_RL_mmio_handlePRq ;

  // rule RL_mmio_sendDataReq
  assign CAN_FIRE_RL_mmio_sendDataReq =
	     !mmio_dataReqQ_empty && !mmio_cRqQ_full ;
  assign WILL_FIRE_RL_mmio_sendDataReq = CAN_FIRE_RL_mmio_sendDataReq ;

  // rule RL_mmio_sendInstReq
  assign CAN_FIRE_RL_mmio_sendInstReq =
	     !mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_deq &&
	     fetchStage$RDY_mmioIfc_instReq_first_fst &&
	     fetchStage$RDY_mmioIfc_instReq_first_snd ;
  assign WILL_FIRE_RL_mmio_sendInstReq =
	     CAN_FIRE_RL_mmio_sendInstReq && !WILL_FIRE_RL_mmio_sendDataReq ;

  // rule RL_mmio_sendDataResp
  assign CAN_FIRE_RL_mmio_sendDataResp =
	     !mmio_dataRespQ_full && !mmio_pRsQ_empty &&
	     mmio_pRsQ_data_0[66] ;
  assign WILL_FIRE_RL_mmio_sendDataResp = CAN_FIRE_RL_mmio_sendDataResp ;

  // rule RL_mmio_sendInstResp
  assign CAN_FIRE_RL_mmio_sendInstResp =
	     !mmio_pRsQ_empty && fetchStage$RDY_mmioIfc_instResp_enq &&
	     !mmio_pRsQ_data_0[66] ;
  assign WILL_FIRE_RL_mmio_sendInstResp = CAN_FIRE_RL_mmio_sendInstResp ;

  // rule RL_mmio_cRqQ_canonicalize
  assign CAN_FIRE_RL_mmio_cRqQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_mmio_cRqQ_canonicalize = 1'd1 ;

  // rule RL_mmio_cRqQ_enqReq_canon
  assign CAN_FIRE_RL_mmio_cRqQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_cRqQ_enqReq_canon = 1'd1 ;

  // rule RL_mmio_cRqQ_deqReq_canon
  assign CAN_FIRE_RL_mmio_cRqQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_cRqQ_deqReq_canon = 1'd1 ;

  // rule RL_mmio_cRqQ_clearReq_canon
  assign CAN_FIRE_RL_mmio_cRqQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_cRqQ_clearReq_canon = 1'd1 ;

  // rule RL_mmio_pRsQ_canonicalize
  assign CAN_FIRE_RL_mmio_pRsQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_mmio_pRsQ_canonicalize = 1'd1 ;

  // rule RL_mmio_pRsQ_enqReq_canon
  assign CAN_FIRE_RL_mmio_pRsQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_pRsQ_enqReq_canon = 1'd1 ;

  // rule RL_mmio_pRsQ_deqReq_canon
  assign CAN_FIRE_RL_mmio_pRsQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_pRsQ_deqReq_canon = 1'd1 ;

  // rule RL_mmio_pRsQ_clearReq_canon
  assign CAN_FIRE_RL_mmio_pRsQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_pRsQ_clearReq_canon = 1'd1 ;

  // rule RL_mmio_cRsQ_canonicalize
  assign CAN_FIRE_RL_mmio_cRsQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_mmio_cRsQ_canonicalize = 1'd1 ;

  // rule RL_mmio_cRsQ_enqReq_canon
  assign CAN_FIRE_RL_mmio_cRsQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_cRsQ_enqReq_canon = 1'd1 ;

  // rule RL_mmio_cRsQ_deqReq_canon
  assign CAN_FIRE_RL_mmio_cRsQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_cRsQ_deqReq_canon = 1'd1 ;

  // rule RL_mmio_cRsQ_clearReq_canon
  assign CAN_FIRE_RL_mmio_cRsQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_cRsQ_clearReq_canon = 1'd1 ;

  // rule RL_coreFix_doFetchTrainBP
  assign CAN_FIRE_RL_coreFix_doFetchTrainBP = coreFix_trainBPQ_1$EMPTY_N ;
  assign WILL_FIRE_RL_coreFix_doFetchTrainBP = coreFix_trainBPQ_1$EMPTY_N ;

  // rule RL_coreFix_doFetchTrainBP_1
  assign CAN_FIRE_RL_coreFix_doFetchTrainBP_1 = coreFix_trainBPQ_0$EMPTY_N ;
  assign WILL_FIRE_RL_coreFix_doFetchTrainBP_1 =
	     coreFix_trainBPQ_0$EMPTY_N && !coreFix_trainBPQ_1$EMPTY_N ;

  // rule RL_coreFix_memExe_doIssueSB
  assign CAN_FIRE_RL_coreFix_memExe_doIssueSB =
	     (!coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT ||
	      !coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT ||
	      !coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT ||
	      !coreFix_memExe_reqStQ_full_rl) &&
	     coreFix_memExe_stb$RDY_issue ;
  assign WILL_FIRE_RL_coreFix_memExe_doIssueSB =
	     CAN_FIRE_RL_coreFix_memExe_doIssueSB ;

  // rule RL_coreFix_memExe_doDeqLdQ_Lr_issue
  assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue =
	     NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1026 &&
	     coreFix_memExe_lsq$RDY_firstLd &&
	     !coreFix_memExe_lsq$firstLd[7] &&
	     !coreFix_memExe_lsq$firstLd[16] &&
	     coreFix_memExe_lsq$firstLd[101] &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
	     coreFix_memExe_stb$noMatchLdQ &&
	     (!coreFix_memExe_lsq$firstLd[90] || coreFix_memExe_stb$isEmpty) ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue =
	     CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;

  // rule RL_coreFix_memExe_doDeqLdQ_MMIO_issue
  assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue =
	     !mmio_dataReqQ_full && !mmio_dataPendQ_full &&
	     coreFix_memExe_lsq$RDY_firstLd &&
	     !coreFix_memExe_lsq$firstLd[7] &&
	     coreFix_memExe_lsq$firstLd[16] &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
	     (!coreFix_memExe_lsq$firstLd[90] || coreFix_memExe_stb$isEmpty) ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue =
	     CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ;

  // rule RL_coreFix_memExe_dMem_perfReqQ_canonicalize
  assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize = 1'd1 ;

  // rule RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp =
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$EMPTY_N &&
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP =
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N &&
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$EMPTY_N ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq =
	     !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full &&
	     coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry &&
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N &&
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[3] ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP =
	     !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full &&
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$EMPTY_N ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq =
	     !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full &&
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N &&
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$FULL_N &&
	     !coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[3] ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo =
	     !coreFix_memExe_respLrScAmoQ_full &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
	     coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2778 &&
	     !coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] ==
	     2'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon =
	     1'd1 ;

  // rule RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned =
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned ;

  // rule RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned =
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned ;

  // rule RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned =
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned ;

  // rule RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned =
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned ;

  // rule RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned =
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$EMPTY_N &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned ;

  // rule RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute =
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$EMPTY_N &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$EMPTY_N &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$FULL_N ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute ;

  // rule RL_renameStage_doRenaming_wrongPath
  assign CAN_FIRE_RL_renameStage_doRenaming_wrongPath =
	     fetchStage$RDY_pipelines_0_first &&
	     (!fetchStage$pipelines_0_canDeq ||
	      epochManager$checkEpoch_0_check ||
	      fetchStage$RDY_pipelines_0_deq) &&
	     NOT_fetchStage_pipelines_1_canDeq__2934_2935_O_ETC___d12943 &&
	     !epochManager$checkEpoch_0_check ;
  assign WILL_FIRE_RL_renameStage_doRenaming_wrongPath =
	     CAN_FIRE_RL_renameStage_doRenaming_wrongPath ;

  // rule RL_commitStage_doCommitTrap_flush
  assign CAN_FIRE_RL_commitStage_doCommitTrap_flush =
	     rob$RDY_deqPort_0_deq && rob$RDY_deqPort_0_deq_data &&
	     (rob$deqPort_0_deq_data[12] ||
	      epochManager$RDY_incrementEpoch) &&
	     !commitStage_commitTrap[165] &&
	     rob$deqPort_0_deq_data[167] ;
  assign WILL_FIRE_RL_commitStage_doCommitTrap_flush =
	     CAN_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_renameStage_doRenaming &&
	     !WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	     !WILL_FIRE_RL_renameStage_doRenaming_Trap &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     !WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doExeMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_commitStage_doCommitTrap_handle
  assign CAN_FIRE_RL_commitStage_doCommitTrap_handle =
	     coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty &&
	     fetchStage$iTlbIfc_noPendingReq &&
	     coreFix_memExe_dTlb$noPendingReq &&
	     commitStage_commitTrap[165] ;
  assign WILL_FIRE_RL_commitStage_doCommitTrap_handle =
	     CAN_FIRE_RL_commitStage_doCommitTrap_handle &&
	     !WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	     !WILL_FIRE_RL_renameStage_doRenaming_Trap &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_prepareCachesAndTlbs ;

  // rule RL_commitStage_doCommitKilledLd
  assign CAN_FIRE_RL_commitStage_doCommitKilledLd =
	     epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq &&
	     rob$RDY_deqPort_0_deq_data &&
	     !commitStage_commitTrap[165] &&
	     !rob$deqPort_0_deq_data[167] &&
	     rob$deqPort_0_deq_data[18] ;
  assign WILL_FIRE_RL_commitStage_doCommitKilledLd =
	     CAN_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_renameStage_doRenaming &&
	     !WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	     !WILL_FIRE_RL_renameStage_doRenaming_Trap &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     !WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doExeMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_commitStage_doCommitSystemInst
  assign CAN_FIRE_RL_commitStage_doCommitSystemInst =
	     coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14793 &&
	     !commitStage_commitTrap[165] &&
	     !rob$deqPort_0_deq_data[167] &&
	     !rob$deqPort_0_deq_data[18] &&
	     rob$deqPort_0_deq_data[25] &&
	     (rob$deqPort_0_deq_data[257:253] == 5'd0 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd21 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd17 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd18 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd13 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd16 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd15 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd19 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd20) ;
  assign WILL_FIRE_RL_commitStage_doCommitSystemInst =
	     CAN_FIRE_RL_commitStage_doCommitSystemInst &&
	     !WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	     !WILL_FIRE_RL_renameStage_doRenaming_Trap &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_prepareCachesAndTlbs ;

  // rule RL_csrf_incCycle
  assign CAN_FIRE_RL_csrf_incCycle = 1'd1 ;
  assign WILL_FIRE_RL_csrf_incCycle = 1'd1 ;

  // rule RL_csrf_mcycle_ehr_data_canon
  assign CAN_FIRE_RL_csrf_mcycle_ehr_data_canon = 1'd1 ;
  assign WILL_FIRE_RL_csrf_mcycle_ehr_data_canon = 1'd1 ;

  // rule RL_commitStage_notifyLSQCommit
  assign CAN_FIRE_RL_commitStage_notifyLSQCommit =
	     rob$RDY_setLSQAtCommitNotified && rob$RDY_deqPort_0_deq_data &&
	     !commitStage_commitTrap[165] &&
	     !rob$deqPort_0_deq_data[167] &&
	     !rob$deqPort_0_deq_data[18] &&
	     !rob$deqPort_0_deq_data[25] &&
	     rob$deqPort_0_deq_data[15] &&
	     !rob$deqPort_0_deq_data[14] ;
  assign WILL_FIRE_RL_commitStage_notifyLSQCommit =
	     CAN_FIRE_RL_commitStage_notifyLSQCommit ;

  // rule RL_commitStage_doCommitNormalInst
  assign CAN_FIRE_RL_commitStage_doCommitNormalInst =
	     rob$RDY_deqPort_0_deq_data &&
	     NOT_rob_deqPort_0_canDeq__4995_4996_OR_regRena_ETC___d15034 &&
	     !commitStage_commitTrap[165] &&
	     !rob$deqPort_0_deq_data[167] &&
	     !rob$deqPort_0_deq_data[18] &&
	     rob$deqPort_0_deq_data[25] &&
	     rob$deqPort_0_deq_data[257:253] != 5'd0 &&
	     rob$deqPort_0_deq_data[257:253] != 5'd21 &&
	     rob$deqPort_0_deq_data[257:253] != 5'd17 &&
	     rob$deqPort_0_deq_data[257:253] != 5'd18 &&
	     rob$deqPort_0_deq_data[257:253] != 5'd13 &&
	     rob$deqPort_0_deq_data[257:253] != 5'd16 &&
	     rob$deqPort_0_deq_data[257:253] != 5'd15 &&
	     rob$deqPort_0_deq_data[257:253] != 5'd19 &&
	     rob$deqPort_0_deq_data[257:253] != 5'd20 ;
  assign WILL_FIRE_RL_commitStage_doCommitNormalInst =
	     CAN_FIRE_RL_commitStage_doCommitNormalInst ;

  // rule RL_csrf_minstret_ehr_data_canon
  assign CAN_FIRE_RL_csrf_minstret_ehr_data_canon = 1'd1 ;
  assign WILL_FIRE_RL_csrf_minstret_ehr_data_canon = 1'd1 ;

  // rule RL_coreFix_aluExe_1_doFinishAlu_T
  assign CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T =
	     coreFix_aluExe_1_exeToFinQ$first[17] &&
	     coreFix_aluExe_1_exeToFinQ$RDY_deq &&
	     coreFix_aluExe_1_exeToFinQ$RDY_first &&
	     rob$RDY_setExecuted_doFinishAlu_1_set &&
	     epochManager$RDY_incrementEpoch &&
	     coreFix_trainBPQ_1$FULL_N ;
  assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T =
	     CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     !WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doExeMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_coreFix_aluExe_0_doFinishAlu_T
  assign CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T =
	     coreFix_aluExe_0_exeToFinQ$first[17] &&
	     coreFix_aluExe_0_exeToFinQ$RDY_deq &&
	     coreFix_aluExe_0_exeToFinQ$RDY_first &&
	     rob$RDY_setExecuted_doFinishAlu_0_set &&
	     epochManager$RDY_incrementEpoch &&
	     coreFix_trainBPQ_0$FULL_N ;
  assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T =
	     CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     !WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doExeMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_coreFix_aluExe_0_doFinishAlu_F
  assign CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F =
	     !coreFix_aluExe_0_exeToFinQ$first[17] &&
	     coreFix_aluExe_0_exeToFinQ$RDY_deq &&
	     coreFix_aluExe_0_exeToFinQ_RDY_first__2811_AND_ETC___d12851 ;
  assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F =
	     CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ;

  // rule RL_coreFix_aluExe_1_doFinishAlu_F
  assign CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F =
	     !coreFix_aluExe_1_exeToFinQ$first[17] &&
	     coreFix_aluExe_1_exeToFinQ$RDY_deq &&
	     coreFix_aluExe_1_exeToFinQ_RDY_first__2137_AND_ETC___d12178 ;
  assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F =
	     CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ;

  // rule RL_coreFix_aluExe_1_doExeAlu
  assign CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu =
	     coreFix_aluExe_1_regToExeQ$RDY_deq &&
	     coreFix_aluExe_1_exeToFinQ$RDY_enq &&
	     coreFix_aluExe_1_regToExeQ$RDY_first ;
  assign WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu =
	     CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_aluExe_0_doExeAlu
  assign CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu =
	     coreFix_aluExe_0_regToExeQ$RDY_deq &&
	     coreFix_aluExe_0_exeToFinQ$RDY_enq &&
	     coreFix_aluExe_0_regToExeQ$RDY_first ;
  assign WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu =
	     CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_aluExe_1_doRegReadAlu
  assign CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu =
	     coreFix_aluExe_1_dispToRegQ$RDY_deq &&
	     coreFix_aluExe_1_regToExeQ$RDY_enq &&
	     coreFix_aluExe_1_dispToRegQ_RDY_first__1488_AN_ETC___d11579 ;
  assign WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu =
	     CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_aluExe_0_doRegReadAlu
  assign CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu =
	     coreFix_aluExe_0_dispToRegQ$RDY_deq &&
	     coreFix_aluExe_0_regToExeQ$RDY_enq &&
	     coreFix_aluExe_0_dispToRegQ_RDY_first__2344_AN_ETC___d12435 ;
  assign WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu =
	     CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_aluExe_0_doDispatchAlu
  assign CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu =
	     coreFix_aluExe_0_dispToRegQ$RDY_enq &&
	     coreFix_aluExe_0_rsAlu$RDY_dispatchData &&
	     coreFix_aluExe_0_rsAlu$RDY_doDispatch ;
  assign WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu =
	     CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_aluExe_1_doDispatchAlu
  assign CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu =
	     coreFix_aluExe_1_dispToRegQ$RDY_enq &&
	     coreFix_aluExe_1_rsAlu$RDY_dispatchData &&
	     coreFix_aluExe_1_rsAlu$RDY_doDispatch ;
  assign WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu =
	     CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_fpuMulDivExe_0_doFinishFpSimple
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple =
	     coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_first &&
	     rob$RDY_setExecuted_doFinishFpuMulDiv_0_set ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;

  // rule RL_coreFix_fpuMulDivExe_0_doFinishFpFma
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma =
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3976 ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;

  // rule RL_coreFix_fpuMulDivExe_0_doFinishFpDiv
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv =
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5368 ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;

  // rule RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt =
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6760 ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;

  // rule RL_coreFix_fpuMulDivExe_0_doFinishIntMul
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul =
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8152 ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;

  // rule RL_coreFix_fpuMulDivExe_0_doFinishIntDiv
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv =
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned &&
	     !coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned &&
	     rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_data &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$EMPTY_N ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     !WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;

  // rule RL_coreFix_memExe_doDeqLdQ_fault
  assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault =
	     rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd &&
	     coreFix_memExe_lsq$RDY_deqLd &&
	     coreFix_memExe_lsq$firstLd[7] ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault =
	     CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_coreFix_memExe_doDeqLdQ_Ld_Mem
  assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem =
	     rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstLd &&
	     coreFix_memExe_lsq$RDY_deqLd &&
	     !coreFix_memExe_lsq$firstLd[7] &&
	     !coreFix_memExe_lsq$firstLd[101] &&
	     !coreFix_memExe_lsq$firstLd[16] ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem =
	     CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ;

  // rule RL_coreFix_memExe_doDeqLdQ_Lr_deq
  assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq =
	     !coreFix_memExe_respLrScAmoQ_empty &&
	     rob$RDY_setExecuted_deqLSQ &&
	     coreFix_memExe_lsq$RDY_firstLd &&
	     coreFix_memExe_lsq$RDY_deqLd &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq =
	     CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_coreFix_memExe_doDeqLdQ_MMIO_deq
  assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq =
	     !mmio_dataRespQ_empty &&
	     NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1400 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[0] &&
	     mmio_dataRespQ_data_0[64] ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq =
	     CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_coreFix_memExe_doDeqLdQ_MMIO_fault
  assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault =
	     !mmio_dataRespQ_empty &&
	     NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1400 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[0] &&
	     !mmio_dataRespQ_data_0[64] ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault =
	     CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_coreFix_memExe_doFinishMem
  assign CAN_FIRE_RL_coreFix_memExe_doFinishMem =
	     rob$RDY_setExecuted_doFinishMem &&
	     coreFix_memExe_dTlb$RDY_procResp &&
	     coreFix_memExe_dTlb$RDY_deqProcResp ;
  assign WILL_FIRE_RL_coreFix_memExe_doFinishMem =
	     CAN_FIRE_RL_coreFix_memExe_doFinishMem ;

  // rule RL_coreFix_memExe_doDeqStQ_ScAmo_issue
  assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue =
	     NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1026 &&
	     coreFix_memExe_lsq$RDY_firstSt &&
	     !coreFix_memExe_lsq$firstSt[4] &&
	     !coreFix_memExe_lsq$firstSt[77] &&
	     (coreFix_memExe_lsq$firstSt[158:157] == 2'd1 ||
	      coreFix_memExe_lsq$firstSt[158:157] == 2'd2) &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
	     coreFix_memExe_stb$noMatchStQ &&
	     (!coreFix_memExe_lsq$firstSt[151] ||
	      coreFix_memExe_stb$isEmpty) ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue =
	     CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;

  // rule RL_coreFix_memExe_doDeqStQ_MMIO_issue
  assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue =
	     !mmio_dataReqQ_full && !mmio_dataPendQ_full &&
	     coreFix_memExe_lsq$RDY_firstSt &&
	     !coreFix_memExe_lsq$firstSt[4] &&
	     coreFix_memExe_lsq$firstSt[158:157] != 2'd3 &&
	     coreFix_memExe_lsq$firstSt[77] &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
	     (!coreFix_memExe_lsq$firstSt[151] ||
	      coreFix_memExe_stb$isEmpty) ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue =
	     CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;

  // rule RL_mmio_dataReqQ_canonicalize
  assign CAN_FIRE_RL_mmio_dataReqQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataReqQ_canonicalize = 1'd1 ;

  // rule RL_mmio_dataReqQ_enqReq_canon
  assign CAN_FIRE_RL_mmio_dataReqQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataReqQ_enqReq_canon = 1'd1 ;

  // rule RL_mmio_dataReqQ_deqReq_canon
  assign CAN_FIRE_RL_mmio_dataReqQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataReqQ_deqReq_canon = 1'd1 ;

  // rule RL_mmio_dataReqQ_clearReq_canon
  assign CAN_FIRE_RL_mmio_dataReqQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataReqQ_clearReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_sendLrScAmoToMem
  assign CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1141 &&
	     (!coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT ||
	      !coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT ||
	      coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ||
	      !coreFix_memExe_reqLrScAmoQ_empty_rl) ;
  assign WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem =
	     CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;

  // rule RL_coreFix_memExe_doIssueLdFromIssueQ
  assign CAN_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ =
	     coreFix_memExe_lsq$RDY_getIssueLd &&
	     !coreFix_memExe_forwardQ_full &&
	     NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1486 ;
  assign WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ =
	     CAN_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;

  // rule RL_coreFix_memExe_doIssueLdFromUpdate
  assign CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate =
	     !coreFix_memExe_forwardQ_full &&
	     NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1486 &&
	     coreFix_memExe_issueLd$whas ;
  assign WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate =
	     CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;

  // rule RL_coreFix_memExe_doDeqStQ_fault
  assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault =
	     rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt &&
	     coreFix_memExe_lsq$RDY_deqSt &&
	     coreFix_memExe_lsq$firstSt[4] ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault =
	     CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_coreFix_memExe_doDeqStQ_Fence
  assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence =
	     rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_firstSt &&
	     coreFix_memExe_lsq$RDY_deqSt &&
	     !coreFix_memExe_lsq$firstSt[4] &&
	     coreFix_memExe_lsq$firstSt[158:157] == 2'd3 &&
	     (!coreFix_memExe_lsq$firstSt[151] ||
	      coreFix_memExe_stb$isEmpty) ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence =
	     CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_coreFix_memExe_doDeqStQ_ScAmo_deq
  assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq =
	     !coreFix_memExe_respLrScAmoQ_empty &&
	     rob$RDY_setExecuted_deqLSQ &&
	     coreFix_memExe_lsq$RDY_firstSt &&
	     coreFix_memExe_lsq$RDY_deqSt &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd2 ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq =
	     CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     !WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_coreFix_memExe_doDeqStQ_MMIO_deq
  assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq =
	     !mmio_dataRespQ_empty &&
	     NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1099 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
	     !coreFix_memExe_waitLrScAmoMMIOResp[0] &&
	     mmio_dataRespQ_data_0[64] ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq =
	     CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     !WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_coreFix_memExe_doDeqStQ_MMIO_fault
  assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault =
	     !mmio_dataRespQ_empty &&
	     NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1099 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
	     coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
	     !coreFix_memExe_waitLrScAmoMMIOResp[0] &&
	     !mmio_dataRespQ_data_0[64] ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault =
	     CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;

  // rule RL_mmio_dataRespQ_canonicalize
  assign CAN_FIRE_RL_mmio_dataRespQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataRespQ_canonicalize = 1'd1 ;

  // rule RL_mmio_dataRespQ_enqReq_canon
  assign CAN_FIRE_RL_mmio_dataRespQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataRespQ_enqReq_canon = 1'd1 ;

  // rule RL_mmio_dataRespQ_deqReq_canon
  assign CAN_FIRE_RL_mmio_dataRespQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataRespQ_deqReq_canon = 1'd1 ;

  // rule RL_mmio_dataRespQ_clearReq_canon
  assign CAN_FIRE_RL_mmio_dataRespQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataRespQ_clearReq_canon = 1'd1 ;

  // rule RL_mmio_dataPendQ_canonicalize
  assign CAN_FIRE_RL_mmio_dataPendQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataPendQ_canonicalize = 1'd1 ;

  // rule RL_mmio_dataPendQ_enqReq_canon
  assign CAN_FIRE_RL_mmio_dataPendQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataPendQ_enqReq_canon = 1'd1 ;

  // rule RL_mmio_dataPendQ_deqReq_canon
  assign CAN_FIRE_RL_mmio_dataPendQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataPendQ_deqReq_canon = 1'd1 ;

  // rule RL_mmio_dataPendQ_clearReq_canon
  assign CAN_FIRE_RL_mmio_dataPendQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_dataPendQ_clearReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_sendLdToMem
  assign CAN_FIRE_RL_coreFix_memExe_sendLdToMem =
	     (!coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT ||
	      !coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT ||
	      coreFix_memExe_reqLdQ_empty_lat_0$whas ||
	      !coreFix_memExe_reqLdQ_empty_rl) &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1141 ;
  assign WILL_FIRE_RL_coreFix_memExe_sendLdToMem =
	     CAN_FIRE_RL_coreFix_memExe_sendLdToMem &&
	     !WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;

  // rule RL_coreFix_memExe_sendStToMem
  assign CAN_FIRE_RL_coreFix_memExe_sendStToMem =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1141 &&
	     (!coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT ||
	      !coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT ||
	      CAN_FIRE_RL_coreFix_memExe_doIssueSB ||
	      !coreFix_memExe_reqStQ_empty_rl) ;
  assign WILL_FIRE_RL_coreFix_memExe_sendStToMem =
	     CAN_FIRE_RL_coreFix_memExe_sendStToMem &&
	     !WILL_FIRE_RL_coreFix_memExe_sendLdToMem &&
	     !WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2136 &&
	     !coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] ==
	     2'd0 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2747 &&
	     !coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] !=
	     2'd0 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] !=
	     2'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;

  // rule RL_coreFix_memExe_doDeqStQ_St_Mem
  assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem =
	     coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_firstSt &&
	     coreFix_memExe_lsq$RDY_deqSt &&
	     !coreFix_memExe_lsq$firstSt[4] &&
	     coreFix_memExe_lsq$firstSt[158:157] == 2'd0 &&
	     !coreFix_memExe_lsq$firstSt[77] &&
	     coreFix_memExe_stb$getEnqIndex[2] ;
  assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem =
	     CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_memExe_doRespLdMem
  assign CAN_FIRE_RL_coreFix_memExe_doRespLdMem =
	     !coreFix_memExe_memRespLdQ_empty ;
  assign WILL_FIRE_RL_coreFix_memExe_doRespLdMem =
	     CAN_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;

  // rule RL_coreFix_memExe_doRespLdForward
  assign CAN_FIRE_RL_coreFix_memExe_doRespLdForward =
	     !coreFix_memExe_forwardQ_empty ;
  assign WILL_FIRE_RL_coreFix_memExe_doRespLdForward =
	     CAN_FIRE_RL_coreFix_memExe_doRespLdForward &&
	     !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     !WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;

  // rule RL_coreFix_memExe_doExeMem
  assign CAN_FIRE_RL_coreFix_memExe_doExeMem =
	     coreFix_memExe_regToExeQ$RDY_deq &&
	     coreFix_memExe_regToExeQ$RDY_first &&
	     coreFix_memExe_dTlb$RDY_procReq ;
  assign WILL_FIRE_RL_coreFix_memExe_doExeMem =
	     CAN_FIRE_RL_coreFix_memExe_doExeMem ;

  // rule RL_prepareCachesAndTlbs
  assign CAN_FIRE_RL_prepareCachesAndTlbs =
	     (!flush_tlbs ||
	      fetchStage$RDY_iTlbIfc_flush &&
	      coreFix_memExe_dTlb$RDY_flush) &&
	     (flush_reservation || flush_tlbs || update_vm_info) ;
  assign WILL_FIRE_RL_prepareCachesAndTlbs =
	     CAN_FIRE_RL_prepareCachesAndTlbs ;

  // rule RL_coreFix_memExe_doRegReadMem
  assign CAN_FIRE_RL_coreFix_memExe_doRegReadMem =
	     coreFix_memExe_dispToRegQ$RDY_deq &&
	     coreFix_memExe_regToExeQ_RDY_enq__563_AND_core_ETC___d1653 ;
  assign WILL_FIRE_RL_coreFix_memExe_doRegReadMem =
	     CAN_FIRE_RL_coreFix_memExe_doRegReadMem &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_memExe_doDispatchMem
  assign CAN_FIRE_RL_coreFix_memExe_doDispatchMem =
	     coreFix_memExe_dispToRegQ$RDY_enq &&
	     coreFix_memExe_rsMem$RDY_dispatchData &&
	     coreFix_memExe_rsMem$RDY_doDispatch ;
  assign WILL_FIRE_RL_coreFix_memExe_doDispatchMem =
	     CAN_FIRE_RL_coreFix_memExe_doDispatchMem &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer =
	     !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send &&
	     coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit &&
	     CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry =
	     !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new =
	     (!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT ||
	      !coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT ||
	      coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ||
	      !coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl) &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_cRqTransfer_getEmptyEntryInit &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer &&
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer =
	     !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send &&
	     CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_respLrScAmoQ_canonicalize
  assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon
  assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon =
	     1'd1 ;

  // rule RL_coreFix_memExe_respLrScAmoQ_clearReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_respLrScAmoQ_deqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_respLrScAmoQ_enqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_memRespLdQ_canonicalize
  assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ;

  // rule RL_coreFix_memExe_memRespLdQ_clearReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_memRespLdQ_deqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_memRespLdQ_enqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_forwardQ_canonicalize
  assign CAN_FIRE_RL_coreFix_memExe_forwardQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_forwardQ_canonicalize = 1'd1 ;

  // rule RL_coreFix_memExe_forwardQ_clearReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_forwardQ_deqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_forwardQ_enqReq_canon
  assign CAN_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon = 1'd1 ;

  // rule RL_coreFix_memExe_reqStQ_full_canon
  assign CAN_FIRE_RL_coreFix_memExe_reqStQ_full_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_reqStQ_full_canon = 1'd1 ;

  // rule RL_coreFix_memExe_reqStQ_empty_canon
  assign CAN_FIRE_RL_coreFix_memExe_reqStQ_empty_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_reqStQ_empty_canon = 1'd1 ;

  // rule RL_coreFix_memExe_reqStQ_data_0_canon
  assign CAN_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon = 1'd1 ;

  // rule RL_coreFix_memExe_reqLrScAmoQ_full_canon
  assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon = 1'd1 ;

  // rule RL_coreFix_memExe_reqLrScAmoQ_empty_canon
  assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ;

  // rule RL_coreFix_memExe_reqLrScAmoQ_data_0_canon
  assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ;

  // rule RL_coreFix_memExe_reqLdQ_full_canon
  assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_full_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_full_canon = 1'd1 ;

  // rule RL_coreFix_memExe_reqLdQ_empty_canon
  assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ;

  // rule RL_coreFix_memExe_reqLdQ_data_0_canon
  assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon = 1'd1 ;

  // rule RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv =
	     coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_regToExeQ$RDY_first &&
	     IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8541 ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv =
	     coreFix_fpuMulDivExe_0_dispToRegQ$RDY_deq &&
	     coreFix_fpuMulDivExe_0_regToExeQ$RDY_enq &&
	     coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first__2_ETC___d8395 ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv =
	     coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq &&
	     coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData &&
	     coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv &&
	     !WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	     !WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit =
	     !coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit ;

  // rule RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_rl_ready
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_rl_ready =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_rl_ready =
	     1'd1 ;

  // rule RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon = 1'd1 ;

  // rule RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_canon
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_canon =
	     1'd1 ;

  // rule RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_canon
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_canon =
	     1'd1 ;

  // rule RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_canon
  assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_canon =
	     1'd1 ;
  assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_canon =
	     1'd1 ;

  // rule RL_renameStage_doRenaming_Trap
  assign CAN_FIRE_RL_renameStage_doRenaming_Trap =
	     fetchStage$RDY_pipelines_0_deq &&
	     fetchStage$RDY_pipelines_0_first &&
	     epochManager$RDY_incrementEpoch &&
	     rob$RDY_enqPort_0_enq &&
	     mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13208 ;
  assign WILL_FIRE_RL_renameStage_doRenaming_Trap =
	     CAN_FIRE_RL_renameStage_doRenaming_Trap &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_renameStage_doRenaming_SystemInst
  assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst =
	     fetchStage$RDY_pipelines_0_deq &&
	     fetchStage_RDY_pipelines_0_first__2925_AND_epo_ETC___d13407 &&
	     mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13461 &&
	     rob$isEmpty ;
  assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst =
	     CAN_FIRE_RL_renameStage_doRenaming_SystemInst &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_csrInstOrInterruptInflight_canon
  assign CAN_FIRE_RL_csrInstOrInterruptInflight_canon = 1'd1 ;
  assign WILL_FIRE_RL_csrInstOrInterruptInflight_canon = 1'd1 ;

  // rule RL_commitStage_doSetLSQAtCommit
  assign CAN_FIRE_RL_commitStage_doSetLSQAtCommit =
	     MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 ||
	     WILL_FIRE_RL_commitStage_notifyLSQCommit ;
  assign WILL_FIRE_RL_commitStage_doSetLSQAtCommit =
	     CAN_FIRE_RL_commitStage_doSetLSQAtCommit ;

  // rule RL_commitStage_doSetLSQAtCommit_1
  assign CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 =
	     WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	     rob$deqPort_1_canDeq &&
	     rob$deqPort_1_deq_data[25] &&
	     !rob$deqPort_1_deq_data[18] &&
	     !rob$deqPort_1_deq_data[167] &&
	     rob$deqPort_1_deq_data[257:253] != 5'd0 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd21 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd17 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd18 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd13 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd16 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd15 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd19 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd20 &&
	     rob$deqPort_1_deq_data[13] ;
  assign WILL_FIRE_RL_commitStage_doSetLSQAtCommit_1 =
	     CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 ;

  // rule RL_renameStage_doRenaming
  assign CAN_FIRE_RL_renameStage_doRenaming =
	     (!fetchStage$pipelines_0_canDeq ||
	      IF_fetchStage_RDY_pipelines_0_first__2925_AND__ETC___d13555) &&
	     IF_NOT_fetchStage_pipelines_0_canDeq__2926_292_ETC___d14005 &&
	     IF_NOT_fetchStage_pipelines_0_canDeq__2926_292_ETC___d14013 &&
	     NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14177 &&
	     mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14180 ;
  assign WILL_FIRE_RL_renameStage_doRenaming =
	     CAN_FIRE_RL_renameStage_doRenaming &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;

  // rule RL_mmio_pRqQ_canonicalize
  assign CAN_FIRE_RL_mmio_pRqQ_canonicalize = 1'd1 ;
  assign WILL_FIRE_RL_mmio_pRqQ_canonicalize = 1'd1 ;

  // rule RL_mmio_pRqQ_enqReq_canon
  assign CAN_FIRE_RL_mmio_pRqQ_enqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_pRqQ_enqReq_canon = 1'd1 ;

  // rule RL_mmio_pRqQ_deqReq_canon
  assign CAN_FIRE_RL_mmio_pRqQ_deqReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_pRqQ_deqReq_canon = 1'd1 ;

  // rule RL_mmio_pRqQ_clearReq_canon
  assign CAN_FIRE_RL_mmio_pRqQ_clearReq_canon = 1'd1 ;
  assign WILL_FIRE_RL_mmio_pRqQ_clearReq_canon = 1'd1 ;

  // rule RL_coreFix_globalSpecUpdate_canon_correct_spec
  assign CAN_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec = 1'd1 ;
  assign WILL_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec = 1'd1 ;

  // inputs to muxes for submodule ports
  assign MUX_commitStage_rg_serial_num$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle ;
  assign MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	     rob$deqPort_0_canDeq &&
	     rob$deqPort_0_deq_data[13] ;
  assign MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3 =
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 =
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	     fetchStage$pipelines_0_first[194:192] == 3'd0 ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
	     coreFix_memExe_lsq$firstSt[150] ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 =
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
	     coreFix_memExe_lsq$firstLd[89] ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2650 ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 &&
	     coreFix_memExe_lsq$getHit[8] &&
	     !coreFix_memExe_lsq$getHit[9] ;
  assign MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
	     coreFix_memExe_lsq$firstSt[150] ;
  assign MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
	     coreFix_memExe_lsq$firstLd[89] ;
  assign MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
	     coreFix_memExe_lsq$firstSt[150] ;
  assign MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
	     coreFix_memExe_lsq$firstLd[89] ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2627 ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	     3'd4 ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2559 ||
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2563) ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2610 ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd2 ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd3) ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2821 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] ==
	     2'd0 ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	      (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	       3'd4 ||
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 &&
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055 ||
	       !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045) ||
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2151) ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	      (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	       !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd4 ||
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2666) ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd4 ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2771 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2774 ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2730 ;
  assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ;
  assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2 =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ;
  assign MUX_coreFix_memExe_lsq$getHit_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	      (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	       !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd0 ||
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2633) ;
  assign MUX_coreFix_memExe_lsq$getHit_1__SEL_2 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 ;
  assign MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	      (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	       !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd1 ||
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2658) ;
  assign MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
	     coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
  assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2593 ;
  assign MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
	     coreFix_memExe_lsq$firstSt[150] ;
  assign MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
	     coreFix_memExe_lsq$firstLd[89] ;
  assign MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
  assign MUX_coreFix_trainBPQ_0$enq_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
	     (coreFix_aluExe_0_exeToFinQ$first[326:322] == 5'd9 ||
	      coreFix_aluExe_0_exeToFinQ$first[326:322] == 5'd10) ;
  assign MUX_coreFix_trainBPQ_1$enq_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
	     (coreFix_aluExe_1_exeToFinQ$first[326:322] == 5'd9 ||
	      coreFix_aluExe_1_exeToFinQ$first[326:322] == 5'd10) ;
  assign MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 ;
  assign MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     commitStage_commitTrap[36] ;
  assign MUX_csrInstOrInterruptInflight_dummy2_1$write_1__SEL_2 =
	     WILL_FIRE_RL_renameStage_doRenaming_Trap &&
	     !fetchStage$pipelines_0_first[68] &&
	     (IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] ||
	      IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[1] ||
	      IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[2] ||
	      IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[3] ||
	      IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[4] ||
	      IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[5] ||
	      IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[6] ||
	      IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[7] ||
	      IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[8] ||
	      IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[9] ||
	      IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[10] ||
	      IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[11]) ;
  assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd16 ||
	      IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd29) ;
  assign MUX_csrf_fflags_reg$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd0 ||
	      IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd2) ;
  assign MUX_csrf_fs_reg$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd0 ||
	      IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd1 ||
	      IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd2 ||
	      IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd8 ||
	      IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd18) ;
  assign MUX_csrf_ie_vec_1$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 ;
  assign MUX_csrf_ie_vec_3$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 ;
  assign MUX_csrf_prv_reg$write_1__SEL_1 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     (rob$deqPort_0_deq_data[257:253] == 5'd19 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd20) ;
  assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 =
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     fetchStage$pipelines_0_canDeq &&
	     NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183 &&
	     IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 ;
  assign MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 =
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 &&
	     NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14319 &&
	     IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13999 ;
  assign MUX_flush_reservation$write_1__SEL_1 =
	     WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ;
  assign MUX_flush_tlbs$write_1__SEL_1 =
	     WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ;
  assign MUX_rf$write_3_wr_1__PSEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
	     WILL_FIRE_RL_coreFix_memExe_doRespLdMem ;
  assign MUX_rf$write_3_wr_1__SEL_1 =
	     MUX_rf$write_3_wr_1__PSEL_1 && coreFix_memExe_lsq$respLd[72] ;
  assign MUX_rf$write_3_wr_1__SEL_2 =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
	     coreFix_memExe_lsq$firstSt[150] ;
  assign MUX_rf$write_3_wr_1__SEL_3 =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
	     coreFix_memExe_lsq$firstSt[150] ;
  assign MUX_rf$write_3_wr_1__SEL_4 =
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	     coreFix_memExe_lsq$firstLd[89] ;
  assign MUX_rf$write_3_wr_1__SEL_5 =
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     coreFix_memExe_lsq$firstLd[89] ;
  assign MUX_rf$write_3_wr_2__SEL_1 =
	     MUX_rf$write_3_wr_1__PSEL_1 && coreFix_memExe_lsq$respLd[72] ;
  assign MUX_rob$setExecuted_deqLSQ_1__SEL_1 =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ;
  assign MUX_sbAggr$setReady_4_put_1__SEL_1 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
	     coreFix_memExe_lsq$firstSt[150] ;
  assign MUX_sbAggr$setReady_4_put_1__SEL_2 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
	     coreFix_memExe_lsq$firstLd[89] ;
  assign MUX_sbCons$setReady_3_put_1__SEL_1 =
	     MUX_rf$write_3_wr_1__PSEL_1 && coreFix_memExe_lsq$respLd[72] ;
  assign MUX_sbCons$setReady_3_put_1__SEL_2 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
	     coreFix_memExe_lsq$firstSt[150] ;
  assign MUX_sbCons$setReady_3_put_1__SEL_3 =
	     MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
	     coreFix_memExe_lsq$firstLd[89] ;
  assign MUX_update_vm_info$write_1__SEL_1 =
	     WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ;
  assign MUX_commitStage_commitTrap$write_1__VAL_2 =
	     { 1'd1,
	       rob$deqPort_0_deq_data[353:290],
	       x__h705027,
	       rob$deqPort_0_deq_data[166],
	       rob$deqPort_0_deq_data[166] ?
		 CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q260 :
		 CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q261,
	       rob$deqPort_0_deq_data[289:258] } ;
  assign MUX_commitStage_rg_serial_num$write_1__VAL_1 =
	     commitStage_rg_serial_num + 64'd1 ;
  assign MUX_commitStage_rg_serial_num$write_1__VAL_2 =
	     commitStage_rg_serial_num + y__h723410 ;
  assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 =
	     { fetchStage$pipelines_0_first[199:195],
	       IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043,
	       fetchStage$pipelines_0_first[173],
	       IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125,
	       fetchStage$pipelines_0_first[160:128],
	       fetchStage$pipelines_0_first[255:232],
	       regRenamingTable$rename_0_getRename,
	       rob$enqPort_0_getEnqInstTag,
	       specTagManager$currentSpecBits,
	       5'd10,
	       sbAggr$eagerLookup_0_get } ;
  assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 =
	     (k__h675032 == 1'd0 &&
	      fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14186) ?
	       { fetchStage$pipelines_0_first[199:195],
		 IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043,
		 fetchStage$pipelines_0_first[173],
		 IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125,
		 fetchStage$pipelines_0_first[160:128],
		 fetchStage$pipelines_0_first[255:232],
		 regRenamingTable$rename_0_getRename,
		 rob$enqPort_0_getEnqInstTag,
		 specTagManager$currentSpecBits,
		 fetchStage$pipelines_0_first[194:192] == 3'd1,
		 specTagManager$nextSpecTag,
		 sbAggr$eagerLookup_0_get } :
	       { fetchStage$pipelines_1_first[199:195],
		 IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13701,
		 fetchStage_pipelines_1_first__2937_BIT_173_370_ETC___d13785,
		 fetchStage$pipelines_1_first[160:128],
		 fetchStage$pipelines_1_first[255:232],
		 regRenamingTable$rename_1_getRename,
		 rob$enqPort_1_getEnqInstTag,
		 renaming_spec_bits__h690496,
		 fetchStage$pipelines_1_first[194:192] == 3'd1,
		 specTagManager$nextSpecTag,
		 sbAggr$eagerLookup_1_get } ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 =
	     { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25] } ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 =
	     { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25] } ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 =
	     { 1'd1, coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25] } ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 =
	     { 1'd1,
	       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25] } ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 =
	     { 1'd1,
	       coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25] } ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6 =
	     { 1'd1,
	       coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25] } ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 =
	     { 1'd1, coreFix_memExe_lsq$firstSt[149:143] } ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 =
	     { 1'd1, coreFix_memExe_lsq$firstLd[88:82] } ;
  assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 =
	     { 1'd1, coreFix_memExe_lsq$getHit[7:1] } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
	       (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 ?
		  3'd3 :
		  3'd5) :
	       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567 ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
	       (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 ?
		  { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
		    coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
		    53'h15555555555555 } :
		  58'h155555555555554) :
	       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2578 ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2 =
	     { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
	       55'h15555555555555 } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
	       { (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
		  !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
		 3'd2,
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } :
	       { coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 &&
		 (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
		  !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
		 3'd2,
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2 =
	     { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	       3'd2,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
	       { coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
		 (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
		  !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3],
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } :
	       { (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
		  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
		  3'd1) &&
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 &&
		 (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
		  !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3],
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
	       (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 ?
		  IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2538 :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:0]) :
	       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2551 ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2 =
	     { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
	       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2172,
	       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2528 } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3 =
	     { coreFix_memExe_dMem_cache_m_banks_0_processAmo[151:100],
	       2'd3,
	       coreFix_memExe_dMem_cache_m_banks_0_processAmo[3:0],
	       IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2033,
	       (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
		3'd0) ?
		 n__h196842 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 =
	     { IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2787,
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	       (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
		!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) :
	       NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2554 ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 =
	     { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84],
	       x__h290393 } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 =
	     { 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
	       x__h291838,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 =
	     { 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
	       SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2968,
	       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 =
	     { 2'd2,
	       addr__h294614,
	       SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3038 } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 =
	     { 1'd1,
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2 =
	     { 1'd1,
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 =
	     { x__h155092, x__h155098, 84'h82AAAAAAAAAAAAAAAAAAA } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 =
	     { x__h158639, x__h158645, 84'hCAAAAAAAAAAAAAAAAAAAA } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 =
	     { x__h161455,
	       x__h161459,
	       IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1216,
	       IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1220,
	       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224,
	       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1228,
	       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1232,
	       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1237,
	       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1241,
	       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1246,
	       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1250,
	       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1255,
	       x__h163307,
	       IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1263,
	       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267,
	       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1271,
	       coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1275 } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 =
	     { 1'd1,
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2 =
	     { 1'd0,
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 =
	     { 1'd1,
	       resp_addr__h296629,
	       2'd0,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ;
  assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 =
	     { 1'd1,
	       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq,
	       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ;
  assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1 =
	     { 1'd1,
	       coreFix_memExe_lsq$getIssueLd[76:72],
	       coreFix_memExe_lsq$issueLd[63:0] } ;
  assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2 =
	     { 1'd1,
	       coreFix_memExe_issueLd$wget[76:72],
	       coreFix_memExe_lsq$issueLd[63:0] } ;
  assign MUX_coreFix_memExe_lsq$getHit_1__VAL_1 =
	     { 1'd0,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148] } ;
  assign MUX_coreFix_memExe_lsq$issueLd_4__VAL_1 =
	     { coreFix_memExe_stb$search[67],
	       coreFix_memExe_stb$search[67] ?
		 coreFix_memExe_stb$search[66:65] :
		 2'h2,
	       coreFix_memExe_stb$search[64],
	       coreFix_memExe_stb$search[64] ?
		 coreFix_memExe_stb$search[63:0] :
		 64'hAAAAAAAAAAAAAAAA } ;
  always@(coreFix_memExe_memRespLdQ_deqP or
	  coreFix_memExe_memRespLdQ_data_0 or
	  coreFix_memExe_memRespLdQ_data_1)
  begin
    case (coreFix_memExe_memRespLdQ_deqP)
      1'd0:
	  MUX_coreFix_memExe_lsq$respLd_1__VAL_1 =
	      coreFix_memExe_memRespLdQ_data_0[68:64];
      1'd1:
	  MUX_coreFix_memExe_lsq$respLd_1__VAL_1 =
	      coreFix_memExe_memRespLdQ_data_1[68:64];
    endcase
  end
  always@(coreFix_memExe_forwardQ_deqP or
	  coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1)
  begin
    case (coreFix_memExe_forwardQ_deqP)
      1'd0:
	  MUX_coreFix_memExe_lsq$respLd_1__VAL_2 =
	      coreFix_memExe_forwardQ_data_0[68:64];
      1'd1:
	  MUX_coreFix_memExe_lsq$respLd_1__VAL_2 =
	      coreFix_memExe_forwardQ_data_1[68:64];
    endcase
  end
  always@(coreFix_memExe_memRespLdQ_deqP or
	  coreFix_memExe_memRespLdQ_data_0 or
	  coreFix_memExe_memRespLdQ_data_1)
  begin
    case (coreFix_memExe_memRespLdQ_deqP)
      1'd0:
	  MUX_coreFix_memExe_lsq$respLd_2__VAL_1 =
	      coreFix_memExe_memRespLdQ_data_0[63:0];
      1'd1:
	  MUX_coreFix_memExe_lsq$respLd_2__VAL_1 =
	      coreFix_memExe_memRespLdQ_data_1[63:0];
    endcase
  end
  always@(coreFix_memExe_forwardQ_deqP or
	  coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1)
  begin
    case (coreFix_memExe_forwardQ_deqP)
      1'd0:
	  MUX_coreFix_memExe_lsq$respLd_2__VAL_2 =
	      coreFix_memExe_forwardQ_data_0[63:0];
      1'd1:
	  MUX_coreFix_memExe_lsq$respLd_2__VAL_2 =
	      coreFix_memExe_forwardQ_data_1[63:0];
    endcase
  end
  assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 =
	     { 1'd1,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148],
	       x__h200347 } ;
  assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 =
	     { 5'd0,
	       coreFix_memExe_lsq$firstSt[141:78],
	       2'd3,
	       (coreFix_memExe_lsq$firstSt[158:157] == 2'd1) ? 3'd3 : 3'd4,
	       coreFix_memExe_lsq$firstSt[76:5],
	       coreFix_memExe_lsq$firstSt[156:153],
	       coreFix_memExe_lsq$firstSt[69] &&
	       coreFix_memExe_lsq$firstSt[70] &&
	       coreFix_memExe_lsq$firstSt[71] &&
	       coreFix_memExe_lsq$firstSt[72] &&
	       coreFix_memExe_lsq$firstSt[73] &&
	       coreFix_memExe_lsq$firstSt[74] &&
	       coreFix_memExe_lsq$firstSt[75] &&
	       coreFix_memExe_lsq$firstSt[76],
	       coreFix_memExe_lsq$firstSt[152:151] } ;
  assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_2 =
	     { 5'd0,
	       coreFix_memExe_lsq$firstLd[80:17],
	       84'h92AAAAAAAAAAAAAAAAAAA } ;
  assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
	       ((!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
		 !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) ?
		  { 1'd1,
		    IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2595 } :
		  65'h10000000000000001) :
	       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2598 ;
  assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2 =
	     { 1'd1,
	       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2595 } ;
  assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 =
	     { 1'd1,
	       coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ?
		 curData__h195304 :
		 { {32{x__h196067[31]}}, x__h196067 } } ;
  assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 =
	     { coreFix_aluExe_0_exeToFinQ$first[146:19],
	       coreFix_aluExe_0_exeToFinQ$first[326:322],
	       coreFix_aluExe_0_exeToFinQ$first[18],
	       coreFix_aluExe_0_exeToFinQ$first[300:277],
	       1'd0,
	       coreFix_aluExe_0_exeToFinQ$first[276] } ;
  assign MUX_coreFix_trainBPQ_0$enq_1__VAL_2 =
	     { coreFix_aluExe_0_exeToFinQ$first[146:19],
	       coreFix_aluExe_0_exeToFinQ$first[326:322],
	       coreFix_aluExe_0_exeToFinQ$first[18],
	       coreFix_aluExe_0_exeToFinQ$first[300:277],
	       1'd1,
	       coreFix_aluExe_0_exeToFinQ$first[276] } ;
  assign MUX_coreFix_trainBPQ_1$enq_1__VAL_1 =
	     { coreFix_aluExe_1_exeToFinQ$first[146:19],
	       coreFix_aluExe_1_exeToFinQ$first[326:322],
	       coreFix_aluExe_1_exeToFinQ$first[18],
	       coreFix_aluExe_1_exeToFinQ$first[300:277],
	       1'd0,
	       coreFix_aluExe_1_exeToFinQ$first[276] } ;
  assign MUX_coreFix_trainBPQ_1$enq_1__VAL_2 =
	     { coreFix_aluExe_1_exeToFinQ$first[146:19],
	       coreFix_aluExe_1_exeToFinQ$first[326:322],
	       coreFix_aluExe_1_exeToFinQ$first[18],
	       coreFix_aluExe_1_exeToFinQ$first[300:277],
	       1'd1,
	       coreFix_aluExe_1_exeToFinQ$first[276] } ;
  assign MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1 =
	     MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 ||
	     MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ;
  assign MUX_csrf_fflags_reg$write_1__VAL_2 =
	     csrf_fflags_reg | fflags__h723387 ;
  always@(IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 or
	  robdeqPort_0_deq_data_BITS_95_TO_32__q262)
  begin
    case (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778)
      6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_1 = 2'b11;
      default: MUX_csrf_fs_reg$write_1__VAL_1 =
		   robdeqPort_0_deq_data_BITS_95_TO_32__q262[14:13];
    endcase
  end
  assign MUX_csrf_ie_vec_1$write_1__VAL_2 =
	     (rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	      (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	       6'd8 ||
	       IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	       6'd18)) ?
	       robdeqPort_0_deq_data_BITS_95_TO_32__q262[1] :
	       csrf_prev_ie_vec_1 ;
  assign MUX_csrf_ie_vec_3$write_1__VAL_2 =
	     (rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	      IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd18) ?
	       robdeqPort_0_deq_data_BITS_95_TO_32__q262[3] :
	       csrf_prev_ie_vec_3 ;
  assign MUX_csrf_mepc_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ;
  assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 =
	     n__read__h720316 + 64'd1 ;
  assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 =
	     n__read__h720316 + { 62'd0, x__h723635 } ;
  assign MUX_csrf_mpp_reg$write_1__VAL_2 =
	     (rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	      IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd18) ?
	       MUX_csrf_mepc_csr$write_1__VAL_2[12:11] :
	       2'd0 ;
  assign MUX_csrf_mtval_csr$write_1__VAL_1 =
	     commitStage_commitTrap[36] ? 64'd0 : trap_val__h709721 ;
  assign MUX_csrf_mtval_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ;
  assign MUX_csrf_prev_ie_vec_1$write_1__VAL_2 =
	     rob$deqPort_0_deq_data[257:253] != 5'd13 ||
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 !=
	     6'd8 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 !=
	     6'd18 ||
	     MUX_csrf_mtval_csr$write_1__VAL_2[5] ;
  assign MUX_csrf_prev_ie_vec_3$write_1__VAL_2 =
	     rob$deqPort_0_deq_data[257:253] != 5'd13 ||
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 !=
	     6'd18 ||
	     MUX_csrf_mtval_csr$write_1__VAL_2[7] ;
  assign MUX_csrf_prv_reg$write_1__VAL_1 =
	     (rob$deqPort_0_deq_data[257:253] == 5'd19) ?
	       x__h719695 :
	       csrf_mpp_reg ;
  assign MUX_csrf_prv_reg$write_1__VAL_2 =
	     csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 ?
	       2'd1 :
	       2'd3 ;
  assign MUX_csrf_sepc_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ;
  assign MUX_csrf_spp_reg$write_1__VAL_2 =
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd8 ||
	      IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd18) &&
	     MUX_csrf_sepc_csr$write_1__VAL_2[8] ;
  assign MUX_fetchStage$redirect_1__VAL_4 =
	     csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 ?
	       y_avValue_new_pc__h711402 :
	       y_avValue_new_pc__h711588 ;
  always@(rob$deqPort_0_deq_data or
	  next_pc__h719526 or csrf_sepc_csr or csrf_mepc_csr)
  begin
    case (rob$deqPort_0_deq_data[257:253])
      5'd19: MUX_fetchStage$redirect_1__VAL_5 = csrf_sepc_csr;
      5'd20: MUX_fetchStage$redirect_1__VAL_5 = csrf_mepc_csr;
      default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h719526;
    endcase
  end
  assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 =
	     { 1'd1,
	       coreFix_memExe_dTlb$toParent_rqToP_first[1:0],
	       coreFix_memExe_dTlb$toParent_rqToP_first[28:2] } ;
  assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2 =
	     { 3'd2, fetchStage$iTlbIfc_toParent_rqToP_first } ;
  assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 =
	     { 1'd1,
	       mmio_dataReqQ_data_0[141:78],
	       CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q263,
	       mmio_dataReqQ_data_0[71:0] } ;
  assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2 =
	     { 1'd1,
	       fetchStage$mmioIfc_instReq_first_fst,
	       5'd2,
	       fetchStage$mmioIfc_instReq_first_snd,
	       72'hAAAAAAAAAAAAAAAAAA } ;
  assign MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1 =
	     { 1'd1,
	       coreFix_memExe_lsq$firstSt[141:78],
	       (coreFix_memExe_lsq$firstSt[158:157] == 2'd0) ?
		 6'd42 :
		 { 2'd3, coreFix_memExe_lsq$firstSt[156:153] },
	       coreFix_memExe_lsq$firstSt[76:5] } ;
  assign MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_2 =
	     { 1'd1,
	       coreFix_memExe_lsq$firstLd[80:17],
	       6'd26,
	       coreFix_memExe_lsq$firstLd[15:0],
	       56'hAAAAAAAAAAAAAA } ;
  assign MUX_rf$write_2_wr_2__VAL_2 =
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ?
	       res_data__h342526 :
	       res_data__h342521 ;
  assign MUX_rf$write_2_wr_2__VAL_3 =
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ?
	       res_data__h388228 :
	       res_data__h388223 ;
  assign MUX_rf$write_2_wr_2__VAL_4 =
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ?
	       res_data__h433923 :
	       res_data__h433918 ;
  assign MUX_rf$write_2_wr_2__VAL_5 =
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ?
	       data___1__h479775 :
	       data__h479263 ;
  assign MUX_rf$write_2_wr_2__VAL_6 =
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ?
	       data___1__h480707 :
	       data__h480195 ;
  assign MUX_rf$write_3_wr_2__VAL_4 =
	     coreFix_memExe_lsq$firstLd[100] ?
	       coreFix_memExe_respLrScAmoQ_data_0 :
	       IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1386 ;
  assign MUX_rf$write_3_wr_2__VAL_5 =
	     coreFix_memExe_lsq$firstLd[100] ?
	       mmio_dataRespQ_data_0[63:0] :
	       IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1435 ;
  assign MUX_rob$enqPort_0_enq_1__VAL_1 =
	     { fetchStage$pipelines_0_first[387:324],
	       fetchStage$pipelines_0_first[127:96],
	       fetchStage$pipelines_0_first[199:195],
	       fetchStage$pipelines_0_first[75:69],
	       64'hAAAAAAAAAAAAAAAA,
	       fetchStage$pipelines_0_first[173],
	       IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125,
	       73'h1280000000000000000,
	       fetchStage$pipelines_0_first[323:260],
	       5'd0,
	       fetchStage$pipelines_0_first[75] &&
	       fetchStage$pipelines_0_first[74],
	       fetchStage$pipelines_0_first[194:192] != 3'd0 &&
	       fetchStage$pipelines_0_first[194:192] != 3'd1 &&
	       fetchStage$pipelines_0_first[194:192] != 3'd2 &&
	       fetchStage$pipelines_0_first[194:192] != 3'd3 &&
	       fetchStage$pipelines_0_first[194:192] != 3'd4,
	       NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14283 } ;
  assign MUX_rob$enqPort_0_enq_1__VAL_2 =
	     { fetchStage$pipelines_0_first[387:324],
	       fetchStage$pipelines_0_first[127:96],
	       fetchStage$pipelines_0_first[199:195],
	       fetchStage$pipelines_0_first[75:69],
	       64'hAAAAAAAAAAAAAAAA,
	       fetchStage$pipelines_0_first[173],
	       IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125,
	       2'd1,
	       !fetchStage$pipelines_0_first[68] &&
	       (IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] ||
		IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[1] ||
		IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[2] ||
		IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[3] ||
		IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[4] ||
		IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[5] ||
		IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[6] ||
		IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[7] ||
		IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[8] ||
		IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[9] ||
		IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[10] ||
		IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[11]),
	       IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13385,
	       fetchStage$pipelines_0_first[63:0],
	       2'd0,
	       fetchStage$pipelines_0_first[323:260],
	       20'd13601,
	       specTagManager$currentSpecBits } ;
  assign MUX_rob$enqPort_0_enq_1__VAL_3 =
	     { fetchStage$pipelines_0_first[387:324],
	       fetchStage$pipelines_0_first[127:96],
	       fetchStage$pipelines_0_first[199:195],
	       fetchStage$pipelines_0_first[75:69],
	       64'hAAAAAAAAAAAAAAAA,
	       fetchStage_pipelines_0_first__2928_BIT_173_304_ETC___d13522 } ;
  assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 =
	     { 1'd1,
	       CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264 } ;
  assign MUX_rob$setExecuted_deqLSQ_2__VAL_6 =
	     { 1'd1,
	       CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q265 } ;
  assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 =
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ?
	       coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] :
	       res_fflags__h342522 ;
  assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 =
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ?
	       coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] :
	       res_fflags__h388224 ;
  assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 =
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ?
	       coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] :
	       res_fflags__h433919 ;

  // inlined wires
  assign csrf_minstret_ehr_data_lat_0$whas =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd31 ;
  assign csrf_minstret_ehr_data_lat_1$whas =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst ||
	     WILL_FIRE_RL_commitStage_doCommitNormalInst ;
  assign csrf_minstret_ehr_data_dummy_1_0$whas =
	     WILL_FIRE_RL_commitStage_doCommitNormalInst ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst ;
  assign csrf_mcycle_ehr_data_lat_0$wget = rob$deqPort_0_deq_data[95:32] ;
  assign csrf_mcycle_ehr_data_lat_0$whas =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd30 ;
  assign csrInstOrInterruptInflight_lat_1$whas =
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	     fetchStage$pipelines_0_first[199:195] == 5'd13 ||
	     MUX_csrInstOrInterruptInflight_dummy2_1$write_1__SEL_2 ;
  assign mmio_dataReqQ_enqReq_lat_0$wget =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ?
	       MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1 :
	       MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_2 ;
  assign mmio_dataReqQ_enqReq_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ;
  assign mmio_dataRespQ_enqReq_lat_0$wget = { 1'd1, mmio_pRsQ_data_0[64:0] } ;
  assign mmio_dataRespQ_deqReq_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ;
  assign mmio_dataPendQ_enqReq_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ;
  assign mmio_cRqQ_enqReq_lat_0$wget =
	     WILL_FIRE_RL_mmio_sendDataReq ?
	       MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 :
	       MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2 ;
  assign mmio_cRqQ_enqReq_lat_0$whas =
	     WILL_FIRE_RL_mmio_sendDataReq || WILL_FIRE_RL_mmio_sendInstReq ;
  assign mmio_pRsQ_enqReq_lat_0$wget = { 1'd1, mmioToPlatform_pRs_enq_x } ;
  assign mmio_pRsQ_deqReq_lat_0$whas =
	     WILL_FIRE_RL_mmio_sendInstResp ||
	     WILL_FIRE_RL_mmio_sendDataResp ;
  assign mmio_pRqQ_enqReq_lat_0$wget =
	     { 1'd1,
	       mmioToPlatform_pRq_enq_x[38],
	       CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q266,
	       mmioToPlatform_pRq_enq_x[31:0] } ;
  assign mmio_cRsQ_enqReq_lat_0$wget =
	     { 1'd1, csrf_software_int_pend_vec_3 } ;
  assign coreFix_globalSpecUpdate_correctSpecTag_0$whas =
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
	     coreFix_aluExe_0_exeToFinQ$first[16] ;
  assign coreFix_globalSpecUpdate_correctSpecTag_1$whas =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
	     coreFix_aluExe_1_exeToFinQ$first[16] ;
  assign coreFix_aluExe_0_bypassWire_0$wget =
	     { coreFix_aluExe_0_regToExeQ$first[348:342],
	       basicExec___d12775[321:258] } ;
  assign coreFix_aluExe_0_bypassWire_0$whas =
	     WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
	     coreFix_aluExe_0_regToExeQ$first[349] ;
  assign coreFix_aluExe_0_bypassWire_1$wget =
	     { coreFix_aluExe_1_regToExeQ$first[348:342],
	       basicExec___d12101[321:258] } ;
  assign coreFix_aluExe_0_bypassWire_1$whas =
	     WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
	     coreFix_aluExe_1_regToExeQ$first[349] ;
  assign coreFix_aluExe_0_bypassWire_2$wget =
	     { coreFix_aluExe_0_exeToFinQ$first[320:314],
	       coreFix_aluExe_0_exeToFinQ$first[275:212] } ;
  assign coreFix_aluExe_0_bypassWire_2$whas =
	     _dor1coreFix_aluExe_0_bypassWire_2$EN_wset &&
	     coreFix_aluExe_0_exeToFinQ$first[321] ;
  assign coreFix_aluExe_0_bypassWire_3$wget =
	     { coreFix_aluExe_1_exeToFinQ$first[320:314],
	       coreFix_aluExe_1_exeToFinQ$first[275:212] } ;
  assign coreFix_aluExe_0_bypassWire_3$whas =
	     _dor1coreFix_aluExe_0_bypassWire_3$EN_wset &&
	     coreFix_aluExe_1_exeToFinQ$first[321] ;
  assign coreFix_aluExe_1_bypassWire_2$whas =
	     _dor1coreFix_aluExe_1_bypassWire_2$EN_wset &&
	     coreFix_aluExe_0_exeToFinQ$first[321] ;
  assign coreFix_aluExe_1_bypassWire_3$whas =
	     _dor1coreFix_aluExe_1_bypassWire_3$EN_wset &&
	     coreFix_aluExe_1_exeToFinQ$first[321] ;
  assign coreFix_fpuMulDivExe_0_bypassWire_2$whas =
	     _dor1coreFix_fpuMulDivExe_0_bypassWire_2$EN_wset &&
	     coreFix_aluExe_0_exeToFinQ$first[321] ;
  assign coreFix_fpuMulDivExe_0_bypassWire_3$whas =
	     _dor1coreFix_fpuMulDivExe_0_bypassWire_3$EN_wset &&
	     coreFix_aluExe_1_exeToFinQ$first[321] ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_newReq$whas =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_newReq$whas =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_newReq$whas =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] != 2'd0 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] != 2'd1 ;
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225])
      2'd0, 2'd1:
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[226:225];
      default: coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget = 2'd2;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) ;
  assign coreFix_memExe_bypassWire_2$whas =
	     _dor1coreFix_memExe_bypassWire_2$EN_wset &&
	     coreFix_aluExe_0_exeToFinQ$first[321] ;
  assign coreFix_memExe_bypassWire_3$whas =
	     _dor1coreFix_memExe_bypassWire_3$EN_wset &&
	     coreFix_aluExe_1_exeToFinQ$first[321] ;
  assign coreFix_memExe_issueLd$wget =
	     { coreFix_memExe_dTlb$procResp[89:85],
	       coreFix_memExe_dTlb$procResp[174:111],
	       coreFix_memExe_dTlb$procResp[84:77] } ;
  assign coreFix_memExe_issueLd$whas =
	     WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
	     coreFix_memExe_dTlb_procResp__740_BITS_105_TO__ETC___d1894 ;
  assign coreFix_memExe_reqLdQ_data_0_lat_0$wget =
	     MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1 ?
	       coreFix_memExe_issueLd$wget[76:8] :
	       coreFix_memExe_lsq$getIssueLd[76:8] ;
  assign coreFix_memExe_reqLdQ_data_0_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
	     coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
	     coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
  assign coreFix_memExe_reqLdQ_empty_lat_0$whas =
	     _dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset &&
	     coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
  assign coreFix_memExe_reqLdQ_full_lat_0$whas =
	     _dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset &&
	     coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ?
	       MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 :
	       MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_2 ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;
  assign coreFix_memExe_reqStQ_data_0_lat_0$wget =
	     { coreFix_memExe_stb$issue[635:576], 6'd0 } ;
  assign coreFix_memExe_forwardQ_enqReq_lat_0$wget =
	     MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 ?
	       MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1 :
	       MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2 ;
  assign coreFix_memExe_forwardQ_enqReq_lat_0$whas =
	     MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 ||
	     MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2 ;
  assign coreFix_memExe_memRespLdQ_enqReq_lat_0$wget =
	     MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ?
	       MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 :
	       MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 ;
  assign coreFix_memExe_memRespLdQ_enqReq_lat_0$whas =
	     MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ||
	     MUX_coreFix_memExe_lsq$getHit_1__SEL_2 ;
  always@(MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 or
	  MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 or
	  MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2 or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
	  MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1:
	  coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
	      MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1;
      MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2:
	  coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
	      MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2;
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
	  coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
	      MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3;
      default: coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
		   65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas =
	     MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 ||
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
  assign coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
  always@(WILL_FIRE_RL_coreFix_memExe_sendLdToMem or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 or
	  WILL_FIRE_RL_coreFix_memExe_sendStToMem or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 or
	  WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_memExe_sendLdToMem:
	  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1;
      WILL_FIRE_RL_coreFix_memExe_sendStToMem:
	  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2;
      WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem:
	  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3;
      default: coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
		   153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_sendLdToMem ||
	     WILL_FIRE_RL_coreFix_memExe_sendStToMem ||
	     WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ?
	       MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 :
	       MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget =
	     { 1'd1,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq[147:84],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot[54:53],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq[83:82],
	       1'd1,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot[57:55] } ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget =
	     { 1'd1, dCacheToParent_fromP_enq_x } ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget =
	     { 1'd1,
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2677 ;
  always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1:
	  coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1;
      MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2:
	  coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2;
      MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3:
	  coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
	      59'h2AAAAAAAAAAAAAA;
      default: coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
		   59'h2AAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas =
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 ||
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 ||
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ;
  assign coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas =
	     WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ||
	     WILL_FIRE_RL_coreFix_memExe_sendStToMem ||
	     WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;

  // register commitStage_commitTrap
  assign commitStage_commitTrap$D_IN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle ?
	       166'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
	       MUX_commitStage_commitTrap$write_1__VAL_2 ;
  assign commitStage_commitTrap$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;

  // register commitStage_rg_serial_num
  assign commitStage_rg_serial_num$D_IN =
	     MUX_commitStage_rg_serial_num$write_1__SEL_1 ?
	       MUX_commitStage_rg_serial_num$write_1__VAL_1 :
	       MUX_commitStage_rg_serial_num$write_1__VAL_2 ;
  assign commitStage_rg_serial_num$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle ||
	     WILL_FIRE_RL_commitStage_doCommitNormalInst ;

  // register coreFix_doStatsReg
  assign coreFix_doStatsReg$D_IN = 1'b0 ;
  assign coreFix_doStatsReg$EN = 1'b0 ;

  // register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$D_IN =
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt + 4'd1 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$EN =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit ;

  // register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$D_IN = 1'd1 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$EN =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt == 4'd15 ;

  // register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready$D_IN = 1'd1 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready$EN = 1'd1 ;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN =
	     coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ?
	       v__h610689 :
	       v__h609621 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0$D_IN =
	     { coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_newReq$whas,
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11200[127:0] } ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0$EN =
	     1'd1 ;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1$D_IN =
	     coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1$EN =
	     1'd1 ;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0$D_IN =
	     { coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_newReq$whas,
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11187[127:0] } ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0$EN =
	     1'd1 ;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1$D_IN =
	     coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1$EN =
	     1'd1 ;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0$D_IN =
	     { coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_newReq$whas,
	       _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11193[127:0] } ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0$EN =
	     1'd1 ;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1$D_IN =
	     coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1$EN =
	     1'd1 ;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$D_IN =
	     { coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas,
	       coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget } ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$EN = 1'd1 ;

  // register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$D_IN =
	     coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$D_IN =
	     1'd0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$EN =
	     1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ?
	       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[2:0] :
	       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[2:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
	     3'd0 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3153 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3127 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
	     3'd1 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3153 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3127 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
	     3'd2 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3153 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3127 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
	     3'd3 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3153 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3127 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
	     3'd4 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3153 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3127 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
	     3'd5 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3153 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3127 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
	     3'd6 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3153 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3127 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
	     3'd7 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3153 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3127 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ?
	       3'd0 :
	       _theResult_____2__h301173 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$D_IN =
	     1'd0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$EN =
	     1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ||
	     IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3154 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3174 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ?
	       3'd0 :
	       v__h300593 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$D_IN =
	     4'b0010 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$EN =
	     1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$D_IN =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3153 &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3154 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3163 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN =
	     { !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT ||
	       IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3276 ||
	       (EN_dCacheToParent_fromP_enq ?
		  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[582] :
		  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[582]),
	       IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3343 } ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP == 1'd0 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3223 &&
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3234 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP == 1'd1 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3223 &&
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3234 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3223 &&
	     _theResult_____2__h309169 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT &&
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl ||
	     IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3256 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3279 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3223 &&
	     v__h303938 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN =
	     584'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$D_IN =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3223 &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3256 &&
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3266 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$D_IN =
	     { IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3100,
	       IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3108 } ;
  assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_processAmo
  always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2 or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1:
	  coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1;
      MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2:
	  coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2;
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
	  coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
	      161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
      default: coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
		   161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_dMem_cache_m_banks_0_processAmo$EN =
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd4 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget :
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$D_IN =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ||
	     !coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas &&
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$D_IN =
	     !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ||
	      coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$D_IN =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[71:0] :
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[71:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP == 1'd0 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3394 &&
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3405 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$D_IN =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[71:0] :
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[71:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP == 1'd1 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3394 &&
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3405 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3394 &&
	     _theResult_____2__h315163 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT &&
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl ||
	     IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3428 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3451 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3394 &&
	     v__h314452 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$D_IN =
	     73'h0AAAAAAAAAAAAAAAAAA ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$D_IN =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3394 &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3428 &&
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enq_ETC___d3437 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN =
	     { x_addr__h318726,
	       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
		 coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] :
		 coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513],
	       !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT ||
	       IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3543 ||
	       (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
		  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[512] :
		  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[512]),
	       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
		 coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[511:0] :
		 coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[511:0] } ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP == 1'd0 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3490 &&
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3501 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP == 1'd1 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3490 &&
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3501 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3490 &&
	     _theResult_____2__h323017 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT &&
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl ||
	     IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3524 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3547 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3490 &&
	     v__h318328 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN =
	     580'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$D_IN =
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3490 &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3524 &&
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enq_ETC___d3533 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$EN = 1'd1 ;

  // register coreFix_memExe_dMem_perfReqQ_clearReq_rl
  assign coreFix_memExe_dMem_perfReqQ_clearReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_dMem_perfReqQ_clearReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_perfReqQ_data_0
  assign coreFix_memExe_dMem_perfReqQ_data_0$D_IN =
	     coreFix_memExe_dMem_perfReqQ_enqReq_rl[3:0] ;
  assign coreFix_memExe_dMem_perfReqQ_data_0$EN =
	     NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1908 &&
	     coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT &&
	     coreFix_memExe_dMem_perfReqQ_enqReq_rl[4] ;

  // register coreFix_memExe_dMem_perfReqQ_deqReq_rl
  assign coreFix_memExe_dMem_perfReqQ_deqReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_dMem_perfReqQ_deqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_perfReqQ_empty
  assign coreFix_memExe_dMem_perfReqQ_empty$D_IN =
	     coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT &&
	     coreFix_memExe_dMem_perfReqQ_clearReq_rl ||
	     NOT_coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_ETC___d1952 ;
  assign coreFix_memExe_dMem_perfReqQ_empty$EN = 1'd1 ;

  // register coreFix_memExe_dMem_perfReqQ_enqReq_rl
  assign coreFix_memExe_dMem_perfReqQ_enqReq_rl$D_IN = 5'b01010 ;
  assign coreFix_memExe_dMem_perfReqQ_enqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_dMem_perfReqQ_full
  assign coreFix_memExe_dMem_perfReqQ_full$D_IN =
	     NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1908 &&
	     coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2_r_ETC___d1936 ;
  assign coreFix_memExe_dMem_perfReqQ_full$EN = 1'd1 ;

  // register coreFix_memExe_forwardQ_clearReq_rl
  assign coreFix_memExe_forwardQ_clearReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_forwardQ_clearReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_forwardQ_data_0
  assign coreFix_memExe_forwardQ_data_0$D_IN =
	     coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
	       coreFix_memExe_forwardQ_enqReq_lat_0$wget[68:0] :
	       coreFix_memExe_forwardQ_enqReq_rl[68:0] ;
  assign coreFix_memExe_forwardQ_data_0$EN =
	     coreFix_memExe_forwardQ_enqP == 1'd0 &&
	     NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3813 &&
	     coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3824 ;

  // register coreFix_memExe_forwardQ_data_1
  assign coreFix_memExe_forwardQ_data_1$D_IN =
	     coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
	       coreFix_memExe_forwardQ_enqReq_lat_0$wget[68:0] :
	       coreFix_memExe_forwardQ_enqReq_rl[68:0] ;
  assign coreFix_memExe_forwardQ_data_1$EN =
	     coreFix_memExe_forwardQ_enqP == 1'd1 &&
	     NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3813 &&
	     coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3824 ;

  // register coreFix_memExe_forwardQ_deqP
  assign coreFix_memExe_forwardQ_deqP$D_IN =
	     NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3813 &&
	     _theResult_____2__h336586 ;
  assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ;

  // register coreFix_memExe_forwardQ_deqReq_rl
  assign coreFix_memExe_forwardQ_deqReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_forwardQ_deqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_forwardQ_empty
  assign coreFix_memExe_forwardQ_empty$D_IN =
	     coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT &&
	     coreFix_memExe_forwardQ_clearReq_rl ||
	     IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3846 &&
	     NOT_coreFix_memExe_forwardQ_enqReq_dummy2_2_re_ETC___d3868 ;
  assign coreFix_memExe_forwardQ_empty$EN = 1'd1 ;

  // register coreFix_memExe_forwardQ_enqP
  assign coreFix_memExe_forwardQ_enqP$D_IN =
	     NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3813 &&
	     v__h336154 ;
  assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ;

  // register coreFix_memExe_forwardQ_enqReq_rl
  assign coreFix_memExe_forwardQ_enqReq_rl$D_IN = 70'h0AAAAAAAAAAAAAAAAA ;
  assign coreFix_memExe_forwardQ_enqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_forwardQ_full
  assign coreFix_memExe_forwardQ_full$D_IN =
	     NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3813 &&
	     IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3846 &&
	     coreFix_memExe_forwardQ_enqReq_dummy2_2_read___ETC___d3855 ;
  assign coreFix_memExe_forwardQ_full$EN = 1'd1 ;

  // register coreFix_memExe_memRespLdQ_clearReq_rl
  assign coreFix_memExe_memRespLdQ_clearReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_memRespLdQ_clearReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_memRespLdQ_data_0
  assign coreFix_memExe_memRespLdQ_data_0$D_IN =
	     coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
	       coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[68:0] :
	       coreFix_memExe_memRespLdQ_enqReq_rl[68:0] ;
  assign coreFix_memExe_memRespLdQ_data_0$EN =
	     coreFix_memExe_memRespLdQ_enqP == 1'd0 &&
	     NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3719 &&
	     coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3730 ;

  // register coreFix_memExe_memRespLdQ_data_1
  assign coreFix_memExe_memRespLdQ_data_1$D_IN =
	     coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
	       coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[68:0] :
	       coreFix_memExe_memRespLdQ_enqReq_rl[68:0] ;
  assign coreFix_memExe_memRespLdQ_data_1$EN =
	     coreFix_memExe_memRespLdQ_enqP == 1'd1 &&
	     NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3719 &&
	     coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3730 ;

  // register coreFix_memExe_memRespLdQ_deqP
  assign coreFix_memExe_memRespLdQ_deqP$D_IN =
	     NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3719 &&
	     _theResult_____2__h333361 ;
  assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ;

  // register coreFix_memExe_memRespLdQ_deqReq_rl
  assign coreFix_memExe_memRespLdQ_deqReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_memRespLdQ_deqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_memRespLdQ_empty
  assign coreFix_memExe_memRespLdQ_empty$D_IN =
	     coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT &&
	     coreFix_memExe_memRespLdQ_clearReq_rl ||
	     IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3752 &&
	     NOT_coreFix_memExe_memRespLdQ_enqReq_dummy2_2__ETC___d3774 ;
  assign coreFix_memExe_memRespLdQ_empty$EN = 1'd1 ;

  // register coreFix_memExe_memRespLdQ_enqP
  assign coreFix_memExe_memRespLdQ_enqP$D_IN =
	     NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3719 &&
	     v__h332929 ;
  assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ;

  // register coreFix_memExe_memRespLdQ_enqReq_rl
  assign coreFix_memExe_memRespLdQ_enqReq_rl$D_IN = 70'h0AAAAAAAAAAAAAAAAA ;
  assign coreFix_memExe_memRespLdQ_enqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_memRespLdQ_full
  assign coreFix_memExe_memRespLdQ_full$D_IN =
	     NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3719 &&
	     IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3752 &&
	     coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3761 ;
  assign coreFix_memExe_memRespLdQ_full$EN = 1'd1 ;

  // register coreFix_memExe_reqLdQ_data_0_rl
  assign coreFix_memExe_reqLdQ_data_0_rl$D_IN =
	     coreFix_memExe_reqLdQ_data_0_lat_0$whas ?
	       coreFix_memExe_reqLdQ_data_0_lat_0$wget :
	       coreFix_memExe_reqLdQ_data_0_rl ;
  assign coreFix_memExe_reqLdQ_data_0_rl$EN = 1'd1 ;

  // register coreFix_memExe_reqLdQ_empty_rl
  assign coreFix_memExe_reqLdQ_empty_rl$D_IN =
	     WILL_FIRE_RL_coreFix_memExe_sendLdToMem ||
	     !coreFix_memExe_reqLdQ_empty_lat_0$whas &&
	     coreFix_memExe_reqLdQ_empty_rl ;
  assign coreFix_memExe_reqLdQ_empty_rl$EN = 1'd1 ;

  // register coreFix_memExe_reqLdQ_full_rl
  assign coreFix_memExe_reqLdQ_full_rl$D_IN =
	     !WILL_FIRE_RL_coreFix_memExe_sendLdToMem &&
	     (coreFix_memExe_reqLdQ_full_lat_0$whas ||
	      coreFix_memExe_reqLdQ_full_rl) ;
  assign coreFix_memExe_reqLdQ_full_rl$EN = 1'd1 ;

  // register coreFix_memExe_reqLrScAmoQ_data_0_rl
  assign coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN =
	     coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
	       coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget :
	       coreFix_memExe_reqLrScAmoQ_data_0_rl ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_rl$EN = 1'd1 ;

  // register coreFix_memExe_reqLrScAmoQ_empty_rl
  assign coreFix_memExe_reqLrScAmoQ_empty_rl$D_IN =
	     CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ||
	     !coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas &&
	     coreFix_memExe_reqLrScAmoQ_empty_rl ;
  assign coreFix_memExe_reqLrScAmoQ_empty_rl$EN = 1'd1 ;

  // register coreFix_memExe_reqLrScAmoQ_full_rl
  assign coreFix_memExe_reqLrScAmoQ_full_rl$D_IN =
	     !CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem &&
	     (coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ||
	      coreFix_memExe_reqLrScAmoQ_full_rl) ;
  assign coreFix_memExe_reqLrScAmoQ_full_rl$EN = 1'd1 ;

  // register coreFix_memExe_reqStQ_data_0_rl
  assign coreFix_memExe_reqStQ_data_0_rl$D_IN =
	     CAN_FIRE_RL_coreFix_memExe_doIssueSB ?
	       coreFix_memExe_reqStQ_data_0_lat_0$wget :
	       coreFix_memExe_reqStQ_data_0_rl ;
  assign coreFix_memExe_reqStQ_data_0_rl$EN = 1'd1 ;

  // register coreFix_memExe_reqStQ_empty_rl
  assign coreFix_memExe_reqStQ_empty_rl$D_IN =
	     WILL_FIRE_RL_coreFix_memExe_sendStToMem ||
	     !CAN_FIRE_RL_coreFix_memExe_doIssueSB &&
	     coreFix_memExe_reqStQ_empty_rl ;
  assign coreFix_memExe_reqStQ_empty_rl$EN = 1'd1 ;

  // register coreFix_memExe_reqStQ_full_rl
  assign coreFix_memExe_reqStQ_full_rl$D_IN =
	     !WILL_FIRE_RL_coreFix_memExe_sendStToMem &&
	     (CAN_FIRE_RL_coreFix_memExe_doIssueSB ||
	      coreFix_memExe_reqStQ_full_rl) ;
  assign coreFix_memExe_reqStQ_full_rl$EN = 1'd1 ;

  // register coreFix_memExe_respLrScAmoQ_clearReq_rl
  assign coreFix_memExe_respLrScAmoQ_clearReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_respLrScAmoQ_clearReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_respLrScAmoQ_data_0
  assign coreFix_memExe_respLrScAmoQ_data_0$D_IN =
	     coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ?
	       coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[63:0] :
	       coreFix_memExe_respLrScAmoQ_enqReq_rl[63:0] ;
  assign coreFix_memExe_respLrScAmoQ_data_0$EN =
	     NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3643 &&
	     coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3654 ;

  // register coreFix_memExe_respLrScAmoQ_deqReq_rl
  assign coreFix_memExe_respLrScAmoQ_deqReq_rl$D_IN = 1'd0 ;
  assign coreFix_memExe_respLrScAmoQ_deqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_respLrScAmoQ_empty
  assign coreFix_memExe_respLrScAmoQ_empty$D_IN =
	     coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT &&
	     coreFix_memExe_respLrScAmoQ_clearReq_rl ||
	     NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3685 ;
  assign coreFix_memExe_respLrScAmoQ_empty$EN = 1'd1 ;

  // register coreFix_memExe_respLrScAmoQ_enqReq_rl
  assign coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN = 65'h0AAAAAAAAAAAAAAAA ;
  assign coreFix_memExe_respLrScAmoQ_enqReq_rl$EN = 1'd1 ;

  // register coreFix_memExe_respLrScAmoQ_full
  assign coreFix_memExe_respLrScAmoQ_full$D_IN =
	     NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3643 &&
	     coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3670 ;
  assign coreFix_memExe_respLrScAmoQ_full$EN = 1'd1 ;

  // register coreFix_memExe_waitLrScAmoMMIOResp
  always@(MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1 or
	  WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue or
	  WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue or
	  WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue or
	  WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1:
	  coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd0;
      WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue:
	  coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd4;
      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue:
	  coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd2;
      WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue:
	  coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd6;
      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue:
	  coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd7;
      default: coreFix_memExe_waitLrScAmoMMIOResp$D_IN =
		   3'b010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_waitLrScAmoMMIOResp$EN =
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ;

  // register csrInstOrInterruptInflight_rl
  assign csrInstOrInterruptInflight_rl$D_IN =
	     csrInstOrInterruptInflight_lat_1$whas ?
	       1'd1 :
	       (MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1 ?
		  1'd0 :
		  csrInstOrInterruptInflight_rl) ;
  assign csrInstOrInterruptInflight_rl$EN = 1'd1 ;

  // register csrf_external_int_en_vec_0
  assign csrf_external_int_en_vec_0$D_IN = 1'b0 ;
  assign csrf_external_int_en_vec_0$EN = 1'b0 ;

  // register csrf_external_int_en_vec_1
  assign csrf_external_int_en_vec_1$D_IN =
	     csrf_mcycle_ehr_data_lat_0$wget[9] ;
  assign csrf_external_int_en_vec_1$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd9 ||
	      IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd22) ;

  // register csrf_external_int_en_vec_3
  assign csrf_external_int_en_vec_3$D_IN =
	     csrf_mcycle_ehr_data_lat_0$wget[11] ;
  assign csrf_external_int_en_vec_3$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd22 ;

  // register csrf_external_int_pend_vec_0
  assign csrf_external_int_pend_vec_0$D_IN = 1'b0 ;
  assign csrf_external_int_pend_vec_0$EN = 1'b0 ;

  // register csrf_external_int_pend_vec_1
  assign csrf_external_int_pend_vec_1$D_IN =
	     MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ?
	       csrf_mcycle_ehr_data_lat_0$wget[9] :
	       setSEIP_v ;
  assign csrf_external_int_pend_vec_1$EN =
	     MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 || EN_setSEIP ;

  // register csrf_external_int_pend_vec_3
  assign csrf_external_int_pend_vec_3$D_IN = setMEIP_v ;
  assign csrf_external_int_pend_vec_3$EN = EN_setMEIP ;

  // register csrf_fflags_reg
  assign csrf_fflags_reg$D_IN =
	     MUX_csrf_fflags_reg$write_1__SEL_1 ?
	       csrf_mcycle_ehr_data_lat_0$wget[4:0] :
	       MUX_csrf_fflags_reg$write_1__VAL_2 ;
  assign csrf_fflags_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd0 ||
	      IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd2) ||
	     WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	     NOT_IF_NOT_rob_deqPort_0_canDeq__4995_4996_OR__ETC___d15213 ;

  // register csrf_frm_reg
  assign csrf_frm_reg$D_IN =
	     (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd1) ?
	       csrf_mcycle_ehr_data_lat_0$wget[2:0] :
	       csrf_mcycle_ehr_data_lat_0$wget[7:5] ;
  assign csrf_frm_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd1 ||
	      IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd2) ;

  // register csrf_fs_reg
  assign csrf_fs_reg$D_IN =
	     MUX_csrf_fs_reg$write_1__SEL_1 ?
	       MUX_csrf_fs_reg$write_1__VAL_1 :
	       2'b11 ;
  assign csrf_fs_reg$EN =
	     MUX_csrf_fs_reg$write_1__SEL_1 ||
	     WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	     NOT_IF_NOT_rob_deqPort_0_canDeq__4995_4996_OR__ETC___d15213 ;

  // register csrf_ie_vec_0
  assign csrf_ie_vec_0$D_IN = csrf_mcycle_ehr_data_lat_0$wget[0] ;
  assign csrf_ie_vec_0$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd8 ||
	      IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd18) ;

  // register csrf_ie_vec_1
  assign csrf_ie_vec_1$D_IN =
	     !MUX_csrf_ie_vec_1$write_1__SEL_1 &&
	     MUX_csrf_ie_vec_1$write_1__VAL_2 ;
  assign csrf_ie_vec_1$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ;

  // register csrf_ie_vec_3
  assign csrf_ie_vec_3$D_IN =
	     !MUX_csrf_ie_vec_3$write_1__SEL_1 &&
	     MUX_csrf_ie_vec_3$write_1__VAL_2 ;
  assign csrf_ie_vec_3$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ;

  // register csrf_mcause_code_reg
  assign csrf_mcause_code_reg$D_IN =
	     MUX_csrf_ie_vec_3$write_1__SEL_1 ?
	       cause_code__h708698 :
	       csrf_mcycle_ehr_data_lat_0$wget[3:0] ;
  assign csrf_mcause_code_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd27 ;

  // register csrf_mcause_interrupt_reg
  assign csrf_mcause_interrupt_reg$D_IN =
	     MUX_csrf_ie_vec_3$write_1__SEL_1 ?
	       commitStage_commitTrap[36] :
	       csrf_mcycle_ehr_data_lat_0$wget[63] ;
  assign csrf_mcause_interrupt_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd27 ;

  // register csrf_mcounteren_cy_reg
  assign csrf_mcounteren_cy_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[0] ;
  assign csrf_mcounteren_cy_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd24 ;

  // register csrf_mcounteren_ir_reg
  assign csrf_mcounteren_ir_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[2] ;
  assign csrf_mcounteren_ir_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd24 ;

  // register csrf_mcounteren_tm_reg
  assign csrf_mcounteren_tm_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[1] ;
  assign csrf_mcounteren_tm_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd24 ;

  // register csrf_mcycle_ehr_data_rl
  assign csrf_mcycle_ehr_data_rl$D_IN = upd__h4998 ;
  assign csrf_mcycle_ehr_data_rl$EN = 1'd1 ;

  // register csrf_medeleg_13_11_reg
  assign csrf_medeleg_13_11_reg$D_IN =
	     csrf_mcycle_ehr_data_lat_0$wget[13:11] ;
  assign csrf_medeleg_13_11_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd20 ;

  // register csrf_medeleg_15_reg
  assign csrf_medeleg_15_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[15] ;
  assign csrf_medeleg_15_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd20 ;

  // register csrf_medeleg_9_0_reg
  assign csrf_medeleg_9_0_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[9:0] ;
  assign csrf_medeleg_9_0_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd20 ;

  // register csrf_mepc_csr
  assign csrf_mepc_csr$D_IN =
	     MUX_csrf_ie_vec_3$write_1__SEL_1 ?
	       commitStage_commitTrap[164:101] :
	       rob$deqPort_0_deq_data[95:32] ;
  assign csrf_mepc_csr$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd26 ;

  // register csrf_mideleg_11_reg
  assign csrf_mideleg_11_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[11] ;
  assign csrf_mideleg_11_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd21 ;

  // register csrf_mideleg_1_0_reg
  assign csrf_mideleg_1_0_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[1:0] ;
  assign csrf_mideleg_1_0_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd21 ;

  // register csrf_mideleg_5_3_reg
  assign csrf_mideleg_5_3_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[5:3] ;
  assign csrf_mideleg_5_3_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd21 ;

  // register csrf_mideleg_9_7_reg
  assign csrf_mideleg_9_7_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[9:7] ;
  assign csrf_mideleg_9_7_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd21 ;

  // register csrf_minstret_ehr_data_rl
  assign csrf_minstret_ehr_data_rl$D_IN =
	     csrf_minstret_ehr_data_lat_1$whas ?
	       upd__h3681 :
	       IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 ;
  assign csrf_minstret_ehr_data_rl$EN = 1'd1 ;

  // register csrf_mpp_reg
  assign csrf_mpp_reg$D_IN =
	     MUX_csrf_ie_vec_3$write_1__SEL_1 ?
	       csrf_prv_reg :
	       MUX_csrf_mpp_reg$write_1__VAL_2 ;
  assign csrf_mpp_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ;

  // register csrf_mprv_reg
  assign csrf_mprv_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[17] ;
  assign csrf_mprv_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd18 ;

  // register csrf_mscratch_csr
  assign csrf_mscratch_csr$D_IN = rob$deqPort_0_deq_data[95:32] ;
  assign csrf_mscratch_csr$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd25 ;

  // register csrf_mtval_csr
  assign csrf_mtval_csr$D_IN =
	     MUX_csrf_ie_vec_3$write_1__SEL_1 ?
	       MUX_csrf_mtval_csr$write_1__VAL_1 :
	       rob$deqPort_0_deq_data[95:32] ;
  assign csrf_mtval_csr$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd28 ;

  // register csrf_mtvec_base_hi_reg
  assign csrf_mtvec_base_hi_reg$D_IN = csrf_mscratch_csr$D_IN[63:2] ;
  assign csrf_mtvec_base_hi_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd23 ;

  // register csrf_mtvec_mode_low_reg
  assign csrf_mtvec_mode_low_reg$D_IN = csrf_mscratch_csr$D_IN[0] ;
  assign csrf_mtvec_mode_low_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd23 ;

  // register csrf_mxr_reg
  assign csrf_mxr_reg$D_IN = csrf_mscratch_csr$D_IN[19] ;
  assign csrf_mxr_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd8 ||
	      IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd18) ;

  // register csrf_ppn_reg
  assign csrf_ppn_reg$D_IN = csrf_mscratch_csr$D_IN[43:0] ;
  assign csrf_ppn_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd17 ;

  // register csrf_prev_ie_vec_0
  assign csrf_prev_ie_vec_0$D_IN = csrf_mscratch_csr$D_IN[4] ;
  assign csrf_prev_ie_vec_0$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd8 ||
	      IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd18) ;

  // register csrf_prev_ie_vec_1
  assign csrf_prev_ie_vec_1$D_IN =
	     MUX_csrf_ie_vec_1$write_1__SEL_1 ?
	       csrf_ie_vec_1 :
	       MUX_csrf_prev_ie_vec_1$write_1__VAL_2 ;
  assign csrf_prev_ie_vec_1$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ;

  // register csrf_prev_ie_vec_3
  assign csrf_prev_ie_vec_3$D_IN =
	     MUX_csrf_ie_vec_3$write_1__SEL_1 ?
	       csrf_ie_vec_3 :
	       MUX_csrf_prev_ie_vec_3$write_1__VAL_2 ;
  assign csrf_prev_ie_vec_3$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ;

  // register csrf_prv_reg
  assign csrf_prv_reg$D_IN =
	     MUX_csrf_prv_reg$write_1__SEL_1 ?
	       MUX_csrf_prv_reg$write_1__VAL_1 :
	       MUX_csrf_prv_reg$write_1__VAL_2 ;
  assign csrf_prv_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     (rob$deqPort_0_deq_data[257:253] == 5'd19 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd20) ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle ;

  // register csrf_rg_tdata1_data
  assign csrf_rg_tdata1_data$D_IN = csrf_mscratch_csr$D_IN[58:0] ;
  assign csrf_rg_tdata1_data$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd37 ;

  // register csrf_rg_tdata1_dmode
  assign csrf_rg_tdata1_dmode$D_IN = csrf_mscratch_csr$D_IN[59] ;
  assign csrf_rg_tdata1_dmode$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd37 ;

  // register csrf_rg_tdata2
  assign csrf_rg_tdata2$D_IN = rob$deqPort_0_deq_data[95:32] ;
  assign csrf_rg_tdata2$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd38 ;

  // register csrf_rg_tdata3
  assign csrf_rg_tdata3$D_IN = rob$deqPort_0_deq_data[95:32] ;
  assign csrf_rg_tdata3$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd39 ;

  // register csrf_rg_tselect
  assign csrf_rg_tselect$D_IN = rob$deqPort_0_deq_data[95:32] ;
  assign csrf_rg_tselect$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd36 ;

  // register csrf_scause_code_reg
  assign csrf_scause_code_reg$D_IN =
	     MUX_csrf_ie_vec_1$write_1__SEL_1 ?
	       cause_code__h708698 :
	       csrf_rg_tdata3$D_IN[3:0] ;
  assign csrf_scause_code_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd14 ;

  // register csrf_scause_interrupt_reg
  assign csrf_scause_interrupt_reg$D_IN =
	     MUX_csrf_ie_vec_1$write_1__SEL_1 ?
	       commitStage_commitTrap[36] :
	       csrf_rg_tselect$D_IN[63] ;
  assign csrf_scause_interrupt_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd14 ;

  // register csrf_scounteren_cy_reg
  assign csrf_scounteren_cy_reg$D_IN = csrf_rg_tselect$D_IN[0] ;
  assign csrf_scounteren_cy_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd11 ;

  // register csrf_scounteren_ir_reg
  assign csrf_scounteren_ir_reg$D_IN = csrf_rg_tselect$D_IN[2] ;
  assign csrf_scounteren_ir_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd11 ;

  // register csrf_scounteren_tm_reg
  assign csrf_scounteren_tm_reg$D_IN = csrf_rg_tselect$D_IN[1] ;
  assign csrf_scounteren_tm_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd11 ;

  // register csrf_sepc_csr
  assign csrf_sepc_csr$D_IN =
	     MUX_csrf_ie_vec_1$write_1__SEL_1 ?
	       commitStage_commitTrap[164:101] :
	       rob$deqPort_0_deq_data[95:32] ;
  assign csrf_sepc_csr$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd13 ;

  // register csrf_software_int_en_vec_0
  assign csrf_software_int_en_vec_0$D_IN = 1'b0 ;
  assign csrf_software_int_en_vec_0$EN = 1'b0 ;

  // register csrf_software_int_en_vec_1
  assign csrf_software_int_en_vec_1$D_IN = csrf_rg_tselect$D_IN[1] ;
  assign csrf_software_int_en_vec_1$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd9 ||
	      IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd22) ;

  // register csrf_software_int_en_vec_3
  assign csrf_software_int_en_vec_3$D_IN = csrf_rg_tselect$D_IN[3] ;
  assign csrf_software_int_en_vec_3$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd22 ;

  // register csrf_software_int_pend_vec_0
  assign csrf_software_int_pend_vec_0$D_IN = 1'b0 ;
  assign csrf_software_int_pend_vec_0$EN = 1'b0 ;

  // register csrf_software_int_pend_vec_1
  assign csrf_software_int_pend_vec_1$D_IN = csrf_rg_tselect$D_IN[1] ;
  assign csrf_software_int_pend_vec_1$EN =
	     MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ;

  // register csrf_software_int_pend_vec_3
  assign csrf_software_int_pend_vec_3$D_IN =
	     (mmio_pRqQ_data_0[37:36] == 2'd2) ?
	       mmio_pRqQ_data_0[0] :
	       amoExec___d882[0] ;
  assign csrf_software_int_pend_vec_3$EN =
	     WILL_FIRE_RL_mmio_handlePRq && !mmio_pRqQ_data_0[38] &&
	     mmio_pRqQ_data_0[37:36] != 2'd0 &&
	     mmio_pRqQ_data_0[37:36] != 2'd1 ;

  // register csrf_spp_reg
  assign csrf_spp_reg$D_IN =
	     MUX_csrf_ie_vec_1$write_1__SEL_1 ?
	       csrf_prv_reg[0] :
	       MUX_csrf_spp_reg$write_1__VAL_2 ;
  assign csrf_spp_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ;

  // register csrf_sscratch_csr
  assign csrf_sscratch_csr$D_IN = rob$deqPort_0_deq_data[95:32] ;
  assign csrf_sscratch_csr$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd12 ;

  // register csrf_stats_module_doStats
  assign csrf_stats_module_doStats$D_IN = recvDoStats_x ;
  assign csrf_stats_module_doStats$EN = EN_recvDoStats ;

  // register csrf_stval_csr
  assign csrf_stval_csr$D_IN =
	     MUX_csrf_ie_vec_1$write_1__SEL_1 ?
	       MUX_csrf_mtval_csr$write_1__VAL_1 :
	       rob$deqPort_0_deq_data[95:32] ;
  assign csrf_stval_csr$EN =
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd15 ;

  // register csrf_stvec_base_hi_reg
  assign csrf_stvec_base_hi_reg$D_IN = csrf_sscratch_csr$D_IN[63:2] ;
  assign csrf_stvec_base_hi_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd10 ;

  // register csrf_stvec_mode_low_reg
  assign csrf_stvec_mode_low_reg$D_IN = csrf_sscratch_csr$D_IN[0] ;
  assign csrf_stvec_mode_low_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd10 ;

  // register csrf_sum_reg
  assign csrf_sum_reg$D_IN = csrf_sscratch_csr$D_IN[18] ;
  assign csrf_sum_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd8 ||
	      IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd18) ;

  // register csrf_time_reg
  assign csrf_time_reg$D_IN = mmioToPlatform_setTime_t ;
  assign csrf_time_reg$EN = EN_mmioToPlatform_setTime ;

  // register csrf_timer_int_en_vec_0
  assign csrf_timer_int_en_vec_0$D_IN = 1'b0 ;
  assign csrf_timer_int_en_vec_0$EN = 1'b0 ;

  // register csrf_timer_int_en_vec_1
  assign csrf_timer_int_en_vec_1$D_IN = csrf_sscratch_csr$D_IN[5] ;
  assign csrf_timer_int_en_vec_1$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd9 ||
	      IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd22) ;

  // register csrf_timer_int_en_vec_3
  assign csrf_timer_int_en_vec_3$D_IN = csrf_sscratch_csr$D_IN[7] ;
  assign csrf_timer_int_en_vec_3$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd22 ;

  // register csrf_timer_int_pend_vec_0
  assign csrf_timer_int_pend_vec_0$D_IN = 1'b0 ;
  assign csrf_timer_int_pend_vec_0$EN = 1'b0 ;

  // register csrf_timer_int_pend_vec_1
  assign csrf_timer_int_pend_vec_1$D_IN = csrf_sscratch_csr$D_IN[5] ;
  assign csrf_timer_int_pend_vec_1$EN =
	     MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ;

  // register csrf_timer_int_pend_vec_3
  assign csrf_timer_int_pend_vec_3$D_IN = mmio_pRqQ_data_0[0] ;
  assign csrf_timer_int_pend_vec_3$EN =
	     WILL_FIRE_RL_mmio_handlePRq && mmio_pRqQ_data_0[38] &&
	     mmio_pRqQ_data_0[37:36] == 2'd2 ;

  // register csrf_tsr_reg
  assign csrf_tsr_reg$D_IN = csrf_sscratch_csr$D_IN[22] ;
  assign csrf_tsr_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd18 ;

  // register csrf_tvm_reg
  assign csrf_tvm_reg$D_IN = csrf_sscratch_csr$D_IN[20] ;
  assign csrf_tvm_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd18 ;

  // register csrf_tw_reg
  assign csrf_tw_reg$D_IN = csrf_sscratch_csr$D_IN[21] ;
  assign csrf_tw_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd18 ;

  // register csrf_vm_mode_sv39_reg
  assign csrf_vm_mode_sv39_reg$D_IN = csrf_sscratch_csr$D_IN[63] ;
  assign csrf_vm_mode_sv39_reg$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd17 ;

  // register flush_reservation
  assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_1 ;
  assign flush_reservation$EN =
	     WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle ;

  // register flush_tlbs
  assign flush_tlbs$D_IN = !MUX_flush_tlbs$write_1__SEL_1 ;
  assign flush_tlbs$EN =
	     WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     (rob$deqPort_0_deq_data[257:253] == 5'd16 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	      IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd17) ;

  // register mmio_cRqQ_clearReq_rl
  assign mmio_cRqQ_clearReq_rl$D_IN = 1'd0 ;
  assign mmio_cRqQ_clearReq_rl$EN = 1'd1 ;

  // register mmio_cRqQ_data_0
  assign mmio_cRqQ_data_0$D_IN =
	     { x__h45840,
	       (mmio_cRqQ_enqReq_lat_0$whas ?
		  mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd0 :
		  mmio_cRqQ_enqReq_rl[77:76] == 2'd0) ?
		 { 5'd2,
		   mmio_cRqQ_enqReq_lat_0$whas ?
		     mmio_cRqQ_enqReq_lat_0$wget[72] :
		     mmio_cRqQ_enqReq_rl[72] } :
		 IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463,
	       mmio_cRqQ_enqReq_lat_0$whas ?
		 mmio_cRqQ_enqReq_lat_0$wget[71:64] :
		 mmio_cRqQ_enqReq_rl[71:64],
	       x__h48376 } ;
  assign mmio_cRqQ_data_0$EN =
	     NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 &&
	     mmio_cRqQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 ;

  // register mmio_cRqQ_deqReq_rl
  assign mmio_cRqQ_deqReq_rl$D_IN = 1'd0 ;
  assign mmio_cRqQ_deqReq_rl$EN = 1'd1 ;

  // register mmio_cRqQ_empty
  assign mmio_cRqQ_empty$D_IN =
	     mmio_cRqQ_clearReq_dummy2_1$Q_OUT && mmio_cRqQ_clearReq_rl ||
	     NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452 ;
  assign mmio_cRqQ_empty$EN = 1'd1 ;

  // register mmio_cRqQ_enqReq_rl
  assign mmio_cRqQ_enqReq_rl$D_IN =
	     143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
  assign mmio_cRqQ_enqReq_rl$EN = 1'd1 ;

  // register mmio_cRqQ_full
  assign mmio_cRqQ_full$D_IN =
	     NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 &&
	     mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 ;
  assign mmio_cRqQ_full$EN = 1'd1 ;

  // register mmio_cRsQ_clearReq_rl
  assign mmio_cRsQ_clearReq_rl$D_IN = 1'd0 ;
  assign mmio_cRsQ_clearReq_rl$EN = 1'd1 ;

  // register mmio_cRsQ_data_0
  assign mmio_cRsQ_data_0$D_IN =
	     CAN_FIRE_RL_mmio_handlePRq ?
	       mmio_cRsQ_enqReq_lat_0$wget[0] :
	       mmio_cRsQ_enqReq_rl[0] ;
  assign mmio_cRsQ_data_0$EN =
	     NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 &&
	     mmio_cRsQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 ;

  // register mmio_cRsQ_deqReq_rl
  assign mmio_cRsQ_deqReq_rl$D_IN = 1'd0 ;
  assign mmio_cRsQ_deqReq_rl$EN = 1'd1 ;

  // register mmio_cRsQ_empty
  assign mmio_cRsQ_empty$D_IN =
	     mmio_cRsQ_clearReq_dummy2_1$Q_OUT && mmio_cRsQ_clearReq_rl ||
	     NOT_mmio_cRsQ_enqReq_dummy2_2_read__24_39_OR_I_ETC___d844 ;
  assign mmio_cRsQ_empty$EN = 1'd1 ;

  // register mmio_cRsQ_enqReq_rl
  assign mmio_cRsQ_enqReq_rl$D_IN = 2'b0 ;
  assign mmio_cRsQ_enqReq_rl$EN = 1'd1 ;

  // register mmio_cRsQ_full
  assign mmio_cRsQ_full$D_IN =
	     NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 &&
	     mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836 ;
  assign mmio_cRsQ_full$EN = 1'd1 ;

  // register mmio_dataPendQ_clearReq_rl
  assign mmio_dataPendQ_clearReq_rl$D_IN = 1'd0 ;
  assign mmio_dataPendQ_clearReq_rl$EN = 1'd1 ;

  // register mmio_dataPendQ_deqReq_rl
  assign mmio_dataPendQ_deqReq_rl$D_IN = 1'd0 ;
  assign mmio_dataPendQ_deqReq_rl$EN = 1'd1 ;

  // register mmio_dataPendQ_empty
  assign mmio_dataPendQ_empty$D_IN =
	     mmio_dataPendQ_clearReq_dummy2_1$Q_OUT &&
	     mmio_dataPendQ_clearReq_rl ||
	     NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 ;
  assign mmio_dataPendQ_empty$EN = 1'd1 ;

  // register mmio_dataPendQ_enqReq_rl
  assign mmio_dataPendQ_enqReq_rl$D_IN = 1'd0 ;
  assign mmio_dataPendQ_enqReq_rl$EN = 1'd1 ;

  // register mmio_dataPendQ_full
  assign mmio_dataPendQ_full$D_IN =
	     (!mmio_dataPendQ_clearReq_dummy2_1$Q_OUT ||
	      !mmio_dataPendQ_clearReq_rl) &&
	     mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312 ;
  assign mmio_dataPendQ_full$EN = 1'd1 ;

  // register mmio_dataReqQ_clearReq_rl
  assign mmio_dataReqQ_clearReq_rl$D_IN = 1'd0 ;
  assign mmio_dataReqQ_clearReq_rl$EN = 1'd1 ;

  // register mmio_dataReqQ_data_0
  assign mmio_dataReqQ_data_0$D_IN =
	     { x__h17933,
	       (mmio_dataReqQ_enqReq_lat_0$whas ?
		  mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd0 :
		  mmio_dataReqQ_enqReq_rl[77:76] == 2'd0) ?
		 { 5'd2,
		   mmio_dataReqQ_enqReq_lat_0$whas ?
		     mmio_dataReqQ_enqReq_lat_0$wget[72] :
		     mmio_dataReqQ_enqReq_rl[72] } :
		 IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172,
	       mmio_dataReqQ_enqReq_lat_0$whas ?
		 mmio_dataReqQ_enqReq_lat_0$wget[71:64] :
		 mmio_dataReqQ_enqReq_rl[71:64],
	       x__h20471 } ;
  assign mmio_dataReqQ_data_0$EN =
	     NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 &&
	     mmio_dataReqQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 ;

  // register mmio_dataReqQ_deqReq_rl
  assign mmio_dataReqQ_deqReq_rl$D_IN = 1'd0 ;
  assign mmio_dataReqQ_deqReq_rl$EN = 1'd1 ;

  // register mmio_dataReqQ_empty
  assign mmio_dataReqQ_empty$D_IN =
	     mmio_dataReqQ_clearReq_dummy2_1$Q_OUT &&
	     mmio_dataReqQ_clearReq_rl ||
	     NOT_mmio_dataReqQ_enqReq_dummy2_2_read__41_56__ETC___d161 ;
  assign mmio_dataReqQ_empty$EN = 1'd1 ;

  // register mmio_dataReqQ_enqReq_rl
  assign mmio_dataReqQ_enqReq_rl$D_IN =
	     143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
  assign mmio_dataReqQ_enqReq_rl$EN = 1'd1 ;

  // register mmio_dataReqQ_full
  assign mmio_dataReqQ_full$D_IN =
	     NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 &&
	     mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153 ;
  assign mmio_dataReqQ_full$EN = 1'd1 ;

  // register mmio_dataRespQ_clearReq_rl
  assign mmio_dataRespQ_clearReq_rl$D_IN = 1'd0 ;
  assign mmio_dataRespQ_clearReq_rl$EN = 1'd1 ;

  // register mmio_dataRespQ_data_0
  assign mmio_dataRespQ_data_0$D_IN =
	     CAN_FIRE_RL_mmio_sendDataResp ?
	       mmio_dataRespQ_enqReq_lat_0$wget[64:0] :
	       mmio_dataRespQ_enqReq_rl[64:0] ;
  assign mmio_dataRespQ_data_0$EN =
	     NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 &&
	     mmio_dataRespQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 ;

  // register mmio_dataRespQ_deqReq_rl
  assign mmio_dataRespQ_deqReq_rl$D_IN = 1'd0 ;
  assign mmio_dataRespQ_deqReq_rl$EN = 1'd1 ;

  // register mmio_dataRespQ_empty
  assign mmio_dataRespQ_empty$D_IN =
	     mmio_dataRespQ_clearReq_dummy2_1$Q_OUT &&
	     mmio_dataRespQ_clearReq_rl ||
	     NOT_mmio_dataRespQ_enqReq_dummy2_2_read__42_57_ETC___d262 ;
  assign mmio_dataRespQ_empty$EN = 1'd1 ;

  // register mmio_dataRespQ_enqReq_rl
  assign mmio_dataRespQ_enqReq_rl$D_IN = 66'h0AAAAAAAAAAAAAAAA ;
  assign mmio_dataRespQ_enqReq_rl$EN = 1'd1 ;

  // register mmio_dataRespQ_full
  assign mmio_dataRespQ_full$D_IN =
	     NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 &&
	     mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254 ;
  assign mmio_dataRespQ_full$EN = 1'd1 ;

  // register mmio_fromHostAddr
  assign mmio_fromHostAddr$D_IN = coreReq_start_fromHostAddr[63:3] ;
  assign mmio_fromHostAddr$EN = EN_coreReq_start ;

  // register mmio_pRqQ_clearReq_rl
  assign mmio_pRqQ_clearReq_rl$D_IN = 1'd0 ;
  assign mmio_pRqQ_clearReq_rl$EN = 1'd1 ;

  // register mmio_pRqQ_data_0
  assign mmio_pRqQ_data_0$D_IN =
	     { EN_mmioToPlatform_pRq_enq ?
		 mmio_pRqQ_enqReq_lat_0$wget[38] :
		 mmio_pRqQ_enqReq_rl[38],
	       (EN_mmioToPlatform_pRq_enq ?
		  mmio_pRqQ_enqReq_lat_0$wget[37:36] == 2'd0 :
		  mmio_pRqQ_enqReq_rl[37:36] == 2'd0) ?
		 { 5'd2,
		   EN_mmioToPlatform_pRq_enq ?
		     mmio_pRqQ_enqReq_lat_0$wget[32] :
		     mmio_pRqQ_enqReq_rl[32] } :
		 IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766,
	       x_data__h65634 } ;
  assign mmio_pRqQ_data_0$EN =
	     NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 &&
	     mmio_pRqQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 ;

  // register mmio_pRqQ_deqReq_rl
  assign mmio_pRqQ_deqReq_rl$D_IN = 1'd0 ;
  assign mmio_pRqQ_deqReq_rl$EN = 1'd1 ;

  // register mmio_pRqQ_empty
  assign mmio_pRqQ_empty$D_IN =
	     mmio_pRqQ_clearReq_dummy2_1$Q_OUT && mmio_pRqQ_clearReq_rl ||
	     NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755 ;
  assign mmio_pRqQ_empty$EN = 1'd1 ;

  // register mmio_pRqQ_enqReq_rl
  assign mmio_pRqQ_enqReq_rl$D_IN = 40'h2AAAAAAAAA ;
  assign mmio_pRqQ_enqReq_rl$EN = 1'd1 ;

  // register mmio_pRqQ_full
  assign mmio_pRqQ_full$D_IN =
	     NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 &&
	     mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747 ;
  assign mmio_pRqQ_full$EN = 1'd1 ;

  // register mmio_pRsQ_clearReq_rl
  assign mmio_pRsQ_clearReq_rl$D_IN = 1'd0 ;
  assign mmio_pRsQ_clearReq_rl$EN = 1'd1 ;

  // register mmio_pRsQ_data_0
  assign mmio_pRsQ_data_0$D_IN =
	     { EN_mmioToPlatform_pRs_enq ?
		 mmio_pRsQ_enqReq_lat_0$wget[66] :
		 mmio_pRsQ_enqReq_rl[66],
	       IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627 } ;
  assign mmio_pRsQ_data_0$EN =
	     NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 &&
	     mmio_pRsQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 ;

  // register mmio_pRsQ_deqReq_rl
  assign mmio_pRsQ_deqReq_rl$D_IN = 1'd0 ;
  assign mmio_pRsQ_deqReq_rl$EN = 1'd1 ;

  // register mmio_pRsQ_empty
  assign mmio_pRsQ_empty$D_IN =
	     mmio_pRsQ_clearReq_dummy2_1$Q_OUT && mmio_pRsQ_clearReq_rl ||
	     NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614 ;
  assign mmio_pRsQ_empty$EN = 1'd1 ;

  // register mmio_pRsQ_enqReq_rl
  assign mmio_pRsQ_enqReq_rl$D_IN = 68'h2AAAAAAAAAAAAAAAA ;
  assign mmio_pRsQ_enqReq_rl$EN = 1'd1 ;

  // register mmio_pRsQ_full
  assign mmio_pRsQ_full$D_IN =
	     NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 &&
	     mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606 ;
  assign mmio_pRsQ_full$EN = 1'd1 ;

  // register mmio_toHostAddr
  assign mmio_toHostAddr$D_IN = coreReq_start_toHostAddr[63:3] ;
  assign mmio_toHostAddr$EN = EN_coreReq_start ;

  // register outOfReset
  assign outOfReset$D_IN = 1'd1 ;
  assign outOfReset$EN = CAN_FIRE_RL_rl_outOfReset ;

  // register started
  assign started$D_IN = 1'd1 ;
  assign started$EN = EN_coreReq_start ;

  // register update_vm_info
  assign update_vm_info$D_IN = !MUX_update_vm_info$write_1__SEL_1 ;
  assign update_vm_info$EN =
	     WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle ;

  // submodule coreFix_aluExe_0_dispToRegQ
  assign coreFix_aluExe_0_dispToRegQ$enq_x =
	     { coreFix_aluExe_0_rsAlu$dispatchData[161:157],
	       CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268,
	       coreFix_aluExe_0_rsAlu$dispatchData[135],
	       CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q269,
	       coreFix_aluExe_0_rsAlu$dispatchData[122:90],
	       coreFix_aluExe_0_rsAlu$dispatchData[65:21],
	       coreFix_aluExe_0_rsAlu$dispatchData[89:66],
	       coreFix_aluExe_0_rsAlu$dispatchData[8:4],
	       coreFix_aluExe_0_rsAlu$dispatchData[20:9] } ;
  assign coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
	     !WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	     !WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_0_dispToRegQ$EN_enq =
	     WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ;
  assign coreFix_aluExe_0_dispToRegQ$EN_deq =
	     WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu ;
  assign coreFix_aluExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_aluExe_0_dispToRegQ$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_aluExe_0_exeToFinQ
  assign coreFix_aluExe_0_exeToFinQ$enq_x =
	     { coreFix_aluExe_0_regToExeQ$first[421:417],
	       coreFix_aluExe_0_regToExeQ$first[349:305],
	       coreFix_aluExe_0_regToExeQ$first[18:17] != 2'b11,
	       basicExec___d12775[321:258],
	       coreFix_aluExe_0_regToExeQ$first[395],
	       basicExec___d12775[257:194],
	       basicExec___d12775[129:0],
	       coreFix_aluExe_0_regToExeQ$first[16:0] } ;
  assign coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_0_exeToFinQ$EN_enq =
	     WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu ;
  assign coreFix_aluExe_0_exeToFinQ$EN_deq =
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
  assign coreFix_aluExe_0_exeToFinQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_aluExe_0_exeToFinQ$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_aluExe_0_regToExeQ
  assign coreFix_aluExe_0_regToExeQ$enq_x =
	     { coreFix_aluExe_0_dispToRegQ$first[157:153],
	       CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q271,
	       coreFix_aluExe_0_dispToRegQ$first[131],
	       CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q272,
	       coreFix_aluExe_0_dispToRegQ$first[118:86],
	       coreFix_aluExe_0_dispToRegQ$first[61:17],
	       x__h646279,
	       x__h646280,
	       rob$getOrigPC_0_get,
	       rob$getOrigPredPC_0_get,
	       rob$getOrig_Inst_0_get,
	       coreFix_aluExe_0_dispToRegQ$first[16:0] } ;
  assign coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_0_regToExeQ$EN_enq =
	     WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu ;
  assign coreFix_aluExe_0_regToExeQ$EN_deq =
	     WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu ;
  assign coreFix_aluExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_aluExe_0_regToExeQ$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_aluExe_0_rsAlu
  assign coreFix_aluExe_0_rsAlu$enq_x =
	     MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 ?
	       MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 :
	       MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 ;
  assign coreFix_aluExe_0_rsAlu$setRegReady_0_put =
	     { 1'd1, coreFix_aluExe_0_rsAlu$dispatchData[40:34] } ;
  assign coreFix_aluExe_0_rsAlu$setRegReady_1_put =
	     { 1'd1, coreFix_aluExe_1_rsAlu$dispatchData[40:34] } ;
  always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
	  coreFix_aluExe_0_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
	  coreFix_aluExe_0_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
	  coreFix_aluExe_0_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
	  coreFix_aluExe_0_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
	  coreFix_aluExe_0_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
	  coreFix_aluExe_0_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
      default: coreFix_aluExe_0_rsAlu$setRegReady_2_put =
		   8'b10101010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_0_rsAlu$setRegReady_3_put =
	     { 1'd1, coreFix_memExe_lsq$issueLd[71:65] } ;
  always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1:
	  coreFix_aluExe_0_rsAlu$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2:
	  coreFix_aluExe_0_rsAlu$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
	  coreFix_aluExe_0_rsAlu$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
	  coreFix_aluExe_0_rsAlu$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
      default: coreFix_aluExe_0_rsAlu$setRegReady_4_put =
		   8'b10101010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_0_rsAlu$setRobEnqTime_t = rob$getEnqTime ;
  assign coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_0_rsAlu$EN_enq =
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	     fetchStage$pipelines_0_first[194:192] == 3'd0 ||
	     WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ;
  assign coreFix_aluExe_0_rsAlu$EN_setRobEnqTime = 1'd1 ;
  assign coreFix_aluExe_0_rsAlu$EN_doDispatch =
	     WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ;
  assign coreFix_aluExe_0_rsAlu$EN_setRegReady_0_put =
	     WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
	     coreFix_aluExe_0_rsAlu$dispatchData[41] ;
  assign coreFix_aluExe_0_rsAlu$EN_setRegReady_1_put =
	     WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
	     coreFix_aluExe_1_rsAlu$dispatchData[41] ;
  assign coreFix_aluExe_0_rsAlu$EN_setRegReady_2_put =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
  assign coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put =
	     _dor1coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
	     coreFix_memExe_lsq$issueLd[72] ;
  assign coreFix_aluExe_0_rsAlu$EN_setRegReady_4_put =
	     (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
	     coreFix_memExe_lsq$firstSt[150] ||
	     (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
	     coreFix_memExe_lsq$firstLd[89] ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2650 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 &&
	     coreFix_memExe_lsq$getHit[8] &&
	     !coreFix_memExe_lsq$getHit[9] ;
  assign coreFix_aluExe_0_rsAlu$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_aluExe_0_rsAlu$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_aluExe_1_dispToRegQ
  assign coreFix_aluExe_1_dispToRegQ$enq_x =
	     { coreFix_aluExe_1_rsAlu$dispatchData[161:157],
	       CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274,
	       coreFix_aluExe_1_rsAlu$dispatchData[135],
	       CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q275,
	       coreFix_aluExe_1_rsAlu$dispatchData[122:90],
	       coreFix_aluExe_1_rsAlu$dispatchData[65:21],
	       coreFix_aluExe_1_rsAlu$dispatchData[89:66],
	       coreFix_aluExe_1_rsAlu$dispatchData[8:4],
	       coreFix_aluExe_1_rsAlu$dispatchData[20:9] } ;
  assign coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_1_dispToRegQ$EN_enq =
	     WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu ;
  assign coreFix_aluExe_1_dispToRegQ$EN_deq =
	     WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu ;
  assign coreFix_aluExe_1_dispToRegQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_aluExe_1_dispToRegQ$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_aluExe_1_exeToFinQ
  assign coreFix_aluExe_1_exeToFinQ$enq_x =
	     { coreFix_aluExe_1_regToExeQ$first[421:417],
	       coreFix_aluExe_1_regToExeQ$first[349:305],
	       coreFix_aluExe_1_regToExeQ$first[18:17] != 2'b11,
	       basicExec___d12101[321:258],
	       coreFix_aluExe_1_regToExeQ$first[395],
	       basicExec___d12101[257:194],
	       basicExec___d12101[129:0],
	       coreFix_aluExe_1_regToExeQ$first[16:0] } ;
  assign coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_1_exeToFinQ$EN_enq =
	     WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu ;
  assign coreFix_aluExe_1_exeToFinQ$EN_deq =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
  assign coreFix_aluExe_1_exeToFinQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_aluExe_1_exeToFinQ$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_aluExe_1_regToExeQ
  assign coreFix_aluExe_1_regToExeQ$enq_x =
	     { coreFix_aluExe_1_dispToRegQ$first[157:153],
	       CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q277,
	       coreFix_aluExe_1_dispToRegQ$first[131],
	       CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q278,
	       coreFix_aluExe_1_dispToRegQ$first[118:86],
	       coreFix_aluExe_1_dispToRegQ$first[61:17],
	       x__h623649,
	       x__h623650,
	       rob$getOrigPC_1_get,
	       rob$getOrigPredPC_1_get,
	       rob$getOrig_Inst_1_get,
	       coreFix_aluExe_1_dispToRegQ$first[16:0] } ;
  assign coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_1_regToExeQ$EN_enq =
	     WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu ;
  assign coreFix_aluExe_1_regToExeQ$EN_deq =
	     WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu ;
  assign coreFix_aluExe_1_regToExeQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_aluExe_1_regToExeQ$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_aluExe_1_rsAlu
  assign coreFix_aluExe_1_rsAlu$enq_x =
	     (k__h675032 == 1'd1 &&
	      fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14186) ?
	       { fetchStage$pipelines_0_first[199:195],
		 IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043,
		 fetchStage$pipelines_0_first[173],
		 IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125,
		 fetchStage$pipelines_0_first[160:128],
		 fetchStage$pipelines_0_first[255:232],
		 regRenamingTable$rename_0_getRename,
		 rob$enqPort_0_getEnqInstTag,
		 specTagManager$currentSpecBits,
		 fetchStage$pipelines_0_first[194:192] == 3'd1,
		 specTagManager$nextSpecTag,
		 sbAggr$eagerLookup_0_get } :
	       { fetchStage$pipelines_1_first[199:195],
		 IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13701,
		 fetchStage_pipelines_1_first__2937_BIT_173_370_ETC___d13785,
		 fetchStage$pipelines_1_first[160:128],
		 fetchStage$pipelines_1_first[255:232],
		 regRenamingTable$rename_1_getRename,
		 rob$enqPort_1_getEnqInstTag,
		 renaming_spec_bits__h690496,
		 fetchStage$pipelines_1_first[194:192] == 3'd1,
		 specTagManager$nextSpecTag,
		 sbAggr$eagerLookup_1_get } ;
  assign coreFix_aluExe_1_rsAlu$setRegReady_0_put =
	     coreFix_aluExe_0_rsAlu$setRegReady_0_put ;
  assign coreFix_aluExe_1_rsAlu$setRegReady_1_put =
	     coreFix_aluExe_0_rsAlu$setRegReady_1_put ;
  always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
	  coreFix_aluExe_1_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
	  coreFix_aluExe_1_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
	  coreFix_aluExe_1_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
	  coreFix_aluExe_1_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
	  coreFix_aluExe_1_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
	  coreFix_aluExe_1_rsAlu$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
      default: coreFix_aluExe_1_rsAlu$setRegReady_2_put =
		   8'b10101010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_1_rsAlu$setRegReady_3_put =
	     coreFix_aluExe_0_rsAlu$setRegReady_3_put ;
  always@(MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
	  MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1:
	  coreFix_aluExe_1_rsAlu$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
      MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2:
	  coreFix_aluExe_1_rsAlu$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
	  coreFix_aluExe_1_rsAlu$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
	  coreFix_aluExe_1_rsAlu$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
      default: coreFix_aluExe_1_rsAlu$setRegReady_4_put =
		   8'b10101010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_1_rsAlu$setRobEnqTime_t = rob$getEnqTime ;
  assign coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_aluExe_1_rsAlu$EN_enq =
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     (k__h675032 == 1'd1 &&
	      fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14186 ||
	      fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14305 ==
	      1'd1 &&
	      NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14322) ;
  assign coreFix_aluExe_1_rsAlu$EN_setRobEnqTime = 1'd1 ;
  assign coreFix_aluExe_1_rsAlu$EN_doDispatch =
	     WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu ;
  assign coreFix_aluExe_1_rsAlu$EN_setRegReady_0_put =
	     WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
	     coreFix_aluExe_0_rsAlu$dispatchData[41] ;
  assign coreFix_aluExe_1_rsAlu$EN_setRegReady_1_put =
	     WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
	     coreFix_aluExe_1_rsAlu$dispatchData[41] ;
  assign coreFix_aluExe_1_rsAlu$EN_setRegReady_2_put =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
  assign coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put =
	     _dor1coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
	     coreFix_memExe_lsq$issueLd[72] ;
  assign coreFix_aluExe_1_rsAlu$EN_setRegReady_4_put =
	     (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
	     coreFix_memExe_lsq$firstSt[150] ||
	     (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
	     coreFix_memExe_lsq$firstLd[89] ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2650 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 &&
	     coreFix_memExe_lsq$getHit[8] &&
	     !coreFix_memExe_lsq$getHit[9] ;
  assign coreFix_aluExe_1_rsAlu$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_aluExe_1_rsAlu$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_fpuMulDivExe_0_dispToRegQ
  assign coreFix_fpuMulDivExe_0_dispToRegQ$enq_x =
	     { CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q280,
	       coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[65:9] } ;
  assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_enq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv ;
  assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_deq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv ;
  assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_correctSpeculation =
	     1'd1 ;

  // submodule coreFix_fpuMulDivExe_0_fpuExec_divQ
  assign coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x =
	     { IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828,
	       coreFix_fpuMulDivExe_0_regToExeQ$first[225],
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10965,
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d11001,
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d11049,
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d11091,
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d11133,
	       coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
	       coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28,
	       coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
	       coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
  assign coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_enq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd3 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_deq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv ;
  assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_correctSpeculation =
	     1'd1 ;

  // submodule coreFix_fpuMulDivExe_0_fpuExec_double_div
  assign coreFix_fpuMulDivExe_0_fpuExec_double_div$request_put =
	     { IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9285,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10765,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 } ;
  assign coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_request_put =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd3 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_response_get =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv ;

  // submodule coreFix_fpuMulDivExe_0_fpuExec_double_fma
  assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put =
	     { coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd2,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10055,
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281,
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q282,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 } ;
  assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd1 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd2 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) ;
  assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_response_get =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma ;

  // submodule coreFix_fpuMulDivExe_0_fpuExec_double_sqrt
  assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$request_put =
	     { IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9285,
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 } ;
  assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_request_put =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd4 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_response_get =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt ;

  // submodule coreFix_fpuMulDivExe_0_fpuExec_fmaQ
  assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x =
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x ;
  assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_enq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd1 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd2 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) ;
  assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_deq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma ;
  assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_correctSpeculation =
	     1'd1 ;

  // submodule coreFix_fpuMulDivExe_0_fpuExec_simpleQ
  assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$enq_x =
	     { execFpuSimple___d11167,
	       coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
	       coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
  assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_enq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd0 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd1 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd2 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd25 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd26 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd27 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd28 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd3 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd4 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_deq =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
  assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_correctSpeculation =
	     1'd1 ;

  // submodule coreFix_fpuMulDivExe_0_fpuExec_sqrtQ
  assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x =
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x ;
  assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_enq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd4 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_deq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt ;
  assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_correctSpeculation =
	     1'd1 ;

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_divQ
  assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$enq_x =
	     { coreFix_fpuMulDivExe_0_regToExeQ$first[229:227],
	       coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
	       coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_enq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_deq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_correctSpeculation =
	     1'd1 ;

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_IN =
	     { x__h608911,
	       b__h608375 == 64'd0,
	       a__h608374,
	       coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0,
	       x__h608937,
	       a__h608374[63],
	       8'd0 } ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$ENQ =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$DEQ =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$CLR =
	     1'b0 ;

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_IN =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ?
	       _theResult___snd__h608923 :
	       b__h608375 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$ENQ =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$DEQ =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$CLR =
	     1'b0 ;

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_IN =
	     { x__h609551,
	       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[75:0] } ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$ENQ =
	     CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_compute ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$DEQ =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$CLR = 1'b0 ;

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulQ
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$enq_x =
	     { coreFix_fpuMulDivExe_0_regToExeQ$first[229:227],
	       coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
	       coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_enq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_deq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_correctSpeculation =
	     1'd1 ;

  // submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ
  always@(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 or
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1 or
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1 or
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1)
  begin
    case (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1[1:0])
      2'd0:
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN =
	      coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1[127:0];
      2'd1:
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN =
	      coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1[127:0];
      default: coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN =
		   coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1[127:0];
    endcase
  end
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$ENQ =
	     coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1[2] ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$DEQ =
	     coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$CLR = 1'b0 ;

  // submodule coreFix_fpuMulDivExe_0_regToExeQ
  assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x =
	     { CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q284,
	       coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12],
	       x__h487050,
	       x__h487051,
	       x__h487052,
	       coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ;
  assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_regToExeQ$EN_enq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv ;
  assign coreFix_fpuMulDivExe_0_regToExeQ$EN_deq =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ;
  assign coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_correctSpeculation =
	     1'd1 ;

  // submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x =
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3528_AND__ETC___d14198) ?
	       { IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043,
		 regRenamingTable$rename_0_getRename,
		 rob$enqPort_0_getEnqInstTag,
		 specTagManager$currentSpecBits,
		 fetchStage$pipelines_0_first[194:192] == 3'd1,
		 specTagManager$nextSpecTag,
		 sbAggr$eagerLookup_0_get } :
	       { IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13701,
		 regRenamingTable$rename_1_getRename,
		 rob$enqPort_1_getEnqInstTag,
		 renaming_spec_bits__h690496,
		 fetchStage$pipelines_1_first[194:192] == 3'd1,
		 specTagManager$nextSpecTag,
		 sbAggr$eagerLookup_1_get } ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_0_put =
	     coreFix_aluExe_0_rsAlu$setRegReady_0_put ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_1_put =
	     coreFix_aluExe_0_rsAlu$setRegReady_1_put ;
  always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
      default: coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
		   8'b10101010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_3_put =
	     coreFix_aluExe_0_rsAlu$setRegReady_3_put ;
  always@(MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
	  MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
      MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
      default: coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
		   8'b10101010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t = rob$getEnqTime ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq =
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3528_AND__ETC___d14198 ||
	      NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 &&
	      regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 &&
	      (fetchStage$pipelines_1_first[194:192] == 3'd3 ||
	       fetchStage$pipelines_1_first[194:192] == 3'd4) &&
	      NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14358 &&
	      coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq) ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime = 1'd1 ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_0_put =
	     WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
	     coreFix_aluExe_0_rsAlu$dispatchData[41] ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_1_put =
	     WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
	     coreFix_aluExe_1_rsAlu$dispatchData[41] ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_2_put =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put =
	     _dor1coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
	     coreFix_memExe_lsq$issueLd[72] ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_4_put =
	     (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
	     coreFix_memExe_lsq$firstSt[150] ||
	     (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
	     coreFix_memExe_lsq$firstLd[89] ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2650 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 &&
	     coreFix_memExe_lsq$getHit[8] &&
	     !coreFix_memExe_lsq$getHit[9] ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_correctSpeculation =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r =
	     { x__h291826,
	       x__h291838,
	       IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2882,
	       IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2886,
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2890,
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2894,
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2898,
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2903,
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2907,
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2912,
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2916,
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2921,
	       x__h293692,
	       IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2929,
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2933,
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2937,
	       coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2941 } ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n =
	     x__h290393 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n =
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] ==
	      2'd0) ?
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] :
	       (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] :
		  3'd0) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ;
  always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1 or
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
	  coreFix_memExe_dMem_cache_m_banks_0_processAmo)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1:
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574];
      MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2:
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512];
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
	      coreFix_memExe_dMem_cache_m_banks_0_processAmo[159:157];
      default: coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
		   3'b010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain_addr =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:84] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d =
	     { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
	       2'd3,
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_n =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_n =
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ?
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] :
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot =
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ?
	       MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1 :
	       MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_state =
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ?
	       MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1 :
	       3'd3 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_n =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[2:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_succ =
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq_n =
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot_n =
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData_n =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq_n =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot_n =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState_n =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_n =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_slot =
	     { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[57:55],
	       55'h15555555555555 } ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_cRqTransfer_getEmptyEntryInit =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_sendRsToP_cRq_setWaitSt_setSlot_clearData =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_releaseEntry =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2627 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	     3'd4 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setData =
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setStateSlot =
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2771 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2774 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setSucc =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
	      3'd1) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_stuck_get = 1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN =
	     EN_dCacheToParent_fromP_enq ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2610 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd2 ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd3) ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2821 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] ==
	     2'd0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN =
	     MUX_flush_reservation$write_1__SEL_1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r =
	     { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2968,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q285 } ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n =
	     2'h0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_releaseEntry_n =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d =
	     { !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
	       2'd3,
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_n =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData_n =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[1:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq_n =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[1:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_releaseEntry_n =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[1:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_getEmptyEntryInit =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_sendRsToP_pRq_releaseEntry =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_releaseEntry =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] ||
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2771 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2774) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_setDone_setData =
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_stuck_get = 1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_pipeline
  always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
	  coreFix_memExe_dMem_cache_m_banks_0_processAmo or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1;
      MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc;
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
	      coreFix_memExe_dMem_cache_m_banks_0_processAmo[3:0];
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq = 4'd2;
      default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1 or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1;
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
	      1'd0;
      MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 ||
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
	      1'd1;
      default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
		   1'b0 /* unspecified value */ ;
    endcase
  end
  always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2 or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3 or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1;
      MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2;
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3;
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4;
      default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
		   570'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  always@(WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 or
	  WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer or
	  MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1;
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2;
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3;
      WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer:
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
	      MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4;
      default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
		   584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_send =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_deqWrite =
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	     3'd4 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_IN =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ?
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_OUT :
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_OUT ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$ENQ =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$DEQ =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$CLR = 1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$ENQ =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2679 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	      (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	       3'd1) &&
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2683) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$DEQ =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$CLR =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_IN =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$ENQ =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$DEQ =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$CLR =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN =
	     EN_dCacheToParent_rqToP_deq ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_IN =
	     MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 ?
	       MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 :
	       MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$ENQ =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2771 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2774 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2730 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$DEQ =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$CLR = 1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN =
	     EN_dCacheToParent_rsToP_deq ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN =
	     1'b0 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN =
	     1'b0 ;

  // submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN =
	     1'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN =
	     1'd1 ;

  // submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0
  assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1
  assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0
  assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN = 1'b0 ;
  assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN = 1'b0 ;

  // submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1
  assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2
  assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0
  assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN = 1'b0 ;
  assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN = 1'b0 ;

  // submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1
  assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2
  assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule coreFix_memExe_dTlb
  assign coreFix_memExe_dTlb$perf_req_r = 3'h0 ;
  assign coreFix_memExe_dTlb$perf_setStatus_doStats = 1'b0 ;
  assign coreFix_memExe_dTlb$procReq_req =
	     { coreFix_memExe_regToExeQ$first[192:190],
	       coreFix_memExe_regToExeQ$first[157:140],
	       coreFix_memExe_lsq$getOrigBE << vaddr__h184738[2:0],
	       vaddr__h184738,
	       coreFix_memExe_lsq$getOrigBE[7] ?
		 vaddr__h184738[2:0] != 3'd0 :
		 (coreFix_memExe_lsq$getOrigBE[3] ?
		    vaddr__h184738[1:0] != 2'd0 :
		    coreFix_memExe_lsq$getOrigBE[1] && vaddr__h184738[0]),
	       coreFix_memExe_regToExeQ$first[11:0] } ;
  assign coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_dTlb$toParent_ldTransRsFromP_enq_x =
	     { l2Tlb$toChildren_rsToC_first[80:0],
	       l2Tlb$toChildren_rsToC_first[82:81] } ;
  assign coreFix_memExe_dTlb$updateVMInfo_vm =
	     { prv__h724946,
	       prv__h724946 != 2'd3 && csrf_vm_mode_sv39_reg,
	       csrf_mxr_reg,
	       csrf_sum_reg,
	       csrf_ppn_reg } ;
  assign coreFix_memExe_dTlb$EN_flush = MUX_flush_tlbs$write_1__SEL_1 ;
  assign coreFix_memExe_dTlb$EN_updateVMInfo =
	     MUX_update_vm_info$write_1__SEL_1 ;
  assign coreFix_memExe_dTlb$EN_procReq =
	     CAN_FIRE_RL_coreFix_memExe_doExeMem ;
  assign coreFix_memExe_dTlb$EN_deqProcResp =
	     CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
  assign coreFix_memExe_dTlb$EN_toParent_rqToP_deq = CAN_FIRE_RL_sendDTlbReq ;
  assign coreFix_memExe_dTlb$EN_toParent_ldTransRsFromP_enq =
	     CAN_FIRE_RL_sendRsToDTlb ;
  assign coreFix_memExe_dTlb$EN_toParent_flush_request_get =
	     CAN_FIRE_RL_mkConnectionGetPut ;
  assign coreFix_memExe_dTlb$EN_toParent_flush_response_put =
	     CAN_FIRE_RL_sendFlushDone ;
  assign coreFix_memExe_dTlb$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_memExe_dTlb$EN_specUpdate_correctSpeculation = 1'd1 ;
  assign coreFix_memExe_dTlb$EN_perf_setStatus = 1'b0 ;
  assign coreFix_memExe_dTlb$EN_perf_req = 1'b0 ;
  assign coreFix_memExe_dTlb$EN_perf_resp = 1'b0 ;

  // submodule coreFix_memExe_dispToRegQ
  assign coreFix_memExe_dispToRegQ$enq_x =
	     { coreFix_memExe_rsMem$dispatchData[106:72],
	       coreFix_memExe_rsMem$dispatchData[65:21],
	       coreFix_memExe_rsMem$dispatchData[71:66],
	       coreFix_memExe_rsMem$dispatchData[20:9] } ;
  assign coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_dispToRegQ$EN_enq =
	     WILL_FIRE_RL_coreFix_memExe_doDispatchMem ;
  assign coreFix_memExe_dispToRegQ$EN_deq =
	     WILL_FIRE_RL_coreFix_memExe_doRegReadMem ;
  assign coreFix_memExe_dispToRegQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_memExe_dispToRegQ$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_memExe_forwardQ_clearReq_dummy2_0
  assign coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign coreFix_memExe_forwardQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule coreFix_memExe_forwardQ_clearReq_dummy2_1
  assign coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign coreFix_memExe_forwardQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule coreFix_memExe_forwardQ_deqReq_dummy2_0
  assign coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_forwardQ_deqReq_dummy2_0$EN =
	     WILL_FIRE_RL_coreFix_memExe_doRespLdForward ;

  // submodule coreFix_memExe_forwardQ_deqReq_dummy2_1
  assign coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_forwardQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_forwardQ_deqReq_dummy2_2
  assign coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign coreFix_memExe_forwardQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule coreFix_memExe_forwardQ_enqReq_dummy2_0
  assign coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_forwardQ_enqReq_dummy2_0$EN =
	     _dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ;

  // submodule coreFix_memExe_forwardQ_enqReq_dummy2_1
  assign coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_forwardQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_forwardQ_enqReq_dummy2_2
  assign coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign coreFix_memExe_forwardQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule coreFix_memExe_lsq
  assign coreFix_memExe_lsq$enqLd_dst =
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3528_AND__ETC___d14255) ?
	       regRenamingTable$rename_0_getRename[8:0] :
	       regRenamingTable$rename_1_getRename[8:0] ;
  assign coreFix_memExe_lsq$enqLd_inst_tag =
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3528_AND__ETC___d14255) ?
	       rob$enqPort_0_getEnqInstTag :
	       rob$enqPort_1_getEnqInstTag ;
  assign coreFix_memExe_lsq$enqLd_mem_inst =
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3528_AND__ETC___d14255) ?
	       fetchStage$pipelines_0_first[191:174] :
	       fetchStage$pipelines_1_first[191:174] ;
  assign coreFix_memExe_lsq$enqLd_spec_bits =
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3528_AND__ETC___d14255) ?
	       specTagManager$currentSpecBits :
	       renaming_spec_bits__h690496 ;
  assign coreFix_memExe_lsq$enqSt_dst =
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3528_AND__ETC___d14263) ?
	       regRenamingTable$rename_0_getRename[8:0] :
	       regRenamingTable$rename_1_getRename[8:0] ;
  assign coreFix_memExe_lsq$enqSt_inst_tag =
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3528_AND__ETC___d14263) ?
	       rob$enqPort_0_getEnqInstTag :
	       rob$enqPort_1_getEnqInstTag ;
  assign coreFix_memExe_lsq$enqSt_mem_inst =
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3528_AND__ETC___d14263) ?
	       fetchStage$pipelines_0_first[191:174] :
	       fetchStage$pipelines_1_first[191:174] ;
  assign coreFix_memExe_lsq$enqSt_spec_bits =
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3528_AND__ETC___d14263) ?
	       specTagManager$currentSpecBits :
	       renaming_spec_bits__h690496 ;
  assign coreFix_memExe_lsq$getHit_t =
	     MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ?
	       MUX_coreFix_memExe_lsq$getHit_1__VAL_1 :
	       MUX_coreFix_memExe_lsq$getHit_1__VAL_1 ;
  assign coreFix_memExe_lsq$getOrigBE_t =
	     coreFix_memExe_regToExeQ$first[145:140] ;
  assign coreFix_memExe_lsq$issueLd_lsqTag =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
	       coreFix_memExe_lsq$getIssueLd[76:72] :
	       coreFix_memExe_issueLd$wget[76:72] ;
  assign coreFix_memExe_lsq$issueLd_paddr =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
	       coreFix_memExe_lsq$getIssueLd[71:8] :
	       coreFix_memExe_issueLd$wget[71:8] ;
  assign coreFix_memExe_lsq$issueLd_sbRes =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
	       MUX_coreFix_memExe_lsq$issueLd_4__VAL_1 :
	       coreFix_memExe_stb$search ;
  assign coreFix_memExe_lsq$issueLd_shiftedBE =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
	       coreFix_memExe_lsq$getIssueLd[7:0] :
	       coreFix_memExe_issueLd$wget[7:0] ;
  assign coreFix_memExe_lsq$respLd_alignedData =
	     WILL_FIRE_RL_coreFix_memExe_doRespLdMem ?
	       MUX_coreFix_memExe_lsq$respLd_2__VAL_1 :
	       MUX_coreFix_memExe_lsq$respLd_2__VAL_2 ;
  assign coreFix_memExe_lsq$respLd_t =
	     WILL_FIRE_RL_coreFix_memExe_doRespLdMem ?
	       MUX_coreFix_memExe_lsq$respLd_1__VAL_1 :
	       MUX_coreFix_memExe_lsq$respLd_1__VAL_2 ;
  assign coreFix_memExe_lsq$setAtCommit_0_put =
	     rob$deqPort_0_deq_data[24:19] ;
  assign coreFix_memExe_lsq$setAtCommit_1_put =
	     rob$deqPort_1_deq_data[24:19] ;
  assign coreFix_memExe_lsq$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_lsq$updateAddr_fault =
	     { (!coreFix_memExe_dTlb$procResp[12] &&
		!coreFix_memExe_dTlb$procResp[110] &&
		coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1759) ?
		 coreFix_memExe_dTlb$procResp[105:103] == 3'd2 ||
		 coreFix_memExe_dTlb$procResp[105:103] == 3'd3 ||
		 coreFix_memExe_dTlb$procResp[12] :
		 coreFix_memExe_dTlb$procResp[12] ||
		 coreFix_memExe_dTlb$procResp[110],
	       IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1885 } ;
  assign coreFix_memExe_lsq$updateAddr_isMMIO =
	     coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1759 ;
  assign coreFix_memExe_lsq$updateAddr_lsqTag =
	     coreFix_memExe_dTlb$procResp[90:85] ;
  assign coreFix_memExe_lsq$updateAddr_paddr =
	     coreFix_memExe_dTlb$procResp[174:111] ;
  assign coreFix_memExe_lsq$updateAddr_shiftedBE =
	     coreFix_memExe_dTlb$procResp[84:77] ;
  assign coreFix_memExe_lsq$updateData_d =
	     (coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ?
	       coreFix_memExe_regToExeQ$first[75:12] :
	       shiftData__h184743 ;
  assign coreFix_memExe_lsq$updateData_t =
	     coreFix_memExe_regToExeQ$first[143:140] ;
  assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[149:148] ;
  assign coreFix_memExe_lsq$EN_enqLd =
	     WILL_FIRE_RL_renameStage_doRenaming && _dfoo7 ;
  assign coreFix_memExe_lsq$EN_enqSt =
	     WILL_FIRE_RL_renameStage_doRenaming && _dfoo2 ;
  assign coreFix_memExe_lsq$EN_getHit =
	     MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 ;
  assign coreFix_memExe_lsq$EN_updateData =
	     WILL_FIRE_RL_coreFix_memExe_doExeMem &&
	     coreFix_memExe_regToExeQ$first[145] ;
  assign coreFix_memExe_lsq$EN_updateAddr =
	     CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
  assign coreFix_memExe_lsq$EN_issueLd =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign coreFix_memExe_lsq$EN_getIssueLd =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ;
  assign coreFix_memExe_lsq$EN_respLd =
	     WILL_FIRE_RL_coreFix_memExe_doRespLdMem ||
	     WILL_FIRE_RL_coreFix_memExe_doRespLdForward ;
  assign coreFix_memExe_lsq$EN_deqLd =
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
  assign coreFix_memExe_lsq$EN_deqSt =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault ;
  assign coreFix_memExe_lsq$EN_wakeupLdStalledBySB =
	     MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd1 ;
  assign coreFix_memExe_lsq$EN_setAtCommit_0_put =
	     CAN_FIRE_RL_commitStage_doSetLSQAtCommit ;
  assign coreFix_memExe_lsq$EN_setAtCommit_1_put =
	     CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 ;
  assign coreFix_memExe_lsq$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_memExe_lsq$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0
  assign coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1
  assign coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0
  assign coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN =
	     WILL_FIRE_RL_coreFix_memExe_doRespLdMem ;

  // submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1
  assign coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2
  assign coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0
  assign coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN =
	     MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 ;

  // submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1
  assign coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2
  assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule coreFix_memExe_regToExeQ
  assign coreFix_memExe_regToExeQ$enq_x =
	     { coreFix_memExe_dispToRegQ$first[97:63],
	       coreFix_memExe_dispToRegQ$first[29:12],
	       x__h184650,
	       x__h184651,
	       coreFix_memExe_dispToRegQ$first[11:0] } ;
  assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_regToExeQ$EN_enq =
	     WILL_FIRE_RL_coreFix_memExe_doRegReadMem ;
  assign coreFix_memExe_regToExeQ$EN_deq =
	     CAN_FIRE_RL_coreFix_memExe_doExeMem ;
  assign coreFix_memExe_regToExeQ$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_memExe_regToExeQ$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_memExe_reqLdQ_data_0_dummy2_0
  assign coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLdQ_data_0_dummy2_0$EN =
	     _dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write &&
	     coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;

  // submodule coreFix_memExe_reqLdQ_data_0_dummy2_1
  assign coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_reqLdQ_data_0_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_reqLdQ_deqP_dummy2_0
  assign coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLdQ_deqP_dummy2_0$EN =
	     WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;

  // submodule coreFix_memExe_reqLdQ_deqP_dummy2_1
  assign coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_reqLdQ_deqP_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_reqLdQ_empty_dummy2_0
  assign coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLdQ_empty_dummy2_0$EN =
	     _dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write &&
	     coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;

  // submodule coreFix_memExe_reqLdQ_empty_dummy2_1
  assign coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLdQ_empty_dummy2_1$EN =
	     WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;

  // submodule coreFix_memExe_reqLdQ_empty_dummy2_2
  assign coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN = 1'b0 ;
  assign coreFix_memExe_reqLdQ_empty_dummy2_2$EN = 1'b0 ;

  // submodule coreFix_memExe_reqLdQ_enqP_dummy2_0
  assign coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLdQ_enqP_dummy2_0$EN =
	     _dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write &&
	     coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;

  // submodule coreFix_memExe_reqLdQ_enqP_dummy2_1
  assign coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_reqLdQ_enqP_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_reqLdQ_full_dummy2_0
  assign coreFix_memExe_reqLdQ_full_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLdQ_full_dummy2_0$EN =
	     _dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write &&
	     coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;

  // submodule coreFix_memExe_reqLdQ_full_dummy2_1
  assign coreFix_memExe_reqLdQ_full_dummy2_1$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLdQ_full_dummy2_1$EN =
	     WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;

  // submodule coreFix_memExe_reqLdQ_full_dummy2_2
  assign coreFix_memExe_reqLdQ_full_dummy2_2$D_IN = 1'b0 ;
  assign coreFix_memExe_reqLdQ_full_dummy2_2$EN = 1'b0 ;

  // submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN =
	     coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;

  // submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0
  assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN =
	     CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;

  // submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1
  assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0
  assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN =
	     coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;

  // submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1
  assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN =
	     CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;

  // submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2
  assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN = 1'b0 ;
  assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN = 1'b0 ;

  // submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0
  assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN =
	     coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;

  // submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1
  assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0
  assign coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN =
	     coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;

  // submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1
  assign coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN = 1'd1 ;
  assign coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN =
	     CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;

  // submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2
  assign coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN = 1'b0 ;
  assign coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN = 1'b0 ;

  // submodule coreFix_memExe_reqStQ_data_0_dummy2_0
  assign coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqStQ_data_0_dummy2_0$EN =
	     CAN_FIRE_RL_coreFix_memExe_doIssueSB ;

  // submodule coreFix_memExe_reqStQ_data_0_dummy2_1
  assign coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_reqStQ_data_0_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_reqStQ_deqP_dummy2_0
  assign coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqStQ_deqP_dummy2_0$EN =
	     WILL_FIRE_RL_coreFix_memExe_sendStToMem ;

  // submodule coreFix_memExe_reqStQ_deqP_dummy2_1
  assign coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_reqStQ_deqP_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_reqStQ_empty_dummy2_0
  assign coreFix_memExe_reqStQ_empty_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqStQ_empty_dummy2_0$EN =
	     CAN_FIRE_RL_coreFix_memExe_doIssueSB ;

  // submodule coreFix_memExe_reqStQ_empty_dummy2_1
  assign coreFix_memExe_reqStQ_empty_dummy2_1$D_IN = 1'd1 ;
  assign coreFix_memExe_reqStQ_empty_dummy2_1$EN =
	     WILL_FIRE_RL_coreFix_memExe_sendStToMem ;

  // submodule coreFix_memExe_reqStQ_empty_dummy2_2
  assign coreFix_memExe_reqStQ_empty_dummy2_2$D_IN = 1'b0 ;
  assign coreFix_memExe_reqStQ_empty_dummy2_2$EN = 1'b0 ;

  // submodule coreFix_memExe_reqStQ_enqP_dummy2_0
  assign coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqStQ_enqP_dummy2_0$EN =
	     CAN_FIRE_RL_coreFix_memExe_doIssueSB ;

  // submodule coreFix_memExe_reqStQ_enqP_dummy2_1
  assign coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_reqStQ_enqP_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_reqStQ_full_dummy2_0
  assign coreFix_memExe_reqStQ_full_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_reqStQ_full_dummy2_0$EN =
	     CAN_FIRE_RL_coreFix_memExe_doIssueSB ;

  // submodule coreFix_memExe_reqStQ_full_dummy2_1
  assign coreFix_memExe_reqStQ_full_dummy2_1$D_IN = 1'd1 ;
  assign coreFix_memExe_reqStQ_full_dummy2_1$EN =
	     WILL_FIRE_RL_coreFix_memExe_sendStToMem ;

  // submodule coreFix_memExe_reqStQ_full_dummy2_2
  assign coreFix_memExe_reqStQ_full_dummy2_2$D_IN = 1'b0 ;
  assign coreFix_memExe_reqStQ_full_dummy2_2$EN = 1'b0 ;

  // submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0
  assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1
  assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0
  assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN =
	     coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas ;

  // submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1
  assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2
  assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0
  assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2593 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd2 ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd3) ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;

  // submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1
  assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2
  assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule coreFix_memExe_rsMem
  assign coreFix_memExe_rsMem$enq_x =
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3528_AND__ETC___d14221) ?
	       { fetchStage$pipelines_0_first[191:189],
		 IF_fetchStage_pipelines_0_first__2928_BIT_160__ETC___d14237,
		 regRenamingTable$rename_0_getRename,
		 rob$enqPort_0_getEnqInstTag,
		 specTagManager$currentSpecBits,
		 fetchStage$pipelines_0_first[194:192] == 3'd1,
		 specTagManager$nextSpecTag,
		 sbAggr$eagerLookup_0_get } :
	       { fetchStage$pipelines_1_first[191:189],
		 IF_fetchStage_pipelines_1_first__2937_BIT_160__ETC___d14398,
		 regRenamingTable$rename_1_getRename,
		 rob$enqPort_1_getEnqInstTag,
		 renaming_spec_bits__h690496,
		 fetchStage$pipelines_1_first[194:192] == 3'd1,
		 specTagManager$nextSpecTag,
		 sbAggr$eagerLookup_1_get } ;
  assign coreFix_memExe_rsMem$setRegReady_0_put =
	     coreFix_aluExe_0_rsAlu$setRegReady_0_put ;
  assign coreFix_memExe_rsMem$setRegReady_1_put =
	     coreFix_aluExe_0_rsAlu$setRegReady_1_put ;
  always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
	  coreFix_memExe_rsMem$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
	  coreFix_memExe_rsMem$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
	  coreFix_memExe_rsMem$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
	  coreFix_memExe_rsMem$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
	  coreFix_memExe_rsMem$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
	  coreFix_memExe_rsMem$setRegReady_2_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
      default: coreFix_memExe_rsMem$setRegReady_2_put =
		   8'b10101010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_rsMem$setRegReady_3_put =
	     coreFix_aluExe_0_rsAlu$setRegReady_3_put ;
  always@(MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
	  MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1:
	  coreFix_memExe_rsMem$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
      MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2:
	  coreFix_memExe_rsMem$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
	  coreFix_memExe_rsMem$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
	  coreFix_memExe_rsMem$setRegReady_4_put =
	      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
      default: coreFix_memExe_rsMem$setRegReady_4_put =
		   8'b10101010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_rsMem$setRobEnqTime_t = rob$getEnqTime ;
  assign coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign coreFix_memExe_rsMem$EN_enq =
	     WILL_FIRE_RL_renameStage_doRenaming && _dfoo12 ;
  assign coreFix_memExe_rsMem$EN_setRobEnqTime = 1'd1 ;
  assign coreFix_memExe_rsMem$EN_doDispatch =
	     WILL_FIRE_RL_coreFix_memExe_doDispatchMem ;
  assign coreFix_memExe_rsMem$EN_setRegReady_0_put =
	     WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
	     coreFix_aluExe_0_rsAlu$dispatchData[41] ;
  assign coreFix_memExe_rsMem$EN_setRegReady_1_put =
	     WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
	     coreFix_aluExe_1_rsAlu$dispatchData[41] ;
  assign coreFix_memExe_rsMem$EN_setRegReady_2_put =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
  assign coreFix_memExe_rsMem$EN_setRegReady_3_put =
	     _dor1coreFix_memExe_rsMem$EN_setRegReady_3_put &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
	     coreFix_memExe_lsq$issueLd[72] ;
  assign coreFix_memExe_rsMem$EN_setRegReady_4_put =
	     (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
	     coreFix_memExe_lsq$firstSt[150] ||
	     (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
	     coreFix_memExe_lsq$firstLd[89] ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2650 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 &&
	     coreFix_memExe_lsq$getHit[8] &&
	     !coreFix_memExe_lsq$getHit[9] ;
  assign coreFix_memExe_rsMem$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign coreFix_memExe_rsMem$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule coreFix_memExe_stb
  assign coreFix_memExe_stb$deq_idx =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[149:148] ;
  assign coreFix_memExe_stb$enq_be = coreFix_memExe_lsq$firstSt[76:69] ;
  assign coreFix_memExe_stb$enq_data = coreFix_memExe_lsq$firstSt[68:5] ;
  assign coreFix_memExe_stb$enq_idx = coreFix_memExe_stb$getEnqIndex[1:0] ;
  assign coreFix_memExe_stb$enq_paddr = coreFix_memExe_lsq$firstSt[141:78] ;
  assign coreFix_memExe_stb$getEnqIndex_paddr =
	     coreFix_memExe_lsq$firstSt[141:78] ;
  assign coreFix_memExe_stb$noMatchLdQ_be = coreFix_memExe_lsq$firstLd[15:8] ;
  assign coreFix_memExe_stb$noMatchLdQ_paddr =
	     coreFix_memExe_lsq$firstLd[80:17] ;
  assign coreFix_memExe_stb$noMatchStQ_be =
	     coreFix_memExe_lsq$firstSt[76:69] ;
  assign coreFix_memExe_stb$noMatchStQ_paddr =
	     coreFix_memExe_lsq$firstSt[141:78] ;
  assign coreFix_memExe_stb$search_be =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
	       coreFix_memExe_lsq$getIssueLd[7:0] :
	       coreFix_memExe_issueLd$wget[7:0] ;
  assign coreFix_memExe_stb$search_paddr =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
	       coreFix_memExe_lsq$getIssueLd[71:8] :
	       coreFix_memExe_issueLd$wget[71:8] ;
  assign coreFix_memExe_stb$EN_enq =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem ;
  assign coreFix_memExe_stb$EN_deq =
	     MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd1 ;
  assign coreFix_memExe_stb$EN_issue = CAN_FIRE_RL_coreFix_memExe_doIssueSB ;

  // submodule coreFix_trainBPQ_0
  assign coreFix_trainBPQ_0$D_IN =
	     MUX_coreFix_trainBPQ_0$enq_1__SEL_1 ?
	       MUX_coreFix_trainBPQ_0$enq_1__VAL_1 :
	       MUX_coreFix_trainBPQ_0$enq_1__VAL_2 ;
  assign coreFix_trainBPQ_0$ENQ =
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
	     (coreFix_aluExe_0_exeToFinQ$first[326:322] == 5'd9 ||
	      coreFix_aluExe_0_exeToFinQ$first[326:322] == 5'd10) ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
  assign coreFix_trainBPQ_0$DEQ = WILL_FIRE_RL_coreFix_doFetchTrainBP_1 ;
  assign coreFix_trainBPQ_0$CLR = 1'b0 ;

  // submodule coreFix_trainBPQ_1
  assign coreFix_trainBPQ_1$D_IN =
	     MUX_coreFix_trainBPQ_1$enq_1__SEL_1 ?
	       MUX_coreFix_trainBPQ_1$enq_1__VAL_1 :
	       MUX_coreFix_trainBPQ_1$enq_1__VAL_2 ;
  assign coreFix_trainBPQ_1$ENQ =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
	     (coreFix_aluExe_1_exeToFinQ$first[326:322] == 5'd9 ||
	      coreFix_aluExe_1_exeToFinQ$first[326:322] == 5'd10) ||
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
  assign coreFix_trainBPQ_1$DEQ = coreFix_trainBPQ_1$EMPTY_N ;
  assign coreFix_trainBPQ_1$CLR = 1'b0 ;

  // submodule csrInstOrInterruptInflight_dummy2_0
  assign csrInstOrInterruptInflight_dummy2_0$D_IN = 1'd1 ;
  assign csrInstOrInterruptInflight_dummy2_0$EN =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
	     commitStage_commitTrap[36] ;

  // submodule csrInstOrInterruptInflight_dummy2_1
  assign csrInstOrInterruptInflight_dummy2_1$D_IN = 1'd1 ;
  assign csrInstOrInterruptInflight_dummy2_1$EN =
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	     fetchStage$pipelines_0_first[199:195] == 5'd13 ||
	     MUX_csrInstOrInterruptInflight_dummy2_1$write_1__SEL_2 ;

  // submodule csrf_mcycle_ehr_data_dummy2_0
  assign csrf_mcycle_ehr_data_dummy2_0$D_IN = 1'd1 ;
  assign csrf_mcycle_ehr_data_dummy2_0$EN = csrf_mcycle_ehr_data_lat_0$whas ;

  // submodule csrf_mcycle_ehr_data_dummy2_1
  assign csrf_mcycle_ehr_data_dummy2_1$D_IN = 1'd1 ;
  assign csrf_mcycle_ehr_data_dummy2_1$EN = 1'd1 ;

  // submodule csrf_minstret_ehr_data_dummy2_0
  assign csrf_minstret_ehr_data_dummy2_0$D_IN = 1'd1 ;
  assign csrf_minstret_ehr_data_dummy2_0$EN =
	     csrf_minstret_ehr_data_lat_0$whas ;

  // submodule csrf_minstret_ehr_data_dummy2_1
  assign csrf_minstret_ehr_data_dummy2_1$D_IN = 1'd1 ;
  assign csrf_minstret_ehr_data_dummy2_1$EN =
	     csrf_minstret_ehr_data_dummy_1_0$whas ;

  // submodule csrf_stats_module_writeQ
  assign csrf_stats_module_writeQ$D_IN = csrf_sscratch_csr$D_IN[0] ;
  assign csrf_stats_module_writeQ$ENQ =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd7 ;
  assign csrf_stats_module_writeQ$DEQ = EN_sendDoStats ;
  assign csrf_stats_module_writeQ$CLR = 1'b0 ;

  // submodule csrf_terminate_module_terminateQ
  assign csrf_terminate_module_terminateQ$ENQ =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd6 ;
  assign csrf_terminate_module_terminateQ$DEQ = EN_coreIndInv_terminate ;
  assign csrf_terminate_module_terminateQ$CLR = 1'b0 ;

  // submodule epochManager
  assign epochManager$checkEpoch_0_check_e =
	     fetchStage$pipelines_0_first[259:256] ;
  assign epochManager$checkEpoch_1_check_e =
	     fetchStage$pipelines_1_first[259:256] ;
  assign epochManager$updatePrevEpoch_0_update_e =
	     fetchStage$pipelines_0_first[259:256] ;
  assign epochManager$updatePrevEpoch_1_update_e =
	     fetchStage$pipelines_1_first[259:256] ;
  assign epochManager$EN_updatePrevEpoch_0_update =
	     WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
	     fetchStage$pipelines_0_canDeq ||
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     fetchStage$pipelines_0_canDeq &&
	     NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183 &&
	     IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 ||
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
	     WILL_FIRE_RL_renameStage_doRenaming_Trap ;
  assign epochManager$EN_updatePrevEpoch_1_update =
	     WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
	     fetchStage$pipelines_1_canDeq &&
	     !epochManager$checkEpoch_1_check ||
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 &&
	     NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14319 &&
	     IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13999 ;
  assign epochManager$EN_incrementEpoch =
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !rob$deqPort_0_deq_data[12] ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
	     WILL_FIRE_RL_renameStage_doRenaming_Trap ;

  // submodule fetchStage
  assign fetchStage$iMemIfc_perf_req_r = 2'h0 ;
  assign fetchStage$iMemIfc_perf_setStatus_doStats = 1'b0 ;
  assign fetchStage$iMemIfc_to_parent_fromP_enq_x =
	     iCacheToParent_fromP_enq_x ;
  assign fetchStage$iMemIfc_to_proc_request_put = 64'h0 ;
  assign fetchStage$iTlbIfc_perf_req_r = 3'h0 ;
  assign fetchStage$iTlbIfc_perf_setStatus_doStats = 1'b0 ;
  assign fetchStage$iTlbIfc_toParent_rsFromP_enq_x =
	     l2Tlb$toChildren_rsToC_first[80:0] ;
  assign fetchStage$iTlbIfc_to_proc_request_put = 64'h0 ;
  assign fetchStage$iTlbIfc_updateVMInfo_vm =
	     { csrf_prv_reg,
	       csrf_prv_reg != 2'd3 && csrf_vm_mode_sv39_reg,
	       csrf_mxr_reg,
	       csrf_sum_reg,
	       csrf_ppn_reg } ;
  assign fetchStage$mmioIfc_instResp_enq_x = mmio_pRsQ_data_0[65:0] ;
  assign fetchStage$mmioIfc_setHtifAddrs_fromHost =
	     coreReq_start_fromHostAddr ;
  assign fetchStage$mmioIfc_setHtifAddrs_toHost = coreReq_start_toHostAddr ;
  assign fetchStage$perf_req_r = 2'h0 ;
  assign fetchStage$perf_setStatus_doStats = 1'b0 ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  WILL_FIRE_RL_commitStage_doCommitKilledLd or
	  rob$deqPort_0_deq_data or
	  WILL_FIRE_RL_commitStage_doCommitTrap_handle or
	  MUX_fetchStage$redirect_1__VAL_4 or
	  WILL_FIRE_RL_commitStage_doCommitSystemInst or
	  MUX_fetchStage$redirect_1__VAL_5)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  fetchStage$redirect_pc = coreFix_aluExe_1_exeToFinQ$first[82:19];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  fetchStage$redirect_pc = coreFix_aluExe_0_exeToFinQ$first[82:19];
      WILL_FIRE_RL_commitStage_doCommitKilledLd:
	  fetchStage$redirect_pc = rob$deqPort_0_deq_data[353:290];
      WILL_FIRE_RL_commitStage_doCommitTrap_handle:
	  fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_4;
      WILL_FIRE_RL_commitStage_doCommitSystemInst:
	  fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_5;
      default: fetchStage$redirect_pc =
		   64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign fetchStage$start_pc = coreReq_start_startpc ;
  assign fetchStage$train_predictors_dpTrain =
	     coreFix_trainBPQ_1$EMPTY_N ?
	       coreFix_trainBPQ_1$D_OUT[25:2] :
	       coreFix_trainBPQ_0$D_OUT[25:2] ;
  assign fetchStage$train_predictors_iType =
	     coreFix_trainBPQ_1$EMPTY_N ?
	       coreFix_trainBPQ_1$D_OUT[31:27] :
	       coreFix_trainBPQ_0$D_OUT[31:27] ;
  assign fetchStage$train_predictors_isCompressed =
	     coreFix_trainBPQ_1$EMPTY_N ?
	       coreFix_trainBPQ_1$D_OUT[0] :
	       coreFix_trainBPQ_0$D_OUT[0] ;
  assign fetchStage$train_predictors_mispred =
	     coreFix_trainBPQ_1$EMPTY_N ?
	       coreFix_trainBPQ_1$D_OUT[1] :
	       coreFix_trainBPQ_0$D_OUT[1] ;
  assign fetchStage$train_predictors_next_pc =
	     coreFix_trainBPQ_1$EMPTY_N ?
	       coreFix_trainBPQ_1$D_OUT[95:32] :
	       coreFix_trainBPQ_0$D_OUT[95:32] ;
  assign fetchStage$train_predictors_pc =
	     coreFix_trainBPQ_1$EMPTY_N ?
	       coreFix_trainBPQ_1$D_OUT[159:96] :
	       coreFix_trainBPQ_0$D_OUT[159:96] ;
  assign fetchStage$train_predictors_taken =
	     coreFix_trainBPQ_1$EMPTY_N ?
	       coreFix_trainBPQ_1$D_OUT[26] :
	       coreFix_trainBPQ_0$D_OUT[26] ;
  assign fetchStage$EN_pipelines_0_deq =
	     WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
	     fetchStage$pipelines_0_canDeq ||
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     fetchStage$pipelines_0_canDeq &&
	     NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183 &&
	     IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 ||
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
	     WILL_FIRE_RL_renameStage_doRenaming_Trap ;
  assign fetchStage$EN_pipelines_1_deq =
	     WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
	     fetchStage$pipelines_1_canDeq &&
	     !epochManager$checkEpoch_1_check ||
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 &&
	     NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14319 &&
	     IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13999 ;
  assign fetchStage$EN_iTlbIfc_flush = MUX_flush_tlbs$write_1__SEL_1 ;
  assign fetchStage$EN_iTlbIfc_updateVMInfo =
	     MUX_update_vm_info$write_1__SEL_1 ;
  assign fetchStage$EN_iTlbIfc_to_proc_request_put = 1'b0 ;
  assign fetchStage$EN_iTlbIfc_to_proc_response_get = 1'b0 ;
  assign fetchStage$EN_iTlbIfc_toParent_rqToP_deq = WILL_FIRE_RL_sendITlbReq ;
  assign fetchStage$EN_iTlbIfc_toParent_rsFromP_enq =
	     CAN_FIRE_RL_sendRsToITlb ;
  assign fetchStage$EN_iTlbIfc_toParent_flush_request_get =
	     CAN_FIRE_RL_mkConnectionGetPut_1 ;
  assign fetchStage$EN_iTlbIfc_toParent_flush_response_put =
	     CAN_FIRE_RL_sendFlushDone ;
  assign fetchStage$EN_iTlbIfc_perf_setStatus = 1'b0 ;
  assign fetchStage$EN_iTlbIfc_perf_req = 1'b0 ;
  assign fetchStage$EN_iTlbIfc_perf_resp = 1'b0 ;
  assign fetchStage$EN_iMemIfc_to_proc_request_put = 1'b0 ;
  assign fetchStage$EN_iMemIfc_to_proc_response_get = 1'b0 ;
  assign fetchStage$EN_iMemIfc_flush = 1'b0 ;
  assign fetchStage$EN_iMemIfc_perf_setStatus = 1'b0 ;
  assign fetchStage$EN_iMemIfc_perf_req = 1'b0 ;
  assign fetchStage$EN_iMemIfc_perf_resp = 1'b0 ;
  assign fetchStage$EN_iMemIfc_to_parent_rsToP_deq =
	     EN_iCacheToParent_rsToP_deq ;
  assign fetchStage$EN_iMemIfc_to_parent_rqToP_deq =
	     EN_iCacheToParent_rqToP_deq ;
  assign fetchStage$EN_iMemIfc_to_parent_fromP_enq =
	     EN_iCacheToParent_fromP_enq ;
  assign fetchStage$EN_iMemIfc_cRqStuck_get = EN_deadlock_iCacheCRqStuck_get ;
  assign fetchStage$EN_iMemIfc_pRqStuck_get = EN_deadlock_iCachePRqStuck_get ;
  assign fetchStage$EN_mmioIfc_instReq_deq = WILL_FIRE_RL_mmio_sendInstReq ;
  assign fetchStage$EN_mmioIfc_instResp_enq = CAN_FIRE_RL_mmio_sendInstResp ;
  assign fetchStage$EN_mmioIfc_setHtifAddrs = EN_coreReq_start ;
  assign fetchStage$EN_start = EN_coreReq_start ;
  assign fetchStage$EN_stop = 1'b0 ;
  assign fetchStage$EN_setWaitRedirect =
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	     !rob$deqPort_0_deq_data[12] ||
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
	     WILL_FIRE_RL_renameStage_doRenaming_Trap ;
  assign fetchStage$EN_redirect =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_handle ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst ;
  assign fetchStage$EN_done_flushing = CAN_FIRE_RL_readyToFetch ;
  assign fetchStage$EN_train_predictors =
	     coreFix_trainBPQ_1$EMPTY_N ||
	     WILL_FIRE_RL_coreFix_doFetchTrainBP_1 ;
  assign fetchStage$EN_flush_predictors = 1'b0 ;
  assign fetchStage$EN_perf_setStatus = 1'b0 ;
  assign fetchStage$EN_perf_req = 1'b0 ;
  assign fetchStage$EN_perf_resp = 1'b0 ;

  // submodule l2Tlb
  assign l2Tlb$perf_req_r = 4'h0 ;
  assign l2Tlb$perf_setStatus_doStats = 1'b0 ;
  assign l2Tlb$toChildren_rqFromC_put =
	     WILL_FIRE_RL_sendDTlbReq ?
	       MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 :
	       MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2 ;
  assign l2Tlb$toMem_respLd_enq_x = tlbToMem_respLd_enq_x ;
  assign l2Tlb$updateVMInfo_vmD = coreFix_memExe_dTlb$updateVMInfo_vm ;
  assign l2Tlb$updateVMInfo_vmI = fetchStage$iTlbIfc_updateVMInfo_vm ;
  assign l2Tlb$EN_updateVMInfo = MUX_update_vm_info$write_1__SEL_1 ;
  assign l2Tlb$EN_toChildren_rqFromC_put =
	     WILL_FIRE_RL_sendDTlbReq || WILL_FIRE_RL_sendITlbReq ;
  assign l2Tlb$EN_toChildren_rsToC_deq =
	     WILL_FIRE_RL_sendRsToITlb || WILL_FIRE_RL_sendRsToDTlb ;
  assign l2Tlb$EN_toChildren_iTlbReqFlush_put =
	     CAN_FIRE_RL_mkConnectionGetPut_1 ;
  assign l2Tlb$EN_toChildren_dTlbReqFlush_put =
	     CAN_FIRE_RL_mkConnectionGetPut ;
  assign l2Tlb$EN_toChildren_flushDone_get = CAN_FIRE_RL_sendFlushDone ;
  assign l2Tlb$EN_toMem_memReq_deq = EN_tlbToMem_memReq_deq ;
  assign l2Tlb$EN_toMem_respLd_enq = EN_tlbToMem_respLd_enq ;
  assign l2Tlb$EN_perf_setStatus = 1'b0 ;
  assign l2Tlb$EN_perf_req = 1'b0 ;
  assign l2Tlb$EN_perf_resp = 1'b0 ;

  // submodule mmio_cRqQ_clearReq_dummy2_0
  assign mmio_cRqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign mmio_cRqQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule mmio_cRqQ_clearReq_dummy2_1
  assign mmio_cRqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign mmio_cRqQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule mmio_cRqQ_deqReq_dummy2_0
  assign mmio_cRqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_cRqQ_deqReq_dummy2_0$EN = EN_mmioToPlatform_cRq_deq ;

  // submodule mmio_cRqQ_deqReq_dummy2_1
  assign mmio_cRqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_cRqQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_cRqQ_deqReq_dummy2_2
  assign mmio_cRqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_cRqQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_cRqQ_enqReq_dummy2_0
  assign mmio_cRqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_cRqQ_enqReq_dummy2_0$EN =
	     WILL_FIRE_RL_mmio_sendInstReq || WILL_FIRE_RL_mmio_sendDataReq ;

  // submodule mmio_cRqQ_enqReq_dummy2_1
  assign mmio_cRqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_cRqQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_cRqQ_enqReq_dummy2_2
  assign mmio_cRqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_cRqQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_cRsQ_clearReq_dummy2_0
  assign mmio_cRsQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign mmio_cRsQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule mmio_cRsQ_clearReq_dummy2_1
  assign mmio_cRsQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign mmio_cRsQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule mmio_cRsQ_deqReq_dummy2_0
  assign mmio_cRsQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_cRsQ_deqReq_dummy2_0$EN = EN_mmioToPlatform_cRs_deq ;

  // submodule mmio_cRsQ_deqReq_dummy2_1
  assign mmio_cRsQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_cRsQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_cRsQ_deqReq_dummy2_2
  assign mmio_cRsQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_cRsQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_cRsQ_enqReq_dummy2_0
  assign mmio_cRsQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_cRsQ_enqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_handlePRq ;

  // submodule mmio_cRsQ_enqReq_dummy2_1
  assign mmio_cRsQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_cRsQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_cRsQ_enqReq_dummy2_2
  assign mmio_cRsQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_cRsQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_dataPendQ_clearReq_dummy2_0
  assign mmio_dataPendQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign mmio_dataPendQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule mmio_dataPendQ_clearReq_dummy2_1
  assign mmio_dataPendQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign mmio_dataPendQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule mmio_dataPendQ_deqReq_dummy2_0
  assign mmio_dataPendQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_dataPendQ_deqReq_dummy2_0$EN =
	     mmio_dataRespQ_deqReq_lat_0$whas ;

  // submodule mmio_dataPendQ_deqReq_dummy2_1
  assign mmio_dataPendQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_dataPendQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_dataPendQ_deqReq_dummy2_2
  assign mmio_dataPendQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_dataPendQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_dataPendQ_enqReq_dummy2_0
  assign mmio_dataPendQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_dataPendQ_enqReq_dummy2_0$EN =
	     mmio_dataPendQ_enqReq_lat_0$whas ;

  // submodule mmio_dataPendQ_enqReq_dummy2_1
  assign mmio_dataPendQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_dataPendQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_dataPendQ_enqReq_dummy2_2
  assign mmio_dataPendQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_dataPendQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_dataReqQ_clearReq_dummy2_0
  assign mmio_dataReqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign mmio_dataReqQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule mmio_dataReqQ_clearReq_dummy2_1
  assign mmio_dataReqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign mmio_dataReqQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule mmio_dataReqQ_deqReq_dummy2_0
  assign mmio_dataReqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_dataReqQ_deqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_sendDataReq ;

  // submodule mmio_dataReqQ_deqReq_dummy2_1
  assign mmio_dataReqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_dataReqQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_dataReqQ_deqReq_dummy2_2
  assign mmio_dataReqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_dataReqQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_dataReqQ_enqReq_dummy2_0
  assign mmio_dataReqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_dataReqQ_enqReq_dummy2_0$EN = mmio_dataPendQ_enqReq_lat_0$whas ;

  // submodule mmio_dataReqQ_enqReq_dummy2_1
  assign mmio_dataReqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_dataReqQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_dataReqQ_enqReq_dummy2_2
  assign mmio_dataReqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_dataReqQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_dataRespQ_clearReq_dummy2_0
  assign mmio_dataRespQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign mmio_dataRespQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule mmio_dataRespQ_clearReq_dummy2_1
  assign mmio_dataRespQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign mmio_dataRespQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule mmio_dataRespQ_deqReq_dummy2_0
  assign mmio_dataRespQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_dataRespQ_deqReq_dummy2_0$EN =
	     mmio_dataRespQ_deqReq_lat_0$whas ;

  // submodule mmio_dataRespQ_deqReq_dummy2_1
  assign mmio_dataRespQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_dataRespQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_dataRespQ_deqReq_dummy2_2
  assign mmio_dataRespQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_dataRespQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_dataRespQ_enqReq_dummy2_0
  assign mmio_dataRespQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_dataRespQ_enqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_sendDataResp ;

  // submodule mmio_dataRespQ_enqReq_dummy2_1
  assign mmio_dataRespQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_dataRespQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_dataRespQ_enqReq_dummy2_2
  assign mmio_dataRespQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_dataRespQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_pRqQ_clearReq_dummy2_0
  assign mmio_pRqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign mmio_pRqQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule mmio_pRqQ_clearReq_dummy2_1
  assign mmio_pRqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign mmio_pRqQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule mmio_pRqQ_deqReq_dummy2_0
  assign mmio_pRqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_pRqQ_deqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_handlePRq ;

  // submodule mmio_pRqQ_deqReq_dummy2_1
  assign mmio_pRqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_pRqQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_pRqQ_deqReq_dummy2_2
  assign mmio_pRqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_pRqQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_pRqQ_enqReq_dummy2_0
  assign mmio_pRqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_pRqQ_enqReq_dummy2_0$EN = EN_mmioToPlatform_pRq_enq ;

  // submodule mmio_pRqQ_enqReq_dummy2_1
  assign mmio_pRqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_pRqQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_pRqQ_enqReq_dummy2_2
  assign mmio_pRqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_pRqQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_pRsQ_clearReq_dummy2_0
  assign mmio_pRsQ_clearReq_dummy2_0$D_IN = 1'b0 ;
  assign mmio_pRsQ_clearReq_dummy2_0$EN = 1'b0 ;

  // submodule mmio_pRsQ_clearReq_dummy2_1
  assign mmio_pRsQ_clearReq_dummy2_1$D_IN = 1'd1 ;
  assign mmio_pRsQ_clearReq_dummy2_1$EN = 1'd1 ;

  // submodule mmio_pRsQ_deqReq_dummy2_0
  assign mmio_pRsQ_deqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_pRsQ_deqReq_dummy2_0$EN = mmio_pRsQ_deqReq_lat_0$whas ;

  // submodule mmio_pRsQ_deqReq_dummy2_1
  assign mmio_pRsQ_deqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_pRsQ_deqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_pRsQ_deqReq_dummy2_2
  assign mmio_pRsQ_deqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_pRsQ_deqReq_dummy2_2$EN = 1'd1 ;

  // submodule mmio_pRsQ_enqReq_dummy2_0
  assign mmio_pRsQ_enqReq_dummy2_0$D_IN = 1'd1 ;
  assign mmio_pRsQ_enqReq_dummy2_0$EN = EN_mmioToPlatform_pRs_enq ;

  // submodule mmio_pRsQ_enqReq_dummy2_1
  assign mmio_pRsQ_enqReq_dummy2_1$D_IN = 1'b0 ;
  assign mmio_pRsQ_enqReq_dummy2_1$EN = 1'b0 ;

  // submodule mmio_pRsQ_enqReq_dummy2_2
  assign mmio_pRsQ_enqReq_dummy2_2$D_IN = 1'd1 ;
  assign mmio_pRsQ_enqReq_dummy2_2$EN = 1'd1 ;

  // submodule perfReqQ
  assign perfReqQ$D_IN = { coreReq_perfReq_loc, coreReq_perfReq_t } ;
  assign perfReqQ$ENQ = EN_coreReq_perfReq ;
  assign perfReqQ$DEQ = EN_coreIndInv_perfResp ;
  assign perfReqQ$CLR = 1'b0 ;

  // submodule regRenamingTable
  assign regRenamingTable$rename_0_claimRename_r =
	     fetchStage$pipelines_0_first[95:69] ;
  assign regRenamingTable$rename_0_claimRename_sb =
	     specTagManager$currentSpecBits ;
  assign regRenamingTable$rename_0_getRename_r =
	     fetchStage$pipelines_0_first[95:69] ;
  assign regRenamingTable$rename_1_claimRename_r =
	     fetchStage$pipelines_1_first[95:69] ;
  assign regRenamingTable$rename_1_claimRename_sb =
	     renaming_spec_bits__h690496 ;
  assign regRenamingTable$rename_1_getRename_r =
	     fetchStage$pipelines_1_first[95:69] ;
  assign regRenamingTable$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign regRenamingTable$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign regRenamingTable$EN_rename_0_claimRename =
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     fetchStage$pipelines_0_canDeq &&
	     NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183 &&
	     IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 ||
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
  assign regRenamingTable$EN_rename_1_claimRename =
	     MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
  assign regRenamingTable$EN_commit_0_commit =
	     WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	     rob$deqPort_0_canDeq ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst ;
  assign regRenamingTable$EN_commit_1_commit =
	     WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	     rob$deqPort_1_canDeq &&
	     rob$deqPort_1_deq_data[25] &&
	     !rob$deqPort_1_deq_data[18] &&
	     !rob$deqPort_1_deq_data[167] &&
	     rob$deqPort_1_deq_data[257:253] != 5'd0 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd21 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd17 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd18 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd13 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd16 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd15 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd19 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd20 ;
  assign regRenamingTable$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign regRenamingTable$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule rf
  assign rf$read_0_rd1_rindx = coreFix_aluExe_0_dispToRegQ$first[84:78] ;
  assign rf$read_0_rd2_rindx = coreFix_aluExe_0_dispToRegQ$first[76:70] ;
  assign rf$read_0_rd3_rindx = 7'h0 ;
  assign rf$read_1_rd1_rindx = coreFix_aluExe_1_dispToRegQ$first[84:78] ;
  assign rf$read_1_rd2_rindx = coreFix_aluExe_1_dispToRegQ$first[76:70] ;
  assign rf$read_1_rd3_rindx = 7'h0 ;
  assign rf$read_2_rd1_rindx =
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
  assign rf$read_2_rd2_rindx =
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
  assign rf$read_2_rd3_rindx =
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
  assign rf$read_3_rd1_rindx = coreFix_memExe_dispToRegQ$first[61:55] ;
  assign rf$read_3_rd2_rindx = coreFix_memExe_dispToRegQ$first[53:47] ;
  assign rf$read_3_rd3_rindx = 7'h0 ;
  assign rf$read_4_rd1_rindx = 7'h0 ;
  assign rf$read_4_rd2_rindx = 7'h0 ;
  assign rf$read_4_rd3_rindx = 7'h0 ;
  assign rf$write_0_wr_data = coreFix_aluExe_0_exeToFinQ$first[275:212] ;
  assign rf$write_0_wr_rindx = coreFix_aluExe_0_exeToFinQ$first[320:314] ;
  assign rf$write_1_wr_data = coreFix_aluExe_1_exeToFinQ$first[275:212] ;
  assign rf$write_1_wr_rindx = coreFix_aluExe_1_exeToFinQ$first[320:314] ;
  always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
	  coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
	  MUX_rf$write_2_wr_2__VAL_2 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
	  MUX_rf$write_2_wr_2__VAL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
	  MUX_rf$write_2_wr_2__VAL_4 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
	  MUX_rf$write_2_wr_2__VAL_5 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
	  MUX_rf$write_2_wr_2__VAL_6)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
	  rf$write_2_wr_data =
	      coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
	  rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_2;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
	  rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_3;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
	  rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_4;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
	  rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_5;
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
	  rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_6;
      default: rf$write_2_wr_data =
		   64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
	  coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
	  coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
	  coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
	  coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
	  coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
	  coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
	  rf$write_2_wr_rindx =
	      coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
	  rf$write_2_wr_rindx =
	      coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
	  rf$write_2_wr_rindx =
	      coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
	  rf$write_2_wr_rindx =
	      coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
	  rf$write_2_wr_rindx =
	      coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
	  rf$write_2_wr_rindx =
	      coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25];
      default: rf$write_2_wr_rindx = 7'b0101010 /* unspecified value */ ;
    endcase
  end
  always@(MUX_rf$write_3_wr_2__SEL_1 or
	  coreFix_memExe_lsq$respLd or
	  MUX_rf$write_3_wr_1__SEL_2 or
	  coreFix_memExe_respLrScAmoQ_data_0 or
	  MUX_rf$write_3_wr_1__SEL_3 or
	  mmio_dataRespQ_data_0 or
	  MUX_rf$write_3_wr_1__SEL_4 or
	  MUX_rf$write_3_wr_2__VAL_4 or
	  MUX_rf$write_3_wr_1__SEL_5 or MUX_rf$write_3_wr_2__VAL_5)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_rf$write_3_wr_2__SEL_1:
	  rf$write_3_wr_data = coreFix_memExe_lsq$respLd[63:0];
      MUX_rf$write_3_wr_1__SEL_2:
	  rf$write_3_wr_data = coreFix_memExe_respLrScAmoQ_data_0;
      MUX_rf$write_3_wr_1__SEL_3:
	  rf$write_3_wr_data = mmio_dataRespQ_data_0[63:0];
      MUX_rf$write_3_wr_1__SEL_4:
	  rf$write_3_wr_data = MUX_rf$write_3_wr_2__VAL_4;
      MUX_rf$write_3_wr_1__SEL_5:
	  rf$write_3_wr_data = MUX_rf$write_3_wr_2__VAL_5;
      default: rf$write_3_wr_data =
		   64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  always@(MUX_rf$write_3_wr_1__SEL_1 or
	  coreFix_memExe_lsq$respLd or
	  MUX_rf$write_3_wr_1__SEL_4 or
	  MUX_rf$write_3_wr_1__SEL_5 or
	  coreFix_memExe_lsq$firstLd or
	  MUX_rf$write_3_wr_1__SEL_2 or
	  MUX_rf$write_3_wr_1__SEL_3 or coreFix_memExe_lsq$firstSt)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_rf$write_3_wr_1__SEL_1:
	  rf$write_3_wr_rindx = coreFix_memExe_lsq$respLd[71:65];
      MUX_rf$write_3_wr_1__SEL_4 || MUX_rf$write_3_wr_1__SEL_5:
	  rf$write_3_wr_rindx = coreFix_memExe_lsq$firstLd[88:82];
      MUX_rf$write_3_wr_1__SEL_2 || MUX_rf$write_3_wr_1__SEL_3:
	  rf$write_3_wr_rindx = coreFix_memExe_lsq$firstSt[149:143];
      default: rf$write_3_wr_rindx = 7'b0101010 /* unspecified value */ ;
    endcase
  end
  assign rf$write_4_wr_data = 64'h0 ;
  assign rf$write_4_wr_rindx = 7'h0 ;
  assign rf$EN_write_0_wr =
	     _dor1rf$EN_write_0_wr && coreFix_aluExe_0_exeToFinQ$first[321] ;
  assign rf$EN_write_1_wr =
	     _dor1rf$EN_write_1_wr && coreFix_aluExe_1_exeToFinQ$first[321] ;
  assign rf$EN_write_2_wr =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
  assign rf$EN_write_3_wr =
	     (WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
	      WILL_FIRE_RL_coreFix_memExe_doRespLdMem) &&
	     coreFix_memExe_lsq$respLd[72] ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
	     coreFix_memExe_lsq$firstSt[150] ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
	     coreFix_memExe_lsq$firstSt[150] ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	     coreFix_memExe_lsq$firstLd[89] ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	     coreFix_memExe_lsq$firstLd[89] ;
  assign rf$EN_write_4_wr = 1'b0 ;

  // submodule rob
  always@(MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 or
	  MUX_rob$enqPort_0_enq_1__VAL_1 or
	  WILL_FIRE_RL_renameStage_doRenaming_Trap or
	  MUX_rob$enqPort_0_enq_1__VAL_2 or
	  WILL_FIRE_RL_renameStage_doRenaming_SystemInst or
	  MUX_rob$enqPort_0_enq_1__VAL_3)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2:
	  rob$enqPort_0_enq_x = MUX_rob$enqPort_0_enq_1__VAL_1;
      WILL_FIRE_RL_renameStage_doRenaming_Trap:
	  rob$enqPort_0_enq_x = MUX_rob$enqPort_0_enq_1__VAL_2;
      WILL_FIRE_RL_renameStage_doRenaming_SystemInst:
	  rob$enqPort_0_enq_x = MUX_rob$enqPort_0_enq_1__VAL_3;
      default: rob$enqPort_0_enq_x =
		   354'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign rob$enqPort_1_enq_x =
	     { fetchStage$pipelines_1_first[387:324],
	       fetchStage$pipelines_1_first[127:96],
	       fetchStage$pipelines_1_first[199:195],
	       fetchStage$pipelines_1_first[75:69],
	       64'hAAAAAAAAAAAAAAAA,
	       fetchStage_pipelines_1_first__2937_BIT_173_370_ETC___d13785,
	       73'h1280000000000000000,
	       fetchStage$pipelines_1_first[323:260],
	       5'd0,
	       fetchStage$pipelines_1_first[75] &&
	       fetchStage$pipelines_1_first[74],
	       fetchStage$pipelines_1_first[194:192] != 3'd0 &&
	       fetchStage$pipelines_1_first[194:192] != 3'd1 &&
	       fetchStage$pipelines_1_first[194:192] != 3'd2 &&
	       fetchStage$pipelines_1_first[194:192] != 3'd3 &&
	       fetchStage$pipelines_1_first[194:192] != 3'd4,
	       fetchStage$pipelines_1_first[194:192] != 3'd2 ||
	       fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14441 ||
	       IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14392,
	       IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14451,
	       7'd32,
	       renaming_spec_bits__h690496 } ;
  assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ;
  assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ;
  assign rob$getOrigPC_2_get_x = 12'h0 ;
  assign rob$getOrigPredPC_0_get_x =
	     coreFix_aluExe_0_dispToRegQ$first[52:41] ;
  assign rob$getOrigPredPC_1_get_x =
	     coreFix_aluExe_1_dispToRegQ$first[52:41] ;
  assign rob$getOrig_Inst_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ;
  assign rob$getOrig_Inst_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ;
  always@(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or
	  MUX_rob$setExecuted_deqLSQ_2__VAL_2 or
	  WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or
	  MUX_rob$setExecuted_deqLSQ_2__VAL_6 or
	  MUX_rob$setExecuted_deqLSQ_1__SEL_1 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 or
	  WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem or
	  WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault or
	  WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault:
	  rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_2;
      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault:
	  rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_6;
      MUX_rob$setExecuted_deqLSQ_1__SEL_1 ||
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 ||
      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem:
	  rob$setExecuted_deqLSQ_cause = 5'd10;
      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault:
	  rob$setExecuted_deqLSQ_cause = 5'd21;
      WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault:
	  rob$setExecuted_deqLSQ_cause = 5'd23;
      default: rob$setExecuted_deqLSQ_cause =
		   5'b01010 /* unspecified value */ ;
    endcase
  end
  assign rob$setExecuted_deqLSQ_ld_killed =
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ?
	       coreFix_memExe_lsq$firstLd[2:0] :
	       3'd2 ;
  assign rob$setExecuted_deqLSQ_x =
	     (MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) ?
	       coreFix_memExe_lsq$firstLd[113:102] :
	       coreFix_memExe_lsq$firstSt[170:159] ;
  assign rob$setExecuted_doFinishAlu_0_set_cf =
	     coreFix_aluExe_0_exeToFinQ$first[146:17] ;
  assign rob$setExecuted_doFinishAlu_0_set_csrData =
	     coreFix_aluExe_0_exeToFinQ$first[211:147] ;
  assign rob$setExecuted_doFinishAlu_0_set_dst_data =
	     coreFix_aluExe_0_exeToFinQ$first[275:212] ;
  assign rob$setExecuted_doFinishAlu_0_set_x =
	     coreFix_aluExe_0_exeToFinQ$first[312:301] ;
  assign rob$setExecuted_doFinishAlu_1_set_cf =
	     coreFix_aluExe_1_exeToFinQ$first[146:17] ;
  assign rob$setExecuted_doFinishAlu_1_set_csrData =
	     coreFix_aluExe_1_exeToFinQ$first[211:147] ;
  assign rob$setExecuted_doFinishAlu_1_set_dst_data =
	     coreFix_aluExe_1_exeToFinQ$first[275:212] ;
  assign rob$setExecuted_doFinishAlu_1_set_x =
	     coreFix_aluExe_1_exeToFinQ$first[312:301] ;
  always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or
	  coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or
	  MUX_rf$write_2_wr_2__VAL_2 or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or
	  MUX_rf$write_2_wr_2__VAL_3 or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or
	  MUX_rf$write_2_wr_2__VAL_4 or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or
	  MUX_rf$write_2_wr_2__VAL_5 or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or
	  MUX_rf$write_2_wr_2__VAL_6)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
	      coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38];
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
	      MUX_rf$write_2_wr_2__VAL_2;
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
	      MUX_rf$write_2_wr_2__VAL_3;
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
	      MUX_rf$write_2_wr_2__VAL_4;
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
	      MUX_rf$write_2_wr_2__VAL_5;
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
	      MUX_rf$write_2_wr_2__VAL_6;
      default: rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
		   64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or
	  coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or
	  MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or
	  MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or
	  MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
	      coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[37:33];
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
	      MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2;
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
	      MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3;
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
	      MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4;
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ||
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_fflags = 5'd0;
      default: rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
		   5'b01010 /* unspecified value */ ;
    endcase
  end
  always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or
	  coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or
	  coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or
	  coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or
	  coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or
	  coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or
	  WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or
	  coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_x =
	      coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[23:12];
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_x =
	      coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[23:12];
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_x =
	      coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[23:12];
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_x =
	      coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[23:12];
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_x =
	      coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[23:12];
      WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv:
	  rob$setExecuted_doFinishFpuMulDiv_0_set_x =
	      coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[23:12];
      default: rob$setExecuted_doFinishFpuMulDiv_0_set_x =
		   12'b101010101010 /* unspecified value */ ;
    endcase
  end
  assign rob$setExecuted_doFinishMem_access_at_commit =
	     IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1768 &&
	     (coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1759 ||
	      coreFix_memExe_dTlb$procResp[105:103] == 3'd2 ||
	      coreFix_memExe_dTlb$procResp[105:103] == 3'd3 ||
	      coreFix_memExe_dTlb$procResp[105:103] == 3'd4) ;
  assign rob$setExecuted_doFinishMem_non_mmio_st_done =
	     IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1768 &&
	     NOT_coreFix_memExe_dTlb_procResp__740_BITS_174_ETC___d1779 &&
	     coreFix_memExe_dTlb$procResp[105:103] == 3'd1 ;
  assign rob$setExecuted_doFinishMem_store_data =
	     64'hAAAAAAAAAAAAAAAA /* unspecified value */  ;
  assign rob$setExecuted_doFinishMem_store_data_BE =
	     8'b10101010 /* unspecified value */  ;
  assign rob$setExecuted_doFinishMem_vaddr =
	     coreFix_memExe_dTlb$procResp[76:13] ;
  assign rob$setExecuted_doFinishMem_x =
	     coreFix_memExe_dTlb$procResp[102:91] ;
  assign rob$setLSQAtCommitNotified_x = rob$deqPort_0_getDeqInstTag ;
  assign rob$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  rob$specUpdate_incorrectSpeculation_inst_tag =
	      coreFix_aluExe_1_exeToFinQ$first[312:301];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  rob$specUpdate_incorrectSpeculation_inst_tag =
	      coreFix_aluExe_0_exeToFinQ$first[312:301];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  rob$specUpdate_incorrectSpeculation_inst_tag =
	      12'b101010101010 /* unspecified value */ ;
      default: rob$specUpdate_incorrectSpeculation_inst_tag =
		   12'b101010101010 /* unspecified value */ ;
    endcase
  end
  assign rob$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  rob$specUpdate_incorrectSpeculation_spec_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  rob$specUpdate_incorrectSpeculation_spec_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  rob$specUpdate_incorrectSpeculation_spec_tag =
	      4'b1010 /* unspecified value */ ;
      default: rob$specUpdate_incorrectSpeculation_spec_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign rob$EN_enqPort_0_enq =
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     fetchStage$pipelines_0_canDeq &&
	     NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183 &&
	     IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 ||
	     WILL_FIRE_RL_renameStage_doRenaming_Trap ||
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
  assign rob$EN_enqPort_1_enq =
	     MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
  assign rob$EN_deqPort_0_deq =
	     WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	     rob$deqPort_0_canDeq ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ||
	     WILL_FIRE_RL_commitStage_doCommitSystemInst ;
  assign rob$EN_deqPort_1_deq =
	     WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	     rob$deqPort_1_canDeq &&
	     rob$deqPort_1_deq_data[25] &&
	     !rob$deqPort_1_deq_data[18] &&
	     !rob$deqPort_1_deq_data[167] &&
	     rob$deqPort_1_deq_data[257:253] != 5'd0 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd21 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd17 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd18 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd13 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd16 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd15 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd19 &&
	     rob$deqPort_1_deq_data[257:253] != 5'd20 ;
  assign rob$EN_setLSQAtCommitNotified =
	     CAN_FIRE_RL_commitStage_notifyLSQCommit ;
  assign rob$EN_setExecuted_deqLSQ =
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ||
	     WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ;
  assign rob$EN_setExecuted_doFinishAlu_0_set =
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
  assign rob$EN_setExecuted_doFinishAlu_1_set =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
  assign rob$EN_setExecuted_doFinishFpuMulDiv_0_set =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv ;
  assign rob$EN_setExecuted_doFinishMem =
	     CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
  assign rob$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign rob$EN_specUpdate_correctSpeculation = 1'd1 ;

  // submodule sbAggr
  assign sbAggr$eagerLookup_0_get_r = regRenamingTable$rename_0_getRename ;
  assign sbAggr$eagerLookup_1_get_r = regRenamingTable$rename_1_getRename ;
  assign sbAggr$setBusy_0_set_dst = regRenamingTable$rename_0_getRename[8:0] ;
  assign sbAggr$setBusy_1_set_dst = regRenamingTable$rename_1_getRename[8:0] ;
  assign sbAggr$setReady_0_put = coreFix_aluExe_0_rsAlu$dispatchData[40:34] ;
  assign sbAggr$setReady_1_put = coreFix_aluExe_1_rsAlu$dispatchData[40:34] ;
  always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
	  coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
	  coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
	  coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
	  coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
	  coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
	  coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
	  sbAggr$setReady_2_put =
	      coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
	  sbAggr$setReady_2_put =
	      coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
	  sbAggr$setReady_2_put =
	      coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
	  sbAggr$setReady_2_put =
	      coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
	  sbAggr$setReady_2_put =
	      coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
	  sbAggr$setReady_2_put =
	      coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25];
      default: sbAggr$setReady_2_put = 7'b0101010 /* unspecified value */ ;
    endcase
  end
  assign sbAggr$setReady_3_put = coreFix_memExe_lsq$issueLd[71:65] ;
  always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4 or
	  coreFix_memExe_lsq$getHit or
	  MUX_sbAggr$setReady_4_put_1__SEL_2 or
	  coreFix_memExe_lsq$firstLd or
	  MUX_sbAggr$setReady_4_put_1__SEL_1 or coreFix_memExe_lsq$firstSt)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 ||
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
	  sbAggr$setReady_4_put = coreFix_memExe_lsq$getHit[7:1];
      MUX_sbAggr$setReady_4_put_1__SEL_2:
	  sbAggr$setReady_4_put = coreFix_memExe_lsq$firstLd[88:82];
      MUX_sbAggr$setReady_4_put_1__SEL_1:
	  sbAggr$setReady_4_put = coreFix_memExe_lsq$firstSt[149:143];
      default: sbAggr$setReady_4_put = 7'b0101010 /* unspecified value */ ;
    endcase
  end
  assign sbAggr$EN_setBusy_0_set =
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     fetchStage$pipelines_0_canDeq &&
	     NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183 &&
	     IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 ||
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
  assign sbAggr$EN_setBusy_1_set =
	     MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
  assign sbAggr$EN_setReady_0_put =
	     WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
	     coreFix_aluExe_0_rsAlu$dispatchData[41] ;
  assign sbAggr$EN_setReady_1_put =
	     WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
	     coreFix_aluExe_1_rsAlu$dispatchData[41] ;
  assign sbAggr$EN_setReady_2_put =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
  assign sbAggr$EN_setReady_3_put =
	     _dor1sbAggr$EN_setReady_3_put &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
	     coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
	     coreFix_memExe_lsq$issueLd[72] ;
  assign sbAggr$EN_setReady_4_put =
	     (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
	     coreFix_memExe_lsq$firstSt[150] ||
	     (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
	     coreFix_memExe_lsq$firstLd[89] ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2650 ||
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 &&
	     coreFix_memExe_lsq$getHit[8] &&
	     !coreFix_memExe_lsq$getHit[9] ;

  // submodule sbCons
  assign sbCons$eagerLookup_0_get_r = 33'h0 ;
  assign sbCons$eagerLookup_1_get_r = 33'h0 ;
  assign sbCons$lazyLookup_0_get_r =
	     coreFix_aluExe_0_dispToRegQ$first[85:53] ;
  assign sbCons$lazyLookup_1_get_r =
	     coreFix_aluExe_1_dispToRegQ$first[85:53] ;
  assign sbCons$lazyLookup_2_get_r =
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[56:24] ;
  assign sbCons$lazyLookup_3_get_r = coreFix_memExe_dispToRegQ$first[62:30] ;
  assign sbCons$lazyLookup_4_get_r = 33'h0 ;
  assign sbCons$setBusy_0_set_dst = regRenamingTable$rename_0_getRename[8:0] ;
  assign sbCons$setBusy_1_set_dst = regRenamingTable$rename_1_getRename[8:0] ;
  assign sbCons$setReady_0_put = coreFix_aluExe_0_exeToFinQ$first[320:314] ;
  assign sbCons$setReady_1_put = coreFix_aluExe_1_exeToFinQ$first[320:314] ;
  always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
	  coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
	  coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
	  coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
	  coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
	  coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or
	  MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
	  coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
	  sbCons$setReady_2_put =
	      coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
	  sbCons$setReady_2_put =
	      coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
	  sbCons$setReady_2_put =
	      coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
	  sbCons$setReady_2_put =
	      coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
	  sbCons$setReady_2_put =
	      coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25];
      MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
	  sbCons$setReady_2_put =
	      coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25];
      default: sbCons$setReady_2_put = 7'b0101010 /* unspecified value */ ;
    endcase
  end
  always@(MUX_sbCons$setReady_3_put_1__SEL_1 or
	  coreFix_memExe_lsq$respLd or
	  MUX_sbCons$setReady_3_put_1__SEL_2 or
	  coreFix_memExe_lsq$firstSt or
	  MUX_sbCons$setReady_3_put_1__SEL_3 or coreFix_memExe_lsq$firstLd)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_sbCons$setReady_3_put_1__SEL_1:
	  sbCons$setReady_3_put = coreFix_memExe_lsq$respLd[71:65];
      MUX_sbCons$setReady_3_put_1__SEL_2:
	  sbCons$setReady_3_put = coreFix_memExe_lsq$firstSt[149:143];
      MUX_sbCons$setReady_3_put_1__SEL_3:
	  sbCons$setReady_3_put = coreFix_memExe_lsq$firstLd[88:82];
      default: sbCons$setReady_3_put = 7'b0101010 /* unspecified value */ ;
    endcase
  end
  assign sbCons$setReady_4_put = 7'h0 ;
  assign sbCons$EN_setBusy_0_set =
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     fetchStage$pipelines_0_canDeq &&
	     NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183 &&
	     IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 ||
	     WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
  assign sbCons$EN_setBusy_1_set =
	     MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
  assign sbCons$EN_setReady_0_put =
	     _dor1sbCons$EN_setReady_0_put &&
	     coreFix_aluExe_0_exeToFinQ$first[321] ;
  assign sbCons$EN_setReady_1_put =
	     _dor1sbCons$EN_setReady_1_put &&
	     coreFix_aluExe_1_exeToFinQ$first[321] ;
  assign sbCons$EN_setReady_2_put =
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
	     coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
	     WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
  assign sbCons$EN_setReady_3_put =
	     (WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
	      WILL_FIRE_RL_coreFix_memExe_doRespLdMem) &&
	     coreFix_memExe_lsq$respLd[72] ||
	     (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
	     coreFix_memExe_lsq$firstSt[150] ||
	     (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
	      WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
	     coreFix_memExe_lsq$firstLd[89] ;
  assign sbCons$EN_setReady_4_put = 1'b0 ;

  // submodule specTagManager
  assign specTagManager$specUpdate_correctSpeculation_mask =
	     IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 ;
  assign specTagManager$specUpdate_incorrectSpeculation_kill_all =
	     coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
  always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
	  coreFix_aluExe_1_exeToFinQ$first or
	  WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
	  coreFix_aluExe_0_exeToFinQ$first or
	  MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
	  specTagManager$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_1_exeToFinQ$first[15:12];
      WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
	  specTagManager$specUpdate_incorrectSpeculation_kill_tag =
	      coreFix_aluExe_0_exeToFinQ$first[15:12];
      MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
	  specTagManager$specUpdate_incorrectSpeculation_kill_tag =
	      4'b1010 /* unspecified value */ ;
      default: specTagManager$specUpdate_incorrectSpeculation_kill_tag =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign specTagManager$EN_claimSpecTag =
	     WILL_FIRE_RL_renameStage_doRenaming &&
	     (fetchStage_pipelines_0_canDeq__2926_AND_specTa_ETC___d14269 ||
	      NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 &&
	      NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14430) ;
  assign specTagManager$EN_specUpdate_incorrectSpeculation =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
	     WILL_FIRE_RL_commitStage_doCommitKilledLd ||
	     WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
  assign specTagManager$EN_specUpdate_correctSpeculation = 1'd1 ;

  // remaining internal signals
  module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]),
				    .amoExec_current_data(curData__h195304),
				    .amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]),
				    .amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]),
				    .amoExec(n__h196842));
  module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32],
							3'd0 }),
				    .amoExec_current_data({ 63'd0,
							    r__h620919 }),
				    .amoExec_in_data({ 32'd0, x__h75785 }),
				    .amoExec_upper_32_bits(1'd0),
				    .amoExec(amoExec___d882));
  module_basicExec instance_basicExec_6(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[421:417],
							   CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220,
							   { coreFix_aluExe_1_regToExeQ$first[395],
							     CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221,
							     coreFix_aluExe_1_regToExeQ$first[382],
							     coreFix_aluExe_1_regToExeQ$first[381:350] } }),
					.basicExec_rVal1(coreFix_aluExe_1_regToExeQ$first[304:241]),
					.basicExec_rVal2(coreFix_aluExe_1_regToExeQ$first[240:177]),
					.basicExec_pc(coreFix_aluExe_1_regToExeQ$first[176:113]),
					.basicExec_ppc(coreFix_aluExe_1_regToExeQ$first[112:49]),
					.basicExec_orig_inst(coreFix_aluExe_1_regToExeQ$first[48:17]),
					.basicExec(basicExec___d12101));
  module_basicExec instance_basicExec_5(.basicExec_dInst({ coreFix_aluExe_0_regToExeQ$first[421:417],
							   CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223,
							   { coreFix_aluExe_0_regToExeQ$first[395],
							     CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q224,
							     coreFix_aluExe_0_regToExeQ$first[382],
							     coreFix_aluExe_0_regToExeQ$first[381:350] } }),
					.basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[304:241]),
					.basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[240:177]),
					.basicExec_pc(coreFix_aluExe_0_regToExeQ$first[176:113]),
					.basicExec_ppc(coreFix_aluExe_0_regToExeQ$first[112:49]),
					.basicExec_orig_inst(coreFix_aluExe_0_regToExeQ$first[48:17]),
					.basicExec(basicExec___d12775));
  module_checkForException instance_checkForException_0(.checkForException_dInst({ fetchStage$pipelines_0_first[199:195],
										   IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043,
										   { { fetchStage$pipelines_0_first[173],
										       IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125 },
										     fetchStage$pipelines_0_first[160],
										     x_data_imm__h682377 } }),
							.checkForException_regs({ fetchStage$pipelines_0_first[95],
										  fetchStage$pipelines_0_first[94:89],
										  { fetchStage$pipelines_0_first[88],
										    fetchStage$pipelines_0_first[87:82] },
										  { fetchStage$pipelines_0_first[81],
										    fetchStage$pipelines_0_first[80:76],
										    { fetchStage$pipelines_0_first[75],
										      fetchStage$pipelines_0_first[74:69] } } }),
							.checkForException_csrState({ x_decodeInfo_frm__h661528,
										      r1__read_BITS_13_TO_12___h661713 !=
										      2'd0,
										      { prv__h724902,
											csrf_tvm_reg,
											{ r1__read_BIT_20___h662377,
											  csrf_tsr_reg,
											  { csrf_mcounteren_cy_reg,
											    csrf_mcounteren_cy_reg &&
											    csrf_scounteren_cy_reg,
											    { csrf_mcounteren_ir_reg,
											      csrf_mcounteren_ir_reg &&
											      csrf_scounteren_ir_reg,
											      { csrf_mcounteren_tm_reg,
												csrf_mcounteren_tm_reg &&
												csrf_scounteren_tm_reg } } } } } }),
							.checkForException(checkForException___d13160));
  module_checkForException instance_checkForException_1(.checkForException_dInst({ fetchStage$pipelines_1_first[199:195],
										   IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13701,
										   { fetchStage_pipelines_1_first__2937_BIT_173_370_ETC___d13785,
										     fetchStage$pipelines_1_first[160],
										     x_data_imm__h698281 } }),
							.checkForException_regs({ fetchStage$pipelines_1_first[95],
										  fetchStage$pipelines_1_first[94:89],
										  { fetchStage$pipelines_1_first[88],
										    fetchStage$pipelines_1_first[87:82] },
										  { fetchStage$pipelines_1_first[81],
										    fetchStage$pipelines_1_first[80:76],
										    { fetchStage$pipelines_1_first[75],
										      fetchStage$pipelines_1_first[74:69] } } }),
							.checkForException_csrState({ x_decodeInfo_frm__h661528,
										      r1__read_BITS_13_TO_12___h661713 !=
										      2'd0,
										      { prv__h724902,
											csrf_tvm_reg,
											{ r1__read_BIT_20___h662377,
											  csrf_tsr_reg,
											  { csrf_mcounteren_cy_reg,
											    csrf_mcounteren_cy_reg &&
											    csrf_scounteren_cy_reg,
											    { csrf_mcounteren_ir_reg,
											      csrf_mcounteren_ir_reg &&
											      csrf_scounteren_ir_reg,
											      { csrf_mcounteren_tm_reg,
												csrf_mcounteren_tm_reg &&
												csrf_scounteren_tm_reg } } } } } }),
							.checkForException(checkForException___d13807));
  module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229],
									  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242,
									  coreFix_fpuMulDivExe_0_regToExeQ$first[225] }),
						.execFpuSimple_rVal1(rVal1__h487144),
						.execFpuSimple_rVal2(rVal2__h487145),
						.execFpuSimple(execFpuSimple___d11167));
  assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21 =
	     _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4345 ?
	       _theResult___snd__h358911 :
	       _theResult____h350737 ;
  assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q56 =
	     _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5737 ?
	       _theResult___snd__h404608 :
	       _theResult____h396436 ;
  assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q91 =
	     _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7129 ?
	       _theResult___snd__h450303 :
	       _theResult____h442131 ;
  assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q130 =
	     _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9008 ?
	       _theResult___snd__h516556 :
	       _theResult____h508257 ;
  assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q147 =
	     _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9723 ?
	       _theResult___snd__h594713 :
	       _theResult____h586414 ;
  assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q170 =
	     _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10493 ?
	       _theResult___snd__h555409 :
	       _theResult____h547110 ;
  assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q101 =
	     _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7680 ?
	       _theResult___snd__h468069 :
	       _theResult____h459768 ;
  assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q31 =
	     _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4896 ?
	       _theResult___snd__h376677 :
	       _theResult____h368376 ;
  assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q66 =
	     _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6288 ?
	       _theResult___snd__h422374 :
	       _theResult____h414073 ;
  assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q126 =
	     _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8696 ?
	       _theResult___snd__h506905 :
	       57'd0 ;
  assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q133 =
	     _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9058 ?
	       _theResult___snd__h506905 :
	       _theResult___snd__h525310 ;
  assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q143 =
	     _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9426 ?
	       _theResult___snd__h585062 :
	       57'd0 ;
  assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q150 =
	     _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9773 ?
	       _theResult___snd__h585062 :
	       _theResult___snd__h603467 ;
  assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q166 =
	     _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10196 ?
	       _theResult___snd__h545758 :
	       57'd0 ;
  assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q173 =
	     _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10543 ?
	       _theResult___snd__h545758 :
	       _theResult___snd__h564163 ;
  assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q106 =
	     _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7753 ?
	       _theResult___snd__h458885 :
	       _theResult___snd__h476675 ;
  assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q23 =
	     _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4576 ?
	       _theResult___snd__h367493 :
	       57'd0 ;
  assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q36 =
	     _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4969 ?
	       _theResult___snd__h367493 :
	       _theResult___snd__h385283 ;
  assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q58 =
	     _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5968 ?
	       _theResult___snd__h413190 :
	       57'd0 ;
  assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q71 =
	     _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6361 ?
	       _theResult___snd__h413190 :
	       _theResult___snd__h430980 ;
  assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q93 =
	     _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7360 ?
	       _theResult___snd__h458885 :
	       57'd0 ;
  assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5165 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ?
	       ((_theResult___fst_exp__h358848 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150) :
	       ((_theResult___fst_exp__h367504 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163) ;
  assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5215 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ?
	       ((_theResult___fst_exp__h358848 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206) :
	       ((_theResult___fst_exp__h367504 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213) ;
  assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6557 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ?
	       ((_theResult___fst_exp__h404545 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542) :
	       ((_theResult___fst_exp__h413201 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555) ;
  assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6607 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ?
	       ((_theResult___fst_exp__h404545 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598) :
	       ((_theResult___fst_exp__h413201 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605) ;
  assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7949 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ?
	       ((_theResult___fst_exp__h450240 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934) :
	       ((_theResult___fst_exp__h458896 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947) ;
  assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7999 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ?
	       ((_theResult___fst_exp__h450240 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990) :
	       ((_theResult___fst_exp__h458896 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997) ;
  assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343 =
	     (_theResult____h350737[56] ?
		6'd0 :
		(_theResult____h350737[55] ?
		   6'd1 :
		   (_theResult____h350737[54] ?
		      6'd2 :
		      (_theResult____h350737[53] ?
			 6'd3 :
			 (_theResult____h350737[52] ?
			    6'd4 :
			    (_theResult____h350737[51] ?
			       6'd5 :
			       (_theResult____h350737[50] ?
				  6'd6 :
				  (_theResult____h350737[49] ?
				     6'd7 :
				     (_theResult____h350737[48] ?
					6'd8 :
					(_theResult____h350737[47] ?
					   6'd9 :
					   (_theResult____h350737[46] ?
					      6'd10 :
					      (_theResult____h350737[45] ?
						 6'd11 :
						 (_theResult____h350737[44] ?
						    6'd12 :
						    (_theResult____h350737[43] ?
						       6'd13 :
						       (_theResult____h350737[42] ?
							  6'd14 :
							  (_theResult____h350737[41] ?
							     6'd15 :
							     (_theResult____h350737[40] ?
								6'd16 :
								(_theResult____h350737[39] ?
								   6'd17 :
								   (_theResult____h350737[38] ?
								      6'd18 :
								      (_theResult____h350737[37] ?
									 6'd19 :
									 (_theResult____h350737[36] ?
									    6'd20 :
									    (_theResult____h350737[35] ?
									       6'd21 :
									       (_theResult____h350737[34] ?
										  6'd22 :
										  (_theResult____h350737[33] ?
										     6'd23 :
										     (_theResult____h350737[32] ?
											6'd24 :
											(_theResult____h350737[31] ?
											   6'd25 :
											   (_theResult____h350737[30] ?
											      6'd26 :
											      (_theResult____h350737[29] ?
												 6'd27 :
												 (_theResult____h350737[28] ?
												    6'd28 :
												    (_theResult____h350737[27] ?
												       6'd29 :
												       (_theResult____h350737[26] ?
													  6'd30 :
													  (_theResult____h350737[25] ?
													     6'd31 :
													     (_theResult____h350737[24] ?
														6'd32 :
														(_theResult____h350737[23] ?
														   6'd33 :
														   (_theResult____h350737[22] ?
														      6'd34 :
														      (_theResult____h350737[21] ?
															 6'd35 :
															 (_theResult____h350737[20] ?
															    6'd36 :
															    (_theResult____h350737[19] ?
															       6'd37 :
															       (_theResult____h350737[18] ?
																  6'd38 :
																  (_theResult____h350737[17] ?
																     6'd39 :
																     (_theResult____h350737[16] ?
																	6'd40 :
																	(_theResult____h350737[15] ?
																	   6'd41 :
																	   (_theResult____h350737[14] ?
																	      6'd42 :
																	      (_theResult____h350737[13] ?
																		 6'd43 :
																		 (_theResult____h350737[12] ?
																		    6'd44 :
																		    (_theResult____h350737[11] ?
																		       6'd45 :
																		       (_theResult____h350737[10] ?
																			  6'd46 :
																			  (_theResult____h350737[9] ?
																			     6'd47 :
																			     (_theResult____h350737[8] ?
																				6'd48 :
																				(_theResult____h350737[7] ?
																				   6'd49 :
																				   (_theResult____h350737[6] ?
																				      6'd50 :
																				      (_theResult____h350737[5] ?
																					 6'd51 :
																					 (_theResult____h350737[4] ?
																					    6'd52 :
																					    (_theResult____h350737[3] ?
																					       6'd53 :
																					       (_theResult____h350737[2] ?
																						  6'd54 :
																						  (_theResult____h350737[1] ?
																						     6'd55 :
																						     (_theResult____h350737[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 =
	     (_theResult____h396436[56] ?
		6'd0 :
		(_theResult____h396436[55] ?
		   6'd1 :
		   (_theResult____h396436[54] ?
		      6'd2 :
		      (_theResult____h396436[53] ?
			 6'd3 :
			 (_theResult____h396436[52] ?
			    6'd4 :
			    (_theResult____h396436[51] ?
			       6'd5 :
			       (_theResult____h396436[50] ?
				  6'd6 :
				  (_theResult____h396436[49] ?
				     6'd7 :
				     (_theResult____h396436[48] ?
					6'd8 :
					(_theResult____h396436[47] ?
					   6'd9 :
					   (_theResult____h396436[46] ?
					      6'd10 :
					      (_theResult____h396436[45] ?
						 6'd11 :
						 (_theResult____h396436[44] ?
						    6'd12 :
						    (_theResult____h396436[43] ?
						       6'd13 :
						       (_theResult____h396436[42] ?
							  6'd14 :
							  (_theResult____h396436[41] ?
							     6'd15 :
							     (_theResult____h396436[40] ?
								6'd16 :
								(_theResult____h396436[39] ?
								   6'd17 :
								   (_theResult____h396436[38] ?
								      6'd18 :
								      (_theResult____h396436[37] ?
									 6'd19 :
									 (_theResult____h396436[36] ?
									    6'd20 :
									    (_theResult____h396436[35] ?
									       6'd21 :
									       (_theResult____h396436[34] ?
										  6'd22 :
										  (_theResult____h396436[33] ?
										     6'd23 :
										     (_theResult____h396436[32] ?
											6'd24 :
											(_theResult____h396436[31] ?
											   6'd25 :
											   (_theResult____h396436[30] ?
											      6'd26 :
											      (_theResult____h396436[29] ?
												 6'd27 :
												 (_theResult____h396436[28] ?
												    6'd28 :
												    (_theResult____h396436[27] ?
												       6'd29 :
												       (_theResult____h396436[26] ?
													  6'd30 :
													  (_theResult____h396436[25] ?
													     6'd31 :
													     (_theResult____h396436[24] ?
														6'd32 :
														(_theResult____h396436[23] ?
														   6'd33 :
														   (_theResult____h396436[22] ?
														      6'd34 :
														      (_theResult____h396436[21] ?
															 6'd35 :
															 (_theResult____h396436[20] ?
															    6'd36 :
															    (_theResult____h396436[19] ?
															       6'd37 :
															       (_theResult____h396436[18] ?
																  6'd38 :
																  (_theResult____h396436[17] ?
																     6'd39 :
																     (_theResult____h396436[16] ?
																	6'd40 :
																	(_theResult____h396436[15] ?
																	   6'd41 :
																	   (_theResult____h396436[14] ?
																	      6'd42 :
																	      (_theResult____h396436[13] ?
																		 6'd43 :
																		 (_theResult____h396436[12] ?
																		    6'd44 :
																		    (_theResult____h396436[11] ?
																		       6'd45 :
																		       (_theResult____h396436[10] ?
																			  6'd46 :
																			  (_theResult____h396436[9] ?
																			     6'd47 :
																			     (_theResult____h396436[8] ?
																				6'd48 :
																				(_theResult____h396436[7] ?
																				   6'd49 :
																				   (_theResult____h396436[6] ?
																				      6'd50 :
																				      (_theResult____h396436[5] ?
																					 6'd51 :
																					 (_theResult____h396436[4] ?
																					    6'd52 :
																					    (_theResult____h396436[3] ?
																					       6'd53 :
																					       (_theResult____h396436[2] ?
																						  6'd54 :
																						  (_theResult____h396436[1] ?
																						     6'd55 :
																						     (_theResult____h396436[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 =
	     (_theResult____h442131[56] ?
		6'd0 :
		(_theResult____h442131[55] ?
		   6'd1 :
		   (_theResult____h442131[54] ?
		      6'd2 :
		      (_theResult____h442131[53] ?
			 6'd3 :
			 (_theResult____h442131[52] ?
			    6'd4 :
			    (_theResult____h442131[51] ?
			       6'd5 :
			       (_theResult____h442131[50] ?
				  6'd6 :
				  (_theResult____h442131[49] ?
				     6'd7 :
				     (_theResult____h442131[48] ?
					6'd8 :
					(_theResult____h442131[47] ?
					   6'd9 :
					   (_theResult____h442131[46] ?
					      6'd10 :
					      (_theResult____h442131[45] ?
						 6'd11 :
						 (_theResult____h442131[44] ?
						    6'd12 :
						    (_theResult____h442131[43] ?
						       6'd13 :
						       (_theResult____h442131[42] ?
							  6'd14 :
							  (_theResult____h442131[41] ?
							     6'd15 :
							     (_theResult____h442131[40] ?
								6'd16 :
								(_theResult____h442131[39] ?
								   6'd17 :
								   (_theResult____h442131[38] ?
								      6'd18 :
								      (_theResult____h442131[37] ?
									 6'd19 :
									 (_theResult____h442131[36] ?
									    6'd20 :
									    (_theResult____h442131[35] ?
									       6'd21 :
									       (_theResult____h442131[34] ?
										  6'd22 :
										  (_theResult____h442131[33] ?
										     6'd23 :
										     (_theResult____h442131[32] ?
											6'd24 :
											(_theResult____h442131[31] ?
											   6'd25 :
											   (_theResult____h442131[30] ?
											      6'd26 :
											      (_theResult____h442131[29] ?
												 6'd27 :
												 (_theResult____h442131[28] ?
												    6'd28 :
												    (_theResult____h442131[27] ?
												       6'd29 :
												       (_theResult____h442131[26] ?
													  6'd30 :
													  (_theResult____h442131[25] ?
													     6'd31 :
													     (_theResult____h442131[24] ?
														6'd32 :
														(_theResult____h442131[23] ?
														   6'd33 :
														   (_theResult____h442131[22] ?
														      6'd34 :
														      (_theResult____h442131[21] ?
															 6'd35 :
															 (_theResult____h442131[20] ?
															    6'd36 :
															    (_theResult____h442131[19] ?
															       6'd37 :
															       (_theResult____h442131[18] ?
																  6'd38 :
																  (_theResult____h442131[17] ?
																     6'd39 :
																     (_theResult____h442131[16] ?
																	6'd40 :
																	(_theResult____h442131[15] ?
																	   6'd41 :
																	   (_theResult____h442131[14] ?
																	      6'd42 :
																	      (_theResult____h442131[13] ?
																		 6'd43 :
																		 (_theResult____h442131[12] ?
																		    6'd44 :
																		    (_theResult____h442131[11] ?
																		       6'd45 :
																		       (_theResult____h442131[10] ?
																			  6'd46 :
																			  (_theResult____h442131[9] ?
																			     6'd47 :
																			     (_theResult____h442131[8] ?
																				6'd48 :
																				(_theResult____h442131[7] ?
																				   6'd49 :
																				   (_theResult____h442131[6] ?
																				      6'd50 :
																				      (_theResult____h442131[5] ?
																					 6'd51 :
																					 (_theResult____h442131[4] ?
																					    6'd52 :
																					    (_theResult____h442131[3] ?
																					       6'd53 :
																					       (_theResult____h442131[2] ?
																						  6'd54 :
																						  (_theResult____h442131[1] ?
																						     6'd55 :
																						     (_theResult____h442131[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10491 =
	     (_theResult____h547110[56] ?
		6'd0 :
		(_theResult____h547110[55] ?
		   6'd1 :
		   (_theResult____h547110[54] ?
		      6'd2 :
		      (_theResult____h547110[53] ?
			 6'd3 :
			 (_theResult____h547110[52] ?
			    6'd4 :
			    (_theResult____h547110[51] ?
			       6'd5 :
			       (_theResult____h547110[50] ?
				  6'd6 :
				  (_theResult____h547110[49] ?
				     6'd7 :
				     (_theResult____h547110[48] ?
					6'd8 :
					(_theResult____h547110[47] ?
					   6'd9 :
					   (_theResult____h547110[46] ?
					      6'd10 :
					      (_theResult____h547110[45] ?
						 6'd11 :
						 (_theResult____h547110[44] ?
						    6'd12 :
						    (_theResult____h547110[43] ?
						       6'd13 :
						       (_theResult____h547110[42] ?
							  6'd14 :
							  (_theResult____h547110[41] ?
							     6'd15 :
							     (_theResult____h547110[40] ?
								6'd16 :
								(_theResult____h547110[39] ?
								   6'd17 :
								   (_theResult____h547110[38] ?
								      6'd18 :
								      (_theResult____h547110[37] ?
									 6'd19 :
									 (_theResult____h547110[36] ?
									    6'd20 :
									    (_theResult____h547110[35] ?
									       6'd21 :
									       (_theResult____h547110[34] ?
										  6'd22 :
										  (_theResult____h547110[33] ?
										     6'd23 :
										     (_theResult____h547110[32] ?
											6'd24 :
											(_theResult____h547110[31] ?
											   6'd25 :
											   (_theResult____h547110[30] ?
											      6'd26 :
											      (_theResult____h547110[29] ?
												 6'd27 :
												 (_theResult____h547110[28] ?
												    6'd28 :
												    (_theResult____h547110[27] ?
												       6'd29 :
												       (_theResult____h547110[26] ?
													  6'd30 :
													  (_theResult____h547110[25] ?
													     6'd31 :
													     (_theResult____h547110[24] ?
														6'd32 :
														(_theResult____h547110[23] ?
														   6'd33 :
														   (_theResult____h547110[22] ?
														      6'd34 :
														      (_theResult____h547110[21] ?
															 6'd35 :
															 (_theResult____h547110[20] ?
															    6'd36 :
															    (_theResult____h547110[19] ?
															       6'd37 :
															       (_theResult____h547110[18] ?
																  6'd38 :
																  (_theResult____h547110[17] ?
																     6'd39 :
																     (_theResult____h547110[16] ?
																	6'd40 :
																	(_theResult____h547110[15] ?
																	   6'd41 :
																	   (_theResult____h547110[14] ?
																	      6'd42 :
																	      (_theResult____h547110[13] ?
																		 6'd43 :
																		 (_theResult____h547110[12] ?
																		    6'd44 :
																		    (_theResult____h547110[11] ?
																		       6'd45 :
																		       (_theResult____h547110[10] ?
																			  6'd46 :
																			  (_theResult____h547110[9] ?
																			     6'd47 :
																			     (_theResult____h547110[8] ?
																				6'd48 :
																				(_theResult____h547110[7] ?
																				   6'd49 :
																				   (_theResult____h547110[6] ?
																				      6'd50 :
																				      (_theResult____h547110[5] ?
																					 6'd51 :
																					 (_theResult____h547110[4] ?
																					    6'd52 :
																					    (_theResult____h547110[3] ?
																					       6'd53 :
																					       (_theResult____h547110[2] ?
																						  6'd54 :
																						  (_theResult____h547110[1] ?
																						     6'd55 :
																						     (_theResult____h547110[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9006 =
	     (_theResult____h508257[56] ?
		6'd0 :
		(_theResult____h508257[55] ?
		   6'd1 :
		   (_theResult____h508257[54] ?
		      6'd2 :
		      (_theResult____h508257[53] ?
			 6'd3 :
			 (_theResult____h508257[52] ?
			    6'd4 :
			    (_theResult____h508257[51] ?
			       6'd5 :
			       (_theResult____h508257[50] ?
				  6'd6 :
				  (_theResult____h508257[49] ?
				     6'd7 :
				     (_theResult____h508257[48] ?
					6'd8 :
					(_theResult____h508257[47] ?
					   6'd9 :
					   (_theResult____h508257[46] ?
					      6'd10 :
					      (_theResult____h508257[45] ?
						 6'd11 :
						 (_theResult____h508257[44] ?
						    6'd12 :
						    (_theResult____h508257[43] ?
						       6'd13 :
						       (_theResult____h508257[42] ?
							  6'd14 :
							  (_theResult____h508257[41] ?
							     6'd15 :
							     (_theResult____h508257[40] ?
								6'd16 :
								(_theResult____h508257[39] ?
								   6'd17 :
								   (_theResult____h508257[38] ?
								      6'd18 :
								      (_theResult____h508257[37] ?
									 6'd19 :
									 (_theResult____h508257[36] ?
									    6'd20 :
									    (_theResult____h508257[35] ?
									       6'd21 :
									       (_theResult____h508257[34] ?
										  6'd22 :
										  (_theResult____h508257[33] ?
										     6'd23 :
										     (_theResult____h508257[32] ?
											6'd24 :
											(_theResult____h508257[31] ?
											   6'd25 :
											   (_theResult____h508257[30] ?
											      6'd26 :
											      (_theResult____h508257[29] ?
												 6'd27 :
												 (_theResult____h508257[28] ?
												    6'd28 :
												    (_theResult____h508257[27] ?
												       6'd29 :
												       (_theResult____h508257[26] ?
													  6'd30 :
													  (_theResult____h508257[25] ?
													     6'd31 :
													     (_theResult____h508257[24] ?
														6'd32 :
														(_theResult____h508257[23] ?
														   6'd33 :
														   (_theResult____h508257[22] ?
														      6'd34 :
														      (_theResult____h508257[21] ?
															 6'd35 :
															 (_theResult____h508257[20] ?
															    6'd36 :
															    (_theResult____h508257[19] ?
															       6'd37 :
															       (_theResult____h508257[18] ?
																  6'd38 :
																  (_theResult____h508257[17] ?
																     6'd39 :
																     (_theResult____h508257[16] ?
																	6'd40 :
																	(_theResult____h508257[15] ?
																	   6'd41 :
																	   (_theResult____h508257[14] ?
																	      6'd42 :
																	      (_theResult____h508257[13] ?
																		 6'd43 :
																		 (_theResult____h508257[12] ?
																		    6'd44 :
																		    (_theResult____h508257[11] ?
																		       6'd45 :
																		       (_theResult____h508257[10] ?
																			  6'd46 :
																			  (_theResult____h508257[9] ?
																			     6'd47 :
																			     (_theResult____h508257[8] ?
																				6'd48 :
																				(_theResult____h508257[7] ?
																				   6'd49 :
																				   (_theResult____h508257[6] ?
																				      6'd50 :
																				      (_theResult____h508257[5] ?
																					 6'd51 :
																					 (_theResult____h508257[4] ?
																					    6'd52 :
																					    (_theResult____h508257[3] ?
																					       6'd53 :
																					       (_theResult____h508257[2] ?
																						  6'd54 :
																						  (_theResult____h508257[1] ?
																						     6'd55 :
																						     (_theResult____h508257[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9721 =
	     (_theResult____h586414[56] ?
		6'd0 :
		(_theResult____h586414[55] ?
		   6'd1 :
		   (_theResult____h586414[54] ?
		      6'd2 :
		      (_theResult____h586414[53] ?
			 6'd3 :
			 (_theResult____h586414[52] ?
			    6'd4 :
			    (_theResult____h586414[51] ?
			       6'd5 :
			       (_theResult____h586414[50] ?
				  6'd6 :
				  (_theResult____h586414[49] ?
				     6'd7 :
				     (_theResult____h586414[48] ?
					6'd8 :
					(_theResult____h586414[47] ?
					   6'd9 :
					   (_theResult____h586414[46] ?
					      6'd10 :
					      (_theResult____h586414[45] ?
						 6'd11 :
						 (_theResult____h586414[44] ?
						    6'd12 :
						    (_theResult____h586414[43] ?
						       6'd13 :
						       (_theResult____h586414[42] ?
							  6'd14 :
							  (_theResult____h586414[41] ?
							     6'd15 :
							     (_theResult____h586414[40] ?
								6'd16 :
								(_theResult____h586414[39] ?
								   6'd17 :
								   (_theResult____h586414[38] ?
								      6'd18 :
								      (_theResult____h586414[37] ?
									 6'd19 :
									 (_theResult____h586414[36] ?
									    6'd20 :
									    (_theResult____h586414[35] ?
									       6'd21 :
									       (_theResult____h586414[34] ?
										  6'd22 :
										  (_theResult____h586414[33] ?
										     6'd23 :
										     (_theResult____h586414[32] ?
											6'd24 :
											(_theResult____h586414[31] ?
											   6'd25 :
											   (_theResult____h586414[30] ?
											      6'd26 :
											      (_theResult____h586414[29] ?
												 6'd27 :
												 (_theResult____h586414[28] ?
												    6'd28 :
												    (_theResult____h586414[27] ?
												       6'd29 :
												       (_theResult____h586414[26] ?
													  6'd30 :
													  (_theResult____h586414[25] ?
													     6'd31 :
													     (_theResult____h586414[24] ?
														6'd32 :
														(_theResult____h586414[23] ?
														   6'd33 :
														   (_theResult____h586414[22] ?
														      6'd34 :
														      (_theResult____h586414[21] ?
															 6'd35 :
															 (_theResult____h586414[20] ?
															    6'd36 :
															    (_theResult____h586414[19] ?
															       6'd37 :
															       (_theResult____h586414[18] ?
																  6'd38 :
																  (_theResult____h586414[17] ?
																     6'd39 :
																     (_theResult____h586414[16] ?
																	6'd40 :
																	(_theResult____h586414[15] ?
																	   6'd41 :
																	   (_theResult____h586414[14] ?
																	      6'd42 :
																	      (_theResult____h586414[13] ?
																		 6'd43 :
																		 (_theResult____h586414[12] ?
																		    6'd44 :
																		    (_theResult____h586414[11] ?
																		       6'd45 :
																		       (_theResult____h586414[10] ?
																			  6'd46 :
																			  (_theResult____h586414[9] ?
																			     6'd47 :
																			     (_theResult____h586414[8] ?
																				6'd48 :
																				(_theResult____h586414[7] ?
																				   6'd49 :
																				   (_theResult____h586414[6] ?
																				      6'd50 :
																				      (_theResult____h586414[5] ?
																					 6'd51 :
																					 (_theResult____h586414[4] ?
																					    6'd52 :
																					    (_theResult____h586414[3] ?
																					       6'd53 :
																					       (_theResult____h586414[2] ?
																						  6'd54 :
																						  (_theResult____h586414[1] ?
																						     6'd55 :
																						     (_theResult____h586414[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4894 =
	     (_theResult____h368376[56] ?
		6'd0 :
		(_theResult____h368376[55] ?
		   6'd1 :
		   (_theResult____h368376[54] ?
		      6'd2 :
		      (_theResult____h368376[53] ?
			 6'd3 :
			 (_theResult____h368376[52] ?
			    6'd4 :
			    (_theResult____h368376[51] ?
			       6'd5 :
			       (_theResult____h368376[50] ?
				  6'd6 :
				  (_theResult____h368376[49] ?
				     6'd7 :
				     (_theResult____h368376[48] ?
					6'd8 :
					(_theResult____h368376[47] ?
					   6'd9 :
					   (_theResult____h368376[46] ?
					      6'd10 :
					      (_theResult____h368376[45] ?
						 6'd11 :
						 (_theResult____h368376[44] ?
						    6'd12 :
						    (_theResult____h368376[43] ?
						       6'd13 :
						       (_theResult____h368376[42] ?
							  6'd14 :
							  (_theResult____h368376[41] ?
							     6'd15 :
							     (_theResult____h368376[40] ?
								6'd16 :
								(_theResult____h368376[39] ?
								   6'd17 :
								   (_theResult____h368376[38] ?
								      6'd18 :
								      (_theResult____h368376[37] ?
									 6'd19 :
									 (_theResult____h368376[36] ?
									    6'd20 :
									    (_theResult____h368376[35] ?
									       6'd21 :
									       (_theResult____h368376[34] ?
										  6'd22 :
										  (_theResult____h368376[33] ?
										     6'd23 :
										     (_theResult____h368376[32] ?
											6'd24 :
											(_theResult____h368376[31] ?
											   6'd25 :
											   (_theResult____h368376[30] ?
											      6'd26 :
											      (_theResult____h368376[29] ?
												 6'd27 :
												 (_theResult____h368376[28] ?
												    6'd28 :
												    (_theResult____h368376[27] ?
												       6'd29 :
												       (_theResult____h368376[26] ?
													  6'd30 :
													  (_theResult____h368376[25] ?
													     6'd31 :
													     (_theResult____h368376[24] ?
														6'd32 :
														(_theResult____h368376[23] ?
														   6'd33 :
														   (_theResult____h368376[22] ?
														      6'd34 :
														      (_theResult____h368376[21] ?
															 6'd35 :
															 (_theResult____h368376[20] ?
															    6'd36 :
															    (_theResult____h368376[19] ?
															       6'd37 :
															       (_theResult____h368376[18] ?
																  6'd38 :
																  (_theResult____h368376[17] ?
																     6'd39 :
																     (_theResult____h368376[16] ?
																	6'd40 :
																	(_theResult____h368376[15] ?
																	   6'd41 :
																	   (_theResult____h368376[14] ?
																	      6'd42 :
																	      (_theResult____h368376[13] ?
																		 6'd43 :
																		 (_theResult____h368376[12] ?
																		    6'd44 :
																		    (_theResult____h368376[11] ?
																		       6'd45 :
																		       (_theResult____h368376[10] ?
																			  6'd46 :
																			  (_theResult____h368376[9] ?
																			     6'd47 :
																			     (_theResult____h368376[8] ?
																				6'd48 :
																				(_theResult____h368376[7] ?
																				   6'd49 :
																				   (_theResult____h368376[6] ?
																				      6'd50 :
																				      (_theResult____h368376[5] ?
																					 6'd51 :
																					 (_theResult____h368376[4] ?
																					    6'd52 :
																					    (_theResult____h368376[3] ?
																					       6'd53 :
																					       (_theResult____h368376[2] ?
																						  6'd54 :
																						  (_theResult____h368376[1] ?
																						     6'd55 :
																						     (_theResult____h368376[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 =
	     (_theResult____h414073[56] ?
		6'd0 :
		(_theResult____h414073[55] ?
		   6'd1 :
		   (_theResult____h414073[54] ?
		      6'd2 :
		      (_theResult____h414073[53] ?
			 6'd3 :
			 (_theResult____h414073[52] ?
			    6'd4 :
			    (_theResult____h414073[51] ?
			       6'd5 :
			       (_theResult____h414073[50] ?
				  6'd6 :
				  (_theResult____h414073[49] ?
				     6'd7 :
				     (_theResult____h414073[48] ?
					6'd8 :
					(_theResult____h414073[47] ?
					   6'd9 :
					   (_theResult____h414073[46] ?
					      6'd10 :
					      (_theResult____h414073[45] ?
						 6'd11 :
						 (_theResult____h414073[44] ?
						    6'd12 :
						    (_theResult____h414073[43] ?
						       6'd13 :
						       (_theResult____h414073[42] ?
							  6'd14 :
							  (_theResult____h414073[41] ?
							     6'd15 :
							     (_theResult____h414073[40] ?
								6'd16 :
								(_theResult____h414073[39] ?
								   6'd17 :
								   (_theResult____h414073[38] ?
								      6'd18 :
								      (_theResult____h414073[37] ?
									 6'd19 :
									 (_theResult____h414073[36] ?
									    6'd20 :
									    (_theResult____h414073[35] ?
									       6'd21 :
									       (_theResult____h414073[34] ?
										  6'd22 :
										  (_theResult____h414073[33] ?
										     6'd23 :
										     (_theResult____h414073[32] ?
											6'd24 :
											(_theResult____h414073[31] ?
											   6'd25 :
											   (_theResult____h414073[30] ?
											      6'd26 :
											      (_theResult____h414073[29] ?
												 6'd27 :
												 (_theResult____h414073[28] ?
												    6'd28 :
												    (_theResult____h414073[27] ?
												       6'd29 :
												       (_theResult____h414073[26] ?
													  6'd30 :
													  (_theResult____h414073[25] ?
													     6'd31 :
													     (_theResult____h414073[24] ?
														6'd32 :
														(_theResult____h414073[23] ?
														   6'd33 :
														   (_theResult____h414073[22] ?
														      6'd34 :
														      (_theResult____h414073[21] ?
															 6'd35 :
															 (_theResult____h414073[20] ?
															    6'd36 :
															    (_theResult____h414073[19] ?
															       6'd37 :
															       (_theResult____h414073[18] ?
																  6'd38 :
																  (_theResult____h414073[17] ?
																     6'd39 :
																     (_theResult____h414073[16] ?
																	6'd40 :
																	(_theResult____h414073[15] ?
																	   6'd41 :
																	   (_theResult____h414073[14] ?
																	      6'd42 :
																	      (_theResult____h414073[13] ?
																		 6'd43 :
																		 (_theResult____h414073[12] ?
																		    6'd44 :
																		    (_theResult____h414073[11] ?
																		       6'd45 :
																		       (_theResult____h414073[10] ?
																			  6'd46 :
																			  (_theResult____h414073[9] ?
																			     6'd47 :
																			     (_theResult____h414073[8] ?
																				6'd48 :
																				(_theResult____h414073[7] ?
																				   6'd49 :
																				   (_theResult____h414073[6] ?
																				      6'd50 :
																				      (_theResult____h414073[5] ?
																					 6'd51 :
																					 (_theResult____h414073[4] ?
																					    6'd52 :
																					    (_theResult____h414073[3] ?
																					       6'd53 :
																					       (_theResult____h414073[2] ?
																						  6'd54 :
																						  (_theResult____h414073[1] ?
																						     6'd55 :
																						     (_theResult____h414073[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 =
	     (_theResult____h459768[56] ?
		6'd0 :
		(_theResult____h459768[55] ?
		   6'd1 :
		   (_theResult____h459768[54] ?
		      6'd2 :
		      (_theResult____h459768[53] ?
			 6'd3 :
			 (_theResult____h459768[52] ?
			    6'd4 :
			    (_theResult____h459768[51] ?
			       6'd5 :
			       (_theResult____h459768[50] ?
				  6'd6 :
				  (_theResult____h459768[49] ?
				     6'd7 :
				     (_theResult____h459768[48] ?
					6'd8 :
					(_theResult____h459768[47] ?
					   6'd9 :
					   (_theResult____h459768[46] ?
					      6'd10 :
					      (_theResult____h459768[45] ?
						 6'd11 :
						 (_theResult____h459768[44] ?
						    6'd12 :
						    (_theResult____h459768[43] ?
						       6'd13 :
						       (_theResult____h459768[42] ?
							  6'd14 :
							  (_theResult____h459768[41] ?
							     6'd15 :
							     (_theResult____h459768[40] ?
								6'd16 :
								(_theResult____h459768[39] ?
								   6'd17 :
								   (_theResult____h459768[38] ?
								      6'd18 :
								      (_theResult____h459768[37] ?
									 6'd19 :
									 (_theResult____h459768[36] ?
									    6'd20 :
									    (_theResult____h459768[35] ?
									       6'd21 :
									       (_theResult____h459768[34] ?
										  6'd22 :
										  (_theResult____h459768[33] ?
										     6'd23 :
										     (_theResult____h459768[32] ?
											6'd24 :
											(_theResult____h459768[31] ?
											   6'd25 :
											   (_theResult____h459768[30] ?
											      6'd26 :
											      (_theResult____h459768[29] ?
												 6'd27 :
												 (_theResult____h459768[28] ?
												    6'd28 :
												    (_theResult____h459768[27] ?
												       6'd29 :
												       (_theResult____h459768[26] ?
													  6'd30 :
													  (_theResult____h459768[25] ?
													     6'd31 :
													     (_theResult____h459768[24] ?
														6'd32 :
														(_theResult____h459768[23] ?
														   6'd33 :
														   (_theResult____h459768[22] ?
														      6'd34 :
														      (_theResult____h459768[21] ?
															 6'd35 :
															 (_theResult____h459768[20] ?
															    6'd36 :
															    (_theResult____h459768[19] ?
															       6'd37 :
															       (_theResult____h459768[18] ?
																  6'd38 :
																  (_theResult____h459768[17] ?
																     6'd39 :
																     (_theResult____h459768[16] ?
																	6'd40 :
																	(_theResult____h459768[15] ?
																	   6'd41 :
																	   (_theResult____h459768[14] ?
																	      6'd42 :
																	      (_theResult____h459768[13] ?
																		 6'd43 :
																		 (_theResult____h459768[12] ?
																		    6'd44 :
																		    (_theResult____h459768[11] ?
																		       6'd45 :
																		       (_theResult____h459768[10] ?
																			  6'd46 :
																			  (_theResult____h459768[9] ?
																			     6'd47 :
																			     (_theResult____h459768[8] ?
																				6'd48 :
																				(_theResult____h459768[7] ?
																				   6'd49 :
																				   (_theResult____h459768[6] ?
																				      6'd50 :
																				      (_theResult____h459768[5] ?
																					 6'd51 :
																					 (_theResult____h459768[4] ?
																					    6'd52 :
																					    (_theResult____h459768[3] ?
																					       6'd53 :
																					       (_theResult____h459768[2] ?
																						  6'd54 :
																						  (_theResult____h459768[1] ?
																						     6'd55 :
																						     (_theResult____h459768[0] ?
																							6'd56 :
																							6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
	     6'd1 ;
  assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10033 =
	     (_theResult___fst_exp__h594650 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
	       32'hFFFFFFFF ||
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard86424_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161) ;
  assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10535 =
	     (_theResult___fst_exp__h555346 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard47120_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186) ;
  assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10802 =
	     (_theResult___fst_exp__h555346 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	       32'hFFFFFFFF ||
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard47120_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192) ;
  assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9050 =
	     (_theResult___fst_exp__h516493 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard08267_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140) ;
  assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9765 =
	     (_theResult___fst_exp__h594650 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard86424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155) ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4406 =
	     (guard__h350747 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
	       _theResult___fst_exp__h358848 :
	       _theResult___exp__h359364 ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4409 =
	     (guard__h350747 == 2'b0) ?
	       _theResult___fst_exp__h358848 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		  _theResult___exp__h359364 :
		  _theResult___fst_exp__h358848) ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053 =
	     (guard__h350747 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
	       sfdin__h358842[56:34] :
	       _theResult___sfd__h359365 ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055 =
	     (guard__h350747 == 2'b0) ?
	       sfdin__h358842[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		  _theResult___sfd__h359365 :
		  sfdin__h358842[56:34]) ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5798 =
	     (guard__h396446 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
	       _theResult___fst_exp__h404545 :
	       _theResult___exp__h405061 ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5801 =
	     (guard__h396446 == 2'b0) ?
	       _theResult___fst_exp__h404545 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		  _theResult___exp__h405061 :
		  _theResult___fst_exp__h404545) ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445 =
	     (guard__h396446 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
	       sfdin__h404539[56:34] :
	       _theResult___sfd__h405062 ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447 =
	     (guard__h396446 == 2'b0) ?
	       sfdin__h404539[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		  _theResult___sfd__h405062 :
		  sfdin__h404539[56:34]) ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7190 =
	     (guard__h442141 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
	       _theResult___fst_exp__h450240 :
	       _theResult___exp__h450756 ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7193 =
	     (guard__h442141 == 2'b0) ?
	       _theResult___fst_exp__h450240 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		  _theResult___exp__h450756 :
		  _theResult___fst_exp__h450240) ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7837 =
	     (guard__h442141 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
	       sfdin__h450234[56:34] :
	       _theResult___sfd__h450757 ;
  assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7839 =
	     (guard__h442141 == 2'b0) ?
	       sfdin__h450234[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		  _theResult___sfd__h450757 :
		  sfdin__h450234[56:34]) ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10647 =
	     (guard__h547120 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
	       _theResult___fst_exp__h555346 :
	       _theResult___exp__h556075 ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10649 =
	     (guard__h547120 == 2'b0) ?
	       _theResult___fst_exp__h555346 :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
		  _theResult___exp__h556075 :
		  _theResult___fst_exp__h555346) ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10730 =
	     (guard__h547120 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
	       sfdin__h555340[56:5] :
	       _theResult___sfd__h556076 ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10732 =
	     (guard__h547120 == 2'b0) ?
	       sfdin__h555340[56:5] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
		  _theResult___sfd__h556076 :
		  sfdin__h555340[56:5]) ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9167 =
	     (guard__h508267 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
	       _theResult___fst_exp__h516493 :
	       _theResult___exp__h517222 ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9169 =
	     (guard__h508267 == 2'b0) ?
	       _theResult___fst_exp__h516493 :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
		  _theResult___exp__h517222 :
		  _theResult___fst_exp__h516493) ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251 =
	     (guard__h508267 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
	       sfdin__h516487[56:5] :
	       _theResult___sfd__h517223 ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9253 =
	     (guard__h508267 == 2'b0) ?
	       sfdin__h516487[56:5] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
		  _theResult___sfd__h517223 :
		  sfdin__h516487[56:5]) ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9877 =
	     (guard__h586424 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
	       _theResult___fst_exp__h594650 :
	       _theResult___exp__h595379 ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9879 =
	     (guard__h586424 == 2'b0) ?
	       _theResult___fst_exp__h594650 :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
		  _theResult___exp__h595379 :
		  _theResult___fst_exp__h594650) ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9960 =
	     (guard__h586424 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
	       sfdin__h594644[56:5] :
	       _theResult___sfd__h595380 ;
  assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9962 =
	     (guard__h586424 == 2'b0) ?
	       sfdin__h594644[56:5] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
		  _theResult___sfd__h595380 :
		  sfdin__h594644[56:5]) ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4953 =
	     (guard__h368386 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
	       _theResult___fst_exp__h376614 :
	       _theResult___exp__h377130 ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4955 =
	     (guard__h368386 == 2'b0) ?
	       _theResult___fst_exp__h376614 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		  _theResult___exp__h377130 :
		  _theResult___fst_exp__h376614) ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5099 =
	     (guard__h368386 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
	       sfdin__h376608[56:34] :
	       _theResult___sfd__h377131 ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5101 =
	     (guard__h368386 == 2'b0) ?
	       sfdin__h376608[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		  _theResult___sfd__h377131 :
		  sfdin__h376608[56:34]) ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6345 =
	     (guard__h414083 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
	       _theResult___fst_exp__h422311 :
	       _theResult___exp__h422827 ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6347 =
	     (guard__h414083 == 2'b0) ?
	       _theResult___fst_exp__h422311 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		  _theResult___exp__h422827 :
		  _theResult___fst_exp__h422311) ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6491 =
	     (guard__h414083 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
	       sfdin__h422305[56:34] :
	       _theResult___sfd__h422828 ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6493 =
	     (guard__h414083 == 2'b0) ?
	       sfdin__h422305[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		  _theResult___sfd__h422828 :
		  sfdin__h422305[56:34]) ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7737 =
	     (guard__h459778 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
	       _theResult___fst_exp__h468006 :
	       _theResult___exp__h468522 ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7739 =
	     (guard__h459778 == 2'b0) ?
	       _theResult___fst_exp__h468006 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		  _theResult___exp__h468522 :
		  _theResult___fst_exp__h468006) ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7883 =
	     (guard__h459778 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
	       sfdin__h468000[56:34] :
	       _theResult___sfd__h468523 ;
  assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7885 =
	     (guard__h459778 == 2'b0) ?
	       sfdin__h468000[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		  _theResult___sfd__h468523 :
		  sfdin__h468000[56:34]) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10609 =
	     (guard__h537808 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
	       _theResult___fst_exp__h545769 :
	       _theResult___exp__h546424 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10611 =
	     (guard__h537808 == 2'b0) ?
	       _theResult___fst_exp__h545769 :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
		  _theResult___exp__h546424 :
		  _theResult___fst_exp__h545769) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10678 =
	     (guard__h556189 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
	       _theResult___fst_exp__h564179 :
	       _theResult___exp__h564859 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10680 =
	     (guard__h556189 == 2'b0) ?
	       _theResult___fst_exp__h564179 :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
		  _theResult___exp__h564859 :
		  _theResult___fst_exp__h564179) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10704 =
	     (guard__h537808 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
	       _theResult___snd__h545720[56:5] :
	       _theResult___sfd__h546425 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10706 =
	     (guard__h537808 == 2'b0) ?
	       _theResult___snd__h545720[56:5] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
		  _theResult___sfd__h546425 :
		  _theResult___snd__h545720[56:5]) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10749 =
	     (guard__h556189 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
	       _theResult___snd__h564125[56:5] :
	       _theResult___sfd__h564860 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10751 =
	     (guard__h556189 == 2'b0) ?
	       _theResult___snd__h564125[56:5] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
		  _theResult___sfd__h564860 :
		  _theResult___snd__h564125[56:5]) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9124 =
	     (guard__h498955 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
	       _theResult___fst_exp__h506916 :
	       _theResult___exp__h507571 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9126 =
	     (guard__h498955 == 2'b0) ?
	       _theResult___fst_exp__h506916 :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
		  _theResult___exp__h507571 :
		  _theResult___fst_exp__h506916) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9198 =
	     (guard__h517336 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
	       _theResult___fst_exp__h525326 :
	       _theResult___exp__h526006 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9200 =
	     (guard__h517336 == 2'b0) ?
	       _theResult___fst_exp__h525326 :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
		  _theResult___exp__h526006 :
		  _theResult___fst_exp__h525326) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9224 =
	     (guard__h498955 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
	       _theResult___snd__h506867[56:5] :
	       _theResult___sfd__h507572 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9226 =
	     (guard__h498955 == 2'b0) ?
	       _theResult___snd__h506867[56:5] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
		  _theResult___sfd__h507572 :
		  _theResult___snd__h506867[56:5]) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9270 =
	     (guard__h517336 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
	       _theResult___snd__h525272[56:5] :
	       _theResult___sfd__h526007 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9272 =
	     (guard__h517336 == 2'b0) ?
	       _theResult___snd__h525272[56:5] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
		  _theResult___sfd__h526007 :
		  _theResult___snd__h525272[56:5]) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9839 =
	     (guard__h577112 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
	       _theResult___fst_exp__h585073 :
	       _theResult___exp__h585728 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9841 =
	     (guard__h577112 == 2'b0) ?
	       _theResult___fst_exp__h585073 :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
		  _theResult___exp__h585728 :
		  _theResult___fst_exp__h585073) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9908 =
	     (guard__h595493 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
	       _theResult___fst_exp__h603483 :
	       _theResult___exp__h604163 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9910 =
	     (guard__h595493 == 2'b0) ?
	       _theResult___fst_exp__h603483 :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
		  _theResult___exp__h604163 :
		  _theResult___fst_exp__h603483) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9934 =
	     (guard__h577112 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
	       _theResult___snd__h585024[56:5] :
	       _theResult___sfd__h585729 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9936 =
	     (guard__h577112 == 2'b0) ?
	       _theResult___snd__h585024[56:5] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
		  _theResult___sfd__h585729 :
		  _theResult___snd__h585024[56:5]) ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9979 =
	     (guard__h595493 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
	       _theResult___snd__h603429[56:5] :
	       _theResult___sfd__h604164 ;
  assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9981 =
	     (guard__h595493 == 2'b0) ?
	       _theResult___snd__h603429[56:5] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		 32'hFFFFFFFF &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
		  _theResult___sfd__h604164 :
		  _theResult___snd__h603429[56:5]) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628 =
	     (guard__h359456 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
	       _theResult___fst_exp__h367504 :
	       _theResult___exp__h367946 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630 =
	     (guard__h359456 == 2'b0) ?
	       _theResult___fst_exp__h367504 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		  _theResult___exp__h367946 :
		  _theResult___fst_exp__h367504) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 =
	     (guard__h377222 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
	       _theResult___fst_exp__h385299 :
	       _theResult___exp__h385766 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 =
	     (guard__h377222 == 2'b0) ?
	       _theResult___fst_exp__h385299 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		  _theResult___exp__h385766 :
		  _theResult___fst_exp__h385299) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072 =
	     (guard__h359456 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
	       _theResult___snd__h367455[56:34] :
	       _theResult___sfd__h367947 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074 =
	     (guard__h359456 == 2'b0) ?
	       _theResult___snd__h367455[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		  _theResult___sfd__h367947 :
		  _theResult___snd__h367455[56:34]) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118 =
	     (guard__h377222 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
	       _theResult___snd__h385245[56:34] :
	       _theResult___sfd__h385767 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120 =
	     (guard__h377222 == 2'b0) ?
	       _theResult___snd__h385245[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		  _theResult___sfd__h385767 :
		  _theResult___snd__h385245[56:34]) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6020 =
	     (guard__h405153 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
	       _theResult___fst_exp__h413201 :
	       _theResult___exp__h413643 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6022 =
	     (guard__h405153 == 2'b0) ?
	       _theResult___fst_exp__h413201 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		  _theResult___exp__h413643 :
		  _theResult___fst_exp__h413201) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 =
	     (guard__h422919 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
	       _theResult___fst_exp__h430996 :
	       _theResult___exp__h431463 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 =
	     (guard__h422919 == 2'b0) ?
	       _theResult___fst_exp__h430996 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		  _theResult___exp__h431463 :
		  _theResult___fst_exp__h430996) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464 =
	     (guard__h405153 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
	       _theResult___snd__h413152[56:34] :
	       _theResult___sfd__h413644 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6466 =
	     (guard__h405153 == 2'b0) ?
	       _theResult___snd__h413152[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		  _theResult___sfd__h413644 :
		  _theResult___snd__h413152[56:34]) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6510 =
	     (guard__h422919 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
	       _theResult___snd__h430942[56:34] :
	       _theResult___sfd__h431464 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6512 =
	     (guard__h422919 == 2'b0) ?
	       _theResult___snd__h430942[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		  _theResult___sfd__h431464 :
		  _theResult___snd__h430942[56:34]) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7412 =
	     (guard__h450848 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
	       _theResult___fst_exp__h458896 :
	       _theResult___exp__h459338 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7414 =
	     (guard__h450848 == 2'b0) ?
	       _theResult___fst_exp__h458896 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		  _theResult___exp__h459338 :
		  _theResult___fst_exp__h458896) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 =
	     (guard__h468614 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
	       _theResult___fst_exp__h476691 :
	       _theResult___exp__h477158 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 =
	     (guard__h468614 == 2'b0) ?
	       _theResult___fst_exp__h476691 :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		  _theResult___exp__h477158 :
		  _theResult___fst_exp__h476691) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7856 =
	     (guard__h450848 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
	       _theResult___snd__h458847[56:34] :
	       _theResult___sfd__h459339 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858 =
	     (guard__h450848 == 2'b0) ?
	       _theResult___snd__h458847[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		  _theResult___sfd__h459339 :
		  _theResult___snd__h458847[56:34]) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902 =
	     (guard__h468614 == 2'b0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
	       _theResult___snd__h476637[56:34] :
	       _theResult___sfd__h477159 ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904 =
	     (guard__h468614 == 2'b0) ?
	       _theResult___snd__h476637[56:34] :
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		  _theResult___sfd__h477159 :
		  _theResult___snd__h476637[56:34]) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10018 =
	     (_theResult___fst_exp__h585073 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
	       32'hFFFFFFFF ||
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard77112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10045 =
	     (_theResult___fst_exp__h603483 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
	       32'hFFFFFFFF ||
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard95493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10581 =
	     (_theResult___fst_exp__h564179 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard56189_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10787 =
	     (_theResult___fst_exp__h545769 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	       32'hFFFFFFFF ||
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard37808_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10814 =
	     (_theResult___fst_exp__h564179 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	       32'hFFFFFFFF ||
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard56189_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9096 =
	     (_theResult___fst_exp__h525326 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard17336_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142) ;
  assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9811 =
	     (_theResult___fst_exp__h603483 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard95493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159) ;
  assign IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992 =
	     (_theResult____h658034 == 12'd0 &&
	      (csrf_prv_reg == 2'd0 ||
	       csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ?
	       enabled_ints__h658493 :
	       _theResult____h658034 ;
  assign IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13204 =
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[1] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[2] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[3] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[4] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[5] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[6] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[7] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[8] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[9] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[10] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[11] ||
	     checkForException___d13160[4] ||
	     csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13197 ||
	     fetchStage$pipelines_0_first[231:200] == 32'h10500073 &&
	     csrf_tw_reg &&
	     csrf_prv_reg != 2'd3 ;
  assign IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13862 =
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[1] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[2] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[3] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[4] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[5] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[6] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[7] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[8] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[9] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[10] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[11] ||
	     checkForException___d13160[4] ||
	     csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13620 ;
  assign IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13898 =
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[1] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[2] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[3] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[4] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[5] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[6] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[7] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[8] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[9] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[10] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[11] ||
	     checkForException___d13807[4] ||
	     csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13896 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10048 =
	     (f3_exp__h565826 == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 ?
		  (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 ?
		     coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
		     32'hFFFFFFFF ||
		     !coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
		     IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10018) :
		  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10020) :
	       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10047 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10049 =
	     (f3_exp__h565826 == 8'd255 && f3_sfd__h565827 != 23'd0 ||
	      (f3_exp__h565826 == 8'd255 || f3_exp__h565826 == 8'd0) &&
	      f3_sfd__h565827 == 23'd0) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
	       32'hFFFFFFFF ||
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10048 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 =
	     ((f2_exp__h526522 == 8'd0) ?
		(f2_sfd__h526523[22] ?
		   6'd2 :
		   (f2_sfd__h526523[21] ?
		      6'd3 :
		      (f2_sfd__h526523[20] ?
			 6'd4 :
			 (f2_sfd__h526523[19] ?
			    6'd5 :
			    (f2_sfd__h526523[18] ?
			       6'd6 :
			       (f2_sfd__h526523[17] ?
				  6'd7 :
				  (f2_sfd__h526523[16] ?
				     6'd8 :
				     (f2_sfd__h526523[15] ?
					6'd9 :
					(f2_sfd__h526523[14] ?
					   6'd10 :
					   (f2_sfd__h526523[13] ?
					      6'd11 :
					      (f2_sfd__h526523[12] ?
						 6'd12 :
						 (f2_sfd__h526523[11] ?
						    6'd13 :
						    (f2_sfd__h526523[10] ?
						       6'd14 :
						       (f2_sfd__h526523[9] ?
							  6'd15 :
							  (f2_sfd__h526523[8] ?
							     6'd16 :
							     (f2_sfd__h526523[7] ?
								6'd17 :
								(f2_sfd__h526523[6] ?
								   6'd18 :
								   (f2_sfd__h526523[5] ?
								      6'd19 :
								      (f2_sfd__h526523[4] ?
									 6'd20 :
									 (f2_sfd__h526523[3] ?
									    6'd21 :
									    (f2_sfd__h526523[2] ?
									       6'd22 :
									       (f2_sfd__h526523[1] ?
										  6'd23 :
										  (f2_sfd__h526523[0] ?
										     6'd24 :
										     6'd57))))))))))))))))))))))) :
		6'd1) -
	     6'd1 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10585 =
	     (f2_exp__h526522 == 8'd255 && f2_sfd__h526523 != 23'd0 ||
	      (f2_exp__h526522 == 8'd255 || f2_exp__h526522 == 8'd0) &&
	      f2_sfd__h526523 == 23'd0) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
	       ((f2_exp__h526522 == 8'd0) ?
		  IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10240 :
		  IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10583) ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762 =
	     (f2_exp__h526522 == 8'd255 && f2_sfd__h526523 != 23'd0) ?
	       _theResult___snd_fst_sfd__h526838 :
	       _theResult___fst_sfd__h564978 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10763 =
	     { (f2_exp__h526522 == 8'd255) ?
		 11'd2047 :
		 _theResult___fst_exp__h564974,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762 } ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10817 =
	     (f2_exp__h526522 == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 ?
		  (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 ?
		     coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
		     32'hFFFFFFFF ||
		     !coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
		     IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10787) :
		  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10789) :
	       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10816 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10818 =
	     (f2_exp__h526522 == 8'd255 && f2_sfd__h526523 != 23'd0 ||
	      (f2_exp__h526522 == 8'd255 || f2_exp__h526522 == 8'd0) &&
	      f2_sfd__h526523 == 23'd0) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	       32'hFFFFFFFF ||
	       !coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10817 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10873 =
	     (f1_exp__h487528 == 8'd0) ?
	       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 &&
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[4] :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 &&
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 &&
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[4] ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10914 =
	     (f2_exp__h526522 == 8'd0) ?
	       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 &&
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[4] :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 &&
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 &&
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[4] ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10958 =
	     (f3_exp__h565826 == 8'd0) ?
	       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 &&
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[4] :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 &&
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 &&
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[4] ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973 =
	     (f1_exp__h487528 == 8'd0) ?
	       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 &&
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[3] :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 &&
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 &&
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[3] ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10983 =
	     (f2_exp__h526522 == 8'd0) ?
	       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 &&
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[3] :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 &&
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 &&
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[3] ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10994 =
	     (f3_exp__h565826 == 8'd0) ?
	       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 &&
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[3] :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 &&
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 &&
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[3] ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11013 =
	     (f1_exp__h487528 == 8'd0) ?
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 ||
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[2] :
	       !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 ||
	       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11011 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11027 =
	     (f2_exp__h526522 == 8'd0) ?
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 ||
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[2] :
	       !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 ||
	       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11025 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11042 =
	     (f3_exp__h565826 == 8'd0) ?
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 ||
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[2] :
	       !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 ||
	       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11040 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11059 =
	     (f1_exp__h487528 == 8'd0) ?
	       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 &&
	       (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 ||
		_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[1]) :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 &&
	       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11057 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11071 =
	     (f2_exp__h526522 == 8'd0) ?
	       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 &&
	       (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 ||
		_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[1]) :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 &&
	       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11069 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11084 =
	     (f3_exp__h565826 == 8'd0) ?
	       _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 &&
	       (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 ||
		_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[1]) :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 &&
	       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11082 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11101 =
	     (f1_exp__h487528 == 8'd0) ?
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 ||
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852[0] :
	       !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 ||
	       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11099 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11113 =
	     (f2_exp__h526522 == 8'd0) ?
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 ||
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893[0] :
	       !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 ||
	       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11111 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11126 =
	     (f3_exp__h565826 == 8'd0) ?
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 ||
	       !_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 &&
	       _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937[0] :
	       !SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 ||
	       IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11124 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 =
	     ((f1_exp__h487528 == 8'd0) ?
		(f1_sfd__h487529[22] ?
		   6'd2 :
		   (f1_sfd__h487529[21] ?
		      6'd3 :
		      (f1_sfd__h487529[20] ?
			 6'd4 :
			 (f1_sfd__h487529[19] ?
			    6'd5 :
			    (f1_sfd__h487529[18] ?
			       6'd6 :
			       (f1_sfd__h487529[17] ?
				  6'd7 :
				  (f1_sfd__h487529[16] ?
				     6'd8 :
				     (f1_sfd__h487529[15] ?
					6'd9 :
					(f1_sfd__h487529[14] ?
					   6'd10 :
					   (f1_sfd__h487529[13] ?
					      6'd11 :
					      (f1_sfd__h487529[12] ?
						 6'd12 :
						 (f1_sfd__h487529[11] ?
						    6'd13 :
						    (f1_sfd__h487529[10] ?
						       6'd14 :
						       (f1_sfd__h487529[9] ?
							  6'd15 :
							  (f1_sfd__h487529[8] ?
							     6'd16 :
							     (f1_sfd__h487529[7] ?
								6'd17 :
								(f1_sfd__h487529[6] ?
								   6'd18 :
								   (f1_sfd__h487529[5] ?
								      6'd19 :
								      (f1_sfd__h487529[4] ?
									 6'd20 :
									 (f1_sfd__h487529[3] ?
									    6'd21 :
									    (f1_sfd__h487529[2] ?
									       6'd22 :
									       (f1_sfd__h487529[1] ?
										  6'd23 :
										  (f1_sfd__h487529[0] ?
										     6'd24 :
										     6'd57))))))))))))))))))))))) :
		6'd1) -
	     6'd1 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9100 =
	     (f1_exp__h487528 == 8'd255 && f1_sfd__h487529 != 23'd0 ||
	      (f1_exp__h487528 == 8'd255 || f1_exp__h487528 == 8'd0) &&
	      f1_sfd__h487529 == 23'd0) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
	       ((f1_exp__h487528 == 8'd0) ?
		  IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8755 :
		  IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9098) ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9283 =
	     (f1_exp__h487528 == 8'd255 && f1_sfd__h487529 != 23'd0) ?
	       _theResult___snd_fst_sfd__h487844 :
	       _theResult___fst_sfd__h526125 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9284 =
	     { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9100,
	       (f1_exp__h487528 == 8'd255) ?
		 11'd2047 :
		 _theResult___fst_exp__h526121,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9283 } ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9424 =
	     ((f3_exp__h565826 == 8'd0) ?
		(f3_sfd__h565827[22] ?
		   6'd2 :
		   (f3_sfd__h565827[21] ?
		      6'd3 :
		      (f3_sfd__h565827[20] ?
			 6'd4 :
			 (f3_sfd__h565827[19] ?
			    6'd5 :
			    (f3_sfd__h565827[18] ?
			       6'd6 :
			       (f3_sfd__h565827[17] ?
				  6'd7 :
				  (f3_sfd__h565827[16] ?
				     6'd8 :
				     (f3_sfd__h565827[15] ?
					6'd9 :
					(f3_sfd__h565827[14] ?
					   6'd10 :
					   (f3_sfd__h565827[13] ?
					      6'd11 :
					      (f3_sfd__h565827[12] ?
						 6'd12 :
						 (f3_sfd__h565827[11] ?
						    6'd13 :
						    (f3_sfd__h565827[10] ?
						       6'd14 :
						       (f3_sfd__h565827[9] ?
							  6'd15 :
							  (f3_sfd__h565827[8] ?
							     6'd16 :
							     (f3_sfd__h565827[7] ?
								6'd17 :
								(f3_sfd__h565827[6] ?
								   6'd18 :
								   (f3_sfd__h565827[5] ?
								      6'd19 :
								      (f3_sfd__h565827[4] ?
									 6'd20 :
									 (f3_sfd__h565827[3] ?
									    6'd21 :
									    (f3_sfd__h565827[2] ?
									       6'd22 :
									       (f3_sfd__h565827[1] ?
										  6'd23 :
										  (f3_sfd__h565827[0] ?
										     6'd24 :
										     6'd57))))))))))))))))))))))) :
		6'd1) -
	     6'd1 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9815 =
	     (f3_exp__h565826 == 8'd255 && f3_sfd__h565827 != 23'd0 ||
	      (f3_exp__h565826 == 8'd255 || f3_exp__h565826 == 8'd0) &&
	      f3_sfd__h565827 == 23'd0) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
	       ((f3_exp__h565826 == 8'd0) ?
		  IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9470 :
		  IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9813) ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9992 =
	     (f3_exp__h565826 == 8'd255 && f3_sfd__h565827 != 23'd0) ?
	       _theResult___snd_fst_sfd__h566142 :
	       _theResult___fst_sfd__h604282 ;
  assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9993 =
	     { (f3_exp__h565826 == 8'd255) ?
		 11'd2047 :
		 _theResult___fst_exp__h604278,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9992 } ;
  assign IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1875 =
	     IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1864 ?
	       4'd11 :
	       (IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1868 ?
		  4'd12 :
		  (IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1872 ?
		     4'd13 :
		     4'd15)) ;
  assign IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1877 =
	     IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1856 ?
	       4'd8 :
	       (IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1860 ?
		  4'd9 :
		  IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1875) ;
  assign IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1879 =
	     IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1848 ?
	       4'd6 :
	       (IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1852 ?
		  4'd7 :
		  IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1877) ;
  assign IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1881 =
	     IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1840 ?
	       4'd4 :
	       (IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1844 ?
		  4'd5 :
		  IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1879) ;
  assign IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1883 =
	     IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1832 ?
	       4'd2 :
	       (IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1836 ?
		  4'd3 :
		  IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1881) ;
  assign IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1885 =
	     IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1824 ?
	       4'd0 :
	       (IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1828 ?
		  4'd1 :
		  IF_IF_coreFix_memExe_dTlb_procResp__740_BIT_11_ETC___d1883) ;
  assign IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13334 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13266 ==
		4'd12 :
		IF_checkForException_3160_BIT_4_3161_THEN_IF_c_ETC___d13295 ==
		4'd12) ?
	       4'd13 :
	       4'd15 ;
  assign IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13335 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13266 ==
		4'd11 :
		IF_checkForException_3160_BIT_4_3161_THEN_IF_c_ETC___d13295 ==
		4'd11) ?
	       4'd12 :
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13334 ;
  assign IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13336 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13266 ==
		4'd10 :
		IF_checkForException_3160_BIT_4_3161_THEN_IF_c_ETC___d13295 ==
		4'd10) ?
	       4'd11 :
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13335 ;
  assign IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13337 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13266 ==
		4'd9 :
		IF_checkForException_3160_BIT_4_3161_THEN_IF_c_ETC___d13295 ==
		4'd9) ?
	       4'd9 :
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13336 ;
  assign IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13338 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13266 ==
		4'd8 :
		IF_checkForException_3160_BIT_4_3161_THEN_IF_c_ETC___d13295 ==
		4'd8) ?
	       4'd8 :
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13337 ;
  assign IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13339 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13266 ==
		4'd7 :
		IF_checkForException_3160_BIT_4_3161_THEN_IF_c_ETC___d13295 ==
		4'd7) ?
	       4'd7 :
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13338 ;
  assign IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13340 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13266 ==
		4'd6 :
		IF_checkForException_3160_BIT_4_3161_THEN_IF_c_ETC___d13295 ==
		4'd6) ?
	       4'd6 :
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13339 ;
  assign IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13341 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13266 ==
		4'd5 :
		IF_checkForException_3160_BIT_4_3161_THEN_IF_c_ETC___d13295 ==
		4'd5) ?
	       4'd5 :
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13340 ;
  assign IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13342 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13266 ==
		4'd4 :
		IF_checkForException_3160_BIT_4_3161_THEN_IF_c_ETC___d13295 ==
		4'd4) ?
	       4'd4 :
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13341 ;
  assign IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13343 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13266 ==
		4'd3 :
		IF_checkForException_3160_BIT_4_3161_THEN_IF_c_ETC___d13295 ==
		4'd3) ?
	       4'd3 :
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13342 ;
  assign IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13344 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13266 ==
		4'd2 :
		IF_checkForException_3160_BIT_4_3161_THEN_IF_c_ETC___d13295 ==
		4'd2) ?
	       4'd2 :
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13343 ;
  assign IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13345 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13266 ==
		4'd1 :
		IF_checkForException_3160_BIT_4_3161_THEN_IF_c_ETC___d13295 ==
		4'd1) ?
	       4'd1 :
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13344 ;
  assign IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13346 =
	     (fetchStage$pipelines_0_first[68] ?
		IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13266 ==
		4'd0 :
		IF_checkForException_3160_BIT_4_3161_THEN_IF_c_ETC___d13295 ==
		4'd0) ?
	       4'd0 :
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13345 ;
  assign IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463 =
	     { (mmio_cRqQ_enqReq_lat_0$whas ?
		  mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd1 :
		  mmio_cRqQ_enqReq_rl[77:76] == 2'd1) ?
		 2'd1 :
		 ((mmio_cRqQ_enqReq_lat_0$whas ?
		     mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd2 :
		     mmio_cRqQ_enqReq_rl[77:76] == 2'd2) ?
		    2'd2 :
		    2'd3),
	       mmio_cRqQ_enqReq_lat_0$whas ?
		 mmio_cRqQ_enqReq_lat_0$wget[75:72] :
		 mmio_cRqQ_enqReq_rl[75:72] } ;
  assign IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172 =
	     { (mmio_dataReqQ_enqReq_lat_0$whas ?
		  mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd1 :
		  mmio_dataReqQ_enqReq_rl[77:76] == 2'd1) ?
		 2'd1 :
		 ((mmio_dataReqQ_enqReq_lat_0$whas ?
		     mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd2 :
		     mmio_dataReqQ_enqReq_rl[77:76] == 2'd2) ?
		    2'd2 :
		    2'd3),
	       mmio_dataReqQ_enqReq_lat_0$whas ?
		 mmio_dataReqQ_enqReq_lat_0$wget[75:72] :
		 mmio_dataReqQ_enqReq_rl[75:72] } ;
  assign IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766 =
	     { (EN_mmioToPlatform_pRq_enq ?
		  mmio_pRqQ_enqReq_lat_0$wget[37:36] == 2'd1 :
		  mmio_pRqQ_enqReq_rl[37:36] == 2'd1) ?
		 2'd1 :
		 ((EN_mmioToPlatform_pRq_enq ?
		     mmio_pRqQ_enqReq_lat_0$wget[37:36] == 2'd2 :
		     mmio_pRqQ_enqReq_rl[37:36] == 2'd2) ?
		    2'd2 :
		    2'd3),
	       EN_mmioToPlatform_pRq_enq ?
		 mmio_pRqQ_enqReq_lat_0$wget[35:32] :
		 mmio_pRqQ_enqReq_rl[35:32] } ;
  assign IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627 =
	     (EN_mmioToPlatform_pRs_enq ?
		!mmio_pRsQ_enqReq_lat_0$wget[66] :
		!mmio_pRsQ_enqReq_rl[66]) ?
	       { EN_mmioToPlatform_pRs_enq ?
		   mmio_pRsQ_enqReq_lat_0$wget[65] :
		   mmio_pRsQ_enqReq_rl[65],
		 EN_mmioToPlatform_pRs_enq ?
		   mmio_pRsQ_enqReq_lat_0$wget[64:33] :
		   mmio_pRsQ_enqReq_rl[64:33],
		 EN_mmioToPlatform_pRs_enq ?
		   mmio_pRsQ_enqReq_lat_0$wget[32] :
		   mmio_pRsQ_enqReq_rl[32],
		 EN_mmioToPlatform_pRs_enq ?
		   mmio_pRsQ_enqReq_lat_0$wget[31:0] :
		   mmio_pRsQ_enqReq_rl[31:0] } :
	       { 1'h0,
		 EN_mmioToPlatform_pRs_enq ?
		   mmio_pRsQ_enqReq_lat_0$wget[64:0] :
		   mmio_pRsQ_enqReq_rl[64:0] } ;
  assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10240 =
	     (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 ||
	      _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 ||
	      _theResult___fst_exp__h545769 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard37808_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188) ;
  assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8755 =
	     (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 ||
	      _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 ||
	      _theResult___fst_exp__h506916 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard98955_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138) ;
  assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9470 =
	     (!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 ||
	      _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 ||
	      _theResult___fst_exp__h585073 == 11'd2047) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
	       ((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
		 coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
		  CASE_guard77112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 :
		  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157) ;
  assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3__ETC___d13368 =
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] ?
	       4'd0 :
	       (IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[1] ?
		  4'd1 :
		  ((IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[3] &&
		    !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[2]) ?
		     4'd2 :
		     ((IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[4] &&
		       !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[2] &&
		       !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[3]) ?
			4'd3 :
			((IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[5] &&
			  !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[2] &&
			  !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[3] &&
			  !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[4]) ?
			   4'd4 :
			   ((IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[7] &&
			     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[2] &&
			     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[3] &&
			     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[4] &&
			     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[5] &&
			     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[6]) ?
			      4'd5 :
			      ((IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[8] &&
				!IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[2] &&
				!IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[3] &&
				!IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[4] &&
				!IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[5] &&
				!IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[6] &&
				!IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[7]) ?
				 4'd6 :
				 ((IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[9] &&
				   !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[2] &&
				   !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[3] &&
				   !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[4] &&
				   !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[5] &&
				   !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[6] &&
				   !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[7] &&
				   !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[8]) ?
				    4'd7 :
				    4'd8))))))) ;
  assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12401 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_0_bypassWire_0_wget__2367_BITS__ETC___d12369) ?
	       coreFix_aluExe_0_bypassWire_1$whas &&
	       coreFix_aluExe_0_bypassWire_1_wget__2380_BITS__ETC___d12382 :
	       coreFix_aluExe_0_bypassWire_0$whas ;
  assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12402 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_aluExe_0_bypassWire_0_wget__2367_BITS__ETC___d12369) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_aluExe_0_bypassWire_1_wget__2380_BITS__ETC___d12382)) ?
	       coreFix_aluExe_0_bypassWire_2$whas &&
	       coreFix_aluExe_0_bypassWire_2_wget__2388_BITS__ETC___d12390 :
	       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12401 ;
  assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12403 =
	     NOT_coreFix_aluExe_0_bypassWire_0_whas__2366_2_ETC___d12393 ?
	       coreFix_aluExe_0_bypassWire_3$whas &&
	       coreFix_aluExe_0_bypassWire_3_wget__2395_BITS__ETC___d12397 :
	       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12402 ;
  assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12428 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_0_bypassWire_0_wget__2367_BITS__ETC___d12410) ?
	       coreFix_aluExe_0_bypassWire_1$whas &&
	       coreFix_aluExe_0_bypassWire_1_wget__2380_BITS__ETC___d12416 :
	       coreFix_aluExe_0_bypassWire_0$whas ;
  assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12429 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_aluExe_0_bypassWire_0_wget__2367_BITS__ETC___d12410) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_aluExe_0_bypassWire_1_wget__2380_BITS__ETC___d12416)) ?
	       coreFix_aluExe_0_bypassWire_2$whas &&
	       coreFix_aluExe_0_bypassWire_2_wget__2388_BITS__ETC___d12420 :
	       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12428 ;
  assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12430 =
	     NOT_coreFix_aluExe_0_bypassWire_0_whas__2366_2_ETC___d12423 ?
	       coreFix_aluExe_0_bypassWire_3$whas &&
	       coreFix_aluExe_0_bypassWire_3_wget__2395_BITS__ETC___d12424 :
	       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12429 ;
  assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12444 =
	     IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12403 &&
	     NOT_coreFix_aluExe_0_bypassWire_0_whas__2366_2_ETC___d12393 &&
	     (!coreFix_aluExe_0_bypassWire_3$whas ||
	      !coreFix_aluExe_0_bypassWire_3_wget__2395_BITS__ETC___d12397) ;
  assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12452 =
	     IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12430 &&
	     NOT_coreFix_aluExe_0_bypassWire_0_whas__2366_2_ETC___d12423 &&
	     (!coreFix_aluExe_0_bypassWire_3$whas ||
	      !coreFix_aluExe_0_bypassWire_3_wget__2395_BITS__ETC___d12424) ;
  assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12616 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_0_bypassWire_0_wget__2367_BITS__ETC___d12369) ?
	       coreFix_aluExe_0_bypassWire_1$wget[63:0] :
	       coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
  assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12617 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_aluExe_0_bypassWire_0_wget__2367_BITS__ETC___d12369) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_aluExe_0_bypassWire_1_wget__2380_BITS__ETC___d12382)) ?
	       coreFix_aluExe_0_bypassWire_2$wget[63:0] :
	       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12616 ;
  assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12625 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_0_bypassWire_0_wget__2367_BITS__ETC___d12410) ?
	       coreFix_aluExe_0_bypassWire_1$wget[63:0] :
	       coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
  assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12626 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_aluExe_0_bypassWire_0_wget__2367_BITS__ETC___d12410) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_aluExe_0_bypassWire_1_wget__2380_BITS__ETC___d12416)) ?
	       coreFix_aluExe_0_bypassWire_2$wget[63:0] :
	       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12625 ;
  assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11545 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11513) ?
	       coreFix_aluExe_0_bypassWire_1$whas &&
	       coreFix_aluExe_1_bypassWire_1_wget__1524_BITS__ETC___d11526 :
	       coreFix_aluExe_0_bypassWire_0$whas ;
  assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11546 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11513) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_aluExe_1_bypassWire_1_wget__1524_BITS__ETC___d11526)) ?
	       coreFix_aluExe_1_bypassWire_2$whas &&
	       coreFix_aluExe_1_bypassWire_2_wget__1532_BITS__ETC___d11534 :
	       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11545 ;
  assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11547 =
	     NOT_coreFix_aluExe_1_bypassWire_0_whas__1510_1_ETC___d11537 ?
	       coreFix_aluExe_1_bypassWire_3$whas &&
	       coreFix_aluExe_1_bypassWire_3_wget__1539_BITS__ETC___d11541 :
	       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11546 ;
  assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11572 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11554) ?
	       coreFix_aluExe_0_bypassWire_1$whas &&
	       coreFix_aluExe_1_bypassWire_1_wget__1524_BITS__ETC___d11560 :
	       coreFix_aluExe_0_bypassWire_0$whas ;
  assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11573 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11554) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_aluExe_1_bypassWire_1_wget__1524_BITS__ETC___d11560)) ?
	       coreFix_aluExe_1_bypassWire_2$whas &&
	       coreFix_aluExe_1_bypassWire_2_wget__1532_BITS__ETC___d11564 :
	       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11572 ;
  assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11574 =
	     NOT_coreFix_aluExe_1_bypassWire_0_whas__1510_1_ETC___d11567 ?
	       coreFix_aluExe_1_bypassWire_3$whas &&
	       coreFix_aluExe_1_bypassWire_3_wget__1539_BITS__ETC___d11568 :
	       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11573 ;
  assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11588 =
	     IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11547 &&
	     NOT_coreFix_aluExe_1_bypassWire_0_whas__1510_1_ETC___d11537 &&
	     (!coreFix_aluExe_1_bypassWire_3$whas ||
	      !coreFix_aluExe_1_bypassWire_3_wget__1539_BITS__ETC___d11541) ;
  assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11596 =
	     IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11574 &&
	     NOT_coreFix_aluExe_1_bypassWire_0_whas__1510_1_ETC___d11567 &&
	     (!coreFix_aluExe_1_bypassWire_3$whas ||
	      !coreFix_aluExe_1_bypassWire_3_wget__1539_BITS__ETC___d11568) ;
  assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11942 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11513) ?
	       coreFix_aluExe_0_bypassWire_1$wget[63:0] :
	       coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
  assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11943 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11513) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_aluExe_1_bypassWire_1_wget__1524_BITS__ETC___d11526)) ?
	       coreFix_aluExe_0_bypassWire_2$wget[63:0] :
	       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11942 ;
  assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11951 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11554) ?
	       coreFix_aluExe_0_bypassWire_1$wget[63:0] :
	       coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
  assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11952 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11554) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_aluExe_1_bypassWire_1_wget__1524_BITS__ETC___d11560)) ?
	       coreFix_aluExe_0_bypassWire_2$wget[63:0] :
	       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11951 ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8335 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8303) ?
	       coreFix_aluExe_0_bypassWire_1$whas &&
	       coreFix_fpuMulDivExe_0_bypassWire_1_wget__314__ETC___d8316 :
	       coreFix_aluExe_0_bypassWire_0$whas ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8336 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8303) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_1_wget__314__ETC___d8316)) ?
	       coreFix_fpuMulDivExe_0_bypassWire_2$whas &&
	       coreFix_fpuMulDivExe_0_bypassWire_2_wget__322__ETC___d8324 :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8335 ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8337 =
	     NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8327 ?
	       coreFix_fpuMulDivExe_0_bypassWire_3$whas &&
	       coreFix_fpuMulDivExe_0_bypassWire_3_wget__329__ETC___d8331 :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8336 ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8361 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8343) ?
	       coreFix_aluExe_0_bypassWire_1$whas &&
	       coreFix_fpuMulDivExe_0_bypassWire_1_wget__314__ETC___d8349 :
	       coreFix_aluExe_0_bypassWire_0$whas ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8362 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8343) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_1_wget__314__ETC___d8349)) ?
	       coreFix_fpuMulDivExe_0_bypassWire_2$whas &&
	       coreFix_fpuMulDivExe_0_bypassWire_2_wget__322__ETC___d8353 :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8361 ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8363 =
	     NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8356 ?
	       coreFix_fpuMulDivExe_0_bypassWire_3$whas &&
	       coreFix_fpuMulDivExe_0_bypassWire_3_wget__329__ETC___d8357 :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8362 ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8387 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8369) ?
	       coreFix_aluExe_0_bypassWire_1$whas &&
	       coreFix_fpuMulDivExe_0_bypassWire_1_wget__314__ETC___d8375 :
	       coreFix_aluExe_0_bypassWire_0$whas ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8388 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8369) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_1_wget__314__ETC___d8375)) ?
	       coreFix_fpuMulDivExe_0_bypassWire_2$whas &&
	       coreFix_fpuMulDivExe_0_bypassWire_2_wget__322__ETC___d8379 :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8387 ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8389 =
	     NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8382 ?
	       coreFix_fpuMulDivExe_0_bypassWire_3$whas &&
	       coreFix_fpuMulDivExe_0_bypassWire_3_wget__329__ETC___d8383 :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8388 ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8403 =
	     IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8337 &&
	     NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8327 &&
	     (!coreFix_fpuMulDivExe_0_bypassWire_3$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_3_wget__329__ETC___d8331) ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8410 =
	     IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8363 &&
	     NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8356 &&
	     (!coreFix_fpuMulDivExe_0_bypassWire_3$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_3_wget__329__ETC___d8357) ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8417 =
	     IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8389 &&
	     NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8382 &&
	     (!coreFix_fpuMulDivExe_0_bypassWire_3$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_3_wget__329__ETC___d8383) ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8453 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8303) ?
	       coreFix_aluExe_0_bypassWire_1$wget[63:0] :
	       coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8454 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8303) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_1_wget__314__ETC___d8316)) ?
	       coreFix_aluExe_0_bypassWire_2$wget[63:0] :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8453 ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8461 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8343) ?
	       coreFix_aluExe_0_bypassWire_1$wget[63:0] :
	       coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8462 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8343) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_1_wget__314__ETC___d8349)) ?
	       coreFix_aluExe_0_bypassWire_2$wget[63:0] :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8461 ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8469 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8369) ?
	       coreFix_aluExe_0_bypassWire_1$wget[63:0] :
	       coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
  assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8470 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8369) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_fpuMulDivExe_0_bypassWire_1_wget__314__ETC___d8375)) ?
	       coreFix_aluExe_0_bypassWire_2$wget[63:0] :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8469 ;
  assign IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1619 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1587) ?
	       coreFix_aluExe_0_bypassWire_1$whas &&
	       coreFix_memExe_bypassWire_1_wget__598_BITS_70__ETC___d1600 :
	       coreFix_aluExe_0_bypassWire_0$whas ;
  assign IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1620 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1587) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_memExe_bypassWire_1_wget__598_BITS_70__ETC___d1600)) ?
	       coreFix_memExe_bypassWire_2$whas &&
	       coreFix_memExe_bypassWire_2_wget__606_BITS_70__ETC___d1608 :
	       IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1619 ;
  assign IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1621 =
	     NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1611 ?
	       coreFix_memExe_bypassWire_3$whas &&
	       coreFix_memExe_bypassWire_3_wget__613_BITS_70__ETC___d1615 :
	       IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1620 ;
  assign IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1645 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1627) ?
	       coreFix_aluExe_0_bypassWire_1$whas &&
	       coreFix_memExe_bypassWire_1_wget__598_BITS_70__ETC___d1633 :
	       coreFix_aluExe_0_bypassWire_0$whas ;
  assign IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1646 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1627) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_memExe_bypassWire_1_wget__598_BITS_70__ETC___d1633)) ?
	       coreFix_memExe_bypassWire_2$whas &&
	       coreFix_memExe_bypassWire_2_wget__606_BITS_70__ETC___d1637 :
	       IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1645 ;
  assign IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1647 =
	     NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1640 ?
	       coreFix_memExe_bypassWire_3$whas &&
	       coreFix_memExe_bypassWire_3_wget__613_BITS_70__ETC___d1641 :
	       IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1646 ;
  assign IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1660 =
	     IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1621 &&
	     NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1611 &&
	     (!coreFix_memExe_bypassWire_3$whas ||
	      !coreFix_memExe_bypassWire_3_wget__613_BITS_70__ETC___d1615) ;
  assign IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1667 =
	     IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1647 &&
	     NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1640 &&
	     (!coreFix_memExe_bypassWire_3$whas ||
	      !coreFix_memExe_bypassWire_3_wget__613_BITS_70__ETC___d1641) ;
  assign IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1678 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1587) ?
	       coreFix_aluExe_0_bypassWire_1$wget[63:0] :
	       coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
  assign IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1679 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1587) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_memExe_bypassWire_1_wget__598_BITS_70__ETC___d1600)) ?
	       coreFix_aluExe_0_bypassWire_2$wget[63:0] :
	       IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1678 ;
  assign IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1686 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1627) ?
	       coreFix_aluExe_0_bypassWire_1$wget[63:0] :
	       coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
  assign IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1687 =
	     ((!coreFix_aluExe_0_bypassWire_0$whas ||
	       !coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1627) &&
	      (!coreFix_aluExe_0_bypassWire_1$whas ||
	       !coreFix_memExe_bypassWire_1_wget__598_BITS_70__ETC___d1633)) ?
	       coreFix_aluExe_0_bypassWire_2$wget[63:0] :
	       IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1686 ;
  assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2114 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) ?
	       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2086 :
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
	       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2112 ;
  assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2131 =
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
	      2'd0 &&
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124) ?
	       coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N :
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N ;
  assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2538 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) ?
	       { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
		 IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2172,
		 IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2528 } :
	       { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
		  3'd3 &&
		  NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2100) ?
		   { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:516],
		     4'd2 } :
		   { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
		     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
		     1'd1,
		     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] },
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
  assign IF_NOT_coreFix_memExe_dTlb_procResp__740_BIT_1_ETC___d1819 =
	     (!coreFix_memExe_dTlb$procResp[110] &&
	      coreFix_memExe_dTlb$procResp[12]) ?
	       CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q13 :
	       CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q14 ;
  assign IF_NOT_fetchStage_pipelines_0_canDeq__2926_292_ETC___d14005 =
	     ((!fetchStage$pipelines_0_canDeq ||
	       NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13585) &&
	      fetchStage$pipelines_1_canDeq) ?
	       fetchStage$RDY_pipelines_1_first &&
	       (fetchStage$pipelines_1_first[194:192] != 3'd1 ||
		!fetchStage$pipelines_0_canDeq ||
		fetchStage$RDY_pipelines_0_first) &&
	       IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d14002 :
	       !fetchStage$pipelines_0_canDeq ||
	       fetchStage$RDY_pipelines_0_first ;
  assign IF_NOT_fetchStage_pipelines_0_canDeq__2926_292_ETC___d14013 =
	     ((!fetchStage$pipelines_0_canDeq ||
	       NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13585) &&
	      fetchStage$pipelines_1_canDeq) ?
	       IF_NOT_fetchStage_pipelines_1_first__2937_BITS_ETC___d14012 :
	       fetchStage$pipelines_0_canDeq &&
	       NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14010 ;
  assign IF_NOT_fetchStage_pipelines_1_first__2937_BITS_ETC___d13935 =
	     (fetchStage$pipelines_1_first[194:192] == 3'd3 ||
	      fetchStage$pipelines_1_first[194:192] == 3'd4) ?
	       NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13918 :
	       ((fetchStage$pipelines_1_first[194:192] == 3'd2) ?
		  NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13929 :
		  (fetchStage$pipelines_1_first[194:192] != 3'd1 ||
		   !fetchStage$pipelines_0_canDeq ||
		   fetchStage$RDY_pipelines_0_first) &&
		  _0_OR_fetchStage_RDY_pipelines_0_first__2925_39_ETC___d13932) ;
  assign IF_NOT_fetchStage_pipelines_1_first__2937_BITS_ETC___d14012 =
	     NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13845 ?
	       IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13999 ||
	       fetchStage$pipelines_0_canDeq &&
	       (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
		specTagManager$canClaim) &&
	       regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598 &&
	       IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 :
	       fetchStage$pipelines_0_canDeq &&
	       NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14010 ;
  assign IF_NOT_rob_deqPort_1_deq_data__5002_BIT_25_500_ETC___d15207 =
	     (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
	      rob$deqPort_1_deq_data[167] ||
	      rob$deqPort_1_deq_data[257:253] == 5'd0 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd21 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd17 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd18 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd13 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd16 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd15 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd19 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd20) ?
	       rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] :
	       rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ||
	       rob$deqPort_1_deq_data[26] ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10047 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 ?
	       (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ?
		  IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10033 :
		  IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10045) :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10020 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10542 =
	     ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169[10:0] ==
	       11'd0) ?
		12'd3074 :
		{ SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q172[10],
		  SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q172 }) -
	     12'd3074 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10583 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 ?
	       (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ?
		  IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10535 :
		  IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10581) :
	       coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[107] ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10816 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 ?
	       (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ?
		  IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10802 :
		  IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10814) :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10789 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11011 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ?
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[2] :
	       _theResult___fst_exp__h526109 == 11'd2047 &&
	       _theResult___fst_sfd__h526110 == 52'd0 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11025 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ?
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[2] :
	       _theResult___fst_exp__h564962 == 11'd2047 &&
	       _theResult___fst_sfd__h564963 == 52'd0 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11040 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ?
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[2] :
	       _theResult___fst_exp__h604266 == 11'd2047 &&
	       _theResult___fst_sfd__h604267 == 52'd0 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11057 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ?
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[1] :
	       _theResult___fst_exp__h525326 == 11'd0 &&
	       guard__h517336 != 2'b0 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11069 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ?
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[1] :
	       _theResult___fst_exp__h564179 == 11'd0 &&
	       guard__h556189 != 2'b0 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11082 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ?
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[1] :
	       _theResult___fst_exp__h603483 == 11'd0 &&
	       guard__h595493 != 2'b0 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11099 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ?
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869[0] :
	       _theResult___fst_exp__h525326 != 11'd2047 &&
	       guard__h517336 != 2'b0 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11111 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ?
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910[0] :
	       _theResult___fst_exp__h564179 != 11'd2047 &&
	       guard__h556189 != 2'b0 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11124 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ?
	       _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954[0] :
	       _theResult___fst_exp__h603483 != 11'd2047 &&
	       guard__h595493 != 2'b0 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9057 =
	     ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129[10:0] ==
	       11'd0) ?
		12'd3074 :
		{ SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q132[10],
		  SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q132 }) -
	     12'd3074 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9098 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 ?
	       (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ?
		  IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9050 :
		  IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9096) :
	       coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[171] ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9772 =
	     ((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q146[10:0] ==
	       11'd0) ?
		12'd3074 :
		{ SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q149[10],
		  SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q149 }) -
	     12'd3074 ;
  assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9813 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 ?
	       (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ?
		  IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9765 :
		  IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9811) :
	       coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[43] ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4968 =
	     ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] ==
	       8'd0) ?
		9'd386 :
		{ SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q35[7],
		  SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q35 }) -
	     9'd386 ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5195 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ?
	       ((_theResult___fst_exp__h376614 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180) :
	       ((_theResult___fst_exp__h385299 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193) ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5232 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ?
	       ((_theResult___fst_exp__h376614 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223) :
	       ((_theResult___fst_exp__h385299 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230) ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5323 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ?
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294[2] :
	       _theResult___fst_exp__h385847 == 8'd255 &&
	       _theResult___fst_sfd__h385848 == 23'd0 ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5336 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ?
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294[1] :
	       _theResult___fst_exp__h385299 == 8'd0 &&
	       guard__h377222 != 2'b0 ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5349 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ?
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294[0] :
	       _theResult___fst_exp__h385299 != 8'd255 &&
	       guard__h377222 != 2'b0 ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360 =
	     ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] ==
	       8'd0) ?
		9'd386 :
		{ SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q70[7],
		  SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q70 }) -
	     9'd386 ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6587 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ?
	       ((_theResult___fst_exp__h422311 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572) :
	       ((_theResult___fst_exp__h430996 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585) ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6624 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ?
	       ((_theResult___fst_exp__h422311 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615) :
	       ((_theResult___fst_exp__h430996 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622) ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6715 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ?
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686[2] :
	       _theResult___fst_exp__h431544 == 8'd255 &&
	       _theResult___fst_sfd__h431545 == 23'd0 ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6728 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ?
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686[1] :
	       _theResult___fst_exp__h430996 == 8'd0 &&
	       guard__h422919 != 2'b0 ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6741 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ?
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686[0] :
	       _theResult___fst_exp__h430996 != 8'd255 &&
	       guard__h422919 != 2'b0 ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752 =
	     ((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] ==
	       8'd0) ?
		9'd386 :
		{ SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q105[7],
		  SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q105 }) -
	     9'd386 ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7979 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ?
	       ((_theResult___fst_exp__h468006 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964) :
	       ((_theResult___fst_exp__h476691 == 8'd255) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977) ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8016 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ?
	       ((_theResult___fst_exp__h468006 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007) :
	       ((_theResult___fst_exp__h476691 == 8'd255) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014) ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8107 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ?
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078[2] :
	       _theResult___fst_exp__h477239 == 8'd255 &&
	       _theResult___fst_sfd__h477240 == 23'd0 ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8120 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ?
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078[1] :
	       _theResult___fst_exp__h476691 == 8'd0 &&
	       guard__h468614 != 2'b0 ;
  assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8133 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ?
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078[0] :
	       _theResult___fst_exp__h476691 != 8'd255 &&
	       guard__h468614 != 2'b0 ;
  assign IF_checkForException_3160_BIT_4_3161_THEN_IF_c_ETC___d13295 =
	     checkForException___d13160[4] ?
	       CASE_checkForException_3160_BITS_3_TO_0_0_chec_ETC__q226 :
	       4'd2 ;
  assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2344_ETC___d12377 =
	     (coreFix_aluExe_0_dispToRegQ$RDY_first &&
	      coreFix_aluExe_0_bypassWire_0$whas &&
	      coreFix_aluExe_0_bypassWire_0_wget__2367_BITS__ETC___d12369) ?
	       !coreFix_aluExe_0_bypassWire_0$whas ||
	       coreFix_aluExe_0_dispToRegQ$RDY_first :
	       !coreFix_aluExe_0_bypassWire_1$whas ||
	       coreFix_aluExe_0_dispToRegQ$RDY_first ;
  assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2344_ETC___d12413 =
	     (coreFix_aluExe_0_dispToRegQ$RDY_first &&
	      coreFix_aluExe_0_bypassWire_0$whas &&
	      coreFix_aluExe_0_bypassWire_0_wget__2367_BITS__ETC___d12410) ?
	       !coreFix_aluExe_0_bypassWire_0$whas ||
	       coreFix_aluExe_0_dispToRegQ$RDY_first :
	       !coreFix_aluExe_0_bypassWire_1$whas ||
	       coreFix_aluExe_0_dispToRegQ$RDY_first ;
  assign IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1488_ETC___d11521 =
	     (coreFix_aluExe_1_dispToRegQ$RDY_first &&
	      coreFix_aluExe_0_bypassWire_0$whas &&
	      coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11513) ?
	       !coreFix_aluExe_0_bypassWire_0$whas ||
	       coreFix_aluExe_1_dispToRegQ$RDY_first :
	       !coreFix_aluExe_0_bypassWire_1$whas ||
	       coreFix_aluExe_1_dispToRegQ$RDY_first ;
  assign IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1488_ETC___d11557 =
	     (coreFix_aluExe_1_dispToRegQ$RDY_first &&
	      coreFix_aluExe_0_bypassWire_0$whas &&
	      coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11554) ?
	       !coreFix_aluExe_0_bypassWire_0$whas ||
	       coreFix_aluExe_1_dispToRegQ$RDY_first :
	       !coreFix_aluExe_0_bypassWire_1$whas ||
	       coreFix_aluExe_1_dispToRegQ$RDY_first ;
  assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8311 =
	     (coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
	      coreFix_aluExe_0_bypassWire_0$whas &&
	      coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8303) ?
	       !coreFix_aluExe_0_bypassWire_0$whas ||
	       coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first :
	       !coreFix_aluExe_0_bypassWire_1$whas ||
	       coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ;
  assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8346 =
	     (coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
	      coreFix_aluExe_0_bypassWire_0$whas &&
	      coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8343) ?
	       !coreFix_aluExe_0_bypassWire_0$whas ||
	       coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first :
	       !coreFix_aluExe_0_bypassWire_1$whas ||
	       coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ;
  assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8372 =
	     (coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
	      coreFix_aluExe_0_bypassWire_0$whas &&
	      coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8369) ?
	       !coreFix_aluExe_0_bypassWire_0$whas ||
	       coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first :
	       !coreFix_aluExe_0_bypassWire_1$whas ||
	       coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6628 =
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[33] ?
	       ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
		 11'd2047 &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		 52'd0 ||
		 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
		  11'd2047 ||
		  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
		  11'd0) &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
		 52'd0) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6589) :
	       ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
		 11'd2047 &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		 52'd0 ||
		 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
		  11'd2047 ||
		  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
		  11'd0) &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
		 52'd0) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6626) ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 =
	     ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	       11'd0) ?
		(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] ?
		   6'd2 :
		   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] ?
		      6'd3 :
		      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] ?
			 6'd4 :
			 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[53] ?
			    6'd5 :
			    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[52] ?
			       6'd6 :
			       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[51] ?
				  6'd7 :
				  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[50] ?
				     6'd8 :
				     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[49] ?
					6'd9 :
					(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[48] ?
					   6'd10 :
					   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[47] ?
					      6'd11 :
					      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[46] ?
						 6'd12 :
						 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[45] ?
						    6'd13 :
						    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[44] ?
						       6'd14 :
						       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[43] ?
							  6'd15 :
							  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[42] ?
							     6'd16 :
							     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[41] ?
								6'd17 :
								(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[40] ?
								   6'd18 :
								   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[39] ?
								      6'd19 :
								      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[38] ?
									 6'd20 :
									 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[37] ?
									    6'd21 :
									    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[36] ?
									       6'd22 :
									       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[35] ?
										  6'd23 :
										  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[34] ?
										     6'd24 :
										     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[33] ?
											6'd25 :
											(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[32] ?
											   6'd26 :
											   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[31] ?
											      6'd27 :
											      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[30] ?
												 6'd28 :
												 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[29] ?
												    6'd29 :
												    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[28] ?
												       6'd30 :
												       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[27] ?
													  6'd31 :
													  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[26] ?
													     6'd32 :
													     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[25] ?
														6'd33 :
														(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[24] ?
														   6'd34 :
														   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[23] ?
														      6'd35 :
														      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[22] ?
															 6'd36 :
															 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[21] ?
															    6'd37 :
															    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[20] ?
															       6'd38 :
															       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[19] ?
																  6'd39 :
																  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[18] ?
																     6'd40 :
																     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[17] ?
																	6'd41 :
																	(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[16] ?
																	   6'd42 :
																	   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[15] ?
																	      6'd43 :
																	      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[14] ?
																		 6'd44 :
																		 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[13] ?
																		    6'd45 :
																		    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[12] ?
																		       6'd46 :
																		       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[11] ?
																			  6'd47 :
																			  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[10] ?
																			     6'd48 :
																			     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[9] ?
																				6'd49 :
																				(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[8] ?
																				   6'd50 :
																				   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] ?
																				      6'd51 :
																				      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] ?
																					 6'd52 :
																					 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ?
																					    6'd53 :
																					    6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
		6'd1) -
	     6'd1 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6589 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500 ?
		  IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6557 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 ?
		  IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6587 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559) ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6626 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500 ?
		  IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6607 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6608) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 ?
		  IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6624 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6608) ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6690 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6672 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 &&
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 &&
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686[4] ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6701 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6697 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 &&
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 &&
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686[3] ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6717 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6709 :
	       !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 ||
	       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6715 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6730 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6724 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 &&
	       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6728 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6743 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6737 :
	       !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 ||
	       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6741 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 =
	     ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	       11'd0) ?
		(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] ?
		   6'd2 :
		   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] ?
		      6'd3 :
		      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] ?
			 6'd4 :
			 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[53] ?
			    6'd5 :
			    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[52] ?
			       6'd6 :
			       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[51] ?
				  6'd7 :
				  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[50] ?
				     6'd8 :
				     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[49] ?
					6'd9 :
					(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[48] ?
					   6'd10 :
					   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[47] ?
					      6'd11 :
					      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[46] ?
						 6'd12 :
						 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[45] ?
						    6'd13 :
						    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[44] ?
						       6'd14 :
						       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[43] ?
							  6'd15 :
							  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[42] ?
							     6'd16 :
							     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[41] ?
								6'd17 :
								(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[40] ?
								   6'd18 :
								   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[39] ?
								      6'd19 :
								      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[38] ?
									 6'd20 :
									 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[37] ?
									    6'd21 :
									    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[36] ?
									       6'd22 :
									       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[35] ?
										  6'd23 :
										  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[34] ?
										     6'd24 :
										     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[33] ?
											6'd25 :
											(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[32] ?
											   6'd26 :
											   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[31] ?
											      6'd27 :
											      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[30] ?
												 6'd28 :
												 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[29] ?
												    6'd29 :
												    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[28] ?
												       6'd30 :
												       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[27] ?
													  6'd31 :
													  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[26] ?
													     6'd32 :
													     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[25] ?
														6'd33 :
														(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[24] ?
														   6'd34 :
														   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[23] ?
														      6'd35 :
														      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[22] ?
															 6'd36 :
															 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[21] ?
															    6'd37 :
															    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[20] ?
															       6'd38 :
															       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[19] ?
																  6'd39 :
																  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[18] ?
																     6'd40 :
																     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[17] ?
																	6'd41 :
																	(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[16] ?
																	   6'd42 :
																	   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[15] ?
																	      6'd43 :
																	      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[14] ?
																		 6'd44 :
																		 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[13] ?
																		    6'd45 :
																		    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[12] ?
																		       6'd46 :
																		       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[11] ?
																			  6'd47 :
																			  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[10] ?
																			     6'd48 :
																			     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[9] ?
																				6'd49 :
																				(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[8] ?
																				   6'd50 :
																				   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] ?
																				      6'd51 :
																				      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] ?
																					 6'd52 :
																					 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ?
																					    6'd53 :
																					    6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
		6'd1) -
	     6'd1 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5197 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 ?
		  IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5165 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5167) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 ?
		  IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5195 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5167) ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5234 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 ?
		  IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5215 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 ?
		  IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5232 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216) ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5298 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5280 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 &&
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 &&
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294[4] ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5309 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5305 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 &&
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 &&
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294[3] ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5325 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5317 :
	       !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 ||
	       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5323 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5338 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5332 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 &&
	       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5336 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5351 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5345 :
	       !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 ||
	       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5349 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 =
	     ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	       11'd0) ?
		(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] ?
		   6'd2 :
		   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[55] ?
		      6'd3 :
		      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[54] ?
			 6'd4 :
			 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[53] ?
			    6'd5 :
			    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[52] ?
			       6'd6 :
			       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[51] ?
				  6'd7 :
				  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[50] ?
				     6'd8 :
				     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[49] ?
					6'd9 :
					(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[48] ?
					   6'd10 :
					   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[47] ?
					      6'd11 :
					      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[46] ?
						 6'd12 :
						 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[45] ?
						    6'd13 :
						    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[44] ?
						       6'd14 :
						       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[43] ?
							  6'd15 :
							  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[42] ?
							     6'd16 :
							     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[41] ?
								6'd17 :
								(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[40] ?
								   6'd18 :
								   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[39] ?
								      6'd19 :
								      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[38] ?
									 6'd20 :
									 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[37] ?
									    6'd21 :
									    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[36] ?
									       6'd22 :
									       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[35] ?
										  6'd23 :
										  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[34] ?
										     6'd24 :
										     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[33] ?
											6'd25 :
											(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[32] ?
											   6'd26 :
											   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[31] ?
											      6'd27 :
											      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[30] ?
												 6'd28 :
												 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[29] ?
												    6'd29 :
												    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[28] ?
												       6'd30 :
												       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[27] ?
													  6'd31 :
													  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[26] ?
													     6'd32 :
													     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[25] ?
														6'd33 :
														(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[24] ?
														   6'd34 :
														   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[23] ?
														      6'd35 :
														      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[22] ?
															 6'd36 :
															 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[21] ?
															    6'd37 :
															    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[20] ?
															       6'd38 :
															       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[19] ?
																  6'd39 :
																  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[18] ?
																     6'd40 :
																     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[17] ?
																	6'd41 :
																	(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[16] ?
																	   6'd42 :
																	   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[15] ?
																	      6'd43 :
																	      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[14] ?
																		 6'd44 :
																		 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[13] ?
																		    6'd45 :
																		    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[12] ?
																		       6'd46 :
																		       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[11] ?
																			  6'd47 :
																			  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[10] ?
																			     6'd48 :
																			     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[9] ?
																				6'd49 :
																				(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[8] ?
																				   6'd50 :
																				   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[7] ?
																				      6'd51 :
																				      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[6] ?
																					 6'd52 :
																					 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ?
																					    6'd53 :
																					    6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
		6'd1) -
	     6'd1 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7981 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892 ?
		  IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7949 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7951) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 ?
		  IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7979 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7951) ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8018 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892 ?
		  IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7999 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8000) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 ?
		  IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8016 :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8000) ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8082 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8064 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 &&
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 &&
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078[4] ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8093 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8089 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 &&
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 &&
	       _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078[3] ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8109 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8101 :
	       !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 ||
	       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8107 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8122 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8116 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 &&
	       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8120 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8135 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8129 :
	       !SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 ||
	       IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8133 ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5236 =
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[33] ?
	       ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
		 11'd2047 &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		 52'd0 ||
		 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
		  11'd2047 ||
		  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
		  11'd0) &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
		 52'd0) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5197) :
	       ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
		 11'd2047 &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		 52'd0 ||
		 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
		  11'd2047 ||
		  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
		  11'd0) &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
		 52'd0) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5234) ;
  assign IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8020 =
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[33] ?
	       ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
		 11'd2047 &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		 52'd0 ||
		 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
		  11'd2047 ||
		  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
		  11'd0) &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
		 52'd0) ?
		  !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7981) :
	       ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
		 11'd2047 &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		 52'd0 ||
		 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
		  11'd2047 ||
		  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
		  11'd0) &&
		 coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
		 52'd0) ?
		  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		  IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8018) ;
  assign IF_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_d_ETC___d11255 =
	     (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT ==
	      64'd0) ?
	       64'd1 :
	       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT ;
  assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10020 =
	     coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
	     !coreFix_fpuMulDivExe_0_regToExeQ$first[43] ;
  assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10051 =
	     coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
	       { !coreFix_fpuMulDivExe_0_regToExeQ$first[75],
		 coreFix_fpuMulDivExe_0_regToExeQ$first[74:12] } :
	       { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10049,
		 IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9993 } ;
  assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10765 =
	     coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] :
	       { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10585,
		 IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10763 } ;
  assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10789 =
	     coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	     32'hFFFFFFFF ||
	     !coreFix_fpuMulDivExe_0_regToExeQ$first[107] ;
  assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8541 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4) ?
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8507 &&
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8520 :
	       NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d8540 ;
  assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9285 =
	     coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] :
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9284 ;
  assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9995 =
	     coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[75:12] :
	       { IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9815,
		 IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9993 } ;
  assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12869 =
	     coreFix_globalSpecUpdate_correctSpecTag_1$whas ?
	       result__h653741 :
	       w__h653736 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2112 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd3 &&
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2100) ?
	       NOT_coreFix_memExe_respLrScAmoQ_full_977_978_A_ETC___d2110 :
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2132 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd3 &&
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2100) ?
	       NOT_coreFix_memExe_respLrScAmoQ_full_977_978_A_ETC___d2110 :
	       IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2131 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2135 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
	      3'd1) ?
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite :
	       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2134 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2226 =
	     { (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
		3'd7) ?
		 n___1__h201750 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448],
	       (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
		3'd6) ?
		 n___1__h201750 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384],
	       (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
		3'd5) ?
		 n___1__h201750 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320],
	       (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
		3'd4) ?
		 n___1__h201750 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2231 =
	     { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2226,
	       (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
		3'd3) ?
		 n___1__h201750 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192],
	       (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
		3'd2) ?
		 n___1__h201750 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2236 =
	     { IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2231,
	       (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
		3'd1) ?
		 n___1__h201750 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64],
	       (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
		3'd0) ?
		 n___1__h201750 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2549 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd3 &&
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2100) ?
	       { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:516],
		 4'd2,
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } :
	       { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
		 (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
		  2'd0 &&
		  !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124) ?
		   { 3'd1,
		     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } :
		   { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
		     1'd1,
		     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] },
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2551 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
	      3'd1) ?
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:0] :
	       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2550 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
	      3'd1) ?
	       3'd5 :
	       ((coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
		 2'd0 &&
		 !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124) ?
		  3'd2 :
		  3'd3) ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2578 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
	      3'd1) ?
	       58'h155555555555554 :
	       ((coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
		 2'd0 &&
		 !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124) ?
		  { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
		    2'd0,
		    coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518],
		    1'd0 } :
		  { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
		    coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
		    53'h15555555555555 }) ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2595 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd2) ?
	       x__h200347 :
	       (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2178 ?
		  64'd0 :
		  64'd1) ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3127 =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ?
	       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[3] :
	       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[3] ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3142 =
	     WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry ||
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3154 =
	     _theResult_____2__h301173 == v__h300593 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3234 =
	     EN_dCacheToParent_fromP_enq ?
	       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] :
	       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[583] ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3249 =
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas ||
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3256 =
	     _theResult_____2__h309169 == v__h303938 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3276 =
	     EN_dCacheToParent_fromP_enq ?
	       !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] :
	       !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[583] ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3343 =
	     (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3234 &&
	      (EN_dCacheToParent_fromP_enq ?
		 !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[582] :
		 !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[582])) ?
	       { 516'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
		 EN_dCacheToParent_fromP_enq ?
		   coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[65:0] :
		   coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[65:0] } :
	       { EN_dCacheToParent_fromP_enq ?
		   coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[581:518] :
		   coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[581:518],
		 EN_dCacheToParent_fromP_enq ?
		   coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[517:516] :
		   coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[517:516],
		 !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT ||
		 IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3276 ||
		 (EN_dCacheToParent_fromP_enq ?
		    coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[515] :
		    coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[515]),
		 EN_dCacheToParent_fromP_enq ?
		   coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] :
		   coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3],
		 x__h306803 } ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3100 =
	     !MUX_flush_reservation$write_1__SEL_1 &&
	     (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[58] :
		coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58]) ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3108 =
	     MUX_flush_reservation$write_1__SEL_1 ?
	       58'h2AAAAAAAAAAAAAA :
	       (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ?
		  coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[57:0] :
		  coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0]) ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2075 =
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd3) ?
	       !coreFix_memExe_respLrScAmoQ_full :
	       !coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first ||
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	       3'd1 ||
	       coreFix_memExe_stb$RDY_deq ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2077 =
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd2) ?
	       !coreFix_memExe_respLrScAmoQ_full :
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	       3'd4 ||
	       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2075 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2078 =
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd0) ?
	       !coreFix_memExe_memRespLdQ_full :
	       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2077 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2086 =
	     IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2078 &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd4 ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
	      (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	       3'd1 ||
	       coreFix_memExe_stb$RDY_deq)) ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2134 =
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 &&
	      (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	       !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055)) ?
	       IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2086 :
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
	       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2132 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2136 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
	       (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 ?
		  IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2114 :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite) :
	       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2135 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2172 =
	     { (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <=
		coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82]) ?
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82] :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2550 =
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 &&
	      (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	       !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055)) ?
	       { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
		 IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2172,
		 IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2528 } :
	       IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2549 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2598 =
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 &&
	      (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	       !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055)) ?
	       { 1'd1,
		 IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2595 } :
	       65'h10000000000000001 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2778 =
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] ||
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2771 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2774) ?
	       coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_pipelineResp_releaseEntry :
	       coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2787 =
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] ||
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2771 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2774) ?
	       coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:512] :
	       { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518],
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
		   2'd0 :
		   coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0],
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515:512] } ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2023 =
	     { (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
		3'd7) ?
		 n__h196842 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448],
	       (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
		3'd6) ?
		 n__h196842 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384],
	       (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
		3'd5) ?
		 n__h196842 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2028 =
	     { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2023,
	       (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
		3'd4) ?
		 n__h196842 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256],
	       (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
		3'd3) ?
		 n__h196842 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2033 =
	     { IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2028,
	       (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
		3'd2) ?
		 n__h196842 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128],
	       (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
		3'd1) ?
		 n__h196842 :
		 coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2882 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[83:82] :
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[83:82]) :
	       2'd0 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2886 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[81:79] :
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[81:79]) :
	       3'd0 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2929 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[6:3] :
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[6:3]) :
	       4'd0 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3405 =
	     CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[72] :
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[72] ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3420 =
	     EN_dCacheToParent_rqToP_deq ||
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3428 =
	     _theResult_____2__h315163 == v__h314452 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3501 =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
	       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] :
	       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[579] ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3516 =
	     EN_dCacheToParent_rsToP_deq ||
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3524 =
	     _theResult_____2__h323017 == v__h318328 ;
  assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3543 =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
	       !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] :
	       !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[579] ;
  assign IF_coreFix_memExe_dTlb_procResp__740_BITS_105__ETC___d1820 =
	     (coreFix_memExe_dTlb$procResp[105:103] == 3'd3) ?
	       4'd7 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__740_BIT_1_ETC___d1819 ;
  assign IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1768 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[110] &&
	      coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1759) ?
	       coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
	       coreFix_memExe_dTlb$procResp[105:103] != 3'd3 &&
	       !coreFix_memExe_dTlb$procResp[12] :
	       !coreFix_memExe_dTlb$procResp[12] &&
	       !coreFix_memExe_dTlb$procResp[110] ;
  assign IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1824 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[110] &&
	      coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1759) ?
	       coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__740_BITS_105__ETC___d1820 ==
	       4'd0 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__740_BIT_1_ETC___d1819 ==
	       4'd0 ;
  assign IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1828 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[110] &&
	      coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1759) ?
	       coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__740_BITS_105__ETC___d1820 ==
	       4'd1 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__740_BIT_1_ETC___d1819 ==
	       4'd1 ;
  assign IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1832 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[110] &&
	      coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1759) ?
	       coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__740_BITS_105__ETC___d1820 ==
	       4'd2 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__740_BIT_1_ETC___d1819 ==
	       4'd2 ;
  assign IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1836 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[110] &&
	      coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1759) ?
	       coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__740_BITS_105__ETC___d1820 ==
	       4'd3 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__740_BIT_1_ETC___d1819 ==
	       4'd3 ;
  assign IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1840 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[110] &&
	      coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1759) ?
	       coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__740_BITS_105__ETC___d1820 ==
	       4'd4 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__740_BIT_1_ETC___d1819 ==
	       4'd4 ;
  assign IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1844 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[110] &&
	      coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1759) ?
	       coreFix_memExe_dTlb$procResp[105:103] == 3'd2 ||
	       IF_coreFix_memExe_dTlb_procResp__740_BITS_105__ETC___d1820 ==
	       4'd5 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__740_BIT_1_ETC___d1819 ==
	       4'd5 ;
  assign IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1848 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[110] &&
	      coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1759) ?
	       coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__740_BITS_105__ETC___d1820 ==
	       4'd6 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__740_BIT_1_ETC___d1819 ==
	       4'd6 ;
  assign IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1852 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[110] &&
	      coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1759) ?
	       coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__740_BITS_105__ETC___d1820 ==
	       4'd7 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__740_BIT_1_ETC___d1819 ==
	       4'd7 ;
  assign IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1856 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[110] &&
	      coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1759) ?
	       coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__740_BITS_105__ETC___d1820 ==
	       4'd8 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__740_BIT_1_ETC___d1819 ==
	       4'd8 ;
  assign IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1860 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[110] &&
	      coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1759) ?
	       coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__740_BITS_105__ETC___d1820 ==
	       4'd9 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__740_BIT_1_ETC___d1819 ==
	       4'd9 ;
  assign IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1864 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[110] &&
	      coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1759) ?
	       coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__740_BITS_105__ETC___d1820 ==
	       4'd10 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__740_BIT_1_ETC___d1819 ==
	       4'd10 ;
  assign IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1868 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[110] &&
	      coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1759) ?
	       coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__740_BITS_105__ETC___d1820 ==
	       4'd11 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__740_BIT_1_ETC___d1819 ==
	       4'd11 ;
  assign IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1872 =
	     (!coreFix_memExe_dTlb$procResp[12] &&
	      !coreFix_memExe_dTlb$procResp[110] &&
	      coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1759) ?
	       coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
	       IF_coreFix_memExe_dTlb_procResp__740_BITS_105__ETC___d1820 ==
	       4'd12 :
	       IF_NOT_coreFix_memExe_dTlb_procResp__740_BIT_1_ETC___d1819 ==
	       4'd12 ;
  assign IF_coreFix_memExe_dispToRegQ_RDY_first__564_AN_ETC___d1595 =
	     (coreFix_memExe_dispToRegQ$RDY_first &&
	      coreFix_aluExe_0_bypassWire_0$whas &&
	      coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1587) ?
	       !coreFix_aluExe_0_bypassWire_0$whas ||
	       coreFix_memExe_dispToRegQ$RDY_first :
	       !coreFix_aluExe_0_bypassWire_1$whas ||
	       coreFix_memExe_dispToRegQ$RDY_first ;
  assign IF_coreFix_memExe_dispToRegQ_RDY_first__564_AN_ETC___d1630 =
	     (coreFix_memExe_dispToRegQ$RDY_first &&
	      coreFix_aluExe_0_bypassWire_0$whas &&
	      coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1627) ?
	       !coreFix_aluExe_0_bypassWire_0$whas ||
	       coreFix_memExe_dispToRegQ$RDY_first :
	       !coreFix_aluExe_0_bypassWire_1$whas ||
	       coreFix_memExe_dispToRegQ$RDY_first ;
  assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3846 =
	     _theResult_____2__h336586 == v__h336154 ;
  assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3839 =
	     WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
	     coreFix_memExe_forwardQ_deqReq_rl ;
  assign IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3824 =
	     coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
	       coreFix_memExe_forwardQ_enqReq_lat_0$wget[69] :
	       coreFix_memExe_forwardQ_enqReq_rl[69] ;
  assign IF_coreFix_memExe_lsq_firstLd__285_BIT_94_360__ETC___d1385 =
	     coreFix_memExe_lsq$firstLd[94] ?
	       (coreFix_memExe_lsq$firstLd[92] ?
		  { 48'd0,
		    SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 } :
		  { {48{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367[15]}},
		    SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 }) :
	       (coreFix_memExe_lsq$firstLd[92] ?
		  { 56'd0,
		    SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381 } :
		  { {56{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381[7]}},
		    SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381 }) ;
  assign IF_coreFix_memExe_lsq_firstLd__285_BIT_94_360__ETC___d1434 =
	     coreFix_memExe_lsq$firstLd[94] ?
	       (coreFix_memExe_lsq$firstLd[92] ?
		  { 48'd0,
		    SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 } :
		  { {48{SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417[15]}},
		    SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 }) :
	       (coreFix_memExe_lsq$firstLd[92] ?
		  { 56'd0,
		    SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430 } :
		  { {56{SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430[7]}},
		    SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430 }) ;
  assign IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1386 =
	     coreFix_memExe_lsq$firstLd[96] ?
	       (coreFix_memExe_lsq$firstLd[92] ?
		  { 32'd0,
		    SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1356 } :
		  { {32{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1356[31]}},
		    SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1356 }) :
	       IF_coreFix_memExe_lsq_firstLd__285_BIT_94_360__ETC___d1385 ;
  assign IF_coreFix_memExe_lsq_firstLd__285_BIT_96_350__ETC___d1435 =
	     coreFix_memExe_lsq$firstLd[96] ?
	       (coreFix_memExe_lsq$firstLd[92] ?
		  { 32'd0,
		    SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408 } :
		  { {32{SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408[31]}},
		    SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408 }) :
	       IF_coreFix_memExe_lsq_firstLd__285_BIT_94_360__ETC___d1434 ;
  assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3752 =
	     _theResult_____2__h333361 == v__h332929 ;
  assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3745 =
	     WILL_FIRE_RL_coreFix_memExe_doRespLdMem ||
	     coreFix_memExe_memRespLdQ_deqReq_rl ;
  assign IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3730 =
	     coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
	       coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[69] :
	       coreFix_memExe_memRespLdQ_enqReq_rl[69] ;
  assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1216 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		  coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[83:82] :
		  coreFix_memExe_reqLrScAmoQ_data_0_rl[83:82]) :
	       2'd0 ;
  assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1220 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		  coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[81:79] :
		  coreFix_memExe_reqLrScAmoQ_data_0_rl[81:79]) :
	       3'd0 ;
  assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1263 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		  coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[6:3] :
		  coreFix_memExe_reqLrScAmoQ_data_0_rl[6:3]) :
	       4'd0 ;
  assign IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3654 =
	     coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ?
	       coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[64] :
	       coreFix_memExe_respLrScAmoQ_enqReq_rl[64] ;
  assign IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 =
	     csrf_minstret_ehr_data_lat_0$whas ?
	       rob$deqPort_0_deq_data[95:32] :
	       csrf_minstret_ehr_data_rl ;
  assign IF_fetchStage_RDY_pipelines_0_first__2925_AND__ETC___d13555 =
	     fetchStage_RDY_pipelines_0_first__2925_AND_NOT_ETC___d13551 ?
	       fetchStage$RDY_pipelines_0_first :
	       !regRenamingTable$rename_0_canRename ||
	       fetchStage$RDY_pipelines_0_first ;
  assign IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d13937 =
	     (fetchStage$RDY_pipelines_1_first &&
	      (fetchStage$pipelines_1_first[194:192] == 3'd0 ||
	       fetchStage$pipelines_1_first[194:192] == 3'd1)) ?
	       (!fetchStage$pipelines_0_canDeq ||
		fetchStage$RDY_pipelines_0_first) &&
	       SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13907 :
	       fetchStage$RDY_pipelines_1_first &&
	       IF_NOT_fetchStage_pipelines_1_first__2937_BITS_ETC___d13935 ;
  assign IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d14002 =
	     (fetchStage$RDY_pipelines_1_first &&
	      (fetchStage$pipelines_1_first[194:192] != 3'd1 ||
	       !fetchStage$pipelines_0_canDeq ||
	       fetchStage$RDY_pipelines_0_first) &&
	      fetchStage_RDY_pipelines_0_first__2925_AND_fet_ETC___d13617 &&
	      NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13845) ?
	       IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d13937 &&
	       (IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13999 ||
		!fetchStage$pipelines_0_canDeq ||
		fetchStage$RDY_pipelines_0_first) :
	       !fetchStage$pipelines_0_canDeq ||
	       fetchStage$RDY_pipelines_0_first ;
  assign IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14050 =
	     IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14043 ||
	     fetchStage$RDY_pipelines_0_deq &&
	     regRenamingTable$RDY_rename_0_getRename &&
	     regRenamingTable$RDY_rename_0_claimRename &&
	     rob$RDY_enqPort_0_enq &&
	     (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	      specTagManager$RDY_claimSpecTag) ;
  assign IF_fetchStage_pipelines_0_first__2928_BIT_160__ETC___d14237 =
	     { fetchStage$pipelines_0_first[159:128],
	       IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14225,
	       IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14228 ?
		 IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14231 :
		 { 1'h0,
		   IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14234 } } ;
  assign IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13385 =
	     (fetchStage$pipelines_0_first[68] ||
	      !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[1] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[2] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[3] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[4] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[5] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[6] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[7] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[8] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[9] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[10] &&
	      !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[11]) ?
	       IF_IF_fetchStage_pipelines_0_first__2928_BIT_6_ETC___d13346 :
	       CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2956__ETC__q227 ;
  assign IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14171 =
	     IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14130 &&
	     IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d13937 &&
	     (IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14155 ||
	      fetchStage$RDY_pipelines_1_deq &&
	      regRenamingTable$RDY_rename_1_getRename &&
	      regRenamingTable$RDY_rename_1_claimRename &&
	      rob_RDY_enqPort_1_enq__4157_AND_NOT_fetchStage_ETC___d14165) ;
  assign IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14451 =
	     (fetchStage$pipelines_1_first[194:192] == 3'd2 &&
	      NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14386 &&
	      IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14393) ?
	       IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14394 :
	       { 1'h0,
		 IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14395 } ;
  assign IF_fetchStage_pipelines_1_first__2937_BIT_160__ETC___d14398 =
	     { fetchStage$pipelines_1_first[159:128],
	       IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14392,
	       IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14393 ?
		 IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14394 :
		 { 1'h0,
		   IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14395 } } ;
  assign IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 =
	     mmio_cRqQ_enqReq_lat_0$whas ?
	       mmio_cRqQ_enqReq_lat_0$wget[142] :
	       mmio_cRqQ_enqReq_rl[142] ;
  assign IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 =
	     CAN_FIRE_RL_mmio_handlePRq ?
	       mmio_cRsQ_enqReq_lat_0$wget[1] :
	       mmio_cRsQ_enqReq_rl[1] ;
  assign IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 =
	     mmio_dataReqQ_enqReq_lat_0$whas ?
	       mmio_dataReqQ_enqReq_lat_0$wget[142] :
	       mmio_dataReqQ_enqReq_rl[142] ;
  assign IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 =
	     CAN_FIRE_RL_mmio_sendDataResp ?
	       mmio_dataRespQ_enqReq_lat_0$wget[65] :
	       mmio_dataRespQ_enqReq_rl[65] ;
  assign IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 =
	     EN_mmioToPlatform_pRq_enq ?
	       mmio_pRqQ_enqReq_lat_0$wget[39] :
	       mmio_pRqQ_enqReq_rl[39] ;
  assign IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 =
	     EN_mmioToPlatform_pRs_enq ?
	       mmio_pRsQ_enqReq_lat_0$wget[67] :
	       mmio_pRsQ_enqReq_rl[67] ;
  assign IF_rob_deqPort_0_canDeq__4995_THEN_IF_NOT_rob__ETC___d15104 =
	     rob$deqPort_0_canDeq ?
	       y_avValue_snd_snd_snd_snd_snd__h722804 :
	       64'd0 ;
  assign IF_rob_deqPort_0_canDeq__4995_THEN_IF_NOT_rob__ETC___d15194 =
	     rob$deqPort_0_canDeq ? y_avValue_fst__h722364 : 5'd0 ;
  assign IF_rob_deqPort_0_canDeq__4995_THEN_IF_NOT_rob__ETC___d15216 =
	     rob$deqPort_0_canDeq ?
	       y_avValue_snd_snd_snd_fst__h722798 :
	       2'd0 ;
  assign IF_rob_deqPort_1_canDeq__4999_THEN_IF_NOT_rob__ETC___d15208 =
	     rob$deqPort_1_canDeq ?
	       IF_NOT_rob_deqPort_1_deq_data__5002_BIT_25_500_ETC___d15207 :
	       rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ;
  assign IF_sfdin04539_BIT_33_THEN_2_ELSE_0__q57 =
	     sfdin__h404539[33] ? 2'd2 : 2'd0 ;
  assign IF_sfdin16487_BIT_4_THEN_2_ELSE_0__q131 =
	     sfdin__h516487[4] ? 2'd2 : 2'd0 ;
  assign IF_sfdin22305_BIT_33_THEN_2_ELSE_0__q67 =
	     sfdin__h422305[33] ? 2'd2 : 2'd0 ;
  assign IF_sfdin50234_BIT_33_THEN_2_ELSE_0__q92 =
	     sfdin__h450234[33] ? 2'd2 : 2'd0 ;
  assign IF_sfdin55340_BIT_4_THEN_2_ELSE_0__q171 =
	     sfdin__h555340[4] ? 2'd2 : 2'd0 ;
  assign IF_sfdin58842_BIT_33_THEN_2_ELSE_0__q22 =
	     sfdin__h358842[33] ? 2'd2 : 2'd0 ;
  assign IF_sfdin68000_BIT_33_THEN_2_ELSE_0__q102 =
	     sfdin__h468000[33] ? 2'd2 : 2'd0 ;
  assign IF_sfdin76608_BIT_33_THEN_2_ELSE_0__q32 =
	     sfdin__h376608[33] ? 2'd2 : 2'd0 ;
  assign IF_sfdin94644_BIT_4_THEN_2_ELSE_0__q148 =
	     sfdin__h594644[4] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd03429_BIT_4_THEN_2_ELSE_0__q151 =
	     _theResult___snd__h603429[4] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd06867_BIT_4_THEN_2_ELSE_0__q127 =
	     _theResult___snd__h506867[4] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd13152_BIT_33_THEN_2_ELSE_0__q59 =
	     _theResult___snd__h413152[33] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd25272_BIT_4_THEN_2_ELSE_0__q134 =
	     _theResult___snd__h525272[4] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd30942_BIT_33_THEN_2_ELSE_0__q72 =
	     _theResult___snd__h430942[33] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd45720_BIT_4_THEN_2_ELSE_0__q167 =
	     _theResult___snd__h545720[4] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd58847_BIT_33_THEN_2_ELSE_0__q94 =
	     _theResult___snd__h458847[33] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd64125_BIT_4_THEN_2_ELSE_0__q174 =
	     _theResult___snd__h564125[4] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd67455_BIT_33_THEN_2_ELSE_0__q24 =
	     _theResult___snd__h367455[33] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd76637_BIT_33_THEN_2_ELSE_0__q107 =
	     _theResult___snd__h476637[33] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd85024_BIT_4_THEN_2_ELSE_0__q144 =
	     _theResult___snd__h585024[4] ? 2'd2 : 2'd0 ;
  assign IF_theResult___snd85245_BIT_33_THEN_2_ELSE_0__q37 =
	     _theResult___snd__h385245[33] ? 2'd2 : 2'd0 ;
  assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5317 =
	     !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 ||
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5265[2] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5277[2]) ;
  assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5345 =
	     !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 ||
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5265[0] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5277[0]) ;
  assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6709 =
	     !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500 ||
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6657[2] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6669[2]) ;
  assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6737 =
	     !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500 ||
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6657[0] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6669[0]) ;
  assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8101 =
	     !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892 ||
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8049[2] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8061[2]) ;
  assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8129 =
	     !_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892 ||
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8049[0] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8061[0]) ;
  assign NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13442 =
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[1] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[2] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[3] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[4] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[5] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[6] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[7] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[8] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[9] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[10] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[11] &&
	     !checkForException___d13160[4] &&
	     NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13435 &&
	     (fetchStage$pipelines_0_first[231:200] != 32'h10500073 ||
	      !csrf_tw_reg ||
	      csrf_prv_reg == 2'd3) ;
  assign NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13543 =
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[1] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[2] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[3] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[4] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[5] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[6] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[7] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[8] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[9] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[10] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[11] &&
	     !checkForException___d13160[4] &&
	     NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13541 ;
  assign NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13834 =
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[1] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[2] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[3] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[4] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[5] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[6] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[7] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[8] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[9] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[10] &&
	     !IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[11] &&
	     !checkForException___d13807[4] &&
	     NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13832 ;
  assign NOT_IF_NOT_rob_deqPort_0_canDeq__4995_4996_OR__ETC___d15213 =
	     (fflags__h723387 & csrf_fflags_reg) != fflags__h723387 ||
	     !r__h619422 &&
	     (IF_rob_deqPort_1_canDeq__4999_THEN_IF_NOT_rob__ETC___d15208 ||
	      fflags__h723387 != 5'd0) ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167 =
	     !f2_sfd__h526523[21] && !f2_sfd__h526523[20] &&
	     !f2_sfd__h526523[19] &&
	     !f2_sfd__h526523[18] &&
	     !f2_sfd__h526523[17] &&
	     !f2_sfd__h526523[16] &&
	     !f2_sfd__h526523[15] &&
	     !f2_sfd__h526523[14] &&
	     !f2_sfd__h526523[13] &&
	     !f2_sfd__h526523[12] &&
	     !f2_sfd__h526523[11] &&
	     !f2_sfd__h526523[10] &&
	     !f2_sfd__h526523[9] &&
	     !f2_sfd__h526523[8] &&
	     !f2_sfd__h526523[7] &&
	     !f2_sfd__h526523[6] &&
	     !f2_sfd__h526523[5] &&
	     !f2_sfd__h526523[4] &&
	     !f2_sfd__h526523[3] &&
	     !f2_sfd__h526523[2] &&
	     !f2_sfd__h526523[1] &&
	     !f2_sfd__h526523[0] ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 =
	     (f1_exp__h487528 != 8'd255 || f1_sfd__h487529 == 23'd0) &&
	     (f1_exp__h487528 != 8'd255 || f1_sfd__h487529 != 23'd0) &&
	     (f1_exp__h487528 != 8'd0 || f1_sfd__h487529 != 23'd0) &&
	     IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10873 ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10918 =
	     NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 |
	     ((f2_exp__h526522 != 8'd255 || f2_sfd__h526523 == 23'd0) &&
	      (f2_exp__h526522 != 8'd255 || f2_sfd__h526523 != 23'd0) &&
	      (f2_exp__h526522 != 8'd0 || f2_sfd__h526523 != 23'd0) &&
	      IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10914) ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10976 =
	     (f1_exp__h487528 != 8'd255 || f1_sfd__h487529 == 23'd0) &&
	     (f1_exp__h487528 != 8'd255 || f1_sfd__h487529 != 23'd0) &&
	     (f1_exp__h487528 != 8'd0 || f1_sfd__h487529 != 23'd0) &&
	     IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973 ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10987 =
	     NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10976 |
	     ((f2_exp__h526522 != 8'd255 || f2_sfd__h526523 == 23'd0) &&
	      (f2_exp__h526522 != 8'd255 || f2_sfd__h526523 != 23'd0) &&
	      (f2_exp__h526522 != 8'd0 || f2_sfd__h526523 != 23'd0) &&
	      IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10983) ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11016 =
	     (f1_exp__h487528 != 8'd255 || f1_sfd__h487529 == 23'd0) &&
	     (f1_exp__h487528 != 8'd255 || f1_sfd__h487529 != 23'd0) &&
	     (f1_exp__h487528 != 8'd0 || f1_sfd__h487529 != 23'd0) &&
	     IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11013 ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11031 =
	     NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11016 |
	     ((f2_exp__h526522 != 8'd255 || f2_sfd__h526523 == 23'd0) &&
	      (f2_exp__h526522 != 8'd255 || f2_sfd__h526523 != 23'd0) &&
	      (f2_exp__h526522 != 8'd0 || f2_sfd__h526523 != 23'd0) &&
	      IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11027) ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11062 =
	     (f1_exp__h487528 != 8'd255 || f1_sfd__h487529 == 23'd0) &&
	     (f1_exp__h487528 != 8'd255 || f1_sfd__h487529 != 23'd0) &&
	     (f1_exp__h487528 != 8'd0 || f1_sfd__h487529 != 23'd0) &&
	     IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11059 ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11075 =
	     NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11062 |
	     ((f2_exp__h526522 != 8'd255 || f2_sfd__h526523 == 23'd0) &&
	      (f2_exp__h526522 != 8'd255 || f2_sfd__h526523 != 23'd0) &&
	      (f2_exp__h526522 != 8'd0 || f2_sfd__h526523 != 23'd0) &&
	      IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11071) ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11104 =
	     (f1_exp__h487528 != 8'd255 || f1_sfd__h487529 == 23'd0) &&
	     (f1_exp__h487528 != 8'd255 || f1_sfd__h487529 != 23'd0) &&
	     (f1_exp__h487528 != 8'd0 || f1_sfd__h487529 != 23'd0) &&
	     IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11101 ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11117 =
	     NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11104 |
	     ((f2_exp__h526522 != 8'd255 || f2_sfd__h526523 == 23'd0) &&
	      (f2_exp__h526522 != 8'd255 || f2_sfd__h526523 != 23'd0) &&
	      (f2_exp__h526522 != 8'd0 || f2_sfd__h526523 != 23'd0) &&
	      IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11113) ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667 =
	     !f1_sfd__h487529[21] && !f1_sfd__h487529[20] &&
	     !f1_sfd__h487529[19] &&
	     !f1_sfd__h487529[18] &&
	     !f1_sfd__h487529[17] &&
	     !f1_sfd__h487529[16] &&
	     !f1_sfd__h487529[15] &&
	     !f1_sfd__h487529[14] &&
	     !f1_sfd__h487529[13] &&
	     !f1_sfd__h487529[12] &&
	     !f1_sfd__h487529[11] &&
	     !f1_sfd__h487529[10] &&
	     !f1_sfd__h487529[9] &&
	     !f1_sfd__h487529[8] &&
	     !f1_sfd__h487529[7] &&
	     !f1_sfd__h487529[6] &&
	     !f1_sfd__h487529[5] &&
	     !f1_sfd__h487529[4] &&
	     !f1_sfd__h487529[3] &&
	     !f1_sfd__h487529[2] &&
	     !f1_sfd__h487529[1] &&
	     !f1_sfd__h487529[0] ;
  assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397 =
	     !f3_sfd__h565827[21] && !f3_sfd__h565827[20] &&
	     !f3_sfd__h565827[19] &&
	     !f3_sfd__h565827[18] &&
	     !f3_sfd__h565827[17] &&
	     !f3_sfd__h565827[16] &&
	     !f3_sfd__h565827[15] &&
	     !f3_sfd__h565827[14] &&
	     !f3_sfd__h565827[13] &&
	     !f3_sfd__h565827[12] &&
	     !f3_sfd__h565827[11] &&
	     !f3_sfd__h565827[10] &&
	     !f3_sfd__h565827[9] &&
	     !f3_sfd__h565827[8] &&
	     !f3_sfd__h565827[7] &&
	     !f3_sfd__h565827[6] &&
	     !f3_sfd__h565827[5] &&
	     !f3_sfd__h565827[4] &&
	     !f3_sfd__h565827[3] &&
	     !f3_sfd__h565827[2] &&
	     !f3_sfd__h565827[1] &&
	     !f3_sfd__h565827[0] ;
  assign NOT_IF_rob_deqPort_0_deq_data__4466_BITS_97_TO_ETC___d14971 =
	     next_pc__h719526 !=
	     rob_deqPort_0_deq_data__4466_BITS_353_TO_290_4_ETC___d14968 ;
  assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13603 =
	     !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601 &&
	     (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	      specTagManager$canClaim) &&
	     regRenamingTable$rename_0_canRename &&
	     NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548 ;
  assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2366_2_ETC___d12393 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_0_bypassWire_0_wget__2367_BITS__ETC___d12369) &&
	     (!coreFix_aluExe_0_bypassWire_1$whas ||
	      !coreFix_aluExe_0_bypassWire_1_wget__2380_BITS__ETC___d12382) &&
	     (!coreFix_aluExe_0_bypassWire_2$whas ||
	      !coreFix_aluExe_0_bypassWire_2_wget__2388_BITS__ETC___d12390) ;
  assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2366_2_ETC___d12423 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_0_bypassWire_0_wget__2367_BITS__ETC___d12410) &&
	     (!coreFix_aluExe_0_bypassWire_1$whas ||
	      !coreFix_aluExe_0_bypassWire_1_wget__2380_BITS__ETC___d12416) &&
	     (!coreFix_aluExe_0_bypassWire_2$whas ||
	      !coreFix_aluExe_0_bypassWire_2_wget__2388_BITS__ETC___d12420) ;
  assign NOT_coreFix_aluExe_1_bypassWire_0_whas__1510_1_ETC___d11537 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11513) &&
	     (!coreFix_aluExe_0_bypassWire_1$whas ||
	      !coreFix_aluExe_1_bypassWire_1_wget__1524_BITS__ETC___d11526) &&
	     (!coreFix_aluExe_1_bypassWire_2$whas ||
	      !coreFix_aluExe_1_bypassWire_2_wget__1532_BITS__ETC___d11534) ;
  assign NOT_coreFix_aluExe_1_bypassWire_0_whas__1510_1_ETC___d11567 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11554) &&
	     (!coreFix_aluExe_0_bypassWire_1$whas ||
	      !coreFix_aluExe_1_bypassWire_1_wget__1524_BITS__ETC___d11560) &&
	     (!coreFix_aluExe_1_bypassWire_2$whas ||
	      !coreFix_aluExe_1_bypassWire_2_wget__1532_BITS__ETC___d11564) ;
  assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8327 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8303) &&
	     (!coreFix_aluExe_0_bypassWire_1$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_1_wget__314__ETC___d8316) &&
	     (!coreFix_fpuMulDivExe_0_bypassWire_2$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_2_wget__322__ETC___d8324) ;
  assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8356 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8343) &&
	     (!coreFix_aluExe_0_bypassWire_1$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_1_wget__314__ETC___d8349) &&
	     (!coreFix_fpuMulDivExe_0_bypassWire_2$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_2_wget__322__ETC___d8353) ;
  assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8382 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8369) &&
	     (!coreFix_aluExe_0_bypassWire_1$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_1_wget__314__ETC___d8375) &&
	     (!coreFix_fpuMulDivExe_0_bypassWire_2$whas ||
	      !coreFix_fpuMulDivExe_0_bypassWire_2_wget__322__ETC___d8379) ;
  assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911 =
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[53] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[52] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[51] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[50] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[49] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[48] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[47] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[46] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[45] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[44] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[43] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[42] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[41] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[40] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[39] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[38] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[37] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[36] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[35] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[34] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[33] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[32] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[31] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[30] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[29] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[28] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[27] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[26] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[25] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[24] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[23] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[22] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[21] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[20] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[19] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[18] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[17] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[16] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[15] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[14] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[13] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[12] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[11] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[10] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[9] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[8] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ;
  assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519 =
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[53] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[52] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[51] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[50] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[49] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[48] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[47] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[46] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[45] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[44] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[43] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[42] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[41] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[40] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[39] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[38] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[37] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[36] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[35] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[34] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[33] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[32] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[31] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[30] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[29] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[28] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[27] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[26] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[25] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[24] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[23] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[22] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[21] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[20] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[19] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[18] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[17] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[16] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[15] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[14] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[13] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[12] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[11] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[10] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[9] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[8] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ;
  assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303 =
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[55] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[54] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[53] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[52] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[51] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[50] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[49] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[48] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[47] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[46] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[45] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[44] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[43] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[42] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[41] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[40] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[39] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[38] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[37] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[36] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[35] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[34] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[33] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[32] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[31] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[30] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[29] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[28] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[27] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[26] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[25] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[24] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[23] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[22] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[21] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[20] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[19] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[18] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[17] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[16] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[15] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[14] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[13] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[12] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[11] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[10] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[9] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[8] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[7] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[6] &&
	     !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ;
  assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__48_ETC___d8540 =
	     coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] != 3'd3 ||
	     CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q252 ;
  assign NOT_coreFix_fpuMulDivExe_0_rsFpuMulDiv_canEnq__ETC___d13946 =
	     !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
	     fetchStage$pipelines_0_first[68] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[1] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[2] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[3] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[4] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[5] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[6] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[7] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[8] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[9] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[10] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[11] ;
  assign NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1611 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1587) &&
	     (!coreFix_aluExe_0_bypassWire_1$whas ||
	      !coreFix_memExe_bypassWire_1_wget__598_BITS_70__ETC___d1600) &&
	     (!coreFix_memExe_bypassWire_2$whas ||
	      !coreFix_memExe_bypassWire_2_wget__606_BITS_70__ETC___d1608) ;
  assign NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1640 =
	     (!coreFix_aluExe_0_bypassWire_0$whas ||
	      !coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1627) &&
	     (!coreFix_aluExe_0_bypassWire_1$whas ||
	      !coreFix_memExe_bypassWire_1_wget__598_BITS_70__ETC___d1633) &&
	     (!coreFix_memExe_bypassWire_2$whas ||
	      !coreFix_memExe_bypassWire_2_wget__606_BITS_70__ETC___d1637) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2554 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd1) &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2730 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd1) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	      3'd3 ||
	      coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2178) &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
	     2'd0 &&
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3153 =
	     !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT ||
	     !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3174 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT ||
	      (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ?
		 !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[3] :
		 !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[3])) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3142 ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3223 =
	     !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT ||
	     !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3279 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT ||
	      IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3276) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3249 ||
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2100 =
	     !coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT ||
	     !coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT ||
	     !coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] ||
	     !coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2098 ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2151 =
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
	      3'd1 ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	      3'd4 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 ||
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2561 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 ||
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	      3'd3 ||
	      coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2178) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2563 =
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
	      3'd1 ||
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2561) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2585 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd2 ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd3) ||
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd3 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2100 ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2589 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 ||
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd3 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2100 ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2592 =
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd1) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2588 ||
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2589) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2606 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 ||
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2605 ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2609 =
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd1) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2588 ||
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2606) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2620 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	     3'd4 ||
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd3 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2100 ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2626 =
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd1) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 &&
	      (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	       !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	      3'd4 ||
	      NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2589) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2633 =
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd1) &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2658 =
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd1) &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd1 ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2666 =
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd1) &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd4 ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2674 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 ||
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd3 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2100 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2683 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 ||
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	      3'd3 ||
	      coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2178) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
	      2'd0 ||
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2708 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	     3'd0 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	     3'd2 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	     3'd4 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	     3'd3 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	     3'd1 ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2725 =
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd1) &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
	     2'd0 ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2728 =
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd1) &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2726 ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2739 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 ||
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	      3'd3 ||
	      coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2178) &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2737 ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2741 =
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd1) &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2739 ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2747 =
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ||
	     IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2078 &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd4 ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
	      (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	       3'd1 ||
	       coreFix_memExe_stb$RDY_deq)) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2815 =
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2771 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2774 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
	      2'd1 ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82] <=
	      2'd1 ||
	      coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] !=
	      2'd0 ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd3 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot[0]) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1141 =
	     !coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT ||
	     !coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT ||
	     !coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT ||
	     !coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3394 =
	     !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT ||
	     !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3451 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT ||
	      (CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
		 !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[72] :
		 !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[72])) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3420 ||
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty) ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3490 =
	     !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT ||
	     !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl ;
  assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3547 =
	     (!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT ||
	      IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3543) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3516 ||
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty) ;
  assign NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1908 =
	     !coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT ||
	     !coreFix_memExe_dMem_perfReqQ_clearReq_rl ;
  assign NOT_coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_ETC___d1952 =
	     (!coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT ||
	      !coreFix_memExe_dMem_perfReqQ_enqReq_rl[4]) &&
	     (coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT &&
	      coreFix_memExe_dMem_perfReqQ_deqReq_rl ||
	      coreFix_memExe_dMem_perfReqQ_empty) ;
  assign NOT_coreFix_memExe_dTlb_procResp__740_BITS_174_ETC___d1779 =
	     !coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1750 &&
	     coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1751 &&
	     !coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1755 &&
	     !coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1758 ;
  assign NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3813 =
	     !coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT ||
	     !coreFix_memExe_forwardQ_clearReq_rl ;
  assign NOT_coreFix_memExe_forwardQ_enqReq_dummy2_2_re_ETC___d3868 =
	     (!coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT ||
	      (coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
		 !coreFix_memExe_forwardQ_enqReq_lat_0$wget[69] :
		 !coreFix_memExe_forwardQ_enqReq_rl[69])) &&
	     (coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3839 ||
	      coreFix_memExe_forwardQ_empty) ;
  assign NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3719 =
	     !coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT ||
	     !coreFix_memExe_memRespLdQ_clearReq_rl ;
  assign NOT_coreFix_memExe_memRespLdQ_enqReq_dummy2_2__ETC___d3774 =
	     (!coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT ||
	      (coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
		 !coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[69] :
		 !coreFix_memExe_memRespLdQ_enqReq_rl[69])) &&
	     (coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3745 ||
	      coreFix_memExe_memRespLdQ_empty) ;
  assign NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1486 =
	     !coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT ||
	     !coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT ||
	     !coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT ||
	     !coreFix_memExe_reqLdQ_full_rl ;
  assign NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1026 =
	     !coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT ||
	     !coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT ||
	     !coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT ||
	     !coreFix_memExe_reqLrScAmoQ_full_rl ;
  assign NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3643 =
	     !coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT ||
	     !coreFix_memExe_respLrScAmoQ_clearReq_rl ;
  assign NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3685 =
	     (!coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT ||
	      (coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ?
		 !coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[64] :
		 !coreFix_memExe_respLrScAmoQ_enqReq_rl[64])) &&
	     (coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT &&
	      (coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas ||
	       coreFix_memExe_respLrScAmoQ_deqReq_rl) ||
	      coreFix_memExe_respLrScAmoQ_empty) ;
  assign NOT_coreFix_memExe_respLrScAmoQ_full_977_978_A_ETC___d2110 =
	     !coreFix_memExe_respLrScAmoQ_full &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ||
	      !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full) ;
  assign NOT_coreFix_memExe_rsMem_canEnq__3571_3633_OR__ETC___d13947 =
	     !coreFix_memExe_rsMem$canEnq ||
	     IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 ||
	     fetchStage$pipelines_0_first[68] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[1] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[2] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[3] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[4] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[5] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[6] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[7] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[8] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[9] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[10] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[11] ;
  assign NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13435 =
	     (csrf_fs_reg != 2'd0 ||
	      (!fetchStage$pipelines_0_first[95] ||
	       !fetchStage$pipelines_0_first[94]) &&
	      (!fetchStage$pipelines_0_first[88] ||
	       !fetchStage$pipelines_0_first[87]) &&
	      !fetchStage$pipelines_0_first[81] &&
	      (!fetchStage$pipelines_0_first[75] ||
	       !fetchStage$pipelines_0_first[74])) &&
	     (fetchStage$pipelines_0_first[199:195] != 5'd13 ||
	      NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13429 &&
	      !csrf_prv_reg_read__2956_ULT_IF_fetchStage_pipe_ETC___d13192 &&
	      csr_addr__h661843 != 12'h8FF) ;
  assign NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13541 =
	     (csrf_fs_reg != 2'd0 ||
	      (!fetchStage$pipelines_0_first[95] ||
	       !fetchStage$pipelines_0_first[94]) &&
	      (!fetchStage$pipelines_0_first[88] ||
	       !fetchStage$pipelines_0_first[87]) &&
	      !fetchStage$pipelines_0_first[81] &&
	      (!fetchStage$pipelines_0_first[75] ||
	       !fetchStage$pipelines_0_first[74])) &&
	     (fetchStage$pipelines_0_first[231:200] != 32'h10500073 ||
	      !csrf_tw_reg ||
	      csrf_prv_reg == 2'd3) ;
  assign NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13832 =
	     (csrf_fs_reg != 2'd0 ||
	      (!fetchStage$pipelines_1_first[95] ||
	       !fetchStage$pipelines_1_first[94]) &&
	      (!fetchStage$pipelines_1_first[88] ||
	       !fetchStage$pipelines_1_first[87]) &&
	      !fetchStage$pipelines_1_first[81] &&
	      (!fetchStage$pipelines_1_first[75] ||
	       !fetchStage$pipelines_1_first[74])) &&
	     (fetchStage$pipelines_1_first[231:200] != 32'h10500073 ||
	      !csrf_tw_reg ||
	      csrf_prv_reg == 2'd3) ;
  assign NOT_csrf_prv_reg_read__2956_ULE_1_4607_4671_OR_ETC___d14675 =
	     !csrf_prv_reg_read__2956_ULE_1___d14607 ||
	     (commitStage_commitTrap[36] ?
		!_0b0_CONCAT_csrf_mideleg_11_reg_read__1833_1834_ETC___d14625 :
		!_0b0_CONCAT_csrf_medeleg_15_reg_read__1825_1826_ETC___d14644) ;
  assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13918 =
	     (!fetchStage$pipelines_0_canDeq ||
	      fetchStage$RDY_pipelines_0_first) &&
	     (regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598 &&
	      (fetchStage$pipelines_0_first[194:192] == 3'd3 ||
	       fetchStage$pipelines_0_first[194:192] == 3'd4) ||
	      !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
	      !regRenamingTable$rename_1_canRename ||
	      fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13904) ;
  assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13929 =
	     (!fetchStage$pipelines_0_canDeq ||
	      fetchStage$RDY_pipelines_0_first) &&
	     (regRenamingTable_rename_0_canRename__3528_AND__ETC___d13927 ||
	      !regRenamingTable$rename_1_canRename ||
	      fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13904) ;
  assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13968 =
	     !fetchStage$pipelines_0_canDeq ||
	     NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13962 ||
	     fetchStage$pipelines_0_first[194:192] != 3'd3 &&
	     fetchStage$pipelines_0_first[194:192] != 3'd4 ;
  assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13985 =
	     (!fetchStage$pipelines_0_canDeq ||
	      NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13627 ||
	      fetchStage$pipelines_0_first[194:192] != 3'd2 ||
	      IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636) &&
	     coreFix_memExe_rsMem$canEnq &&
	     CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231 ;
  assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14106 =
	     (!fetchStage$pipelines_0_canDeq ||
	      fetchStage$pipelines_0_first[194:192] == 3'd1 &&
	      !specTagManager$canClaim ||
	      NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13962 ||
	      fetchStage$pipelines_0_first[194:192] != 3'd0 &&
	      fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	      !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568) &&
	     coreFix_aluExe_1_rsAlu$canEnq &&
	     !coreFix_aluExe_0_rsAlu_approximateCount__3562__ETC___d13564 ;
  assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14125 =
	     (!fetchStage$pipelines_0_canDeq ||
	      NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14096) &&
	     CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235 &&
	     (fetchStage$pipelines_1_first[199:195] == 5'd14 ||
	      coreFix_memExe_rsMem$RDY_enq) ;
  assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14177 =
	     (!fetchStage$pipelines_0_canDeq ||
	      fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14052 &&
	      IF_fetchStage_RDY_pipelines_0_first__2925_AND__ETC___d13555) &&
	     fetchStage$RDY_pipelines_0_first &&
	     fetchStage_pipelines_0_canDeq__2926_AND_fetchS_ETC___d14175 ;
  assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 =
	     (!fetchStage$pipelines_0_canDeq ||
	      NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183 &&
	      IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13584) &&
	     fetchStage$pipelines_1_canDeq ;
  assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14311 =
	     !fetchStage$pipelines_0_canDeq ||
	     NOT_regRenamingTable_rename_0_canRename__3528__ETC___d14017 ||
	     IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13641 ||
	     fetchStage$pipelines_0_first[194:192] != 3'd1 ;
  assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14322 =
	     NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 &&
	     NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14319 &&
	     (fetchStage$pipelines_1_first[194:192] == 3'd0 ||
	      fetchStage$pipelines_1_first[194:192] == 3'd1) &&
	     SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14091 ;
  assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14358 =
	     !fetchStage$pipelines_0_canDeq ||
	     NOT_regRenamingTable_rename_0_canRename__3528__ETC___d14017 ||
	     fetchStage$pipelines_0_first[194:192] != 3'd3 &&
	     fetchStage$pipelines_0_first[194:192] != 3'd4 ;
  assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14378 =
	     NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 &&
	     regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 &&
	     (fetchStage$pipelines_1_first[194:192] == 3'd3 ||
	      fetchStage$pipelines_1_first[194:192] == 3'd4) &&
	     NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14358 &&
	     coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq &&
	     NOT_fetchStage_pipelines_1_first__2937_BITS_32_ETC___d14373 ;
  assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14386 =
	     (!fetchStage$pipelines_0_canDeq ||
	      NOT_regRenamingTable_rename_0_canRename__3528__ETC___d14017 ||
	      fetchStage$pipelines_0_first[194:192] != 3'd2 ||
	      IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636) &&
	     coreFix_memExe_rsMem$canEnq &&
	     CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231 ;
  assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14407 =
	     NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 &&
	     regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 &&
	     fetchStage$pipelines_1_first[194:192] == 3'd2 &&
	     NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14386 &&
	     fetchStage$pipelines_1_first[173] ;
  assign NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14430 =
	     NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14311 &&
	     specTagManager$canClaim &&
	     regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 &&
	     IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13999 &&
	     fetchStage$pipelines_1_first[194:192] == 3'd1 ;
  assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13429 =
	     (fetchStage$pipelines_0_first[194:192] != 3'd0 ||
	      fetchStage$pipelines_0_first[178:174] != 5'd15) &&
	     rs1__h661844 == 5'd0 &&
	     imm__h661845 == 32'd0 ||
	     csr_addr__h661843[11:10] != 2'b11 ;
  assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548 =
	     fetchStage$pipelines_0_first[199:195] != 5'd0 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd21 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd17 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd18 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd13 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd16 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd15 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd19 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd20 &&
	     !fetchStage$pipelines_0_first[68] &&
	     NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13543 &&
	     rob$enqPort_0_canEnq &&
	     epochManager$checkEpoch_0_check ;
  assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13585 =
	     (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	      specTagManager$canClaim) &&
	     regRenamingTable$rename_0_canRename &&
	     NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548 &&
	     IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13584 ;
  assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13852 =
	     (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	      specTagManager$canClaim) &&
	     regRenamingTable$rename_0_canRename &&
	     NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548 &&
	     fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13851 ;
  assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13858 =
	     (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	      specTagManager$canClaim) &&
	     regRenamingTable$rename_0_canRename &&
	     NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548 &&
	     (fetchStage$pipelines_0_first[194:192] == 3'd0 ||
	      fetchStage$pipelines_0_first[194:192] == 3'd1) &&
	     SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 &&
	     (!coreFix_aluExe_0_rsAlu$canEnq ||
	      !coreFix_aluExe_0_rsAlu_approximateCount__3562__ETC___d13564) ;
  assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14010 =
	     (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	      specTagManager$canClaim) &&
	     regRenamingTable$rename_0_canRename &&
	     NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548 &&
	     IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 ;
  assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183 =
	     (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	      specTagManager$canClaim) &&
	     regRenamingTable$rename_0_canRename &&
	     !checkForException___d13160[4] &&
	     rob$enqPort_0_canEnq ;
  assign NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14283 =
	     { fetchStage$pipelines_0_first[194:192] != 3'd2 ||
	       !coreFix_memExe_rsMem$canEnq ||
	       IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 ||
	       IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14225,
	       (fetchStage$pipelines_0_first[194:192] == 3'd2 &&
		coreFix_memExe_rsMem$canEnq &&
		IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 &&
		IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14228) ?
		 IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14231 :
		 { 1'h0,
		   IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14234 },
	       7'd32,
	       specTagManager$currentSpecBits } ;
  assign NOT_fetchStage_pipelines_0_first__2928_BITS_32_ETC___d14207 =
	     fetchStage$pipelines_0_first[323:260] !=
	     fallthrough_pc__h671324 ;
  assign NOT_fetchStage_pipelines_0_first__2928_BIT_68__ETC___d13596 =
	     !fetchStage$pipelines_0_first[68] &&
	     !checkForException___d13160[4] &&
	     NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13541 &&
	     rob$enqPort_0_canEnq &&
	     epochManager$checkEpoch_0_check ;
  assign NOT_fetchStage_pipelines_1_canDeq__2934_2935_O_ETC___d12943 =
	     !fetchStage$pipelines_1_canDeq ||
	     fetchStage$RDY_pipelines_1_first &&
	     (epochManager$checkEpoch_1_check ||
	      fetchStage$RDY_pipelines_1_deq) ;
  assign NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13843 =
	     fetchStage$pipelines_1_first[199:195] != 5'd0 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd21 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd17 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd18 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd13 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd16 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd15 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd19 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd20 &&
	     !fetchStage$pipelines_1_first[68] &&
	     NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13834 &&
	     rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13841 ;
  assign NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13845 =
	     (fetchStage$pipelines_1_first[194:192] != 3'd1 ||
	      (!fetchStage$pipelines_0_canDeq ||
	       NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13627 ||
	       IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13641 ||
	       fetchStage$pipelines_0_first[194:192] != 3'd1) &&
	      specTagManager$canClaim) &&
	     regRenamingTable$rename_1_canRename &&
	     NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13843 ;
  assign NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13956 =
	     (fetchStage$pipelines_1_first[194:192] != 3'd1 ||
	      (!fetchStage$pipelines_0_canDeq ||
	       NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13627 ||
	       IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13950 ||
	       fetchStage$pipelines_0_first[194:192] != 3'd1) &&
	      specTagManager$canClaim) &&
	     regRenamingTable$rename_1_canRename &&
	     NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13843 ;
  assign NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13977 =
	     fetchStage$pipelines_1_first[199:195] != 5'd0 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd21 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd17 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd18 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd13 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd16 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd15 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd19 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd20 &&
	     !fetchStage$pipelines_1_first[68] &&
	     NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13834 &&
	     rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13975 ;
  assign NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13994 =
	     fetchStage$pipelines_1_first[199:195] != 5'd0 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd21 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd17 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd18 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd13 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd16 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd15 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd19 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd20 &&
	     !fetchStage$pipelines_1_first[68] &&
	     NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13834 &&
	     rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13992 ;
  assign NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14319 =
	     (fetchStage$pipelines_1_first[194:192] != 3'd1 ||
	      NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14311 &&
	      specTagManager$canClaim) &&
	     regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 ;
  assign NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14381 =
	     (fetchStage$pipelines_1_first[194:192] == 3'd3 ||
	      fetchStage$pipelines_1_first[194:192] == 3'd4) &&
	     NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14358 &&
	     coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq &&
	     fetchStage$pipelines_1_first[173] ;
  assign NOT_fetchStage_pipelines_1_first__2937_BITS_32_ETC___d14373 =
	     fetchStage$pipelines_1_first[323:260] !=
	     fallthrough_pc__h687070 ;
  assign NOT_fetchStage_pipelines_1_first__2937_BIT_68__ETC___d14316 =
	     !fetchStage$pipelines_1_first[68] &&
	     !checkForException___d13807[4] &&
	     NOT_csrf_fs_reg_read__1726_EQ_0_3149_3150_OR_N_ETC___d13832 &&
	     rob$enqPort_1_canEnq &&
	     epochManager$checkEpoch_1_check ;
  assign NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 =
	     !mmio_cRqQ_clearReq_dummy2_1$Q_OUT || !mmio_cRqQ_clearReq_rl ;
  assign NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452 =
	     (!mmio_cRqQ_enqReq_dummy2_2$Q_OUT ||
	      (mmio_cRqQ_enqReq_lat_0$whas ?
		 !mmio_cRqQ_enqReq_lat_0$wget[142] :
		 !mmio_cRqQ_enqReq_rl[142])) &&
	     (mmio_cRqQ_deqReq_dummy2_2$Q_OUT &&
	      (EN_mmioToPlatform_cRq_deq || mmio_cRqQ_deqReq_rl) ||
	      mmio_cRqQ_empty) ;
  assign NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 =
	     !mmio_cRsQ_clearReq_dummy2_1$Q_OUT || !mmio_cRsQ_clearReq_rl ;
  assign NOT_mmio_cRsQ_enqReq_dummy2_2_read__24_39_OR_I_ETC___d844 =
	     (!mmio_cRsQ_enqReq_dummy2_2$Q_OUT ||
	      (CAN_FIRE_RL_mmio_handlePRq ?
		 !mmio_cRsQ_enqReq_lat_0$wget[1] :
		 !mmio_cRsQ_enqReq_rl[1])) &&
	     (mmio_cRsQ_deqReq_dummy2_2$Q_OUT &&
	      (EN_mmioToPlatform_cRs_deq || mmio_cRsQ_deqReq_rl) ||
	      mmio_cRsQ_empty) ;
  assign NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1099 =
	     !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ &&
	     coreFix_memExe_lsq$RDY_firstSt &&
	     coreFix_memExe_lsq$RDY_deqSt ;
  assign NOT_mmio_dataPendQ_empty_23_098_AND_rob_RDY_se_ETC___d1400 =
	     !mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ &&
	     coreFix_memExe_lsq$RDY_firstLd &&
	     coreFix_memExe_lsq$RDY_deqLd ;
  assign NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 =
	     (!mmio_dataPendQ_enqReq_dummy2_2$Q_OUT ||
	      !mmio_dataPendQ_enqReq_lat_0$whas &&
	      !mmio_dataPendQ_enqReq_rl) &&
	     (mmio_dataPendQ_deqReq_dummy2_2$Q_OUT &&
	      (mmio_dataRespQ_deqReq_lat_0$whas ||
	       mmio_dataPendQ_deqReq_rl) ||
	      mmio_dataPendQ_empty) ;
  assign NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 =
	     !mmio_dataReqQ_clearReq_dummy2_1$Q_OUT ||
	     !mmio_dataReqQ_clearReq_rl ;
  assign NOT_mmio_dataReqQ_enqReq_dummy2_2_read__41_56__ETC___d161 =
	     (!mmio_dataReqQ_enqReq_dummy2_2$Q_OUT ||
	      (mmio_dataReqQ_enqReq_lat_0$whas ?
		 !mmio_dataReqQ_enqReq_lat_0$wget[142] :
		 !mmio_dataReqQ_enqReq_rl[142])) &&
	     (mmio_dataReqQ_deqReq_dummy2_2$Q_OUT &&
	      (CAN_FIRE_RL_mmio_sendDataReq || mmio_dataReqQ_deqReq_rl) ||
	      mmio_dataReqQ_empty) ;
  assign NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 =
	     !mmio_dataRespQ_clearReq_dummy2_1$Q_OUT ||
	     !mmio_dataRespQ_clearReq_rl ;
  assign NOT_mmio_dataRespQ_enqReq_dummy2_2_read__42_57_ETC___d262 =
	     (!mmio_dataRespQ_enqReq_dummy2_2$Q_OUT ||
	      (CAN_FIRE_RL_mmio_sendDataResp ?
		 !mmio_dataRespQ_enqReq_lat_0$wget[65] :
		 !mmio_dataRespQ_enqReq_rl[65])) &&
	     (mmio_dataRespQ_deqReq_dummy2_2$Q_OUT &&
	      (mmio_dataRespQ_deqReq_lat_0$whas ||
	       mmio_dataRespQ_deqReq_rl) ||
	      mmio_dataRespQ_empty) ;
  assign NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 =
	     !mmio_pRqQ_clearReq_dummy2_1$Q_OUT || !mmio_pRqQ_clearReq_rl ;
  assign NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755 =
	     (!mmio_pRqQ_enqReq_dummy2_2$Q_OUT ||
	      (EN_mmioToPlatform_pRq_enq ?
		 !mmio_pRqQ_enqReq_lat_0$wget[39] :
		 !mmio_pRqQ_enqReq_rl[39])) &&
	     (mmio_pRqQ_deqReq_dummy2_2$Q_OUT &&
	      (CAN_FIRE_RL_mmio_handlePRq || mmio_pRqQ_deqReq_rl) ||
	      mmio_pRqQ_empty) ;
  assign NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 =
	     !mmio_pRsQ_clearReq_dummy2_1$Q_OUT || !mmio_pRsQ_clearReq_rl ;
  assign NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614 =
	     (!mmio_pRsQ_enqReq_dummy2_2$Q_OUT ||
	      (EN_mmioToPlatform_pRs_enq ?
		 !mmio_pRsQ_enqReq_lat_0$wget[67] :
		 !mmio_pRsQ_enqReq_rl[67])) &&
	     (mmio_pRsQ_deqReq_dummy2_2$Q_OUT &&
	      (mmio_pRsQ_deqReq_lat_0$whas || mmio_pRsQ_deqReq_rl) ||
	      mmio_pRsQ_empty) ;
  assign NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13627 =
	     !regRenamingTable$rename_0_canRename ||
	     fetchStage$pipelines_0_first[199:195] == 5'd0 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd21 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd17 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd18 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd13 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd16 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd15 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd19 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd20 ||
	     fetchStage_pipelines_0_first__2928_BIT_68_2955_ETC___d13625 ;
  assign NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13962 =
	     !regRenamingTable$rename_0_canRename ||
	     fetchStage$pipelines_0_first[199:195] == 5'd0 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd21 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd17 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd18 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd13 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd16 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd15 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd19 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd20 ||
	     fetchStage_pipelines_0_first__2928_BIT_68_2955_ETC___d13625 ;
  assign NOT_regRenamingTable_rename_0_canRename__3528__ETC___d14017 =
	     !regRenamingTable$rename_0_canRename ||
	     fetchStage$pipelines_0_first[68] ||
	     checkForException___d13160[4] ||
	     !rob$enqPort_0_canEnq ;
  assign NOT_regRenamingTable_rename_1_canRename__3647__ETC___d14075 =
	     !regRenamingTable$rename_1_canRename ||
	     fetchStage$pipelines_1_first[199:195] == 5'd0 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd21 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd17 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd18 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd13 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd16 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd15 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd19 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd20 ||
	     fetchStage_pipelines_1_first__2937_BIT_68_3675_ETC___d14073 ;
  assign NOT_rob_deqPort_0_canDeq__4995_4996_OR_regRena_ETC___d15034 =
	     (!rob$deqPort_0_canDeq ||
	      regRenamingTable$RDY_commit_0_commit &&
	      rob$RDY_deqPort_0_deq) &&
	     (!rob$deqPort_1_canDeq ||
	      rob$RDY_deqPort_1_deq_data &&
	      NOT_rob_deqPort_1_deq_data__5002_BIT_25_5003_5_ETC___d15031) ;
  assign NOT_rob_deqPort_0_canDeq__4995_4996_OR_rob_deq_ETC___d15187 =
	     (!rob$deqPort_0_canDeq ||
	      rob$deqPort_0_deq_data[25] && !rob$deqPort_0_deq_data[18] &&
	      !rob$deqPort_0_deq_data[167] &&
	      rob$deqPort_0_deq_data[257:253] != 5'd0 &&
	      rob$deqPort_0_deq_data[257:253] != 5'd21 &&
	      rob$deqPort_0_deq_data[257:253] != 5'd17 &&
	      rob$deqPort_0_deq_data[257:253] != 5'd18 &&
	      rob$deqPort_0_deq_data[257:253] != 5'd13 &&
	      rob$deqPort_0_deq_data[257:253] != 5'd16 &&
	      rob$deqPort_0_deq_data[257:253] != 5'd15 &&
	      rob$deqPort_0_deq_data[257:253] != 5'd19 &&
	      rob$deqPort_0_deq_data[257:253] != 5'd20) &&
	     rob$deqPort_1_canDeq ;
  assign NOT_rob_deqPort_0_deq_data__4466_BITS_257_TO_2_ETC___d14788 =
	     rob$deqPort_0_deq_data[257:253] != 5'd13 ||
	     (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 !=
	      6'd7 ||
	      csrf_stats_module_writeQ$FULL_N) &&
	     (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 !=
	      6'd6 ||
	      csrf_terminate_module_terminateQ$FULL_N) ;
  assign NOT_rob_deqPort_0_deq_data__4466_BITS_257_TO_2_ETC___d14981 =
	     (rob$deqPort_0_deq_data[257:253] == 5'd13) !=
	     rob$deqPort_0_deq_data[181] ;
  assign NOT_rob_deqPort_1_deq_data__5002_BIT_25_5003_5_ETC___d15031 =
	     !rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
	     rob$deqPort_1_deq_data[167] ||
	     rob$deqPort_1_deq_data[257:253] == 5'd0 ||
	     rob$deqPort_1_deq_data[257:253] == 5'd21 ||
	     rob$deqPort_1_deq_data[257:253] == 5'd17 ||
	     rob$deqPort_1_deq_data[257:253] == 5'd18 ||
	     rob$deqPort_1_deq_data[257:253] == 5'd13 ||
	     rob$deqPort_1_deq_data[257:253] == 5'd16 ||
	     rob$deqPort_1_deq_data[257:253] == 5'd15 ||
	     rob$deqPort_1_deq_data[257:253] == 5'd19 ||
	     rob$deqPort_1_deq_data[257:253] == 5'd20 ||
	     regRenamingTable$RDY_commit_1_commit && rob$RDY_deqPort_1_deq ;
  assign NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14096 =
	     !specTagManager$canClaim ||
	     NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13962 ||
	     IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14043 ||
	     fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	     specTagManager$RDY_nextSpecTag ;
  assign NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14161 =
	     !specTagManager$canClaim ||
	     NOT_regRenamingTable_rename_0_canRename__3528__ETC___d14017 ||
	     IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14043 ||
	     fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	     specTagManager$RDY_nextSpecTag ;
  assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3013 =
	     { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q15,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q16,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q17,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q18 } ;
  assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3022 =
	     { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3013,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q19,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q20 } ;
  assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3031 =
	     { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3022,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q243,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q244 } ;
  assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3038 =
	     { CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250,
	       !CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251,
	       SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d3031,
	       x__h296163 } ;
  assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15335 =
	     { CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255 } ;
  assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15291 =
	     { CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q236,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q237,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q238,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q239 } ;
  assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15300 =
	     { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15291,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q240,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q241 } ;
  assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15309 =
	     { SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15300,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245,
	       CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 } ;
  assign SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13907 =
	     SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13877 ||
	     fetchStage$pipelines_1_first[194:192] == 3'd1 &&
	     regRenamingTable_rename_0_canRename__3528_AND__ETC___d13612 ||
	     !regRenamingTable$rename_1_canRename ||
	     fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13904 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10242 =
	     { {4{f2_exp26522_MINUS_127__q168[7]}},
	       f2_exp26522_MINUS_127__q168 } ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 =
	     (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10242 ^
	      12'h800) <=
	     12'd3071 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 =
	     (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10242 ^
	      12'h800) <
	     12'd1026 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11187 =
	     b__h608522 * b__h608598 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d11200 =
	     b__h608522 * b__h608711 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8757 =
	     { {4{f1_exp87528_MINUS_127__q128[7]}},
	       f1_exp87528_MINUS_127__q128 } ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 =
	     (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8757 ^
	      12'h800) <=
	     12'd3071 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 =
	     (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8757 ^
	      12'h800) <
	     12'd1026 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9472 =
	     { {4{f3_exp65826_MINUS_127__q145[7]}},
	       f3_exp65826_MINUS_127__q145 } ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 =
	     (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9472 ^
	      12'h800) <=
	     12'd3071 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 =
	     (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9472 ^
	      12'h800) <
	     12'd1026 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8757 +
	     12'd1023 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q132 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129[10:0] -
	     11'd1023 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q146 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9472 +
	     12'd1023 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q149 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q146[10:0] -
	     11'd1023 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10242 +
	     12'd1023 ;
  assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q172 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169[10:0] -
	     11'd1023 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6039 =
	     { coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q64[10],
	       coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q64 } ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 =
	     (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6039 ^
	      12'h800) <=
	     12'd2175 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 =
	     (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6039 ^
	      12'h800) <
	     12'd1922 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6039 +
	     12'd127 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q70 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] -
	     8'd127 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4647 =
	     { coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q29[10],
	       coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q29 } ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 =
	     (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4647 ^
	      12'h800) <=
	     12'd2175 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 =
	     (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4647 ^
	      12'h800) <
	     12'd1922 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4647 +
	     12'd127 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q35 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] -
	     8'd127 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7431 =
	     { coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q99[10],
	       coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q99 } ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 =
	     (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7431 ^
	      12'h800) <=
	     12'd2175 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 =
	     (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7431 ^
	      12'h800) <
	     12'd1922 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7431 +
	     12'd127 ;
  assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q105 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] -
	     8'd127 ;
  assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4345 =
	     ({ 3'd0,
		IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343 } ^
	      9'h100) <=
	     9'd256 ;
  assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5265 =
	     { 3'd0,
	       _theResult___fst_exp__h358848 == 8'd0 &&
	       (sfdin__h358842[56:34] == 23'd0 || guard__h350747 != 2'b0),
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h359445 == 8'd255 &&
	       _theResult___fst_sfd__h359446 == 23'd0,
	       1'd0,
	       _theResult___fst_exp__h358848 != 8'd255 &&
	       guard__h350747 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5737 =
	     ({ 3'd0,
		IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 } ^
	      9'h100) <=
	     9'd256 ;
  assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6657 =
	     { 3'd0,
	       _theResult___fst_exp__h404545 == 8'd0 &&
	       (sfdin__h404539[56:34] == 23'd0 || guard__h396446 != 2'b0),
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h405142 == 8'd255 &&
	       _theResult___fst_sfd__h405143 == 23'd0,
	       1'd0,
	       _theResult___fst_exp__h404545 != 8'd255 &&
	       guard__h396446 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7129 =
	     ({ 3'd0,
		IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 } ^
	      9'h100) <=
	     9'd256 ;
  assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8049 =
	     { 3'd0,
	       _theResult___fst_exp__h450240 == 8'd0 &&
	       (sfdin__h450234[56:34] == 23'd0 || guard__h442141 != 2'b0),
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h450837 == 8'd255 &&
	       _theResult___fst_sfd__h450838 == 23'd0,
	       1'd0,
	       _theResult___fst_exp__h450240 != 8'd255 &&
	       guard__h442141 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10493 =
	     ({ 6'd0,
		IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10491 } ^
	      12'h800) <=
	     12'd2048 ;
  assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10869 =
	     { 3'd0,
	       _theResult___fst_exp__h516493 == 11'd0 &&
	       (sfdin__h516487[56:5] == 52'd0 || guard__h508267 != 2'b0),
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h517325 == 11'd2047 &&
	       _theResult___fst_sfd__h517326 == 52'd0,
	       1'd0,
	       _theResult___fst_exp__h516493 != 11'd2047 &&
	       guard__h508267 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10910 =
	     { 3'd0,
	       _theResult___fst_exp__h555346 == 11'd0 &&
	       (sfdin__h555340[56:5] == 52'd0 || guard__h547120 != 2'b0),
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h556178 == 11'd2047 &&
	       _theResult___fst_sfd__h556179 == 52'd0,
	       1'd0,
	       _theResult___fst_exp__h555346 != 11'd2047 &&
	       guard__h547120 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10954 =
	     { 3'd0,
	       _theResult___fst_exp__h594650 == 11'd0 &&
	       (sfdin__h594644[56:5] == 52'd0 || guard__h586424 != 2'b0),
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h595482 == 11'd2047 &&
	       _theResult___fst_sfd__h595483 == 52'd0,
	       1'd0,
	       _theResult___fst_exp__h594650 != 11'd2047 &&
	       guard__h586424 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9008 =
	     ({ 6'd0,
		IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9006 } ^
	      12'h800) <=
	     12'd2048 ;
  assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9723 =
	     ({ 6'd0,
		IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9721 } ^
	      12'h800) <=
	     12'd2048 ;
  assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4896 =
	     ({ 3'd0,
		IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4894 } ^
	      9'h100) <=
	     9'd256 ;
  assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5294 =
	     { 3'd0,
	       _theResult___fst_exp__h376614 == 8'd0 &&
	       (sfdin__h376608[56:34] == 23'd0 || guard__h368386 != 2'b0),
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h377211 == 8'd255 &&
	       _theResult___fst_sfd__h377212 == 23'd0,
	       1'd0,
	       _theResult___fst_exp__h376614 != 8'd255 &&
	       guard__h368386 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6288 =
	     ({ 3'd0,
		IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 } ^
	      9'h100) <=
	     9'd256 ;
  assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6686 =
	     { 3'd0,
	       _theResult___fst_exp__h422311 == 8'd0 &&
	       (sfdin__h422305[56:34] == 23'd0 || guard__h414083 != 2'b0),
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h422908 == 8'd255 &&
	       _theResult___fst_sfd__h422909 == 23'd0,
	       1'd0,
	       _theResult___fst_exp__h422311 != 8'd255 &&
	       guard__h414083 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7680 =
	     ({ 3'd0,
		IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 } ^
	      9'h100) <=
	     9'd256 ;
  assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d8078 =
	     { 3'd0,
	       _theResult___fst_exp__h468006 == 8'd0 &&
	       (sfdin__h468000[56:34] == 23'd0 || guard__h459778 != 2'b0),
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h468603 == 8'd255 &&
	       _theResult___fst_sfd__h468604 == 23'd0,
	       1'd0,
	       _theResult___fst_exp__h468006 != 8'd255 &&
	       guard__h459778 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10196 =
	     ({ 6'd0,
		IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 } ^
	      12'h800) <=
	     12'd2944 ;
  assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10543 =
	     ({ 6'd0,
		IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 } ^
	      12'h800) <=
	     (IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10542 ^
	      12'h800) ;
  assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10852 =
	     { 3'd0,
	       _theResult___fst_exp__h506916 == 11'd0 &&
	       guard__h498955 != 2'b0,
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h507674 == 11'd2047 &&
	       _theResult___fst_sfd__h507675 == 52'd0,
	       1'd0,
	       _theResult___fst_exp__h506916 != 11'd2047 &&
	       guard__h498955 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10893 =
	     { 3'd0,
	       _theResult___fst_exp__h545769 == 11'd0 &&
	       guard__h537808 != 2'b0,
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h546527 == 11'd2047 &&
	       _theResult___fst_sfd__h546528 == 52'd0,
	       1'd0,
	       _theResult___fst_exp__h545769 != 11'd2047 &&
	       guard__h537808 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10937 =
	     { 3'd0,
	       _theResult___fst_exp__h585073 == 11'd0 &&
	       guard__h577112 != 2'b0,
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h585831 == 11'd2047 &&
	       _theResult___fst_sfd__h585832 == 52'd0,
	       1'd0,
	       _theResult___fst_exp__h585073 != 11'd2047 &&
	       guard__h577112 != 2'b0 } ;
  assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8696 =
	     ({ 6'd0,
		IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 } ^
	      12'h800) <=
	     12'd2944 ;
  assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9058 =
	     ({ 6'd0,
		IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 } ^
	      12'h800) <=
	     (IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9057 ^
	      12'h800) ;
  assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9426 =
	     ({ 6'd0,
		IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9424 } ^
	      12'h800) <=
	     12'd2944 ;
  assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9773 =
	     ({ 6'd0,
		IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9424 } ^
	      12'h800) <=
	     (IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9772 ^
	      12'h800) ;
  assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4576 =
	     ({ 3'd0,
		IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 } ^
	      9'h100) <=
	     9'd384 ;
  assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4969 =
	     ({ 3'd0,
		IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 } ^
	      9'h100) <=
	     (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4968 ^
	      9'h100) ;
  assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5277 =
	     { 3'd0,
	       _theResult___fst_exp__h367504 == 8'd0 &&
	       guard__h359456 != 2'b0,
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h368027 == 8'd255 &&
	       _theResult___fst_sfd__h368028 == 23'd0,
	       1'd0,
	       _theResult___fst_exp__h367504 != 8'd255 &&
	       guard__h359456 != 2'b0 } ;
  assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5968 =
	     ({ 3'd0,
		IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 } ^
	      9'h100) <=
	     9'd384 ;
  assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6361 =
	     ({ 3'd0,
		IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 } ^
	      9'h100) <=
	     (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360 ^
	      9'h100) ;
  assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6669 =
	     { 3'd0,
	       _theResult___fst_exp__h413201 == 8'd0 &&
	       guard__h405153 != 2'b0,
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h413724 == 8'd255 &&
	       _theResult___fst_sfd__h413725 == 23'd0,
	       1'd0,
	       _theResult___fst_exp__h413201 != 8'd255 &&
	       guard__h405153 != 2'b0 } ;
  assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7360 =
	     ({ 3'd0,
		IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 } ^
	      9'h100) <=
	     9'd384 ;
  assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7753 =
	     ({ 3'd0,
		IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 } ^
	      9'h100) <=
	     (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752 ^
	      9'h100) ;
  assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8061 =
	     { 3'd0,
	       _theResult___fst_exp__h458896 == 8'd0 &&
	       guard__h450848 != 2'b0,
	       1'd0 } |
	     { 2'd0,
	       _theResult___fst_exp__h459419 == 8'd255 &&
	       _theResult___fst_sfd__h459420 == 23'd0,
	       1'd0,
	       _theResult___fst_exp__h458896 != 8'd255 &&
	       guard__h450848 != 2'b0 } ;
  assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d11193 =
	     b__h608699 * b__h608711 ;
  assign _0_OR_NOT_fetchStage_pipelines_0_first__2928_BI_ETC___d14024 =
	     (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	      specTagManager$RDY_nextSpecTag) &&
	     CASE_k75032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 ;
  assign _0_OR_NOT_fetchStage_pipelines_1_first__2937_BI_ETC___d14109 =
	     (fetchStage$pipelines_1_first[194:192] != 3'd1 ||
	      specTagManager$RDY_nextSpecTag) &&
	     CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q234 ;
  assign _0_OR_fetchStage_RDY_pipelines_0_first__2925_39_ETC___d13932 =
	     fetchStage$RDY_pipelines_0_first &&
	     fetchStage$pipelines_1_first[194:192] == 3'd1 &&
	     regRenamingTable_rename_0_canRename__3528_AND__ETC___d13612 ||
	     !regRenamingTable$rename_1_canRename ||
	     fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13904 ;
  assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10249 =
	     sfd__h526884 >>
	     _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10245 ;
  assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8764 =
	     sfd__h487890 >>
	     _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8760 ;
  assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9479 =
	     sfd__h566188 >>
	     _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9475 ;
  assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4654 =
	     sfd__h343132 >>
	     (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650[11] ?
		12'hAAA :
		_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650) ;
  assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6046 =
	     sfd__h388834 >>
	     (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042[11] ?
		12'hAAA :
		_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042) ;
  assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7438 =
	     sfd__h434529 >>
	     (_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434[11] ?
		12'hAAA :
		_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434) ;
  assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1825_1826_ETC___d14644 =
	     medeleg_csr__read__h617229[i__h708713] ;
  assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1833_1834_ETC___d14625 =
	     mideleg_csr__read__h617324[i__h708873] ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4107 =
	     12'd3074 -
	     { 6'd0,
	       coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] ?
		 6'd0 :
		 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] ?
		    6'd1 :
		    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] ?
		       6'd2 :
		       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[53] ?
			  6'd3 :
			  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[52] ?
			     6'd4 :
			     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[51] ?
				6'd5 :
				(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[50] ?
				   6'd6 :
				   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[49] ?
				      6'd7 :
				      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[48] ?
					 6'd8 :
					 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[47] ?
					    6'd9 :
					    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[46] ?
					       6'd10 :
					       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[45] ?
						  6'd11 :
						  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[44] ?
						     6'd12 :
						     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[43] ?
							6'd13 :
							(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[42] ?
							   6'd14 :
							   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[41] ?
							      6'd15 :
							      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[40] ?
								 6'd16 :
								 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[39] ?
								    6'd17 :
								    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[38] ?
								       6'd18 :
								       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[37] ?
									  6'd19 :
									  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[36] ?
									     6'd20 :
									     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[35] ?
										6'd21 :
										(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[34] ?
										   6'd22 :
										   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[33] ?
										      6'd23 :
										      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[32] ?
											 6'd24 :
											 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[31] ?
											    6'd25 :
											    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[30] ?
											       6'd26 :
											       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[29] ?
												  6'd27 :
												  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[28] ?
												     6'd28 :
												     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[27] ?
													6'd29 :
													(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[26] ?
													   6'd30 :
													   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[25] ?
													      6'd31 :
													      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[24] ?
														 6'd32 :
														 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[23] ?
														    6'd33 :
														    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[22] ?
														       6'd34 :
														       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[21] ?
															  6'd35 :
															  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[20] ?
															     6'd36 :
															     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[19] ?
																6'd37 :
																(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[18] ?
																   6'd38 :
																   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[17] ?
																      6'd39 :
																      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[16] ?
																	 6'd40 :
																	 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[15] ?
																	    6'd41 :
																	    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[14] ?
																	       6'd42 :
																	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[13] ?
																		  6'd43 :
																		  (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[12] ?
																		     6'd44 :
																		     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[11] ?
																			6'd45 :
																			(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[10] ?
																			   6'd46 :
																			   (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[9] ?
																			      6'd47 :
																			      (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[8] ?
																				 6'd48 :
																				 (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] ?
																				    6'd49 :
																				    (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] ?
																				       6'd50 :
																				       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ?
																					  6'd51 :
																					  6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 =
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4107 ^
	      12'h800) <=
	     12'd2175 ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 =
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4107 ^
	      12'h800) <
	     12'd1922 ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5280 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 &&
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5265[4] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5277[4]) ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5305 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 &&
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5265[3] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5277[3]) ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5332 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 &&
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5265[1] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5277[1]) ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5499 =
	     12'd3074 -
	     { 6'd0,
	       coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] ?
		 6'd0 :
		 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] ?
		    6'd1 :
		    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] ?
		       6'd2 :
		       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[53] ?
			  6'd3 :
			  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[52] ?
			     6'd4 :
			     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[51] ?
				6'd5 :
				(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[50] ?
				   6'd6 :
				   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[49] ?
				      6'd7 :
				      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[48] ?
					 6'd8 :
					 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[47] ?
					    6'd9 :
					    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[46] ?
					       6'd10 :
					       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[45] ?
						  6'd11 :
						  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[44] ?
						     6'd12 :
						     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[43] ?
							6'd13 :
							(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[42] ?
							   6'd14 :
							   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[41] ?
							      6'd15 :
							      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[40] ?
								 6'd16 :
								 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[39] ?
								    6'd17 :
								    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[38] ?
								       6'd18 :
								       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[37] ?
									  6'd19 :
									  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[36] ?
									     6'd20 :
									     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[35] ?
										6'd21 :
										(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[34] ?
										   6'd22 :
										   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[33] ?
										      6'd23 :
										      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[32] ?
											 6'd24 :
											 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[31] ?
											    6'd25 :
											    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[30] ?
											       6'd26 :
											       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[29] ?
												  6'd27 :
												  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[28] ?
												     6'd28 :
												     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[27] ?
													6'd29 :
													(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[26] ?
													   6'd30 :
													   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[25] ?
													      6'd31 :
													      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[24] ?
														 6'd32 :
														 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[23] ?
														    6'd33 :
														    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[22] ?
														       6'd34 :
														       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[21] ?
															  6'd35 :
															  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[20] ?
															     6'd36 :
															     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[19] ?
																6'd37 :
																(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[18] ?
																   6'd38 :
																   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[17] ?
																      6'd39 :
																      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[16] ?
																	 6'd40 :
																	 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[15] ?
																	    6'd41 :
																	    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[14] ?
																	       6'd42 :
																	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[13] ?
																		  6'd43 :
																		  (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[12] ?
																		     6'd44 :
																		     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[11] ?
																			6'd45 :
																			(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[10] ?
																			   6'd46 :
																			   (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[9] ?
																			      6'd47 :
																			      (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[8] ?
																				 6'd48 :
																				 (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] ?
																				    6'd49 :
																				    (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] ?
																				       6'd50 :
																				       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ?
																					  6'd51 :
																					  6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500 =
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5499 ^
	      12'h800) <=
	     12'd2175 ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 =
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5499 ^
	      12'h800) <
	     12'd1922 ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6672 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500 &&
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6657[4] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6669[4]) ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6697 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500 &&
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6657[3] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6669[3]) ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6724 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500 &&
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6657[1] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6669[1]) ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6891 =
	     12'd3074 -
	     { 6'd0,
	       coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] ?
		 6'd0 :
		 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[55] ?
		    6'd1 :
		    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[54] ?
		       6'd2 :
		       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[53] ?
			  6'd3 :
			  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[52] ?
			     6'd4 :
			     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[51] ?
				6'd5 :
				(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[50] ?
				   6'd6 :
				   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[49] ?
				      6'd7 :
				      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[48] ?
					 6'd8 :
					 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[47] ?
					    6'd9 :
					    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[46] ?
					       6'd10 :
					       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[45] ?
						  6'd11 :
						  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[44] ?
						     6'd12 :
						     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[43] ?
							6'd13 :
							(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[42] ?
							   6'd14 :
							   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[41] ?
							      6'd15 :
							      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[40] ?
								 6'd16 :
								 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[39] ?
								    6'd17 :
								    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[38] ?
								       6'd18 :
								       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[37] ?
									  6'd19 :
									  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[36] ?
									     6'd20 :
									     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[35] ?
										6'd21 :
										(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[34] ?
										   6'd22 :
										   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[33] ?
										      6'd23 :
										      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[32] ?
											 6'd24 :
											 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[31] ?
											    6'd25 :
											    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[30] ?
											       6'd26 :
											       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[29] ?
												  6'd27 :
												  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[28] ?
												     6'd28 :
												     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[27] ?
													6'd29 :
													(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[26] ?
													   6'd30 :
													   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[25] ?
													      6'd31 :
													      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[24] ?
														 6'd32 :
														 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[23] ?
														    6'd33 :
														    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[22] ?
														       6'd34 :
														       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[21] ?
															  6'd35 :
															  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[20] ?
															     6'd36 :
															     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[19] ?
																6'd37 :
																(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[18] ?
																   6'd38 :
																   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[17] ?
																      6'd39 :
																      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[16] ?
																	 6'd40 :
																	 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[15] ?
																	    6'd41 :
																	    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[14] ?
																	       6'd42 :
																	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[13] ?
																		  6'd43 :
																		  (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[12] ?
																		     6'd44 :
																		     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[11] ?
																			6'd45 :
																			(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[10] ?
																			   6'd46 :
																			   (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[9] ?
																			      6'd47 :
																			      (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[8] ?
																				 6'd48 :
																				 (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[7] ?
																				    6'd49 :
																				    (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[6] ?
																				       6'd50 :
																				       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ?
																					  6'd51 :
																					  6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892 =
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6891 ^
	      12'h800) <=
	     12'd2175 ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 =
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6891 ^
	      12'h800) <
	     12'd1922 ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8064 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892 &&
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8049[4] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8061[4]) ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8089 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892 &&
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8049[3] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8061[3]) ;
  assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8116 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892 &&
	     (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ?
		_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d8049[1] :
		_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d8061[1]) ;
  assign _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10245 =
	     12'd3074 -
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10242 ;
  assign _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8760 =
	     12'd3074 -
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8757 ;
  assign _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9475 =
	     12'd3074 -
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9472 ;
  assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10120 =
	     12'd3970 -
	     { 7'd0,
	       f2_sfd__h526523[22] ?
		 5'd0 :
		 (f2_sfd__h526523[21] ?
		    5'd1 :
		    (f2_sfd__h526523[20] ?
		       5'd2 :
		       (f2_sfd__h526523[19] ?
			  5'd3 :
			  (f2_sfd__h526523[18] ?
			     5'd4 :
			     (f2_sfd__h526523[17] ?
				5'd5 :
				(f2_sfd__h526523[16] ?
				   5'd6 :
				   (f2_sfd__h526523[15] ?
				      5'd7 :
				      (f2_sfd__h526523[14] ?
					 5'd8 :
					 (f2_sfd__h526523[13] ?
					    5'd9 :
					    (f2_sfd__h526523[12] ?
					       5'd10 :
					       (f2_sfd__h526523[11] ?
						  5'd11 :
						  (f2_sfd__h526523[10] ?
						     5'd12 :
						     (f2_sfd__h526523[9] ?
							5'd13 :
							(f2_sfd__h526523[8] ?
							   5'd14 :
							   (f2_sfd__h526523[7] ?
							      5'd15 :
							      (f2_sfd__h526523[6] ?
								 5'd16 :
								 (f2_sfd__h526523[5] ?
								    5'd17 :
								    (f2_sfd__h526523[4] ?
								       5'd18 :
								       (f2_sfd__h526523[3] ?
									  5'd19 :
									  (f2_sfd__h526523[2] ?
									     5'd20 :
									     (f2_sfd__h526523[1] ?
										5'd21 :
										(f2_sfd__h526523[0] ?
										   5'd22 :
										   5'd23)))))))))))))))))))))) } ;
  assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 =
	     (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10120 ^
	      12'h800) <=
	     12'd3071 ;
  assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 =
	     (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10120 ^
	      12'h800) <
	     12'd1026 ;
  assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8620 =
	     12'd3970 -
	     { 7'd0,
	       f1_sfd__h487529[22] ?
		 5'd0 :
		 (f1_sfd__h487529[21] ?
		    5'd1 :
		    (f1_sfd__h487529[20] ?
		       5'd2 :
		       (f1_sfd__h487529[19] ?
			  5'd3 :
			  (f1_sfd__h487529[18] ?
			     5'd4 :
			     (f1_sfd__h487529[17] ?
				5'd5 :
				(f1_sfd__h487529[16] ?
				   5'd6 :
				   (f1_sfd__h487529[15] ?
				      5'd7 :
				      (f1_sfd__h487529[14] ?
					 5'd8 :
					 (f1_sfd__h487529[13] ?
					    5'd9 :
					    (f1_sfd__h487529[12] ?
					       5'd10 :
					       (f1_sfd__h487529[11] ?
						  5'd11 :
						  (f1_sfd__h487529[10] ?
						     5'd12 :
						     (f1_sfd__h487529[9] ?
							5'd13 :
							(f1_sfd__h487529[8] ?
							   5'd14 :
							   (f1_sfd__h487529[7] ?
							      5'd15 :
							      (f1_sfd__h487529[6] ?
								 5'd16 :
								 (f1_sfd__h487529[5] ?
								    5'd17 :
								    (f1_sfd__h487529[4] ?
								       5'd18 :
								       (f1_sfd__h487529[3] ?
									  5'd19 :
									  (f1_sfd__h487529[2] ?
									     5'd20 :
									     (f1_sfd__h487529[1] ?
										5'd21 :
										(f1_sfd__h487529[0] ?
										   5'd22 :
										   5'd23)))))))))))))))))))))) } ;
  assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 =
	     (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8620 ^
	      12'h800) <=
	     12'd3071 ;
  assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 =
	     (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8620 ^
	      12'h800) <
	     12'd1026 ;
  assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9350 =
	     12'd3970 -
	     { 7'd0,
	       f3_sfd__h565827[22] ?
		 5'd0 :
		 (f3_sfd__h565827[21] ?
		    5'd1 :
		    (f3_sfd__h565827[20] ?
		       5'd2 :
		       (f3_sfd__h565827[19] ?
			  5'd3 :
			  (f3_sfd__h565827[18] ?
			     5'd4 :
			     (f3_sfd__h565827[17] ?
				5'd5 :
				(f3_sfd__h565827[16] ?
				   5'd6 :
				   (f3_sfd__h565827[15] ?
				      5'd7 :
				      (f3_sfd__h565827[14] ?
					 5'd8 :
					 (f3_sfd__h565827[13] ?
					    5'd9 :
					    (f3_sfd__h565827[12] ?
					       5'd10 :
					       (f3_sfd__h565827[11] ?
						  5'd11 :
						  (f3_sfd__h565827[10] ?
						     5'd12 :
						     (f3_sfd__h565827[9] ?
							5'd13 :
							(f3_sfd__h565827[8] ?
							   5'd14 :
							   (f3_sfd__h565827[7] ?
							      5'd15 :
							      (f3_sfd__h565827[6] ?
								 5'd16 :
								 (f3_sfd__h565827[5] ?
								    5'd17 :
								    (f3_sfd__h565827[4] ?
								       5'd18 :
								       (f3_sfd__h565827[3] ?
									  5'd19 :
									  (f3_sfd__h565827[2] ?
									     5'd20 :
									     (f3_sfd__h565827[1] ?
										5'd21 :
										(f3_sfd__h565827[0] ?
										   5'd22 :
										   5'd23)))))))))))))))))))))) } ;
  assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 =
	     (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9350 ^
	      12'h800) <=
	     12'd3071 ;
  assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 =
	     (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9350 ^
	      12'h800) <
	     12'd1026 ;
  assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650 =
	     12'd3970 -
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4647 ;
  assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042 =
	     12'd3970 -
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6039 ;
  assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434 =
	     12'd3970 -
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7431 ;
  assign _dfoo12 =
	     fetchStage$pipelines_0_canDeq &&
	     regRenamingTable_rename_0_canRename__3528_AND__ETC___d14221 ||
	     NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 &&
	     regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 &&
	     fetchStage$pipelines_1_first[194:192] == 3'd2 &&
	     NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14386 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd14 ;
  assign _dfoo18 =
	     k__h675032 == 1'd0 &&
	     fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14186 ||
	     fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14305 ==
	     1'd0 &&
	     NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14322 ;
  assign _dfoo2 =
	     fetchStage$pipelines_0_canDeq &&
	     regRenamingTable_rename_0_canRename__3528_AND__ETC___d14263 ||
	     NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 &&
	     regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 &&
	     fetchStage$pipelines_1_first[194:192] == 3'd2 &&
	     NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14386 &&
	     fetchStage$pipelines_1_first[191:189] != 3'd0 &&
	     fetchStage$pipelines_1_first[191:189] != 3'd2 ;
  assign _dfoo20 =
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	     6'd18 ||
	     rob$deqPort_0_deq_data[257:253] == 5'd20 ;
  assign _dfoo26 =
	     rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	     (IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd8 ||
	      IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 ==
	      6'd18) ||
	     rob$deqPort_0_deq_data[257:253] == 5'd19 ;
  assign _dfoo7 =
	     fetchStage$pipelines_0_canDeq &&
	     regRenamingTable_rename_0_canRename__3528_AND__ETC___d14255 ||
	     NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 &&
	     regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 &&
	     fetchStage$pipelines_1_first[194:192] == 3'd2 &&
	     NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14386 &&
	     (fetchStage$pipelines_1_first[191:189] == 3'd0 ||
	      fetchStage$pipelines_1_first[191:189] == 3'd2) ;
  assign _dor1coreFix_aluExe_0_bypassWire_2$EN_wset =
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
  assign _dor1coreFix_aluExe_0_bypassWire_3$EN_wset =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
  assign _dor1coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1coreFix_aluExe_1_bypassWire_2$EN_wset =
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
  assign _dor1coreFix_aluExe_1_bypassWire_3$EN_wset =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
  assign _dor1coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1coreFix_fpuMulDivExe_0_bypassWire_2$EN_wset =
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
  assign _dor1coreFix_fpuMulDivExe_0_bypassWire_3$EN_wset =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
  assign _dor1coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1coreFix_memExe_bypassWire_2$EN_wset =
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
  assign _dor1coreFix_memExe_bypassWire_3$EN_wset =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
  assign _dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1coreFix_memExe_rsMem$EN_setRegReady_3_put =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1rf$EN_write_0_wr =
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
  assign _dor1rf$EN_write_1_wr =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
  assign _dor1sbAggr$EN_setReady_3_put =
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
	     WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
  assign _dor1sbCons$EN_setReady_0_put =
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
  assign _dor1sbCons$EN_setReady_1_put =
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
	     WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
  assign _theResult_____2__h301173 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3142) ?
	       next_deqP___1__h301452 :
	       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ;
  assign _theResult_____2__h309169 =
	     (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3249) ?
	       next_deqP___1__h309448 :
	       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ;
  assign _theResult_____2__h315163 =
	     (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3420) ?
	       next_deqP___1__h315729 :
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ;
  assign _theResult_____2__h323017 =
	     (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3516) ?
	       next_deqP___1__h323583 :
	       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ;
  assign _theResult_____2__h333361 =
	     (coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3745) ?
	       next_deqP___1__h333640 :
	       coreFix_memExe_memRespLdQ_deqP ;
  assign _theResult_____2__h336586 =
	     (coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3839) ?
	       next_deqP___1__h336865 :
	       coreFix_memExe_forwardQ_deqP ;
  assign _theResult____h350737 =
	     (value__h351359 == 54'd0) ? sfd__h343132 : 57'd1 ;
  assign _theResult____h368376 =
	     ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650 ^
	       12'h800) <
	      12'd2105) ?
	       result__h368989 :
	       _theResult____h350737 ;
  assign _theResult____h396436 =
	     (value__h397056 == 54'd0) ? sfd__h388834 : 57'd1 ;
  assign _theResult____h414073 =
	     ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042 ^
	       12'h800) <
	      12'd2105) ?
	       result__h414686 :
	       _theResult____h396436 ;
  assign _theResult____h442131 =
	     (value__h442751 == 54'd0) ? sfd__h434529 : 57'd1 ;
  assign _theResult____h459768 =
	     ((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434 ^
	       12'h800) <
	      12'd2105) ?
	       result__h460381 :
	       _theResult____h442131 ;
  assign _theResult____h508257 =
	     ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8760 ^
	       12'h800) <
	      12'd2105) ?
	       result__h508870 :
	       ((value__h492473 == 25'd0) ? sfd__h487890 : 57'd1) ;
  assign _theResult____h547110 =
	     ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10245 ^
	       12'h800) <
	      12'd2105) ?
	       result__h547723 :
	       ((value__h531326 == 25'd0) ? sfd__h526884 : 57'd1) ;
  assign _theResult____h586414 =
	     ((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9475 ^
	       12'h800) <
	      12'd2105) ?
	       result__h587027 :
	       ((value__h570630 == 25'd0) ? sfd__h566188 : 57'd1) ;
  assign _theResult____h658034 =
	     (csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ?
	       enabled_ints___1__h658447 :
	       12'd0 ;
  assign _theResult___exp__h359364 =
	     sfd__h358940[24] ?
	       ((_theResult___fst_exp__h358848 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h385881) :
	       ((_theResult___fst_exp__h358848 == 8'd0 &&
		 sfd__h358940[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h358848) ;
  assign _theResult___exp__h367946 =
	     sfd__h367522[24] ?
	       ((_theResult___fst_exp__h367504 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h385905) :
	       ((_theResult___fst_exp__h367504 == 8'd0 &&
		 sfd__h367522[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h367504) ;
  assign _theResult___exp__h377130 =
	     sfd__h376706[24] ?
	       ((_theResult___fst_exp__h376614 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h385935) :
	       ((_theResult___fst_exp__h376614 == 8'd0 &&
		 sfd__h376706[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h376614) ;
  assign _theResult___exp__h385766 =
	     sfd__h385318[24] ?
	       ((_theResult___fst_exp__h385299 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h385959) :
	       ((_theResult___fst_exp__h385299 == 8'd0 &&
		 sfd__h385318[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h385299) ;
  assign _theResult___exp__h385868 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd2047) ?
	       8'd255 :
	       _theResult___fst_exp__h385859 ;
  assign _theResult___exp__h405061 =
	     sfd__h404637[24] ?
	       ((_theResult___fst_exp__h404545 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h431578) :
	       ((_theResult___fst_exp__h404545 == 8'd0 &&
		 sfd__h404637[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h404545) ;
  assign _theResult___exp__h413643 =
	     sfd__h413219[24] ?
	       ((_theResult___fst_exp__h413201 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h431602) :
	       ((_theResult___fst_exp__h413201 == 8'd0 &&
		 sfd__h413219[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h413201) ;
  assign _theResult___exp__h422827 =
	     sfd__h422403[24] ?
	       ((_theResult___fst_exp__h422311 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h431632) :
	       ((_theResult___fst_exp__h422311 == 8'd0 &&
		 sfd__h422403[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h422311) ;
  assign _theResult___exp__h431463 =
	     sfd__h431015[24] ?
	       ((_theResult___fst_exp__h430996 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h431656) :
	       ((_theResult___fst_exp__h430996 == 8'd0 &&
		 sfd__h431015[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h430996) ;
  assign _theResult___exp__h431565 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd2047) ?
	       8'd255 :
	       _theResult___fst_exp__h431556 ;
  assign _theResult___exp__h450756 =
	     sfd__h450332[24] ?
	       ((_theResult___fst_exp__h450240 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h477273) :
	       ((_theResult___fst_exp__h450240 == 8'd0 &&
		 sfd__h450332[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h450240) ;
  assign _theResult___exp__h459338 =
	     sfd__h458914[24] ?
	       ((_theResult___fst_exp__h458896 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h477297) :
	       ((_theResult___fst_exp__h458896 == 8'd0 &&
		 sfd__h458914[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h458896) ;
  assign _theResult___exp__h468522 =
	     sfd__h468098[24] ?
	       ((_theResult___fst_exp__h468006 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h477327) :
	       ((_theResult___fst_exp__h468006 == 8'd0 &&
		 sfd__h468098[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h468006) ;
  assign _theResult___exp__h477158 =
	     sfd__h476710[24] ?
	       ((_theResult___fst_exp__h476691 == 8'd254) ?
		  8'd255 :
		  din_inc___2_exp__h477351) :
	       ((_theResult___fst_exp__h476691 == 8'd0 &&
		 sfd__h476710[24:23] == 2'b01) ?
		  8'd1 :
		  _theResult___fst_exp__h476691) ;
  assign _theResult___exp__h477260 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd2047) ?
	       8'd255 :
	       _theResult___fst_exp__h477251 ;
  assign _theResult___exp__h507571 =
	     sfd__h506934[53] ?
	       ((_theResult___fst_exp__h506916 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h526166) :
	       ((_theResult___fst_exp__h506916 == 11'd0 &&
		 sfd__h506934[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h506916) ;
  assign _theResult___exp__h517222 =
	     sfd__h516585[53] ?
	       ((_theResult___fst_exp__h516493 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h526201) :
	       ((_theResult___fst_exp__h516493 == 11'd0 &&
		 sfd__h516585[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h516493) ;
  assign _theResult___exp__h526006 =
	     sfd__h525345[53] ?
	       ((_theResult___fst_exp__h525326 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h526227) :
	       ((_theResult___fst_exp__h525326 == 11'd0 &&
		 sfd__h525345[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h525326) ;
  assign _theResult___exp__h546424 =
	     sfd__h545787[53] ?
	       ((_theResult___fst_exp__h545769 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h565019) :
	       ((_theResult___fst_exp__h545769 == 11'd0 &&
		 sfd__h545787[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h545769) ;
  assign _theResult___exp__h556075 =
	     sfd__h555438[53] ?
	       ((_theResult___fst_exp__h555346 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h565054) :
	       ((_theResult___fst_exp__h555346 == 11'd0 &&
		 sfd__h555438[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h555346) ;
  assign _theResult___exp__h564859 =
	     sfd__h564198[53] ?
	       ((_theResult___fst_exp__h564179 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h565080) :
	       ((_theResult___fst_exp__h564179 == 11'd0 &&
		 sfd__h564198[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h564179) ;
  assign _theResult___exp__h585728 =
	     sfd__h585091[53] ?
	       ((_theResult___fst_exp__h585073 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h604323) :
	       ((_theResult___fst_exp__h585073 == 11'd0 &&
		 sfd__h585091[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h585073) ;
  assign _theResult___exp__h595379 =
	     sfd__h594742[53] ?
	       ((_theResult___fst_exp__h594650 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h604358) :
	       ((_theResult___fst_exp__h594650 == 11'd0 &&
		 sfd__h594742[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h594650) ;
  assign _theResult___exp__h604163 =
	     sfd__h603502[53] ?
	       ((_theResult___fst_exp__h603483 == 11'd2046) ?
		  11'd2047 :
		  din_inc___2_exp__h604384) :
	       ((_theResult___fst_exp__h603483 == 11'd0 &&
		 sfd__h603502[53:52] == 2'b01) ?
		  11'd1 :
		  _theResult___fst_exp__h603483) ;
  assign _theResult___fst__h608922 =
	     a__h608374[63] ? a___1__h608927 : a__h608374 ;
  assign _theResult___fst_exp__h358848 =
	     _theResult____h350737[56] ?
	       8'd2 :
	       _theResult___fst_exp__h358922 ;
  assign _theResult___fst_exp__h358913 =
	     8'd0 -
	     { 2'd0,
	       IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343 } ;
  assign _theResult___fst_exp__h358919 =
	     (!_theResult____h350737[56] && !_theResult____h350737[55] &&
	      !_theResult____h350737[54] &&
	      !_theResult____h350737[53] &&
	      !_theResult____h350737[52] &&
	      !_theResult____h350737[51] &&
	      !_theResult____h350737[50] &&
	      !_theResult____h350737[49] &&
	      !_theResult____h350737[48] &&
	      !_theResult____h350737[47] &&
	      !_theResult____h350737[46] &&
	      !_theResult____h350737[45] &&
	      !_theResult____h350737[44] &&
	      !_theResult____h350737[43] &&
	      !_theResult____h350737[42] &&
	      !_theResult____h350737[41] &&
	      !_theResult____h350737[40] &&
	      !_theResult____h350737[39] &&
	      !_theResult____h350737[38] &&
	      !_theResult____h350737[37] &&
	      !_theResult____h350737[36] &&
	      !_theResult____h350737[35] &&
	      !_theResult____h350737[34] &&
	      !_theResult____h350737[33] &&
	      !_theResult____h350737[32] &&
	      !_theResult____h350737[31] &&
	      !_theResult____h350737[30] &&
	      !_theResult____h350737[29] &&
	      !_theResult____h350737[28] &&
	      !_theResult____h350737[27] &&
	      !_theResult____h350737[26] &&
	      !_theResult____h350737[25] &&
	      !_theResult____h350737[24] &&
	      !_theResult____h350737[23] &&
	      !_theResult____h350737[22] &&
	      !_theResult____h350737[21] &&
	      !_theResult____h350737[20] &&
	      !_theResult____h350737[19] &&
	      !_theResult____h350737[18] &&
	      !_theResult____h350737[17] &&
	      !_theResult____h350737[16] &&
	      !_theResult____h350737[15] &&
	      !_theResult____h350737[14] &&
	      !_theResult____h350737[13] &&
	      !_theResult____h350737[12] &&
	      !_theResult____h350737[11] &&
	      !_theResult____h350737[10] &&
	      !_theResult____h350737[9] &&
	      !_theResult____h350737[8] &&
	      !_theResult____h350737[7] &&
	      !_theResult____h350737[6] &&
	      !_theResult____h350737[5] &&
	      !_theResult____h350737[4] &&
	      !_theResult____h350737[3] &&
	      !_theResult____h350737[2] &&
	      !_theResult____h350737[1] &&
	      !_theResult____h350737[0] ||
	      !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4345) ?
	       8'd0 :
	       _theResult___fst_exp__h358913 ;
  assign _theResult___fst_exp__h358922 =
	     (!_theResult____h350737[56] && _theResult____h350737[55]) ?
	       8'd1 :
	       _theResult___fst_exp__h358919 ;
  assign _theResult___fst_exp__h359445 =
	     (_theResult___fst_exp__h358848 == 8'd255) ?
	       _theResult___fst_exp__h358848 :
	       _theResult___fst_exp__h359442 ;
  assign _theResult___fst_exp__h367495 =
	     8'd129 -
	     { 2'd0,
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 } ;
  assign _theResult___fst_exp__h367501 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519 ||
	      !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4576) ?
	       8'd0 :
	       _theResult___fst_exp__h367495 ;
  assign _theResult___fst_exp__h367504 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       _theResult___fst_exp__h367501 :
	       8'd129 ;
  assign _theResult___fst_exp__h368027 =
	     (_theResult___fst_exp__h367504 == 8'd255) ?
	       _theResult___fst_exp__h367504 :
	       _theResult___fst_exp__h368024 ;
  assign _theResult___fst_exp__h376614 =
	     _theResult____h368376[56] ?
	       8'd2 :
	       _theResult___fst_exp__h376688 ;
  assign _theResult___fst_exp__h376679 =
	     8'd0 -
	     { 2'd0,
	       IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4894 } ;
  assign _theResult___fst_exp__h376685 =
	     (!_theResult____h368376[56] && !_theResult____h368376[55] &&
	      !_theResult____h368376[54] &&
	      !_theResult____h368376[53] &&
	      !_theResult____h368376[52] &&
	      !_theResult____h368376[51] &&
	      !_theResult____h368376[50] &&
	      !_theResult____h368376[49] &&
	      !_theResult____h368376[48] &&
	      !_theResult____h368376[47] &&
	      !_theResult____h368376[46] &&
	      !_theResult____h368376[45] &&
	      !_theResult____h368376[44] &&
	      !_theResult____h368376[43] &&
	      !_theResult____h368376[42] &&
	      !_theResult____h368376[41] &&
	      !_theResult____h368376[40] &&
	      !_theResult____h368376[39] &&
	      !_theResult____h368376[38] &&
	      !_theResult____h368376[37] &&
	      !_theResult____h368376[36] &&
	      !_theResult____h368376[35] &&
	      !_theResult____h368376[34] &&
	      !_theResult____h368376[33] &&
	      !_theResult____h368376[32] &&
	      !_theResult____h368376[31] &&
	      !_theResult____h368376[30] &&
	      !_theResult____h368376[29] &&
	      !_theResult____h368376[28] &&
	      !_theResult____h368376[27] &&
	      !_theResult____h368376[26] &&
	      !_theResult____h368376[25] &&
	      !_theResult____h368376[24] &&
	      !_theResult____h368376[23] &&
	      !_theResult____h368376[22] &&
	      !_theResult____h368376[21] &&
	      !_theResult____h368376[20] &&
	      !_theResult____h368376[19] &&
	      !_theResult____h368376[18] &&
	      !_theResult____h368376[17] &&
	      !_theResult____h368376[16] &&
	      !_theResult____h368376[15] &&
	      !_theResult____h368376[14] &&
	      !_theResult____h368376[13] &&
	      !_theResult____h368376[12] &&
	      !_theResult____h368376[11] &&
	      !_theResult____h368376[10] &&
	      !_theResult____h368376[9] &&
	      !_theResult____h368376[8] &&
	      !_theResult____h368376[7] &&
	      !_theResult____h368376[6] &&
	      !_theResult____h368376[5] &&
	      !_theResult____h368376[4] &&
	      !_theResult____h368376[3] &&
	      !_theResult____h368376[2] &&
	      !_theResult____h368376[1] &&
	      !_theResult____h368376[0] ||
	      !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4896) ?
	       8'd0 :
	       _theResult___fst_exp__h376679 ;
  assign _theResult___fst_exp__h376688 =
	     (!_theResult____h368376[56] && _theResult____h368376[55]) ?
	       8'd1 :
	       _theResult___fst_exp__h376685 ;
  assign _theResult___fst_exp__h377211 =
	     (_theResult___fst_exp__h376614 == 8'd255) ?
	       _theResult___fst_exp__h376614 :
	       _theResult___fst_exp__h377208 ;
  assign _theResult___fst_exp__h385251 =
	     (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] ==
	      8'd0) ?
	       8'd1 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] ;
  assign _theResult___fst_exp__h385290 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q30[7:0] -
	     { 2'd0,
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 } ;
  assign _theResult___fst_exp__h385296 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519 ||
	      !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4969) ?
	       8'd0 :
	       _theResult___fst_exp__h385290 ;
  assign _theResult___fst_exp__h385299 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       _theResult___fst_exp__h385296 :
	       _theResult___fst_exp__h385251 ;
  assign _theResult___fst_exp__h385847 =
	     (_theResult___fst_exp__h385299 == 8'd255) ?
	       _theResult___fst_exp__h385299 :
	       _theResult___fst_exp__h385844 ;
  assign _theResult___fst_exp__h385856 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 ?
		  _theResult___snd_fst_exp__h368030 :
		  _theResult___fst_exp__h350719) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 ?
		  _theResult___snd_fst_exp__h385850 :
		  _theResult___fst_exp__h350719) ;
  assign _theResult___fst_exp__h385859 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
	      52'd0) ?
	       8'd0 :
	       _theResult___fst_exp__h385856 ;
  assign _theResult___fst_exp__h404545 =
	     _theResult____h396436[56] ?
	       8'd2 :
	       _theResult___fst_exp__h404619 ;
  assign _theResult___fst_exp__h404610 =
	     8'd0 -
	     { 2'd0,
	       IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 } ;
  assign _theResult___fst_exp__h404616 =
	     (!_theResult____h396436[56] && !_theResult____h396436[55] &&
	      !_theResult____h396436[54] &&
	      !_theResult____h396436[53] &&
	      !_theResult____h396436[52] &&
	      !_theResult____h396436[51] &&
	      !_theResult____h396436[50] &&
	      !_theResult____h396436[49] &&
	      !_theResult____h396436[48] &&
	      !_theResult____h396436[47] &&
	      !_theResult____h396436[46] &&
	      !_theResult____h396436[45] &&
	      !_theResult____h396436[44] &&
	      !_theResult____h396436[43] &&
	      !_theResult____h396436[42] &&
	      !_theResult____h396436[41] &&
	      !_theResult____h396436[40] &&
	      !_theResult____h396436[39] &&
	      !_theResult____h396436[38] &&
	      !_theResult____h396436[37] &&
	      !_theResult____h396436[36] &&
	      !_theResult____h396436[35] &&
	      !_theResult____h396436[34] &&
	      !_theResult____h396436[33] &&
	      !_theResult____h396436[32] &&
	      !_theResult____h396436[31] &&
	      !_theResult____h396436[30] &&
	      !_theResult____h396436[29] &&
	      !_theResult____h396436[28] &&
	      !_theResult____h396436[27] &&
	      !_theResult____h396436[26] &&
	      !_theResult____h396436[25] &&
	      !_theResult____h396436[24] &&
	      !_theResult____h396436[23] &&
	      !_theResult____h396436[22] &&
	      !_theResult____h396436[21] &&
	      !_theResult____h396436[20] &&
	      !_theResult____h396436[19] &&
	      !_theResult____h396436[18] &&
	      !_theResult____h396436[17] &&
	      !_theResult____h396436[16] &&
	      !_theResult____h396436[15] &&
	      !_theResult____h396436[14] &&
	      !_theResult____h396436[13] &&
	      !_theResult____h396436[12] &&
	      !_theResult____h396436[11] &&
	      !_theResult____h396436[10] &&
	      !_theResult____h396436[9] &&
	      !_theResult____h396436[8] &&
	      !_theResult____h396436[7] &&
	      !_theResult____h396436[6] &&
	      !_theResult____h396436[5] &&
	      !_theResult____h396436[4] &&
	      !_theResult____h396436[3] &&
	      !_theResult____h396436[2] &&
	      !_theResult____h396436[1] &&
	      !_theResult____h396436[0] ||
	      !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5737) ?
	       8'd0 :
	       _theResult___fst_exp__h404610 ;
  assign _theResult___fst_exp__h404619 =
	     (!_theResult____h396436[56] && _theResult____h396436[55]) ?
	       8'd1 :
	       _theResult___fst_exp__h404616 ;
  assign _theResult___fst_exp__h405142 =
	     (_theResult___fst_exp__h404545 == 8'd255) ?
	       _theResult___fst_exp__h404545 :
	       _theResult___fst_exp__h405139 ;
  assign _theResult___fst_exp__h413192 =
	     8'd129 -
	     { 2'd0,
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 } ;
  assign _theResult___fst_exp__h413198 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911 ||
	      !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5968) ?
	       8'd0 :
	       _theResult___fst_exp__h413192 ;
  assign _theResult___fst_exp__h413201 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       _theResult___fst_exp__h413198 :
	       8'd129 ;
  assign _theResult___fst_exp__h413724 =
	     (_theResult___fst_exp__h413201 == 8'd255) ?
	       _theResult___fst_exp__h413201 :
	       _theResult___fst_exp__h413721 ;
  assign _theResult___fst_exp__h422311 =
	     _theResult____h414073[56] ?
	       8'd2 :
	       _theResult___fst_exp__h422385 ;
  assign _theResult___fst_exp__h422376 =
	     8'd0 -
	     { 2'd0,
	       IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 } ;
  assign _theResult___fst_exp__h422382 =
	     (!_theResult____h414073[56] && !_theResult____h414073[55] &&
	      !_theResult____h414073[54] &&
	      !_theResult____h414073[53] &&
	      !_theResult____h414073[52] &&
	      !_theResult____h414073[51] &&
	      !_theResult____h414073[50] &&
	      !_theResult____h414073[49] &&
	      !_theResult____h414073[48] &&
	      !_theResult____h414073[47] &&
	      !_theResult____h414073[46] &&
	      !_theResult____h414073[45] &&
	      !_theResult____h414073[44] &&
	      !_theResult____h414073[43] &&
	      !_theResult____h414073[42] &&
	      !_theResult____h414073[41] &&
	      !_theResult____h414073[40] &&
	      !_theResult____h414073[39] &&
	      !_theResult____h414073[38] &&
	      !_theResult____h414073[37] &&
	      !_theResult____h414073[36] &&
	      !_theResult____h414073[35] &&
	      !_theResult____h414073[34] &&
	      !_theResult____h414073[33] &&
	      !_theResult____h414073[32] &&
	      !_theResult____h414073[31] &&
	      !_theResult____h414073[30] &&
	      !_theResult____h414073[29] &&
	      !_theResult____h414073[28] &&
	      !_theResult____h414073[27] &&
	      !_theResult____h414073[26] &&
	      !_theResult____h414073[25] &&
	      !_theResult____h414073[24] &&
	      !_theResult____h414073[23] &&
	      !_theResult____h414073[22] &&
	      !_theResult____h414073[21] &&
	      !_theResult____h414073[20] &&
	      !_theResult____h414073[19] &&
	      !_theResult____h414073[18] &&
	      !_theResult____h414073[17] &&
	      !_theResult____h414073[16] &&
	      !_theResult____h414073[15] &&
	      !_theResult____h414073[14] &&
	      !_theResult____h414073[13] &&
	      !_theResult____h414073[12] &&
	      !_theResult____h414073[11] &&
	      !_theResult____h414073[10] &&
	      !_theResult____h414073[9] &&
	      !_theResult____h414073[8] &&
	      !_theResult____h414073[7] &&
	      !_theResult____h414073[6] &&
	      !_theResult____h414073[5] &&
	      !_theResult____h414073[4] &&
	      !_theResult____h414073[3] &&
	      !_theResult____h414073[2] &&
	      !_theResult____h414073[1] &&
	      !_theResult____h414073[0] ||
	      !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6288) ?
	       8'd0 :
	       _theResult___fst_exp__h422376 ;
  assign _theResult___fst_exp__h422385 =
	     (!_theResult____h414073[56] && _theResult____h414073[55]) ?
	       8'd1 :
	       _theResult___fst_exp__h422382 ;
  assign _theResult___fst_exp__h422908 =
	     (_theResult___fst_exp__h422311 == 8'd255) ?
	       _theResult___fst_exp__h422311 :
	       _theResult___fst_exp__h422905 ;
  assign _theResult___fst_exp__h430948 =
	     (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] ==
	      8'd0) ?
	       8'd1 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] ;
  assign _theResult___fst_exp__h430987 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q65[7:0] -
	     { 2'd0,
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 } ;
  assign _theResult___fst_exp__h430993 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911 ||
	      !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6361) ?
	       8'd0 :
	       _theResult___fst_exp__h430987 ;
  assign _theResult___fst_exp__h430996 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       _theResult___fst_exp__h430993 :
	       _theResult___fst_exp__h430948 ;
  assign _theResult___fst_exp__h431544 =
	     (_theResult___fst_exp__h430996 == 8'd255) ?
	       _theResult___fst_exp__h430996 :
	       _theResult___fst_exp__h431541 ;
  assign _theResult___fst_exp__h431553 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500 ?
		  _theResult___snd_fst_exp__h413727 :
		  _theResult___fst_exp__h396418) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 ?
		  _theResult___snd_fst_exp__h431547 :
		  _theResult___fst_exp__h396418) ;
  assign _theResult___fst_exp__h431556 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
	      52'd0) ?
	       8'd0 :
	       _theResult___fst_exp__h431553 ;
  assign _theResult___fst_exp__h450240 =
	     _theResult____h442131[56] ?
	       8'd2 :
	       _theResult___fst_exp__h450314 ;
  assign _theResult___fst_exp__h450305 =
	     8'd0 -
	     { 2'd0,
	       IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 } ;
  assign _theResult___fst_exp__h450311 =
	     (!_theResult____h442131[56] && !_theResult____h442131[55] &&
	      !_theResult____h442131[54] &&
	      !_theResult____h442131[53] &&
	      !_theResult____h442131[52] &&
	      !_theResult____h442131[51] &&
	      !_theResult____h442131[50] &&
	      !_theResult____h442131[49] &&
	      !_theResult____h442131[48] &&
	      !_theResult____h442131[47] &&
	      !_theResult____h442131[46] &&
	      !_theResult____h442131[45] &&
	      !_theResult____h442131[44] &&
	      !_theResult____h442131[43] &&
	      !_theResult____h442131[42] &&
	      !_theResult____h442131[41] &&
	      !_theResult____h442131[40] &&
	      !_theResult____h442131[39] &&
	      !_theResult____h442131[38] &&
	      !_theResult____h442131[37] &&
	      !_theResult____h442131[36] &&
	      !_theResult____h442131[35] &&
	      !_theResult____h442131[34] &&
	      !_theResult____h442131[33] &&
	      !_theResult____h442131[32] &&
	      !_theResult____h442131[31] &&
	      !_theResult____h442131[30] &&
	      !_theResult____h442131[29] &&
	      !_theResult____h442131[28] &&
	      !_theResult____h442131[27] &&
	      !_theResult____h442131[26] &&
	      !_theResult____h442131[25] &&
	      !_theResult____h442131[24] &&
	      !_theResult____h442131[23] &&
	      !_theResult____h442131[22] &&
	      !_theResult____h442131[21] &&
	      !_theResult____h442131[20] &&
	      !_theResult____h442131[19] &&
	      !_theResult____h442131[18] &&
	      !_theResult____h442131[17] &&
	      !_theResult____h442131[16] &&
	      !_theResult____h442131[15] &&
	      !_theResult____h442131[14] &&
	      !_theResult____h442131[13] &&
	      !_theResult____h442131[12] &&
	      !_theResult____h442131[11] &&
	      !_theResult____h442131[10] &&
	      !_theResult____h442131[9] &&
	      !_theResult____h442131[8] &&
	      !_theResult____h442131[7] &&
	      !_theResult____h442131[6] &&
	      !_theResult____h442131[5] &&
	      !_theResult____h442131[4] &&
	      !_theResult____h442131[3] &&
	      !_theResult____h442131[2] &&
	      !_theResult____h442131[1] &&
	      !_theResult____h442131[0] ||
	      !_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7129) ?
	       8'd0 :
	       _theResult___fst_exp__h450305 ;
  assign _theResult___fst_exp__h450314 =
	     (!_theResult____h442131[56] && _theResult____h442131[55]) ?
	       8'd1 :
	       _theResult___fst_exp__h450311 ;
  assign _theResult___fst_exp__h450837 =
	     (_theResult___fst_exp__h450240 == 8'd255) ?
	       _theResult___fst_exp__h450240 :
	       _theResult___fst_exp__h450834 ;
  assign _theResult___fst_exp__h458887 =
	     8'd129 -
	     { 2'd0,
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 } ;
  assign _theResult___fst_exp__h458893 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303 ||
	      !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7360) ?
	       8'd0 :
	       _theResult___fst_exp__h458887 ;
  assign _theResult___fst_exp__h458896 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       _theResult___fst_exp__h458893 :
	       8'd129 ;
  assign _theResult___fst_exp__h459419 =
	     (_theResult___fst_exp__h458896 == 8'd255) ?
	       _theResult___fst_exp__h458896 :
	       _theResult___fst_exp__h459416 ;
  assign _theResult___fst_exp__h468006 =
	     _theResult____h459768[56] ?
	       8'd2 :
	       _theResult___fst_exp__h468080 ;
  assign _theResult___fst_exp__h468071 =
	     8'd0 -
	     { 2'd0,
	       IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 } ;
  assign _theResult___fst_exp__h468077 =
	     (!_theResult____h459768[56] && !_theResult____h459768[55] &&
	      !_theResult____h459768[54] &&
	      !_theResult____h459768[53] &&
	      !_theResult____h459768[52] &&
	      !_theResult____h459768[51] &&
	      !_theResult____h459768[50] &&
	      !_theResult____h459768[49] &&
	      !_theResult____h459768[48] &&
	      !_theResult____h459768[47] &&
	      !_theResult____h459768[46] &&
	      !_theResult____h459768[45] &&
	      !_theResult____h459768[44] &&
	      !_theResult____h459768[43] &&
	      !_theResult____h459768[42] &&
	      !_theResult____h459768[41] &&
	      !_theResult____h459768[40] &&
	      !_theResult____h459768[39] &&
	      !_theResult____h459768[38] &&
	      !_theResult____h459768[37] &&
	      !_theResult____h459768[36] &&
	      !_theResult____h459768[35] &&
	      !_theResult____h459768[34] &&
	      !_theResult____h459768[33] &&
	      !_theResult____h459768[32] &&
	      !_theResult____h459768[31] &&
	      !_theResult____h459768[30] &&
	      !_theResult____h459768[29] &&
	      !_theResult____h459768[28] &&
	      !_theResult____h459768[27] &&
	      !_theResult____h459768[26] &&
	      !_theResult____h459768[25] &&
	      !_theResult____h459768[24] &&
	      !_theResult____h459768[23] &&
	      !_theResult____h459768[22] &&
	      !_theResult____h459768[21] &&
	      !_theResult____h459768[20] &&
	      !_theResult____h459768[19] &&
	      !_theResult____h459768[18] &&
	      !_theResult____h459768[17] &&
	      !_theResult____h459768[16] &&
	      !_theResult____h459768[15] &&
	      !_theResult____h459768[14] &&
	      !_theResult____h459768[13] &&
	      !_theResult____h459768[12] &&
	      !_theResult____h459768[11] &&
	      !_theResult____h459768[10] &&
	      !_theResult____h459768[9] &&
	      !_theResult____h459768[8] &&
	      !_theResult____h459768[7] &&
	      !_theResult____h459768[6] &&
	      !_theResult____h459768[5] &&
	      !_theResult____h459768[4] &&
	      !_theResult____h459768[3] &&
	      !_theResult____h459768[2] &&
	      !_theResult____h459768[1] &&
	      !_theResult____h459768[0] ||
	      !_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7680) ?
	       8'd0 :
	       _theResult___fst_exp__h468071 ;
  assign _theResult___fst_exp__h468080 =
	     (!_theResult____h459768[56] && _theResult____h459768[55]) ?
	       8'd1 :
	       _theResult___fst_exp__h468077 ;
  assign _theResult___fst_exp__h468603 =
	     (_theResult___fst_exp__h468006 == 8'd255) ?
	       _theResult___fst_exp__h468006 :
	       _theResult___fst_exp__h468600 ;
  assign _theResult___fst_exp__h476643 =
	     (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] ==
	      8'd0) ?
	       8'd1 :
	       SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] ;
  assign _theResult___fst_exp__h476682 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q100[7:0] -
	     { 2'd0,
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 } ;
  assign _theResult___fst_exp__h476688 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303 ||
	      !_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7753) ?
	       8'd0 :
	       _theResult___fst_exp__h476682 ;
  assign _theResult___fst_exp__h476691 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       _theResult___fst_exp__h476688 :
	       _theResult___fst_exp__h476643 ;
  assign _theResult___fst_exp__h477239 =
	     (_theResult___fst_exp__h476691 == 8'd255) ?
	       _theResult___fst_exp__h476691 :
	       _theResult___fst_exp__h477236 ;
  assign _theResult___fst_exp__h477248 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892 ?
		  _theResult___snd_fst_exp__h459422 :
		  _theResult___fst_exp__h442113) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 ?
		  _theResult___snd_fst_exp__h477242 :
		  _theResult___fst_exp__h442113) ;
  assign _theResult___fst_exp__h477251 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
	      52'd0) ?
	       8'd0 :
	       _theResult___fst_exp__h477248 ;
  assign _theResult___fst_exp__h491843 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
	       11'd2047 :
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 ;
  assign _theResult___fst_exp__h506907 =
	     11'd897 -
	     { 5'd0,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 } ;
  assign _theResult___fst_exp__h506913 =
	     (f1_exp__h487528 == 8'd0 && !f1_sfd__h487529[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667 ||
	      !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8696) ?
	       11'd0 :
	       _theResult___fst_exp__h506907 ;
  assign _theResult___fst_exp__h506916 =
	     (f1_exp__h487528 == 8'd0) ?
	       _theResult___fst_exp__h506913 :
	       11'd897 ;
  assign _theResult___fst_exp__h507671 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard98955_0b0_theResult___fst_exp06916_0_ETC__q136 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 ;
  assign _theResult___fst_exp__h507674 =
	     (_theResult___fst_exp__h506916 == 11'd2047) ?
	       _theResult___fst_exp__h506916 :
	       _theResult___fst_exp__h507671 ;
  assign _theResult___fst_exp__h516493 =
	     _theResult____h508257[56] ?
	       11'd2 :
	       _theResult___fst_exp__h516567 ;
  assign _theResult___fst_exp__h516558 =
	     11'd0 -
	     { 5'd0,
	       IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9006 } ;
  assign _theResult___fst_exp__h516564 =
	     (!_theResult____h508257[56] && !_theResult____h508257[55] &&
	      !_theResult____h508257[54] &&
	      !_theResult____h508257[53] &&
	      !_theResult____h508257[52] &&
	      !_theResult____h508257[51] &&
	      !_theResult____h508257[50] &&
	      !_theResult____h508257[49] &&
	      !_theResult____h508257[48] &&
	      !_theResult____h508257[47] &&
	      !_theResult____h508257[46] &&
	      !_theResult____h508257[45] &&
	      !_theResult____h508257[44] &&
	      !_theResult____h508257[43] &&
	      !_theResult____h508257[42] &&
	      !_theResult____h508257[41] &&
	      !_theResult____h508257[40] &&
	      !_theResult____h508257[39] &&
	      !_theResult____h508257[38] &&
	      !_theResult____h508257[37] &&
	      !_theResult____h508257[36] &&
	      !_theResult____h508257[35] &&
	      !_theResult____h508257[34] &&
	      !_theResult____h508257[33] &&
	      !_theResult____h508257[32] &&
	      !_theResult____h508257[31] &&
	      !_theResult____h508257[30] &&
	      !_theResult____h508257[29] &&
	      !_theResult____h508257[28] &&
	      !_theResult____h508257[27] &&
	      !_theResult____h508257[26] &&
	      !_theResult____h508257[25] &&
	      !_theResult____h508257[24] &&
	      !_theResult____h508257[23] &&
	      !_theResult____h508257[22] &&
	      !_theResult____h508257[21] &&
	      !_theResult____h508257[20] &&
	      !_theResult____h508257[19] &&
	      !_theResult____h508257[18] &&
	      !_theResult____h508257[17] &&
	      !_theResult____h508257[16] &&
	      !_theResult____h508257[15] &&
	      !_theResult____h508257[14] &&
	      !_theResult____h508257[13] &&
	      !_theResult____h508257[12] &&
	      !_theResult____h508257[11] &&
	      !_theResult____h508257[10] &&
	      !_theResult____h508257[9] &&
	      !_theResult____h508257[8] &&
	      !_theResult____h508257[7] &&
	      !_theResult____h508257[6] &&
	      !_theResult____h508257[5] &&
	      !_theResult____h508257[4] &&
	      !_theResult____h508257[3] &&
	      !_theResult____h508257[2] &&
	      !_theResult____h508257[1] &&
	      !_theResult____h508257[0] ||
	      !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9008) ?
	       11'd0 :
	       _theResult___fst_exp__h516558 ;
  assign _theResult___fst_exp__h516567 =
	     (!_theResult____h508257[56] && _theResult____h508257[55]) ?
	       11'd1 :
	       _theResult___fst_exp__h516564 ;
  assign _theResult___fst_exp__h517322 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard08267_0b0_theResult___fst_exp16493_0_ETC__q204 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 ;
  assign _theResult___fst_exp__h517325 =
	     (_theResult___fst_exp__h516493 == 11'd2047) ?
	       _theResult___fst_exp__h516493 :
	       _theResult___fst_exp__h517322 ;
  assign _theResult___fst_exp__h525278 =
	     (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129[10:0] ==
	      11'd0) ?
	       11'd1 :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129[10:0] ;
  assign _theResult___fst_exp__h525317 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q129[10:0] -
	     { 5'd0,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 } ;
  assign _theResult___fst_exp__h525323 =
	     (f1_exp__h487528 == 8'd0 && !f1_sfd__h487529[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667 ||
	      !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9058) ?
	       11'd0 :
	       _theResult___fst_exp__h525317 ;
  assign _theResult___fst_exp__h525326 =
	     (f1_exp__h487528 == 8'd0) ?
	       _theResult___fst_exp__h525323 :
	       _theResult___fst_exp__h525278 ;
  assign _theResult___fst_exp__h526106 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard17336_0b0_theResult___fst_exp25326_0_ETC__q208 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 ;
  assign _theResult___fst_exp__h526109 =
	     (_theResult___fst_exp__h525326 == 11'd2047) ?
	       _theResult___fst_exp__h525326 :
	       _theResult___fst_exp__h526106 ;
  assign _theResult___fst_exp__h526118 =
	     (f1_exp__h487528 == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 ?
		  _theResult___snd_fst_exp__h507677 :
		  _theResult___fst_exp__h491843) :
	       (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 ?
		  _theResult___snd_fst_exp__h526112 :
		  _theResult___fst_exp__h491843) ;
  assign _theResult___fst_exp__h526121 =
	     (f1_exp__h487528 == 8'd0 && f1_sfd__h487529 == 23'd0) ?
	       11'd0 :
	       _theResult___fst_exp__h526118 ;
  assign _theResult___fst_exp__h530696 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
	       11'd2047 :
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 ;
  assign _theResult___fst_exp__h545760 =
	     11'd897 -
	     { 5'd0,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 } ;
  assign _theResult___fst_exp__h545766 =
	     (f2_exp__h526522 == 8'd0 && !f2_sfd__h526523[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167 ||
	      !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10196) ?
	       11'd0 :
	       _theResult___fst_exp__h545760 ;
  assign _theResult___fst_exp__h545769 =
	     (f2_exp__h526522 == 8'd0) ?
	       _theResult___fst_exp__h545766 :
	       11'd897 ;
  assign _theResult___fst_exp__h546524 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard37808_0b0_theResult___fst_exp45769_0_ETC__q176 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 ;
  assign _theResult___fst_exp__h546527 =
	     (_theResult___fst_exp__h545769 == 11'd2047) ?
	       _theResult___fst_exp__h545769 :
	       _theResult___fst_exp__h546524 ;
  assign _theResult___fst_exp__h555346 =
	     _theResult____h547110[56] ?
	       11'd2 :
	       _theResult___fst_exp__h555420 ;
  assign _theResult___fst_exp__h555411 =
	     11'd0 -
	     { 5'd0,
	       IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10491 } ;
  assign _theResult___fst_exp__h555417 =
	     (!_theResult____h547110[56] && !_theResult____h547110[55] &&
	      !_theResult____h547110[54] &&
	      !_theResult____h547110[53] &&
	      !_theResult____h547110[52] &&
	      !_theResult____h547110[51] &&
	      !_theResult____h547110[50] &&
	      !_theResult____h547110[49] &&
	      !_theResult____h547110[48] &&
	      !_theResult____h547110[47] &&
	      !_theResult____h547110[46] &&
	      !_theResult____h547110[45] &&
	      !_theResult____h547110[44] &&
	      !_theResult____h547110[43] &&
	      !_theResult____h547110[42] &&
	      !_theResult____h547110[41] &&
	      !_theResult____h547110[40] &&
	      !_theResult____h547110[39] &&
	      !_theResult____h547110[38] &&
	      !_theResult____h547110[37] &&
	      !_theResult____h547110[36] &&
	      !_theResult____h547110[35] &&
	      !_theResult____h547110[34] &&
	      !_theResult____h547110[33] &&
	      !_theResult____h547110[32] &&
	      !_theResult____h547110[31] &&
	      !_theResult____h547110[30] &&
	      !_theResult____h547110[29] &&
	      !_theResult____h547110[28] &&
	      !_theResult____h547110[27] &&
	      !_theResult____h547110[26] &&
	      !_theResult____h547110[25] &&
	      !_theResult____h547110[24] &&
	      !_theResult____h547110[23] &&
	      !_theResult____h547110[22] &&
	      !_theResult____h547110[21] &&
	      !_theResult____h547110[20] &&
	      !_theResult____h547110[19] &&
	      !_theResult____h547110[18] &&
	      !_theResult____h547110[17] &&
	      !_theResult____h547110[16] &&
	      !_theResult____h547110[15] &&
	      !_theResult____h547110[14] &&
	      !_theResult____h547110[13] &&
	      !_theResult____h547110[12] &&
	      !_theResult____h547110[11] &&
	      !_theResult____h547110[10] &&
	      !_theResult____h547110[9] &&
	      !_theResult____h547110[8] &&
	      !_theResult____h547110[7] &&
	      !_theResult____h547110[6] &&
	      !_theResult____h547110[5] &&
	      !_theResult____h547110[4] &&
	      !_theResult____h547110[3] &&
	      !_theResult____h547110[2] &&
	      !_theResult____h547110[1] &&
	      !_theResult____h547110[0] ||
	      !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10493) ?
	       11'd0 :
	       _theResult___fst_exp__h555411 ;
  assign _theResult___fst_exp__h555420 =
	     (!_theResult____h547110[56] && _theResult____h547110[55]) ?
	       11'd1 :
	       _theResult___fst_exp__h555417 ;
  assign _theResult___fst_exp__h556175 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard47120_0b0_theResult___fst_exp55346_0_ETC__q178 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 ;
  assign _theResult___fst_exp__h556178 =
	     (_theResult___fst_exp__h555346 == 11'd2047) ?
	       _theResult___fst_exp__h555346 :
	       _theResult___fst_exp__h556175 ;
  assign _theResult___fst_exp__h564131 =
	     (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169[10:0] ==
	      11'd0) ?
	       11'd1 :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169[10:0] ;
  assign _theResult___fst_exp__h564170 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q169[10:0] -
	     { 5'd0,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 } ;
  assign _theResult___fst_exp__h564176 =
	     (f2_exp__h526522 == 8'd0 && !f2_sfd__h526523[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167 ||
	      !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10543) ?
	       11'd0 :
	       _theResult___fst_exp__h564170 ;
  assign _theResult___fst_exp__h564179 =
	     (f2_exp__h526522 == 8'd0) ?
	       _theResult___fst_exp__h564176 :
	       _theResult___fst_exp__h564131 ;
  assign _theResult___fst_exp__h564959 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard56189_0b0_theResult___fst_exp64179_0_ETC__q180 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 ;
  assign _theResult___fst_exp__h564962 =
	     (_theResult___fst_exp__h564179 == 11'd2047) ?
	       _theResult___fst_exp__h564179 :
	       _theResult___fst_exp__h564959 ;
  assign _theResult___fst_exp__h564971 =
	     (f2_exp__h526522 == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 ?
		  _theResult___snd_fst_exp__h546530 :
		  _theResult___fst_exp__h530696) :
	       (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 ?
		  _theResult___snd_fst_exp__h564965 :
		  _theResult___fst_exp__h530696) ;
  assign _theResult___fst_exp__h564974 =
	     (f2_exp__h526522 == 8'd0 && f2_sfd__h526523 == 23'd0) ?
	       11'd0 :
	       _theResult___fst_exp__h564971 ;
  assign _theResult___fst_exp__h570000 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
	       11'd2047 :
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 ;
  assign _theResult___fst_exp__h585064 =
	     11'd897 -
	     { 5'd0,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9424 } ;
  assign _theResult___fst_exp__h585070 =
	     (f3_exp__h565826 == 8'd0 && !f3_sfd__h565827[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397 ||
	      !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9426) ?
	       11'd0 :
	       _theResult___fst_exp__h585064 ;
  assign _theResult___fst_exp__h585073 =
	     (f3_exp__h565826 == 8'd0) ?
	       _theResult___fst_exp__h585070 :
	       11'd897 ;
  assign _theResult___fst_exp__h585828 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard77112_0b0_theResult___fst_exp85073_0_ETC__q153 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 ;
  assign _theResult___fst_exp__h585831 =
	     (_theResult___fst_exp__h585073 == 11'd2047) ?
	       _theResult___fst_exp__h585073 :
	       _theResult___fst_exp__h585828 ;
  assign _theResult___fst_exp__h594650 =
	     _theResult____h586414[56] ?
	       11'd2 :
	       _theResult___fst_exp__h594724 ;
  assign _theResult___fst_exp__h594715 =
	     11'd0 -
	     { 5'd0,
	       IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9721 } ;
  assign _theResult___fst_exp__h594721 =
	     (!_theResult____h586414[56] && !_theResult____h586414[55] &&
	      !_theResult____h586414[54] &&
	      !_theResult____h586414[53] &&
	      !_theResult____h586414[52] &&
	      !_theResult____h586414[51] &&
	      !_theResult____h586414[50] &&
	      !_theResult____h586414[49] &&
	      !_theResult____h586414[48] &&
	      !_theResult____h586414[47] &&
	      !_theResult____h586414[46] &&
	      !_theResult____h586414[45] &&
	      !_theResult____h586414[44] &&
	      !_theResult____h586414[43] &&
	      !_theResult____h586414[42] &&
	      !_theResult____h586414[41] &&
	      !_theResult____h586414[40] &&
	      !_theResult____h586414[39] &&
	      !_theResult____h586414[38] &&
	      !_theResult____h586414[37] &&
	      !_theResult____h586414[36] &&
	      !_theResult____h586414[35] &&
	      !_theResult____h586414[34] &&
	      !_theResult____h586414[33] &&
	      !_theResult____h586414[32] &&
	      !_theResult____h586414[31] &&
	      !_theResult____h586414[30] &&
	      !_theResult____h586414[29] &&
	      !_theResult____h586414[28] &&
	      !_theResult____h586414[27] &&
	      !_theResult____h586414[26] &&
	      !_theResult____h586414[25] &&
	      !_theResult____h586414[24] &&
	      !_theResult____h586414[23] &&
	      !_theResult____h586414[22] &&
	      !_theResult____h586414[21] &&
	      !_theResult____h586414[20] &&
	      !_theResult____h586414[19] &&
	      !_theResult____h586414[18] &&
	      !_theResult____h586414[17] &&
	      !_theResult____h586414[16] &&
	      !_theResult____h586414[15] &&
	      !_theResult____h586414[14] &&
	      !_theResult____h586414[13] &&
	      !_theResult____h586414[12] &&
	      !_theResult____h586414[11] &&
	      !_theResult____h586414[10] &&
	      !_theResult____h586414[9] &&
	      !_theResult____h586414[8] &&
	      !_theResult____h586414[7] &&
	      !_theResult____h586414[6] &&
	      !_theResult____h586414[5] &&
	      !_theResult____h586414[4] &&
	      !_theResult____h586414[3] &&
	      !_theResult____h586414[2] &&
	      !_theResult____h586414[1] &&
	      !_theResult____h586414[0] ||
	      !_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9723) ?
	       11'd0 :
	       _theResult___fst_exp__h594715 ;
  assign _theResult___fst_exp__h594724 =
	     (!_theResult____h586414[56] && _theResult____h586414[55]) ?
	       11'd1 :
	       _theResult___fst_exp__h594721 ;
  assign _theResult___fst_exp__h595479 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard86424_0b0_theResult___fst_exp94650_0_ETC__q182 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 ;
  assign _theResult___fst_exp__h595482 =
	     (_theResult___fst_exp__h594650 == 11'd2047) ?
	       _theResult___fst_exp__h594650 :
	       _theResult___fst_exp__h595479 ;
  assign _theResult___fst_exp__h603435 =
	     (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q146[10:0] ==
	      11'd0) ?
	       11'd1 :
	       SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q146[10:0] ;
  assign _theResult___fst_exp__h603474 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q146[10:0] -
	     { 5'd0,
	       IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9424 } ;
  assign _theResult___fst_exp__h603480 =
	     (f3_exp__h565826 == 8'd0 && !f3_sfd__h565827[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397 ||
	      !_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9773) ?
	       11'd0 :
	       _theResult___fst_exp__h603474 ;
  assign _theResult___fst_exp__h603483 =
	     (f3_exp__h565826 == 8'd0) ?
	       _theResult___fst_exp__h603480 :
	       _theResult___fst_exp__h603435 ;
  assign _theResult___fst_exp__h604263 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard95493_0b0_theResult___fst_exp03483_0_ETC__q184 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 ;
  assign _theResult___fst_exp__h604266 =
	     (_theResult___fst_exp__h603483 == 11'd2047) ?
	       _theResult___fst_exp__h603483 :
	       _theResult___fst_exp__h604263 ;
  assign _theResult___fst_exp__h604275 =
	     (f3_exp__h565826 == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 ?
		  _theResult___snd_fst_exp__h585834 :
		  _theResult___fst_exp__h570000) :
	       (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 ?
		  _theResult___snd_fst_exp__h604269 :
		  _theResult___fst_exp__h570000) ;
  assign _theResult___fst_exp__h604278 =
	     (f3_exp__h565826 == 8'd0 && f3_sfd__h565827 == 23'd0) ?
	       11'd0 :
	       _theResult___fst_exp__h604275 ;
  assign _theResult___fst_sfd__h359446 =
	     (_theResult___fst_exp__h358848 == 8'd255) ?
	       sfdin__h358842[56:34] :
	       _theResult___fst_sfd__h359443 ;
  assign _theResult___fst_sfd__h368028 =
	     (_theResult___fst_exp__h367504 == 8'd255) ?
	       _theResult___snd__h367455[56:34] :
	       _theResult___fst_sfd__h368025 ;
  assign _theResult___fst_sfd__h377212 =
	     (_theResult___fst_exp__h376614 == 8'd255) ?
	       sfdin__h376608[56:34] :
	       _theResult___fst_sfd__h377209 ;
  assign _theResult___fst_sfd__h385848 =
	     (_theResult___fst_exp__h385299 == 8'd255) ?
	       _theResult___snd__h385245[56:34] :
	       _theResult___fst_sfd__h385845 ;
  assign _theResult___fst_sfd__h385857 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4108 ?
		  _theResult___snd_fst_sfd__h368031 :
		  _theResult___fst_sfd__h350720) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4648 ?
		  _theResult___snd_fst_sfd__h385851 :
		  _theResult___fst_sfd__h350720) ;
  assign _theResult___fst_sfd__h385863 =
	     ((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	       11'd2047 ||
	       coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	       11'd0) &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
	      52'd0) ?
	       23'd0 :
	       _theResult___fst_sfd__h385857 ;
  assign _theResult___fst_sfd__h405143 =
	     (_theResult___fst_exp__h404545 == 8'd255) ?
	       sfdin__h404539[56:34] :
	       _theResult___fst_sfd__h405140 ;
  assign _theResult___fst_sfd__h413725 =
	     (_theResult___fst_exp__h413201 == 8'd255) ?
	       _theResult___snd__h413152[56:34] :
	       _theResult___fst_sfd__h413722 ;
  assign _theResult___fst_sfd__h422909 =
	     (_theResult___fst_exp__h422311 == 8'd255) ?
	       sfdin__h422305[56:34] :
	       _theResult___fst_sfd__h422906 ;
  assign _theResult___fst_sfd__h431545 =
	     (_theResult___fst_exp__h430996 == 8'd255) ?
	       _theResult___snd__h430942[56:34] :
	       _theResult___fst_sfd__h431542 ;
  assign _theResult___fst_sfd__h431554 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5500 ?
		  _theResult___snd_fst_sfd__h413728 :
		  _theResult___fst_sfd__h396419) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6040 ?
		  _theResult___snd_fst_sfd__h431548 :
		  _theResult___fst_sfd__h396419) ;
  assign _theResult___fst_sfd__h431560 =
	     ((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	       11'd2047 ||
	       coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	       11'd0) &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
	      52'd0) ?
	       23'd0 :
	       _theResult___fst_sfd__h431554 ;
  assign _theResult___fst_sfd__h450838 =
	     (_theResult___fst_exp__h450240 == 8'd255) ?
	       sfdin__h450234[56:34] :
	       _theResult___fst_sfd__h450835 ;
  assign _theResult___fst_sfd__h459420 =
	     (_theResult___fst_exp__h458896 == 8'd255) ?
	       _theResult___snd__h458847[56:34] :
	       _theResult___fst_sfd__h459417 ;
  assign _theResult___fst_sfd__h468604 =
	     (_theResult___fst_exp__h468006 == 8'd255) ?
	       sfdin__h468000[56:34] :
	       _theResult___fst_sfd__h468601 ;
  assign _theResult___fst_sfd__h477240 =
	     (_theResult___fst_exp__h476691 == 8'd255) ?
	       _theResult___snd__h476637[56:34] :
	       _theResult___fst_sfd__h477237 ;
  assign _theResult___fst_sfd__h477249 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       (_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6892 ?
		  _theResult___snd_fst_sfd__h459423 :
		  _theResult___fst_sfd__h442114) :
	       (SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7432 ?
		  _theResult___snd_fst_sfd__h477243 :
		  _theResult___fst_sfd__h442114) ;
  assign _theResult___fst_sfd__h477255 =
	     ((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	       11'd2047 ||
	       coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	       11'd0) &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
	      52'd0) ?
	       23'd0 :
	       _theResult___fst_sfd__h477249 ;
  assign _theResult___fst_sfd__h491844 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
	       52'd0 :
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 ;
  assign _theResult___fst_sfd__h507672 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard98955_0b0_theResult___snd06867_BITS__ETC__q206 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 ;
  assign _theResult___fst_sfd__h507675 =
	     (_theResult___fst_exp__h506916 == 11'd2047) ?
	       _theResult___snd__h506867[56:5] :
	       _theResult___fst_sfd__h507672 ;
  assign _theResult___fst_sfd__h517323 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard08267_0b0_sfdin16487_BITS_56_TO_5_0b_ETC__q210 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 ;
  assign _theResult___fst_sfd__h517326 =
	     (_theResult___fst_exp__h516493 == 11'd2047) ?
	       sfdin__h516487[56:5] :
	       _theResult___fst_sfd__h517323 ;
  assign _theResult___fst_sfd__h526107 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard17336_0b0_theResult___snd25272_BITS__ETC__q212 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 ;
  assign _theResult___fst_sfd__h526110 =
	     (_theResult___fst_exp__h525326 == 11'd2047) ?
	       _theResult___snd__h525272[56:5] :
	       _theResult___fst_sfd__h526107 ;
  assign _theResult___fst_sfd__h526119 =
	     (f1_exp__h487528 == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8621 ?
		  _theResult___snd_fst_sfd__h507678 :
		  _theResult___fst_sfd__h491844) :
	       (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8758 ?
		  _theResult___snd_fst_sfd__h526113 :
		  _theResult___fst_sfd__h491844) ;
  assign _theResult___fst_sfd__h526125 =
	     ((f1_exp__h487528 == 8'd255 || f1_exp__h487528 == 8'd0) &&
	      f1_sfd__h487529 == 23'd0) ?
	       52'd0 :
	       _theResult___fst_sfd__h526119 ;
  assign _theResult___fst_sfd__h530697 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
	       52'd0 :
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 ;
  assign _theResult___fst_sfd__h546525 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard37808_0b0_theResult___snd45720_BITS__ETC__q198 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 ;
  assign _theResult___fst_sfd__h546528 =
	     (_theResult___fst_exp__h545769 == 11'd2047) ?
	       _theResult___snd__h545720[56:5] :
	       _theResult___fst_sfd__h546525 ;
  assign _theResult___fst_sfd__h556176 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard47120_0b0_sfdin55340_BITS_56_TO_5_0b_ETC__q200 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 ;
  assign _theResult___fst_sfd__h556179 =
	     (_theResult___fst_exp__h555346 == 11'd2047) ?
	       sfdin__h555340[56:5] :
	       _theResult___fst_sfd__h556176 ;
  assign _theResult___fst_sfd__h564960 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard56189_0b0_theResult___snd64125_BITS__ETC__q202 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 ;
  assign _theResult___fst_sfd__h564963 =
	     (_theResult___fst_exp__h564179 == 11'd2047) ?
	       _theResult___snd__h564125[56:5] :
	       _theResult___fst_sfd__h564960 ;
  assign _theResult___fst_sfd__h564972 =
	     (f2_exp__h526522 == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10121 ?
		  _theResult___snd_fst_sfd__h546531 :
		  _theResult___fst_sfd__h530697) :
	       (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10243 ?
		  _theResult___snd_fst_sfd__h564966 :
		  _theResult___fst_sfd__h530697) ;
  assign _theResult___fst_sfd__h564978 =
	     ((f2_exp__h526522 == 8'd255 || f2_exp__h526522 == 8'd0) &&
	      f2_sfd__h526523 == 23'd0) ?
	       52'd0 :
	       _theResult___fst_sfd__h564972 ;
  assign _theResult___fst_sfd__h570001 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
	       52'd0 :
	       CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q12 ;
  assign _theResult___fst_sfd__h585829 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard77112_0b0_theResult___snd85024_BITS__ETC__q214 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 ;
  assign _theResult___fst_sfd__h585832 =
	     (_theResult___fst_exp__h585073 == 11'd2047) ?
	       _theResult___snd__h585024[56:5] :
	       _theResult___fst_sfd__h585829 ;
  assign _theResult___fst_sfd__h595480 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard86424_0b0_sfdin94644_BITS_56_TO_5_0b_ETC__q216 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 ;
  assign _theResult___fst_sfd__h595483 =
	     (_theResult___fst_exp__h594650 == 11'd2047) ?
	       sfdin__h594644[56:5] :
	       _theResult___fst_sfd__h595480 ;
  assign _theResult___fst_sfd__h604264 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
	       CASE_guard95493_0b0_theResult___snd03429_BITS__ETC__q218 :
	       IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 ;
  assign _theResult___fst_sfd__h604267 =
	     (_theResult___fst_exp__h603483 == 11'd2047) ?
	       _theResult___snd__h603429[56:5] :
	       _theResult___fst_sfd__h604264 ;
  assign _theResult___fst_sfd__h604276 =
	     (f3_exp__h565826 == 8'd0) ?
	       (_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9351 ?
		  _theResult___snd_fst_sfd__h585835 :
		  _theResult___fst_sfd__h570001) :
	       (SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9473 ?
		  _theResult___snd_fst_sfd__h604270 :
		  _theResult___fst_sfd__h570001) ;
  assign _theResult___fst_sfd__h604282 =
	     ((f3_exp__h565826 == 8'd255 || f3_exp__h565826 == 8'd0) &&
	      f3_sfd__h565827 == 23'd0) ?
	       52'd0 :
	       _theResult___fst_sfd__h604276 ;
  assign _theResult___sfd__h359365 =
	     sfd__h358940[24] ?
	       ((_theResult___fst_exp__h358848 == 8'd254) ?
		  23'd0 :
		  sfd__h358940[23:1]) :
	       sfd__h358940[22:0] ;
  assign _theResult___sfd__h367947 =
	     sfd__h367522[24] ?
	       ((_theResult___fst_exp__h367504 == 8'd254) ?
		  23'd0 :
		  sfd__h367522[23:1]) :
	       sfd__h367522[22:0] ;
  assign _theResult___sfd__h377131 =
	     sfd__h376706[24] ?
	       ((_theResult___fst_exp__h376614 == 8'd254) ?
		  23'd0 :
		  sfd__h376706[23:1]) :
	       sfd__h376706[22:0] ;
  assign _theResult___sfd__h385767 =
	     sfd__h385318[24] ?
	       ((_theResult___fst_exp__h385299 == 8'd254) ?
		  23'd0 :
		  sfd__h385318[23:1]) :
	       sfd__h385318[22:0] ;
  assign _theResult___sfd__h385869 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd2047 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
	      52'd0) ?
	       _theResult___snd_fst_sfd__h343082 :
	       _theResult___fst_sfd__h385863 ;
  assign _theResult___sfd__h405062 =
	     sfd__h404637[24] ?
	       ((_theResult___fst_exp__h404545 == 8'd254) ?
		  23'd0 :
		  sfd__h404637[23:1]) :
	       sfd__h404637[22:0] ;
  assign _theResult___sfd__h413644 =
	     sfd__h413219[24] ?
	       ((_theResult___fst_exp__h413201 == 8'd254) ?
		  23'd0 :
		  sfd__h413219[23:1]) :
	       sfd__h413219[22:0] ;
  assign _theResult___sfd__h422828 =
	     sfd__h422403[24] ?
	       ((_theResult___fst_exp__h422311 == 8'd254) ?
		  23'd0 :
		  sfd__h422403[23:1]) :
	       sfd__h422403[22:0] ;
  assign _theResult___sfd__h431464 =
	     sfd__h431015[24] ?
	       ((_theResult___fst_exp__h430996 == 8'd254) ?
		  23'd0 :
		  sfd__h431015[23:1]) :
	       sfd__h431015[22:0] ;
  assign _theResult___sfd__h431566 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd2047 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
	      52'd0) ?
	       _theResult___snd_fst_sfd__h388784 :
	       _theResult___fst_sfd__h431560 ;
  assign _theResult___sfd__h450757 =
	     sfd__h450332[24] ?
	       ((_theResult___fst_exp__h450240 == 8'd254) ?
		  23'd0 :
		  sfd__h450332[23:1]) :
	       sfd__h450332[22:0] ;
  assign _theResult___sfd__h459339 =
	     sfd__h458914[24] ?
	       ((_theResult___fst_exp__h458896 == 8'd254) ?
		  23'd0 :
		  sfd__h458914[23:1]) :
	       sfd__h458914[22:0] ;
  assign _theResult___sfd__h468523 =
	     sfd__h468098[24] ?
	       ((_theResult___fst_exp__h468006 == 8'd254) ?
		  23'd0 :
		  sfd__h468098[23:1]) :
	       sfd__h468098[22:0] ;
  assign _theResult___sfd__h477159 =
	     sfd__h476710[24] ?
	       ((_theResult___fst_exp__h476691 == 8'd254) ?
		  23'd0 :
		  sfd__h476710[23:1]) :
	       sfd__h476710[22:0] ;
  assign _theResult___sfd__h477261 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd2047 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
	      52'd0) ?
	       _theResult___snd_fst_sfd__h434479 :
	       _theResult___fst_sfd__h477255 ;
  assign _theResult___sfd__h507572 =
	     sfd__h506934[53] ?
	       ((_theResult___fst_exp__h506916 == 11'd2046) ?
		  52'd0 :
		  sfd__h506934[52:1]) :
	       sfd__h506934[51:0] ;
  assign _theResult___sfd__h517223 =
	     sfd__h516585[53] ?
	       ((_theResult___fst_exp__h516493 == 11'd2046) ?
		  52'd0 :
		  sfd__h516585[52:1]) :
	       sfd__h516585[51:0] ;
  assign _theResult___sfd__h526007 =
	     sfd__h525345[53] ?
	       ((_theResult___fst_exp__h525326 == 11'd2046) ?
		  52'd0 :
		  sfd__h525345[52:1]) :
	       sfd__h525345[51:0] ;
  assign _theResult___sfd__h546425 =
	     sfd__h545787[53] ?
	       ((_theResult___fst_exp__h545769 == 11'd2046) ?
		  52'd0 :
		  sfd__h545787[52:1]) :
	       sfd__h545787[51:0] ;
  assign _theResult___sfd__h556076 =
	     sfd__h555438[53] ?
	       ((_theResult___fst_exp__h555346 == 11'd2046) ?
		  52'd0 :
		  sfd__h555438[52:1]) :
	       sfd__h555438[51:0] ;
  assign _theResult___sfd__h564860 =
	     sfd__h564198[53] ?
	       ((_theResult___fst_exp__h564179 == 11'd2046) ?
		  52'd0 :
		  sfd__h564198[52:1]) :
	       sfd__h564198[51:0] ;
  assign _theResult___sfd__h585729 =
	     sfd__h585091[53] ?
	       ((_theResult___fst_exp__h585073 == 11'd2046) ?
		  52'd0 :
		  sfd__h585091[52:1]) :
	       sfd__h585091[51:0] ;
  assign _theResult___sfd__h595380 =
	     sfd__h594742[53] ?
	       ((_theResult___fst_exp__h594650 == 11'd2046) ?
		  52'd0 :
		  sfd__h594742[52:1]) :
	       sfd__h594742[51:0] ;
  assign _theResult___sfd__h604164 =
	     sfd__h603502[53] ?
	       ((_theResult___fst_exp__h603483 == 11'd2046) ?
		  52'd0 :
		  sfd__h603502[52:1]) :
	       sfd__h603502[51:0] ;
  assign _theResult___snd__h358859 = { _theResult____h350737[55:0], 1'd0 } ;
  assign _theResult___snd__h358870 =
	     (!_theResult____h350737[56] && _theResult____h350737[55]) ?
	       _theResult___snd__h358872 :
	       _theResult___snd__h358882 ;
  assign _theResult___snd__h358872 = { _theResult____h350737[54:0], 2'd0 } ;
  assign _theResult___snd__h358882 =
	     (!_theResult____h350737[56] && !_theResult____h350737[55] &&
	      !_theResult____h350737[54] &&
	      !_theResult____h350737[53] &&
	      !_theResult____h350737[52] &&
	      !_theResult____h350737[51] &&
	      !_theResult____h350737[50] &&
	      !_theResult____h350737[49] &&
	      !_theResult____h350737[48] &&
	      !_theResult____h350737[47] &&
	      !_theResult____h350737[46] &&
	      !_theResult____h350737[45] &&
	      !_theResult____h350737[44] &&
	      !_theResult____h350737[43] &&
	      !_theResult____h350737[42] &&
	      !_theResult____h350737[41] &&
	      !_theResult____h350737[40] &&
	      !_theResult____h350737[39] &&
	      !_theResult____h350737[38] &&
	      !_theResult____h350737[37] &&
	      !_theResult____h350737[36] &&
	      !_theResult____h350737[35] &&
	      !_theResult____h350737[34] &&
	      !_theResult____h350737[33] &&
	      !_theResult____h350737[32] &&
	      !_theResult____h350737[31] &&
	      !_theResult____h350737[30] &&
	      !_theResult____h350737[29] &&
	      !_theResult____h350737[28] &&
	      !_theResult____h350737[27] &&
	      !_theResult____h350737[26] &&
	      !_theResult____h350737[25] &&
	      !_theResult____h350737[24] &&
	      !_theResult____h350737[23] &&
	      !_theResult____h350737[22] &&
	      !_theResult____h350737[21] &&
	      !_theResult____h350737[20] &&
	      !_theResult____h350737[19] &&
	      !_theResult____h350737[18] &&
	      !_theResult____h350737[17] &&
	      !_theResult____h350737[16] &&
	      !_theResult____h350737[15] &&
	      !_theResult____h350737[14] &&
	      !_theResult____h350737[13] &&
	      !_theResult____h350737[12] &&
	      !_theResult____h350737[11] &&
	      !_theResult____h350737[10] &&
	      !_theResult____h350737[9] &&
	      !_theResult____h350737[8] &&
	      !_theResult____h350737[7] &&
	      !_theResult____h350737[6] &&
	      !_theResult____h350737[5] &&
	      !_theResult____h350737[4] &&
	      !_theResult____h350737[3] &&
	      !_theResult____h350737[2] &&
	      !_theResult____h350737[1] &&
	      !_theResult____h350737[0]) ?
	       _theResult____h350737 :
	       _theResult___snd__h358888 ;
  assign _theResult___snd__h358888 =
	     { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q21[54:0],
	       2'd0 } ;
  assign _theResult___snd__h358911 =
	     _theResult____h350737 <<
	     IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4343 ;
  assign _theResult___snd__h367455 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       _theResult___snd__h367464 :
	       _theResult___snd__h367457 ;
  assign _theResult___snd__h367457 =
	     { coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5],
	       5'd0 } ;
  assign _theResult___snd__h367464 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519) ?
	       sfd__h343132 :
	       _theResult___snd__h367470 ;
  assign _theResult___snd__h367470 =
	     { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q23[54:0],
	       2'd0 } ;
  assign _theResult___snd__h367493 =
	     sfd__h343132 <<
	     IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4574 ;
  assign _theResult___snd__h376625 = { _theResult____h368376[55:0], 1'd0 } ;
  assign _theResult___snd__h376636 =
	     (!_theResult____h368376[56] && _theResult____h368376[55]) ?
	       _theResult___snd__h376638 :
	       _theResult___snd__h376648 ;
  assign _theResult___snd__h376638 = { _theResult____h368376[54:0], 2'd0 } ;
  assign _theResult___snd__h376648 =
	     (!_theResult____h368376[56] && !_theResult____h368376[55] &&
	      !_theResult____h368376[54] &&
	      !_theResult____h368376[53] &&
	      !_theResult____h368376[52] &&
	      !_theResult____h368376[51] &&
	      !_theResult____h368376[50] &&
	      !_theResult____h368376[49] &&
	      !_theResult____h368376[48] &&
	      !_theResult____h368376[47] &&
	      !_theResult____h368376[46] &&
	      !_theResult____h368376[45] &&
	      !_theResult____h368376[44] &&
	      !_theResult____h368376[43] &&
	      !_theResult____h368376[42] &&
	      !_theResult____h368376[41] &&
	      !_theResult____h368376[40] &&
	      !_theResult____h368376[39] &&
	      !_theResult____h368376[38] &&
	      !_theResult____h368376[37] &&
	      !_theResult____h368376[36] &&
	      !_theResult____h368376[35] &&
	      !_theResult____h368376[34] &&
	      !_theResult____h368376[33] &&
	      !_theResult____h368376[32] &&
	      !_theResult____h368376[31] &&
	      !_theResult____h368376[30] &&
	      !_theResult____h368376[29] &&
	      !_theResult____h368376[28] &&
	      !_theResult____h368376[27] &&
	      !_theResult____h368376[26] &&
	      !_theResult____h368376[25] &&
	      !_theResult____h368376[24] &&
	      !_theResult____h368376[23] &&
	      !_theResult____h368376[22] &&
	      !_theResult____h368376[21] &&
	      !_theResult____h368376[20] &&
	      !_theResult____h368376[19] &&
	      !_theResult____h368376[18] &&
	      !_theResult____h368376[17] &&
	      !_theResult____h368376[16] &&
	      !_theResult____h368376[15] &&
	      !_theResult____h368376[14] &&
	      !_theResult____h368376[13] &&
	      !_theResult____h368376[12] &&
	      !_theResult____h368376[11] &&
	      !_theResult____h368376[10] &&
	      !_theResult____h368376[9] &&
	      !_theResult____h368376[8] &&
	      !_theResult____h368376[7] &&
	      !_theResult____h368376[6] &&
	      !_theResult____h368376[5] &&
	      !_theResult____h368376[4] &&
	      !_theResult____h368376[3] &&
	      !_theResult____h368376[2] &&
	      !_theResult____h368376[1] &&
	      !_theResult____h368376[0]) ?
	       _theResult____h368376 :
	       _theResult___snd__h376654 ;
  assign _theResult___snd__h376654 =
	     { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q31[54:0],
	       2'd0 } ;
  assign _theResult___snd__h376677 =
	     _theResult____h368376 <<
	     IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4894 ;
  assign _theResult___snd__h385245 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0) ?
	       _theResult___snd__h385259 :
	       _theResult___snd__h367457 ;
  assign _theResult___snd__h385259 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4519) ?
	       sfd__h343132 :
	       _theResult___snd__h385265 ;
  assign _theResult___snd__h385265 =
	     { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q36[54:0],
	       2'd0 } ;
  assign _theResult___snd__h385283 =
	     sfd__h343132 <<
	     (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4968[8] ?
		9'h0AA :
		IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4968) ;
  assign _theResult___snd__h404556 = { _theResult____h396436[55:0], 1'd0 } ;
  assign _theResult___snd__h404567 =
	     (!_theResult____h396436[56] && _theResult____h396436[55]) ?
	       _theResult___snd__h404569 :
	       _theResult___snd__h404579 ;
  assign _theResult___snd__h404569 = { _theResult____h396436[54:0], 2'd0 } ;
  assign _theResult___snd__h404579 =
	     (!_theResult____h396436[56] && !_theResult____h396436[55] &&
	      !_theResult____h396436[54] &&
	      !_theResult____h396436[53] &&
	      !_theResult____h396436[52] &&
	      !_theResult____h396436[51] &&
	      !_theResult____h396436[50] &&
	      !_theResult____h396436[49] &&
	      !_theResult____h396436[48] &&
	      !_theResult____h396436[47] &&
	      !_theResult____h396436[46] &&
	      !_theResult____h396436[45] &&
	      !_theResult____h396436[44] &&
	      !_theResult____h396436[43] &&
	      !_theResult____h396436[42] &&
	      !_theResult____h396436[41] &&
	      !_theResult____h396436[40] &&
	      !_theResult____h396436[39] &&
	      !_theResult____h396436[38] &&
	      !_theResult____h396436[37] &&
	      !_theResult____h396436[36] &&
	      !_theResult____h396436[35] &&
	      !_theResult____h396436[34] &&
	      !_theResult____h396436[33] &&
	      !_theResult____h396436[32] &&
	      !_theResult____h396436[31] &&
	      !_theResult____h396436[30] &&
	      !_theResult____h396436[29] &&
	      !_theResult____h396436[28] &&
	      !_theResult____h396436[27] &&
	      !_theResult____h396436[26] &&
	      !_theResult____h396436[25] &&
	      !_theResult____h396436[24] &&
	      !_theResult____h396436[23] &&
	      !_theResult____h396436[22] &&
	      !_theResult____h396436[21] &&
	      !_theResult____h396436[20] &&
	      !_theResult____h396436[19] &&
	      !_theResult____h396436[18] &&
	      !_theResult____h396436[17] &&
	      !_theResult____h396436[16] &&
	      !_theResult____h396436[15] &&
	      !_theResult____h396436[14] &&
	      !_theResult____h396436[13] &&
	      !_theResult____h396436[12] &&
	      !_theResult____h396436[11] &&
	      !_theResult____h396436[10] &&
	      !_theResult____h396436[9] &&
	      !_theResult____h396436[8] &&
	      !_theResult____h396436[7] &&
	      !_theResult____h396436[6] &&
	      !_theResult____h396436[5] &&
	      !_theResult____h396436[4] &&
	      !_theResult____h396436[3] &&
	      !_theResult____h396436[2] &&
	      !_theResult____h396436[1] &&
	      !_theResult____h396436[0]) ?
	       _theResult____h396436 :
	       _theResult___snd__h404585 ;
  assign _theResult___snd__h404585 =
	     { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q56[54:0],
	       2'd0 } ;
  assign _theResult___snd__h404608 =
	     _theResult____h396436 <<
	     IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5735 ;
  assign _theResult___snd__h413152 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       _theResult___snd__h413161 :
	       _theResult___snd__h413154 ;
  assign _theResult___snd__h413154 =
	     { coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5],
	       5'd0 } ;
  assign _theResult___snd__h413161 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911) ?
	       sfd__h388834 :
	       _theResult___snd__h413167 ;
  assign _theResult___snd__h413167 =
	     { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q58[54:0],
	       2'd0 } ;
  assign _theResult___snd__h413190 =
	     sfd__h388834 <<
	     IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5966 ;
  assign _theResult___snd__h422322 = { _theResult____h414073[55:0], 1'd0 } ;
  assign _theResult___snd__h422333 =
	     (!_theResult____h414073[56] && _theResult____h414073[55]) ?
	       _theResult___snd__h422335 :
	       _theResult___snd__h422345 ;
  assign _theResult___snd__h422335 = { _theResult____h414073[54:0], 2'd0 } ;
  assign _theResult___snd__h422345 =
	     (!_theResult____h414073[56] && !_theResult____h414073[55] &&
	      !_theResult____h414073[54] &&
	      !_theResult____h414073[53] &&
	      !_theResult____h414073[52] &&
	      !_theResult____h414073[51] &&
	      !_theResult____h414073[50] &&
	      !_theResult____h414073[49] &&
	      !_theResult____h414073[48] &&
	      !_theResult____h414073[47] &&
	      !_theResult____h414073[46] &&
	      !_theResult____h414073[45] &&
	      !_theResult____h414073[44] &&
	      !_theResult____h414073[43] &&
	      !_theResult____h414073[42] &&
	      !_theResult____h414073[41] &&
	      !_theResult____h414073[40] &&
	      !_theResult____h414073[39] &&
	      !_theResult____h414073[38] &&
	      !_theResult____h414073[37] &&
	      !_theResult____h414073[36] &&
	      !_theResult____h414073[35] &&
	      !_theResult____h414073[34] &&
	      !_theResult____h414073[33] &&
	      !_theResult____h414073[32] &&
	      !_theResult____h414073[31] &&
	      !_theResult____h414073[30] &&
	      !_theResult____h414073[29] &&
	      !_theResult____h414073[28] &&
	      !_theResult____h414073[27] &&
	      !_theResult____h414073[26] &&
	      !_theResult____h414073[25] &&
	      !_theResult____h414073[24] &&
	      !_theResult____h414073[23] &&
	      !_theResult____h414073[22] &&
	      !_theResult____h414073[21] &&
	      !_theResult____h414073[20] &&
	      !_theResult____h414073[19] &&
	      !_theResult____h414073[18] &&
	      !_theResult____h414073[17] &&
	      !_theResult____h414073[16] &&
	      !_theResult____h414073[15] &&
	      !_theResult____h414073[14] &&
	      !_theResult____h414073[13] &&
	      !_theResult____h414073[12] &&
	      !_theResult____h414073[11] &&
	      !_theResult____h414073[10] &&
	      !_theResult____h414073[9] &&
	      !_theResult____h414073[8] &&
	      !_theResult____h414073[7] &&
	      !_theResult____h414073[6] &&
	      !_theResult____h414073[5] &&
	      !_theResult____h414073[4] &&
	      !_theResult____h414073[3] &&
	      !_theResult____h414073[2] &&
	      !_theResult____h414073[1] &&
	      !_theResult____h414073[0]) ?
	       _theResult____h414073 :
	       _theResult___snd__h422351 ;
  assign _theResult___snd__h422351 =
	     { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q66[54:0],
	       2'd0 } ;
  assign _theResult___snd__h422374 =
	     _theResult____h414073 <<
	     IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6286 ;
  assign _theResult___snd__h430942 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0) ?
	       _theResult___snd__h430956 :
	       _theResult___snd__h413154 ;
  assign _theResult___snd__h430956 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5911) ?
	       sfd__h388834 :
	       _theResult___snd__h430962 ;
  assign _theResult___snd__h430962 =
	     { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q71[54:0],
	       2'd0 } ;
  assign _theResult___snd__h430980 =
	     sfd__h388834 <<
	     (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360[8] ?
		9'h0AA :
		IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6360) ;
  assign _theResult___snd__h450251 = { _theResult____h442131[55:0], 1'd0 } ;
  assign _theResult___snd__h450262 =
	     (!_theResult____h442131[56] && _theResult____h442131[55]) ?
	       _theResult___snd__h450264 :
	       _theResult___snd__h450274 ;
  assign _theResult___snd__h450264 = { _theResult____h442131[54:0], 2'd0 } ;
  assign _theResult___snd__h450274 =
	     (!_theResult____h442131[56] && !_theResult____h442131[55] &&
	      !_theResult____h442131[54] &&
	      !_theResult____h442131[53] &&
	      !_theResult____h442131[52] &&
	      !_theResult____h442131[51] &&
	      !_theResult____h442131[50] &&
	      !_theResult____h442131[49] &&
	      !_theResult____h442131[48] &&
	      !_theResult____h442131[47] &&
	      !_theResult____h442131[46] &&
	      !_theResult____h442131[45] &&
	      !_theResult____h442131[44] &&
	      !_theResult____h442131[43] &&
	      !_theResult____h442131[42] &&
	      !_theResult____h442131[41] &&
	      !_theResult____h442131[40] &&
	      !_theResult____h442131[39] &&
	      !_theResult____h442131[38] &&
	      !_theResult____h442131[37] &&
	      !_theResult____h442131[36] &&
	      !_theResult____h442131[35] &&
	      !_theResult____h442131[34] &&
	      !_theResult____h442131[33] &&
	      !_theResult____h442131[32] &&
	      !_theResult____h442131[31] &&
	      !_theResult____h442131[30] &&
	      !_theResult____h442131[29] &&
	      !_theResult____h442131[28] &&
	      !_theResult____h442131[27] &&
	      !_theResult____h442131[26] &&
	      !_theResult____h442131[25] &&
	      !_theResult____h442131[24] &&
	      !_theResult____h442131[23] &&
	      !_theResult____h442131[22] &&
	      !_theResult____h442131[21] &&
	      !_theResult____h442131[20] &&
	      !_theResult____h442131[19] &&
	      !_theResult____h442131[18] &&
	      !_theResult____h442131[17] &&
	      !_theResult____h442131[16] &&
	      !_theResult____h442131[15] &&
	      !_theResult____h442131[14] &&
	      !_theResult____h442131[13] &&
	      !_theResult____h442131[12] &&
	      !_theResult____h442131[11] &&
	      !_theResult____h442131[10] &&
	      !_theResult____h442131[9] &&
	      !_theResult____h442131[8] &&
	      !_theResult____h442131[7] &&
	      !_theResult____h442131[6] &&
	      !_theResult____h442131[5] &&
	      !_theResult____h442131[4] &&
	      !_theResult____h442131[3] &&
	      !_theResult____h442131[2] &&
	      !_theResult____h442131[1] &&
	      !_theResult____h442131[0]) ?
	       _theResult____h442131 :
	       _theResult___snd__h450280 ;
  assign _theResult___snd__h450280 =
	     { IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q91[54:0],
	       2'd0 } ;
  assign _theResult___snd__h450303 =
	     _theResult____h442131 <<
	     IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7127 ;
  assign _theResult___snd__h458847 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       _theResult___snd__h458856 :
	       _theResult___snd__h458849 ;
  assign _theResult___snd__h458849 =
	     { coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5],
	       5'd0 } ;
  assign _theResult___snd__h458856 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303) ?
	       sfd__h434529 :
	       _theResult___snd__h458862 ;
  assign _theResult___snd__h458862 =
	     { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q93[54:0],
	       2'd0 } ;
  assign _theResult___snd__h458885 =
	     sfd__h434529 <<
	     IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7358 ;
  assign _theResult___snd__h468017 = { _theResult____h459768[55:0], 1'd0 } ;
  assign _theResult___snd__h468028 =
	     (!_theResult____h459768[56] && _theResult____h459768[55]) ?
	       _theResult___snd__h468030 :
	       _theResult___snd__h468040 ;
  assign _theResult___snd__h468030 = { _theResult____h459768[54:0], 2'd0 } ;
  assign _theResult___snd__h468040 =
	     (!_theResult____h459768[56] && !_theResult____h459768[55] &&
	      !_theResult____h459768[54] &&
	      !_theResult____h459768[53] &&
	      !_theResult____h459768[52] &&
	      !_theResult____h459768[51] &&
	      !_theResult____h459768[50] &&
	      !_theResult____h459768[49] &&
	      !_theResult____h459768[48] &&
	      !_theResult____h459768[47] &&
	      !_theResult____h459768[46] &&
	      !_theResult____h459768[45] &&
	      !_theResult____h459768[44] &&
	      !_theResult____h459768[43] &&
	      !_theResult____h459768[42] &&
	      !_theResult____h459768[41] &&
	      !_theResult____h459768[40] &&
	      !_theResult____h459768[39] &&
	      !_theResult____h459768[38] &&
	      !_theResult____h459768[37] &&
	      !_theResult____h459768[36] &&
	      !_theResult____h459768[35] &&
	      !_theResult____h459768[34] &&
	      !_theResult____h459768[33] &&
	      !_theResult____h459768[32] &&
	      !_theResult____h459768[31] &&
	      !_theResult____h459768[30] &&
	      !_theResult____h459768[29] &&
	      !_theResult____h459768[28] &&
	      !_theResult____h459768[27] &&
	      !_theResult____h459768[26] &&
	      !_theResult____h459768[25] &&
	      !_theResult____h459768[24] &&
	      !_theResult____h459768[23] &&
	      !_theResult____h459768[22] &&
	      !_theResult____h459768[21] &&
	      !_theResult____h459768[20] &&
	      !_theResult____h459768[19] &&
	      !_theResult____h459768[18] &&
	      !_theResult____h459768[17] &&
	      !_theResult____h459768[16] &&
	      !_theResult____h459768[15] &&
	      !_theResult____h459768[14] &&
	      !_theResult____h459768[13] &&
	      !_theResult____h459768[12] &&
	      !_theResult____h459768[11] &&
	      !_theResult____h459768[10] &&
	      !_theResult____h459768[9] &&
	      !_theResult____h459768[8] &&
	      !_theResult____h459768[7] &&
	      !_theResult____h459768[6] &&
	      !_theResult____h459768[5] &&
	      !_theResult____h459768[4] &&
	      !_theResult____h459768[3] &&
	      !_theResult____h459768[2] &&
	      !_theResult____h459768[1] &&
	      !_theResult____h459768[0]) ?
	       _theResult____h459768 :
	       _theResult___snd__h468046 ;
  assign _theResult___snd__h468046 =
	     { IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q101[54:0],
	       2'd0 } ;
  assign _theResult___snd__h468069 =
	     _theResult____h459768 <<
	     IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7678 ;
  assign _theResult___snd__h476637 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0) ?
	       _theResult___snd__h476651 :
	       _theResult___snd__h458849 ;
  assign _theResult___snd__h476651 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd0 &&
	      NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7303) ?
	       sfd__h434529 :
	       _theResult___snd__h476657 ;
  assign _theResult___snd__h476657 =
	     { IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q106[54:0],
	       2'd0 } ;
  assign _theResult___snd__h476675 =
	     sfd__h434529 <<
	     (IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752[8] ?
		9'h0AA :
		IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7752) ;
  assign _theResult___snd__h506867 =
	     (f1_exp__h487528 == 8'd0) ?
	       _theResult___snd__h506876 :
	       _theResult___snd__h506869 ;
  assign _theResult___snd__h506869 = { f1_sfd__h487529, 34'd0 } ;
  assign _theResult___snd__h506876 =
	     (f1_exp__h487528 == 8'd0 && !f1_sfd__h487529[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667) ?
	       sfd__h487890 :
	       _theResult___snd__h506882 ;
  assign _theResult___snd__h506882 =
	     { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q126[54:0],
	       2'd0 } ;
  assign _theResult___snd__h506905 =
	     sfd__h487890 <<
	     IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8694 ;
  assign _theResult___snd__h516504 = { _theResult____h508257[55:0], 1'd0 } ;
  assign _theResult___snd__h516515 =
	     (!_theResult____h508257[56] && _theResult____h508257[55]) ?
	       _theResult___snd__h516517 :
	       _theResult___snd__h516527 ;
  assign _theResult___snd__h516517 = { _theResult____h508257[54:0], 2'd0 } ;
  assign _theResult___snd__h516527 =
	     (!_theResult____h508257[56] && !_theResult____h508257[55] &&
	      !_theResult____h508257[54] &&
	      !_theResult____h508257[53] &&
	      !_theResult____h508257[52] &&
	      !_theResult____h508257[51] &&
	      !_theResult____h508257[50] &&
	      !_theResult____h508257[49] &&
	      !_theResult____h508257[48] &&
	      !_theResult____h508257[47] &&
	      !_theResult____h508257[46] &&
	      !_theResult____h508257[45] &&
	      !_theResult____h508257[44] &&
	      !_theResult____h508257[43] &&
	      !_theResult____h508257[42] &&
	      !_theResult____h508257[41] &&
	      !_theResult____h508257[40] &&
	      !_theResult____h508257[39] &&
	      !_theResult____h508257[38] &&
	      !_theResult____h508257[37] &&
	      !_theResult____h508257[36] &&
	      !_theResult____h508257[35] &&
	      !_theResult____h508257[34] &&
	      !_theResult____h508257[33] &&
	      !_theResult____h508257[32] &&
	      !_theResult____h508257[31] &&
	      !_theResult____h508257[30] &&
	      !_theResult____h508257[29] &&
	      !_theResult____h508257[28] &&
	      !_theResult____h508257[27] &&
	      !_theResult____h508257[26] &&
	      !_theResult____h508257[25] &&
	      !_theResult____h508257[24] &&
	      !_theResult____h508257[23] &&
	      !_theResult____h508257[22] &&
	      !_theResult____h508257[21] &&
	      !_theResult____h508257[20] &&
	      !_theResult____h508257[19] &&
	      !_theResult____h508257[18] &&
	      !_theResult____h508257[17] &&
	      !_theResult____h508257[16] &&
	      !_theResult____h508257[15] &&
	      !_theResult____h508257[14] &&
	      !_theResult____h508257[13] &&
	      !_theResult____h508257[12] &&
	      !_theResult____h508257[11] &&
	      !_theResult____h508257[10] &&
	      !_theResult____h508257[9] &&
	      !_theResult____h508257[8] &&
	      !_theResult____h508257[7] &&
	      !_theResult____h508257[6] &&
	      !_theResult____h508257[5] &&
	      !_theResult____h508257[4] &&
	      !_theResult____h508257[3] &&
	      !_theResult____h508257[2] &&
	      !_theResult____h508257[1] &&
	      !_theResult____h508257[0]) ?
	       _theResult____h508257 :
	       _theResult___snd__h516533 ;
  assign _theResult___snd__h516533 =
	     { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q130[54:0],
	       2'd0 } ;
  assign _theResult___snd__h516556 =
	     _theResult____h508257 <<
	     IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9006 ;
  assign _theResult___snd__h525272 =
	     (f1_exp__h487528 == 8'd0) ?
	       _theResult___snd__h525286 :
	       _theResult___snd__h506869 ;
  assign _theResult___snd__h525286 =
	     (f1_exp__h487528 == 8'd0 && !f1_sfd__h487529[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8667) ?
	       sfd__h487890 :
	       _theResult___snd__h525292 ;
  assign _theResult___snd__h525292 =
	     { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q133[54:0],
	       2'd0 } ;
  assign _theResult___snd__h525310 =
	     sfd__h487890 <<
	     IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9057 ;
  assign _theResult___snd__h545720 =
	     (f2_exp__h526522 == 8'd0) ?
	       _theResult___snd__h545729 :
	       _theResult___snd__h545722 ;
  assign _theResult___snd__h545722 = { f2_sfd__h526523, 34'd0 } ;
  assign _theResult___snd__h545729 =
	     (f2_exp__h526522 == 8'd0 && !f2_sfd__h526523[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167) ?
	       sfd__h526884 :
	       _theResult___snd__h545735 ;
  assign _theResult___snd__h545735 =
	     { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q166[54:0],
	       2'd0 } ;
  assign _theResult___snd__h545758 =
	     sfd__h526884 <<
	     IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10194 ;
  assign _theResult___snd__h555357 = { _theResult____h547110[55:0], 1'd0 } ;
  assign _theResult___snd__h555368 =
	     (!_theResult____h547110[56] && _theResult____h547110[55]) ?
	       _theResult___snd__h555370 :
	       _theResult___snd__h555380 ;
  assign _theResult___snd__h555370 = { _theResult____h547110[54:0], 2'd0 } ;
  assign _theResult___snd__h555380 =
	     (!_theResult____h547110[56] && !_theResult____h547110[55] &&
	      !_theResult____h547110[54] &&
	      !_theResult____h547110[53] &&
	      !_theResult____h547110[52] &&
	      !_theResult____h547110[51] &&
	      !_theResult____h547110[50] &&
	      !_theResult____h547110[49] &&
	      !_theResult____h547110[48] &&
	      !_theResult____h547110[47] &&
	      !_theResult____h547110[46] &&
	      !_theResult____h547110[45] &&
	      !_theResult____h547110[44] &&
	      !_theResult____h547110[43] &&
	      !_theResult____h547110[42] &&
	      !_theResult____h547110[41] &&
	      !_theResult____h547110[40] &&
	      !_theResult____h547110[39] &&
	      !_theResult____h547110[38] &&
	      !_theResult____h547110[37] &&
	      !_theResult____h547110[36] &&
	      !_theResult____h547110[35] &&
	      !_theResult____h547110[34] &&
	      !_theResult____h547110[33] &&
	      !_theResult____h547110[32] &&
	      !_theResult____h547110[31] &&
	      !_theResult____h547110[30] &&
	      !_theResult____h547110[29] &&
	      !_theResult____h547110[28] &&
	      !_theResult____h547110[27] &&
	      !_theResult____h547110[26] &&
	      !_theResult____h547110[25] &&
	      !_theResult____h547110[24] &&
	      !_theResult____h547110[23] &&
	      !_theResult____h547110[22] &&
	      !_theResult____h547110[21] &&
	      !_theResult____h547110[20] &&
	      !_theResult____h547110[19] &&
	      !_theResult____h547110[18] &&
	      !_theResult____h547110[17] &&
	      !_theResult____h547110[16] &&
	      !_theResult____h547110[15] &&
	      !_theResult____h547110[14] &&
	      !_theResult____h547110[13] &&
	      !_theResult____h547110[12] &&
	      !_theResult____h547110[11] &&
	      !_theResult____h547110[10] &&
	      !_theResult____h547110[9] &&
	      !_theResult____h547110[8] &&
	      !_theResult____h547110[7] &&
	      !_theResult____h547110[6] &&
	      !_theResult____h547110[5] &&
	      !_theResult____h547110[4] &&
	      !_theResult____h547110[3] &&
	      !_theResult____h547110[2] &&
	      !_theResult____h547110[1] &&
	      !_theResult____h547110[0]) ?
	       _theResult____h547110 :
	       _theResult___snd__h555386 ;
  assign _theResult___snd__h555386 =
	     { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q170[54:0],
	       2'd0 } ;
  assign _theResult___snd__h555409 =
	     _theResult____h547110 <<
	     IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10491 ;
  assign _theResult___snd__h564125 =
	     (f2_exp__h526522 == 8'd0) ?
	       _theResult___snd__h564139 :
	       _theResult___snd__h545722 ;
  assign _theResult___snd__h564139 =
	     (f2_exp__h526522 == 8'd0 && !f2_sfd__h526523[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10167) ?
	       sfd__h526884 :
	       _theResult___snd__h564145 ;
  assign _theResult___snd__h564145 =
	     { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q173[54:0],
	       2'd0 } ;
  assign _theResult___snd__h564163 =
	     sfd__h526884 <<
	     IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10542 ;
  assign _theResult___snd__h585024 =
	     (f3_exp__h565826 == 8'd0) ?
	       _theResult___snd__h585033 :
	       _theResult___snd__h585026 ;
  assign _theResult___snd__h585026 = { f3_sfd__h565827, 34'd0 } ;
  assign _theResult___snd__h585033 =
	     (f3_exp__h565826 == 8'd0 && !f3_sfd__h565827[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397) ?
	       sfd__h566188 :
	       _theResult___snd__h585039 ;
  assign _theResult___snd__h585039 =
	     { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q143[54:0],
	       2'd0 } ;
  assign _theResult___snd__h585062 =
	     sfd__h566188 <<
	     IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9424 ;
  assign _theResult___snd__h594661 = { _theResult____h586414[55:0], 1'd0 } ;
  assign _theResult___snd__h594672 =
	     (!_theResult____h586414[56] && _theResult____h586414[55]) ?
	       _theResult___snd__h594674 :
	       _theResult___snd__h594684 ;
  assign _theResult___snd__h594674 = { _theResult____h586414[54:0], 2'd0 } ;
  assign _theResult___snd__h594684 =
	     (!_theResult____h586414[56] && !_theResult____h586414[55] &&
	      !_theResult____h586414[54] &&
	      !_theResult____h586414[53] &&
	      !_theResult____h586414[52] &&
	      !_theResult____h586414[51] &&
	      !_theResult____h586414[50] &&
	      !_theResult____h586414[49] &&
	      !_theResult____h586414[48] &&
	      !_theResult____h586414[47] &&
	      !_theResult____h586414[46] &&
	      !_theResult____h586414[45] &&
	      !_theResult____h586414[44] &&
	      !_theResult____h586414[43] &&
	      !_theResult____h586414[42] &&
	      !_theResult____h586414[41] &&
	      !_theResult____h586414[40] &&
	      !_theResult____h586414[39] &&
	      !_theResult____h586414[38] &&
	      !_theResult____h586414[37] &&
	      !_theResult____h586414[36] &&
	      !_theResult____h586414[35] &&
	      !_theResult____h586414[34] &&
	      !_theResult____h586414[33] &&
	      !_theResult____h586414[32] &&
	      !_theResult____h586414[31] &&
	      !_theResult____h586414[30] &&
	      !_theResult____h586414[29] &&
	      !_theResult____h586414[28] &&
	      !_theResult____h586414[27] &&
	      !_theResult____h586414[26] &&
	      !_theResult____h586414[25] &&
	      !_theResult____h586414[24] &&
	      !_theResult____h586414[23] &&
	      !_theResult____h586414[22] &&
	      !_theResult____h586414[21] &&
	      !_theResult____h586414[20] &&
	      !_theResult____h586414[19] &&
	      !_theResult____h586414[18] &&
	      !_theResult____h586414[17] &&
	      !_theResult____h586414[16] &&
	      !_theResult____h586414[15] &&
	      !_theResult____h586414[14] &&
	      !_theResult____h586414[13] &&
	      !_theResult____h586414[12] &&
	      !_theResult____h586414[11] &&
	      !_theResult____h586414[10] &&
	      !_theResult____h586414[9] &&
	      !_theResult____h586414[8] &&
	      !_theResult____h586414[7] &&
	      !_theResult____h586414[6] &&
	      !_theResult____h586414[5] &&
	      !_theResult____h586414[4] &&
	      !_theResult____h586414[3] &&
	      !_theResult____h586414[2] &&
	      !_theResult____h586414[1] &&
	      !_theResult____h586414[0]) ?
	       _theResult____h586414 :
	       _theResult___snd__h594690 ;
  assign _theResult___snd__h594690 =
	     { IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q147[54:0],
	       2'd0 } ;
  assign _theResult___snd__h594713 =
	     _theResult____h586414 <<
	     IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9721 ;
  assign _theResult___snd__h603429 =
	     (f3_exp__h565826 == 8'd0) ?
	       _theResult___snd__h603443 :
	       _theResult___snd__h585026 ;
  assign _theResult___snd__h603443 =
	     (f3_exp__h565826 == 8'd0 && !f3_sfd__h565827[22] &&
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9397) ?
	       sfd__h566188 :
	       _theResult___snd__h603449 ;
  assign _theResult___snd__h603449 =
	     { IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q150[54:0],
	       2'd0 } ;
  assign _theResult___snd__h603467 =
	     sfd__h566188 <<
	     IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9772 ;
  assign _theResult___snd__h608923 =
	     b__h608375[63] ? b___1__h608988 : b__h608375 ;
  assign _theResult___snd_fst_exp__h368030 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ?
	       _theResult___fst_exp__h359445 :
	       _theResult___fst_exp__h368027 ;
  assign _theResult___snd_fst_exp__h385850 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ?
	       _theResult___fst_exp__h377211 :
	       _theResult___fst_exp__h385847 ;
  assign _theResult___snd_fst_exp__h413727 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ?
	       _theResult___fst_exp__h405142 :
	       _theResult___fst_exp__h413724 ;
  assign _theResult___snd_fst_exp__h431547 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ?
	       _theResult___fst_exp__h422908 :
	       _theResult___fst_exp__h431544 ;
  assign _theResult___snd_fst_exp__h459422 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ?
	       _theResult___fst_exp__h450837 :
	       _theResult___fst_exp__h459419 ;
  assign _theResult___snd_fst_exp__h477242 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ?
	       _theResult___fst_exp__h468603 :
	       _theResult___fst_exp__h477239 ;
  assign _theResult___snd_fst_exp__h507677 =
	     _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 ?
	       11'd0 :
	       _theResult___fst_exp__h507674 ;
  assign _theResult___snd_fst_exp__h526112 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ?
	       _theResult___fst_exp__h517325 :
	       _theResult___fst_exp__h526109 ;
  assign _theResult___snd_fst_exp__h546530 =
	     _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 ?
	       11'd0 :
	       _theResult___fst_exp__h546527 ;
  assign _theResult___snd_fst_exp__h564965 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ?
	       _theResult___fst_exp__h556178 :
	       _theResult___fst_exp__h564962 ;
  assign _theResult___snd_fst_exp__h585834 =
	     _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 ?
	       11'd0 :
	       _theResult___fst_exp__h585831 ;
  assign _theResult___snd_fst_exp__h604269 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ?
	       _theResult___fst_exp__h595482 :
	       _theResult___fst_exp__h604266 ;
  assign _theResult___snd_fst_sfd__h343082 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ==
	      23'd0) ?
	       23'd2097152 :
	       coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ;
  assign _theResult___snd_fst_sfd__h368031 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4109 ?
	       _theResult___fst_sfd__h359446 :
	       _theResult___fst_sfd__h368028 ;
  assign _theResult___snd_fst_sfd__h385851 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4649 ?
	       _theResult___fst_sfd__h377212 :
	       _theResult___fst_sfd__h385848 ;
  assign _theResult___snd_fst_sfd__h388784 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ==
	      23'd0) ?
	       23'd2097152 :
	       coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ;
  assign _theResult___snd_fst_sfd__h413728 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5501 ?
	       _theResult___fst_sfd__h405143 :
	       _theResult___fst_sfd__h413725 ;
  assign _theResult___snd_fst_sfd__h431548 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d6041 ?
	       _theResult___fst_sfd__h422909 :
	       _theResult___fst_sfd__h431545 ;
  assign _theResult___snd_fst_sfd__h434479 =
	     (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ==
	      23'd0) ?
	       23'd2097152 :
	       coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ;
  assign _theResult___snd_fst_sfd__h459423 =
	     _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6893 ?
	       _theResult___fst_sfd__h450838 :
	       _theResult___fst_sfd__h459420 ;
  assign _theResult___snd_fst_sfd__h477243 =
	     SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7433 ?
	       _theResult___fst_sfd__h468604 :
	       _theResult___fst_sfd__h477240 ;
  assign _theResult___snd_fst_sfd__h487844 =
	     (f1_sfd__h487529 == 23'd0) ?
	       52'h4000000000000 :
	       out___1_sfd__h487592 ;
  assign _theResult___snd_fst_sfd__h507678 =
	     _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8623 ?
	       52'd0 :
	       _theResult___fst_sfd__h507675 ;
  assign _theResult___snd_fst_sfd__h526113 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8759 ?
	       _theResult___fst_sfd__h517326 :
	       _theResult___fst_sfd__h526110 ;
  assign _theResult___snd_fst_sfd__h526838 =
	     (f2_sfd__h526523 == 23'd0) ?
	       52'h4000000000000 :
	       out___1_sfd__h526586 ;
  assign _theResult___snd_fst_sfd__h546531 =
	     _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10123 ?
	       52'd0 :
	       _theResult___fst_sfd__h546528 ;
  assign _theResult___snd_fst_sfd__h564966 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10244 ?
	       _theResult___fst_sfd__h556179 :
	       _theResult___fst_sfd__h564963 ;
  assign _theResult___snd_fst_sfd__h566142 =
	     (f3_sfd__h565827 == 23'd0) ?
	       52'h4000000000000 :
	       out___1_sfd__h565890 ;
  assign _theResult___snd_fst_sfd__h585835 =
	     _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9353 ?
	       52'd0 :
	       _theResult___fst_sfd__h585832 ;
  assign _theResult___snd_fst_sfd__h604270 =
	     SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9474 ?
	       _theResult___fst_sfd__h595483 :
	       _theResult___fst_sfd__h604267 ;
  assign a___1__h608536 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ?
	       { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } :
	       { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q3[31]}},
		 coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q3 } ;
  assign a___1__h608927 = 64'd0 - a__h608374 ;
  assign a__h608374 =
	     coreFix_fpuMulDivExe_0_regToExeQ$first[227] ?
	       a___1__h608536 :
	       coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ;
  assign b___1__h608537 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ?
	       { {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4[31]}},
		 coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4 } :
	       { 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ;
  assign b___1__h608988 = 64'd0 - b__h608375 ;
  assign b__h608375 =
	     coreFix_fpuMulDivExe_0_regToExeQ$first[227] ?
	       b___1__h608537 :
	       coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ;
  assign b__h608522 = { {64{a__h608374[63]}}, a__h608374 } ;
  assign b__h608598 = { {64{b__h608375[63]}}, b__h608375 } ;
  assign b__h608699 = { 64'd0, a__h608374 } ;
  assign b__h608711 = { 64'd0, b__h608375 } ;
  assign base__h711621 = { csrf_stvec_base_hi_reg, 2'b0 } ;
  assign base__h711641 = { csrf_mtvec_base_hi_reg, 2'b0 } ;
  assign cause_code__h708698 =
	     commitStage_commitTrap[36] ? i__h708873 : i__h708713 ;
  assign coreFix_aluExe_0_bypassWire_0_wget__2367_BITS__ETC___d12369 =
	     coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
	     coreFix_aluExe_0_dispToRegQ$first[84:78] ;
  assign coreFix_aluExe_0_bypassWire_0_wget__2367_BITS__ETC___d12410 =
	     coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
	     coreFix_aluExe_0_dispToRegQ$first[76:70] ;
  assign coreFix_aluExe_0_bypassWire_1_wget__2380_BITS__ETC___d12382 =
	     coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
	     coreFix_aluExe_0_dispToRegQ$first[84:78] ;
  assign coreFix_aluExe_0_bypassWire_1_wget__2380_BITS__ETC___d12416 =
	     coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
	     coreFix_aluExe_0_dispToRegQ$first[76:70] ;
  assign coreFix_aluExe_0_bypassWire_2_wget__2388_BITS__ETC___d12390 =
	     coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
	     coreFix_aluExe_0_dispToRegQ$first[84:78] ;
  assign coreFix_aluExe_0_bypassWire_2_wget__2388_BITS__ETC___d12420 =
	     coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
	     coreFix_aluExe_0_dispToRegQ$first[76:70] ;
  assign coreFix_aluExe_0_bypassWire_3_wget__2395_BITS__ETC___d12397 =
	     coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
	     coreFix_aluExe_0_dispToRegQ$first[84:78] ;
  assign coreFix_aluExe_0_bypassWire_3_wget__2395_BITS__ETC___d12424 =
	     coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
	     coreFix_aluExe_0_dispToRegQ$first[76:70] ;
  assign coreFix_aluExe_0_dispToRegQ_RDY_first__2344_AN_ETC___d12435 =
	     coreFix_aluExe_0_dispToRegQ$RDY_first &&
	     (coreFix_aluExe_0_dispToRegQ$first[131] ||
	      !coreFix_aluExe_0_dispToRegQ$first[85] ||
	      sbCons$lazyLookup_0_get[3] ||
	      IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2344_ETC___d12377 &&
	      IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12403) &&
	     (!coreFix_aluExe_0_dispToRegQ$first[77] ||
	      sbCons$lazyLookup_0_get[2] ||
	      IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2344_ETC___d12413 &&
	      IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12430) ;
  assign coreFix_aluExe_0_exeToFinQ_RDY_first__2811_AND_ETC___d12851 =
	     coreFix_aluExe_0_exeToFinQ$RDY_first &&
	     rob$RDY_setExecuted_doFinishAlu_0_set &&
	     (coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd9 &&
	      coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd10 ||
	      coreFix_trainBPQ_0$FULL_N) ;
  assign coreFix_aluExe_0_rsAlu_approximateCount__3562__ETC___d13564 =
	     coreFix_aluExe_0_rsAlu$approximateCount <
	     coreFix_aluExe_1_rsAlu$approximateCount ;
  assign coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11513 =
	     coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
	     coreFix_aluExe_1_dispToRegQ$first[84:78] ;
  assign coreFix_aluExe_1_bypassWire_0_wget__1511_BITS__ETC___d11554 =
	     coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
	     coreFix_aluExe_1_dispToRegQ$first[76:70] ;
  assign coreFix_aluExe_1_bypassWire_1_wget__1524_BITS__ETC___d11526 =
	     coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
	     coreFix_aluExe_1_dispToRegQ$first[84:78] ;
  assign coreFix_aluExe_1_bypassWire_1_wget__1524_BITS__ETC___d11560 =
	     coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
	     coreFix_aluExe_1_dispToRegQ$first[76:70] ;
  assign coreFix_aluExe_1_bypassWire_2_wget__1532_BITS__ETC___d11534 =
	     coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
	     coreFix_aluExe_1_dispToRegQ$first[84:78] ;
  assign coreFix_aluExe_1_bypassWire_2_wget__1532_BITS__ETC___d11564 =
	     coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
	     coreFix_aluExe_1_dispToRegQ$first[76:70] ;
  assign coreFix_aluExe_1_bypassWire_3_wget__1539_BITS__ETC___d11541 =
	     coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
	     coreFix_aluExe_1_dispToRegQ$first[84:78] ;
  assign coreFix_aluExe_1_bypassWire_3_wget__1539_BITS__ETC___d11568 =
	     coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
	     coreFix_aluExe_1_dispToRegQ$first[76:70] ;
  assign coreFix_aluExe_1_dispToRegQ_RDY_first__1488_AN_ETC___d11579 =
	     coreFix_aluExe_1_dispToRegQ$RDY_first &&
	     (coreFix_aluExe_1_dispToRegQ$first[131] ||
	      !coreFix_aluExe_1_dispToRegQ$first[85] ||
	      sbCons$lazyLookup_1_get[3] ||
	      IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1488_ETC___d11521 &&
	      IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11547) &&
	     (!coreFix_aluExe_1_dispToRegQ$first[77] ||
	      sbCons$lazyLookup_1_get[2] ||
	      IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1488_ETC___d11557 &&
	      IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11574) ;
  assign coreFix_aluExe_1_exeToFinQ_RDY_first__2137_AND_ETC___d12178 =
	     coreFix_aluExe_1_exeToFinQ$RDY_first &&
	     rob$RDY_setExecuted_doFinishAlu_1_set &&
	     (coreFix_aluExe_1_exeToFinQ$first[326:322] != 5'd9 &&
	      coreFix_aluExe_1_exeToFinQ$first[326:322] != 5'd10 ||
	      coreFix_trainBPQ_1$FULL_N) ;
  assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8303 =
	     coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
  assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8343 =
	     coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
  assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__301__ETC___d8369 =
	     coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
  assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__314__ETC___d8316 =
	     coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
  assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__314__ETC___d8349 =
	     coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
  assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__314__ETC___d8375 =
	     coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
  assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__322__ETC___d8324 =
	     coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
  assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__322__ETC___d8353 =
	     coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
  assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__322__ETC___d8379 =
	     coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
  assign coreFix_fpuMulDivExe_0_bypassWire_3_wget__329__ETC___d8331 =
	     coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
  assign coreFix_fpuMulDivExe_0_bypassWire_3_wget__329__ETC___d8357 =
	     coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
  assign coreFix_fpuMulDivExe_0_bypassWire_3_wget__329__ETC___d8383 =
	     coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
	     coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
  assign coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first__2_ETC___d8395 =
	     coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
	     (!coreFix_fpuMulDivExe_0_dispToRegQ$first[56] ||
	      sbCons$lazyLookup_2_get[3] ||
	      IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8311 &&
	      IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8337) &&
	     (!coreFix_fpuMulDivExe_0_dispToRegQ$first[48] ||
	      sbCons$lazyLookup_2_get[2] ||
	      IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8346 &&
	      IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8363) &&
	     (!coreFix_fpuMulDivExe_0_dispToRegQ$first[40] ||
	      sbCons$lazyLookup_2_get[1] ||
	      IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8372 &&
	      IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8389) ;
  assign coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5368 =
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned &&
	     !coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned &&
	     rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
	     coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get &&
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_data ;
  assign coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q64 =
	     coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] -
	     11'd1023 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q29 =
	     coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] -
	     11'd1023 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q99 =
	     coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] -
	     11'd1023 ;
  assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3976 =
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned &&
	     !coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned &&
	     rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
	     coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get &&
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_data ;
  assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6760 =
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned &&
	     !coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned &&
	     rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
	     coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get &&
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_data ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_enq_ETC___d8538 =
	     coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$FULL_N &&
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$FULL_N ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11256 =
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[139:76] /
	     IF_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_d_ETC___d11255 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11257 =
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[139:76] %
	     IF_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_d_ETC___d11255 ;
  assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8152 =
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned &&
	     !coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned &&
	     rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_data &&
	     coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N ;
  assign coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d10963 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
	     NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10918 |
	     ((f3_exp__h565826 != 8'd255 || f3_sfd__h565827 == 23'd0) &&
	      (f3_exp__h565826 != 8'd255 || f3_sfd__h565827 != 23'd0) &&
	      (f3_exp__h565826 != 8'd0 || f3_sfd__h565827 != 23'd0) &&
	      IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10958) ;
  assign coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d10999 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
	     NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10987 |
	     ((f3_exp__h565826 != 8'd255 || f3_sfd__h565827 == 23'd0) &&
	      (f3_exp__h565826 != 8'd255 || f3_sfd__h565827 != 23'd0) &&
	      (f3_exp__h565826 != 8'd0 || f3_sfd__h565827 != 23'd0) &&
	      IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10994) ;
  assign coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11047 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
	     NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11031 |
	     ((f3_exp__h565826 != 8'd255 || f3_sfd__h565827 == 23'd0) &&
	      (f3_exp__h565826 != 8'd255 || f3_sfd__h565827 != 23'd0) &&
	      (f3_exp__h565826 != 8'd0 || f3_sfd__h565827 != 23'd0) &&
	      IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11042) ;
  assign coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11089 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
	     NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11075 |
	     ((f3_exp__h565826 != 8'd255 || f3_sfd__h565827 == 23'd0) &&
	      (f3_exp__h565826 != 8'd255 || f3_sfd__h565827 != 23'd0) &&
	      (f3_exp__h565826 != 8'd0 || f3_sfd__h565827 != 23'd0) &&
	      IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11084) ;
  assign coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11131 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
	     NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11117 |
	     ((f3_exp__h565826 != 8'd255 || f3_sfd__h565827 == 23'd0) &&
	      (f3_exp__h565826 != 8'd255 || f3_sfd__h565827 != 23'd0) &&
	      (f3_exp__h565826 != 8'd0 || f3_sfd__h565827 != 23'd0) &&
	      IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11126) ;
  assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q4 =
	     coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ;
  assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q3 =
	     coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] ;
  assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14116 =
	     coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq &&
	     regRenamingTable$RDY_rename_1_getRename &&
	     (!fetchStage$pipelines_0_canDeq ||
	      NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14096) ;
  assign coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1587 =
	     coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
	     coreFix_memExe_dispToRegQ$first[61:55] ;
  assign coreFix_memExe_bypassWire_0_wget__585_BITS_70__ETC___d1627 =
	     coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
	     coreFix_memExe_dispToRegQ$first[53:47] ;
  assign coreFix_memExe_bypassWire_1_wget__598_BITS_70__ETC___d1600 =
	     coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
	     coreFix_memExe_dispToRegQ$first[61:55] ;
  assign coreFix_memExe_bypassWire_1_wget__598_BITS_70__ETC___d1633 =
	     coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
	     coreFix_memExe_dispToRegQ$first[53:47] ;
  assign coreFix_memExe_bypassWire_2_wget__606_BITS_70__ETC___d1608 =
	     coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
	     coreFix_memExe_dispToRegQ$first[61:55] ;
  assign coreFix_memExe_bypassWire_2_wget__606_BITS_70__ETC___d1637 =
	     coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
	     coreFix_memExe_dispToRegQ$first[53:47] ;
  assign coreFix_memExe_bypassWire_3_wget__613_BITS_70__ETC___d1615 =
	     coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
	     coreFix_memExe_dispToRegQ$first[61:55] ;
  assign coreFix_memExe_bypassWire_3_wget__613_BITS_70__ETC___d1641 =
	     coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
	     coreFix_memExe_dispToRegQ$first[53:47] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2605 =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd3 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2100 ||
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
	     2'd0 &&
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] ==
	     y__h258435 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3163 =
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3127 ||
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT ||
	      !WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry &&
	      !coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl) &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full ;
  assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3266 =
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3234 ||
	     (!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT ||
	      !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas &&
	      !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl) &&
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
  assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2098 =
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] ==
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2178 =
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2098 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2821 =
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] &&
	     coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] ==
	     coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[65:8] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] ==
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <
	     2'd2 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518] ==
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2559 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055 &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	      3'd3 ||
	      coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2178) ||
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2588 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd2 ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	      3'd3) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2593 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2585 ||
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2592 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2610 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2585 ||
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2609 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2627 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2620 ||
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2626 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2647 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 &&
	     coreFix_memExe_lsq$getHit[8] &&
	     !coreFix_memExe_lsq$getHit[9] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2650 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd0 &&
	     coreFix_memExe_lsq$getHit[8] &&
	     !coreFix_memExe_lsq$getHit[9] ||
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd1) &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2647 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2671 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
	     3'd3 &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2100 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2677 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2671 ||
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
	      coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	      3'd1) &&
	     NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2674 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2679 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055 &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	      3'd3 ||
	      coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2178) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2701 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2714 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 &&
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055 &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	      3'd3 ||
	      coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2178) &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot[0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2726 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	     3'd0 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	     3'd2 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	     3'd4 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	     3'd3 &&
	     coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	     3'd1 ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2737 =
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
	      2'd0 ||
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124) &&
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot[0] ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2757 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	     (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124 ||
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 &&
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2055) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2771 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <=
	     coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2774 =
	     coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518] ==
	     coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[65:14] ;
  assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2797 =
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2771 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2774) &&
	     !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
	     (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
	      2'd1 ||
	      coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] !=
	      2'd1 ||
	      !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2774) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2890 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[78] :
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[78]) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2894 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[77] :
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[77]) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2898 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[76] :
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[76]) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2903 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[75] :
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[75]) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2907 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[74] :
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[74]) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2912 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[73] :
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[73]) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2916 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[72] :
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[72]) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2921 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[71] :
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[71]) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2933 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[2] :
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[2]) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2937 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[1] :
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[1]) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2941 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[0] :
		coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[0]) ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enq_ETC___d3437 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3405 ||
	     (!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT ||
	      !EN_dCacheToParent_rqToP_deq &&
	      !coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl) &&
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full ;
  assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enq_ETC___d3533 =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3501 ||
	     (!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT ||
	      !EN_dCacheToParent_rsToP_deq &&
	      !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl) &&
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full ;
  assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2_r_ETC___d1936 =
	     coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT &&
	     coreFix_memExe_dMem_perfReqQ_enqReq_rl[4] ||
	     (!coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT ||
	      !coreFix_memExe_dMem_perfReqQ_deqReq_rl) &&
	     coreFix_memExe_dMem_perfReqQ_full ;
  assign coreFix_memExe_dTlb_procResp__740_BITS_105_TO__ETC___d1894 =
	     coreFix_memExe_dTlb$procResp[105:103] == 3'd0 &&
	     NOT_coreFix_memExe_dTlb_procResp__740_BITS_174_ETC___d1779 &&
	     IF_coreFix_memExe_dTlb_procResp__740_BIT_110_7_ETC___d1768 &&
	     !coreFix_memExe_lsq$updateAddr ;
  assign coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1750 =
	     coreFix_memExe_dTlb$procResp[174:114] < 61'd268435456 ;
  assign coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1751 =
	     coreFix_memExe_dTlb$procResp[174:114] < 61'd301989888 ;
  assign coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1755 =
	     coreFix_memExe_dTlb$procResp[174:114] == mmio_toHostAddr ;
  assign coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1758 =
	     coreFix_memExe_dTlb$procResp[174:114] == mmio_fromHostAddr ;
  assign coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1759 =
	     coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1750 ||
	     !coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1751 ||
	     coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1755 ||
	     coreFix_memExe_dTlb_procResp__740_BITS_174_TO__ETC___d1758 ;
  assign coreFix_memExe_forwardQ_enqReq_dummy2_2_read___ETC___d3855 =
	     coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3824 ||
	     (!coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT ||
	      !WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	      !coreFix_memExe_forwardQ_deqReq_rl) &&
	     coreFix_memExe_forwardQ_full ;
  assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3761 =
	     coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3730 ||
	     (!coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT ||
	      !WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	      !coreFix_memExe_memRespLdQ_deqReq_rl) &&
	     coreFix_memExe_memRespLdQ_full ;
  assign coreFix_memExe_regToExeQ_RDY_enq__563_AND_core_ETC___d1653 =
	     coreFix_memExe_regToExeQ$RDY_enq &&
	     coreFix_memExe_dispToRegQ$RDY_first &&
	     (!coreFix_memExe_dispToRegQ$first[62] ||
	      sbCons$lazyLookup_3_get[3] ||
	      IF_coreFix_memExe_dispToRegQ_RDY_first__564_AN_ETC___d1595 &&
	      IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1621) &&
	     (!coreFix_memExe_dispToRegQ$first[54] ||
	      sbCons$lazyLookup_3_get[2] ||
	      IF_coreFix_memExe_dispToRegQ_RDY_first__564_AN_ETC___d1630 &&
	      IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1647) ;
  assign coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q5 =
	     coreFix_memExe_regToExeQ$first[189:158] ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[78] :
		coreFix_memExe_reqLrScAmoQ_data_0_rl[78]) ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1228 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[77] :
		coreFix_memExe_reqLrScAmoQ_data_0_rl[77]) ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1232 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[76] :
		coreFix_memExe_reqLrScAmoQ_data_0_rl[76]) ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1237 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[75] :
		coreFix_memExe_reqLrScAmoQ_data_0_rl[75]) ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1241 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[74] :
		coreFix_memExe_reqLrScAmoQ_data_0_rl[74]) ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1246 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[73] :
		coreFix_memExe_reqLrScAmoQ_data_0_rl[73]) ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1250 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[72] :
		coreFix_memExe_reqLrScAmoQ_data_0_rl[72]) ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1255 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[71] :
		coreFix_memExe_reqLrScAmoQ_data_0_rl[71]) ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[2] :
		coreFix_memExe_reqLrScAmoQ_data_0_rl[2]) ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1271 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[1] :
		coreFix_memExe_reqLrScAmoQ_data_0_rl[1]) ;
  assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1275 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
	     (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[0] :
		coreFix_memExe_reqLrScAmoQ_data_0_rl[0]) ;
  assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3670 =
	     coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT &&
	     IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3654 ||
	     (!coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT ||
	      !coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas &&
	      !coreFix_memExe_respLrScAmoQ_deqReq_rl) &&
	     coreFix_memExe_respLrScAmoQ_full ;
  assign coreFix_memExe_stb_isEmpty__011_AND_coreFix_me_ETC___d14793 =
	     coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty &&
	     regRenamingTable$RDY_commit_0_commit &&
	     rob$RDY_deqPort_0_deq &&
	     rob$RDY_deqPort_0_deq_data &&
	     fetchStage$iTlbIfc_noPendingReq &&
	     coreFix_memExe_dTlb$noPendingReq &&
	     NOT_rob_deqPort_0_deq_data__4466_BITS_257_TO_2_ETC___d14788 ;
  assign csr_addr__h661843 =
	     fetchStage$pipelines_0_first[173] ?
	       IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125 :
	       12'hCFF ;
  assign csrf_external_int_en_vec_3_read__1844_AND_csrf_ETC___d12967 =
	     { csrf_external_int_en_vec_3 & csrf_external_int_pend_vec_3,
	       1'd0,
	       csrf_external_int_en_vec_1 & csrf_external_int_pend_vec_1,
	       1'd0,
	       csrf_timer_int_en_vec_3 & csrf_timer_int_pend_vec_3,
	       1'd0,
	       csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1,
	       1'd0 } ;
  assign csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13197 =
	     csrf_fs_reg == 2'd0 &&
	     (fetchStage$pipelines_0_first[95] &&
	      fetchStage$pipelines_0_first[94] ||
	      fetchStage$pipelines_0_first[88] &&
	      fetchStage$pipelines_0_first[87] ||
	      fetchStage$pipelines_0_first[81] ||
	      fetchStage$pipelines_0_first[75] &&
	      fetchStage$pipelines_0_first[74]) ||
	     fetchStage$pipelines_0_first[199:195] == 5'd13 &&
	     (fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13190 ||
	      csrf_prv_reg_read__2956_ULT_IF_fetchStage_pipe_ETC___d13192 ||
	      csr_addr__h661843 == 12'h8FF) ;
  assign csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13620 =
	     csrf_fs_reg == 2'd0 &&
	     (fetchStage$pipelines_0_first[95] &&
	      fetchStage$pipelines_0_first[94] ||
	      fetchStage$pipelines_0_first[88] &&
	      fetchStage$pipelines_0_first[87] ||
	      fetchStage$pipelines_0_first[81] ||
	      fetchStage$pipelines_0_first[75] &&
	      fetchStage$pipelines_0_first[74]) ||
	     fetchStage$pipelines_0_first[231:200] == 32'h10500073 &&
	     csrf_tw_reg &&
	     csrf_prv_reg != 2'd3 ;
  assign csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13896 =
	     csrf_fs_reg == 2'd0 &&
	     (fetchStage$pipelines_1_first[95] &&
	      fetchStage$pipelines_1_first[94] ||
	      fetchStage$pipelines_1_first[88] &&
	      fetchStage$pipelines_1_first[87] ||
	      fetchStage$pipelines_1_first[81] ||
	      fetchStage$pipelines_1_first[75] &&
	      fetchStage$pipelines_1_first[74]) ||
	     fetchStage$pipelines_1_first[231:200] == 32'h10500073 &&
	     csrf_tw_reg &&
	     csrf_prv_reg != 2'd3 ;
  assign csrf_prv_reg_read__2956_ULE_1_4607_AND_IF_comm_ETC___d14646 =
	     csrf_prv_reg_read__2956_ULE_1___d14607 &&
	     (commitStage_commitTrap[36] ?
		_0b0_CONCAT_csrf_mideleg_11_reg_read__1833_1834_ETC___d14625 :
		_0b0_CONCAT_csrf_medeleg_15_reg_read__1825_1826_ETC___d14644) ;
  assign csrf_prv_reg_read__2956_ULE_1___d14607 = csrf_prv_reg <= 2'd1 ;
  assign csrf_prv_reg_read__2956_ULT_IF_fetchStage_pipe_ETC___d13192 =
	     csrf_prv_reg < csr_addr__h661843[9:8] ;
  assign data79263_BITS_31_TO_0__q2 = data__h479263[31:0] ;
  assign data80195_BITS_31_TO_0__q6 = data__h480195[31:0] ;
  assign data___1__h479775 =
	     { {32{data79263_BITS_31_TO_0__q2[31]}},
	       data79263_BITS_31_TO_0__q2 } ;
  assign data___1__h480707 =
	     { {32{data80195_BITS_31_TO_0__q6[31]}},
	       data80195_BITS_31_TO_0__q6 } ;
  assign data__h479263 =
	     (coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] ==
	      2'd0) ?
	       coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[63:0] :
	       coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[127:64] ;
  assign data__h480195 =
	     (coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] ==
	      2'd2) ?
	       x_quotient__h479959 :
	       x_remainder__h479960 ;
  assign din_inc___2_exp__h385881 = _theResult___fst_exp__h358848 + 8'd1 ;
  assign din_inc___2_exp__h385905 = _theResult___fst_exp__h367504 + 8'd1 ;
  assign din_inc___2_exp__h385935 = _theResult___fst_exp__h376614 + 8'd1 ;
  assign din_inc___2_exp__h385959 = _theResult___fst_exp__h385299 + 8'd1 ;
  assign din_inc___2_exp__h431578 = _theResult___fst_exp__h404545 + 8'd1 ;
  assign din_inc___2_exp__h431602 = _theResult___fst_exp__h413201 + 8'd1 ;
  assign din_inc___2_exp__h431632 = _theResult___fst_exp__h422311 + 8'd1 ;
  assign din_inc___2_exp__h431656 = _theResult___fst_exp__h430996 + 8'd1 ;
  assign din_inc___2_exp__h477273 = _theResult___fst_exp__h450240 + 8'd1 ;
  assign din_inc___2_exp__h477297 = _theResult___fst_exp__h458896 + 8'd1 ;
  assign din_inc___2_exp__h477327 = _theResult___fst_exp__h468006 + 8'd1 ;
  assign din_inc___2_exp__h477351 = _theResult___fst_exp__h476691 + 8'd1 ;
  assign din_inc___2_exp__h526166 = _theResult___fst_exp__h506916 + 11'd1 ;
  assign din_inc___2_exp__h526201 = _theResult___fst_exp__h516493 + 11'd1 ;
  assign din_inc___2_exp__h526227 = _theResult___fst_exp__h525326 + 11'd1 ;
  assign din_inc___2_exp__h565019 = _theResult___fst_exp__h545769 + 11'd1 ;
  assign din_inc___2_exp__h565054 = _theResult___fst_exp__h555346 + 11'd1 ;
  assign din_inc___2_exp__h565080 = _theResult___fst_exp__h564179 + 11'd1 ;
  assign din_inc___2_exp__h604323 = _theResult___fst_exp__h585073 + 11'd1 ;
  assign din_inc___2_exp__h604358 = _theResult___fst_exp__h594650 + 11'd1 ;
  assign din_inc___2_exp__h604384 = _theResult___fst_exp__h603483 + 11'd1 ;
  assign enabled_ints___1__h658447 = pend_ints__h658032 & y__h658459 ;
  assign enabled_ints__h658493 =
	     pend_ints__h658032 &
	     { r1__read_BITS_9_TO_0___h658469, csrf_mideleg_1_0_reg } ;
  assign f1_exp87528_MINUS_127__q128 = f1_exp__h487528 - 8'd127 ;
  assign f1_exp__h487528 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] :
	       8'd255 ;
  assign f1_sfd__h487529 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] :
	       23'd4194304 ;
  assign f2_exp26522_MINUS_127__q168 = f2_exp__h526522 - 8'd127 ;
  assign f2_exp__h526522 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] :
	       8'd255 ;
  assign f2_sfd__h526523 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] :
	       23'd4194304 ;
  assign f3_exp65826_MINUS_127__q145 = f3_exp__h565826 - 8'd127 ;
  assign f3_exp__h565826 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] :
	       8'd255 ;
  assign f3_sfd__h565827 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ?
	       coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] :
	       23'd4194304 ;
  assign fallthrough_pc__h671324 =
	     (fetchStage$pipelines_0_first[97:96] == 2'b11) ?
	       fetchStage$pipelines_0_first[387:324] + 64'd4 :
	       fetchStage$pipelines_0_first[387:324] + 64'd2 ;
  assign fallthrough_pc__h687070 =
	     (fetchStage$pipelines_1_first[97:96] == 2'b11) ?
	       fetchStage$pipelines_1_first[387:324] + 64'd4 :
	       fetchStage$pipelines_1_first[387:324] + 64'd2 ;
  assign fcsr_csr__read__h616235 = { 56'd0, x__h619375 } ;
  assign fetchStage_RDY_pipelines_0_first__2925_AND_NOT_ETC___d13551 =
	     fetchStage$RDY_pipelines_0_first &&
	     (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	      specTagManager$canClaim) &&
	     regRenamingTable$rename_0_canRename &&
	     NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548 ;
  assign fetchStage_RDY_pipelines_0_first__2925_AND_epo_ETC___d13407 =
	     fetchStage$RDY_pipelines_0_first &&
	     epochManager$RDY_incrementEpoch &&
	     regRenamingTable$RDY_rename_0_getRename &&
	     regRenamingTable$RDY_rename_0_claimRename &&
	     rob$RDY_enqPort_0_enq &&
	     (fetchStage$pipelines_0_first[194:192] != 3'd0 ||
	      coreFix_aluExe_0_rsAlu$RDY_enq) ;
  assign fetchStage_RDY_pipelines_0_first__2925_AND_fet_ETC___d13617 =
	     fetchStage$RDY_pipelines_0_first &&
	     fetchStage$pipelines_1_first[194:192] == 3'd1 &&
	     regRenamingTable_rename_0_canRename__3528_AND__ETC___d13612 ||
	     !fetchStage$pipelines_0_canDeq ||
	     fetchStage$RDY_pipelines_0_first &&
	     IF_fetchStage_RDY_pipelines_0_first__2925_AND__ETC___d13555 ;
  assign fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14107 =
	     fetchStage$pipelines_0_canDeq &&
	     (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	      specTagManager$canClaim) &&
	     regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598 &&
	     fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13851 ||
	     !coreFix_aluExe_0_rsAlu$canEnq ||
	     NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14106 ;
  assign fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14186 =
	     fetchStage$pipelines_0_canDeq &&
	     NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183 &&
	     (fetchStage$pipelines_0_first[194:192] == 3'd0 ||
	      fetchStage$pipelines_0_first[194:192] == 3'd1) &&
	     SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 ;
  assign fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14305 =
	     fetchStage$pipelines_0_canDeq &&
	     NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d14183 &&
	     fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13851 ||
	     !coreFix_aluExe_0_rsAlu$canEnq ||
	     (!fetchStage$pipelines_0_canDeq ||
	      fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14300 ||
	      fetchStage$pipelines_0_first[194:192] != 3'd0 &&
	      fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	      !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568) &&
	     coreFix_aluExe_1_rsAlu$canEnq &&
	     !coreFix_aluExe_0_rsAlu_approximateCount__3562__ETC___d13564 ;
  assign fetchStage_pipelines_0_canDeq__2926_AND_fetchS_ETC___d14175 =
	     fetchStage$pipelines_0_canDeq &&
	     fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14058 ||
	     !fetchStage$pipelines_1_canDeq ||
	     fetchStage$RDY_pipelines_1_first &&
	     (fetchStage_pipelines_1_first__2937_BITS_194_TO_ETC___d14069 ||
	      NOT_regRenamingTable_rename_1_canRename__3647__ETC___d14075 ||
	      IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14171) &&
	     IF_fetchStage_RDY_pipelines_1_first__2936_AND__ETC___d14002 ;
  assign fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14113 =
	     fetchStage$pipelines_0_canDeq &&
	     regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598 &&
	     (fetchStage$pipelines_0_first[194:192] == 3'd3 ||
	      fetchStage$pipelines_0_first[194:192] == 3'd4) ;
  assign fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14120 =
	     fetchStage$pipelines_0_canDeq &&
	     regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598 &&
	     fetchStage$pipelines_0_first[194:192] == 3'd2 &&
	     IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 ||
	     !coreFix_memExe_rsMem$canEnq ||
	     CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 ;
  assign fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14141 =
	     fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14113 ||
	     !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
	     fetchStage$pipelines_0_canDeq &&
	     (fetchStage$pipelines_0_first[194:192] == 3'd1 &&
	      !specTagManager$canClaim ||
	      NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13627 ||
	      IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14133) ;
  assign fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14152 =
	     fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14120 ||
	     fetchStage$pipelines_0_canDeq &&
	     (fetchStage$pipelines_0_first[194:192] == 3'd1 &&
	      !specTagManager$canClaim ||
	      NOT_regRenamingTable_rename_0_canRename__3528__ETC___d13627 ||
	      IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14144) ;
  assign fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14441 =
	     fetchStage$pipelines_0_canDeq &&
	     regRenamingTable_rename_0_canRename__3528_AND__ETC___d14439 ||
	     !coreFix_memExe_rsMem$canEnq ||
	     CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 ;
  assign fetchStage_pipelines_0_canDeq__2926_AND_specTa_ETC___d14269 =
	     fetchStage$pipelines_0_canDeq && specTagManager$canClaim &&
	     regRenamingTable$rename_0_canRename &&
	     !checkForException___d13160[4] &&
	     rob$enqPort_0_canEnq &&
	     IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 &&
	     fetchStage$pipelines_0_first[194:192] == 3'd1 ;
  assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13190 =
	     (fetchStage$pipelines_0_first[194:192] == 3'd0 &&
	      fetchStage$pipelines_0_first[178:174] == 5'd15 ||
	      rs1__h661844 != 5'd0 ||
	      imm__h661845 != 32'd0) &&
	     csr_addr__h661843[11:10] == 2'b11 ;
  assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13851 =
	     (fetchStage$pipelines_0_first[194:192] == 3'd0 ||
	      fetchStage$pipelines_0_first[194:192] == 3'd1) &&
	     SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 &&
	     (!coreFix_aluExe_1_rsAlu$canEnq ||
	      coreFix_aluExe_0_rsAlu_approximateCount__3562__ETC___d13564) ;
  assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13872 =
	     fetchStage$pipelines_0_first[194:192] == 3'd1 &&
	     !specTagManager$canClaim ||
	     !regRenamingTable$rename_0_canRename ||
	     fetchStage_pipelines_0_first__2928_BITS_199_TO_ETC___d13865 ||
	     fetchStage$pipelines_0_first[194:192] != 3'd0 &&
	     fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	     !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 ;
  assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13944 =
	     fetchStage$pipelines_0_first[194:192] == 3'd1 &&
	     !specTagManager$canClaim ||
	     fetchStage$pipelines_0_first[68] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[1] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[2] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[3] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[4] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[5] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[6] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[7] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[8] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[9] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[10] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[11] ;
  assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14052 =
	     fetchStage$pipelines_0_first[194:192] == 3'd1 &&
	     !specTagManager$canClaim ||
	     NOT_regRenamingTable_rename_0_canRename__3528__ETC___d14017 ||
	     IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14041 &&
	     IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14050 ;
  assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14058 =
	     fetchStage$pipelines_0_first[194:192] == 3'd1 &&
	     !specTagManager$canClaim ||
	     NOT_regRenamingTable_rename_0_canRename__3528__ETC___d14017 ||
	     IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14057 ;
  assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14080 =
	     fetchStage$pipelines_0_first[194:192] == 3'd1 &&
	     !specTagManager$canClaim ||
	     !regRenamingTable$rename_0_canRename ||
	     fetchStage_pipelines_0_first__2928_BITS_199_TO_ETC___d13865 ||
	     fetchStage$pipelines_0_first[194:192] != 3'd0 &&
	     fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	     !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 ||
	     coreFix_aluExe_1_rsAlu$canEnq &&
	     !coreFix_aluExe_0_rsAlu_approximateCount__3562__ETC___d13564 ;
  assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14087 =
	     fetchStage$pipelines_0_first[194:192] == 3'd1 &&
	     !specTagManager$canClaim ||
	     !regRenamingTable$rename_0_canRename ||
	     fetchStage_pipelines_0_first__2928_BITS_199_TO_ETC___d13865 ||
	     fetchStage$pipelines_0_first[194:192] != 3'd0 &&
	     fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	     !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 ||
	     coreFix_aluExe_0_rsAlu$canEnq &&
	     coreFix_aluExe_0_rsAlu_approximateCount__3562__ETC___d13564 ;
  assign fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14300 =
	     fetchStage$pipelines_0_first[194:192] == 3'd1 &&
	     !specTagManager$canClaim ||
	     !regRenamingTable$rename_0_canRename ||
	     fetchStage$pipelines_0_first[68] ||
	     checkForException___d13160[4] ||
	     !rob$enqPort_0_canEnq ;
  assign fetchStage_pipelines_0_first__2928_BITS_199_TO_ETC___d13865 =
	     fetchStage$pipelines_0_first[199:195] == 5'd0 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd21 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd17 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd18 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd13 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd16 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd15 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd19 ||
	     fetchStage$pipelines_0_first[199:195] == 5'd20 ||
	     fetchStage$pipelines_0_first[68] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13862 ||
	     !rob$enqPort_0_canEnq ||
	     !epochManager$checkEpoch_0_check ;
  assign fetchStage_pipelines_0_first__2928_BIT_173_304_ETC___d13522 =
	     { fetchStage$pipelines_0_first[173],
	       IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125,
	       73'h1280000000000000000,
	       fetchStage$pipelines_0_first[323:260],
	       5'd0,
	       (fetchStage$pipelines_0_first[173] &&
		fetchStage$pipelines_0_first[199:195] == 5'd13 &&
		(fetchStage$pipelines_0_first[172:161] == 12'd1 ||
		 fetchStage$pipelines_0_first[172:161] == 12'd2 ||
		 fetchStage$pipelines_0_first[172:161] == 12'd3)) ?
		 fetchStage$pipelines_0_first[194:192] == 3'd0 &&
		 fetchStage$pipelines_0_first[178:174] == 5'd15 ||
		 (!fetchStage$pipelines_0_first[88] ||
		  fetchStage$pipelines_0_first[87] ||
		  fetchStage$pipelines_0_first[86:82] != 5'd0) &&
		 (!fetchStage$pipelines_0_first[160] ||
		  fetchStage$pipelines_0_first[159:128] != 32'd0) :
		 fetchStage$pipelines_0_first[75] &&
		 fetchStage$pipelines_0_first[74],
	       fetchStage$pipelines_0_first[194:192] != 3'd0,
	       13'h1521,
	       specTagManager$currentSpecBits } ;
  assign fetchStage_pipelines_0_first__2928_BIT_68_2955_ETC___d13625 =
	     fetchStage$pipelines_0_first[68] ||
	     checkForException___d13160[4] ||
	     csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13620 ||
	     !rob$enqPort_0_canEnq ||
	     !epochManager$checkEpoch_0_check ;
  assign fetchStage_pipelines_1_first__2937_BITS_194_TO_ETC___d14069 =
	     fetchStage$pipelines_1_first[194:192] == 3'd1 &&
	     (fetchStage$pipelines_0_canDeq &&
	      regRenamingTable_rename_0_canRename__3528_AND__ETC___d14066 ||
	      !specTagManager$canClaim) ;
  assign fetchStage_pipelines_1_first__2937_BITS_199_TO_ETC___d13904 =
	     fetchStage$pipelines_1_first[199:195] == 5'd0 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd21 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd17 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd18 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd13 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd16 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd15 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd19 ||
	     fetchStage$pipelines_1_first[199:195] == 5'd20 ||
	     fetchStage$pipelines_1_first[68] ||
	     IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13898 ||
	     !rob$enqPort_1_canEnq ||
	     !epochManager$checkEpoch_1_check ||
	     !fetchStage$pipelines_0_canDeq ||
	     fetchStage$RDY_pipelines_0_first &&
	     IF_fetchStage_RDY_pipelines_0_first__2925_AND__ETC___d13555 ;
  assign fetchStage_pipelines_1_first__2937_BIT_173_370_ETC___d13785 =
	     { fetchStage$pipelines_1_first[173],
	       CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228 } ;
  assign fetchStage_pipelines_1_first__2937_BIT_68_3675_ETC___d14073 =
	     fetchStage$pipelines_1_first[68] ||
	     checkForException___d13807[4] ||
	     csrf_fs_reg_read__1726_EQ_0_3149_AND_fetchStag_ETC___d13896 ||
	     !rob$enqPort_1_canEnq ||
	     !epochManager$checkEpoch_1_check ||
	     fetchStage$pipelines_0_canDeq &&
	     fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14058 ;
  assign fflags__h723387 =
	     NOT_rob_deqPort_0_canDeq__4995_4996_OR_rob_deq_ETC___d15187 ?
	       y_avValue_fst__h723334 :
	       IF_rob_deqPort_0_canDeq__4995_THEN_IF_NOT_rob__ETC___d15194 ;
  assign fflags_csr__read__h616210 = { 59'd0, csrf_fflags_reg } ;
  assign frm_csr__read__h616221 = { 61'd0, csrf_frm_reg } ;
  assign guard__h350747 =
	     { IF_sfdin58842_BIT_33_THEN_2_ELSE_0__q22[1],
	       { sfdin__h358842[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h359456 =
	     { IF_theResult___snd67455_BIT_33_THEN_2_ELSE_0__q24[1],
	       { _theResult___snd__h367455[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h368386 =
	     { IF_sfdin76608_BIT_33_THEN_2_ELSE_0__q32[1],
	       { sfdin__h376608[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h368984 = x__h369086 != 57'd0 ;
  assign guard__h377222 =
	     { IF_theResult___snd85245_BIT_33_THEN_2_ELSE_0__q37[1],
	       { _theResult___snd__h385245[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h396446 =
	     { IF_sfdin04539_BIT_33_THEN_2_ELSE_0__q57[1],
	       { sfdin__h404539[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h405153 =
	     { IF_theResult___snd13152_BIT_33_THEN_2_ELSE_0__q59[1],
	       { _theResult___snd__h413152[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h414083 =
	     { IF_sfdin22305_BIT_33_THEN_2_ELSE_0__q67[1],
	       { sfdin__h422305[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h414681 = x__h414783 != 57'd0 ;
  assign guard__h422919 =
	     { IF_theResult___snd30942_BIT_33_THEN_2_ELSE_0__q72[1],
	       { _theResult___snd__h430942[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h442141 =
	     { IF_sfdin50234_BIT_33_THEN_2_ELSE_0__q92[1],
	       { sfdin__h450234[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h450848 =
	     { IF_theResult___snd58847_BIT_33_THEN_2_ELSE_0__q94[1],
	       { _theResult___snd__h458847[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h459778 =
	     { IF_sfdin68000_BIT_33_THEN_2_ELSE_0__q102[1],
	       { sfdin__h468000[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h460376 = x__h460478 != 57'd0 ;
  assign guard__h468614 =
	     { IF_theResult___snd76637_BIT_33_THEN_2_ELSE_0__q107[1],
	       { _theResult___snd__h476637[32:0], 23'd0 } != 56'd0 } ;
  assign guard__h498955 =
	     { IF_theResult___snd06867_BIT_4_THEN_2_ELSE_0__q127[1],
	       { _theResult___snd__h506867[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h508267 =
	     { IF_sfdin16487_BIT_4_THEN_2_ELSE_0__q131[1],
	       { sfdin__h516487[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h508865 = x__h508965 != 57'd0 ;
  assign guard__h517336 =
	     { IF_theResult___snd25272_BIT_4_THEN_2_ELSE_0__q134[1],
	       { _theResult___snd__h525272[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h537808 =
	     { IF_theResult___snd45720_BIT_4_THEN_2_ELSE_0__q167[1],
	       { _theResult___snd__h545720[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h547120 =
	     { IF_sfdin55340_BIT_4_THEN_2_ELSE_0__q171[1],
	       { sfdin__h555340[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h547718 = x__h547818 != 57'd0 ;
  assign guard__h556189 =
	     { IF_theResult___snd64125_BIT_4_THEN_2_ELSE_0__q174[1],
	       { _theResult___snd__h564125[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h577112 =
	     { IF_theResult___snd85024_BIT_4_THEN_2_ELSE_0__q144[1],
	       { _theResult___snd__h585024[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h586424 =
	     { IF_sfdin94644_BIT_4_THEN_2_ELSE_0__q148[1],
	       { sfdin__h594644[3:0], 52'd0 } != 56'd0 } ;
  assign guard__h587022 = x__h587122 != 57'd0 ;
  assign guard__h595493 =
	     { IF_theResult___snd03429_BIT_4_THEN_2_ELSE_0__q151[1],
	       { _theResult___snd__h603429[3:0], 52'd0 } != 56'd0 } ;
  assign idx__h690627 =
	     fetchStage$pipelines_0_canDeq &&
	     NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13852 ||
	     !coreFix_aluExe_0_rsAlu$canEnq ||
	     (!fetchStage$pipelines_0_canDeq ||
	      fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13872) &&
	     coreFix_aluExe_1_rsAlu$canEnq &&
	     !coreFix_aluExe_0_rsAlu_approximateCount__3562__ETC___d13564 ;
  assign imm__h661845 =
	     fetchStage$pipelines_0_first[160] ?
	       fetchStage$pipelines_0_first[159:128] :
	       32'd0 ;
  assign k__h675032 =
	     !coreFix_aluExe_0_rsAlu$canEnq ||
	     coreFix_aluExe_1_rsAlu$canEnq &&
	     !coreFix_aluExe_0_rsAlu_approximateCount__3562__ETC___d13564 ;
  assign mcause_csr__read__h617877 =
	     { r1__read__h620838, csrf_mcause_code_reg } ;
  assign mcounteren_csr__read__h617622 =
	     { r1__read__h620825, csrf_mcounteren_cy_reg } ;
  assign medeleg_csr__read__h617229 =
	     { r1__read__h620686, csrf_medeleg_9_0_reg } ;
  assign mideleg_csr__read__h617324 =
	     { r1__read__h620703, csrf_mideleg_1_0_reg } ;
  assign mie_csr__read__h617448 = { r1__read__h620727, 1'b0 } ;
  assign mip_csr__read__h618110 = { r1__read__h620844, 1'b0 } ;
  assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 =
	     mmio_cRqQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 ||
	     (!mmio_cRqQ_deqReq_dummy2_2$Q_OUT ||
	      !EN_mmioToPlatform_cRq_deq && !mmio_cRqQ_deqReq_rl) &&
	     mmio_cRqQ_full ;
  assign mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836 =
	     mmio_cRsQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 ||
	     (!mmio_cRsQ_deqReq_dummy2_2$Q_OUT ||
	      !EN_mmioToPlatform_cRs_deq && !mmio_cRsQ_deqReq_rl) &&
	     mmio_cRsQ_full ;
  assign mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312 =
	     mmio_dataPendQ_enqReq_dummy2_2$Q_OUT &&
	     (mmio_dataPendQ_enqReq_lat_0$whas || mmio_dataPendQ_enqReq_rl) ||
	     (!mmio_dataPendQ_deqReq_dummy2_2$Q_OUT ||
	      !mmio_dataRespQ_deqReq_lat_0$whas &&
	      !mmio_dataPendQ_deqReq_rl) &&
	     mmio_dataPendQ_full ;
  assign mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153 =
	     mmio_dataReqQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 ||
	     (!mmio_dataReqQ_deqReq_dummy2_2$Q_OUT ||
	      !CAN_FIRE_RL_mmio_sendDataReq && !mmio_dataReqQ_deqReq_rl) &&
	     mmio_dataReqQ_full ;
  assign mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254 =
	     mmio_dataRespQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 ||
	     (!mmio_dataRespQ_deqReq_dummy2_2$Q_OUT ||
	      !mmio_dataRespQ_deqReq_lat_0$whas &&
	      !mmio_dataRespQ_deqReq_rl) &&
	     mmio_dataRespQ_full ;
  assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13208 =
	     mmio_pRqQ_empty && epochManager$checkEpoch_0_check &&
	     (fetchStage$pipelines_0_first[68] ||
	      IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d13204) &&
	     rob$isEmpty ;
  assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13461 =
	     mmio_pRqQ_empty && epochManager$checkEpoch_0_check &&
	     !fetchStage$pipelines_0_first[68] &&
	     NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13442 &&
	     (fetchStage$pipelines_0_first[199:195] == 5'd0 ||
	      fetchStage$pipelines_0_first[199:195] == 5'd21 ||
	      fetchStage$pipelines_0_first[199:195] == 5'd17 ||
	      fetchStage$pipelines_0_first[199:195] == 5'd18 ||
	      fetchStage$pipelines_0_first[199:195] == 5'd13 ||
	      fetchStage$pipelines_0_first[199:195] == 5'd16 ||
	      fetchStage$pipelines_0_first[199:195] == 5'd15 ||
	      fetchStage$pipelines_0_first[199:195] == 5'd19 ||
	      fetchStage$pipelines_0_first[199:195] == 5'd20) ;
  assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14180 =
	     mmio_pRqQ_empty && epochManager$checkEpoch_0_check &&
	     !fetchStage$pipelines_0_first[68] &&
	     NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_295_ETC___d13543 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd0 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd21 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd17 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd18 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd13 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd16 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd15 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd19 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd20 ;
  assign mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747 =
	     mmio_pRqQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 ||
	     (!mmio_pRqQ_deqReq_dummy2_2$Q_OUT ||
	      !CAN_FIRE_RL_mmio_handlePRq && !mmio_pRqQ_deqReq_rl) &&
	     mmio_pRqQ_full ;
  assign mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606 =
	     mmio_pRsQ_enqReq_dummy2_2$Q_OUT &&
	     IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 ||
	     (!mmio_pRsQ_deqReq_dummy2_2$Q_OUT ||
	      !mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) &&
	     mmio_pRsQ_full ;
  assign mstatus_csr__read__h617081 = { r1__read__h620561, csrf_ie_vec_0 } ;
  assign mtvec_csr__read__h617530 =
	     { r1__read__h620820, csrf_mtvec_mode_low_reg } ;
  assign n___1__h201750 =
	     { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ?
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] :
		 x__h200347[63:56],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ?
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] :
		 x__h200347[55:48],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ?
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] :
		 x__h200347[47:40],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ?
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] :
		 x__h200347[39:32],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ?
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] :
		 x__h200347[31:24],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ?
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] :
		 x__h200347[23:16],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ?
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] :
		 x__h200347[15:8],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ?
		 coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] :
		 x__h200347[7:0] } ;
  assign n__read__h618214 =
	     (csrf_mcycle_ehr_data_dummy2_0$Q_OUT &&
	      csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ?
	       csrf_mcycle_ehr_data_rl :
	       64'd0 ;
  assign n__read__h618405 =
	     (csrf_minstret_ehr_data_dummy2_0$Q_OUT &&
	      csrf_minstret_ehr_data_dummy2_1$Q_OUT) ?
	       csrf_minstret_ehr_data_rl :
	       64'd0 ;
  assign n__read__h6331 =
	     csrf_mcycle_ehr_data_dummy2_1$Q_OUT ?
	       (csrf_mcycle_ehr_data_lat_0$whas ?
		  rob$deqPort_0_deq_data[95:32] :
		  csrf_mcycle_ehr_data_rl) :
	       64'd0 ;
  assign n__read__h720316 =
	     csrf_minstret_ehr_data_dummy2_1$Q_OUT ?
	       IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 :
	       64'd0 ;
  assign next_deqP___1__h301452 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ==
	      3'd7) ?
	       3'd0 :
	       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP +
	       3'd1 ;
  assign next_deqP___1__h309448 =
	     coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ;
  assign next_deqP___1__h315729 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ;
  assign next_deqP___1__h323583 =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ;
  assign next_deqP___1__h333640 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ;
  assign next_deqP___1__h336865 = coreFix_memExe_forwardQ_deqP + 1'd1 ;
  assign next_pc__h719526 =
	     (rob$deqPort_0_deq_data[97:96] == 2'd0) ?
	       rob$deqPort_0_deq_data[95:32] :
	       rob_deqPort_0_deq_data__4466_BITS_353_TO_290_4_ETC___d14968 ;
  assign out___1_sfd__h487592 = { f1_sfd__h487529, 29'd0 } ;
  assign out___1_sfd__h526586 = { f2_sfd__h526523, 29'd0 } ;
  assign out___1_sfd__h565890 = { f3_sfd__h565827, 29'd0 } ;
  assign out_exp__h359367 =
	     sfdin__h358842[34] ?
	       _theResult___exp__h359364 :
	       _theResult___fst_exp__h358848 ;
  assign out_exp__h367949 =
	     _theResult___snd__h367455[34] ?
	       _theResult___exp__h367946 :
	       _theResult___fst_exp__h367504 ;
  assign out_exp__h377133 =
	     sfdin__h376608[34] ?
	       _theResult___exp__h377130 :
	       _theResult___fst_exp__h376614 ;
  assign out_exp__h385769 =
	     _theResult___snd__h385245[34] ?
	       _theResult___exp__h385766 :
	       _theResult___fst_exp__h385299 ;
  assign out_exp__h405064 =
	     sfdin__h404539[34] ?
	       _theResult___exp__h405061 :
	       _theResult___fst_exp__h404545 ;
  assign out_exp__h413646 =
	     _theResult___snd__h413152[34] ?
	       _theResult___exp__h413643 :
	       _theResult___fst_exp__h413201 ;
  assign out_exp__h422830 =
	     sfdin__h422305[34] ?
	       _theResult___exp__h422827 :
	       _theResult___fst_exp__h422311 ;
  assign out_exp__h431466 =
	     _theResult___snd__h430942[34] ?
	       _theResult___exp__h431463 :
	       _theResult___fst_exp__h430996 ;
  assign out_exp__h450759 =
	     sfdin__h450234[34] ?
	       _theResult___exp__h450756 :
	       _theResult___fst_exp__h450240 ;
  assign out_exp__h459341 =
	     _theResult___snd__h458847[34] ?
	       _theResult___exp__h459338 :
	       _theResult___fst_exp__h458896 ;
  assign out_exp__h468525 =
	     sfdin__h468000[34] ?
	       _theResult___exp__h468522 :
	       _theResult___fst_exp__h468006 ;
  assign out_exp__h477161 =
	     _theResult___snd__h476637[34] ?
	       _theResult___exp__h477158 :
	       _theResult___fst_exp__h476691 ;
  assign out_exp__h507574 =
	     _theResult___snd__h506867[5] ?
	       _theResult___exp__h507571 :
	       _theResult___fst_exp__h506916 ;
  assign out_exp__h517225 =
	     sfdin__h516487[5] ?
	       _theResult___exp__h517222 :
	       _theResult___fst_exp__h516493 ;
  assign out_exp__h526009 =
	     _theResult___snd__h525272[5] ?
	       _theResult___exp__h526006 :
	       _theResult___fst_exp__h525326 ;
  assign out_exp__h546427 =
	     _theResult___snd__h545720[5] ?
	       _theResult___exp__h546424 :
	       _theResult___fst_exp__h545769 ;
  assign out_exp__h556078 =
	     sfdin__h555340[5] ?
	       _theResult___exp__h556075 :
	       _theResult___fst_exp__h555346 ;
  assign out_exp__h564862 =
	     _theResult___snd__h564125[5] ?
	       _theResult___exp__h564859 :
	       _theResult___fst_exp__h564179 ;
  assign out_exp__h585731 =
	     _theResult___snd__h585024[5] ?
	       _theResult___exp__h585728 :
	       _theResult___fst_exp__h585073 ;
  assign out_exp__h595382 =
	     sfdin__h594644[5] ?
	       _theResult___exp__h595379 :
	       _theResult___fst_exp__h594650 ;
  assign out_exp__h604166 =
	     _theResult___snd__h603429[5] ?
	       _theResult___exp__h604163 :
	       _theResult___fst_exp__h603483 ;
  assign out_f_exp__h386145 =
	     (_theResult___exp__h385868 == 8'd255 &&
	      _theResult___sfd__h385869 != 23'd0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
	      11'd2047) ?
	       8'd255 :
	       _theResult___fst_exp__h385859 ;
  assign out_f_exp__h431842 =
	     (_theResult___exp__h431565 == 8'd255 &&
	      _theResult___sfd__h431566 != 23'd0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
	      11'd2047) ?
	       8'd255 :
	       _theResult___fst_exp__h431556 ;
  assign out_f_exp__h477537 =
	     (_theResult___exp__h477260 == 8'd255 &&
	      _theResult___sfd__h477261 != 23'd0 ||
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
	      11'd2047) ?
	       8'd255 :
	       _theResult___fst_exp__h477251 ;
  assign out_f_sfd__h386146 =
	     (_theResult___exp__h385868 == 8'd255 &&
	      _theResult___sfd__h385869 != 23'd0) ?
	       23'd4194304 :
	       _theResult___sfd__h385869 ;
  assign out_f_sfd__h431843 =
	     (_theResult___exp__h431565 == 8'd255 &&
	      _theResult___sfd__h431566 != 23'd0) ?
	       23'd4194304 :
	       _theResult___sfd__h431566 ;
  assign out_f_sfd__h477538 =
	     (_theResult___exp__h477260 == 8'd255 &&
	      _theResult___sfd__h477261 != 23'd0) ?
	       23'd4194304 :
	       _theResult___sfd__h477261 ;
  assign out_sfd__h359368 =
	     sfdin__h358842[34] ?
	       _theResult___sfd__h359365 :
	       sfdin__h358842[56:34] ;
  assign out_sfd__h367950 =
	     _theResult___snd__h367455[34] ?
	       _theResult___sfd__h367947 :
	       _theResult___snd__h367455[56:34] ;
  assign out_sfd__h377134 =
	     sfdin__h376608[34] ?
	       _theResult___sfd__h377131 :
	       sfdin__h376608[56:34] ;
  assign out_sfd__h385770 =
	     _theResult___snd__h385245[34] ?
	       _theResult___sfd__h385767 :
	       _theResult___snd__h385245[56:34] ;
  assign out_sfd__h405065 =
	     sfdin__h404539[34] ?
	       _theResult___sfd__h405062 :
	       sfdin__h404539[56:34] ;
  assign out_sfd__h413647 =
	     _theResult___snd__h413152[34] ?
	       _theResult___sfd__h413644 :
	       _theResult___snd__h413152[56:34] ;
  assign out_sfd__h422831 =
	     sfdin__h422305[34] ?
	       _theResult___sfd__h422828 :
	       sfdin__h422305[56:34] ;
  assign out_sfd__h431467 =
	     _theResult___snd__h430942[34] ?
	       _theResult___sfd__h431464 :
	       _theResult___snd__h430942[56:34] ;
  assign out_sfd__h450760 =
	     sfdin__h450234[34] ?
	       _theResult___sfd__h450757 :
	       sfdin__h450234[56:34] ;
  assign out_sfd__h459342 =
	     _theResult___snd__h458847[34] ?
	       _theResult___sfd__h459339 :
	       _theResult___snd__h458847[56:34] ;
  assign out_sfd__h468526 =
	     sfdin__h468000[34] ?
	       _theResult___sfd__h468523 :
	       sfdin__h468000[56:34] ;
  assign out_sfd__h477162 =
	     _theResult___snd__h476637[34] ?
	       _theResult___sfd__h477159 :
	       _theResult___snd__h476637[56:34] ;
  assign out_sfd__h507575 =
	     _theResult___snd__h506867[5] ?
	       _theResult___sfd__h507572 :
	       _theResult___snd__h506867[56:5] ;
  assign out_sfd__h517226 =
	     sfdin__h516487[5] ?
	       _theResult___sfd__h517223 :
	       sfdin__h516487[56:5] ;
  assign out_sfd__h526010 =
	     _theResult___snd__h525272[5] ?
	       _theResult___sfd__h526007 :
	       _theResult___snd__h525272[56:5] ;
  assign out_sfd__h546428 =
	     _theResult___snd__h545720[5] ?
	       _theResult___sfd__h546425 :
	       _theResult___snd__h545720[56:5] ;
  assign out_sfd__h556079 =
	     sfdin__h555340[5] ?
	       _theResult___sfd__h556076 :
	       sfdin__h555340[56:5] ;
  assign out_sfd__h564863 =
	     _theResult___snd__h564125[5] ?
	       _theResult___sfd__h564860 :
	       _theResult___snd__h564125[56:5] ;
  assign out_sfd__h585732 =
	     _theResult___snd__h585024[5] ?
	       _theResult___sfd__h585729 :
	       _theResult___snd__h585024[56:5] ;
  assign out_sfd__h595383 =
	     sfdin__h594644[5] ?
	       _theResult___sfd__h595380 :
	       sfdin__h594644[56:5] ;
  assign out_sfd__h604167 =
	     _theResult___snd__h603429[5] ?
	       _theResult___sfd__h604164 :
	       _theResult___snd__h603429[56:5] ;
  assign pend_ints__h658032 =
	     { csrf_external_int_en_vec_3_read__1844_AND_csrf_ETC___d12967,
	       csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3,
	       1'd0,
	       csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1,
	       1'd0 } ;
  assign prv__h724902 = csrf_prv_reg ;
  assign prv__h724946 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ;
  assign q___1__h480782 =
	     64'd0 -
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140] ;
  assign r1__read_BITS_13_TO_12___h661713 = csrf_fs_reg ;
  assign r1__read_BITS_9_TO_0___h658469 =
	     { csrf_mideleg_11_reg,
	       1'b0,
	       csrf_mideleg_9_7_reg,
	       1'b0,
	       csrf_mideleg_5_3_reg,
	       1'b0 } ;
  assign r1__read_BIT_20___h662377 = csrf_tw_reg ;
  assign r1__read__h619390 = { r1__read__h619392, csrf_ie_vec_1 } ;
  assign r1__read__h619392 = { r1__read__h619394, 2'b0 } ;
  assign r1__read__h619394 = { r1__read__h619396, csrf_prev_ie_vec_0 } ;
  assign r1__read__h619396 = { r1__read__h619398, csrf_prev_ie_vec_1 } ;
  assign r1__read__h619398 = { r1__read__h619400, 2'b0 } ;
  assign r1__read__h619400 = { r1__read__h619402, csrf_spp_reg } ;
  assign r1__read__h619402 = { r1__read__h619404, 4'b0 } ;
  assign r1__read__h619404 = { r1__read__h619406, csrf_fs_reg } ;
  assign r1__read__h619406 = { r1__read__h619408, 2'd0 } ;
  assign r1__read__h619408 = { r1__read__h619410, 1'b0 } ;
  assign r1__read__h619410 = { r1__read__h619412, csrf_sum_reg } ;
  assign r1__read__h619412 = { r1__read__h619414, csrf_mxr_reg } ;
  assign r1__read__h619414 = { r1__read__h619416, 12'b0 } ;
  assign r1__read__h619416 = { r1__read__h619418, 2'b10 } ;
  assign r1__read__h619418 = { r__h619422, 29'b0 } ;
  assign r1__read__h619794 =
	     { r1__read__h619796, csrf_software_int_en_vec_1 } ;
  assign r1__read__h619796 = { r1__read__h619798, 2'b0 } ;
  assign r1__read__h619798 = { r1__read__h619800, 1'b0 } ;
  assign r1__read__h619800 = { r1__read__h619802, csrf_timer_int_en_vec_1 } ;
  assign r1__read__h619802 = { r1__read__h619804, 2'b0 } ;
  assign r1__read__h619804 = { r1__read__h619806, 1'b0 } ;
  assign r1__read__h619806 = { 54'b0, csrf_external_int_en_vec_1 } ;
  assign r1__read__h620304 = { csrf_stvec_base_hi_reg, 1'b0 } ;
  assign r1__read__h620309 = { r1__read__h620311, csrf_scounteren_tm_reg } ;
  assign r1__read__h620311 = { 61'd0, csrf_scounteren_ir_reg } ;
  assign r1__read__h620322 = { csrf_scause_interrupt_reg, 59'b0 } ;
  assign r1__read__h620328 =
	     { r1__read__h620330, csrf_software_int_pend_vec_1 } ;
  assign r1__read__h620330 = { r1__read__h620332, 2'b0 } ;
  assign r1__read__h620332 = { r1__read__h620334, 1'b0 } ;
  assign r1__read__h620334 =
	     { r1__read__h620336, csrf_timer_int_pend_vec_1 } ;
  assign r1__read__h620336 = { r1__read__h620338, 2'b0 } ;
  assign r1__read__h620338 = { r1__read__h620340, 1'b0 } ;
  assign r1__read__h620340 = { 54'b0, csrf_external_int_pend_vec_1 } ;
  assign r1__read__h620538 = { vm_mode_reg__read__h620544, 16'd0 } ;
  assign r1__read__h620561 = { r1__read__h620563, csrf_ie_vec_1 } ;
  assign r1__read__h620563 = { r1__read__h620565, 1'b0 } ;
  assign r1__read__h620565 = { r1__read__h620567, csrf_ie_vec_3 } ;
  assign r1__read__h620567 = { r1__read__h620569, csrf_prev_ie_vec_0 } ;
  assign r1__read__h620569 = { r1__read__h620571, csrf_prev_ie_vec_1 } ;
  assign r1__read__h620571 = { r1__read__h620573, 1'b0 } ;
  assign r1__read__h620573 = { r1__read__h620575, csrf_prev_ie_vec_3 } ;
  assign r1__read__h620575 = { r1__read__h620577, csrf_spp_reg } ;
  assign r1__read__h620577 = { r1__read__h620579, 2'b0 } ;
  assign r1__read__h620579 = { r1__read__h620581, csrf_mpp_reg } ;
  assign r1__read__h620581 = { r1__read__h620583, csrf_fs_reg } ;
  assign r1__read__h620583 = { r1__read__h620585, 2'd0 } ;
  assign r1__read__h620585 = { r1__read__h620587, csrf_mprv_reg } ;
  assign r1__read__h620587 = { r1__read__h620589, csrf_sum_reg } ;
  assign r1__read__h620589 = { r1__read__h620591, csrf_mxr_reg } ;
  assign r1__read__h620591 = { r1__read__h620593, csrf_tvm_reg } ;
  assign r1__read__h620593 = { r1__read__h620595, csrf_tw_reg } ;
  assign r1__read__h620595 = { r1__read__h620597, csrf_tsr_reg } ;
  assign r1__read__h620597 = { r1__read__h620599, 9'b0 } ;
  assign r1__read__h620599 = { r1__read__h620601, 2'b10 } ;
  assign r1__read__h620601 = { r1__read__h620603, 2'b10 } ;
  assign r1__read__h620603 = { r__h619422, 27'b0 } ;
  assign r1__read__h620686 = { r1__read__h620688, 1'b0 } ;
  assign r1__read__h620688 = { r1__read__h620690, csrf_medeleg_13_11_reg } ;
  assign r1__read__h620690 = { r1__read__h620692, 1'b0 } ;
  assign r1__read__h620692 = { 48'b0, csrf_medeleg_15_reg } ;
  assign r1__read__h620703 = { r1__read__h620705, 1'b0 } ;
  assign r1__read__h620705 = { r1__read__h620707, csrf_mideleg_5_3_reg } ;
  assign r1__read__h620707 = { r1__read__h620709, 1'b0 } ;
  assign r1__read__h620709 = { r1__read__h620711, csrf_mideleg_9_7_reg } ;
  assign r1__read__h620711 = { r1__read__h620713, 1'b0 } ;
  assign r1__read__h620713 = { 52'b0, csrf_mideleg_11_reg } ;
  assign r1__read__h620727 =
	     { r1__read__h620729, csrf_software_int_en_vec_1 } ;
  assign r1__read__h620729 = { r1__read__h620731, 1'b0 } ;
  assign r1__read__h620731 =
	     { r1__read__h620733, csrf_software_int_en_vec_3 } ;
  assign r1__read__h620733 = { r1__read__h620735, 1'b0 } ;
  assign r1__read__h620735 = { r1__read__h620737, csrf_timer_int_en_vec_1 } ;
  assign r1__read__h620737 = { r1__read__h620739, 1'b0 } ;
  assign r1__read__h620739 = { r1__read__h620741, csrf_timer_int_en_vec_3 } ;
  assign r1__read__h620741 = { r1__read__h620743, 1'b0 } ;
  assign r1__read__h620743 =
	     { r1__read__h620745, csrf_external_int_en_vec_1 } ;
  assign r1__read__h620745 = { r1__read__h620747, 1'b0 } ;
  assign r1__read__h620747 = { 52'b0, csrf_external_int_en_vec_3 } ;
  assign r1__read__h620820 = { csrf_mtvec_base_hi_reg, 1'b0 } ;
  assign r1__read__h620825 = { r1__read__h620827, csrf_mcounteren_tm_reg } ;
  assign r1__read__h620827 = { 61'd0, csrf_mcounteren_ir_reg } ;
  assign r1__read__h620838 = { csrf_mcause_interrupt_reg, 59'b0 } ;
  assign r1__read__h620844 =
	     { r1__read__h620846, csrf_software_int_pend_vec_1 } ;
  assign r1__read__h620846 = { r1__read__h620848, 1'b0 } ;
  assign r1__read__h620848 =
	     { r1__read__h620850, csrf_software_int_pend_vec_3 } ;
  assign r1__read__h620850 = { r1__read__h620852, 1'b0 } ;
  assign r1__read__h620852 =
	     { r1__read__h620854, csrf_timer_int_pend_vec_1 } ;
  assign r1__read__h620854 = { r1__read__h620856, 1'b0 } ;
  assign r1__read__h620856 =
	     { r1__read__h620858, csrf_timer_int_pend_vec_3 } ;
  assign r1__read__h620858 = { r1__read__h620860, 1'b0 } ;
  assign r1__read__h620860 =
	     { r1__read__h620862, csrf_external_int_pend_vec_1 } ;
  assign r1__read__h620862 = { r1__read__h620864, 1'b0 } ;
  assign r1__read__h620864 = { 52'b0, csrf_external_int_pend_vec_3 } ;
  assign r1__read__h620945 = { 4'd0, csrf_rg_tdata1_dmode } ;
  assign rVal1__h487144 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ;
  assign rVal2__h487145 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ;
  assign r___1__h480809 =
	     64'd0 -
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76] ;
  assign r__h619422 = csrf_fs_reg == 2'b11 ;
  assign r__h620919 = csrf_software_int_pend_vec_3 ;
  assign regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14037 =
	     regRenamingTable$RDY_rename_0_getRename &&
	     CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 &&
	     (fetchStage$pipelines_0_first[199:195] == 5'd14 ||
	      coreFix_memExe_rsMem$RDY_enq) ;
  assign regRenamingTable_RDY_rename_1_getRename__4093__ETC___d14111 =
	     regRenamingTable$RDY_rename_1_getRename &&
	     (!fetchStage$pipelines_0_canDeq ||
	      NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14096) &&
	     _0_OR_NOT_fetchStage_pipelines_1_first__2937_BI_ETC___d14109 ;
  assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598 =
	     regRenamingTable$rename_0_canRename &&
	     fetchStage$pipelines_0_first[199:195] != 5'd0 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd21 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd17 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd18 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd13 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd16 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd15 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd19 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd20 &&
	     NOT_fetchStage_pipelines_0_first__2928_BIT_68__ETC___d13596 ;
  assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d13612 =
	     regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598 &&
	     IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 &&
	     fetchStage$pipelines_0_first[194:192] == 3'd1 ||
	     !specTagManager$canClaim ;
  assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d13927 =
	     regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598 &&
	     fetchStage$pipelines_0_first[194:192] == 3'd2 &&
	     IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 ||
	     !coreFix_memExe_rsMem$canEnq ||
	     CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 ;
  assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d14066 =
	     regRenamingTable$rename_0_canRename &&
	     !checkForException___d13160[4] &&
	     rob$enqPort_0_canEnq &&
	     IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14064 &&
	     fetchStage$pipelines_0_first[194:192] == 3'd1 ;
  assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d14198 =
	     regRenamingTable$rename_0_canRename &&
	     !checkForException___d13160[4] &&
	     rob$enqPort_0_canEnq &&
	     (fetchStage$pipelines_0_first[194:192] == 3'd3 ||
	      fetchStage$pipelines_0_first[194:192] == 3'd4) &&
	     coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ;
  assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d14211 =
	     regRenamingTable$rename_0_canRename &&
	     !checkForException___d13160[4] &&
	     rob$enqPort_0_canEnq &&
	     (fetchStage$pipelines_0_first[194:192] == 3'd3 ||
	      fetchStage$pipelines_0_first[194:192] == 3'd4) &&
	     coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq &&
	     NOT_fetchStage_pipelines_0_first__2928_BITS_32_ETC___d14207 ;
  assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d14216 =
	     regRenamingTable$rename_0_canRename &&
	     !checkForException___d13160[4] &&
	     rob$enqPort_0_canEnq &&
	     (fetchStage$pipelines_0_first[194:192] == 3'd3 ||
	      fetchStage$pipelines_0_first[194:192] == 3'd4) &&
	     coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq &&
	     fetchStage$pipelines_0_first[173] ;
  assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d14221 =
	     regRenamingTable$rename_0_canRename &&
	     !checkForException___d13160[4] &&
	     rob$enqPort_0_canEnq &&
	     fetchStage$pipelines_0_first[194:192] == 3'd2 &&
	     coreFix_memExe_rsMem$canEnq &&
	     IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 &&
	     fetchStage$pipelines_0_first[199:195] != 5'd14 ;
  assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d14241 =
	     regRenamingTable$rename_0_canRename &&
	     !checkForException___d13160[4] &&
	     rob$enqPort_0_canEnq &&
	     fetchStage$pipelines_0_first[194:192] == 3'd2 &&
	     coreFix_memExe_rsMem$canEnq &&
	     IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 &&
	     NOT_fetchStage_pipelines_0_first__2928_BITS_32_ETC___d14207 ;
  assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d14245 =
	     regRenamingTable$rename_0_canRename &&
	     !checkForException___d13160[4] &&
	     rob$enqPort_0_canEnq &&
	     fetchStage$pipelines_0_first[194:192] == 3'd2 &&
	     coreFix_memExe_rsMem$canEnq &&
	     IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 &&
	     fetchStage$pipelines_0_first[173] ;
  assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d14251 =
	     regRenamingTable$rename_0_canRename &&
	     !checkForException___d13160[4] &&
	     rob$enqPort_0_canEnq &&
	     fetchStage$pipelines_0_first[194:192] == 3'd2 &&
	     coreFix_memExe_rsMem$canEnq &&
	     IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 &&
	     (fetchStage$pipelines_0_first[199:195] != 5'd14) !=
	     fetchStage$pipelines_0_first[160] ;
  assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d14255 =
	     regRenamingTable$rename_0_canRename &&
	     !checkForException___d13160[4] &&
	     rob$enqPort_0_canEnq &&
	     fetchStage$pipelines_0_first[194:192] == 3'd2 &&
	     coreFix_memExe_rsMem$canEnq &&
	     IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 &&
	     (fetchStage$pipelines_0_first[191:189] == 3'd0 ||
	      fetchStage$pipelines_0_first[191:189] == 3'd2) ;
  assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d14263 =
	     regRenamingTable$rename_0_canRename &&
	     !checkForException___d13160[4] &&
	     rob$enqPort_0_canEnq &&
	     fetchStage$pipelines_0_first[194:192] == 3'd2 &&
	     coreFix_memExe_rsMem$canEnq &&
	     IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 &&
	     fetchStage$pipelines_0_first[191:189] != 3'd0 &&
	     fetchStage$pipelines_0_first[191:189] != 3'd2 ;
  assign regRenamingTable_rename_0_canRename__3528_AND__ETC___d14439 =
	     regRenamingTable$rename_0_canRename &&
	     !checkForException___d13160[4] &&
	     rob$enqPort_0_canEnq &&
	     fetchStage$pipelines_0_first[194:192] == 3'd2 &&
	     IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 ;
  assign regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 =
	     regRenamingTable$rename_1_canRename &&
	     fetchStage$pipelines_1_first[199:195] != 5'd0 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd21 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd17 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd18 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd13 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd16 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd15 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd19 &&
	     fetchStage$pipelines_1_first[199:195] != 5'd20 &&
	     NOT_fetchStage_pipelines_1_first__2937_BIT_68__ETC___d14316 ;
  assign regRenamingTable_rename_1_canRename__3647_AND__ETC___d14402 =
	     regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 &&
	     fetchStage$pipelines_1_first[194:192] == 3'd2 &&
	     NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14386 &&
	     NOT_fetchStage_pipelines_1_first__2937_BITS_32_ETC___d14373 ;
  assign regRenamingTable_rename_1_canRename__3647_AND__ETC___d14412 =
	     regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 &&
	     fetchStage$pipelines_1_first[194:192] == 3'd2 &&
	     NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14386 &&
	     (fetchStage$pipelines_1_first[199:195] != 5'd14) !=
	     fetchStage$pipelines_1_first[160] ;
  assign renaming_spec_bits__h690496 =
	     fetchStage$pipelines_0_canDeq ?
	       y_avValue_snd_fst__h687194 :
	       specTagManager$currentSpecBits ;
  assign res_data__h342521 = { 32'hFFFFFFFF, x__h342536 } ;
  assign res_data__h342526 =
	     { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
		52'd0) &&
	       coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[33] ^
	       coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68],
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
		11'd2047 &&
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		52'd0) ?
		 63'h7FF8000000000000 :
		 coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ;
  assign res_data__h388223 = { 32'hFFFFFFFF, x__h388238 } ;
  assign res_data__h388228 =
	     { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
		52'd0) &&
	       coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[33] ^
	       coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68],
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
		11'd2047 &&
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		52'd0) ?
		 63'h7FF8000000000000 :
		 coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ;
  assign res_data__h433918 = { 32'hFFFFFFFF, x__h433933 } ;
  assign res_data__h433923 =
	     { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
		52'd0) &&
	       coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[33] ^
	       coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68],
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
		11'd2047 &&
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		52'd0) ?
		 63'h7FF8000000000000 :
		 coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ;
  assign res_fflags__h342522 =
	     coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] |
	     coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] |
	     { (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5298,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5309,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5325,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5338,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5351 } ;
  assign res_fflags__h388224 =
	     coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] |
	     coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] |
	     { (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6690,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6701,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6717,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6730,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6743 } ;
  assign res_fflags__h433919 =
	     coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] |
	     coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] |
	     { (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8082,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8093,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8109,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8122,
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd2047 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		52'd0) &&
	       (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
		11'd0 ||
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
		52'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8135 } ;
  assign resp_addr__h296629 =
	     { coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ;
  assign result__h368989 =
	     { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4654[56:1],
	       _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4654[0] |
	       guard__h368984 } ;
  assign result__h414686 =
	     { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6046[56:1],
	       _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d6046[0] |
	       guard__h414681 } ;
  assign result__h460381 =
	     { _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7438[56:1],
	       _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7438[0] |
	       guard__h460376 } ;
  assign result__h508870 =
	     { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8764[56:1],
	       _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8764[0] |
	       guard__h508865 } ;
  assign result__h547723 =
	     { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10249[56:1],
	       _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10249[0] |
	       guard__h547718 } ;
  assign result__h587027 =
	     { _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9479[56:1],
	       _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9479[0] |
	       guard__h587022 } ;
  assign result__h653741 = w__h653736 & y__h653770 ;
  assign result__h653792 = ~x__h653791 ;
  assign rg_tdata1__read__h619065 =
	     { r1__read__h620945, csrf_rg_tdata1_data } ;
  assign rob_RDY_enqPort_1_enq__4157_AND_NOT_fetchStage_ETC___d14165 =
	     rob$RDY_enqPort_1_enq &&
	     (!fetchStage$pipelines_0_canDeq ||
	      NOT_specTagManager_canClaim__3526_3611_OR_NOT__ETC___d14161) &&
	     (fetchStage$pipelines_1_first[194:192] != 3'd1 ||
	      specTagManager$RDY_claimSpecTag) ;
  assign rob_deqPort_0_deq_data__4466_BITS_353_TO_290_4_ETC___d14968 =
	     rob$deqPort_0_deq_data[353:290] + 64'd4 ;
  assign rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13841 =
	     rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check &&
	     (!fetchStage$pipelines_0_canDeq ||
	      (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	       specTagManager$canClaim) &&
	      regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598 &&
	      IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13584) ;
  assign rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13975 =
	     rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check &&
	     (!fetchStage$pipelines_0_canDeq ||
	      (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	       specTagManager$canClaim) &&
	      regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598 &&
	      IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13971) ;
  assign rob_enqPort_1_canEnq__3836_AND_epochManager_ch_ETC___d13992 =
	     rob$enqPort_1_canEnq && epochManager$checkEpoch_1_check &&
	     (!fetchStage$pipelines_0_canDeq ||
	      (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	       specTagManager$canClaim) &&
	      regRenamingTable_rename_0_canRename__3528_AND__ETC___d13598 &&
	      IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13988) ;
  assign robdeqPort_0_deq_data_BITS_95_TO_32__q262 =
	     rob$deqPort_0_deq_data[95:32] ;
  assign rs1__h661844 =
	     (fetchStage$pipelines_0_first[88] &&
	      !fetchStage$pipelines_0_first[87]) ?
	       fetchStage$pipelines_0_first[86:82] :
	       5'd0 ;
  assign satp_csr__read__h616938 = { r1__read__h620538, csrf_ppn_reg } ;
  assign sbIdx__h158518 =
	     coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ?
	       (CAN_FIRE_RL_coreFix_memExe_doIssueSB ?
		  coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] :
		  coreFix_memExe_reqStQ_data_0_rl[65:64]) :
	       2'd0 ;
  assign scause_csr__read__h616735 =
	     { r1__read__h620322, csrf_scause_code_reg } ;
  assign scounteren_csr__read__h616597 =
	     { r1__read__h620309, csrf_scounteren_cy_reg } ;
  assign sfd__h343132 = { value__h351359, 3'd0 } ;
  assign sfd__h358940 =
	     { 1'b0,
	       _theResult___fst_exp__h358848 != 8'd0,
	       sfdin__h358842[56:34] } +
	     25'd1 ;
  assign sfd__h367522 =
	     { 1'b0,
	       _theResult___fst_exp__h367504 != 8'd0,
	       _theResult___snd__h367455[56:34] } +
	     25'd1 ;
  assign sfd__h376706 =
	     { 1'b0,
	       _theResult___fst_exp__h376614 != 8'd0,
	       sfdin__h376608[56:34] } +
	     25'd1 ;
  assign sfd__h385318 =
	     { 1'b0,
	       _theResult___fst_exp__h385299 != 8'd0,
	       _theResult___snd__h385245[56:34] } +
	     25'd1 ;
  assign sfd__h388834 = { value__h397056, 3'd0 } ;
  assign sfd__h404637 =
	     { 1'b0,
	       _theResult___fst_exp__h404545 != 8'd0,
	       sfdin__h404539[56:34] } +
	     25'd1 ;
  assign sfd__h413219 =
	     { 1'b0,
	       _theResult___fst_exp__h413201 != 8'd0,
	       _theResult___snd__h413152[56:34] } +
	     25'd1 ;
  assign sfd__h422403 =
	     { 1'b0,
	       _theResult___fst_exp__h422311 != 8'd0,
	       sfdin__h422305[56:34] } +
	     25'd1 ;
  assign sfd__h431015 =
	     { 1'b0,
	       _theResult___fst_exp__h430996 != 8'd0,
	       _theResult___snd__h430942[56:34] } +
	     25'd1 ;
  assign sfd__h434529 = { value__h442751, 3'd0 } ;
  assign sfd__h450332 =
	     { 1'b0,
	       _theResult___fst_exp__h450240 != 8'd0,
	       sfdin__h450234[56:34] } +
	     25'd1 ;
  assign sfd__h458914 =
	     { 1'b0,
	       _theResult___fst_exp__h458896 != 8'd0,
	       _theResult___snd__h458847[56:34] } +
	     25'd1 ;
  assign sfd__h468098 =
	     { 1'b0,
	       _theResult___fst_exp__h468006 != 8'd0,
	       sfdin__h468000[56:34] } +
	     25'd1 ;
  assign sfd__h476710 =
	     { 1'b0,
	       _theResult___fst_exp__h476691 != 8'd0,
	       _theResult___snd__h476637[56:34] } +
	     25'd1 ;
  assign sfd__h487890 = { value__h492473, 32'd0 } ;
  assign sfd__h506934 =
	     { 1'b0,
	       _theResult___fst_exp__h506916 != 11'd0,
	       _theResult___snd__h506867[56:5] } +
	     54'd1 ;
  assign sfd__h516585 =
	     { 1'b0,
	       _theResult___fst_exp__h516493 != 11'd0,
	       sfdin__h516487[56:5] } +
	     54'd1 ;
  assign sfd__h525345 =
	     { 1'b0,
	       _theResult___fst_exp__h525326 != 11'd0,
	       _theResult___snd__h525272[56:5] } +
	     54'd1 ;
  assign sfd__h526884 = { value__h531326, 32'd0 } ;
  assign sfd__h545787 =
	     { 1'b0,
	       _theResult___fst_exp__h545769 != 11'd0,
	       _theResult___snd__h545720[56:5] } +
	     54'd1 ;
  assign sfd__h555438 =
	     { 1'b0,
	       _theResult___fst_exp__h555346 != 11'd0,
	       sfdin__h555340[56:5] } +
	     54'd1 ;
  assign sfd__h564198 =
	     { 1'b0,
	       _theResult___fst_exp__h564179 != 11'd0,
	       _theResult___snd__h564125[56:5] } +
	     54'd1 ;
  assign sfd__h566188 = { value__h570630, 32'd0 } ;
  assign sfd__h585091 =
	     { 1'b0,
	       _theResult___fst_exp__h585073 != 11'd0,
	       _theResult___snd__h585024[56:5] } +
	     54'd1 ;
  assign sfd__h594742 =
	     { 1'b0,
	       _theResult___fst_exp__h594650 != 11'd0,
	       sfdin__h594644[56:5] } +
	     54'd1 ;
  assign sfd__h603502 =
	     { 1'b0,
	       _theResult___fst_exp__h603483 != 11'd0,
	       _theResult___snd__h603429[56:5] } +
	     54'd1 ;
  assign sfdin__h358842 =
	     _theResult____h350737[56] ?
	       _theResult___snd__h358859 :
	       _theResult___snd__h358870 ;
  assign sfdin__h376608 =
	     _theResult____h368376[56] ?
	       _theResult___snd__h376625 :
	       _theResult___snd__h376636 ;
  assign sfdin__h404539 =
	     _theResult____h396436[56] ?
	       _theResult___snd__h404556 :
	       _theResult___snd__h404567 ;
  assign sfdin__h422305 =
	     _theResult____h414073[56] ?
	       _theResult___snd__h422322 :
	       _theResult___snd__h422333 ;
  assign sfdin__h450234 =
	     _theResult____h442131[56] ?
	       _theResult___snd__h450251 :
	       _theResult___snd__h450262 ;
  assign sfdin__h468000 =
	     _theResult____h459768[56] ?
	       _theResult___snd__h468017 :
	       _theResult___snd__h468028 ;
  assign sfdin__h516487 =
	     _theResult____h508257[56] ?
	       _theResult___snd__h516504 :
	       _theResult___snd__h516515 ;
  assign sfdin__h555340 =
	     _theResult____h547110[56] ?
	       _theResult___snd__h555357 :
	       _theResult___snd__h555368 ;
  assign sfdin__h594644 =
	     _theResult____h586414[56] ?
	       _theResult___snd__h594661 :
	       _theResult___snd__h594672 ;
  assign shiftData__h184743 =
	     coreFix_memExe_regToExeQ$first[75:12] << x__h184872 ;
  assign sie_csr__read__h616501 = { r1__read__h619794, 1'b0 } ;
  assign sip_csr__read__h616875 = { r1__read__h620328, 1'b0 } ;
  assign spec_bits__h693623 = specTagManager$currentSpecBits | y__h693636 ;
  assign sstatus_csr__read__h616431 = { r1__read__h619390, csrf_ie_vec_0 } ;
  assign stvec_csr__read__h616544 =
	     { r1__read__h620304, csrf_stvec_mode_low_reg } ;
  assign upd__h3681 =
	     WILL_FIRE_RL_commitStage_doCommitSystemInst ?
	       MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 :
	       MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 ;
  assign upd__h4998 = n__read__h6331 + 64'd1 ;
  assign v__h300593 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3127) ?
	       v__h300824 :
	       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ;
  assign v__h300824 =
	     (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
	      3'd7) ?
	       3'd0 :
	       coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP +
	       3'd1 ;
  assign v__h303938 =
	     (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3234) ?
	       v__h304456 :
	       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ;
  assign v__h304456 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ;
  assign v__h314452 =
	     (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3405) ?
	       v__h314683 :
	       coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ;
  assign v__h314683 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ;
  assign v__h318328 =
	     (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3501) ?
	       v__h318559 :
	       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ;
  assign v__h318559 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ;
  assign v__h332929 =
	     (coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3730) ?
	       v__h333160 :
	       coreFix_memExe_memRespLdQ_enqP ;
  assign v__h333160 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ;
  assign v__h336154 =
	     (coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
	      IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3824) ?
	       v__h336385 :
	       coreFix_memExe_forwardQ_enqP ;
  assign v__h336385 = coreFix_memExe_forwardQ_enqP + 1'd1 ;
  assign v__h609621 =
	     coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ?
	       v__h609631 :
	       coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ;
  assign v__h609631 =
	     coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ;
  assign v__h610689 = v__h609621 - 2'd1 ;
  assign v__h614705 =
	     sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h615876 ;
  assign v__h639708 =
	     sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h640727 ;
  assign vaddr__h184738 =
	     coreFix_memExe_regToExeQ$first[139:76] +
	     { {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q5[31]}},
	       coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q5 } ;
  assign value__h351359 =
	     { 1'b0,
	       coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
	       11'd0,
	       coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ;
  assign value__h397056 =
	     { 1'b0,
	       coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
	       11'd0,
	       coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ;
  assign value__h442751 =
	     { 1'b0,
	       coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
	       11'd0,
	       coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ;
  assign value__h492473 = { 1'b0, f1_exp__h487528 != 8'd0, f1_sfd__h487529 } ;
  assign value__h531326 = { 1'b0, f2_exp__h526522 != 8'd0, f2_sfd__h526523 } ;
  assign value__h570630 = { 1'b0, f3_exp__h565826 != 8'd0, f3_sfd__h565827 } ;
  assign vm_mode_reg__read__h620544 = { csrf_vm_mode_sv39_reg, 3'b0 } ;
  assign w__h653736 =
	     coreFix_globalSpecUpdate_correctSpecTag_0$whas ?
	       result__h653792 :
	       12'd4095 ;
  assign x__h155092 =
	     coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_reqLdQ_data_0_lat_0$whas ?
		  coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] :
		  coreFix_memExe_reqLdQ_data_0_rl[68:64]) :
	       5'd0 ;
  assign x__h155098 =
	     coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_reqLdQ_data_0_lat_0$whas ?
		  coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] :
		  coreFix_memExe_reqLdQ_data_0_rl[63:0]) :
	       64'd0 ;
  assign x__h158639 = { 3'd0, sbIdx__h158518 } ;
  assign x__h158645 =
	     coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ?
	       (CAN_FIRE_RL_coreFix_memExe_doIssueSB ?
		  coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] :
		  coreFix_memExe_reqStQ_data_0_rl[63:0]) :
	       64'd0 ;
  assign x__h161455 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		  coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[152:148] :
		  coreFix_memExe_reqLrScAmoQ_data_0_rl[152:148]) :
	       5'd0 ;
  assign x__h161459 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		  coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[147:84] :
		  coreFix_memExe_reqLrScAmoQ_data_0_rl[147:84]) :
	       64'd0 ;
  assign x__h163307 =
	     coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
		  coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[70:7] :
		  coreFix_memExe_reqLrScAmoQ_data_0_rl[70:7]) :
	       64'd0 ;
  assign x__h17933 =
	     mmio_dataReqQ_enqReq_lat_0$whas ?
	       mmio_dataReqQ_enqReq_lat_0$wget[141:78] :
	       mmio_dataReqQ_enqReq_rl[141:78] ;
  assign x__h184650 =
	     sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h183778 ;
  assign x__h184651 =
	     sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h184497 ;
  assign x__h184872 = { vaddr__h184738[2:0], 3'b0 } ;
  assign x__h196067 =
	     coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ?
	       curData__h195304[63:32] :
	       curData__h195304[31:0] ;
  assign x__h20471 =
	     mmio_dataReqQ_enqReq_lat_0$whas ?
	       mmio_dataReqQ_enqReq_lat_0$wget[63:0] :
	       mmio_dataReqQ_enqReq_rl[63:0] ;
  assign x__h291826 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] :
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) :
	       5'd0 ;
  assign x__h291838 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] :
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) :
	       64'd0 ;
  assign x__h293692 =
	     coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
	       (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] :
		  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) :
	       64'd0 ;
  assign x__h306803 =
	     EN_dCacheToParent_fromP_enq ?
	       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] :
	       coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ;
  assign x__h342536 =
	     { (_theResult___exp__h385868 != 8'd255 ||
		_theResult___sfd__h385869 == 23'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5236,
	       out_f_exp__h386145,
	       out_f_sfd__h386146 } ;
  assign x__h369086 =
	     sfd__h343132 << (x__h369119[11] ? 12'hAAA : x__h369119) ;
  assign x__h369119 =
	     12'd57 -
	     _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4650 ;
  assign x__h388238 =
	     { (_theResult___exp__h431565 != 8'd255 ||
		_theResult___sfd__h431566 == 23'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6628,
	       out_f_exp__h431842,
	       out_f_sfd__h431843 } ;
  assign x__h414783 =
	     sfd__h388834 << (x__h414816[11] ? 12'hAAA : x__h414816) ;
  assign x__h414816 =
	     12'd57 -
	     _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d6042 ;
  assign x__h433933 =
	     { (_theResult___exp__h477260 != 8'd255 ||
		_theResult___sfd__h477261 == 23'd0) &&
	       IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8020,
	       out_f_exp__h477537,
	       out_f_sfd__h477538 } ;
  assign x__h45840 =
	     mmio_cRqQ_enqReq_lat_0$whas ?
	       mmio_cRqQ_enqReq_lat_0$wget[141:78] :
	       mmio_cRqQ_enqReq_rl[141:78] ;
  assign x__h460478 =
	     sfd__h434529 << (x__h460511[11] ? 12'hAAA : x__h460511) ;
  assign x__h460511 =
	     12'd57 -
	     _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7434 ;
  assign x__h48376 =
	     mmio_cRqQ_enqReq_lat_0$whas ?
	       mmio_cRqQ_enqReq_lat_0$wget[63:0] :
	       mmio_cRqQ_enqReq_rl[63:0] ;
  assign x__h487050 =
	     sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h484113 ;
  assign x__h487051 =
	     sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h484834 ;
  assign x__h487052 =
	     sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h485549 ;
  assign x__h508965 = sfd__h487890 << x__h508998 ;
  assign x__h508998 =
	     12'd57 -
	     _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8760 ;
  assign x__h547818 = sfd__h526884 << x__h547851 ;
  assign x__h547851 =
	     12'd57 -
	     _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10245 ;
  assign x__h587122 = sfd__h566188 << x__h587155 ;
  assign x__h587155 =
	     12'd57 -
	     _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9475 ;
  assign x__h608911 =
	     (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ?
	       _theResult___fst__h608922 :
	       a__h608374 ;
  assign x__h608937 = a__h608374[63] ^ b__h608375[63] ;
  assign x__h609551 =
	     (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_divisorQ$D_OUT ==
	      64'd0) ?
	       { 64'hFFFFFFFFFFFFFFFF,
		 coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_dividendQ$D_OUT[139:76] } :
	       { coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11256,
		 coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d11257 } ;
  assign x__h619375 = { csrf_frm_reg, csrf_fflags_reg } ;
  assign x__h623649 =
	     coreFix_aluExe_1_dispToRegQ$first[131] ?
	       rVal1__h615933 :
	       v__h614705 ;
  assign x__h623650 =
	     sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h621659 ;
  assign x__h646279 =
	     coreFix_aluExe_0_dispToRegQ$first[131] ?
	       rVal1__h640782 :
	       v__h639708 ;
  assign x__h646280 =
	     sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h644299 ;
  assign x__h653740 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ;
  assign x__h653791 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ;
  assign x__h705027 =
	     (!rob$deqPort_0_deq_data[166] &&
	      (rob$deqPort_0_deq_data[165:162] == 4'd1 ||
	       rob$deqPort_0_deq_data[165:162] == 4'd12)) ?
	       rob$deqPort_0_deq_data[161:98] :
	       rob$deqPort_0_deq_data[95:32] ;
  assign x__h711636 = { cause_code__h708698, 2'b0 } ;
  assign x__h719695 = { 1'b0, csrf_spp_reg } ;
  assign x__h723635 =
	     NOT_rob_deqPort_0_canDeq__4995_4996_OR_rob_deq_ETC___d15187 ?
	       y_avValue_snd_snd_snd_fst__h723457 :
	       IF_rob_deqPort_0_canDeq__4995_THEN_IF_NOT_rob__ETC___d15216 ;
  assign x__h75785 = mmio_pRqQ_data_0[31:0] ;
  assign x_addr__h318726 =
	     coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
	       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] :
	       coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ;
  assign x_data__h65634 =
	     EN_mmioToPlatform_pRq_enq ?
	       mmio_pRqQ_enqReq_lat_0$wget[31:0] :
	       mmio_pRqQ_enqReq_rl[31:0] ;
  assign x_data_imm__h682377 = fetchStage$pipelines_0_first[159:128] ;
  assign x_data_imm__h698281 = fetchStage$pipelines_1_first[159:128] ;
  assign x_decodeInfo_frm__h661528 = csrf_frm_reg ;
  assign x_quotient__h479959 =
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ?
	       64'hFFFFFFFFFFFFFFFF :
	       ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] &&
		 coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[9]) ?
		  q___1__h480782 :
		  coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[203:140]) ;
  assign x_reg_ifc__read__h616340 = { 63'd0, csrf_stats_module_doStats } ;
  assign x_remainder__h479960 =
	     coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[75] ?
	       coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[74:11] :
	       ((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[10] &&
		 coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[8]) ?
		  r___1__h480809 :
		  coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc_respQ$D_OUT[139:76]) ;
  assign y__h258435 =
	     { coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518],
	       coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ;
  assign y__h626451 = coreFix_aluExe_1_regToExeQ$first[176:113] + 64'd4 ;
  assign y__h648788 = coreFix_aluExe_0_regToExeQ$first[176:113] + 64'd4 ;
  assign y__h653770 = ~x__h653740 ;
  assign y__h658459 =
	     { ~csrf_mideleg_11_reg,
	       1'd1,
	       ~csrf_mideleg_9_7_reg,
	       1'd1,
	       ~csrf_mideleg_5_3_reg,
	       1'd1,
	       ~csrf_mideleg_1_0_reg } ;
  assign y__h693636 = 12'd1 << specTagManager$nextSpecTag ;
  assign y__h723410 =
	     NOT_rob_deqPort_0_canDeq__4995_4996_OR_rob_deq_ETC___d15187 ?
	       y_avValue_snd_snd_snd_snd_snd__h723463 :
	       IF_rob_deqPort_0_canDeq__4995_THEN_IF_NOT_rob__ETC___d15104 ;
  assign y_avValue__h183778 =
	     NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1611 ?
	       coreFix_aluExe_0_bypassWire_3$wget[63:0] :
	       IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1679 ;
  assign y_avValue__h184497 =
	     NOT_coreFix_memExe_bypassWire_0_whas__584_590__ETC___d1640 ?
	       coreFix_aluExe_0_bypassWire_3$wget[63:0] :
	       IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1687 ;
  assign y_avValue__h484113 =
	     NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8327 ?
	       coreFix_aluExe_0_bypassWire_3$wget[63:0] :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8454 ;
  assign y_avValue__h484834 =
	     NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8356 ?
	       coreFix_aluExe_0_bypassWire_3$wget[63:0] :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8462 ;
  assign y_avValue__h485549 =
	     NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8382 ?
	       coreFix_aluExe_0_bypassWire_3$wget[63:0] :
	       IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8470 ;
  assign y_avValue__h615876 =
	     NOT_coreFix_aluExe_1_bypassWire_0_whas__1510_1_ETC___d11537 ?
	       coreFix_aluExe_0_bypassWire_3$wget[63:0] :
	       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11943 ;
  assign y_avValue__h621659 =
	     NOT_coreFix_aluExe_1_bypassWire_0_whas__1510_1_ETC___d11567 ?
	       coreFix_aluExe_0_bypassWire_3$wget[63:0] :
	       IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11952 ;
  assign y_avValue__h640727 =
	     NOT_coreFix_aluExe_0_bypassWire_0_whas__2366_2_ETC___d12393 ?
	       coreFix_aluExe_0_bypassWire_3$wget[63:0] :
	       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12617 ;
  assign y_avValue__h644299 =
	     NOT_coreFix_aluExe_0_bypassWire_0_whas__2366_2_ETC___d12423 ?
	       coreFix_aluExe_0_bypassWire_3$wget[63:0] :
	       IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12626 ;
  assign y_avValue_fst__h686920 =
	     (fetchStage$pipelines_0_first[194:192] == 3'd1) ?
	       spec_bits__h693623 :
	       specTagManager$currentSpecBits ;
  assign y_avValue_fst__h722364 =
	     (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] ||
	      rob$deqPort_0_deq_data[167] ||
	      rob$deqPort_0_deq_data[257:253] == 5'd0 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd21 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd17 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd18 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd13 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd16 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd15 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd19 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd20) ?
	       5'd0 :
	       rob$deqPort_0_deq_data[31:27] ;
  assign y_avValue_fst__h723306 =
	     IF_rob_deqPort_0_canDeq__4995_THEN_IF_NOT_rob__ETC___d15194 |
	     rob$deqPort_1_deq_data[31:27] ;
  assign y_avValue_fst__h723334 =
	     (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
	      rob$deqPort_1_deq_data[167] ||
	      rob$deqPort_1_deq_data[257:253] == 5'd0 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd21 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd17 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd18 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd13 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd16 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd15 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd19 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd20) ?
	       IF_rob_deqPort_0_canDeq__4995_THEN_IF_NOT_rob__ETC___d15194 :
	       y_avValue_fst__h723306 ;
  assign y_avValue_new_pc__h711402 =
	     (csrf_stvec_mode_low_reg && commitStage_commitTrap[36]) ?
	       base__h711621 + { 58'd0, x__h711636 } :
	       base__h711621 ;
  assign y_avValue_new_pc__h711588 =
	     (csrf_mtvec_mode_low_reg && commitStage_commitTrap[36]) ?
	       base__h711641 + { 58'd0, x__h711636 } :
	       base__h711641 ;
  assign y_avValue_snd_fst__h687194 =
	     ((fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	       specTagManager$canClaim) &&
	      regRenamingTable$rename_0_canRename &&
	      NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548) ?
	       y_avValue_snd_fst__h687229 :
	       specTagManager$currentSpecBits ;
  assign y_avValue_snd_fst__h687229 =
	     IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 ?
	       y_avValue_fst__h686920 :
	       specTagManager$currentSpecBits ;
  assign y_avValue_snd_snd_snd_fst__h722798 =
	     (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] ||
	      rob$deqPort_0_deq_data[167] ||
	      rob$deqPort_0_deq_data[257:253] == 5'd0 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd21 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd17 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd18 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd13 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd16 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd15 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd19 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd20) ?
	       2'd0 :
	       2'd1 ;
  assign y_avValue_snd_snd_snd_fst__h723457 =
	     (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
	      rob$deqPort_1_deq_data[167] ||
	      rob$deqPort_1_deq_data[257:253] == 5'd0 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd21 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd17 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd18 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd13 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd16 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd15 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd19 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd20) ?
	       IF_rob_deqPort_0_canDeq__4995_THEN_IF_NOT_rob__ETC___d15216 :
	       y_avValue_snd_snd_snd_fst__h723486 ;
  assign y_avValue_snd_snd_snd_fst__h723486 =
	     IF_rob_deqPort_0_canDeq__4995_THEN_IF_NOT_rob__ETC___d15216 +
	     2'd1 ;
  assign y_avValue_snd_snd_snd_snd_snd__h722804 =
	     (!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] ||
	      rob$deqPort_0_deq_data[167] ||
	      rob$deqPort_0_deq_data[257:253] == 5'd0 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd21 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd17 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd18 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd13 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd16 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd15 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd19 ||
	      rob$deqPort_0_deq_data[257:253] == 5'd20) ?
	       64'd0 :
	       64'd1 ;
  assign y_avValue_snd_snd_snd_snd_snd__h723463 =
	     (!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
	      rob$deqPort_1_deq_data[167] ||
	      rob$deqPort_1_deq_data[257:253] == 5'd0 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd21 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd17 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd18 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd13 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd16 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd15 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd19 ||
	      rob$deqPort_1_deq_data[257:253] == 5'd20) ?
	       IF_rob_deqPort_0_canDeq__4995_THEN_IF_NOT_rob__ETC___d15104 :
	       y_avValue_snd_snd_snd_snd_snd__h723492 ;
  assign y_avValue_snd_snd_snd_snd_snd__h723492 =
	     IF_rob_deqPort_0_canDeq__4995_THEN_IF_NOT_rob__ETC___d15104 +
	     64'd1 ;
  always@(mmio_cRqQ_data_0)
  begin
    case (mmio_cRqQ_data_0[77:76])
      2'd0, 2'd1, 2'd2:
	  CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1 =
	      mmio_cRqQ_data_0[77:72];
      2'd3:
	  CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1 =
	      { 2'd3, mmio_cRqQ_data_0[75:72] };
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87])
      3'd0:
	  x__h200347 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0];
      3'd1:
	  x__h200347 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64];
      3'd2:
	  x__h200347 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128];
      3'd3:
	  x__h200347 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192];
      3'd4:
	  x__h200347 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256];
      3'd5:
	  x__h200347 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320];
      3'd6:
	  x__h200347 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384];
      3'd7:
	  x__h200347 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 or
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 or
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 or
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 or
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 or
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 or
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP)
      3'd0:
	  x__h290393 =
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0;
      3'd1:
	  x__h290393 =
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1;
      3'd2:
	  x__h290393 =
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2;
      3'd3:
	  x__h290393 =
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3;
      3'd4:
	  x__h290393 =
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4;
      3'd5:
	  x__h290393 =
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5;
      3'd6:
	  x__h290393 =
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6;
      3'd7:
	  x__h290393 =
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7;
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  addr__h294614 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518];
      1'd1:
	  addr__h294614 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91])
      3'd0:
	  curData__h195304 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0];
      3'd1:
	  curData__h195304 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64];
      3'd2:
	  curData__h195304 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128];
      3'd3:
	  curData__h195304 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192];
      3'd4:
	  curData__h195304 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256];
      3'd5:
	  curData__h195304 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320];
      3'd6:
	  curData__h195304 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384];
      3'd7:
	  curData__h195304 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448];
    endcase
  end
  always@(commitStage_commitTrap)
  begin
    case (commitStage_commitTrap[35:32])
      4'd0, 4'd3: trap_val__h709721 = commitStage_commitTrap[164:101];
      4'd2: trap_val__h709721 = { 32'd0, commitStage_commitTrap[31:0] };
      default: trap_val__h709721 =
		   (commitStage_commitTrap[35:32] != 4'd8 &&
		    commitStage_commitTrap[35:32] != 4'd9 &&
		    commitStage_commitTrap[35:32] != 4'd11) ?
		     commitStage_commitTrap[100:37] :
		     64'd0;
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  x__h296163 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0];
      1'd1:
	  x__h296163 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0];
    endcase
  end
  always@(coreFix_aluExe_1_dispToRegQ$first or
	  fflags_csr__read__h616210 or
	  frm_csr__read__h616221 or
	  fcsr_csr__read__h616235 or
	  sstatus_csr__read__h616431 or
	  sie_csr__read__h616501 or
	  stvec_csr__read__h616544 or
	  scounteren_csr__read__h616597 or
	  csrf_sscratch_csr or
	  csrf_sepc_csr or
	  scause_csr__read__h616735 or
	  csrf_stval_csr or
	  sip_csr__read__h616875 or
	  satp_csr__read__h616938 or
	  mstatus_csr__read__h617081 or
	  medeleg_csr__read__h617229 or
	  mideleg_csr__read__h617324 or
	  mie_csr__read__h617448 or
	  mtvec_csr__read__h617530 or
	  mcounteren_csr__read__h617622 or
	  csrf_mscratch_csr or
	  csrf_mepc_csr or
	  mcause_csr__read__h617877 or
	  csrf_mtval_csr or
	  mip_csr__read__h618110 or
	  csrf_rg_tselect or
	  rg_tdata1__read__h619065 or
	  csrf_rg_tdata2 or
	  csrf_rg_tdata3 or
	  x_reg_ifc__read__h616340 or
	  n__read__h618214 or n__read__h618405 or csrf_time_reg)
  begin
    case (coreFix_aluExe_1_dispToRegQ$first[130:119])
      12'd1: rVal1__h615933 = fflags_csr__read__h616210;
      12'd2: rVal1__h615933 = frm_csr__read__h616221;
      12'd3: rVal1__h615933 = fcsr_csr__read__h616235;
      12'd256: rVal1__h615933 = sstatus_csr__read__h616431;
      12'd260: rVal1__h615933 = sie_csr__read__h616501;
      12'd261: rVal1__h615933 = stvec_csr__read__h616544;
      12'd262: rVal1__h615933 = scounteren_csr__read__h616597;
      12'd320: rVal1__h615933 = csrf_sscratch_csr;
      12'd321: rVal1__h615933 = csrf_sepc_csr;
      12'd322: rVal1__h615933 = scause_csr__read__h616735;
      12'd323: rVal1__h615933 = csrf_stval_csr;
      12'd324: rVal1__h615933 = sip_csr__read__h616875;
      12'd384: rVal1__h615933 = satp_csr__read__h616938;
      12'd768: rVal1__h615933 = mstatus_csr__read__h617081;
      12'd769: rVal1__h615933 = 64'h800000000014112D;
      12'd770: rVal1__h615933 = medeleg_csr__read__h617229;
      12'd771: rVal1__h615933 = mideleg_csr__read__h617324;
      12'd772: rVal1__h615933 = mie_csr__read__h617448;
      12'd773: rVal1__h615933 = mtvec_csr__read__h617530;
      12'd774: rVal1__h615933 = mcounteren_csr__read__h617622;
      12'd832: rVal1__h615933 = csrf_mscratch_csr;
      12'd833: rVal1__h615933 = csrf_mepc_csr;
      12'd834: rVal1__h615933 = mcause_csr__read__h617877;
      12'd835: rVal1__h615933 = csrf_mtval_csr;
      12'd836: rVal1__h615933 = mip_csr__read__h618110;
      12'd1952: rVal1__h615933 = csrf_rg_tselect;
      12'd1953: rVal1__h615933 = rg_tdata1__read__h619065;
      12'd1954: rVal1__h615933 = csrf_rg_tdata2;
      12'd1955: rVal1__h615933 = csrf_rg_tdata3;
      12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860:
	  rVal1__h615933 = 64'd0;
      12'd2049: rVal1__h615933 = x_reg_ifc__read__h616340;
      12'd2816, 12'd3072: rVal1__h615933 = n__read__h618214;
      12'd2818, 12'd3074: rVal1__h615933 = n__read__h618405;
      12'd3073: rVal1__h615933 = csrf_time_reg;
      default: rVal1__h615933 = 64'b0;
    endcase
  end
  always@(coreFix_aluExe_0_dispToRegQ$first or
	  fflags_csr__read__h616210 or
	  frm_csr__read__h616221 or
	  fcsr_csr__read__h616235 or
	  sstatus_csr__read__h616431 or
	  sie_csr__read__h616501 or
	  stvec_csr__read__h616544 or
	  scounteren_csr__read__h616597 or
	  csrf_sscratch_csr or
	  csrf_sepc_csr or
	  scause_csr__read__h616735 or
	  csrf_stval_csr or
	  sip_csr__read__h616875 or
	  satp_csr__read__h616938 or
	  mstatus_csr__read__h617081 or
	  medeleg_csr__read__h617229 or
	  mideleg_csr__read__h617324 or
	  mie_csr__read__h617448 or
	  mtvec_csr__read__h617530 or
	  mcounteren_csr__read__h617622 or
	  csrf_mscratch_csr or
	  csrf_mepc_csr or
	  mcause_csr__read__h617877 or
	  csrf_mtval_csr or
	  mip_csr__read__h618110 or
	  csrf_rg_tselect or
	  rg_tdata1__read__h619065 or
	  csrf_rg_tdata2 or
	  csrf_rg_tdata3 or
	  x_reg_ifc__read__h616340 or
	  n__read__h618214 or n__read__h618405 or csrf_time_reg)
  begin
    case (coreFix_aluExe_0_dispToRegQ$first[130:119])
      12'd1: rVal1__h640782 = fflags_csr__read__h616210;
      12'd2: rVal1__h640782 = frm_csr__read__h616221;
      12'd3: rVal1__h640782 = fcsr_csr__read__h616235;
      12'd256: rVal1__h640782 = sstatus_csr__read__h616431;
      12'd260: rVal1__h640782 = sie_csr__read__h616501;
      12'd261: rVal1__h640782 = stvec_csr__read__h616544;
      12'd262: rVal1__h640782 = scounteren_csr__read__h616597;
      12'd320: rVal1__h640782 = csrf_sscratch_csr;
      12'd321: rVal1__h640782 = csrf_sepc_csr;
      12'd322: rVal1__h640782 = scause_csr__read__h616735;
      12'd323: rVal1__h640782 = csrf_stval_csr;
      12'd324: rVal1__h640782 = sip_csr__read__h616875;
      12'd384: rVal1__h640782 = satp_csr__read__h616938;
      12'd768: rVal1__h640782 = mstatus_csr__read__h617081;
      12'd769: rVal1__h640782 = 64'h800000000014112D;
      12'd770: rVal1__h640782 = medeleg_csr__read__h617229;
      12'd771: rVal1__h640782 = mideleg_csr__read__h617324;
      12'd772: rVal1__h640782 = mie_csr__read__h617448;
      12'd773: rVal1__h640782 = mtvec_csr__read__h617530;
      12'd774: rVal1__h640782 = mcounteren_csr__read__h617622;
      12'd832: rVal1__h640782 = csrf_mscratch_csr;
      12'd833: rVal1__h640782 = csrf_mepc_csr;
      12'd834: rVal1__h640782 = mcause_csr__read__h617877;
      12'd835: rVal1__h640782 = csrf_mtval_csr;
      12'd836: rVal1__h640782 = mip_csr__read__h618110;
      12'd1952: rVal1__h640782 = csrf_rg_tselect;
      12'd1953: rVal1__h640782 = rg_tdata1__read__h619065;
      12'd1954: rVal1__h640782 = csrf_rg_tdata2;
      12'd1955: rVal1__h640782 = csrf_rg_tdata3;
      12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860:
	  rVal1__h640782 = 64'd0;
      12'd2049: rVal1__h640782 = x_reg_ifc__read__h616340;
      12'd2816, 12'd3072: rVal1__h640782 = n__read__h618214;
      12'd2818, 12'd3074: rVal1__h640782 = n__read__h618405;
      12'd3073: rVal1__h640782 = csrf_time_reg;
      default: rVal1__h640782 = 64'b0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0, 3'd1: _theResult___fst_exp__h442113 = 8'd255;
      3'd2:
	  _theResult___fst_exp__h442113 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		8'd254 :
		8'd255;
      3'd3:
	  _theResult___fst_exp__h442113 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		8'd255 :
		8'd254;
      3'd4: _theResult___fst_exp__h442113 = 8'd254;
      default: _theResult___fst_exp__h442113 = 8'd0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0, 3'd1: _theResult___fst_exp__h350719 = 8'd255;
      3'd2:
	  _theResult___fst_exp__h350719 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		8'd254 :
		8'd255;
      3'd3:
	  _theResult___fst_exp__h350719 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		8'd255 :
		8'd254;
      3'd4: _theResult___fst_exp__h350719 = 8'd254;
      default: _theResult___fst_exp__h350719 = 8'd0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0, 3'd1: _theResult___fst_sfd__h350720 = 23'd0;
      3'd2:
	  _theResult___fst_sfd__h350720 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		23'd8388607 :
		23'd0;
      3'd3:
	  _theResult___fst_sfd__h350720 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
		23'd0 :
		23'd8388607;
      3'd4: _theResult___fst_sfd__h350720 = 23'd8388607;
      default: _theResult___fst_sfd__h350720 = 23'd0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0, 3'd1: _theResult___fst_exp__h396418 = 8'd255;
      3'd2:
	  _theResult___fst_exp__h396418 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		8'd254 :
		8'd255;
      3'd3:
	  _theResult___fst_exp__h396418 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		8'd255 :
		8'd254;
      3'd4: _theResult___fst_exp__h396418 = 8'd254;
      default: _theResult___fst_exp__h396418 = 8'd0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0, 3'd1: _theResult___fst_sfd__h396419 = 23'd0;
      3'd2:
	  _theResult___fst_sfd__h396419 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		23'd8388607 :
		23'd0;
      3'd3:
	  _theResult___fst_sfd__h396419 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
		23'd0 :
		23'd8388607;
      3'd4: _theResult___fst_sfd__h396419 = 23'd8388607;
      default: _theResult___fst_sfd__h396419 = 23'd0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0, 3'd1: _theResult___fst_sfd__h442114 = 23'd0;
      3'd2:
	  _theResult___fst_sfd__h442114 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		23'd8388607 :
		23'd0;
      3'd3:
	  _theResult___fst_sfd__h442114 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
		23'd0 :
		23'd8388607;
      3'd4: _theResult___fst_sfd__h442114 = 23'd8388607;
      default: _theResult___fst_sfd__h442114 = 23'd0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 = 11'd2046;
      3'd2:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
		11'd2047 :
		11'd2046;
      3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
		11'd2046 :
		11'd2047;
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 = 11'd0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 =
	      52'hFFFFFFFFFFFFF;
      3'd2:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
		52'd0 :
		52'hFFFFFFFFFFFFF;
      3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
		52'hFFFFFFFFFFFFF :
		52'd0;
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 = 52'd0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 = 11'd2046;
      3'd2:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
		11'd2047 :
		11'd2046;
      3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
		11'd2046 :
		11'd2047;
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 = 11'd0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 =
	      52'hFFFFFFFFFFFFF;
      3'd2:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
		52'd0 :
		52'hFFFFFFFFFFFFF;
      3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
		52'hFFFFFFFFFFFFF :
		52'd0;
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 = 52'd0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 = 11'd2046;
      3'd2:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
		11'd2047 :
		11'd2046;
      3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
		11'd2046 :
		11'd2047;
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 = 11'd0;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q12 =
	      52'hFFFFFFFFFFFFF;
      3'd2:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q12 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
		52'd0 :
		52'hFFFFFFFFFFFFF;
      3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q12 =
	      (coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
	       32'hFFFFFFFF &&
	       coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
		52'hFFFFFFFFFFFFF :
		52'd0;
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q12 = 52'd0;
    endcase
  end
  always@(commitStage_commitTrap)
  begin
    case (commitStage_commitTrap[35:32])
      4'd0,
      4'd1,
      4'd2,
      4'd3,
      4'd4,
      4'd5,
      4'd6,
      4'd7,
      4'd8,
      4'd9,
      4'd11,
      4'd12,
      4'd13:
	  i__h708713 = commitStage_commitTrap[35:32];
      default: i__h708713 = 4'd15;
    endcase
  end
  always@(commitStage_commitTrap)
  begin
    case (commitStage_commitTrap[35:32])
      4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9:
	  i__h708873 = commitStage_commitTrap[35:32];
      default: i__h708873 = 4'd11;
    endcase
  end
  always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0)
  begin
    case (coreFix_memExe_lsq$firstLd[19])
      1'd0:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1356 =
	      coreFix_memExe_respLrScAmoQ_data_0[31:0];
      1'd1:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1356 =
	      coreFix_memExe_respLrScAmoQ_data_0[63:32];
    endcase
  end
  always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0)
  begin
    case (coreFix_memExe_lsq$firstLd[19:18])
      2'd0:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 =
	      coreFix_memExe_respLrScAmoQ_data_0[15:0];
      2'd1:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 =
	      coreFix_memExe_respLrScAmoQ_data_0[31:16];
      2'd2:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 =
	      coreFix_memExe_respLrScAmoQ_data_0[47:32];
      2'd3:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1367 =
	      coreFix_memExe_respLrScAmoQ_data_0[63:48];
    endcase
  end
  always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0)
  begin
    case (coreFix_memExe_lsq$firstLd[19:17])
      3'd0:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381 =
	      coreFix_memExe_respLrScAmoQ_data_0[7:0];
      3'd1:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381 =
	      coreFix_memExe_respLrScAmoQ_data_0[15:8];
      3'd2:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381 =
	      coreFix_memExe_respLrScAmoQ_data_0[23:16];
      3'd3:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381 =
	      coreFix_memExe_respLrScAmoQ_data_0[31:24];
      3'd4:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381 =
	      coreFix_memExe_respLrScAmoQ_data_0[39:32];
      3'd5:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381 =
	      coreFix_memExe_respLrScAmoQ_data_0[47:40];
      3'd6:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381 =
	      coreFix_memExe_respLrScAmoQ_data_0[55:48];
      3'd7:
	  SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_073_ETC___d1381 =
	      coreFix_memExe_respLrScAmoQ_data_0[63:56];
    endcase
  end
  always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0)
  begin
    case (coreFix_memExe_lsq$firstLd[19])
      1'd0:
	  SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408 =
	      mmio_dataRespQ_data_0[31:0];
      1'd1:
	  SEL_ARR_mmio_dataRespQ_data_0_109_BITS_31_TO_0_ETC___d1408 =
	      mmio_dataRespQ_data_0[63:32];
    endcase
  end
  always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0)
  begin
    case (coreFix_memExe_lsq$firstLd[19:17])
      3'd0:
	  SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430 =
	      mmio_dataRespQ_data_0[7:0];
      3'd1:
	  SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430 =
	      mmio_dataRespQ_data_0[15:8];
      3'd2:
	  SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430 =
	      mmio_dataRespQ_data_0[23:16];
      3'd3:
	  SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430 =
	      mmio_dataRespQ_data_0[31:24];
      3'd4:
	  SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430 =
	      mmio_dataRespQ_data_0[39:32];
      3'd5:
	  SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430 =
	      mmio_dataRespQ_data_0[47:40];
      3'd6:
	  SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430 =
	      mmio_dataRespQ_data_0[55:48];
      3'd7:
	  SEL_ARR_mmio_dataRespQ_data_0_109_BITS_7_TO_0__ETC___d1430 =
	      mmio_dataRespQ_data_0[63:56];
    endcase
  end
  always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0)
  begin
    case (coreFix_memExe_lsq$firstLd[19:18])
      2'd0:
	  SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 =
	      mmio_dataRespQ_data_0[15:0];
      2'd1:
	  SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 =
	      mmio_dataRespQ_data_0[31:16];
      2'd2:
	  SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 =
	      mmio_dataRespQ_data_0[47:32];
      2'd3:
	  SEL_ARR_mmio_dataRespQ_data_0_109_BITS_15_TO_0_ETC___d1417 =
	      mmio_dataRespQ_data_0[63:48];
    endcase
  end
  always@(coreFix_memExe_dTlb$procResp)
  begin
    case (coreFix_memExe_dTlb$procResp[105:103])
      3'd0, 3'd2:
	  CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q13 = 4'd4;
      default: CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q13 = 4'd6;
    endcase
  end
  always@(coreFix_memExe_dTlb$procResp)
  begin
    case (coreFix_memExe_dTlb$procResp[109:106])
      4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9:
	  CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q14 =
	      coreFix_memExe_dTlb$procResp[109:106];
      4'd11: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q14 = 4'd10;
      4'd12: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q14 = 4'd11;
      4'd13: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q14 = 4'd12;
      default: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q14 = 4'd13;
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2968 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[65:2];
      1'd1:
	  SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2968 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[65:2];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q15 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[514:451];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q15 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[514:451];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q16 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[450:387];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q16 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[450:387];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q17 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[386:323];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q17 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[386:323];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q18 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[322:259];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q18 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[322:259];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q19 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[258:195];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q19 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[258:195];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q20 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[194:131];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q20 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0, 3'd1, 3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5216 =
		   coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(guard__h359456 or
	  _theResult___fst_exp__h367504 or
	  out_exp__h367949 or _theResult___exp__h367946)
  begin
    case (guard__h359456)
      2'b0, 2'b01:
	  CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q25 =
	      _theResult___fst_exp__h367504;
      2'b10:
	  CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q25 =
	      out_exp__h367949;
      2'b11:
	  CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q25 =
	      _theResult___exp__h367946;
    endcase
  end
  always@(guard__h359456 or
	  _theResult___fst_exp__h367504 or _theResult___exp__h367946)
  begin
    case (guard__h359456)
      2'b0:
	  CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q26 =
	      _theResult___fst_exp__h367504;
      2'b01, 2'b10, 2'b11:
	  CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q26 =
	      _theResult___exp__h367946;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q25 or
	  CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q26 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630 or
	  _theResult___fst_exp__h367504)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h368024 =
	      CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q25;
      3'd1:
	  _theResult___fst_exp__h368024 =
	      CASE_guard59456_0b0_theResult___fst_exp67504_0_ETC__q26;
      3'd2:
	  _theResult___fst_exp__h368024 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4628;
      3'd3:
	  _theResult___fst_exp__h368024 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4630;
      3'd4: _theResult___fst_exp__h368024 = _theResult___fst_exp__h367504;
      default: _theResult___fst_exp__h368024 = 8'd0;
    endcase
  end
  always@(guard__h350747 or
	  _theResult___fst_exp__h358848 or
	  out_exp__h359367 or _theResult___exp__h359364)
  begin
    case (guard__h350747)
      2'b0, 2'b01:
	  CASE_guard50747_0b0_theResult___fst_exp58848_0_ETC__q27 =
	      _theResult___fst_exp__h358848;
      2'b10:
	  CASE_guard50747_0b0_theResult___fst_exp58848_0_ETC__q27 =
	      out_exp__h359367;
      2'b11:
	  CASE_guard50747_0b0_theResult___fst_exp58848_0_ETC__q27 =
	      _theResult___exp__h359364;
    endcase
  end
  always@(guard__h350747 or
	  _theResult___fst_exp__h358848 or _theResult___exp__h359364)
  begin
    case (guard__h350747)
      2'b0:
	  CASE_guard50747_0b0_theResult___fst_exp58848_0_ETC__q28 =
	      _theResult___fst_exp__h358848;
      2'b01, 2'b10, 2'b11:
	  CASE_guard50747_0b0_theResult___fst_exp58848_0_ETC__q28 =
	      _theResult___exp__h359364;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  CASE_guard50747_0b0_theResult___fst_exp58848_0_ETC__q27 or
	  CASE_guard50747_0b0_theResult___fst_exp58848_0_ETC__q28 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4406 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4409 or
	  _theResult___fst_exp__h358848)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h359442 =
	      CASE_guard50747_0b0_theResult___fst_exp58848_0_ETC__q27;
      3'd1:
	  _theResult___fst_exp__h359442 =
	      CASE_guard50747_0b0_theResult___fst_exp58848_0_ETC__q28;
      3'd2:
	  _theResult___fst_exp__h359442 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4406;
      3'd3:
	  _theResult___fst_exp__h359442 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4409;
      3'd4: _theResult___fst_exp__h359442 = _theResult___fst_exp__h358848;
      default: _theResult___fst_exp__h359442 = 8'd0;
    endcase
  end
  always@(guard__h368386 or
	  _theResult___fst_exp__h376614 or
	  out_exp__h377133 or _theResult___exp__h377130)
  begin
    case (guard__h368386)
      2'b0, 2'b01:
	  CASE_guard68386_0b0_theResult___fst_exp76614_0_ETC__q33 =
	      _theResult___fst_exp__h376614;
      2'b10:
	  CASE_guard68386_0b0_theResult___fst_exp76614_0_ETC__q33 =
	      out_exp__h377133;
      2'b11:
	  CASE_guard68386_0b0_theResult___fst_exp76614_0_ETC__q33 =
	      _theResult___exp__h377130;
    endcase
  end
  always@(guard__h368386 or
	  _theResult___fst_exp__h376614 or _theResult___exp__h377130)
  begin
    case (guard__h368386)
      2'b0:
	  CASE_guard68386_0b0_theResult___fst_exp76614_0_ETC__q34 =
	      _theResult___fst_exp__h376614;
      2'b01, 2'b10, 2'b11:
	  CASE_guard68386_0b0_theResult___fst_exp76614_0_ETC__q34 =
	      _theResult___exp__h377130;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  CASE_guard68386_0b0_theResult___fst_exp76614_0_ETC__q33 or
	  CASE_guard68386_0b0_theResult___fst_exp76614_0_ETC__q34 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4953 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4955 or
	  _theResult___fst_exp__h376614)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h377208 =
	      CASE_guard68386_0b0_theResult___fst_exp76614_0_ETC__q33;
      3'd1:
	  _theResult___fst_exp__h377208 =
	      CASE_guard68386_0b0_theResult___fst_exp76614_0_ETC__q34;
      3'd2:
	  _theResult___fst_exp__h377208 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4953;
      3'd3:
	  _theResult___fst_exp__h377208 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4955;
      3'd4: _theResult___fst_exp__h377208 = _theResult___fst_exp__h376614;
      default: _theResult___fst_exp__h377208 = 8'd0;
    endcase
  end
  always@(guard__h377222 or
	  _theResult___fst_exp__h385299 or
	  out_exp__h385769 or _theResult___exp__h385766)
  begin
    case (guard__h377222)
      2'b0, 2'b01:
	  CASE_guard77222_0b0_theResult___fst_exp85299_0_ETC__q38 =
	      _theResult___fst_exp__h385299;
      2'b10:
	  CASE_guard77222_0b0_theResult___fst_exp85299_0_ETC__q38 =
	      out_exp__h385769;
      2'b11:
	  CASE_guard77222_0b0_theResult___fst_exp85299_0_ETC__q38 =
	      _theResult___exp__h385766;
    endcase
  end
  always@(guard__h377222 or
	  _theResult___fst_exp__h385299 or _theResult___exp__h385766)
  begin
    case (guard__h377222)
      2'b0:
	  CASE_guard77222_0b0_theResult___fst_exp85299_0_ETC__q39 =
	      _theResult___fst_exp__h385299;
      2'b01, 2'b10, 2'b11:
	  CASE_guard77222_0b0_theResult___fst_exp85299_0_ETC__q39 =
	      _theResult___exp__h385766;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  CASE_guard77222_0b0_theResult___fst_exp85299_0_ETC__q38 or
	  CASE_guard77222_0b0_theResult___fst_exp85299_0_ETC__q39 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 or
	  _theResult___fst_exp__h385299)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h385844 =
	      CASE_guard77222_0b0_theResult___fst_exp85299_0_ETC__q38;
      3'd1:
	  _theResult___fst_exp__h385844 =
	      CASE_guard77222_0b0_theResult___fst_exp85299_0_ETC__q39;
      3'd2:
	  _theResult___fst_exp__h385844 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022;
      3'd3:
	  _theResult___fst_exp__h385844 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024;
      3'd4: _theResult___fst_exp__h385844 = _theResult___fst_exp__h385299;
      default: _theResult___fst_exp__h385844 = 8'd0;
    endcase
  end
  always@(guard__h359456 or
	  _theResult___snd__h367455 or
	  out_sfd__h367950 or _theResult___sfd__h367947)
  begin
    case (guard__h359456)
      2'b0, 2'b01:
	  CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q40 =
	      _theResult___snd__h367455[56:34];
      2'b10:
	  CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q40 =
	      out_sfd__h367950;
      2'b11:
	  CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q40 =
	      _theResult___sfd__h367947;
    endcase
  end
  always@(guard__h359456 or
	  _theResult___snd__h367455 or _theResult___sfd__h367947)
  begin
    case (guard__h359456)
      2'b0:
	  CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q41 =
	      _theResult___snd__h367455[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q41 =
	      _theResult___sfd__h367947;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q40 or
	  CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q41 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074 or
	  _theResult___snd__h367455)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h368025 =
	      CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q40;
      3'd1:
	  _theResult___fst_sfd__h368025 =
	      CASE_guard59456_0b0_theResult___snd67455_BITS__ETC__q41;
      3'd2:
	  _theResult___fst_sfd__h368025 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5072;
      3'd3:
	  _theResult___fst_sfd__h368025 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5074;
      3'd4: _theResult___fst_sfd__h368025 = _theResult___snd__h367455[56:34];
      default: _theResult___fst_sfd__h368025 = 23'd0;
    endcase
  end
  always@(guard__h350747 or
	  sfdin__h358842 or out_sfd__h359368 or _theResult___sfd__h359365)
  begin
    case (guard__h350747)
      2'b0, 2'b01:
	  CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q42 =
	      sfdin__h358842[56:34];
      2'b10:
	  CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q42 =
	      out_sfd__h359368;
      2'b11:
	  CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q42 =
	      _theResult___sfd__h359365;
    endcase
  end
  always@(guard__h350747 or sfdin__h358842 or _theResult___sfd__h359365)
  begin
    case (guard__h350747)
      2'b0:
	  CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q43 =
	      sfdin__h358842[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q43 =
	      _theResult___sfd__h359365;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q42 or
	  CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q43 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055 or
	  sfdin__h358842)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h359443 =
	      CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q42;
      3'd1:
	  _theResult___fst_sfd__h359443 =
	      CASE_guard50747_0b0_sfdin58842_BITS_56_TO_34_0_ETC__q43;
      3'd2:
	  _theResult___fst_sfd__h359443 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5053;
      3'd3:
	  _theResult___fst_sfd__h359443 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5055;
      3'd4: _theResult___fst_sfd__h359443 = sfdin__h358842[56:34];
      default: _theResult___fst_sfd__h359443 = 23'd0;
    endcase
  end
  always@(guard__h368386 or
	  sfdin__h376608 or out_sfd__h377134 or _theResult___sfd__h377131)
  begin
    case (guard__h368386)
      2'b0, 2'b01:
	  CASE_guard68386_0b0_sfdin76608_BITS_56_TO_34_0_ETC__q44 =
	      sfdin__h376608[56:34];
      2'b10:
	  CASE_guard68386_0b0_sfdin76608_BITS_56_TO_34_0_ETC__q44 =
	      out_sfd__h377134;
      2'b11:
	  CASE_guard68386_0b0_sfdin76608_BITS_56_TO_34_0_ETC__q44 =
	      _theResult___sfd__h377131;
    endcase
  end
  always@(guard__h368386 or sfdin__h376608 or _theResult___sfd__h377131)
  begin
    case (guard__h368386)
      2'b0:
	  CASE_guard68386_0b0_sfdin76608_BITS_56_TO_34_0_ETC__q45 =
	      sfdin__h376608[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard68386_0b0_sfdin76608_BITS_56_TO_34_0_ETC__q45 =
	      _theResult___sfd__h377131;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  CASE_guard68386_0b0_sfdin76608_BITS_56_TO_34_0_ETC__q44 or
	  CASE_guard68386_0b0_sfdin76608_BITS_56_TO_34_0_ETC__q45 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5099 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5101 or
	  sfdin__h376608)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h377209 =
	      CASE_guard68386_0b0_sfdin76608_BITS_56_TO_34_0_ETC__q44;
      3'd1:
	  _theResult___fst_sfd__h377209 =
	      CASE_guard68386_0b0_sfdin76608_BITS_56_TO_34_0_ETC__q45;
      3'd2:
	  _theResult___fst_sfd__h377209 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5099;
      3'd3:
	  _theResult___fst_sfd__h377209 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5101;
      3'd4: _theResult___fst_sfd__h377209 = sfdin__h376608[56:34];
      default: _theResult___fst_sfd__h377209 = 23'd0;
    endcase
  end
  always@(guard__h377222 or
	  _theResult___snd__h385245 or
	  out_sfd__h385770 or _theResult___sfd__h385767)
  begin
    case (guard__h377222)
      2'b0, 2'b01:
	  CASE_guard77222_0b0_theResult___snd85245_BITS__ETC__q46 =
	      _theResult___snd__h385245[56:34];
      2'b10:
	  CASE_guard77222_0b0_theResult___snd85245_BITS__ETC__q46 =
	      out_sfd__h385770;
      2'b11:
	  CASE_guard77222_0b0_theResult___snd85245_BITS__ETC__q46 =
	      _theResult___sfd__h385767;
    endcase
  end
  always@(guard__h377222 or
	  _theResult___snd__h385245 or _theResult___sfd__h385767)
  begin
    case (guard__h377222)
      2'b0:
	  CASE_guard77222_0b0_theResult___snd85245_BITS__ETC__q47 =
	      _theResult___snd__h385245[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard77222_0b0_theResult___snd85245_BITS__ETC__q47 =
	      _theResult___sfd__h385767;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  CASE_guard77222_0b0_theResult___snd85245_BITS__ETC__q46 or
	  CASE_guard77222_0b0_theResult___snd85245_BITS__ETC__q47 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120 or
	  _theResult___snd__h385245)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h385845 =
	      CASE_guard77222_0b0_theResult___snd85245_BITS__ETC__q46;
      3'd1:
	  _theResult___fst_sfd__h385845 =
	      CASE_guard77222_0b0_theResult___snd85245_BITS__ETC__q47;
      3'd2:
	  _theResult___fst_sfd__h385845 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5118;
      3'd3:
	  _theResult___fst_sfd__h385845 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5120;
      3'd4: _theResult___fst_sfd__h385845 = _theResult___snd__h385245[56:34];
      default: _theResult___fst_sfd__h385845 = 23'd0;
    endcase
  end
  always@(guard__h350747 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (guard__h350747)
      2'b0, 2'b01, 2'b10:
	  CASE_guard50747_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      2'd3:
	  CASE_guard50747_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 =
	      guard__h350747 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
	  CASE_guard50747_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48 or
	  guard__h350747)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206 =
	      CASE_guard50747_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q48;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206 =
	      (guard__h350747 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		(guard__h350747 == 2'b01 || guard__h350747 == 2'b10 ||
		 guard__h350747 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5206 =
		   coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(guard__h350747 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (guard__h350747)
      2'b0, 2'b01, 2'b10:
	  CASE_guard50747_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      2'd3:
	  CASE_guard50747_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 =
	      guard__h350747 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
	  CASE_guard50747_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49 or
	  guard__h350747)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 =
	      CASE_guard50747_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q49;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 =
	      (guard__h350747 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		guard__h350747 != 2'b01 && guard__h350747 != 2'b10 &&
		guard__h350747 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5150 =
		   coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(guard__h359456 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (guard__h359456)
      2'b0, 2'b01, 2'b10:
	  CASE_guard59456_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      2'd3:
	  CASE_guard59456_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 =
	      guard__h359456 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
	  CASE_guard59456_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50 or
	  guard__h359456)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213 =
	      CASE_guard59456_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q50;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213 =
	      (guard__h359456 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		(guard__h359456 == 2'b01 || guard__h359456 == 2'b10 ||
		 guard__h359456 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5213 =
		   coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(guard__h359456 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (guard__h359456)
      2'b0, 2'b01, 2'b10:
	  CASE_guard59456_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      2'd3:
	  CASE_guard59456_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 =
	      guard__h359456 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
	  CASE_guard59456_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 or
	  guard__h359456)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163 =
	      CASE_guard59456_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163 =
	      (guard__h359456 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		guard__h359456 != 2'b01 && guard__h359456 != 2'b10 &&
		guard__h359456 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5163 =
		   coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(guard__h368386 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (guard__h368386)
      2'b0, 2'b01, 2'b10:
	  CASE_guard68386_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      2'd3:
	  CASE_guard68386_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 =
	      guard__h368386 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
	  CASE_guard68386_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 or
	  guard__h368386)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223 =
	      CASE_guard68386_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223 =
	      (guard__h368386 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		(guard__h368386 == 2'b01 || guard__h368386 == 2'b10 ||
		 guard__h368386 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5223 =
		   coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(guard__h368386 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (guard__h368386)
      2'b0, 2'b01, 2'b10:
	  CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      2'd3:
	  CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 =
	      guard__h368386 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
	  CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 or
	  guard__h368386)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180 =
	      CASE_guard68386_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180 =
	      (guard__h368386 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		guard__h368386 != 2'b01 && guard__h368386 != 2'b10 &&
		guard__h368386 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5180 =
		   coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(guard__h377222 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (guard__h377222)
      2'b0, 2'b01, 2'b10:
	  CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      2'd3:
	  CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 =
	      guard__h377222 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
	  CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 or
	  guard__h377222)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 =
	      CASE_guard77222_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 =
	      (guard__h377222 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		(guard__h377222 == 2'b01 || guard__h377222 == 2'b10 ||
		 guard__h377222 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5230 =
		   coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(guard__h377222 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (guard__h377222)
      2'b0, 2'b01, 2'b10:
	  CASE_guard77222_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      2'd3:
	  CASE_guard77222_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 =
	      guard__h377222 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
	  CASE_guard77222_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55 or
	  guard__h377222)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193 =
	      CASE_guard77222_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q55;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193 =
	      (guard__h377222 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
		guard__h377222 != 2'b01 && guard__h377222 != 2'b10 &&
		guard__h377222 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5193 =
		   coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
      3'd0, 3'd1, 3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5167 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5167 =
		   coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
    endcase
  end
  always@(guard__h405153 or
	  _theResult___fst_exp__h413201 or
	  out_exp__h413646 or _theResult___exp__h413643)
  begin
    case (guard__h405153)
      2'b0, 2'b01:
	  CASE_guard05153_0b0_theResult___fst_exp13201_0_ETC__q60 =
	      _theResult___fst_exp__h413201;
      2'b10:
	  CASE_guard05153_0b0_theResult___fst_exp13201_0_ETC__q60 =
	      out_exp__h413646;
      2'b11:
	  CASE_guard05153_0b0_theResult___fst_exp13201_0_ETC__q60 =
	      _theResult___exp__h413643;
    endcase
  end
  always@(guard__h405153 or
	  _theResult___fst_exp__h413201 or _theResult___exp__h413643)
  begin
    case (guard__h405153)
      2'b0:
	  CASE_guard05153_0b0_theResult___fst_exp13201_0_ETC__q61 =
	      _theResult___fst_exp__h413201;
      2'b01, 2'b10, 2'b11:
	  CASE_guard05153_0b0_theResult___fst_exp13201_0_ETC__q61 =
	      _theResult___exp__h413643;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  CASE_guard05153_0b0_theResult___fst_exp13201_0_ETC__q60 or
	  CASE_guard05153_0b0_theResult___fst_exp13201_0_ETC__q61 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6020 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6022 or
	  _theResult___fst_exp__h413201)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h413721 =
	      CASE_guard05153_0b0_theResult___fst_exp13201_0_ETC__q60;
      3'd1:
	  _theResult___fst_exp__h413721 =
	      CASE_guard05153_0b0_theResult___fst_exp13201_0_ETC__q61;
      3'd2:
	  _theResult___fst_exp__h413721 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6020;
      3'd3:
	  _theResult___fst_exp__h413721 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6022;
      3'd4: _theResult___fst_exp__h413721 = _theResult___fst_exp__h413201;
      default: _theResult___fst_exp__h413721 = 8'd0;
    endcase
  end
  always@(guard__h396446 or
	  _theResult___fst_exp__h404545 or
	  out_exp__h405064 or _theResult___exp__h405061)
  begin
    case (guard__h396446)
      2'b0, 2'b01:
	  CASE_guard96446_0b0_theResult___fst_exp04545_0_ETC__q62 =
	      _theResult___fst_exp__h404545;
      2'b10:
	  CASE_guard96446_0b0_theResult___fst_exp04545_0_ETC__q62 =
	      out_exp__h405064;
      2'b11:
	  CASE_guard96446_0b0_theResult___fst_exp04545_0_ETC__q62 =
	      _theResult___exp__h405061;
    endcase
  end
  always@(guard__h396446 or
	  _theResult___fst_exp__h404545 or _theResult___exp__h405061)
  begin
    case (guard__h396446)
      2'b0:
	  CASE_guard96446_0b0_theResult___fst_exp04545_0_ETC__q63 =
	      _theResult___fst_exp__h404545;
      2'b01, 2'b10, 2'b11:
	  CASE_guard96446_0b0_theResult___fst_exp04545_0_ETC__q63 =
	      _theResult___exp__h405061;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  CASE_guard96446_0b0_theResult___fst_exp04545_0_ETC__q62 or
	  CASE_guard96446_0b0_theResult___fst_exp04545_0_ETC__q63 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5798 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5801 or
	  _theResult___fst_exp__h404545)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h405139 =
	      CASE_guard96446_0b0_theResult___fst_exp04545_0_ETC__q62;
      3'd1:
	  _theResult___fst_exp__h405139 =
	      CASE_guard96446_0b0_theResult___fst_exp04545_0_ETC__q63;
      3'd2:
	  _theResult___fst_exp__h405139 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5798;
      3'd3:
	  _theResult___fst_exp__h405139 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5801;
      3'd4: _theResult___fst_exp__h405139 = _theResult___fst_exp__h404545;
      default: _theResult___fst_exp__h405139 = 8'd0;
    endcase
  end
  always@(guard__h414083 or
	  _theResult___fst_exp__h422311 or
	  out_exp__h422830 or _theResult___exp__h422827)
  begin
    case (guard__h414083)
      2'b0, 2'b01:
	  CASE_guard14083_0b0_theResult___fst_exp22311_0_ETC__q68 =
	      _theResult___fst_exp__h422311;
      2'b10:
	  CASE_guard14083_0b0_theResult___fst_exp22311_0_ETC__q68 =
	      out_exp__h422830;
      2'b11:
	  CASE_guard14083_0b0_theResult___fst_exp22311_0_ETC__q68 =
	      _theResult___exp__h422827;
    endcase
  end
  always@(guard__h414083 or
	  _theResult___fst_exp__h422311 or _theResult___exp__h422827)
  begin
    case (guard__h414083)
      2'b0:
	  CASE_guard14083_0b0_theResult___fst_exp22311_0_ETC__q69 =
	      _theResult___fst_exp__h422311;
      2'b01, 2'b10, 2'b11:
	  CASE_guard14083_0b0_theResult___fst_exp22311_0_ETC__q69 =
	      _theResult___exp__h422827;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  CASE_guard14083_0b0_theResult___fst_exp22311_0_ETC__q68 or
	  CASE_guard14083_0b0_theResult___fst_exp22311_0_ETC__q69 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6345 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6347 or
	  _theResult___fst_exp__h422311)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h422905 =
	      CASE_guard14083_0b0_theResult___fst_exp22311_0_ETC__q68;
      3'd1:
	  _theResult___fst_exp__h422905 =
	      CASE_guard14083_0b0_theResult___fst_exp22311_0_ETC__q69;
      3'd2:
	  _theResult___fst_exp__h422905 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6345;
      3'd3:
	  _theResult___fst_exp__h422905 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6347;
      3'd4: _theResult___fst_exp__h422905 = _theResult___fst_exp__h422311;
      default: _theResult___fst_exp__h422905 = 8'd0;
    endcase
  end
  always@(guard__h422919 or
	  _theResult___fst_exp__h430996 or
	  out_exp__h431466 or _theResult___exp__h431463)
  begin
    case (guard__h422919)
      2'b0, 2'b01:
	  CASE_guard22919_0b0_theResult___fst_exp30996_0_ETC__q73 =
	      _theResult___fst_exp__h430996;
      2'b10:
	  CASE_guard22919_0b0_theResult___fst_exp30996_0_ETC__q73 =
	      out_exp__h431466;
      2'b11:
	  CASE_guard22919_0b0_theResult___fst_exp30996_0_ETC__q73 =
	      _theResult___exp__h431463;
    endcase
  end
  always@(guard__h422919 or
	  _theResult___fst_exp__h430996 or _theResult___exp__h431463)
  begin
    case (guard__h422919)
      2'b0:
	  CASE_guard22919_0b0_theResult___fst_exp30996_0_ETC__q74 =
	      _theResult___fst_exp__h430996;
      2'b01, 2'b10, 2'b11:
	  CASE_guard22919_0b0_theResult___fst_exp30996_0_ETC__q74 =
	      _theResult___exp__h431463;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  CASE_guard22919_0b0_theResult___fst_exp30996_0_ETC__q73 or
	  CASE_guard22919_0b0_theResult___fst_exp30996_0_ETC__q74 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 or
	  _theResult___fst_exp__h430996)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h431541 =
	      CASE_guard22919_0b0_theResult___fst_exp30996_0_ETC__q73;
      3'd1:
	  _theResult___fst_exp__h431541 =
	      CASE_guard22919_0b0_theResult___fst_exp30996_0_ETC__q74;
      3'd2:
	  _theResult___fst_exp__h431541 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414;
      3'd3:
	  _theResult___fst_exp__h431541 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416;
      3'd4: _theResult___fst_exp__h431541 = _theResult___fst_exp__h430996;
      default: _theResult___fst_exp__h431541 = 8'd0;
    endcase
  end
  always@(guard__h405153 or
	  _theResult___snd__h413152 or
	  out_sfd__h413647 or _theResult___sfd__h413644)
  begin
    case (guard__h405153)
      2'b0, 2'b01:
	  CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q75 =
	      _theResult___snd__h413152[56:34];
      2'b10:
	  CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q75 =
	      out_sfd__h413647;
      2'b11:
	  CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q75 =
	      _theResult___sfd__h413644;
    endcase
  end
  always@(guard__h405153 or
	  _theResult___snd__h413152 or _theResult___sfd__h413644)
  begin
    case (guard__h405153)
      2'b0:
	  CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q76 =
	      _theResult___snd__h413152[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q76 =
	      _theResult___sfd__h413644;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q75 or
	  CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q76 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6466 or
	  _theResult___snd__h413152)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h413722 =
	      CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q75;
      3'd1:
	  _theResult___fst_sfd__h413722 =
	      CASE_guard05153_0b0_theResult___snd13152_BITS__ETC__q76;
      3'd2:
	  _theResult___fst_sfd__h413722 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6464;
      3'd3:
	  _theResult___fst_sfd__h413722 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6466;
      3'd4: _theResult___fst_sfd__h413722 = _theResult___snd__h413152[56:34];
      default: _theResult___fst_sfd__h413722 = 23'd0;
    endcase
  end
  always@(guard__h396446 or
	  sfdin__h404539 or out_sfd__h405065 or _theResult___sfd__h405062)
  begin
    case (guard__h396446)
      2'b0, 2'b01:
	  CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q77 =
	      sfdin__h404539[56:34];
      2'b10:
	  CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q77 =
	      out_sfd__h405065;
      2'b11:
	  CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q77 =
	      _theResult___sfd__h405062;
    endcase
  end
  always@(guard__h396446 or sfdin__h404539 or _theResult___sfd__h405062)
  begin
    case (guard__h396446)
      2'b0:
	  CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q78 =
	      sfdin__h404539[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q78 =
	      _theResult___sfd__h405062;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q77 or
	  CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q78 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447 or
	  sfdin__h404539)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h405140 =
	      CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q77;
      3'd1:
	  _theResult___fst_sfd__h405140 =
	      CASE_guard96446_0b0_sfdin04539_BITS_56_TO_34_0_ETC__q78;
      3'd2:
	  _theResult___fst_sfd__h405140 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6445;
      3'd3:
	  _theResult___fst_sfd__h405140 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6447;
      3'd4: _theResult___fst_sfd__h405140 = sfdin__h404539[56:34];
      default: _theResult___fst_sfd__h405140 = 23'd0;
    endcase
  end
  always@(guard__h414083 or
	  sfdin__h422305 or out_sfd__h422831 or _theResult___sfd__h422828)
  begin
    case (guard__h414083)
      2'b0, 2'b01:
	  CASE_guard14083_0b0_sfdin22305_BITS_56_TO_34_0_ETC__q79 =
	      sfdin__h422305[56:34];
      2'b10:
	  CASE_guard14083_0b0_sfdin22305_BITS_56_TO_34_0_ETC__q79 =
	      out_sfd__h422831;
      2'b11:
	  CASE_guard14083_0b0_sfdin22305_BITS_56_TO_34_0_ETC__q79 =
	      _theResult___sfd__h422828;
    endcase
  end
  always@(guard__h414083 or sfdin__h422305 or _theResult___sfd__h422828)
  begin
    case (guard__h414083)
      2'b0:
	  CASE_guard14083_0b0_sfdin22305_BITS_56_TO_34_0_ETC__q80 =
	      sfdin__h422305[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard14083_0b0_sfdin22305_BITS_56_TO_34_0_ETC__q80 =
	      _theResult___sfd__h422828;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  CASE_guard14083_0b0_sfdin22305_BITS_56_TO_34_0_ETC__q79 or
	  CASE_guard14083_0b0_sfdin22305_BITS_56_TO_34_0_ETC__q80 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6491 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6493 or
	  sfdin__h422305)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h422906 =
	      CASE_guard14083_0b0_sfdin22305_BITS_56_TO_34_0_ETC__q79;
      3'd1:
	  _theResult___fst_sfd__h422906 =
	      CASE_guard14083_0b0_sfdin22305_BITS_56_TO_34_0_ETC__q80;
      3'd2:
	  _theResult___fst_sfd__h422906 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6491;
      3'd3:
	  _theResult___fst_sfd__h422906 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6493;
      3'd4: _theResult___fst_sfd__h422906 = sfdin__h422305[56:34];
      default: _theResult___fst_sfd__h422906 = 23'd0;
    endcase
  end
  always@(guard__h422919 or
	  _theResult___snd__h430942 or
	  out_sfd__h431467 or _theResult___sfd__h431464)
  begin
    case (guard__h422919)
      2'b0, 2'b01:
	  CASE_guard22919_0b0_theResult___snd30942_BITS__ETC__q81 =
	      _theResult___snd__h430942[56:34];
      2'b10:
	  CASE_guard22919_0b0_theResult___snd30942_BITS__ETC__q81 =
	      out_sfd__h431467;
      2'b11:
	  CASE_guard22919_0b0_theResult___snd30942_BITS__ETC__q81 =
	      _theResult___sfd__h431464;
    endcase
  end
  always@(guard__h422919 or
	  _theResult___snd__h430942 or _theResult___sfd__h431464)
  begin
    case (guard__h422919)
      2'b0:
	  CASE_guard22919_0b0_theResult___snd30942_BITS__ETC__q82 =
	      _theResult___snd__h430942[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard22919_0b0_theResult___snd30942_BITS__ETC__q82 =
	      _theResult___sfd__h431464;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  CASE_guard22919_0b0_theResult___snd30942_BITS__ETC__q81 or
	  CASE_guard22919_0b0_theResult___snd30942_BITS__ETC__q82 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6510 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6512 or
	  _theResult___snd__h430942)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h431542 =
	      CASE_guard22919_0b0_theResult___snd30942_BITS__ETC__q81;
      3'd1:
	  _theResult___fst_sfd__h431542 =
	      CASE_guard22919_0b0_theResult___snd30942_BITS__ETC__q82;
      3'd2:
	  _theResult___fst_sfd__h431542 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6510;
      3'd3:
	  _theResult___fst_sfd__h431542 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6512;
      3'd4: _theResult___fst_sfd__h431542 = _theResult___snd__h430942[56:34];
      default: _theResult___fst_sfd__h431542 = 23'd0;
    endcase
  end
  always@(guard__h396446 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (guard__h396446)
      2'b0, 2'b01, 2'b10:
	  CASE_guard96446_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      2'd3:
	  CASE_guard96446_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 =
	      guard__h396446 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
	  CASE_guard96446_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 or
	  guard__h396446)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598 =
	      CASE_guard96446_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598 =
	      (guard__h396446 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		(guard__h396446 == 2'b01 || guard__h396446 == 2'b10 ||
		 guard__h396446 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6598 =
		   coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(guard__h396446 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (guard__h396446)
      2'b0, 2'b01, 2'b10:
	  CASE_guard96446_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      2'd3:
	  CASE_guard96446_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 =
	      guard__h396446 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
	  CASE_guard96446_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84 or
	  guard__h396446)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 =
	      CASE_guard96446_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q84;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 =
	      (guard__h396446 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		guard__h396446 != 2'b01 && guard__h396446 != 2'b10 &&
		guard__h396446 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6542 =
		   coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(guard__h405153 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (guard__h405153)
      2'b0, 2'b01, 2'b10:
	  CASE_guard05153_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      2'd3:
	  CASE_guard05153_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 =
	      guard__h405153 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
	  CASE_guard05153_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85 or
	  guard__h405153)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 =
	      CASE_guard05153_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q85;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 =
	      (guard__h405153 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		(guard__h405153 == 2'b01 || guard__h405153 == 2'b10 ||
		 guard__h405153 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6605 =
		   coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(guard__h405153 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (guard__h405153)
      2'b0, 2'b01, 2'b10:
	  CASE_guard05153_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      2'd3:
	  CASE_guard05153_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 =
	      guard__h405153 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
	  CASE_guard05153_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86 or
	  guard__h405153)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555 =
	      CASE_guard05153_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q86;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555 =
	      (guard__h405153 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		guard__h405153 != 2'b01 && guard__h405153 != 2'b10 &&
		guard__h405153 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6555 =
		   coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(guard__h414083 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (guard__h414083)
      2'b0, 2'b01, 2'b10:
	  CASE_guard14083_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      2'd3:
	  CASE_guard14083_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 =
	      guard__h414083 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
	  CASE_guard14083_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87 or
	  guard__h414083)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615 =
	      CASE_guard14083_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q87;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615 =
	      (guard__h414083 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		(guard__h414083 == 2'b01 || guard__h414083 == 2'b10 ||
		 guard__h414083 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6615 =
		   coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(guard__h414083 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (guard__h414083)
      2'b0, 2'b01, 2'b10:
	  CASE_guard14083_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      2'd3:
	  CASE_guard14083_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 =
	      guard__h414083 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
	  CASE_guard14083_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88 or
	  guard__h414083)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 =
	      CASE_guard14083_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q88;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 =
	      (guard__h414083 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		guard__h414083 != 2'b01 && guard__h414083 != 2'b10 &&
		guard__h414083 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6572 =
		   coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(guard__h422919 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (guard__h422919)
      2'b0, 2'b01, 2'b10:
	  CASE_guard22919_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      2'd3:
	  CASE_guard22919_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 =
	      guard__h422919 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
	  CASE_guard22919_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89 or
	  guard__h422919)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622 =
	      CASE_guard22919_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q89;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622 =
	      (guard__h422919 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		(guard__h422919 == 2'b01 || guard__h422919 == 2'b10 ||
		 guard__h422919 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6622 =
		   coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(guard__h422919 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (guard__h422919)
      2'b0, 2'b01, 2'b10:
	  CASE_guard22919_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      2'd3:
	  CASE_guard22919_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 =
	      guard__h422919 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
	  CASE_guard22919_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90 or
	  guard__h422919)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585 =
	      CASE_guard22919_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q90;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585 =
	      (guard__h422919 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
		guard__h422919 != 2'b01 && guard__h422919 != 2'b10 &&
		guard__h422919 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6585 =
		   coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0, 3'd1, 3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6608 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6608 =
		   coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
      3'd0, 3'd1, 3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6559 =
		   coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
    endcase
  end
  always@(guard__h450848 or
	  _theResult___fst_exp__h458896 or
	  out_exp__h459341 or _theResult___exp__h459338)
  begin
    case (guard__h450848)
      2'b0, 2'b01:
	  CASE_guard50848_0b0_theResult___fst_exp58896_0_ETC__q95 =
	      _theResult___fst_exp__h458896;
      2'b10:
	  CASE_guard50848_0b0_theResult___fst_exp58896_0_ETC__q95 =
	      out_exp__h459341;
      2'b11:
	  CASE_guard50848_0b0_theResult___fst_exp58896_0_ETC__q95 =
	      _theResult___exp__h459338;
    endcase
  end
  always@(guard__h450848 or
	  _theResult___fst_exp__h458896 or _theResult___exp__h459338)
  begin
    case (guard__h450848)
      2'b0:
	  CASE_guard50848_0b0_theResult___fst_exp58896_0_ETC__q96 =
	      _theResult___fst_exp__h458896;
      2'b01, 2'b10, 2'b11:
	  CASE_guard50848_0b0_theResult___fst_exp58896_0_ETC__q96 =
	      _theResult___exp__h459338;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  CASE_guard50848_0b0_theResult___fst_exp58896_0_ETC__q95 or
	  CASE_guard50848_0b0_theResult___fst_exp58896_0_ETC__q96 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7412 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7414 or
	  _theResult___fst_exp__h458896)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h459416 =
	      CASE_guard50848_0b0_theResult___fst_exp58896_0_ETC__q95;
      3'd1:
	  _theResult___fst_exp__h459416 =
	      CASE_guard50848_0b0_theResult___fst_exp58896_0_ETC__q96;
      3'd2:
	  _theResult___fst_exp__h459416 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7412;
      3'd3:
	  _theResult___fst_exp__h459416 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7414;
      3'd4: _theResult___fst_exp__h459416 = _theResult___fst_exp__h458896;
      default: _theResult___fst_exp__h459416 = 8'd0;
    endcase
  end
  always@(guard__h442141 or
	  _theResult___fst_exp__h450240 or
	  out_exp__h450759 or _theResult___exp__h450756)
  begin
    case (guard__h442141)
      2'b0, 2'b01:
	  CASE_guard42141_0b0_theResult___fst_exp50240_0_ETC__q97 =
	      _theResult___fst_exp__h450240;
      2'b10:
	  CASE_guard42141_0b0_theResult___fst_exp50240_0_ETC__q97 =
	      out_exp__h450759;
      2'b11:
	  CASE_guard42141_0b0_theResult___fst_exp50240_0_ETC__q97 =
	      _theResult___exp__h450756;
    endcase
  end
  always@(guard__h442141 or
	  _theResult___fst_exp__h450240 or _theResult___exp__h450756)
  begin
    case (guard__h442141)
      2'b0:
	  CASE_guard42141_0b0_theResult___fst_exp50240_0_ETC__q98 =
	      _theResult___fst_exp__h450240;
      2'b01, 2'b10, 2'b11:
	  CASE_guard42141_0b0_theResult___fst_exp50240_0_ETC__q98 =
	      _theResult___exp__h450756;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  CASE_guard42141_0b0_theResult___fst_exp50240_0_ETC__q97 or
	  CASE_guard42141_0b0_theResult___fst_exp50240_0_ETC__q98 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7190 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7193 or
	  _theResult___fst_exp__h450240)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h450834 =
	      CASE_guard42141_0b0_theResult___fst_exp50240_0_ETC__q97;
      3'd1:
	  _theResult___fst_exp__h450834 =
	      CASE_guard42141_0b0_theResult___fst_exp50240_0_ETC__q98;
      3'd2:
	  _theResult___fst_exp__h450834 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7190;
      3'd3:
	  _theResult___fst_exp__h450834 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7193;
      3'd4: _theResult___fst_exp__h450834 = _theResult___fst_exp__h450240;
      default: _theResult___fst_exp__h450834 = 8'd0;
    endcase
  end
  always@(guard__h459778 or
	  _theResult___fst_exp__h468006 or
	  out_exp__h468525 or _theResult___exp__h468522)
  begin
    case (guard__h459778)
      2'b0, 2'b01:
	  CASE_guard59778_0b0_theResult___fst_exp68006_0_ETC__q103 =
	      _theResult___fst_exp__h468006;
      2'b10:
	  CASE_guard59778_0b0_theResult___fst_exp68006_0_ETC__q103 =
	      out_exp__h468525;
      2'b11:
	  CASE_guard59778_0b0_theResult___fst_exp68006_0_ETC__q103 =
	      _theResult___exp__h468522;
    endcase
  end
  always@(guard__h459778 or
	  _theResult___fst_exp__h468006 or _theResult___exp__h468522)
  begin
    case (guard__h459778)
      2'b0:
	  CASE_guard59778_0b0_theResult___fst_exp68006_0_ETC__q104 =
	      _theResult___fst_exp__h468006;
      2'b01, 2'b10, 2'b11:
	  CASE_guard59778_0b0_theResult___fst_exp68006_0_ETC__q104 =
	      _theResult___exp__h468522;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  CASE_guard59778_0b0_theResult___fst_exp68006_0_ETC__q103 or
	  CASE_guard59778_0b0_theResult___fst_exp68006_0_ETC__q104 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7737 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7739 or
	  _theResult___fst_exp__h468006)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h468600 =
	      CASE_guard59778_0b0_theResult___fst_exp68006_0_ETC__q103;
      3'd1:
	  _theResult___fst_exp__h468600 =
	      CASE_guard59778_0b0_theResult___fst_exp68006_0_ETC__q104;
      3'd2:
	  _theResult___fst_exp__h468600 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7737;
      3'd3:
	  _theResult___fst_exp__h468600 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7739;
      3'd4: _theResult___fst_exp__h468600 = _theResult___fst_exp__h468006;
      default: _theResult___fst_exp__h468600 = 8'd0;
    endcase
  end
  always@(guard__h468614 or
	  _theResult___fst_exp__h476691 or
	  out_exp__h477161 or _theResult___exp__h477158)
  begin
    case (guard__h468614)
      2'b0, 2'b01:
	  CASE_guard68614_0b0_theResult___fst_exp76691_0_ETC__q108 =
	      _theResult___fst_exp__h476691;
      2'b10:
	  CASE_guard68614_0b0_theResult___fst_exp76691_0_ETC__q108 =
	      out_exp__h477161;
      2'b11:
	  CASE_guard68614_0b0_theResult___fst_exp76691_0_ETC__q108 =
	      _theResult___exp__h477158;
    endcase
  end
  always@(guard__h468614 or
	  _theResult___fst_exp__h476691 or _theResult___exp__h477158)
  begin
    case (guard__h468614)
      2'b0:
	  CASE_guard68614_0b0_theResult___fst_exp76691_0_ETC__q109 =
	      _theResult___fst_exp__h476691;
      2'b01, 2'b10, 2'b11:
	  CASE_guard68614_0b0_theResult___fst_exp76691_0_ETC__q109 =
	      _theResult___exp__h477158;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  CASE_guard68614_0b0_theResult___fst_exp76691_0_ETC__q108 or
	  CASE_guard68614_0b0_theResult___fst_exp76691_0_ETC__q109 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 or
	  _theResult___fst_exp__h476691)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  _theResult___fst_exp__h477236 =
	      CASE_guard68614_0b0_theResult___fst_exp76691_0_ETC__q108;
      3'd1:
	  _theResult___fst_exp__h477236 =
	      CASE_guard68614_0b0_theResult___fst_exp76691_0_ETC__q109;
      3'd2:
	  _theResult___fst_exp__h477236 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806;
      3'd3:
	  _theResult___fst_exp__h477236 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808;
      3'd4: _theResult___fst_exp__h477236 = _theResult___fst_exp__h476691;
      default: _theResult___fst_exp__h477236 = 8'd0;
    endcase
  end
  always@(guard__h450848 or
	  _theResult___snd__h458847 or
	  out_sfd__h459342 or _theResult___sfd__h459339)
  begin
    case (guard__h450848)
      2'b0, 2'b01:
	  CASE_guard50848_0b0_theResult___snd58847_BITS__ETC__q110 =
	      _theResult___snd__h458847[56:34];
      2'b10:
	  CASE_guard50848_0b0_theResult___snd58847_BITS__ETC__q110 =
	      out_sfd__h459342;
      2'b11:
	  CASE_guard50848_0b0_theResult___snd58847_BITS__ETC__q110 =
	      _theResult___sfd__h459339;
    endcase
  end
  always@(guard__h450848 or
	  _theResult___snd__h458847 or _theResult___sfd__h459339)
  begin
    case (guard__h450848)
      2'b0:
	  CASE_guard50848_0b0_theResult___snd58847_BITS__ETC__q111 =
	      _theResult___snd__h458847[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard50848_0b0_theResult___snd58847_BITS__ETC__q111 =
	      _theResult___sfd__h459339;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  CASE_guard50848_0b0_theResult___snd58847_BITS__ETC__q110 or
	  CASE_guard50848_0b0_theResult___snd58847_BITS__ETC__q111 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7856 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858 or
	  _theResult___snd__h458847)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h459417 =
	      CASE_guard50848_0b0_theResult___snd58847_BITS__ETC__q110;
      3'd1:
	  _theResult___fst_sfd__h459417 =
	      CASE_guard50848_0b0_theResult___snd58847_BITS__ETC__q111;
      3'd2:
	  _theResult___fst_sfd__h459417 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7856;
      3'd3:
	  _theResult___fst_sfd__h459417 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7858;
      3'd4: _theResult___fst_sfd__h459417 = _theResult___snd__h458847[56:34];
      default: _theResult___fst_sfd__h459417 = 23'd0;
    endcase
  end
  always@(guard__h442141 or
	  sfdin__h450234 or out_sfd__h450760 or _theResult___sfd__h450757)
  begin
    case (guard__h442141)
      2'b0, 2'b01:
	  CASE_guard42141_0b0_sfdin50234_BITS_56_TO_34_0_ETC__q112 =
	      sfdin__h450234[56:34];
      2'b10:
	  CASE_guard42141_0b0_sfdin50234_BITS_56_TO_34_0_ETC__q112 =
	      out_sfd__h450760;
      2'b11:
	  CASE_guard42141_0b0_sfdin50234_BITS_56_TO_34_0_ETC__q112 =
	      _theResult___sfd__h450757;
    endcase
  end
  always@(guard__h442141 or sfdin__h450234 or _theResult___sfd__h450757)
  begin
    case (guard__h442141)
      2'b0:
	  CASE_guard42141_0b0_sfdin50234_BITS_56_TO_34_0_ETC__q113 =
	      sfdin__h450234[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard42141_0b0_sfdin50234_BITS_56_TO_34_0_ETC__q113 =
	      _theResult___sfd__h450757;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  CASE_guard42141_0b0_sfdin50234_BITS_56_TO_34_0_ETC__q112 or
	  CASE_guard42141_0b0_sfdin50234_BITS_56_TO_34_0_ETC__q113 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7837 or
	  IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7839 or
	  sfdin__h450234)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h450835 =
	      CASE_guard42141_0b0_sfdin50234_BITS_56_TO_34_0_ETC__q112;
      3'd1:
	  _theResult___fst_sfd__h450835 =
	      CASE_guard42141_0b0_sfdin50234_BITS_56_TO_34_0_ETC__q113;
      3'd2:
	  _theResult___fst_sfd__h450835 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7837;
      3'd3:
	  _theResult___fst_sfd__h450835 =
	      IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7839;
      3'd4: _theResult___fst_sfd__h450835 = sfdin__h450234[56:34];
      default: _theResult___fst_sfd__h450835 = 23'd0;
    endcase
  end
  always@(guard__h459778 or
	  sfdin__h468000 or out_sfd__h468526 or _theResult___sfd__h468523)
  begin
    case (guard__h459778)
      2'b0, 2'b01:
	  CASE_guard59778_0b0_sfdin68000_BITS_56_TO_34_0_ETC__q114 =
	      sfdin__h468000[56:34];
      2'b10:
	  CASE_guard59778_0b0_sfdin68000_BITS_56_TO_34_0_ETC__q114 =
	      out_sfd__h468526;
      2'b11:
	  CASE_guard59778_0b0_sfdin68000_BITS_56_TO_34_0_ETC__q114 =
	      _theResult___sfd__h468523;
    endcase
  end
  always@(guard__h459778 or sfdin__h468000 or _theResult___sfd__h468523)
  begin
    case (guard__h459778)
      2'b0:
	  CASE_guard59778_0b0_sfdin68000_BITS_56_TO_34_0_ETC__q115 =
	      sfdin__h468000[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard59778_0b0_sfdin68000_BITS_56_TO_34_0_ETC__q115 =
	      _theResult___sfd__h468523;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  CASE_guard59778_0b0_sfdin68000_BITS_56_TO_34_0_ETC__q114 or
	  CASE_guard59778_0b0_sfdin68000_BITS_56_TO_34_0_ETC__q115 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7883 or
	  IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7885 or
	  sfdin__h468000)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h468601 =
	      CASE_guard59778_0b0_sfdin68000_BITS_56_TO_34_0_ETC__q114;
      3'd1:
	  _theResult___fst_sfd__h468601 =
	      CASE_guard59778_0b0_sfdin68000_BITS_56_TO_34_0_ETC__q115;
      3'd2:
	  _theResult___fst_sfd__h468601 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7883;
      3'd3:
	  _theResult___fst_sfd__h468601 =
	      IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7885;
      3'd4: _theResult___fst_sfd__h468601 = sfdin__h468000[56:34];
      default: _theResult___fst_sfd__h468601 = 23'd0;
    endcase
  end
  always@(guard__h468614 or
	  _theResult___snd__h476637 or
	  out_sfd__h477162 or _theResult___sfd__h477159)
  begin
    case (guard__h468614)
      2'b0, 2'b01:
	  CASE_guard68614_0b0_theResult___snd76637_BITS__ETC__q116 =
	      _theResult___snd__h476637[56:34];
      2'b10:
	  CASE_guard68614_0b0_theResult___snd76637_BITS__ETC__q116 =
	      out_sfd__h477162;
      2'b11:
	  CASE_guard68614_0b0_theResult___snd76637_BITS__ETC__q116 =
	      _theResult___sfd__h477159;
    endcase
  end
  always@(guard__h468614 or
	  _theResult___snd__h476637 or _theResult___sfd__h477159)
  begin
    case (guard__h468614)
      2'b0:
	  CASE_guard68614_0b0_theResult___snd76637_BITS__ETC__q117 =
	      _theResult___snd__h476637[56:34];
      2'b01, 2'b10, 2'b11:
	  CASE_guard68614_0b0_theResult___snd76637_BITS__ETC__q117 =
	      _theResult___sfd__h477159;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  CASE_guard68614_0b0_theResult___snd76637_BITS__ETC__q116 or
	  CASE_guard68614_0b0_theResult___snd76637_BITS__ETC__q117 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902 or
	  IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904 or
	  _theResult___snd__h476637)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  _theResult___fst_sfd__h477237 =
	      CASE_guard68614_0b0_theResult___snd76637_BITS__ETC__q116;
      3'd1:
	  _theResult___fst_sfd__h477237 =
	      CASE_guard68614_0b0_theResult___snd76637_BITS__ETC__q117;
      3'd2:
	  _theResult___fst_sfd__h477237 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7902;
      3'd3:
	  _theResult___fst_sfd__h477237 =
	      IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7904;
      3'd4: _theResult___fst_sfd__h477237 = _theResult___snd__h476637[56:34];
      default: _theResult___fst_sfd__h477237 = 23'd0;
    endcase
  end
  always@(guard__h442141 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (guard__h442141)
      2'b0, 2'b01, 2'b10:
	  CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      2'd3:
	  CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 =
	      guard__h442141 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
	  CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 or
	  guard__h442141)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 =
	      CASE_guard42141_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 =
	      (guard__h442141 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		guard__h442141 != 2'b01 && guard__h442141 != 2'b10 &&
		guard__h442141 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7934 =
		   coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(guard__h442141 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (guard__h442141)
      2'b0, 2'b01, 2'b10:
	  CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      2'd3:
	  CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 =
	      guard__h442141 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
	  CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 or
	  guard__h442141)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 =
	      CASE_guard42141_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 =
	      (guard__h442141 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		(guard__h442141 == 2'b01 || guard__h442141 == 2'b10 ||
		 guard__h442141 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7990 =
		   coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(guard__h450848 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (guard__h450848)
      2'b0, 2'b01, 2'b10:
	  CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      2'd3:
	  CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 =
	      guard__h450848 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
	  CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120 or
	  guard__h450848)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 =
	      CASE_guard50848_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q120;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 =
	      (guard__h450848 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		(guard__h450848 == 2'b01 || guard__h450848 == 2'b10 ||
		 guard__h450848 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7997 =
		   coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(guard__h450848 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (guard__h450848)
      2'b0, 2'b01, 2'b10:
	  CASE_guard50848_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      2'd3:
	  CASE_guard50848_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 =
	      guard__h450848 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
	  CASE_guard50848_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121 or
	  guard__h450848)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947 =
	      CASE_guard50848_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q121;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947 =
	      (guard__h450848 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		guard__h450848 != 2'b01 && guard__h450848 != 2'b10 &&
		guard__h450848 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7947 =
		   coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(guard__h459778 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (guard__h459778)
      2'b0, 2'b01, 2'b10:
	  CASE_guard59778_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      2'd3:
	  CASE_guard59778_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 =
	      guard__h459778 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
	  CASE_guard59778_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122 or
	  guard__h459778)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007 =
	      CASE_guard59778_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q122;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007 =
	      (guard__h459778 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		(guard__h459778 == 2'b01 || guard__h459778 == 2'b10 ||
		 guard__h459778 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8007 =
		   coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(guard__h459778 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (guard__h459778)
      2'b0, 2'b01, 2'b10:
	  CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      2'd3:
	  CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 =
	      guard__h459778 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
	  CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123 or
	  guard__h459778)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964 =
	      CASE_guard59778_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q123;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964 =
	      (guard__h459778 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		guard__h459778 != 2'b01 && guard__h459778 != 2'b10 &&
		guard__h459778 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7964 =
		   coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(guard__h468614 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (guard__h468614)
      2'b0, 2'b01, 2'b10:
	  CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      2'd3:
	  CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 =
	      guard__h468614 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
	  CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124 or
	  guard__h468614)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 =
	      CASE_guard68614_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q124;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 =
	      (guard__h468614 == 2'b0) ?
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		(guard__h468614 == 2'b01 || guard__h468614 == 2'b10 ||
		 guard__h468614 == 2'b11) &&
		coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8014 =
		   coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(guard__h468614 or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (guard__h468614)
      2'b0, 2'b01, 2'b10:
	  CASE_guard68614_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      2'd3:
	  CASE_guard68614_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 =
	      guard__h468614 != 2'b11 ||
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
	  CASE_guard68614_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 or
	  guard__h468614)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977 =
	      CASE_guard68614_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125;
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977 =
	      (guard__h468614 == 2'b0) ?
		!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
		guard__h468614 != 2'b01 && guard__h468614 != 2'b10 &&
		guard__h468614 != 2'b11 ||
		!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7977 =
		   coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0, 3'd1, 3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8000 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d8000 =
		   coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
		   3'd4 &&
		   coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
  begin
    case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
      3'd0, 3'd1, 3'd2, 3'd3:
	  IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7951 =
	      !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
      default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7951 =
		   coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
		   3'd4 ||
		   !coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put or
	  coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put or
	  coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
      5'd0, 5'd1, 5'd2, 5'd25, 5'd26, 5'd27:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8507 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put;
      5'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8507 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put;
      5'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8507 =
	      coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8507 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd28 ||
		   coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put;
    endcase
  end
  always@(guard__h498955 or
	  _theResult___fst_exp__h506916 or _theResult___exp__h507571)
  begin
    case (guard__h498955)
      2'b0:
	  CASE_guard98955_0b0_theResult___fst_exp06916_0_ETC__q135 =
	      _theResult___fst_exp__h506916;
      2'b01, 2'b10, 2'b11:
	  CASE_guard98955_0b0_theResult___fst_exp06916_0_ETC__q135 =
	      _theResult___exp__h507571;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___fst_exp__h506916 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9126 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9124 or
	  CASE_guard98955_0b0_theResult___fst_exp06916_0_ETC__q135)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 =
	      _theResult___fst_exp__h506916;
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9126;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9124;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 =
	      CASE_guard98955_0b0_theResult___fst_exp06916_0_ETC__q135;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9130 =
		   11'd0;
    endcase
  end
  always@(guard__h498955 or
	  _theResult___fst_exp__h506916 or
	  out_exp__h507574 or _theResult___exp__h507571)
  begin
    case (guard__h498955)
      2'b0, 2'b01:
	  CASE_guard98955_0b0_theResult___fst_exp06916_0_ETC__q136 =
	      _theResult___fst_exp__h506916;
      2'b10:
	  CASE_guard98955_0b0_theResult___fst_exp06916_0_ETC__q136 =
	      out_exp__h507574;
      2'b11:
	  CASE_guard98955_0b0_theResult___fst_exp06916_0_ETC__q136 =
	      _theResult___exp__h507571;
    endcase
  end
  always@(guard__h498955 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h498955)
      2'b0, 2'b01, 2'b10:
	  CASE_guard98955_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171];
      2'd3:
	  CASE_guard98955_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 =
	      guard__h498955 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h498955)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 =
	      (guard__h498955 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
		(guard__h498955 == 2'b01 || guard__h498955 == 2'b10 ||
		 guard__h498955 == 2'b11) &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[171];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		   32'hFFFFFFFF &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[171];
    endcase
  end
  always@(guard__h508267 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h508267)
      2'b0, 2'b01, 2'b10:
	  CASE_guard08267_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171];
      2'd3:
	  CASE_guard08267_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 =
	      guard__h508267 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h508267)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 =
	      (guard__h508267 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
		(guard__h508267 == 2'b01 || guard__h508267 == 2'b10 ||
		 guard__h508267 == 2'b11) &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[171];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		   32'hFFFFFFFF &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[171];
    endcase
  end
  always@(guard__h517336 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h517336)
      2'b0, 2'b01, 2'b10:
	  CASE_guard17336_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171];
      2'd3:
	  CASE_guard17336_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 =
	      guard__h517336 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h517336)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[171];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 =
	      (guard__h517336 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
		(guard__h517336 == 2'b01 || guard__h517336 == 2'b10 ||
		 guard__h517336 == 2'b11) &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[171];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
		   32'hFFFFFFFF &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[171];
    endcase
  end
  always@(guard__h577112 or
	  _theResult___fst_exp__h585073 or _theResult___exp__h585728)
  begin
    case (guard__h577112)
      2'b0:
	  CASE_guard77112_0b0_theResult___fst_exp85073_0_ETC__q152 =
	      _theResult___fst_exp__h585073;
      2'b01, 2'b10, 2'b11:
	  CASE_guard77112_0b0_theResult___fst_exp85073_0_ETC__q152 =
	      _theResult___exp__h585728;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___fst_exp__h585073 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9841 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9839 or
	  CASE_guard77112_0b0_theResult___fst_exp85073_0_ETC__q152)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 =
	      _theResult___fst_exp__h585073;
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9841;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9839;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 =
	      CASE_guard77112_0b0_theResult___fst_exp85073_0_ETC__q152;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9845 =
		   11'd0;
    endcase
  end
  always@(guard__h577112 or
	  _theResult___fst_exp__h585073 or
	  out_exp__h585731 or _theResult___exp__h585728)
  begin
    case (guard__h577112)
      2'b0, 2'b01:
	  CASE_guard77112_0b0_theResult___fst_exp85073_0_ETC__q153 =
	      _theResult___fst_exp__h585073;
      2'b10:
	  CASE_guard77112_0b0_theResult___fst_exp85073_0_ETC__q153 =
	      out_exp__h585731;
      2'b11:
	  CASE_guard77112_0b0_theResult___fst_exp85073_0_ETC__q153 =
	      _theResult___exp__h585728;
    endcase
  end
  always@(guard__h586424 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h586424)
      2'b0, 2'b01, 2'b10:
	  CASE_guard86424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      2'd3:
	  CASE_guard86424_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 =
	      guard__h586424 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h586424)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 =
	      (guard__h586424 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
		(guard__h586424 == 2'b01 || guard__h586424 == 2'b10 ||
		 guard__h586424 == 2'b11) &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		   32'hFFFFFFFF &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(guard__h577112 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h577112)
      2'b0, 2'b01, 2'b10:
	  CASE_guard77112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      2'd3:
	  CASE_guard77112_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 =
	      guard__h577112 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h577112)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 =
	      (guard__h577112 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
		(guard__h577112 == 2'b01 || guard__h577112 == 2'b10 ||
		 guard__h577112 == 2'b11) &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		   32'hFFFFFFFF &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(guard__h595493 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h595493)
      2'b0, 2'b01, 2'b10:
	  CASE_guard95493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      2'd3:
	  CASE_guard95493_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 =
	      guard__h595493 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595493)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 =
	      (guard__h595493 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
		(guard__h595493 == 2'b01 || guard__h595493 == 2'b10 ||
		 guard__h595493 == 2'b11) &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
		   32'hFFFFFFFF &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(guard__h586424 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h586424)
      2'b0, 2'b01, 2'b10:
	  CASE_guard86424_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      2'd3:
	  CASE_guard86424_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 =
	      guard__h586424 != 2'b11 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h586424)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 =
	      (guard__h586424 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
		guard__h586424 != 2'b01 && guard__h586424 != 2'b10 &&
		guard__h586424 != 2'b11 ||
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
		   coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
		   32'hFFFFFFFF ||
		   !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(guard__h577112 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h577112)
      2'b0, 2'b01, 2'b10:
	  CASE_guard77112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      2'd3:
	  CASE_guard77112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 =
	      guard__h577112 != 2'b11 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h577112)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 =
	      (guard__h577112 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
		guard__h577112 != 2'b01 && guard__h577112 != 2'b10 &&
		guard__h577112 != 2'b11 ||
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
		   coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
		   32'hFFFFFFFF ||
		   !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(guard__h595493 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h595493)
      2'b0, 2'b01, 2'b10:
	  CASE_guard95493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      2'd3:
	  CASE_guard95493_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 =
	      guard__h595493 != 2'b11 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h595493)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 =
	      (guard__h595493 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
		guard__h595493 != 2'b01 && guard__h595493 != 2'b10 &&
		guard__h595493 != 2'b11 ||
		coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
		   coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
		   32'hFFFFFFFF ||
		   !coreFix_fpuMulDivExe_0_regToExeQ$first[43];
    endcase
  end
  always@(guard__h537808 or
	  _theResult___fst_exp__h545769 or _theResult___exp__h546424)
  begin
    case (guard__h537808)
      2'b0:
	  CASE_guard37808_0b0_theResult___fst_exp45769_0_ETC__q175 =
	      _theResult___fst_exp__h545769;
      2'b01, 2'b10, 2'b11:
	  CASE_guard37808_0b0_theResult___fst_exp45769_0_ETC__q175 =
	      _theResult___exp__h546424;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___fst_exp__h545769 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10611 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10609 or
	  CASE_guard37808_0b0_theResult___fst_exp45769_0_ETC__q175)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 =
	      _theResult___fst_exp__h545769;
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10611;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10609;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 =
	      CASE_guard37808_0b0_theResult___fst_exp45769_0_ETC__q175;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10615 =
		   11'd0;
    endcase
  end
  always@(guard__h537808 or
	  _theResult___fst_exp__h545769 or
	  out_exp__h546427 or _theResult___exp__h546424)
  begin
    case (guard__h537808)
      2'b0, 2'b01:
	  CASE_guard37808_0b0_theResult___fst_exp45769_0_ETC__q176 =
	      _theResult___fst_exp__h545769;
      2'b10:
	  CASE_guard37808_0b0_theResult___fst_exp45769_0_ETC__q176 =
	      out_exp__h546427;
      2'b11:
	  CASE_guard37808_0b0_theResult___fst_exp45769_0_ETC__q176 =
	      _theResult___exp__h546424;
    endcase
  end
  always@(guard__h547120 or
	  _theResult___fst_exp__h555346 or _theResult___exp__h556075)
  begin
    case (guard__h547120)
      2'b0:
	  CASE_guard47120_0b0_theResult___fst_exp55346_0_ETC__q177 =
	      _theResult___fst_exp__h555346;
      2'b01, 2'b10, 2'b11:
	  CASE_guard47120_0b0_theResult___fst_exp55346_0_ETC__q177 =
	      _theResult___exp__h556075;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___fst_exp__h555346 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10649 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10647 or
	  CASE_guard47120_0b0_theResult___fst_exp55346_0_ETC__q177)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 =
	      _theResult___fst_exp__h555346;
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10649;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10647;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 =
	      CASE_guard47120_0b0_theResult___fst_exp55346_0_ETC__q177;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10653 =
		   11'd0;
    endcase
  end
  always@(guard__h547120 or
	  _theResult___fst_exp__h555346 or
	  out_exp__h556078 or _theResult___exp__h556075)
  begin
    case (guard__h547120)
      2'b0, 2'b01:
	  CASE_guard47120_0b0_theResult___fst_exp55346_0_ETC__q178 =
	      _theResult___fst_exp__h555346;
      2'b10:
	  CASE_guard47120_0b0_theResult___fst_exp55346_0_ETC__q178 =
	      out_exp__h556078;
      2'b11:
	  CASE_guard47120_0b0_theResult___fst_exp55346_0_ETC__q178 =
	      _theResult___exp__h556075;
    endcase
  end
  always@(guard__h556189 or
	  _theResult___fst_exp__h564179 or _theResult___exp__h564859)
  begin
    case (guard__h556189)
      2'b0:
	  CASE_guard56189_0b0_theResult___fst_exp64179_0_ETC__q179 =
	      _theResult___fst_exp__h564179;
      2'b01, 2'b10, 2'b11:
	  CASE_guard56189_0b0_theResult___fst_exp64179_0_ETC__q179 =
	      _theResult___exp__h564859;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___fst_exp__h564179 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10680 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10678 or
	  CASE_guard56189_0b0_theResult___fst_exp64179_0_ETC__q179)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 =
	      _theResult___fst_exp__h564179;
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10680;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10678;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 =
	      CASE_guard56189_0b0_theResult___fst_exp64179_0_ETC__q179;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10684 =
		   11'd0;
    endcase
  end
  always@(guard__h556189 or
	  _theResult___fst_exp__h564179 or
	  out_exp__h564862 or _theResult___exp__h564859)
  begin
    case (guard__h556189)
      2'b0, 2'b01:
	  CASE_guard56189_0b0_theResult___fst_exp64179_0_ETC__q180 =
	      _theResult___fst_exp__h564179;
      2'b10:
	  CASE_guard56189_0b0_theResult___fst_exp64179_0_ETC__q180 =
	      out_exp__h564862;
      2'b11:
	  CASE_guard56189_0b0_theResult___fst_exp64179_0_ETC__q180 =
	      _theResult___exp__h564859;
    endcase
  end
  always@(guard__h586424 or
	  _theResult___fst_exp__h594650 or _theResult___exp__h595379)
  begin
    case (guard__h586424)
      2'b0:
	  CASE_guard86424_0b0_theResult___fst_exp94650_0_ETC__q181 =
	      _theResult___fst_exp__h594650;
      2'b01, 2'b10, 2'b11:
	  CASE_guard86424_0b0_theResult___fst_exp94650_0_ETC__q181 =
	      _theResult___exp__h595379;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___fst_exp__h594650 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9879 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9877 or
	  CASE_guard86424_0b0_theResult___fst_exp94650_0_ETC__q181)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 =
	      _theResult___fst_exp__h594650;
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9879;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9877;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 =
	      CASE_guard86424_0b0_theResult___fst_exp94650_0_ETC__q181;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9883 =
		   11'd0;
    endcase
  end
  always@(guard__h586424 or
	  _theResult___fst_exp__h594650 or
	  out_exp__h595382 or _theResult___exp__h595379)
  begin
    case (guard__h586424)
      2'b0, 2'b01:
	  CASE_guard86424_0b0_theResult___fst_exp94650_0_ETC__q182 =
	      _theResult___fst_exp__h594650;
      2'b10:
	  CASE_guard86424_0b0_theResult___fst_exp94650_0_ETC__q182 =
	      out_exp__h595382;
      2'b11:
	  CASE_guard86424_0b0_theResult___fst_exp94650_0_ETC__q182 =
	      _theResult___exp__h595379;
    endcase
  end
  always@(guard__h595493 or
	  _theResult___fst_exp__h603483 or _theResult___exp__h604163)
  begin
    case (guard__h595493)
      2'b0:
	  CASE_guard95493_0b0_theResult___fst_exp03483_0_ETC__q183 =
	      _theResult___fst_exp__h603483;
      2'b01, 2'b10, 2'b11:
	  CASE_guard95493_0b0_theResult___fst_exp03483_0_ETC__q183 =
	      _theResult___exp__h604163;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___fst_exp__h603483 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9910 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9908 or
	  CASE_guard95493_0b0_theResult___fst_exp03483_0_ETC__q183)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 =
	      _theResult___fst_exp__h603483;
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9910;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9908;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 =
	      CASE_guard95493_0b0_theResult___fst_exp03483_0_ETC__q183;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9914 =
		   11'd0;
    endcase
  end
  always@(guard__h595493 or
	  _theResult___fst_exp__h603483 or
	  out_exp__h604166 or _theResult___exp__h604163)
  begin
    case (guard__h595493)
      2'b0, 2'b01:
	  CASE_guard95493_0b0_theResult___fst_exp03483_0_ETC__q184 =
	      _theResult___fst_exp__h603483;
      2'b10:
	  CASE_guard95493_0b0_theResult___fst_exp03483_0_ETC__q184 =
	      out_exp__h604166;
      2'b11:
	  CASE_guard95493_0b0_theResult___fst_exp03483_0_ETC__q184 =
	      _theResult___exp__h604163;
    endcase
  end
  always@(guard__h547120 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h547120)
      2'b0, 2'b01, 2'b10:
	  CASE_guard47120_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      2'd3:
	  CASE_guard47120_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 =
	      guard__h547120 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547120)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 =
	      (guard__h547120 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
		(guard__h547120 == 2'b01 || guard__h547120 == 2'b10 ||
		 guard__h547120 == 2'b11) &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		   32'hFFFFFFFF &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(guard__h537808 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h537808)
      2'b0, 2'b01, 2'b10:
	  CASE_guard37808_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      2'd3:
	  CASE_guard37808_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 =
	      guard__h537808 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h537808)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 =
	      (guard__h537808 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
		(guard__h537808 == 2'b01 || guard__h537808 == 2'b10 ||
		 guard__h537808 == 2'b11) &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		   32'hFFFFFFFF &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(guard__h556189 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h556189)
      2'b0, 2'b01, 2'b10:
	  CASE_guard56189_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      2'd3:
	  CASE_guard56189_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 =
	      guard__h556189 == 2'b11 &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h556189)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
	      32'hFFFFFFFF &&
	      coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 =
	      (guard__h556189 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
		(guard__h556189 == 2'b01 || guard__h556189 == 2'b10 ||
		 guard__h556189 == 2'b11) &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		32'hFFFFFFFF &&
		coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
		   32'hFFFFFFFF &&
		   coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(guard__h547120 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h547120)
      2'b0, 2'b01, 2'b10:
	  CASE_guard47120_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	      32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      2'd3:
	  CASE_guard47120_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 =
	      guard__h547120 != 2'b11 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	      32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547120)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	      32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 =
	      (guard__h547120 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
		guard__h547120 != 2'b01 && guard__h547120 != 2'b10 &&
		guard__h547120 != 2'b11 ||
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
		   coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
		   32'hFFFFFFFF ||
		   !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(guard__h537808 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h537808)
      2'b0, 2'b01, 2'b10:
	  CASE_guard37808_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	      32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      2'd3:
	  CASE_guard37808_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 =
	      guard__h537808 != 2'b11 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	      32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h537808)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	      32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 =
	      (guard__h537808 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
		guard__h537808 != 2'b01 && guard__h537808 != 2'b10 &&
		guard__h537808 != 2'b11 ||
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
		   coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
		   32'hFFFFFFFF ||
		   !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(guard__h556189 or coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (guard__h556189)
      2'b0, 2'b01, 2'b10:
	  CASE_guard56189_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	      32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      2'd3:
	  CASE_guard56189_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 =
	      guard__h556189 != 2'b11 ||
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	      32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h556189)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
	      32'hFFFFFFFF ||
	      !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 =
	      (guard__h556189 == 2'b0) ?
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
		guard__h556189 != 2'b01 && guard__h556189 != 2'b10 &&
		guard__h556189 != 2'b11 ||
		coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
		32'hFFFFFFFF ||
		!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 =
		   coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
		   coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
		   32'hFFFFFFFF ||
		   !coreFix_fpuMulDivExe_0_regToExeQ$first[107];
    endcase
  end
  always@(guard__h537808 or
	  _theResult___snd__h545720 or _theResult___sfd__h546425)
  begin
    case (guard__h537808)
      2'b0:
	  CASE_guard37808_0b0_theResult___snd45720_BITS__ETC__q197 =
	      _theResult___snd__h545720[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard37808_0b0_theResult___snd45720_BITS__ETC__q197 =
	      _theResult___sfd__h546425;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___snd__h545720 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10706 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10704 or
	  CASE_guard37808_0b0_theResult___snd45720_BITS__ETC__q197)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 =
	      _theResult___snd__h545720[56:5];
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10706;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10704;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 =
	      CASE_guard37808_0b0_theResult___snd45720_BITS__ETC__q197;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10710 =
		   52'd0;
    endcase
  end
  always@(guard__h537808 or
	  _theResult___snd__h545720 or
	  out_sfd__h546428 or _theResult___sfd__h546425)
  begin
    case (guard__h537808)
      2'b0, 2'b01:
	  CASE_guard37808_0b0_theResult___snd45720_BITS__ETC__q198 =
	      _theResult___snd__h545720[56:5];
      2'b10:
	  CASE_guard37808_0b0_theResult___snd45720_BITS__ETC__q198 =
	      out_sfd__h546428;
      2'b11:
	  CASE_guard37808_0b0_theResult___snd45720_BITS__ETC__q198 =
	      _theResult___sfd__h546425;
    endcase
  end
  always@(guard__h547120 or sfdin__h555340 or _theResult___sfd__h556076)
  begin
    case (guard__h547120)
      2'b0:
	  CASE_guard47120_0b0_sfdin55340_BITS_56_TO_5_0b_ETC__q199 =
	      sfdin__h555340[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard47120_0b0_sfdin55340_BITS_56_TO_5_0b_ETC__q199 =
	      _theResult___sfd__h556076;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  sfdin__h555340 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10732 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10730 or
	  CASE_guard47120_0b0_sfdin55340_BITS_56_TO_5_0b_ETC__q199)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 =
	      sfdin__h555340[56:5];
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10732;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10730;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 =
	      CASE_guard47120_0b0_sfdin55340_BITS_56_TO_5_0b_ETC__q199;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10736 =
		   52'd0;
    endcase
  end
  always@(guard__h547120 or
	  sfdin__h555340 or out_sfd__h556079 or _theResult___sfd__h556076)
  begin
    case (guard__h547120)
      2'b0, 2'b01:
	  CASE_guard47120_0b0_sfdin55340_BITS_56_TO_5_0b_ETC__q200 =
	      sfdin__h555340[56:5];
      2'b10:
	  CASE_guard47120_0b0_sfdin55340_BITS_56_TO_5_0b_ETC__q200 =
	      out_sfd__h556079;
      2'b11:
	  CASE_guard47120_0b0_sfdin55340_BITS_56_TO_5_0b_ETC__q200 =
	      _theResult___sfd__h556076;
    endcase
  end
  always@(guard__h556189 or
	  _theResult___snd__h564125 or _theResult___sfd__h564860)
  begin
    case (guard__h556189)
      2'b0:
	  CASE_guard56189_0b0_theResult___snd64125_BITS__ETC__q201 =
	      _theResult___snd__h564125[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard56189_0b0_theResult___snd64125_BITS__ETC__q201 =
	      _theResult___sfd__h564860;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___snd__h564125 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10751 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10749 or
	  CASE_guard56189_0b0_theResult___snd64125_BITS__ETC__q201)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 =
	      _theResult___snd__h564125[56:5];
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10751;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10749;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 =
	      CASE_guard56189_0b0_theResult___snd64125_BITS__ETC__q201;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10755 =
		   52'd0;
    endcase
  end
  always@(guard__h556189 or
	  _theResult___snd__h564125 or
	  out_sfd__h564863 or _theResult___sfd__h564860)
  begin
    case (guard__h556189)
      2'b0, 2'b01:
	  CASE_guard56189_0b0_theResult___snd64125_BITS__ETC__q202 =
	      _theResult___snd__h564125[56:5];
      2'b10:
	  CASE_guard56189_0b0_theResult___snd64125_BITS__ETC__q202 =
	      out_sfd__h564863;
      2'b11:
	  CASE_guard56189_0b0_theResult___snd64125_BITS__ETC__q202 =
	      _theResult___sfd__h564860;
    endcase
  end
  always@(guard__h508267 or
	  _theResult___fst_exp__h516493 or _theResult___exp__h517222)
  begin
    case (guard__h508267)
      2'b0:
	  CASE_guard08267_0b0_theResult___fst_exp16493_0_ETC__q203 =
	      _theResult___fst_exp__h516493;
      2'b01, 2'b10, 2'b11:
	  CASE_guard08267_0b0_theResult___fst_exp16493_0_ETC__q203 =
	      _theResult___exp__h517222;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___fst_exp__h516493 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9169 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9167 or
	  CASE_guard08267_0b0_theResult___fst_exp16493_0_ETC__q203)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 =
	      _theResult___fst_exp__h516493;
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9169;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9167;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 =
	      CASE_guard08267_0b0_theResult___fst_exp16493_0_ETC__q203;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9173 =
		   11'd0;
    endcase
  end
  always@(guard__h508267 or
	  _theResult___fst_exp__h516493 or
	  out_exp__h517225 or _theResult___exp__h517222)
  begin
    case (guard__h508267)
      2'b0, 2'b01:
	  CASE_guard08267_0b0_theResult___fst_exp16493_0_ETC__q204 =
	      _theResult___fst_exp__h516493;
      2'b10:
	  CASE_guard08267_0b0_theResult___fst_exp16493_0_ETC__q204 =
	      out_exp__h517225;
      2'b11:
	  CASE_guard08267_0b0_theResult___fst_exp16493_0_ETC__q204 =
	      _theResult___exp__h517222;
    endcase
  end
  always@(guard__h498955 or
	  _theResult___snd__h506867 or _theResult___sfd__h507572)
  begin
    case (guard__h498955)
      2'b0:
	  CASE_guard98955_0b0_theResult___snd06867_BITS__ETC__q205 =
	      _theResult___snd__h506867[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard98955_0b0_theResult___snd06867_BITS__ETC__q205 =
	      _theResult___sfd__h507572;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___snd__h506867 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9226 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9224 or
	  CASE_guard98955_0b0_theResult___snd06867_BITS__ETC__q205)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 =
	      _theResult___snd__h506867[56:5];
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9226;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9224;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 =
	      CASE_guard98955_0b0_theResult___snd06867_BITS__ETC__q205;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9230 =
		   52'd0;
    endcase
  end
  always@(guard__h498955 or
	  _theResult___snd__h506867 or
	  out_sfd__h507575 or _theResult___sfd__h507572)
  begin
    case (guard__h498955)
      2'b0, 2'b01:
	  CASE_guard98955_0b0_theResult___snd06867_BITS__ETC__q206 =
	      _theResult___snd__h506867[56:5];
      2'b10:
	  CASE_guard98955_0b0_theResult___snd06867_BITS__ETC__q206 =
	      out_sfd__h507575;
      2'b11:
	  CASE_guard98955_0b0_theResult___snd06867_BITS__ETC__q206 =
	      _theResult___sfd__h507572;
    endcase
  end
  always@(guard__h517336 or
	  _theResult___fst_exp__h525326 or _theResult___exp__h526006)
  begin
    case (guard__h517336)
      2'b0:
	  CASE_guard17336_0b0_theResult___fst_exp25326_0_ETC__q207 =
	      _theResult___fst_exp__h525326;
      2'b01, 2'b10, 2'b11:
	  CASE_guard17336_0b0_theResult___fst_exp25326_0_ETC__q207 =
	      _theResult___exp__h526006;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___fst_exp__h525326 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9200 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9198 or
	  CASE_guard17336_0b0_theResult___fst_exp25326_0_ETC__q207)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 =
	      _theResult___fst_exp__h525326;
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9200;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9198;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 =
	      CASE_guard17336_0b0_theResult___fst_exp25326_0_ETC__q207;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9204 =
		   11'd0;
    endcase
  end
  always@(guard__h517336 or
	  _theResult___fst_exp__h525326 or
	  out_exp__h526009 or _theResult___exp__h526006)
  begin
    case (guard__h517336)
      2'b0, 2'b01:
	  CASE_guard17336_0b0_theResult___fst_exp25326_0_ETC__q208 =
	      _theResult___fst_exp__h525326;
      2'b10:
	  CASE_guard17336_0b0_theResult___fst_exp25326_0_ETC__q208 =
	      out_exp__h526009;
      2'b11:
	  CASE_guard17336_0b0_theResult___fst_exp25326_0_ETC__q208 =
	      _theResult___exp__h526006;
    endcase
  end
  always@(guard__h508267 or sfdin__h516487 or _theResult___sfd__h517223)
  begin
    case (guard__h508267)
      2'b0:
	  CASE_guard08267_0b0_sfdin16487_BITS_56_TO_5_0b_ETC__q209 =
	      sfdin__h516487[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard08267_0b0_sfdin16487_BITS_56_TO_5_0b_ETC__q209 =
	      _theResult___sfd__h517223;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  sfdin__h516487 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9253 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251 or
	  CASE_guard08267_0b0_sfdin16487_BITS_56_TO_5_0b_ETC__q209)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 =
	      sfdin__h516487[56:5];
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9253;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9251;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 =
	      CASE_guard08267_0b0_sfdin16487_BITS_56_TO_5_0b_ETC__q209;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9257 =
		   52'd0;
    endcase
  end
  always@(guard__h508267 or
	  sfdin__h516487 or out_sfd__h517226 or _theResult___sfd__h517223)
  begin
    case (guard__h508267)
      2'b0, 2'b01:
	  CASE_guard08267_0b0_sfdin16487_BITS_56_TO_5_0b_ETC__q210 =
	      sfdin__h516487[56:5];
      2'b10:
	  CASE_guard08267_0b0_sfdin16487_BITS_56_TO_5_0b_ETC__q210 =
	      out_sfd__h517226;
      2'b11:
	  CASE_guard08267_0b0_sfdin16487_BITS_56_TO_5_0b_ETC__q210 =
	      _theResult___sfd__h517223;
    endcase
  end
  always@(guard__h517336 or
	  _theResult___snd__h525272 or _theResult___sfd__h526007)
  begin
    case (guard__h517336)
      2'b0:
	  CASE_guard17336_0b0_theResult___snd25272_BITS__ETC__q211 =
	      _theResult___snd__h525272[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard17336_0b0_theResult___snd25272_BITS__ETC__q211 =
	      _theResult___sfd__h526007;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___snd__h525272 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9272 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9270 or
	  CASE_guard17336_0b0_theResult___snd25272_BITS__ETC__q211)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 =
	      _theResult___snd__h525272[56:5];
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9272;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9270;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 =
	      CASE_guard17336_0b0_theResult___snd25272_BITS__ETC__q211;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9276 =
		   52'd0;
    endcase
  end
  always@(guard__h517336 or
	  _theResult___snd__h525272 or
	  out_sfd__h526010 or _theResult___sfd__h526007)
  begin
    case (guard__h517336)
      2'b0, 2'b01:
	  CASE_guard17336_0b0_theResult___snd25272_BITS__ETC__q212 =
	      _theResult___snd__h525272[56:5];
      2'b10:
	  CASE_guard17336_0b0_theResult___snd25272_BITS__ETC__q212 =
	      out_sfd__h526010;
      2'b11:
	  CASE_guard17336_0b0_theResult___snd25272_BITS__ETC__q212 =
	      _theResult___sfd__h526007;
    endcase
  end
  always@(guard__h577112 or
	  _theResult___snd__h585024 or _theResult___sfd__h585729)
  begin
    case (guard__h577112)
      2'b0:
	  CASE_guard77112_0b0_theResult___snd85024_BITS__ETC__q213 =
	      _theResult___snd__h585024[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard77112_0b0_theResult___snd85024_BITS__ETC__q213 =
	      _theResult___sfd__h585729;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___snd__h585024 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9936 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9934 or
	  CASE_guard77112_0b0_theResult___snd85024_BITS__ETC__q213)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 =
	      _theResult___snd__h585024[56:5];
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9936;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9934;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 =
	      CASE_guard77112_0b0_theResult___snd85024_BITS__ETC__q213;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9940 =
		   52'd0;
    endcase
  end
  always@(guard__h577112 or
	  _theResult___snd__h585024 or
	  out_sfd__h585732 or _theResult___sfd__h585729)
  begin
    case (guard__h577112)
      2'b0, 2'b01:
	  CASE_guard77112_0b0_theResult___snd85024_BITS__ETC__q214 =
	      _theResult___snd__h585024[56:5];
      2'b10:
	  CASE_guard77112_0b0_theResult___snd85024_BITS__ETC__q214 =
	      out_sfd__h585732;
      2'b11:
	  CASE_guard77112_0b0_theResult___snd85024_BITS__ETC__q214 =
	      _theResult___sfd__h585729;
    endcase
  end
  always@(guard__h586424 or sfdin__h594644 or _theResult___sfd__h595380)
  begin
    case (guard__h586424)
      2'b0:
	  CASE_guard86424_0b0_sfdin94644_BITS_56_TO_5_0b_ETC__q215 =
	      sfdin__h594644[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard86424_0b0_sfdin94644_BITS_56_TO_5_0b_ETC__q215 =
	      _theResult___sfd__h595380;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  sfdin__h594644 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9962 or
	  IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9960 or
	  CASE_guard86424_0b0_sfdin94644_BITS_56_TO_5_0b_ETC__q215)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 =
	      sfdin__h594644[56:5];
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9962;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 =
	      IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9960;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 =
	      CASE_guard86424_0b0_sfdin94644_BITS_56_TO_5_0b_ETC__q215;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9966 =
		   52'd0;
    endcase
  end
  always@(guard__h586424 or
	  sfdin__h594644 or out_sfd__h595383 or _theResult___sfd__h595380)
  begin
    case (guard__h586424)
      2'b0, 2'b01:
	  CASE_guard86424_0b0_sfdin94644_BITS_56_TO_5_0b_ETC__q216 =
	      sfdin__h594644[56:5];
      2'b10:
	  CASE_guard86424_0b0_sfdin94644_BITS_56_TO_5_0b_ETC__q216 =
	      out_sfd__h595383;
      2'b11:
	  CASE_guard86424_0b0_sfdin94644_BITS_56_TO_5_0b_ETC__q216 =
	      _theResult___sfd__h595380;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d10999 or
	  NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10987 or
	  NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10976)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
      5'd0, 5'd1, 5'd2, 5'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d11001 =
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10987;
      5'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d11001 =
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10976;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d11001 =
		   coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d10999;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d10963 or
	  NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10918 or
	  NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
      5'd0, 5'd1, 5'd2, 5'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10965 =
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10918;
      5'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10965 =
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10965 =
		   coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d10963;
    endcase
  end
  always@(guard__h595493 or
	  _theResult___snd__h603429 or _theResult___sfd__h604164)
  begin
    case (guard__h595493)
      2'b0:
	  CASE_guard95493_0b0_theResult___snd03429_BITS__ETC__q217 =
	      _theResult___snd__h603429[56:5];
      2'b01, 2'b10, 2'b11:
	  CASE_guard95493_0b0_theResult___snd03429_BITS__ETC__q217 =
	      _theResult___sfd__h604164;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  _theResult___snd__h603429 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9981 or
	  IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9979 or
	  CASE_guard95493_0b0_theResult___snd03429_BITS__ETC__q217)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 =
	      _theResult___snd__h603429[56:5];
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9981;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 =
	      IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9979;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 =
	      CASE_guard95493_0b0_theResult___snd03429_BITS__ETC__q217;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9985 =
		   52'd0;
    endcase
  end
  always@(guard__h595493 or
	  _theResult___snd__h603429 or
	  out_sfd__h604167 or _theResult___sfd__h604164)
  begin
    case (guard__h595493)
      2'b0, 2'b01:
	  CASE_guard95493_0b0_theResult___snd03429_BITS__ETC__q218 =
	      _theResult___snd__h603429[56:5];
      2'b10:
	  CASE_guard95493_0b0_theResult___snd03429_BITS__ETC__q218 =
	      out_sfd__h604167;
      2'b11:
	  CASE_guard95493_0b0_theResult___snd03429_BITS__ETC__q218 =
	      _theResult___sfd__h604164;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11047 or
	  NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11031 or
	  NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11016)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
      5'd0, 5'd1, 5'd2, 5'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d11049 =
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11031;
      5'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d11049 =
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11016;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d11049 =
		   coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11047;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11089 or
	  NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11075 or
	  NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11062)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
      5'd0, 5'd1, 5'd2, 5'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d11091 =
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11075;
      5'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d11091 =
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11062;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d11091 =
		   coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11089;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11131 or
	  NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11117 or
	  NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11104)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
      5'd0, 5'd1, 5'd2, 5'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d11133 =
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11117;
      5'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d11133 =
	      NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11104;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d11133 =
		   coreFix_fpuMulDivExe_0_regToExeQ_first__482_BI_ETC___d11131;
    endcase
  end
  always@(coreFix_aluExe_1_regToExeQ$first)
  begin
    case (coreFix_aluExe_1_regToExeQ$first[399:397])
      3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
	  CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219 =
	      coreFix_aluExe_1_regToExeQ$first[399:397];
      default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219 = 3'd7;
    endcase
  end
  always@(coreFix_aluExe_1_regToExeQ$first or
	  CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219)
  begin
    case (coreFix_aluExe_1_regToExeQ$first[416:414])
      3'd3, 3'd2, 3'd1, 3'd0:
	  CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220 =
	      coreFix_aluExe_1_regToExeQ$first[416:396];
      3'd4:
	  CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220 =
	      { coreFix_aluExe_1_regToExeQ$first[416:414],
		9'h0AA,
		coreFix_aluExe_1_regToExeQ$first[404:400],
		CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q219,
		coreFix_aluExe_1_regToExeQ$first[396] };
      default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q220 =
		   { 3'd5, 18'h2AAAA };
    endcase
  end
  always@(coreFix_aluExe_1_regToExeQ$first)
  begin
    case (coreFix_aluExe_1_regToExeQ$first[394:383])
      12'd1955,
      12'd1954,
      12'd1953,
      12'd1952,
      12'd3860,
      12'd3859,
      12'd3858,
      12'd3857,
      12'd2818,
      12'd2816,
      12'd836,
      12'd835,
      12'd834,
      12'd833,
      12'd832,
      12'd774,
      12'd773,
      12'd772,
      12'd771,
      12'd770,
      12'd769,
      12'd768,
      12'd384,
      12'd324,
      12'd323,
      12'd322,
      12'd321,
      12'd320,
      12'd262,
      12'd261,
      12'd260,
      12'd256,
      12'd2049,
      12'd2048,
      12'd3074,
      12'd3073,
      12'd3072,
      12'd3,
      12'd2,
      12'd1:
	  CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221 =
	      coreFix_aluExe_1_regToExeQ$first[394:383];
      default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q221 =
		   12'd2303;
    endcase
  end
  always@(coreFix_aluExe_0_regToExeQ$first)
  begin
    case (coreFix_aluExe_0_regToExeQ$first[399:397])
      3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
	  CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222 =
	      coreFix_aluExe_0_regToExeQ$first[399:397];
      default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222 = 3'd7;
    endcase
  end
  always@(coreFix_aluExe_0_regToExeQ$first or
	  CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222)
  begin
    case (coreFix_aluExe_0_regToExeQ$first[416:414])
      3'd3, 3'd2, 3'd1, 3'd0:
	  CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223 =
	      coreFix_aluExe_0_regToExeQ$first[416:396];
      3'd4:
	  CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223 =
	      { coreFix_aluExe_0_regToExeQ$first[416:414],
		9'h0AA,
		coreFix_aluExe_0_regToExeQ$first[404:400],
		CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q222,
		coreFix_aluExe_0_regToExeQ$first[396] };
      default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q223 =
		   { 3'd5, 18'h2AAAA };
    endcase
  end
  always@(coreFix_aluExe_0_regToExeQ$first)
  begin
    case (coreFix_aluExe_0_regToExeQ$first[394:383])
      12'd1955,
      12'd1954,
      12'd1953,
      12'd1952,
      12'd3860,
      12'd3859,
      12'd3858,
      12'd3857,
      12'd2818,
      12'd2816,
      12'd836,
      12'd835,
      12'd834,
      12'd833,
      12'd832,
      12'd774,
      12'd773,
      12'd772,
      12'd771,
      12'd770,
      12'd769,
      12'd768,
      12'd384,
      12'd324,
      12'd323,
      12'd322,
      12'd321,
      12'd320,
      12'd262,
      12'd261,
      12'd260,
      12'd256,
      12'd2049,
      12'd2048,
      12'd3074,
      12'd3073,
      12'd3072,
      12'd3,
      12'd2,
      12'd1:
	  CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q224 =
	      coreFix_aluExe_0_regToExeQ$first[394:383];
      default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q224 =
		   12'd2303;
    endcase
  end
  always@(fetchStage$pipelines_0_first)
  begin
    case (fetchStage$pipelines_0_first[172:161])
      12'd1,
      12'd2,
      12'd3,
      12'd256,
      12'd260,
      12'd261,
      12'd262,
      12'd320,
      12'd321,
      12'd322,
      12'd323,
      12'd324,
      12'd384,
      12'd768,
      12'd769,
      12'd770,
      12'd771,
      12'd772,
      12'd773,
      12'd774,
      12'd832,
      12'd833,
      12'd834,
      12'd835,
      12'd836,
      12'd1952,
      12'd1953,
      12'd1954,
      12'd1955,
      12'd2048,
      12'd2049,
      12'd2816,
      12'd2818,
      12'd3072,
      12'd3073,
      12'd3074,
      12'd3857,
      12'd3858,
      12'd3859,
      12'd3860:
	  IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125 =
	      fetchStage$pipelines_0_first[172:161];
      default: IF_fetchStage_pipelines_0_first__2928_BITS_172_ETC___d13125 =
		   12'd2303;
    endcase
  end
  always@(fetchStage$pipelines_0_first)
  begin
    case (fetchStage$pipelines_0_first[67:64])
      4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9:
	  IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13266 =
	      fetchStage$pipelines_0_first[67:64];
      4'd11:
	  IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13266 = 4'd10;
      4'd12:
	  IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13266 = 4'd11;
      4'd13:
	  IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13266 = 4'd12;
      default: IF_fetchStage_pipelines_0_first__2928_BIT_68_2_ETC___d13266 =
		   4'd13;
    endcase
  end
  always@(fetchStage$pipelines_0_first)
  begin
    case (fetchStage$pipelines_0_first[177:175])
      3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
	  CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225 =
	      fetchStage$pipelines_0_first[177:175];
      default: CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225 = 3'd7;
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1, 3'd2, 3'd3:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043 =
	      fetchStage$pipelines_0_first[194:174];
      3'd4:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043 =
	      { fetchStage$pipelines_0_first[194:192],
		9'h0AA,
		fetchStage$pipelines_0_first[182:178],
		CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q225,
		fetchStage$pipelines_0_first[174] };
      default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13043 =
		   21'd1485482;
    endcase
  end
  always@(checkForException___d13160)
  begin
    case (checkForException___d13160[3:0])
      4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9:
	  CASE_checkForException_3160_BITS_3_TO_0_0_chec_ETC__q226 =
	      checkForException___d13160[3:0];
      4'd11: CASE_checkForException_3160_BITS_3_TO_0_0_chec_ETC__q226 = 4'd10;
      4'd12: CASE_checkForException_3160_BITS_3_TO_0_0_chec_ETC__q226 = 4'd11;
      4'd13: CASE_checkForException_3160_BITS_3_TO_0_0_chec_ETC__q226 = 4'd12;
      default: CASE_checkForException_3160_BITS_3_TO_0_0_chec_ETC__q226 =
		   4'd13;
    endcase
  end
  always@(IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3__ETC___d13368)
  begin
    case (IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3__ETC___d13368)
      4'd0, 4'd1:
	  CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2956__ETC__q227 =
	      IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3__ETC___d13368;
      4'd2: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2956__ETC__q227 = 4'd3;
      4'd3: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2956__ETC__q227 = 4'd4;
      4'd4: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2956__ETC__q227 = 4'd5;
      4'd5: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2956__ETC__q227 = 4'd7;
      4'd6: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2956__ETC__q227 = 4'd8;
      4'd7: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2956__ETC__q227 = 4'd9;
      default: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2956__ETC__q227 =
		   4'd11;
    endcase
  end
  always@(k__h675032 or
	  coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq)
  begin
    case (k__h675032)
      1'd0:
	  SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 =
	      coreFix_aluExe_0_rsAlu$canEnq;
      1'd1:
	  SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 =
	      coreFix_aluExe_1_rsAlu$canEnq;
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_0_first[191:189])
      3'd0, 3'd2:
	  IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 =
	      coreFix_memExe_lsq$enqLdTag[6];
      default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 =
		   coreFix_memExe_lsq$enqStTag[6];
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_rsMem$canEnq or
	  IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 or
	  SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13584 =
	      SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13584 =
	      coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
      default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13584 =
		   fetchStage$pipelines_0_first[194:192] != 3'd2 ||
		   coreFix_memExe_rsMem$canEnq &&
		   IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580;
    endcase
  end
  always@(k__h675032 or
	  coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq)
  begin
    case (k__h675032)
      1'd0:
	  SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601 =
	      !coreFix_aluExe_0_rsAlu$canEnq;
      1'd1:
	  SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601 =
	      !coreFix_aluExe_1_rsAlu$canEnq;
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  regRenamingTable$rename_0_canRename or
	  NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548 or
	  NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13603 or
	  coreFix_memExe_rsMem$canEnq or
	  IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 =
	      NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13603;
      3'd2:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 =
	      coreFix_memExe_rsMem$canEnq &&
	      IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 &&
	      regRenamingTable$rename_0_canRename &&
	      NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 =
	      coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq &&
	      regRenamingTable$rename_0_canRename &&
	      NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548;
      default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13608 =
		   regRenamingTable$rename_0_canRename &&
		   NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13548;
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_0_first[191:189])
      3'd0, 3'd2:
	  IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 =
	      !coreFix_memExe_lsq$enqLdTag[6];
      default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 =
		   !coreFix_memExe_lsq$enqStTag[6];
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_rsMem$canEnq or
	  IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 or
	  SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601 or
	  specTagManager$canClaim or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13641 =
	      SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601 ||
	      fetchStage$pipelines_0_first[194:192] == 3'd1 &&
	      !specTagManager$canClaim;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13641 =
	      !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
      default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13641 =
		   fetchStage$pipelines_0_first[194:192] == 3'd2 &&
		   (!coreFix_memExe_rsMem$canEnq ||
		    IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636);
    endcase
  end
  always@(fetchStage$pipelines_1_first)
  begin
    case (fetchStage$pipelines_1_first[172:161])
      12'd1,
      12'd2,
      12'd3,
      12'd256,
      12'd260,
      12'd261,
      12'd262,
      12'd320,
      12'd321,
      12'd322,
      12'd323,
      12'd324,
      12'd384,
      12'd768,
      12'd769,
      12'd770,
      12'd771,
      12'd772,
      12'd773,
      12'd774,
      12'd832,
      12'd833,
      12'd834,
      12'd835,
      12'd836,
      12'd1952,
      12'd1953,
      12'd1954,
      12'd1955,
      12'd2048,
      12'd2049,
      12'd2816,
      12'd2818,
      12'd3072,
      12'd3073,
      12'd3074,
      12'd3857,
      12'd3858,
      12'd3859,
      12'd3860:
	  CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228 =
	      fetchStage$pipelines_1_first[172:161];
      default: CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q228 =
		   12'd2303;
    endcase
  end
  always@(fetchStage$pipelines_1_first)
  begin
    case (fetchStage$pipelines_1_first[177:175])
      3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
	  CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229 =
	      fetchStage$pipelines_1_first[177:175];
      default: CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229 = 3'd7;
    endcase
  end
  always@(fetchStage$pipelines_1_first or
	  CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229)
  begin
    case (fetchStage$pipelines_1_first[194:192])
      3'd0, 3'd1, 3'd2, 3'd3:
	  IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13701 =
	      fetchStage$pipelines_1_first[194:174];
      3'd4:
	  IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13701 =
	      { fetchStage$pipelines_1_first[194:192],
		9'h0AA,
		fetchStage$pipelines_1_first[182:178],
		CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q229,
		fetchStage$pipelines_1_first[174] };
      default: IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13701 =
		   21'd1485482;
    endcase
  end
  always@(idx__h690627 or
	  fetchStage$pipelines_0_canDeq or
	  NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13852 or
	  coreFix_aluExe_0_rsAlu$canEnq or
	  NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13858 or
	  coreFix_aluExe_1_rsAlu$canEnq)
  begin
    case (idx__h690627)
      1'd0:
	  SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13877 =
	      fetchStage$pipelines_0_canDeq &&
	      NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13852 ||
	      !coreFix_aluExe_0_rsAlu$canEnq;
      1'd1:
	  SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13877 =
	      fetchStage$pipelines_0_canDeq &&
	      NOT_fetchStage_pipelines_0_first__2928_BITS_19_ETC___d13858 ||
	      !coreFix_aluExe_1_rsAlu$canEnq;
    endcase
  end
  always@(fetchStage$pipelines_1_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_1_first[191:189])
      3'd0, 3'd2:
	  CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 =
	      !coreFix_memExe_lsq$enqLdTag[6];
      default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q230 =
		   !coreFix_memExe_lsq$enqStTag[6];
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992 or
	  SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601 or
	  fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13944 or
	  NOT_coreFix_memExe_rsMem_canEnq__3571_3633_OR__ETC___d13947 or
	  NOT_coreFix_fpuMulDivExe_0_rsFpuMulDiv_canEnq__ETC___d13946)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13950 =
	      SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601 ||
	      fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d13944;
      3'd2:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13950 =
	      NOT_coreFix_memExe_rsMem_canEnq__3571_3633_OR__ETC___d13947;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13950 =
	      NOT_coreFix_fpuMulDivExe_0_rsFpuMulDiv_canEnq__ETC___d13946;
      default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13950 =
		   fetchStage$pipelines_0_first[68] ||
		   IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[0] ||
		   IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[1] ||
		   IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[2] ||
		   IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[3] ||
		   IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[4] ||
		   IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[5] ||
		   IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[6] ||
		   IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[7] ||
		   IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[8] ||
		   IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[9] ||
		   IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[10] ||
		   IF_IF_NOT_csrf_prv_reg_read__2956_EQ_3_2957_29_ETC___d12992[11];
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_rsMem$canEnq or
	  IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 or
	  SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13971 =
	      SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568;
      default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13971 =
		   fetchStage$pipelines_0_first[194:192] != 3'd2 ||
		   coreFix_memExe_rsMem$canEnq &&
		   IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580;
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 or
	  SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13988 =
	      SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13988 =
	      coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
      default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d13988 =
		   fetchStage$pipelines_0_first[194:192] != 3'd2 ||
		   IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580;
    endcase
  end
  always@(fetchStage$pipelines_1_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_1_first[191:189])
      3'd0, 3'd2:
	  CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231 =
	      coreFix_memExe_lsq$enqLdTag[6];
      default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q231 =
		   coreFix_memExe_lsq$enqStTag[6];
    endcase
  end
  always@(fetchStage$pipelines_1_first or
	  regRenamingTable$rename_1_canRename or
	  NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13843 or
	  SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13877 or
	  NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13956 or
	  NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13985 or
	  NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13994 or
	  NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13968 or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or
	  NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13977)
  begin
    case (fetchStage$pipelines_1_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13999 =
	      !SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13877 &&
	      NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13956;
      3'd2:
	  IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13999 =
	      NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13985 &&
	      regRenamingTable$rename_1_canRename &&
	      NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13994;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13999 =
	      NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d13968 &&
	      coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq &&
	      regRenamingTable$rename_1_canRename &&
	      NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13977;
      default: IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d13999 =
		   regRenamingTable$rename_1_canRename &&
		   NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d13843;
    endcase
  end
  always@(k__h675032 or
	  coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq)
  begin
    case (k__h675032)
      1'd0:
	  CASE_k75032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 =
	      coreFix_aluExe_0_rsAlu$RDY_enq;
      1'd1:
	  CASE_k75032_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 =
	      coreFix_aluExe_1_rsAlu$RDY_enq;
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd)
  begin
    case (fetchStage$pipelines_0_first[191:189])
      3'd0, 3'd2:
	  CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 =
	      coreFix_memExe_lsq$RDY_enqLd;
      default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q233 =
		   coreFix_memExe_lsq$RDY_enqSt;
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_rsMem$canEnq or
	  IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 or
	  SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601 or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14043 =
	      SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14043 =
	      !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
      default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14043 =
		   fetchStage$pipelines_0_first[194:192] == 3'd2 &&
		   (!coreFix_memExe_rsMem$canEnq ||
		    IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636);
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_rsMem$canEnq or
	  IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 or
	  regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14037 or
	  SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 or
	  regRenamingTable$RDY_rename_0_getRename or
	  _0_OR_NOT_fetchStage_pipelines_0_first__2928_BI_ETC___d14024 or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14041 =
	      !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 ||
	      regRenamingTable$RDY_rename_0_getRename &&
	      _0_OR_NOT_fetchStage_pipelines_0_first__2928_BI_ETC___d14024;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14041 =
	      !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
	      coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq &&
	      regRenamingTable$RDY_rename_0_getRename;
      default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14041 =
		   fetchStage$pipelines_0_first[194:192] != 3'd2 ||
		   !coreFix_memExe_rsMem$canEnq ||
		   IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 ||
		   regRenamingTable_RDY_rename_0_getRename__3398__ETC___d14037;
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_rsMem$canEnq or
	  IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 or
	  SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14057 =
	      !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14057 =
	      !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
      default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14057 =
		   fetchStage$pipelines_0_first[194:192] == 3'd2 &&
		   (!coreFix_memExe_rsMem$canEnq ||
		    IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636);
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_rsMem$canEnq or
	  IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580 or
	  SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601 or
	  specTagManager$canClaim or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14064 =
	      !SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__355_ETC___d13601 &&
	      (fetchStage$pipelines_0_first[194:192] != 3'd1 ||
	       specTagManager$canClaim);
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14064 =
	      coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
      default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14064 =
		   fetchStage$pipelines_0_first[194:192] != 3'd2 ||
		   coreFix_memExe_rsMem$canEnq &&
		   IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13580;
    endcase
  end
  always@(idx__h690627 or
	  fetchStage$pipelines_0_canDeq or
	  fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14080 or
	  coreFix_aluExe_0_rsAlu$canEnq or
	  fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14087 or
	  coreFix_aluExe_1_rsAlu$canEnq)
  begin
    case (idx__h690627)
      1'd0:
	  SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14091 =
	      (!fetchStage$pipelines_0_canDeq ||
	       fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14080) &&
	      coreFix_aluExe_0_rsAlu$canEnq;
      1'd1:
	  SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14091 =
	      (!fetchStage$pipelines_0_canDeq ||
	       fetchStage_pipelines_0_first__2928_BITS_194_TO_ETC___d14087) &&
	      coreFix_aluExe_1_rsAlu$canEnq;
    endcase
  end
  always@(fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14107 or
	  coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq)
  begin
    case (fetchStage_pipelines_0_canDeq__2926_AND_NOT_fe_ETC___d14107)
      1'd0:
	  CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q234 =
	      coreFix_aluExe_0_rsAlu$RDY_enq;
      1'd1:
	  CASE_fetchStage_pipelines_0_canDeq__2926_AND_N_ETC__q234 =
	      coreFix_aluExe_1_rsAlu$RDY_enq;
    endcase
  end
  always@(fetchStage$pipelines_1_first or
	  coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd)
  begin
    case (fetchStage$pipelines_1_first[191:189])
      3'd0, 3'd2:
	  CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235 =
	      coreFix_memExe_lsq$RDY_enqLd;
      default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q235 =
		   coreFix_memExe_lsq$RDY_enqSt;
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_rsMem$canEnq or
	  IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 or
	  SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14133 =
	      !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568;
      default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14133 =
		   fetchStage$pipelines_0_first[194:192] == 3'd2 &&
		   (!coreFix_memExe_rsMem$canEnq ||
		    IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636);
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636 or
	  SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568 or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
  begin
    case (fetchStage$pipelines_0_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14144 =
	      !SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3558_co_ETC___d13568;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14144 =
	      !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
      default: IF_fetchStage_pipelines_0_first__2928_BITS_194_ETC___d14144 =
		   fetchStage$pipelines_0_first[194:192] == 3'd2 &&
		   IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d13636;
    endcase
  end
  always@(fetchStage$pipelines_1_first or
	  fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14152 or
	  SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13877 or
	  fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14141)
  begin
    case (fetchStage$pipelines_1_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14155 =
	      SEL_ARR_fetchStage_pipelines_0_canDeq__2926_AN_ETC___d13877;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14155 =
	      fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14141;
      default: IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14155 =
		   fetchStage$pipelines_1_first[194:192] == 3'd2 &&
		   fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14152;
    endcase
  end
  always@(fetchStage$pipelines_1_first or
	  fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14120 or
	  regRenamingTable$RDY_rename_1_getRename or
	  NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14125 or
	  SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14091 or
	  regRenamingTable_RDY_rename_1_getRename__4093__ETC___d14111 or
	  fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14113 or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14116)
  begin
    case (fetchStage$pipelines_1_first[194:192])
      3'd0, 3'd1:
	  IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14130 =
	      !SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__292_ETC___d14091 ||
	      regRenamingTable_RDY_rename_1_getRename__4093__ETC___d14111;
      3'd3, 3'd4:
	  IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14130 =
	      fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14113 ||
	      !coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
	      coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__40_ETC___d14116;
      default: IF_fetchStage_pipelines_1_first__2937_BITS_194_ETC___d14130 =
		   fetchStage$pipelines_1_first[194:192] != 3'd2 ||
		   fetchStage_pipelines_0_canDeq__2926_AND_regRen_ETC___d14120 ||
		   regRenamingTable$RDY_rename_1_getRename &&
		   NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14125;
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_0_first[191:189])
      3'd0, 3'd2:
	  IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14228 =
	      !coreFix_memExe_lsq$enqLdTag[5];
      default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14228 =
		   !coreFix_memExe_lsq$enqStTag[5];
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_0_first[191:189])
      3'd0, 3'd2:
	  IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14225 =
	      coreFix_memExe_lsq$enqLdTag[5];
      default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14225 =
		   coreFix_memExe_lsq$enqStTag[5];
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_0_first[191:189])
      3'd0, 3'd2:
	  IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14231 =
	      coreFix_memExe_lsq$enqLdTag[4:0];
      default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14231 =
		   coreFix_memExe_lsq$enqStTag[4:0];
    endcase
  end
  always@(fetchStage$pipelines_0_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_0_first[191:189])
      3'd0, 3'd2:
	  IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14234 =
	      coreFix_memExe_lsq$enqLdTag[3:0];
      default: IF_fetchStage_pipelines_0_first__2928_BITS_191_ETC___d14234 =
		   coreFix_memExe_lsq$enqStTag[3:0];
    endcase
  end
  always@(fetchStage$pipelines_1_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_1_first[191:189])
      3'd0, 3'd2:
	  IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14395 =
	      coreFix_memExe_lsq$enqLdTag[3:0];
      default: IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14395 =
		   coreFix_memExe_lsq$enqStTag[3:0];
    endcase
  end
  always@(fetchStage$pipelines_1_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_1_first[191:189])
      3'd0, 3'd2:
	  IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14393 =
	      !coreFix_memExe_lsq$enqLdTag[5];
      default: IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14393 =
		   !coreFix_memExe_lsq$enqStTag[5];
    endcase
  end
  always@(fetchStage$pipelines_1_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_1_first[191:189])
      3'd0, 3'd2:
	  IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14392 =
	      coreFix_memExe_lsq$enqLdTag[5];
      default: IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14392 =
		   coreFix_memExe_lsq$enqStTag[5];
    endcase
  end
  always@(fetchStage$pipelines_1_first or
	  coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
  begin
    case (fetchStage$pipelines_1_first[191:189])
      3'd0, 3'd2:
	  IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14394 =
	      coreFix_memExe_lsq$enqLdTag[4:0];
      default: IF_fetchStage_pipelines_1_first__2937_BITS_191_ETC___d14394 =
		   coreFix_memExe_lsq$enqStTag[4:0];
    endcase
  end
  always@(rob$deqPort_0_deq_data)
  begin
    case (rob$deqPort_0_deq_data[180:169])
      12'd1:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd0;
      12'd2:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd1;
      12'd3:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd2;
      12'd256:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd8;
      12'd260:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd9;
      12'd261:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd10;
      12'd262:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd11;
      12'd320:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd12;
      12'd321:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd13;
      12'd322:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd14;
      12'd323:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd15;
      12'd324:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd16;
      12'd384:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd17;
      12'd768:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd18;
      12'd769:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd19;
      12'd770:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd20;
      12'd771:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd21;
      12'd772:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd22;
      12'd773:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd23;
      12'd774:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd24;
      12'd832:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd25;
      12'd833:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd26;
      12'd834:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd27;
      12'd835:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd28;
      12'd836:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd29;
      12'd1952:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd36;
      12'd1953:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd37;
      12'd1954:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd38;
      12'd1955:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd39;
      12'd2048:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd6;
      12'd2049:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd7;
      12'd2816:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd30;
      12'd2818:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd31;
      12'd3072:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd3;
      12'd3073:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd4;
      12'd3074:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd5;
      12'd3857:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd32;
      12'd3858:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd33;
      12'd3859:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd34;
      12'd3860:
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 = 6'd35;
      default: IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 =
		   6'd40;
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q236 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[511:448];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q236 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[511:448];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q237 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[447:384];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q237 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[447:384];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q238 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[383:320];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q238 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[383:320];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q239 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[319:256];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q239 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[319:256];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q240 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[255:192];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q240 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[255:192];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q241 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[191:128];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q241 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[191:128];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd0:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226];
      3'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = 3'd4;
      3'd2:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = 3'd3;
      3'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = 3'd2;
      3'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 = 3'd1;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10828 =
		   3'd0;
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or
	  coreFix_memExe_stb$deq or
	  coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2178 or
	  IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2236)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79])
      3'd0, 3'd2, 3'd4:
	  IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2528 =
	      coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0];
      3'd1:
	  IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2528 =
	      { coreFix_memExe_stb$deq[575] ?
		  coreFix_memExe_stb$deq[511:504] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:504],
		coreFix_memExe_stb$deq[574] ?
		  coreFix_memExe_stb$deq[503:496] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[503:496],
		coreFix_memExe_stb$deq[573] ?
		  coreFix_memExe_stb$deq[495:488] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[495:488],
		coreFix_memExe_stb$deq[572] ?
		  coreFix_memExe_stb$deq[487:480] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[487:480],
		coreFix_memExe_stb$deq[571] ?
		  coreFix_memExe_stb$deq[479:472] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[479:472],
		coreFix_memExe_stb$deq[570] ?
		  coreFix_memExe_stb$deq[471:464] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[471:464],
		coreFix_memExe_stb$deq[569] ?
		  coreFix_memExe_stb$deq[463:456] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[463:456],
		coreFix_memExe_stb$deq[568] ?
		  coreFix_memExe_stb$deq[455:448] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[455:448],
		coreFix_memExe_stb$deq[567] ?
		  coreFix_memExe_stb$deq[447:440] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:440],
		coreFix_memExe_stb$deq[566] ?
		  coreFix_memExe_stb$deq[439:432] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[439:432],
		coreFix_memExe_stb$deq[565] ?
		  coreFix_memExe_stb$deq[431:424] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[431:424],
		coreFix_memExe_stb$deq[564] ?
		  coreFix_memExe_stb$deq[423:416] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[423:416],
		coreFix_memExe_stb$deq[563] ?
		  coreFix_memExe_stb$deq[415:408] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[415:408],
		coreFix_memExe_stb$deq[562] ?
		  coreFix_memExe_stb$deq[407:400] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[407:400],
		coreFix_memExe_stb$deq[561] ?
		  coreFix_memExe_stb$deq[399:392] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[399:392],
		coreFix_memExe_stb$deq[560] ?
		  coreFix_memExe_stb$deq[391:384] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[391:384],
		coreFix_memExe_stb$deq[559] ?
		  coreFix_memExe_stb$deq[383:376] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:376],
		coreFix_memExe_stb$deq[558] ?
		  coreFix_memExe_stb$deq[375:368] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[375:368],
		coreFix_memExe_stb$deq[557] ?
		  coreFix_memExe_stb$deq[367:360] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[367:360],
		coreFix_memExe_stb$deq[556] ?
		  coreFix_memExe_stb$deq[359:352] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[359:352],
		coreFix_memExe_stb$deq[555] ?
		  coreFix_memExe_stb$deq[351:344] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[351:344],
		coreFix_memExe_stb$deq[554] ?
		  coreFix_memExe_stb$deq[343:336] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[343:336],
		coreFix_memExe_stb$deq[553] ?
		  coreFix_memExe_stb$deq[335:328] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[335:328],
		coreFix_memExe_stb$deq[552] ?
		  coreFix_memExe_stb$deq[327:320] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[327:320],
		coreFix_memExe_stb$deq[551] ?
		  coreFix_memExe_stb$deq[319:312] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:312],
		coreFix_memExe_stb$deq[550] ?
		  coreFix_memExe_stb$deq[311:304] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[311:304],
		coreFix_memExe_stb$deq[549] ?
		  coreFix_memExe_stb$deq[303:296] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[303:296],
		coreFix_memExe_stb$deq[548] ?
		  coreFix_memExe_stb$deq[295:288] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[295:288],
		coreFix_memExe_stb$deq[547] ?
		  coreFix_memExe_stb$deq[287:280] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[287:280],
		coreFix_memExe_stb$deq[546] ?
		  coreFix_memExe_stb$deq[279:272] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[279:272],
		coreFix_memExe_stb$deq[545] ?
		  coreFix_memExe_stb$deq[271:264] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[271:264],
		coreFix_memExe_stb$deq[544] ?
		  coreFix_memExe_stb$deq[263:256] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[263:256],
		coreFix_memExe_stb$deq[543] ?
		  coreFix_memExe_stb$deq[255:248] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:248],
		coreFix_memExe_stb$deq[542] ?
		  coreFix_memExe_stb$deq[247:240] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[247:240],
		coreFix_memExe_stb$deq[541] ?
		  coreFix_memExe_stb$deq[239:232] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[239:232],
		coreFix_memExe_stb$deq[540] ?
		  coreFix_memExe_stb$deq[231:224] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[231:224],
		coreFix_memExe_stb$deq[539] ?
		  coreFix_memExe_stb$deq[223:216] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[223:216],
		coreFix_memExe_stb$deq[538] ?
		  coreFix_memExe_stb$deq[215:208] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[215:208],
		coreFix_memExe_stb$deq[537] ?
		  coreFix_memExe_stb$deq[207:200] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[207:200],
		coreFix_memExe_stb$deq[536] ?
		  coreFix_memExe_stb$deq[199:192] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[199:192],
		coreFix_memExe_stb$deq[535] ?
		  coreFix_memExe_stb$deq[191:184] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:184],
		coreFix_memExe_stb$deq[534] ?
		  coreFix_memExe_stb$deq[183:176] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[183:176],
		coreFix_memExe_stb$deq[533] ?
		  coreFix_memExe_stb$deq[175:168] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[175:168],
		coreFix_memExe_stb$deq[532] ?
		  coreFix_memExe_stb$deq[167:160] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[167:160],
		coreFix_memExe_stb$deq[531] ?
		  coreFix_memExe_stb$deq[159:152] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[159:152],
		coreFix_memExe_stb$deq[530] ?
		  coreFix_memExe_stb$deq[151:144] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[151:144],
		coreFix_memExe_stb$deq[529] ?
		  coreFix_memExe_stb$deq[143:136] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[143:136],
		coreFix_memExe_stb$deq[528] ?
		  coreFix_memExe_stb$deq[135:128] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[135:128],
		coreFix_memExe_stb$deq[527] ?
		  coreFix_memExe_stb$deq[127:120] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:120],
		coreFix_memExe_stb$deq[526] ?
		  coreFix_memExe_stb$deq[119:112] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[119:112],
		coreFix_memExe_stb$deq[525] ?
		  coreFix_memExe_stb$deq[111:104] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[111:104],
		coreFix_memExe_stb$deq[524] ?
		  coreFix_memExe_stb$deq[103:96] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[103:96],
		coreFix_memExe_stb$deq[523] ?
		  coreFix_memExe_stb$deq[95:88] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[95:88],
		coreFix_memExe_stb$deq[522] ?
		  coreFix_memExe_stb$deq[87:80] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[87:80],
		coreFix_memExe_stb$deq[521] ?
		  coreFix_memExe_stb$deq[79:72] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[79:72],
		coreFix_memExe_stb$deq[520] ?
		  coreFix_memExe_stb$deq[71:64] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[71:64],
		coreFix_memExe_stb$deq[519] ?
		  coreFix_memExe_stb$deq[63:56] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:56],
		coreFix_memExe_stb$deq[518] ?
		  coreFix_memExe_stb$deq[55:48] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[55:48],
		coreFix_memExe_stb$deq[517] ?
		  coreFix_memExe_stb$deq[47:40] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[47:40],
		coreFix_memExe_stb$deq[516] ?
		  coreFix_memExe_stb$deq[39:32] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[39:32],
		coreFix_memExe_stb$deq[515] ?
		  coreFix_memExe_stb$deq[31:24] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[31:24],
		coreFix_memExe_stb$deq[514] ?
		  coreFix_memExe_stb$deq[23:16] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[23:16],
		coreFix_memExe_stb$deq[513] ?
		  coreFix_memExe_stb$deq[15:8] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[15:8],
		coreFix_memExe_stb$deq[512] ?
		  coreFix_memExe_stb$deq[7:0] :
		  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[7:0] };
      3'd3:
	  IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2528 =
	      coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2178 ?
		IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2236 :
		coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0];
      default: IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2528 =
		   coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
      3'd4, 3'd3, 3'd2, 3'd1, 3'd0:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[228:226];
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242 = 3'd7;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9995 or
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9285 or
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10051)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
      5'd0, 5'd1:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10055 =
	      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9285;
      5'd25:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10055 =
	      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9995;
      5'd26, 5'd27:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10055 =
	      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10051;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10055 =
		   IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9995;
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q243 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[130:67];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q243 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[130:67];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q244 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[66:3];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q244 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[66:3];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[127:64];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[127:64];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[63:0];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[63:0];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[578:515];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[578:515];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[514:513];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 =
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[514:513];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 =
	      !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[512];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 =
	      !coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[512];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[517:516];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[517:516];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251 =
	      !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[515];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251 =
	      !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[515];
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq or
	  coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq or
	  coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq or
	  coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
      5'd0, 5'd1, 5'd2, 5'd25, 5'd26, 5'd27, 5'd28:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8520 =
	      coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq;
      5'd3:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8520 =
	      coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq;
      5'd4:
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8520 =
	      coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq;
      default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d8520 =
		   coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_enq_ETC___d8538 or
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit or
	  coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[229:228])
      2'd0, 2'd1:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q252 =
	      coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit != 2'd0 &&
	      coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq;
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q252 =
		   coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_enq_ETC___d8538;
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253 =
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[5:4];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253 =
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[5:4];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254 =
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[3];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254 =
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[3];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255 =
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[2:0];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255 =
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[2:0];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q256 =
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[71:8];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q256 =
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[71:8];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q257 =
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[7:6];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q257 =
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[7:6];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258 =
	      !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258 =
	      !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582];
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582];
    endcase
  end
  always@(rob$deqPort_0_deq_data)
  begin
    case (rob$deqPort_0_deq_data[165:162])
      4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9:
	  CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q260 =
	      rob$deqPort_0_deq_data[165:162];
      default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q260 =
		   4'd11;
    endcase
  end
  always@(rob$deqPort_0_deq_data)
  begin
    case (rob$deqPort_0_deq_data[165:162])
      4'd0,
      4'd1,
      4'd2,
      4'd3,
      4'd4,
      4'd5,
      4'd6,
      4'd7,
      4'd8,
      4'd9,
      4'd11,
      4'd12,
      4'd13:
	  CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q261 =
	      rob$deqPort_0_deq_data[165:162];
      default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q261 =
		   4'd15;
    endcase
  end
  always@(mmio_dataReqQ_data_0)
  begin
    case (mmio_dataReqQ_data_0[77:76])
      2'd0, 2'd1, 2'd2:
	  CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q263 =
	      mmio_dataReqQ_data_0[77:72];
      2'd3:
	  CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q263 =
	      { 2'd3, mmio_dataReqQ_data_0[75:72] };
    endcase
  end
  always@(coreFix_memExe_lsq$firstSt)
  begin
    case (coreFix_memExe_lsq$firstSt[3:0])
      4'd0,
      4'd1,
      4'd2,
      4'd3,
      4'd4,
      4'd5,
      4'd6,
      4'd7,
      4'd8,
      4'd9,
      4'd11,
      4'd12,
      4'd13:
	  CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264 =
	      coreFix_memExe_lsq$firstSt[3:0];
      default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264 =
		   4'd15;
    endcase
  end
  always@(coreFix_memExe_lsq$firstLd)
  begin
    case (coreFix_memExe_lsq$firstLd[6:3])
      4'd0,
      4'd1,
      4'd2,
      4'd3,
      4'd4,
      4'd5,
      4'd6,
      4'd7,
      4'd8,
      4'd9,
      4'd11,
      4'd12,
      4'd13:
	  CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q265 =
	      coreFix_memExe_lsq$firstLd[6:3];
      default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q265 =
		   4'd15;
    endcase
  end
  always@(mmioToPlatform_pRq_enq_x)
  begin
    case (mmioToPlatform_pRq_enq_x[37:36])
      2'd0, 2'd1, 2'd2:
	  CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q266 =
	      mmioToPlatform_pRq_enq_x[37:32];
      2'd3:
	  CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q266 =
	      { 2'd3, mmioToPlatform_pRq_enq_x[35:32] };
    endcase
  end
  always@(coreFix_aluExe_0_rsAlu$dispatchData)
  begin
    case (coreFix_aluExe_0_rsAlu$dispatchData[139:137])
      3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
	  CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267 =
	      coreFix_aluExe_0_rsAlu$dispatchData[139:137];
      default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267 = 3'd7;
    endcase
  end
  always@(coreFix_aluExe_0_rsAlu$dispatchData or
	  CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267)
  begin
    case (coreFix_aluExe_0_rsAlu$dispatchData[156:154])
      3'd0, 3'd1, 3'd2, 3'd3:
	  CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268 =
	      coreFix_aluExe_0_rsAlu$dispatchData[156:136];
      3'd4:
	  CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268 =
	      { coreFix_aluExe_0_rsAlu$dispatchData[156:154],
		9'h0AA,
		coreFix_aluExe_0_rsAlu$dispatchData[144:140],
		CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267,
		coreFix_aluExe_0_rsAlu$dispatchData[136] };
      default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268 =
		   21'd1485482;
    endcase
  end
  always@(coreFix_aluExe_0_rsAlu$dispatchData)
  begin
    case (coreFix_aluExe_0_rsAlu$dispatchData[134:123])
      12'd1,
      12'd2,
      12'd3,
      12'd256,
      12'd260,
      12'd261,
      12'd262,
      12'd320,
      12'd321,
      12'd322,
      12'd323,
      12'd324,
      12'd384,
      12'd768,
      12'd769,
      12'd770,
      12'd771,
      12'd772,
      12'd773,
      12'd774,
      12'd832,
      12'd833,
      12'd834,
      12'd835,
      12'd836,
      12'd1952,
      12'd1953,
      12'd1954,
      12'd1955,
      12'd2048,
      12'd2049,
      12'd2816,
      12'd2818,
      12'd3072,
      12'd3073,
      12'd3074,
      12'd3857,
      12'd3858,
      12'd3859,
      12'd3860:
	  CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q269 =
	      coreFix_aluExe_0_rsAlu$dispatchData[134:123];
      default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q269 =
		   12'd2303;
    endcase
  end
  always@(coreFix_aluExe_0_dispToRegQ$first)
  begin
    case (coreFix_aluExe_0_dispToRegQ$first[135:133])
      3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
	  CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q270 =
	      coreFix_aluExe_0_dispToRegQ$first[135:133];
      default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q270 = 3'd7;
    endcase
  end
  always@(coreFix_aluExe_0_dispToRegQ$first or
	  CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q270)
  begin
    case (coreFix_aluExe_0_dispToRegQ$first[152:150])
      3'd0, 3'd1, 3'd2, 3'd3:
	  CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q271 =
	      coreFix_aluExe_0_dispToRegQ$first[152:132];
      3'd4:
	  CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q271 =
	      { coreFix_aluExe_0_dispToRegQ$first[152:150],
		9'h0AA,
		coreFix_aluExe_0_dispToRegQ$first[140:136],
		CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q270,
		coreFix_aluExe_0_dispToRegQ$first[132] };
      default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q271 =
		   21'd1485482;
    endcase
  end
  always@(coreFix_aluExe_0_dispToRegQ$first)
  begin
    case (coreFix_aluExe_0_dispToRegQ$first[130:119])
      12'd1,
      12'd2,
      12'd3,
      12'd256,
      12'd260,
      12'd261,
      12'd262,
      12'd320,
      12'd321,
      12'd322,
      12'd323,
      12'd324,
      12'd384,
      12'd768,
      12'd769,
      12'd770,
      12'd771,
      12'd772,
      12'd773,
      12'd774,
      12'd832,
      12'd833,
      12'd834,
      12'd835,
      12'd836,
      12'd1952,
      12'd1953,
      12'd1954,
      12'd1955,
      12'd2048,
      12'd2049,
      12'd2816,
      12'd2818,
      12'd3072,
      12'd3073,
      12'd3074,
      12'd3857,
      12'd3858,
      12'd3859,
      12'd3860:
	  CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q272 =
	      coreFix_aluExe_0_dispToRegQ$first[130:119];
      default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q272 =
		   12'd2303;
    endcase
  end
  always@(coreFix_aluExe_1_rsAlu$dispatchData)
  begin
    case (coreFix_aluExe_1_rsAlu$dispatchData[139:137])
      3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
	  CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q273 =
	      coreFix_aluExe_1_rsAlu$dispatchData[139:137];
      default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q273 = 3'd7;
    endcase
  end
  always@(coreFix_aluExe_1_rsAlu$dispatchData or
	  CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q273)
  begin
    case (coreFix_aluExe_1_rsAlu$dispatchData[156:154])
      3'd0, 3'd1, 3'd2, 3'd3:
	  CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274 =
	      coreFix_aluExe_1_rsAlu$dispatchData[156:136];
      3'd4:
	  CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274 =
	      { coreFix_aluExe_1_rsAlu$dispatchData[156:154],
		9'h0AA,
		coreFix_aluExe_1_rsAlu$dispatchData[144:140],
		CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q273,
		coreFix_aluExe_1_rsAlu$dispatchData[136] };
      default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274 =
		   21'd1485482;
    endcase
  end
  always@(coreFix_aluExe_1_rsAlu$dispatchData)
  begin
    case (coreFix_aluExe_1_rsAlu$dispatchData[134:123])
      12'd1,
      12'd2,
      12'd3,
      12'd256,
      12'd260,
      12'd261,
      12'd262,
      12'd320,
      12'd321,
      12'd322,
      12'd323,
      12'd324,
      12'd384,
      12'd768,
      12'd769,
      12'd770,
      12'd771,
      12'd772,
      12'd773,
      12'd774,
      12'd832,
      12'd833,
      12'd834,
      12'd835,
      12'd836,
      12'd1952,
      12'd1953,
      12'd1954,
      12'd1955,
      12'd2048,
      12'd2049,
      12'd2816,
      12'd2818,
      12'd3072,
      12'd3073,
      12'd3074,
      12'd3857,
      12'd3858,
      12'd3859,
      12'd3860:
	  CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q275 =
	      coreFix_aluExe_1_rsAlu$dispatchData[134:123];
      default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q275 =
		   12'd2303;
    endcase
  end
  always@(coreFix_aluExe_1_dispToRegQ$first)
  begin
    case (coreFix_aluExe_1_dispToRegQ$first[135:133])
      3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
	  CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q276 =
	      coreFix_aluExe_1_dispToRegQ$first[135:133];
      default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q276 = 3'd7;
    endcase
  end
  always@(coreFix_aluExe_1_dispToRegQ$first or
	  CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q276)
  begin
    case (coreFix_aluExe_1_dispToRegQ$first[152:150])
      3'd0, 3'd1, 3'd2, 3'd3:
	  CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q277 =
	      coreFix_aluExe_1_dispToRegQ$first[152:132];
      3'd4:
	  CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q277 =
	      { coreFix_aluExe_1_dispToRegQ$first[152:150],
		9'h0AA,
		coreFix_aluExe_1_dispToRegQ$first[140:136],
		CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q276,
		coreFix_aluExe_1_dispToRegQ$first[132] };
      default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q277 =
		   21'd1485482;
    endcase
  end
  always@(coreFix_aluExe_1_dispToRegQ$first)
  begin
    case (coreFix_aluExe_1_dispToRegQ$first[130:119])
      12'd1,
      12'd2,
      12'd3,
      12'd256,
      12'd260,
      12'd261,
      12'd262,
      12'd320,
      12'd321,
      12'd322,
      12'd323,
      12'd324,
      12'd384,
      12'd768,
      12'd769,
      12'd770,
      12'd771,
      12'd772,
      12'd773,
      12'd774,
      12'd832,
      12'd833,
      12'd834,
      12'd835,
      12'd836,
      12'd1952,
      12'd1953,
      12'd1954,
      12'd1955,
      12'd2048,
      12'd2049,
      12'd2816,
      12'd2818,
      12'd3072,
      12'd3073,
      12'd3074,
      12'd3857,
      12'd3858,
      12'd3859,
      12'd3860:
	  CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q278 =
	      coreFix_aluExe_1_dispToRegQ$first[130:119];
      default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q278 =
		   12'd2303;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData)
  begin
    case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67])
      3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
	  CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279 =
	      coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67];
      default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279 = 3'd7;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData or
	  CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279)
  begin
    case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:84])
      3'd0, 3'd1, 3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q280 =
	      coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:66];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q280 =
	      { coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:84],
		9'h0AA,
		coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[74:70],
		CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279,
		coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[66] };
      default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q280 =
		   21'd1485482;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9285 or
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10765 or
	  IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10818 or
	  IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10763)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
      5'd0:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281 =
	      IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10765;
      5'd1:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281 =
	      coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
		{ !coreFix_fpuMulDivExe_0_regToExeQ$first[139],
		  coreFix_fpuMulDivExe_0_regToExeQ$first[138:76] } :
		{ IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10818,
		  IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10763 };
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281 =
		   IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d9285;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
	  IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10765)
  begin
    case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
      5'd0, 5'd1:
	  CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q282 =
	      64'h3FF0000000000000;
      default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q282 =
		   IF_coreFix_fpuMulDivExe_0_regToExeQ_first__482_ETC___d10765;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_dispToRegQ$first)
  begin
    case (coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58])
      3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
	  CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283 =
	      coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58];
      default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283 = 3'd7;
    endcase
  end
  always@(coreFix_fpuMulDivExe_0_dispToRegQ$first or
	  CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283)
  begin
    case (coreFix_fpuMulDivExe_0_dispToRegQ$first[77:75])
      3'd0, 3'd1, 3'd2, 3'd3:
	  CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q284 =
	      coreFix_fpuMulDivExe_0_dispToRegQ$first[77:57];
      3'd4:
	  CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q284 =
	      { coreFix_fpuMulDivExe_0_dispToRegQ$first[77:75],
		9'h0AA,
		coreFix_fpuMulDivExe_0_dispToRegQ$first[65:61],
		CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283,
		coreFix_fpuMulDivExe_0_dispToRegQ$first[57] };
      default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q284 =
		   21'd1485482;
    endcase
  end
  always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
  begin
    case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
      1'd0:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q285 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[1:0];
      1'd1:
	  CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q285 =
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[1:0];
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        commitStage_commitTrap <= `BSV_ASSIGNMENT_DELAY
	    166'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	commitStage_rg_serial_num <= `BSV_ASSIGNMENT_DELAY 64'd0;
	coreFix_doStatsReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt <= `BSV_ASSIGNMENT_DELAY
	    4'd0;
	coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit <= `BSV_ASSIGNMENT_DELAY
	    2'd3;
	coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0 <= `BSV_ASSIGNMENT_DELAY
	    129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1 <= `BSV_ASSIGNMENT_DELAY
	    129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0 <= `BSV_ASSIGNMENT_DELAY
	    129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1 <= `BSV_ASSIGNMENT_DELAY
	    129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0 <= `BSV_ASSIGNMENT_DELAY
	    129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1 <= `BSV_ASSIGNMENT_DELAY
	    129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 <= `BSV_ASSIGNMENT_DELAY
	    3'd2;
	coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 <= `BSV_ASSIGNMENT_DELAY
	    3'd2;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	    3'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 <= `BSV_ASSIGNMENT_DELAY
	    3'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 <= `BSV_ASSIGNMENT_DELAY
	    3'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 <= `BSV_ASSIGNMENT_DELAY
	    3'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 <= `BSV_ASSIGNMENT_DELAY
	    3'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 <= `BSV_ASSIGNMENT_DELAY
	    3'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 <= `BSV_ASSIGNMENT_DELAY
	    3'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 <= `BSV_ASSIGNMENT_DELAY
	    3'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP <= `BSV_ASSIGNMENT_DELAY
	    3'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty <= `BSV_ASSIGNMENT_DELAY
	    1'd1;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP <= `BSV_ASSIGNMENT_DELAY
	    3'd0;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    4'd2;
	coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	    583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA80000000000000000;
	coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
	    583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA80000000000000000;
	coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty <= `BSV_ASSIGNMENT_DELAY
	    1'd1;
	coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    584'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl <= `BSV_ASSIGNMENT_DELAY
	    59'h2AAAAAAAAAAAAAA;
	coreFix_memExe_dMem_cache_m_banks_0_processAmo <= `BSV_ASSIGNMENT_DELAY
	    161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
	    153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
	    1'd1;
	coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	    72'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
	    72'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY
	    1'd1;
	coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    73'h0AAAAAAAAAAAAAAAAAA;
	coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	    579'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
	    579'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty <= `BSV_ASSIGNMENT_DELAY
	    1'd1;
	coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    580'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	    1'd0;
	coreFix_memExe_dMem_perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 4'd0;
	coreFix_memExe_dMem_perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_dMem_perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	coreFix_memExe_dMem_perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 5'd10;
	coreFix_memExe_dMem_perfReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_forwardQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_forwardQ_data_0 <= `BSV_ASSIGNMENT_DELAY 69'd0;
	coreFix_memExe_forwardQ_data_1 <= `BSV_ASSIGNMENT_DELAY 69'd0;
	coreFix_memExe_forwardQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_forwardQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_forwardQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	coreFix_memExe_forwardQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_forwardQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    70'h0AAAAAAAAAAAAAAAAA;
	coreFix_memExe_forwardQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_memRespLdQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_memRespLdQ_data_0 <= `BSV_ASSIGNMENT_DELAY 69'd0;
	coreFix_memExe_memRespLdQ_data_1 <= `BSV_ASSIGNMENT_DELAY 69'd0;
	coreFix_memExe_memRespLdQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_memRespLdQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_memRespLdQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	coreFix_memExe_memRespLdQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_memRespLdQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    70'h0AAAAAAAAAAAAAAAAA;
	coreFix_memExe_memRespLdQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_reqLdQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
	    69'h0AAAAAAAAAAAAAAAAA;
	coreFix_memExe_reqLdQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
	coreFix_memExe_reqLdQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_reqLrScAmoQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
	    153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	coreFix_memExe_reqLrScAmoQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
	coreFix_memExe_reqLrScAmoQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_reqStQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
	    66'h2AAAAAAAAAAAAAAAA;
	coreFix_memExe_reqStQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
	coreFix_memExe_reqStQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_respLrScAmoQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_respLrScAmoQ_data_0 <= `BSV_ASSIGNMENT_DELAY 64'd0;
	coreFix_memExe_respLrScAmoQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_respLrScAmoQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	coreFix_memExe_respLrScAmoQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    65'h0AAAAAAAAAAAAAAAA;
	coreFix_memExe_respLrScAmoQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	coreFix_memExe_waitLrScAmoMMIOResp <= `BSV_ASSIGNMENT_DELAY 3'd0;
	csrInstOrInterruptInflight_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_external_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_external_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_external_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_external_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_external_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_external_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_fflags_reg <= `BSV_ASSIGNMENT_DELAY 5'd0;
	csrf_frm_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
	csrf_fs_reg <= `BSV_ASSIGNMENT_DELAY 2'b01;
	csrf_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_mcause_code_reg <= `BSV_ASSIGNMENT_DELAY 4'd0;
	csrf_mcause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_mcounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_mcounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_mcounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_mcycle_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY 64'd0;
	csrf_medeleg_13_11_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
	csrf_medeleg_15_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_medeleg_9_0_reg <= `BSV_ASSIGNMENT_DELAY 10'd0;
	csrf_mepc_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
	csrf_mideleg_11_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_mideleg_1_0_reg <= `BSV_ASSIGNMENT_DELAY 2'd0;
	csrf_mideleg_5_3_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
	csrf_mideleg_9_7_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
	csrf_minstret_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY 64'd0;
	csrf_mpp_reg <= `BSV_ASSIGNMENT_DELAY 2'd0;
	csrf_mprv_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_mscratch_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
	csrf_mtval_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
	csrf_mtvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY 62'd0;
	csrf_mtvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_mxr_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_ppn_reg <= `BSV_ASSIGNMENT_DELAY 44'd0;
	csrf_prev_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_prev_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_prev_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_prv_reg <= `BSV_ASSIGNMENT_DELAY 2'd3;
	csrf_rg_tdata1_data <= `BSV_ASSIGNMENT_DELAY 59'd0;
	csrf_rg_tdata1_dmode <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_rg_tselect <= `BSV_ASSIGNMENT_DELAY 64'd0;
	csrf_scause_code_reg <= `BSV_ASSIGNMENT_DELAY 4'd0;
	csrf_scause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_scounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_scounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_scounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_sepc_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
	csrf_software_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_software_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_software_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_software_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_software_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_software_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_spp_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_sscratch_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
	csrf_stats_module_doStats <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_stval_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
	csrf_stvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY 62'd0;
	csrf_stvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_sum_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_time_reg <= `BSV_ASSIGNMENT_DELAY 64'd0;
	csrf_timer_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_timer_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_timer_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_timer_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_timer_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_timer_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_tsr_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_tvm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_tw_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	csrf_vm_mode_sv39_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	flush_reservation <= `BSV_ASSIGNMENT_DELAY 1'd0;
	flush_tlbs <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_cRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_cRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	    142'h000000000000000004000000000000000000;
	mmio_cRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_cRqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	mmio_cRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	mmio_cRqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_cRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_cRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_cRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_cRsQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	mmio_cRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 2'd0;
	mmio_cRsQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_dataPendQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_dataPendQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_dataPendQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	mmio_dataPendQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_dataPendQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_dataReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_dataReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	    142'h000000000000000004000000000000000000;
	mmio_dataReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_dataReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	mmio_dataReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
	mmio_dataReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_dataRespQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_dataRespQ_data_0 <= `BSV_ASSIGNMENT_DELAY 65'd0;
	mmio_dataRespQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_dataRespQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	mmio_dataRespQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	    66'h0AAAAAAAAAAAAAAAA;
	mmio_dataRespQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_fromHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0;
	mmio_pRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_pRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 39'h0400000000;
	mmio_pRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_pRqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	mmio_pRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 40'h2AAAAAAAAA;
	mmio_pRqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_pRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_pRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY 67'h155555554AAAAAAAA;
	mmio_pRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_pRsQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
	mmio_pRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 68'h2AAAAAAAAAAAAAAAA;
	mmio_pRsQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	mmio_toHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0;
	outOfReset <= `BSV_ASSIGNMENT_DELAY 1'd0;
	started <= `BSV_ASSIGNMENT_DELAY 1'd0;
	update_vm_info <= `BSV_ASSIGNMENT_DELAY 1'd0;
      end
    else
      begin
        if (commitStage_commitTrap$EN)
	  commitStage_commitTrap <= `BSV_ASSIGNMENT_DELAY
	      commitStage_commitTrap$D_IN;
	if (commitStage_rg_serial_num$EN)
	  commitStage_rg_serial_num <= `BSV_ASSIGNMENT_DELAY
	      commitStage_rg_serial_num$D_IN;
	if (coreFix_doStatsReg$EN)
	  coreFix_doStatsReg <= `BSV_ASSIGNMENT_DELAY coreFix_doStatsReg$D_IN;
	if (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$EN)
	  coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt <= `BSV_ASSIGNMENT_DELAY
	      coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$D_IN;
	if (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$EN)
	  coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init <= `BSV_ASSIGNMENT_DELAY
	      coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$D_IN;
	if (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready$EN)
	  coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready <= `BSV_ASSIGNMENT_DELAY
	      coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready$D_IN;
	if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN)
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit <= `BSV_ASSIGNMENT_DELAY
	      coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN;
	if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0$EN)
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0$D_IN;
	if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1$EN)
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1$D_IN;
	if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0$EN)
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0$D_IN;
	if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1$EN)
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1$D_IN;
	if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0$EN)
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0$D_IN;
	if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1$EN)
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1$D_IN;
	if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$EN)
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$D_IN;
	if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$EN)
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_processAmo$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_processAmo <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN;
	if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$EN)
	  coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$D_IN;
	if (coreFix_memExe_dMem_perfReqQ_clearReq_rl$EN)
	  coreFix_memExe_dMem_perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_perfReqQ_clearReq_rl$D_IN;
	if (coreFix_memExe_dMem_perfReqQ_data_0$EN)
	  coreFix_memExe_dMem_perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_perfReqQ_data_0$D_IN;
	if (coreFix_memExe_dMem_perfReqQ_deqReq_rl$EN)
	  coreFix_memExe_dMem_perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_perfReqQ_deqReq_rl$D_IN;
	if (coreFix_memExe_dMem_perfReqQ_empty$EN)
	  coreFix_memExe_dMem_perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_perfReqQ_empty$D_IN;
	if (coreFix_memExe_dMem_perfReqQ_enqReq_rl$EN)
	  coreFix_memExe_dMem_perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_perfReqQ_enqReq_rl$D_IN;
	if (coreFix_memExe_dMem_perfReqQ_full$EN)
	  coreFix_memExe_dMem_perfReqQ_full <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_dMem_perfReqQ_full$D_IN;
	if (coreFix_memExe_forwardQ_clearReq_rl$EN)
	  coreFix_memExe_forwardQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_forwardQ_clearReq_rl$D_IN;
	if (coreFix_memExe_forwardQ_data_0$EN)
	  coreFix_memExe_forwardQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_forwardQ_data_0$D_IN;
	if (coreFix_memExe_forwardQ_data_1$EN)
	  coreFix_memExe_forwardQ_data_1 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_forwardQ_data_1$D_IN;
	if (coreFix_memExe_forwardQ_deqP$EN)
	  coreFix_memExe_forwardQ_deqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_forwardQ_deqP$D_IN;
	if (coreFix_memExe_forwardQ_deqReq_rl$EN)
	  coreFix_memExe_forwardQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_forwardQ_deqReq_rl$D_IN;
	if (coreFix_memExe_forwardQ_empty$EN)
	  coreFix_memExe_forwardQ_empty <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_forwardQ_empty$D_IN;
	if (coreFix_memExe_forwardQ_enqP$EN)
	  coreFix_memExe_forwardQ_enqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_forwardQ_enqP$D_IN;
	if (coreFix_memExe_forwardQ_enqReq_rl$EN)
	  coreFix_memExe_forwardQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_forwardQ_enqReq_rl$D_IN;
	if (coreFix_memExe_forwardQ_full$EN)
	  coreFix_memExe_forwardQ_full <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_forwardQ_full$D_IN;
	if (coreFix_memExe_memRespLdQ_clearReq_rl$EN)
	  coreFix_memExe_memRespLdQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_memRespLdQ_clearReq_rl$D_IN;
	if (coreFix_memExe_memRespLdQ_data_0$EN)
	  coreFix_memExe_memRespLdQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_memRespLdQ_data_0$D_IN;
	if (coreFix_memExe_memRespLdQ_data_1$EN)
	  coreFix_memExe_memRespLdQ_data_1 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_memRespLdQ_data_1$D_IN;
	if (coreFix_memExe_memRespLdQ_deqP$EN)
	  coreFix_memExe_memRespLdQ_deqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_memRespLdQ_deqP$D_IN;
	if (coreFix_memExe_memRespLdQ_deqReq_rl$EN)
	  coreFix_memExe_memRespLdQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_memRespLdQ_deqReq_rl$D_IN;
	if (coreFix_memExe_memRespLdQ_empty$EN)
	  coreFix_memExe_memRespLdQ_empty <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_memRespLdQ_empty$D_IN;
	if (coreFix_memExe_memRespLdQ_enqP$EN)
	  coreFix_memExe_memRespLdQ_enqP <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_memRespLdQ_enqP$D_IN;
	if (coreFix_memExe_memRespLdQ_enqReq_rl$EN)
	  coreFix_memExe_memRespLdQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_memRespLdQ_enqReq_rl$D_IN;
	if (coreFix_memExe_memRespLdQ_full$EN)
	  coreFix_memExe_memRespLdQ_full <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_memRespLdQ_full$D_IN;
	if (coreFix_memExe_reqLdQ_data_0_rl$EN)
	  coreFix_memExe_reqLdQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_reqLdQ_data_0_rl$D_IN;
	if (coreFix_memExe_reqLdQ_empty_rl$EN)
	  coreFix_memExe_reqLdQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_reqLdQ_empty_rl$D_IN;
	if (coreFix_memExe_reqLdQ_full_rl$EN)
	  coreFix_memExe_reqLdQ_full_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_reqLdQ_full_rl$D_IN;
	if (coreFix_memExe_reqLrScAmoQ_data_0_rl$EN)
	  coreFix_memExe_reqLrScAmoQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN;
	if (coreFix_memExe_reqLrScAmoQ_empty_rl$EN)
	  coreFix_memExe_reqLrScAmoQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_reqLrScAmoQ_empty_rl$D_IN;
	if (coreFix_memExe_reqLrScAmoQ_full_rl$EN)
	  coreFix_memExe_reqLrScAmoQ_full_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_reqLrScAmoQ_full_rl$D_IN;
	if (coreFix_memExe_reqStQ_data_0_rl$EN)
	  coreFix_memExe_reqStQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_reqStQ_data_0_rl$D_IN;
	if (coreFix_memExe_reqStQ_empty_rl$EN)
	  coreFix_memExe_reqStQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_reqStQ_empty_rl$D_IN;
	if (coreFix_memExe_reqStQ_full_rl$EN)
	  coreFix_memExe_reqStQ_full_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_reqStQ_full_rl$D_IN;
	if (coreFix_memExe_respLrScAmoQ_clearReq_rl$EN)
	  coreFix_memExe_respLrScAmoQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_respLrScAmoQ_clearReq_rl$D_IN;
	if (coreFix_memExe_respLrScAmoQ_data_0$EN)
	  coreFix_memExe_respLrScAmoQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_respLrScAmoQ_data_0$D_IN;
	if (coreFix_memExe_respLrScAmoQ_deqReq_rl$EN)
	  coreFix_memExe_respLrScAmoQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_respLrScAmoQ_deqReq_rl$D_IN;
	if (coreFix_memExe_respLrScAmoQ_empty$EN)
	  coreFix_memExe_respLrScAmoQ_empty <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_respLrScAmoQ_empty$D_IN;
	if (coreFix_memExe_respLrScAmoQ_enqReq_rl$EN)
	  coreFix_memExe_respLrScAmoQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN;
	if (coreFix_memExe_respLrScAmoQ_full$EN)
	  coreFix_memExe_respLrScAmoQ_full <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_respLrScAmoQ_full$D_IN;
	if (coreFix_memExe_waitLrScAmoMMIOResp$EN)
	  coreFix_memExe_waitLrScAmoMMIOResp <= `BSV_ASSIGNMENT_DELAY
	      coreFix_memExe_waitLrScAmoMMIOResp$D_IN;
	if (csrInstOrInterruptInflight_rl$EN)
	  csrInstOrInterruptInflight_rl <= `BSV_ASSIGNMENT_DELAY
	      csrInstOrInterruptInflight_rl$D_IN;
	if (csrf_external_int_en_vec_0$EN)
	  csrf_external_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY
	      csrf_external_int_en_vec_0$D_IN;
	if (csrf_external_int_en_vec_1$EN)
	  csrf_external_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY
	      csrf_external_int_en_vec_1$D_IN;
	if (csrf_external_int_en_vec_3$EN)
	  csrf_external_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY
	      csrf_external_int_en_vec_3$D_IN;
	if (csrf_external_int_pend_vec_0$EN)
	  csrf_external_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY
	      csrf_external_int_pend_vec_0$D_IN;
	if (csrf_external_int_pend_vec_1$EN)
	  csrf_external_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY
	      csrf_external_int_pend_vec_1$D_IN;
	if (csrf_external_int_pend_vec_3$EN)
	  csrf_external_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY
	      csrf_external_int_pend_vec_3$D_IN;
	if (csrf_fflags_reg$EN)
	  csrf_fflags_reg <= `BSV_ASSIGNMENT_DELAY csrf_fflags_reg$D_IN;
	if (csrf_frm_reg$EN)
	  csrf_frm_reg <= `BSV_ASSIGNMENT_DELAY csrf_frm_reg$D_IN;
	if (csrf_fs_reg$EN)
	  csrf_fs_reg <= `BSV_ASSIGNMENT_DELAY csrf_fs_reg$D_IN;
	if (csrf_ie_vec_0$EN)
	  csrf_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY csrf_ie_vec_0$D_IN;
	if (csrf_ie_vec_1$EN)
	  csrf_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY csrf_ie_vec_1$D_IN;
	if (csrf_ie_vec_3$EN)
	  csrf_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY csrf_ie_vec_3$D_IN;
	if (csrf_mcause_code_reg$EN)
	  csrf_mcause_code_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_mcause_code_reg$D_IN;
	if (csrf_mcause_interrupt_reg$EN)
	  csrf_mcause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_mcause_interrupt_reg$D_IN;
	if (csrf_mcounteren_cy_reg$EN)
	  csrf_mcounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_mcounteren_cy_reg$D_IN;
	if (csrf_mcounteren_ir_reg$EN)
	  csrf_mcounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_mcounteren_ir_reg$D_IN;
	if (csrf_mcounteren_tm_reg$EN)
	  csrf_mcounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_mcounteren_tm_reg$D_IN;
	if (csrf_mcycle_ehr_data_rl$EN)
	  csrf_mcycle_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY
	      csrf_mcycle_ehr_data_rl$D_IN;
	if (csrf_medeleg_13_11_reg$EN)
	  csrf_medeleg_13_11_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_medeleg_13_11_reg$D_IN;
	if (csrf_medeleg_15_reg$EN)
	  csrf_medeleg_15_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_medeleg_15_reg$D_IN;
	if (csrf_medeleg_9_0_reg$EN)
	  csrf_medeleg_9_0_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_medeleg_9_0_reg$D_IN;
	if (csrf_mepc_csr$EN)
	  csrf_mepc_csr <= `BSV_ASSIGNMENT_DELAY csrf_mepc_csr$D_IN;
	if (csrf_mideleg_11_reg$EN)
	  csrf_mideleg_11_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_mideleg_11_reg$D_IN;
	if (csrf_mideleg_1_0_reg$EN)
	  csrf_mideleg_1_0_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_mideleg_1_0_reg$D_IN;
	if (csrf_mideleg_5_3_reg$EN)
	  csrf_mideleg_5_3_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_mideleg_5_3_reg$D_IN;
	if (csrf_mideleg_9_7_reg$EN)
	  csrf_mideleg_9_7_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_mideleg_9_7_reg$D_IN;
	if (csrf_minstret_ehr_data_rl$EN)
	  csrf_minstret_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY
	      csrf_minstret_ehr_data_rl$D_IN;
	if (csrf_mpp_reg$EN)
	  csrf_mpp_reg <= `BSV_ASSIGNMENT_DELAY csrf_mpp_reg$D_IN;
	if (csrf_mprv_reg$EN)
	  csrf_mprv_reg <= `BSV_ASSIGNMENT_DELAY csrf_mprv_reg$D_IN;
	if (csrf_mscratch_csr$EN)
	  csrf_mscratch_csr <= `BSV_ASSIGNMENT_DELAY csrf_mscratch_csr$D_IN;
	if (csrf_mtval_csr$EN)
	  csrf_mtval_csr <= `BSV_ASSIGNMENT_DELAY csrf_mtval_csr$D_IN;
	if (csrf_mtvec_base_hi_reg$EN)
	  csrf_mtvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_mtvec_base_hi_reg$D_IN;
	if (csrf_mtvec_mode_low_reg$EN)
	  csrf_mtvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_mtvec_mode_low_reg$D_IN;
	if (csrf_mxr_reg$EN)
	  csrf_mxr_reg <= `BSV_ASSIGNMENT_DELAY csrf_mxr_reg$D_IN;
	if (csrf_ppn_reg$EN)
	  csrf_ppn_reg <= `BSV_ASSIGNMENT_DELAY csrf_ppn_reg$D_IN;
	if (csrf_prev_ie_vec_0$EN)
	  csrf_prev_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY csrf_prev_ie_vec_0$D_IN;
	if (csrf_prev_ie_vec_1$EN)
	  csrf_prev_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY csrf_prev_ie_vec_1$D_IN;
	if (csrf_prev_ie_vec_3$EN)
	  csrf_prev_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY csrf_prev_ie_vec_3$D_IN;
	if (csrf_prv_reg$EN)
	  csrf_prv_reg <= `BSV_ASSIGNMENT_DELAY csrf_prv_reg$D_IN;
	if (csrf_rg_tdata1_data$EN)
	  csrf_rg_tdata1_data <= `BSV_ASSIGNMENT_DELAY
	      csrf_rg_tdata1_data$D_IN;
	if (csrf_rg_tdata1_dmode$EN)
	  csrf_rg_tdata1_dmode <= `BSV_ASSIGNMENT_DELAY
	      csrf_rg_tdata1_dmode$D_IN;
	if (csrf_rg_tselect$EN)
	  csrf_rg_tselect <= `BSV_ASSIGNMENT_DELAY csrf_rg_tselect$D_IN;
	if (csrf_scause_code_reg$EN)
	  csrf_scause_code_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_scause_code_reg$D_IN;
	if (csrf_scause_interrupt_reg$EN)
	  csrf_scause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_scause_interrupt_reg$D_IN;
	if (csrf_scounteren_cy_reg$EN)
	  csrf_scounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_scounteren_cy_reg$D_IN;
	if (csrf_scounteren_ir_reg$EN)
	  csrf_scounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_scounteren_ir_reg$D_IN;
	if (csrf_scounteren_tm_reg$EN)
	  csrf_scounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_scounteren_tm_reg$D_IN;
	if (csrf_sepc_csr$EN)
	  csrf_sepc_csr <= `BSV_ASSIGNMENT_DELAY csrf_sepc_csr$D_IN;
	if (csrf_software_int_en_vec_0$EN)
	  csrf_software_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY
	      csrf_software_int_en_vec_0$D_IN;
	if (csrf_software_int_en_vec_1$EN)
	  csrf_software_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY
	      csrf_software_int_en_vec_1$D_IN;
	if (csrf_software_int_en_vec_3$EN)
	  csrf_software_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY
	      csrf_software_int_en_vec_3$D_IN;
	if (csrf_software_int_pend_vec_0$EN)
	  csrf_software_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY
	      csrf_software_int_pend_vec_0$D_IN;
	if (csrf_software_int_pend_vec_1$EN)
	  csrf_software_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY
	      csrf_software_int_pend_vec_1$D_IN;
	if (csrf_software_int_pend_vec_3$EN)
	  csrf_software_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY
	      csrf_software_int_pend_vec_3$D_IN;
	if (csrf_spp_reg$EN)
	  csrf_spp_reg <= `BSV_ASSIGNMENT_DELAY csrf_spp_reg$D_IN;
	if (csrf_sscratch_csr$EN)
	  csrf_sscratch_csr <= `BSV_ASSIGNMENT_DELAY csrf_sscratch_csr$D_IN;
	if (csrf_stats_module_doStats$EN)
	  csrf_stats_module_doStats <= `BSV_ASSIGNMENT_DELAY
	      csrf_stats_module_doStats$D_IN;
	if (csrf_stval_csr$EN)
	  csrf_stval_csr <= `BSV_ASSIGNMENT_DELAY csrf_stval_csr$D_IN;
	if (csrf_stvec_base_hi_reg$EN)
	  csrf_stvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_stvec_base_hi_reg$D_IN;
	if (csrf_stvec_mode_low_reg$EN)
	  csrf_stvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_stvec_mode_low_reg$D_IN;
	if (csrf_sum_reg$EN)
	  csrf_sum_reg <= `BSV_ASSIGNMENT_DELAY csrf_sum_reg$D_IN;
	if (csrf_time_reg$EN)
	  csrf_time_reg <= `BSV_ASSIGNMENT_DELAY csrf_time_reg$D_IN;
	if (csrf_timer_int_en_vec_0$EN)
	  csrf_timer_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY
	      csrf_timer_int_en_vec_0$D_IN;
	if (csrf_timer_int_en_vec_1$EN)
	  csrf_timer_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY
	      csrf_timer_int_en_vec_1$D_IN;
	if (csrf_timer_int_en_vec_3$EN)
	  csrf_timer_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY
	      csrf_timer_int_en_vec_3$D_IN;
	if (csrf_timer_int_pend_vec_0$EN)
	  csrf_timer_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY
	      csrf_timer_int_pend_vec_0$D_IN;
	if (csrf_timer_int_pend_vec_1$EN)
	  csrf_timer_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY
	      csrf_timer_int_pend_vec_1$D_IN;
	if (csrf_timer_int_pend_vec_3$EN)
	  csrf_timer_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY
	      csrf_timer_int_pend_vec_3$D_IN;
	if (csrf_tsr_reg$EN)
	  csrf_tsr_reg <= `BSV_ASSIGNMENT_DELAY csrf_tsr_reg$D_IN;
	if (csrf_tvm_reg$EN)
	  csrf_tvm_reg <= `BSV_ASSIGNMENT_DELAY csrf_tvm_reg$D_IN;
	if (csrf_tw_reg$EN)
	  csrf_tw_reg <= `BSV_ASSIGNMENT_DELAY csrf_tw_reg$D_IN;
	if (csrf_vm_mode_sv39_reg$EN)
	  csrf_vm_mode_sv39_reg <= `BSV_ASSIGNMENT_DELAY
	      csrf_vm_mode_sv39_reg$D_IN;
	if (flush_reservation$EN)
	  flush_reservation <= `BSV_ASSIGNMENT_DELAY flush_reservation$D_IN;
	if (flush_tlbs$EN)
	  flush_tlbs <= `BSV_ASSIGNMENT_DELAY flush_tlbs$D_IN;
	if (mmio_cRqQ_clearReq_rl$EN)
	  mmio_cRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_cRqQ_clearReq_rl$D_IN;
	if (mmio_cRqQ_data_0$EN)
	  mmio_cRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_cRqQ_data_0$D_IN;
	if (mmio_cRqQ_deqReq_rl$EN)
	  mmio_cRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_cRqQ_deqReq_rl$D_IN;
	if (mmio_cRqQ_empty$EN)
	  mmio_cRqQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_cRqQ_empty$D_IN;
	if (mmio_cRqQ_enqReq_rl$EN)
	  mmio_cRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_cRqQ_enqReq_rl$D_IN;
	if (mmio_cRqQ_full$EN)
	  mmio_cRqQ_full <= `BSV_ASSIGNMENT_DELAY mmio_cRqQ_full$D_IN;
	if (mmio_cRsQ_clearReq_rl$EN)
	  mmio_cRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_cRsQ_clearReq_rl$D_IN;
	if (mmio_cRsQ_data_0$EN)
	  mmio_cRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_cRsQ_data_0$D_IN;
	if (mmio_cRsQ_deqReq_rl$EN)
	  mmio_cRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_cRsQ_deqReq_rl$D_IN;
	if (mmio_cRsQ_empty$EN)
	  mmio_cRsQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_cRsQ_empty$D_IN;
	if (mmio_cRsQ_enqReq_rl$EN)
	  mmio_cRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_cRsQ_enqReq_rl$D_IN;
	if (mmio_cRsQ_full$EN)
	  mmio_cRsQ_full <= `BSV_ASSIGNMENT_DELAY mmio_cRsQ_full$D_IN;
	if (mmio_dataPendQ_clearReq_rl$EN)
	  mmio_dataPendQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataPendQ_clearReq_rl$D_IN;
	if (mmio_dataPendQ_deqReq_rl$EN)
	  mmio_dataPendQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataPendQ_deqReq_rl$D_IN;
	if (mmio_dataPendQ_empty$EN)
	  mmio_dataPendQ_empty <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataPendQ_empty$D_IN;
	if (mmio_dataPendQ_enqReq_rl$EN)
	  mmio_dataPendQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataPendQ_enqReq_rl$D_IN;
	if (mmio_dataPendQ_full$EN)
	  mmio_dataPendQ_full <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataPendQ_full$D_IN;
	if (mmio_dataReqQ_clearReq_rl$EN)
	  mmio_dataReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataReqQ_clearReq_rl$D_IN;
	if (mmio_dataReqQ_data_0$EN)
	  mmio_dataReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataReqQ_data_0$D_IN;
	if (mmio_dataReqQ_deqReq_rl$EN)
	  mmio_dataReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataReqQ_deqReq_rl$D_IN;
	if (mmio_dataReqQ_empty$EN)
	  mmio_dataReqQ_empty <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataReqQ_empty$D_IN;
	if (mmio_dataReqQ_enqReq_rl$EN)
	  mmio_dataReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataReqQ_enqReq_rl$D_IN;
	if (mmio_dataReqQ_full$EN)
	  mmio_dataReqQ_full <= `BSV_ASSIGNMENT_DELAY mmio_dataReqQ_full$D_IN;
	if (mmio_dataRespQ_clearReq_rl$EN)
	  mmio_dataRespQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataRespQ_clearReq_rl$D_IN;
	if (mmio_dataRespQ_data_0$EN)
	  mmio_dataRespQ_data_0 <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataRespQ_data_0$D_IN;
	if (mmio_dataRespQ_deqReq_rl$EN)
	  mmio_dataRespQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataRespQ_deqReq_rl$D_IN;
	if (mmio_dataRespQ_empty$EN)
	  mmio_dataRespQ_empty <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataRespQ_empty$D_IN;
	if (mmio_dataRespQ_enqReq_rl$EN)
	  mmio_dataRespQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataRespQ_enqReq_rl$D_IN;
	if (mmio_dataRespQ_full$EN)
	  mmio_dataRespQ_full <= `BSV_ASSIGNMENT_DELAY
	      mmio_dataRespQ_full$D_IN;
	if (mmio_fromHostAddr$EN)
	  mmio_fromHostAddr <= `BSV_ASSIGNMENT_DELAY mmio_fromHostAddr$D_IN;
	if (mmio_pRqQ_clearReq_rl$EN)
	  mmio_pRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_pRqQ_clearReq_rl$D_IN;
	if (mmio_pRqQ_data_0$EN)
	  mmio_pRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_pRqQ_data_0$D_IN;
	if (mmio_pRqQ_deqReq_rl$EN)
	  mmio_pRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_pRqQ_deqReq_rl$D_IN;
	if (mmio_pRqQ_empty$EN)
	  mmio_pRqQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_pRqQ_empty$D_IN;
	if (mmio_pRqQ_enqReq_rl$EN)
	  mmio_pRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_pRqQ_enqReq_rl$D_IN;
	if (mmio_pRqQ_full$EN)
	  mmio_pRqQ_full <= `BSV_ASSIGNMENT_DELAY mmio_pRqQ_full$D_IN;
	if (mmio_pRsQ_clearReq_rl$EN)
	  mmio_pRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_pRsQ_clearReq_rl$D_IN;
	if (mmio_pRsQ_data_0$EN)
	  mmio_pRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_pRsQ_data_0$D_IN;
	if (mmio_pRsQ_deqReq_rl$EN)
	  mmio_pRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_pRsQ_deqReq_rl$D_IN;
	if (mmio_pRsQ_empty$EN)
	  mmio_pRsQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_pRsQ_empty$D_IN;
	if (mmio_pRsQ_enqReq_rl$EN)
	  mmio_pRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
	      mmio_pRsQ_enqReq_rl$D_IN;
	if (mmio_pRsQ_full$EN)
	  mmio_pRsQ_full <= `BSV_ASSIGNMENT_DELAY mmio_pRsQ_full$D_IN;
	if (mmio_toHostAddr$EN)
	  mmio_toHostAddr <= `BSV_ASSIGNMENT_DELAY mmio_toHostAddr$D_IN;
	if (outOfReset$EN)
	  outOfReset <= `BSV_ASSIGNMENT_DELAY outOfReset$D_IN;
	if (started$EN) started <= `BSV_ASSIGNMENT_DELAY started$D_IN;
	if (update_vm_info$EN)
	  update_vm_info <= `BSV_ASSIGNMENT_DELAY update_vm_info$D_IN;
      end
    if (csrf_rg_tdata2$EN)
      csrf_rg_tdata2 <= `BSV_ASSIGNMENT_DELAY csrf_rg_tdata2$D_IN;
    if (csrf_rg_tdata3$EN)
      csrf_rg_tdata3 <= `BSV_ASSIGNMENT_DELAY csrf_rg_tdata3$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    commitStage_commitTrap = 166'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    commitStage_rg_serial_num = 64'hAAAAAAAAAAAAAAAA;
    coreFix_doStatsReg = 1'h0;
    coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt = 4'hA;
    coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init = 1'h0;
    coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg_ready = 1'h0;
    coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit = 2'h2;
    coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_0 =
	129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned_pipe_1 =
	129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_0 =
	129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned_pipe_1 =
	129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_0 =
	129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned_pipe_1 =
	129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 = 3'h2;
    coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 = 3'h2;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 = 3'h2;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 = 3'h2;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 = 3'h2;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 = 3'h2;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 = 3'h2;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 = 3'h2;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 = 3'h2;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 = 3'h2;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP = 3'h2;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP = 3'h2;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl = 4'hA;
    coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 =
	583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 =
	583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl =
	584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl = 59'h2AAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_processAmo =
	161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl =
	153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 =
	72'hAAAAAAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1 =
	72'hAAAAAAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl =
	73'h0AAAAAAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 =
	579'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 =
	579'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP = 1'h0;
    coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl =
	580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full = 1'h0;
    coreFix_memExe_dMem_perfReqQ_clearReq_rl = 1'h0;
    coreFix_memExe_dMem_perfReqQ_data_0 = 4'hA;
    coreFix_memExe_dMem_perfReqQ_deqReq_rl = 1'h0;
    coreFix_memExe_dMem_perfReqQ_empty = 1'h0;
    coreFix_memExe_dMem_perfReqQ_enqReq_rl = 5'h0A;
    coreFix_memExe_dMem_perfReqQ_full = 1'h0;
    coreFix_memExe_forwardQ_clearReq_rl = 1'h0;
    coreFix_memExe_forwardQ_data_0 = 69'h0AAAAAAAAAAAAAAAAA;
    coreFix_memExe_forwardQ_data_1 = 69'h0AAAAAAAAAAAAAAAAA;
    coreFix_memExe_forwardQ_deqP = 1'h0;
    coreFix_memExe_forwardQ_deqReq_rl = 1'h0;
    coreFix_memExe_forwardQ_empty = 1'h0;
    coreFix_memExe_forwardQ_enqP = 1'h0;
    coreFix_memExe_forwardQ_enqReq_rl = 70'h2AAAAAAAAAAAAAAAAA;
    coreFix_memExe_forwardQ_full = 1'h0;
    coreFix_memExe_memRespLdQ_clearReq_rl = 1'h0;
    coreFix_memExe_memRespLdQ_data_0 = 69'h0AAAAAAAAAAAAAAAAA;
    coreFix_memExe_memRespLdQ_data_1 = 69'h0AAAAAAAAAAAAAAAAA;
    coreFix_memExe_memRespLdQ_deqP = 1'h0;
    coreFix_memExe_memRespLdQ_deqReq_rl = 1'h0;
    coreFix_memExe_memRespLdQ_empty = 1'h0;
    coreFix_memExe_memRespLdQ_enqP = 1'h0;
    coreFix_memExe_memRespLdQ_enqReq_rl = 70'h2AAAAAAAAAAAAAAAAA;
    coreFix_memExe_memRespLdQ_full = 1'h0;
    coreFix_memExe_reqLdQ_data_0_rl = 69'h0AAAAAAAAAAAAAAAAA;
    coreFix_memExe_reqLdQ_empty_rl = 1'h0;
    coreFix_memExe_reqLdQ_full_rl = 1'h0;
    coreFix_memExe_reqLrScAmoQ_data_0_rl =
	153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    coreFix_memExe_reqLrScAmoQ_empty_rl = 1'h0;
    coreFix_memExe_reqLrScAmoQ_full_rl = 1'h0;
    coreFix_memExe_reqStQ_data_0_rl = 66'h2AAAAAAAAAAAAAAAA;
    coreFix_memExe_reqStQ_empty_rl = 1'h0;
    coreFix_memExe_reqStQ_full_rl = 1'h0;
    coreFix_memExe_respLrScAmoQ_clearReq_rl = 1'h0;
    coreFix_memExe_respLrScAmoQ_data_0 = 64'hAAAAAAAAAAAAAAAA;
    coreFix_memExe_respLrScAmoQ_deqReq_rl = 1'h0;
    coreFix_memExe_respLrScAmoQ_empty = 1'h0;
    coreFix_memExe_respLrScAmoQ_enqReq_rl = 65'h0AAAAAAAAAAAAAAAA;
    coreFix_memExe_respLrScAmoQ_full = 1'h0;
    coreFix_memExe_waitLrScAmoMMIOResp = 3'h2;
    csrInstOrInterruptInflight_rl = 1'h0;
    csrf_external_int_en_vec_0 = 1'h0;
    csrf_external_int_en_vec_1 = 1'h0;
    csrf_external_int_en_vec_3 = 1'h0;
    csrf_external_int_pend_vec_0 = 1'h0;
    csrf_external_int_pend_vec_1 = 1'h0;
    csrf_external_int_pend_vec_3 = 1'h0;
    csrf_fflags_reg = 5'h0A;
    csrf_frm_reg = 3'h2;
    csrf_fs_reg = 2'h2;
    csrf_ie_vec_0 = 1'h0;
    csrf_ie_vec_1 = 1'h0;
    csrf_ie_vec_3 = 1'h0;
    csrf_mcause_code_reg = 4'hA;
    csrf_mcause_interrupt_reg = 1'h0;
    csrf_mcounteren_cy_reg = 1'h0;
    csrf_mcounteren_ir_reg = 1'h0;
    csrf_mcounteren_tm_reg = 1'h0;
    csrf_mcycle_ehr_data_rl = 64'hAAAAAAAAAAAAAAAA;
    csrf_medeleg_13_11_reg = 3'h2;
    csrf_medeleg_15_reg = 1'h0;
    csrf_medeleg_9_0_reg = 10'h2AA;
    csrf_mepc_csr = 64'hAAAAAAAAAAAAAAAA;
    csrf_mideleg_11_reg = 1'h0;
    csrf_mideleg_1_0_reg = 2'h2;
    csrf_mideleg_5_3_reg = 3'h2;
    csrf_mideleg_9_7_reg = 3'h2;
    csrf_minstret_ehr_data_rl = 64'hAAAAAAAAAAAAAAAA;
    csrf_mpp_reg = 2'h2;
    csrf_mprv_reg = 1'h0;
    csrf_mscratch_csr = 64'hAAAAAAAAAAAAAAAA;
    csrf_mtval_csr = 64'hAAAAAAAAAAAAAAAA;
    csrf_mtvec_base_hi_reg = 62'h2AAAAAAAAAAAAAAA;
    csrf_mtvec_mode_low_reg = 1'h0;
    csrf_mxr_reg = 1'h0;
    csrf_ppn_reg = 44'hAAAAAAAAAAA;
    csrf_prev_ie_vec_0 = 1'h0;
    csrf_prev_ie_vec_1 = 1'h0;
    csrf_prev_ie_vec_3 = 1'h0;
    csrf_prv_reg = 2'h2;
    csrf_rg_tdata1_data = 59'h2AAAAAAAAAAAAAA;
    csrf_rg_tdata1_dmode = 1'h0;
    csrf_rg_tdata2 = 64'hAAAAAAAAAAAAAAAA;
    csrf_rg_tdata3 = 64'hAAAAAAAAAAAAAAAA;
    csrf_rg_tselect = 64'hAAAAAAAAAAAAAAAA;
    csrf_scause_code_reg = 4'hA;
    csrf_scause_interrupt_reg = 1'h0;
    csrf_scounteren_cy_reg = 1'h0;
    csrf_scounteren_ir_reg = 1'h0;
    csrf_scounteren_tm_reg = 1'h0;
    csrf_sepc_csr = 64'hAAAAAAAAAAAAAAAA;
    csrf_software_int_en_vec_0 = 1'h0;
    csrf_software_int_en_vec_1 = 1'h0;
    csrf_software_int_en_vec_3 = 1'h0;
    csrf_software_int_pend_vec_0 = 1'h0;
    csrf_software_int_pend_vec_1 = 1'h0;
    csrf_software_int_pend_vec_3 = 1'h0;
    csrf_spp_reg = 1'h0;
    csrf_sscratch_csr = 64'hAAAAAAAAAAAAAAAA;
    csrf_stats_module_doStats = 1'h0;
    csrf_stval_csr = 64'hAAAAAAAAAAAAAAAA;
    csrf_stvec_base_hi_reg = 62'h2AAAAAAAAAAAAAAA;
    csrf_stvec_mode_low_reg = 1'h0;
    csrf_sum_reg = 1'h0;
    csrf_time_reg = 64'hAAAAAAAAAAAAAAAA;
    csrf_timer_int_en_vec_0 = 1'h0;
    csrf_timer_int_en_vec_1 = 1'h0;
    csrf_timer_int_en_vec_3 = 1'h0;
    csrf_timer_int_pend_vec_0 = 1'h0;
    csrf_timer_int_pend_vec_1 = 1'h0;
    csrf_timer_int_pend_vec_3 = 1'h0;
    csrf_tsr_reg = 1'h0;
    csrf_tvm_reg = 1'h0;
    csrf_tw_reg = 1'h0;
    csrf_vm_mode_sv39_reg = 1'h0;
    flush_reservation = 1'h0;
    flush_tlbs = 1'h0;
    mmio_cRqQ_clearReq_rl = 1'h0;
    mmio_cRqQ_data_0 = 142'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    mmio_cRqQ_deqReq_rl = 1'h0;
    mmio_cRqQ_empty = 1'h0;
    mmio_cRqQ_enqReq_rl = 143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    mmio_cRqQ_full = 1'h0;
    mmio_cRsQ_clearReq_rl = 1'h0;
    mmio_cRsQ_data_0 = 1'h0;
    mmio_cRsQ_deqReq_rl = 1'h0;
    mmio_cRsQ_empty = 1'h0;
    mmio_cRsQ_enqReq_rl = 2'h2;
    mmio_cRsQ_full = 1'h0;
    mmio_dataPendQ_clearReq_rl = 1'h0;
    mmio_dataPendQ_deqReq_rl = 1'h0;
    mmio_dataPendQ_empty = 1'h0;
    mmio_dataPendQ_enqReq_rl = 1'h0;
    mmio_dataPendQ_full = 1'h0;
    mmio_dataReqQ_clearReq_rl = 1'h0;
    mmio_dataReqQ_data_0 = 142'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    mmio_dataReqQ_deqReq_rl = 1'h0;
    mmio_dataReqQ_empty = 1'h0;
    mmio_dataReqQ_enqReq_rl = 143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    mmio_dataReqQ_full = 1'h0;
    mmio_dataRespQ_clearReq_rl = 1'h0;
    mmio_dataRespQ_data_0 = 65'h0AAAAAAAAAAAAAAAA;
    mmio_dataRespQ_deqReq_rl = 1'h0;
    mmio_dataRespQ_empty = 1'h0;
    mmio_dataRespQ_enqReq_rl = 66'h2AAAAAAAAAAAAAAAA;
    mmio_dataRespQ_full = 1'h0;
    mmio_fromHostAddr = 61'h0AAAAAAAAAAAAAAA;
    mmio_pRqQ_clearReq_rl = 1'h0;
    mmio_pRqQ_data_0 = 39'h2AAAAAAAAA;
    mmio_pRqQ_deqReq_rl = 1'h0;
    mmio_pRqQ_empty = 1'h0;
    mmio_pRqQ_enqReq_rl = 40'hAAAAAAAAAA;
    mmio_pRqQ_full = 1'h0;
    mmio_pRsQ_clearReq_rl = 1'h0;
    mmio_pRsQ_data_0 = 67'h2AAAAAAAAAAAAAAAA;
    mmio_pRsQ_deqReq_rl = 1'h0;
    mmio_pRsQ_empty = 1'h0;
    mmio_pRsQ_enqReq_rl = 68'hAAAAAAAAAAAAAAAAA;
    mmio_pRsQ_full = 1'h0;
    mmio_toHostAddr = 61'h0AAAAAAAAAAAAAAA;
    outOfReset = 1'h0;
    started = 1'h0;
    update_vm_info = 1'h0;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_outOfReset)
	$fwrite(32'h80000002, "mkProc came out of reset\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_handlePRq && mmio_pRqQ_data_0[38] &&
	  mmio_pRqQ_data_0[37:36] != 2'd2)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_handlePRq && mmio_pRqQ_data_0[38] &&
	  mmio_pRqQ_data_0[37:36] != 2'd2)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/MMIOCore.bsv\", line 133, column 37\nplatform can only write MTIP");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_mmio_handlePRq && mmio_pRqQ_data_0[38] &&
	  mmio_pRqQ_data_0[37:36] != 2'd2)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue &&
	  coreFix_memExe_lsq$firstLd[2])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue &&
	  coreFix_memExe_lsq$firstLd[2])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv\", line 755, column 45\ncannot be killed");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue &&
	  coreFix_memExe_lsq$firstLd[2])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue &&
	  coreFix_memExe_lsq$firstLd[2])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue &&
	  coreFix_memExe_lsq$firstLd[2])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv\", line 834, column 45\ncannot be killed");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue &&
	  coreFix_memExe_lsq$firstLd[2])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue &&
	  coreFix_memExe_lsq$firstLd[101])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue &&
	  coreFix_memExe_lsq$firstLd[101])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv\", line 835, column 42\nLdQ MMIO is only Ld");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue &&
	  coreFix_memExe_lsq$firstLd[101])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState !=
	  3'd2)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState !=
	  3'd2)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/L1Bank.bsv\", line 352, column 13\nsend replacement resp to parent, state should be WaitNewTag");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState !=
	  3'd2)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo &&
	  coreFix_memExe_dMem_cache_m_banks_0_processAmo[87:86] != 2'd3)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo &&
	  coreFix_memExe_dMem_cache_m_banks_0_processAmo[87:86] != 2'd3)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/L1Bank.bsv\", line 572, column 36\nAMO must req for M");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo &&
	  coreFix_memExe_dMem_cache_m_banks_0_processAmo[87:86] != 2'd3)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2797)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2797)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/L1Bank.bsv\", line 853, column 22\npRqMiss deasserted, must be down to S");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2797)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
	  NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2815)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
	  NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2815)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/L1Bank.bsv\", line 870, column 18\npRq overtakes CRq");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
	  NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2815)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush)
	$write("instret:%0d  PC:0x%0h  instr:0x%08h",
	       commitStage_rg_serial_num,
	       rob$deqPort_0_deq_data[353:290],
	       rob$deqPort_0_deq_data[289:258],
	       "  iType:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[257:253] == 5'd0)
	$write("Unsupported");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[257:253] == 5'd1)
	$write("Nop");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[257:253] == 5'd2)
	$write("Amo");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[257:253] == 5'd3)
	$write("Alu");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[257:253] == 5'd4)
	$write("Ld");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[257:253] == 5'd5)
	$write("St");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[257:253] == 5'd6)
	$write("Lr");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[257:253] == 5'd7)
	$write("Sc");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[257:253] == 5'd8)
	$write("J");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[257:253] == 5'd9)
	$write("Jr");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[257:253] == 5'd10)
	$write("Br");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[257:253] == 5'd11)
	$write("Auipc");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[257:253] == 5'd12)
	$write("Fpu");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[257:253] == 5'd13)
	$write("Csr");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[257:253] == 5'd14)
	$write("Fence");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[257:253] == 5'd15)
	$write("FenceI");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[257:253] == 5'd16)
	$write("SFence");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[257:253] == 5'd17)
	$write("Ecall");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[257:253] == 5'd18)
	$write("Ebreak");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[257:253] == 5'd19)
	$write("Sret");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[257:253] == 5'd20)
	$write("Mret");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[257:253] != 5'd0 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd1 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd2 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd3 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd4 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd5 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd6 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd7 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd8 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd9 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd10 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd11 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd12 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd13 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd14 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd15 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd16 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd17 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd18 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd19 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd20)
	$write("Interrupt");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush)
	$write("    [doCommitTrap]", "\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  !rob$deqPort_0_deq_data[25])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  !rob$deqPort_0_deq_data[25])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 578, column 48\nmust be executed");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  !rob$deqPort_0_deq_data[25])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[11:0] != 12'd0)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[11:0] != 12'd0)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 579, column 36\ncannot have spec bits");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
	  rob$deqPort_0_deq_data[11:0] != 12'd0)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	  rob$deqPort_0_deq_data[12])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	  rob$deqPort_0_deq_data[12])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 695, column 39\ncannot increment epoch before");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	  rob$deqPort_0_deq_data[12])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	  !rob$deqPort_0_deq_data[25])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	  !rob$deqPort_0_deq_data[25])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 696, column 48\nmust be executed");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	  !rob$deqPort_0_deq_data[25])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	  rob$deqPort_0_deq_data[11:0] != 12'd0)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	  rob$deqPort_0_deq_data[11:0] != 12'd0)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 697, column 36\ncannot have spec bits");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitKilledLd &&
	  rob$deqPort_0_deq_data[11:0] != 12'd0)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst)
	$write("instret:%0d  PC:0x%0h  instr:0x%08h",
	       commitStage_rg_serial_num,
	       rob$deqPort_0_deq_data[353:290],
	       rob$deqPort_0_deq_data[289:258],
	       "   iType:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd0)
	$write("Unsupported");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd1)
	$write("Nop");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd2)
	$write("Amo");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd3)
	$write("Alu");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd4)
	$write("Ld");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd5)
	$write("St");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd6)
	$write("Lr");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd7)
	$write("Sc");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd8)
	$write("J");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd9)
	$write("Jr");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd10)
	$write("Br");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd11)
	$write("Auipc");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd12)
	$write("Fpu");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd13)
	$write("Csr");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd14)
	$write("Fence");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd15)
	$write("FenceI");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd16)
	$write("SFence");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd17)
	$write("Ecall");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd18)
	$write("Ebreak");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd19)
	$write("Sret");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd20)
	$write("Mret");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] != 5'd0 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd1 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd2 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd3 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd4 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd5 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd6 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd7 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd8 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd9 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd10 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd11 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd12 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd13 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd14 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd15 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd16 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd17 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd18 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd19 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd20)
	$write("Interrupt");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst)
	$write("    [doCommitSystemInst]", "\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	  (rob$deqPort_0_deq_data[97:96] == 2'd0 ||
	   rob$deqPort_0_deq_data[97:96] == 2'd1))
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	  (rob$deqPort_0_deq_data[97:96] == 2'd0 ||
	   rob$deqPort_0_deq_data[97:96] == 2'd1))
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 740, column 33\nmust have csr data");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	  (rob$deqPort_0_deq_data[97:96] == 2'd0 ||
	   rob$deqPort_0_deq_data[97:96] == 2'd1))
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[257:253] == 5'd13 &&
	  IF_rob_deqPort_0_deq_data__4466_BIT_181_4696_T_ETC___d14778 == 6'd6)
	$display("[Terminate CSR] being written (val = %x), ",
		 "send terminate signal to host",
		 rob$deqPort_0_deq_data[95:32]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  NOT_IF_rob_deqPort_0_deq_data__4466_BITS_97_TO_ETC___d14971)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  NOT_IF_rob_deqPort_0_deq_data__4466_BITS_97_TO_ETC___d14971)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 763, column 39\nppc must be pc + 4");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  NOT_IF_rob_deqPort_0_deq_data__4466_BITS_97_TO_ETC___d14971)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  !rob$deqPort_0_deq_data[12])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  !rob$deqPort_0_deq_data[12])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 824, column 38\nmust have already incremented epoch");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  !rob$deqPort_0_deq_data[12])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  NOT_rob_deqPort_0_deq_data__4466_BITS_257_TO_2_ETC___d14981)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  NOT_rob_deqPort_0_deq_data__4466_BITS_257_TO_2_ETC___d14981)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 825, column 54\nonly CSR has valid csr idx");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  NOT_rob_deqPort_0_deq_data__4466_BITS_257_TO_2_ETC___d14981)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[11:0] != 12'd0)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[11:0] != 12'd0)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 829, column 36\ncannot have spec bits");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  rob$deqPort_0_deq_data[11:0] != 12'd0)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  !rob$deqPort_0_deq_data[168])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  !rob$deqPort_0_deq_data[168])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 830, column 37\nmust have claimed phy reg");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
	  !rob$deqPort_0_deq_data[168])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq)
	$write("instret:%0d  PC:0x%0h  instr:0x%08h",
	       commitStage_rg_serial_num,
	       rob$deqPort_0_deq_data[353:290],
	       rob$deqPort_0_deq_data[289:258],
	       "   iType:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[257:253] == 5'd1)
	$write("Nop");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[257:253] == 5'd2)
	$write("Amo");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[257:253] == 5'd3)
	$write("Alu");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[257:253] == 5'd4)
	$write("Ld");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[257:253] == 5'd5)
	$write("St");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[257:253] == 5'd6)
	$write("Lr");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[257:253] == 5'd7)
	$write("Sc");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[257:253] == 5'd8)
	$write("J");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[257:253] == 5'd9)
	$write("Jr");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[257:253] == 5'd10)
	$write("Br");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[257:253] == 5'd11)
	$write("Auipc");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[257:253] == 5'd12)
	$write("Fpu");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[257:253] == 5'd14)
	$write("Fence");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  rob$deqPort_0_deq_data[257:253] != 5'd1 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd2 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd3 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd4 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd5 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd6 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd7 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd8 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd9 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd10 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd11 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd12 &&
	  rob$deqPort_0_deq_data[257:253] != 5'd14)
	$write("Interrupt");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq)
	$write("    [doCommitNormalInst [%0d]]", $signed(32'd0), "\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  !rob$deqPort_0_deq_data[168])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  !rob$deqPort_0_deq_data[168])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 950, column 49\nshould have renamed");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_0_canDeq &&
	  !rob$deqPort_0_deq_data[168])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[257:253] != 5'd0 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd21 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd17 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd18 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd13 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd16 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd15 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd19 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd20)
	$write("instret:%0d  PC:0x%0h  instr:0x%08h",
	       commitStage_rg_serial_num +
	       IF_rob_deqPort_0_canDeq__4995_THEN_IF_NOT_rob__ETC___d15104,
	       rob$deqPort_1_deq_data[353:290],
	       rob$deqPort_1_deq_data[289:258],
	       "   iType:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[257:253] == 5'd1)
	$write("Nop");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[257:253] == 5'd2)
	$write("Amo");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[257:253] == 5'd3)
	$write("Alu");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[257:253] == 5'd4)
	$write("Ld");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[257:253] == 5'd5)
	$write("St");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[257:253] == 5'd6)
	$write("Lr");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[257:253] == 5'd7)
	$write("Sc");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[257:253] == 5'd8)
	$write("J");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[257:253] == 5'd9)
	$write("Jr");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[257:253] == 5'd10)
	$write("Br");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[257:253] == 5'd11)
	$write("Auipc");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[257:253] == 5'd12)
	$write("Fpu");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[257:253] == 5'd14)
	$write("Fence");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[257:253] != 5'd0 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd21 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd17 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd18 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd13 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd16 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd15 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd19 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd20 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd1 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd2 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd3 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd4 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd5 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd6 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd7 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd8 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd9 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd10 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd11 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd12 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd14)
	$write("Interrupt");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[257:253] != 5'd0 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd21 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd17 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd18 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd13 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd16 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd15 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd19 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd20)
	$write("    [doCommitNormalInst [%0d]]", $signed(32'd1), "\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[257:253] != 5'd0 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd21 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd17 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd18 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd13 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd16 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd15 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd19 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd20 &&
	  !rob$deqPort_1_deq_data[168])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[257:253] != 5'd0 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd21 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd17 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd18 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd13 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd16 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd15 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd19 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd20 &&
	  !rob$deqPort_1_deq_data[168])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv\", line 950, column 49\nshould have renamed");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
	  rob$deqPort_1_canDeq &&
	  rob$deqPort_1_deq_data[25] &&
	  !rob$deqPort_1_deq_data[18] &&
	  !rob$deqPort_1_deq_data[167] &&
	  rob$deqPort_1_deq_data[257:253] != 5'd0 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd21 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd17 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd18 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd13 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd16 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd15 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd19 &&
	  rob$deqPort_1_deq_data[257:253] != 5'd20 &&
	  !rob$deqPort_1_deq_data[168])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	  !coreFix_aluExe_1_exeToFinQ$first[16])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	  !coreFix_aluExe_1_exeToFinQ$first[16])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv\", line 332, column 43\nmispredicted branch must have spec tag");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	  !coreFix_aluExe_1_exeToFinQ$first[16])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	  coreFix_aluExe_1_exeToFinQ$first[326:322] != 5'd9 &&
	  coreFix_aluExe_1_exeToFinQ$first[326:322] != 5'd10)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	  coreFix_aluExe_1_exeToFinQ$first[326:322] != 5'd9 &&
	  coreFix_aluExe_1_exeToFinQ$first[326:322] != 5'd10)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv\", line 335, column 54\nonly jr and br can mispredict");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
	  coreFix_aluExe_1_exeToFinQ$first[326:322] != 5'd9 &&
	  coreFix_aluExe_1_exeToFinQ$first[326:322] != 5'd10)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	  !coreFix_aluExe_0_exeToFinQ$first[16])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	  !coreFix_aluExe_0_exeToFinQ$first[16])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv\", line 332, column 43\nmispredicted branch must have spec tag");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	  !coreFix_aluExe_0_exeToFinQ$first[16])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	  coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd9 &&
	  coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd10)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	  coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd9 &&
	  coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd10)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv\", line 335, column 54\nonly jr and br can mispredict");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
	  coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd9 &&
	  coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd10)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
	  coreFix_aluExe_1_regToExeQ$first[395] &&
	  coreFix_aluExe_1_regToExeQ$first[421:417] != 5'd13)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
	  coreFix_aluExe_1_regToExeQ$first[395] &&
	  coreFix_aluExe_1_regToExeQ$first[421:417] != 5'd13)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv\", line 281, column 44\nOnly Csr inst needs to update csrData in ROB");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
	  coreFix_aluExe_1_regToExeQ$first[395] &&
	  coreFix_aluExe_1_regToExeQ$first[421:417] != 5'd13)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
	  coreFix_aluExe_1_regToExeQ$first[395] &&
	  basicExec___d12101[0])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
	  coreFix_aluExe_1_regToExeQ$first[395] &&
	  basicExec___d12101[0])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv\", line 282, column 59\nCsr inst cannot mispredict");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
	  coreFix_aluExe_1_regToExeQ$first[395] &&
	  basicExec___d12101[0])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
	  coreFix_aluExe_1_regToExeQ$first[395] &&
	  (basicExec___d12101[65:2] !=
	   coreFix_aluExe_1_regToExeQ$first[112:49] ||
	   coreFix_aluExe_1_regToExeQ$first[112:49] != y__h626451))
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
	  coreFix_aluExe_1_regToExeQ$first[395] &&
	  (basicExec___d12101[65:2] !=
	   coreFix_aluExe_1_regToExeQ$first[112:49] ||
	   coreFix_aluExe_1_regToExeQ$first[112:49] != y__h626451))
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv\", line 283, column 84\nCsr inst ppc = pc+4");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
	  coreFix_aluExe_1_regToExeQ$first[395] &&
	  (basicExec___d12101[65:2] !=
	   coreFix_aluExe_1_regToExeQ$first[112:49] ||
	   coreFix_aluExe_1_regToExeQ$first[112:49] != y__h626451))
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
	  coreFix_aluExe_0_regToExeQ$first[395] &&
	  coreFix_aluExe_0_regToExeQ$first[421:417] != 5'd13)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
	  coreFix_aluExe_0_regToExeQ$first[395] &&
	  coreFix_aluExe_0_regToExeQ$first[421:417] != 5'd13)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv\", line 281, column 44\nOnly Csr inst needs to update csrData in ROB");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
	  coreFix_aluExe_0_regToExeQ$first[395] &&
	  coreFix_aluExe_0_regToExeQ$first[421:417] != 5'd13)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
	  coreFix_aluExe_0_regToExeQ$first[395] &&
	  basicExec___d12775[0])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
	  coreFix_aluExe_0_regToExeQ$first[395] &&
	  basicExec___d12775[0])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv\", line 282, column 59\nCsr inst cannot mispredict");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
	  coreFix_aluExe_0_regToExeQ$first[395] &&
	  basicExec___d12775[0])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
	  coreFix_aluExe_0_regToExeQ$first[395] &&
	  (basicExec___d12775[65:2] !=
	   coreFix_aluExe_0_regToExeQ$first[112:49] ||
	   coreFix_aluExe_0_regToExeQ$first[112:49] != y__h648788))
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
	  coreFix_aluExe_0_regToExeQ$first[395] &&
	  (basicExec___d12775[65:2] !=
	   coreFix_aluExe_0_regToExeQ$first[112:49] ||
	   coreFix_aluExe_0_regToExeQ$first[112:49] != y__h648788))
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv\", line 283, column 84\nCsr inst ppc = pc+4");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
	  coreFix_aluExe_0_regToExeQ$first[395] &&
	  (basicExec___d12775[65:2] !=
	   coreFix_aluExe_0_regToExeQ$first[112:49] ||
	   coreFix_aluExe_0_regToExeQ$first[112:49] != y__h648788))
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu &&
	  !coreFix_aluExe_1_dispToRegQ$first[131] &&
	  coreFix_aluExe_1_dispToRegQ$first[85] &&
	  !sbCons$lazyLookup_1_get[3] &&
	  IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11588)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu &&
	  !coreFix_aluExe_1_dispToRegQ$first[131] &&
	  coreFix_aluExe_1_dispToRegQ$first[85] &&
	  !sbCons$lazyLookup_1_get[3] &&
	  IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11588)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/Bypass.bsv\", line 57, column 34\nbypass found must be valid");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu &&
	  !coreFix_aluExe_1_dispToRegQ$first[131] &&
	  coreFix_aluExe_1_dispToRegQ$first[85] &&
	  !sbCons$lazyLookup_1_get[3] &&
	  IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11588)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu &&
	  coreFix_aluExe_1_dispToRegQ$first[77] &&
	  !sbCons$lazyLookup_1_get[2] &&
	  IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11596)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu &&
	  coreFix_aluExe_1_dispToRegQ$first[77] &&
	  !sbCons$lazyLookup_1_get[2] &&
	  IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11596)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/Bypass.bsv\", line 57, column 34\nbypass found must be valid");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu &&
	  coreFix_aluExe_1_dispToRegQ$first[77] &&
	  !sbCons$lazyLookup_1_get[2] &&
	  IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__151_ETC___d11596)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu &&
	  !coreFix_aluExe_0_dispToRegQ$first[131] &&
	  coreFix_aluExe_0_dispToRegQ$first[85] &&
	  !sbCons$lazyLookup_0_get[3] &&
	  IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12444)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu &&
	  !coreFix_aluExe_0_dispToRegQ$first[131] &&
	  coreFix_aluExe_0_dispToRegQ$first[85] &&
	  !sbCons$lazyLookup_0_get[3] &&
	  IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12444)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/Bypass.bsv\", line 57, column 34\nbypass found must be valid");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu &&
	  !coreFix_aluExe_0_dispToRegQ$first[131] &&
	  coreFix_aluExe_0_dispToRegQ$first[85] &&
	  !sbCons$lazyLookup_0_get[3] &&
	  IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12444)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu &&
	  coreFix_aluExe_0_dispToRegQ$first[77] &&
	  !sbCons$lazyLookup_0_get[2] &&
	  IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12452)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu &&
	  coreFix_aluExe_0_dispToRegQ$first[77] &&
	  !sbCons$lazyLookup_0_get[2] &&
	  IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12452)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/Bypass.bsv\", line 57, column 34\nbypass found must be valid");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu &&
	  coreFix_aluExe_0_dispToRegQ$first[77] &&
	  !sbCons$lazyLookup_0_get[2] &&
	  IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__236_ETC___d12452)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	  coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] != 2'd0 &&
	  coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] != 2'd1)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	  coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] != 2'd0 &&
	  coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] != 2'd1)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/MulDiv.bsv\", line 174, column 40\nmust be mul func");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
	  coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] != 2'd0 &&
	  coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] != 2'd1)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	  coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] != 2'd2 &&
	  coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] != 2'd3)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	  coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] != 2'd2 &&
	  coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] != 2'd3)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/MulDiv.bsv\", line 196, column 40\nmust be div func");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
	  coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] != 2'd2 &&
	  coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] != 2'd3)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault &&
	  coreFix_memExe_lsq$firstLd[2])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault &&
	  coreFix_memExe_lsq$firstLd[2])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv\", line 698, column 45\ncannot be killed");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault &&
	  coreFix_memExe_lsq$firstLd[2])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	  coreFix_memExe_lsq$firstLd[90])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	  coreFix_memExe_lsq$firstLd[90])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv\", line 709, column 33\nnormal Ld cannot have .rl");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
	  coreFix_memExe_lsq$firstLd[90])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	  (!coreFix_memExe_lsq$firstLd[101] ||
	   coreFix_memExe_lsq$firstLd[16]))
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	  (!coreFix_memExe_lsq$firstLd[101] ||
	   coreFix_memExe_lsq$firstLd[16]))
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv\", line 805, column 62\nmust be non-MMIO Lr");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	  (!coreFix_memExe_lsq$firstLd[101] ||
	   coreFix_memExe_lsq$firstLd[16]))
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	  (coreFix_memExe_lsq$firstLd[7] || coreFix_memExe_lsq$firstLd[2]))
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	  (coreFix_memExe_lsq$firstLd[7] || coreFix_memExe_lsq$firstLd[2]))
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv\", line 806, column 73\nno fualt or kill");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
	  (coreFix_memExe_lsq$firstLd[7] || coreFix_memExe_lsq$firstLd[2]))
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	  (coreFix_memExe_lsq$firstLd[101] ||
	   !coreFix_memExe_lsq$firstLd[16]))
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	  (coreFix_memExe_lsq$firstLd[101] ||
	   !coreFix_memExe_lsq$firstLd[16]))
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv\", line 883, column 61\nmust be MMIO Ld");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	  (coreFix_memExe_lsq$firstLd[101] ||
	   !coreFix_memExe_lsq$firstLd[16]))
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	  (coreFix_memExe_lsq$firstLd[7] || coreFix_memExe_lsq$firstLd[2]))
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	  (coreFix_memExe_lsq$firstLd[7] || coreFix_memExe_lsq$firstLd[2]))
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv\", line 884, column 73\nno fualt or kill");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
	  (coreFix_memExe_lsq$firstLd[7] || coreFix_memExe_lsq$firstLd[2]))
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
	  (coreFix_memExe_lsq$firstLd[101] ||
	   !coreFix_memExe_lsq$firstLd[16]))
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
	  (coreFix_memExe_lsq$firstLd[101] ||
	   !coreFix_memExe_lsq$firstLd[16]))
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv\", line 908, column 61\nmust be MMIO Ld");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
	  (coreFix_memExe_lsq$firstLd[101] ||
	   !coreFix_memExe_lsq$firstLd[16]))
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
	  (coreFix_memExe_lsq$firstLd[7] || coreFix_memExe_lsq$firstLd[2]))
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
	  (coreFix_memExe_lsq$firstLd[7] || coreFix_memExe_lsq$firstLd[2]))
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv\", line 909, column 73\nno fualt or kill");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
	  (coreFix_memExe_lsq$firstLd[7] || coreFix_memExe_lsq$firstLd[2]))
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
	  coreFix_memExe_dTlb_procResp__740_BITS_105_TO__ETC___d1894 &&
	  coreFix_memExe_dTlb$procResp[90])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
	  coreFix_memExe_dTlb_procResp__740_BITS_105_TO__ETC___d1894 &&
	  coreFix_memExe_dTlb$procResp[90])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv\", line 542, column 33\nmust be in LdQ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
	  coreFix_memExe_dTlb_procResp__740_BITS_105_TO__ETC___d1894 &&
	  coreFix_memExe_dTlb$procResp[90])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue &&
	  coreFix_memExe_lsq$firstSt[158:157] != 2'd0 &&
	  coreFix_memExe_lsq$firstSt[158:157] != 2'd2)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue &&
	  coreFix_memExe_lsq$firstSt[158:157] != 2'd0 &&
	  coreFix_memExe_lsq$firstSt[158:157] != 2'd2)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv\", line 1150, column 69\nmust be St/Amo");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue &&
	  coreFix_memExe_lsq$firstSt[158:157] != 2'd0 &&
	  coreFix_memExe_lsq$firstSt[158:157] != 2'd2)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
	  (coreFix_memExe_lsq$firstSt[158:157] != 2'd1 &&
	   coreFix_memExe_lsq$firstSt[158:157] != 2'd2 ||
	   coreFix_memExe_lsq$firstSt[77]))
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
	  (coreFix_memExe_lsq$firstSt[158:157] != 2'd1 &&
	   coreFix_memExe_lsq$firstSt[158:157] != 2'd2 ||
	   coreFix_memExe_lsq$firstSt[77]))
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv\", line 1107, column 36\nmust be non-MMIO Sc/Amo");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
	  (coreFix_memExe_lsq$firstSt[158:157] != 2'd1 &&
	   coreFix_memExe_lsq$firstSt[158:157] != 2'd2 ||
	   coreFix_memExe_lsq$firstSt[77]))
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
	  coreFix_memExe_lsq$firstSt[4])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
	  coreFix_memExe_lsq$firstSt[4])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv\", line 1108, column 44\nno fault");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
	  coreFix_memExe_lsq$firstSt[4])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
	  coreFix_memExe_lsq$firstSt[158:157] != 2'd0 &&
	  coreFix_memExe_lsq$firstSt[158:157] != 2'd2)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
	  coreFix_memExe_lsq$firstSt[158:157] != 2'd0 &&
	  coreFix_memExe_lsq$firstSt[158:157] != 2'd2)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv\", line 1205, column 69\nmust be St/Amo");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
	  coreFix_memExe_lsq$firstSt[158:157] != 2'd0 &&
	  coreFix_memExe_lsq$firstSt[158:157] != 2'd2)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
	  coreFix_memExe_lsq$firstSt[4])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
	  coreFix_memExe_lsq$firstSt[4])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv\", line 1206, column 44\nno fault");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
	  coreFix_memExe_lsq$firstSt[4])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault &&
	  coreFix_memExe_lsq$firstSt[158:157] != 2'd0 &&
	  coreFix_memExe_lsq$firstSt[158:157] != 2'd2)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault &&
	  coreFix_memExe_lsq$firstSt[158:157] != 2'd0 &&
	  coreFix_memExe_lsq$firstSt[158:157] != 2'd2)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv\", line 1230, column 69\nmust be St/Amo");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault &&
	  coreFix_memExe_lsq$firstSt[158:157] != 2'd0 &&
	  coreFix_memExe_lsq$firstSt[158:157] != 2'd2)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault &&
	  coreFix_memExe_lsq$firstSt[4])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault &&
	  coreFix_memExe_lsq$firstSt[4])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv\", line 1231, column 44\nno fault");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault &&
	  coreFix_memExe_lsq$firstSt[4])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	  3'd5)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	  3'd5)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/L1Bank.bsv\", line 733, column 51\nmust be swapped in");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	  3'd5)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	  (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
	   2'd0 ||
	   !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124))
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	  (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
	   2'd0 ||
	   !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124))
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/L1Bank.bsv\", line 735, column 21\ncRq swapped in by previous cRq, tag must match & cs > I");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	  (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
	   2'd0 ||
	   !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124))
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2701)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2701)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/L1Bank.bsv\", line 463, column 13\ncRqHit but tag or cs incorrect");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2701)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	  NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2708)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	  NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2708)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/L1Bank.bsv\", line 502, column 33\nunknown mem op");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	  NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2708)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2714)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2714)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/L1Bank.bsv\", line 638, column 17\nwaitP must be false and cs must not be enough");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2714)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	  3'd1)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	  3'd1)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/L1Bank.bsv\", line 719, column 49\nmust first time go through tag match");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
	  3'd1)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	  (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
	   2'd0 ||
	   !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124))
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	  (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
	   2'd0 ||
	   !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124))
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/L1Bank.bsv\", line 720, column 49\ncRq should hit in tag match");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	  (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
	   2'd0 ||
	   !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124))
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	  !coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	  !coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/L1Bank.bsv\", line 722, column 44\ncRq hit on another cRq, cRqEOC must be true");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2045 &&
	  !coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2725)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2725)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/L1Bank.bsv\", line 781, column 40\nhit, so cs must > I");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2725)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2728)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2728)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/L1Bank.bsv\", line 502, column 33\nunknown mem op");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2728)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2741)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2741)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/L1Bank.bsv\", line 638, column 17\nwaitP must be false and cs must not be enough");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
	  NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2741)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	   !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124))
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	   !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124))
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/L1Bank.bsv\", line 821, column 18\npRs must be a hit");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  (coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2053 ||
	   !coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2124))
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2757)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2757)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/L1Bank.bsv\", line 463, column 13\ncRqHit but tag or cs incorrect");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2757)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	  3'd0 &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	  3'd2 &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	  3'd4 &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	  3'd3 &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	  3'd1)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	  3'd0 &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	  3'd2 &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	  3'd4 &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	  3'd3 &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	  3'd1)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/L1Bank.bsv\", line 502, column 33\nunknown mem op");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	  coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	  3'd0 &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	  3'd2 &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	  3'd4 &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	  3'd3 &&
	  coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
	  3'd1)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	  !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	  !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/coherence/src/L1Bank.bsv\", line 830, column 30\npRs owner must match some cRq");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
	  !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem &&
	  coreFix_memExe_lsq$firstSt[151])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem &&
	  coreFix_memExe_lsq$firstSt[151])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv\", line 962, column 33\nno .rl");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem &&
	  coreFix_memExe_lsq$firstSt[151])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	  coreFix_memExe_lsq$respLd[73] &&
	  coreFix_memExe_lsq$respLd[72])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	  coreFix_memExe_lsq$respLd[73] &&
	  coreFix_memExe_lsq$respLd[72])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv\", line 671, column 42\nwrong path resp cannot write reg");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
	  coreFix_memExe_lsq$respLd[73] &&
	  coreFix_memExe_lsq$respLd[72])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	  coreFix_memExe_lsq$respLd[73] &&
	  coreFix_memExe_lsq$respLd[72])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	  coreFix_memExe_lsq$respLd[73] &&
	  coreFix_memExe_lsq$respLd[72])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv\", line 671, column 42\nwrong path resp cannot write reg");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
	  coreFix_memExe_lsq$respLd[73] &&
	  coreFix_memExe_lsq$respLd[72])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem &&
	  coreFix_memExe_dispToRegQ$first[62] &&
	  !sbCons$lazyLookup_3_get[3] &&
	  IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1660)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem &&
	  coreFix_memExe_dispToRegQ$first[62] &&
	  !sbCons$lazyLookup_3_get[3] &&
	  IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1660)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/Bypass.bsv\", line 57, column 34\nbypass found must be valid");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem &&
	  coreFix_memExe_dispToRegQ$first[62] &&
	  !sbCons$lazyLookup_3_get[3] &&
	  IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1660)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem &&
	  coreFix_memExe_dispToRegQ$first[54] &&
	  !sbCons$lazyLookup_3_get[2] &&
	  IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1667)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem &&
	  coreFix_memExe_dispToRegQ$first[54] &&
	  !sbCons$lazyLookup_3_get[2] &&
	  IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1667)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/Bypass.bsv\", line 57, column 34\nbypass found must be valid");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doRegReadMem &&
	  coreFix_memExe_dispToRegQ$first[54] &&
	  !sbCons$lazyLookup_3_get[2] &&
	  IF_NOT_coreFix_memExe_bypassWire_0_whas__584_5_ETC___d1667)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem &&
	  coreFix_memExe_rsMem$dispatchData[106:104] == 3'd1 &&
	  coreFix_memExe_rsMem$dispatchData[41])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem &&
	  coreFix_memExe_rsMem$dispatchData[106:104] == 3'd1 &&
	  coreFix_memExe_rsMem$dispatchData[41])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv\", line 375, column 18\nSt cannot have dst reg");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_memExe_doDispatchMem &&
	  coreFix_memExe_rsMem$dispatchData[106:104] == 3'd1 &&
	  coreFix_memExe_rsMem$dispatchData[41])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	  coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] != 3'd4 &&
	  coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] != 3'd3)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	  coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] != 3'd4 &&
	  coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] != 3'd3)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv\", line 219, column 33\nunknown execFunc for doExeFpuMulDiv");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
	  coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] != 3'd4 &&
	  coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] != 3'd3)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv &&
	  coreFix_fpuMulDivExe_0_dispToRegQ$first[56] &&
	  !sbCons$lazyLookup_2_get[3] &&
	  IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8403)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv &&
	  coreFix_fpuMulDivExe_0_dispToRegQ$first[56] &&
	  !sbCons$lazyLookup_2_get[3] &&
	  IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8403)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/Bypass.bsv\", line 57, column 34\nbypass found must be valid");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv &&
	  coreFix_fpuMulDivExe_0_dispToRegQ$first[56] &&
	  !sbCons$lazyLookup_2_get[3] &&
	  IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8403)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv &&
	  coreFix_fpuMulDivExe_0_dispToRegQ$first[48] &&
	  !sbCons$lazyLookup_2_get[2] &&
	  IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8410)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv &&
	  coreFix_fpuMulDivExe_0_dispToRegQ$first[48] &&
	  !sbCons$lazyLookup_2_get[2] &&
	  IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8410)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/Bypass.bsv\", line 57, column 34\nbypass found must be valid");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv &&
	  coreFix_fpuMulDivExe_0_dispToRegQ$first[48] &&
	  !sbCons$lazyLookup_2_get[2] &&
	  IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8410)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv &&
	  coreFix_fpuMulDivExe_0_dispToRegQ$first[40] &&
	  !sbCons$lazyLookup_2_get[1] &&
	  IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8417)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv &&
	  coreFix_fpuMulDivExe_0_dispToRegQ$first[40] &&
	  !sbCons$lazyLookup_2_get[1] &&
	  IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8417)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/lib/Bypass.bsv\", line 57, column 34\nbypass found must be valid");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv &&
	  coreFix_fpuMulDivExe_0_dispToRegQ$first[40] &&
	  !sbCons$lazyLookup_2_get[1] &&
	  IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8417)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv &&
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[8])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv &&
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[8])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv\", line 146, column 40\nFpuMulDiv should not carry any spec tag");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv &&
	  coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[8])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas &&
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit == 2'd3)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas &&
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit == 2'd3)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/fpgautils/lib/XilinxIntMul.bsv\", line 147, column 38\ncredit overflow");
    if (RST_N != `BSV_RESET_VALUE)
      if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas &&
	  coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit == 2'd3)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas &&
	  v__h609621 == 2'd0)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas &&
	  v__h609621 == 2'd0)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/fpgautils/lib/XilinxIntMul.bsv\", line 172, column 38\ncredit underflow");
    if (RST_N != `BSV_RESET_VALUE)
      if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas &&
	  v__h609621 == 2'd0)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	  specTagManager$currentSpecBits != 12'd0)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	  specTagManager$currentSpecBits != 12'd0)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 473, column 34\ncannot have spec bits");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	  specTagManager$currentSpecBits != 12'd0)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	  fetchStage$pipelines_0_first[194:192] == 3'd0 &&
	  fetchStage$pipelines_0_first[199:195] != 5'd13)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	  fetchStage$pipelines_0_first[194:192] == 3'd0 &&
	  fetchStage$pipelines_0_first[199:195] != 5'd13)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 498, column 42\nonly CSR inst send to exe");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	  fetchStage$pipelines_0_first[194:192] == 3'd0 &&
	  fetchStage$pipelines_0_first[199:195] != 5'd13)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	  fetchStage$pipelines_0_first[194:192] != 3'd0 &&
	  fetchStage$pipelines_0_first[199:195] != 5'd15 &&
	  fetchStage$pipelines_0_first[199:195] != 5'd16 &&
	  fetchStage$pipelines_0_first[199:195] != 5'd19 &&
	  fetchStage$pipelines_0_first[199:195] != 5'd20)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	  fetchStage$pipelines_0_first[194:192] != 3'd0 &&
	  fetchStage$pipelines_0_first[199:195] != 5'd15 &&
	  fetchStage$pipelines_0_first[199:195] != 5'd16 &&
	  fetchStage$pipelines_0_first[199:195] != 5'd19 &&
	  fetchStage$pipelines_0_first[199:195] != 5'd20)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 505, column 22\nnon-CSR inst not send to exe");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	  fetchStage$pipelines_0_first[194:192] != 3'd0 &&
	  fetchStage$pipelines_0_first[199:195] != 5'd15 &&
	  fetchStage$pipelines_0_first[199:195] != 5'd16 &&
	  fetchStage$pipelines_0_first[199:195] != 5'd19 &&
	  fetchStage$pipelines_0_first[199:195] != 5'd20)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	  fetchStage$pipelines_0_first[194:192] != 3'd0 &&
	  (fetchStage$pipelines_0_first[194:192] == 3'd1 ||
	   fetchStage$pipelines_0_first[194:192] == 3'd2 ||
	   fetchStage$pipelines_0_first[194:192] == 3'd3 ||
	   fetchStage$pipelines_0_first[194:192] == 3'd4))
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	  fetchStage$pipelines_0_first[194:192] != 3'd0 &&
	  (fetchStage$pipelines_0_first[194:192] == 3'd1 ||
	   fetchStage$pipelines_0_first[194:192] == 3'd2 ||
	   fetchStage$pipelines_0_first[194:192] == 3'd3 ||
	   fetchStage$pipelines_0_first[194:192] == 3'd4))
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 507, column 22\nnon-exe inst exec func is other");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	  fetchStage$pipelines_0_first[194:192] != 3'd0 &&
	  (fetchStage$pipelines_0_first[194:192] == 3'd1 ||
	   fetchStage$pipelines_0_first[194:192] == 3'd2 ||
	   fetchStage$pipelines_0_first[194:192] == 3'd3 ||
	   fetchStage$pipelines_0_first[194:192] == 3'd4))
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	  fetchStage$pipelines_0_first[75] &&
	  fetchStage$pipelines_0_first[74])
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	  fetchStage$pipelines_0_first[75] &&
	  fetchStage$pipelines_0_first[74])
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 526, column 29\nsystem inst never touches FP regs");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
	  fetchStage$pipelines_0_first[75] &&
	  fetchStage$pipelines_0_first[74])
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  fetchStage$pipelines_0_canDeq &&
	  regRenamingTable_rename_0_canRename__3528_AND__ETC___d14211)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  fetchStage$pipelines_0_canDeq &&
	  regRenamingTable_rename_0_canRename__3528_AND__ETC___d14211)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 981, column 61\nFpuMulDiv next PC is not PC+4/PC+2");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  fetchStage$pipelines_0_canDeq &&
	  regRenamingTable_rename_0_canRename__3528_AND__ETC___d14211)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  fetchStage$pipelines_0_canDeq &&
	  regRenamingTable_rename_0_canRename__3528_AND__ETC___d14216)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  fetchStage$pipelines_0_canDeq &&
	  regRenamingTable_rename_0_canRename__3528_AND__ETC___d14216)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 982, column 59\nFpuMulDiv never explicitly read/write CSR");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  fetchStage$pipelines_0_canDeq &&
	  regRenamingTable_rename_0_canRename__3528_AND__ETC___d14216)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  fetchStage$pipelines_0_canDeq &&
	  regRenamingTable_rename_0_canRename__3528_AND__ETC___d14241)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  fetchStage$pipelines_0_canDeq &&
	  regRenamingTable_rename_0_canRename__3528_AND__ETC___d14241)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 1013, column 65\nMem next PC is not PC+4/PC+2");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  fetchStage$pipelines_0_canDeq &&
	  regRenamingTable_rename_0_canRename__3528_AND__ETC___d14241)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  fetchStage$pipelines_0_canDeq &&
	  regRenamingTable_rename_0_canRename__3528_AND__ETC___d14245)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  fetchStage$pipelines_0_canDeq &&
	  regRenamingTable_rename_0_canRename__3528_AND__ETC___d14245)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 1014, column 63\nMem never explicitly read/write CSR");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  fetchStage$pipelines_0_canDeq &&
	  regRenamingTable_rename_0_canRename__3528_AND__ETC___d14245)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  fetchStage$pipelines_0_canDeq &&
	  regRenamingTable_rename_0_canRename__3528_AND__ETC___d14251)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  fetchStage$pipelines_0_canDeq &&
	  regRenamingTable_rename_0_canRename__3528_AND__ETC___d14251)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 1016, column 42\nMem (non-Fence) needs imm for virtual addr");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  fetchStage$pipelines_0_canDeq &&
	  regRenamingTable_rename_0_canRename__3528_AND__ETC___d14251)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14378)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14378)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 981, column 61\nFpuMulDiv next PC is not PC+4/PC+2");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14378)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 &&
	  regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 &&
	  NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14381)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 &&
	  regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 &&
	  NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14381)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 982, column 59\nFpuMulDiv never explicitly read/write CSR");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 &&
	  regRenamingTable_rename_1_canRename__3647_AND__ETC___d14318 &&
	  NOT_fetchStage_pipelines_1_first__2937_BITS_19_ETC___d14381)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 &&
	  regRenamingTable_rename_1_canRename__3647_AND__ETC___d14402)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 &&
	  regRenamingTable_rename_1_canRename__3647_AND__ETC___d14402)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 1013, column 65\nMem next PC is not PC+4/PC+2");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 &&
	  regRenamingTable_rename_1_canRename__3647_AND__ETC___d14402)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14407)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14407)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 1014, column 63\nMem never explicitly read/write CSR");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14407)
	$finish(32'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 &&
	  regRenamingTable_rename_1_canRename__3647_AND__ETC___d14412)
	$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 &&
	  regRenamingTable_rename_1_canRename__3647_AND__ETC___d14412)
	$display("Dynamic assertion failed: \"../../src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv\", line 1016, column 42\nMem (non-Fence) needs imm for virtual addr");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_renameStage_doRenaming &&
	  NOT_fetchStage_pipelines_0_canDeq__2926_2927_O_ETC___d14309 &&
	  regRenamingTable_rename_1_canRename__3647_AND__ETC___d14412)
	$finish(32'd0);
  end
  // synopsys translate_on
endmodule  // mkCore

