
VERILOG_SOURCES += $(SPINALROOT)/SdramXdrDdr3S7TesterCocotbTop.v ddr3.v
# OSERDESE2.v IOBUFDS.v OBUFDS.v glbl.v
#$(UNISIM)/OSERDESE2.v $(UNISIM)/IOBUFDS.v $(UNISIM)/OBUFDS.v
TOPLEVEL=SdramXdrDdr3S7TesterCocotbTop
MODULE=Ddr3S7Tester

EXTRA_ARGS += -g2012 -D den2048Mb

include ../../common/Makefile.sim