// vfmv_s_f: vd[0] = rs1 (vs2=0)
require_zvfbfa

VI_VFP_COMMON;

if (vl > 0 && P.VU.vstart->read() < vl) {
  reg_t rd_num = insn.rd();

  switch (P.VU.vsew) {
    case e16:
      P.VU.elt<uint16_t>(rd_num, 0, true) = P.VU.altfmt ? bf16(FRS1).v : f16(FRS1).v;
      break;
    case e32:
      P.VU.elt<uint32_t>(rd_num, 0, true) = f32(FRS1).v;
      break;
    case e64:
      if (FLEN == 64)
        P.VU.elt<uint64_t>(rd_num, 0, true) = f64(FRS1).v;
      else
        P.VU.elt<uint64_t>(rd_num, 0, true) = f32(FRS1).v;
      break;
  }
}
VECTOR_END;
