<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
    <Template>FPGA</Template>
    <Version>5</Version>
    <Device name="GW1NR-9C" pn="GW1NR-LV9QN88PC6/I5">gw1nr9c-004</Device>
    <FileList>
        <File path="project/cache.v" type="file.verilog" enable="0"/>
        <File path="project/cpu.v" type="file.verilog" enable="1"/>
        <File path="project/cpu/alu.v" type="file.verilog" enable="1"/>
        <File path="project/cpu/decode.v" type="file.verilog" enable="1"/>
        <File path="project/cpu/divider.v" type="file.verilog" enable="1"/>
        <File path="project/cpu/execute.v" type="file.verilog" enable="1"/>
        <File path="project/cpu/fetch.v" type="file.verilog" enable="1"/>
        <File path="project/cpu/memory.v" type="file.verilog" enable="1"/>
        <File path="project/cpu/register_bank.v" type="file.verilog" enable="1"/>
        <File path="project/cpu/writeback.v" type="file.verilog" enable="1"/>
        <File path="project/flash.v" type="file.verilog" enable="0"/>
        <File path="project/mmu.v" type="file.verilog" enable="1"/>
        <File path="project/peripheral/buttons.v" type="file.verilog" enable="1"/>
        <File path="project/peripheral/peripheral_manager.v" type="file.verilog" enable="1"/>
        <File path="project/peripheral/pwm_port.v" type="file.verilog" enable="1"/>
        <File path="project/ram.v" type="file.verilog" enable="1"/>
        <File path="project/rom.v" type="file.verilog" enable="1"/>
        <File path="project/top.v" type="file.verilog" enable="1"/>
        <File path="project/uart.v" type="file.verilog" enable="1"/>
        <File path="project/constraints.cst" type="file.cst" enable="1"/>
        <File path="project/init_rom.txt" type="file.other" enable="1"/>
        <File path="project/init_uart.txt" type="file.other" enable="1"/>
    </FileList>
</Project>
