Skip to content

Workspace

/ biriscv /
.git
.Xil
docs
src
tb
build_digilent_arty_a7_100t.tclSep 4, 2026, 3:12:13 AM5.10 KiB
clockInfo.txtSep 4, 2026, 3:19:01 AM375 B
digilent_arty_a7_100t.bitSep 4, 2026, 3:20:18 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptSep 4, 2026, 3:19:13 AM23.67 KiB
digilent_arty_a7_control_sets.rptSep 4, 2026, 3:19:12 AM33.64 KiB
digilent_arty_a7_drc.rptSep 4, 2026, 3:19:55 AM17.06 KiB
digilent_arty_a7_io.rptSep 4, 2026, 3:19:12 AM96.81 KiB
digilent_arty_a7_power.rptSep 4, 2026, 3:19:58 AM8.74 KiB
digilent_arty_a7_route_status.rptSep 4, 2026, 3:19:54 AM651 B
digilent_arty_a7_timing.rptSep 4, 2026, 3:19:56 AM22.74 KiB
digilent_arty_a7_utilization_hierarchical_place.rptSep 4, 2026, 3:19:12 AM7.02 KiB
digilent_arty_a7_utilization_place.rptSep 4, 2026, 3:19:12 AM10.78 KiB
LICENSESep 4, 2026, 3:12:05 AM11.09 KiB
processor_ci_defines.vhSep 4, 2026, 3:12:13 AM300 B
README.mdSep 4, 2026, 3:12:05 AM6.30 KiB