Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date         : Tue Apr 14 23:19:38 2026
| Host         : 685a421e500f running 64-bit unknown
| Command      : report_drc -file digilent_arty_a7_drc.rpt
| Design       : fpga_top
| Device       : xc7a100tcsg324-1
| Speed File   : -1
| Design State : Fully Routed
---------------------------------------------------------------------------------------------------------------------------------------------

Report DRC

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: fpga_top
          Floorplan: design_1
      Design limits: <entire design considered>
           Ruledeck: default
             Max violations: <unlimited>
             Violations found: 22
+-----------+----------+-----------------------------------------------------+------------+
| Rule      | Severity | Description                                         | Violations |
+-----------+----------+-----------------------------------------------------+------------+
| CFGBVS-1  | Warning  | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1          |
| CHECK-3   | Warning  | Report rule limit reached                           | 1          |
| REQP-1840 | Warning  | RAMB18 async control check                          | 20         |
+-----------+----------+-----------------------------------------------------+------------+

2. REPORT DETAILS
-----------------
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties  
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
Related violations: <none>

CHECK-3#1 Warning
Report rule limit reached  
REQP-1840 rule limit reached: 20 violations have been found.
Related violations: <none>

REQP-1840#1 Warning
RAMB18 async control check  
The RAMB18E1 ptop/u_riscv_top/u_icache/u_tag1/ram_reg has an input control pin ptop/u_riscv_top/u_icache/u_tag1/ram_reg/ADDRARDADDR[11] (net: ptop/u_riscv_top/u_icache/u_tag1/tag_addr_r[7]) which is driven by a register (ptop/u_riscv_top/u_core/u_csr/branch_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1840#2 Warning
RAMB18 async control check  
The RAMB18E1 ptop/u_riscv_top/u_icache/u_tag1/ram_reg has an input control pin ptop/u_riscv_top/u_icache/u_tag1/ram_reg/ADDRARDADDR[11] (net: ptop/u_riscv_top/u_icache/u_tag1/tag_addr_r[7]) which is driven by a register (ptop/u_riscv_top/u_core/u_frontend/u_decode/u_fifo/count_q_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1840#3 Warning
RAMB18 async control check  
The RAMB18E1 ptop/u_riscv_top/u_icache/u_tag1/ram_reg has an input control pin ptop/u_riscv_top/u_icache/u_tag1/ram_reg/ADDRARDADDR[11] (net: ptop/u_riscv_top/u_icache/u_tag1/tag_addr_r[7]) which is driven by a register (ptop/u_riscv_top/u_core/u_frontend/u_decode/u_fifo/pc_q_reg[1][3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1840#4 Warning
RAMB18 async control check  
The RAMB18E1 ptop/u_riscv_top/u_icache/u_tag1/ram_reg has an input control pin ptop/u_riscv_top/u_icache/u_tag1/ram_reg/ADDRARDADDR[11] (net: ptop/u_riscv_top/u_icache/u_tag1/tag_addr_r[7]) which is driven by a register (ptop/u_riscv_top/u_core/u_frontend/u_decode/u_fifo/pc_q_reg[1][4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1840#5 Warning
RAMB18 async control check  
The RAMB18E1 ptop/u_riscv_top/u_icache/u_tag1/ram_reg has an input control pin ptop/u_riscv_top/u_icache/u_tag1/ram_reg/ADDRARDADDR[11] (net: ptop/u_riscv_top/u_icache/u_tag1/tag_addr_r[7]) which is driven by a register (ptop/u_riscv_top/u_core/u_frontend/u_decode/u_fifo/rd_ptr_q_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1840#6 Warning
RAMB18 async control check  
The RAMB18E1 ptop/u_riscv_top/u_icache/u_tag1/ram_reg has an input control pin ptop/u_riscv_top/u_icache/u_tag1/ram_reg/ADDRARDADDR[11] (net: ptop/u_riscv_top/u_icache/u_tag1/tag_addr_r[7]) which is driven by a register (ptop/u_riscv_top/u_core/u_frontend/u_fetch/branch_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1840#7 Warning
RAMB18 async control check  
The RAMB18E1 ptop/u_riscv_top/u_icache/u_tag1/ram_reg has an input control pin ptop/u_riscv_top/u_icache/u_tag1/ram_reg/ADDRARDADDR[11] (net: ptop/u_riscv_top/u_icache/u_tag1/tag_addr_r[7]) which is driven by a register (ptop/u_riscv_top/u_core/u_issue/pc_x_q_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1840#8 Warning
RAMB18 async control check  
The RAMB18E1 ptop/u_riscv_top/u_icache/u_tag1/ram_reg has an input control pin ptop/u_riscv_top/u_icache/u_tag1/ram_reg/ADDRARDADDR[11] (net: ptop/u_riscv_top/u_icache/u_tag1/tag_addr_r[7]) which is driven by a register (ptop/u_riscv_top/u_core/u_issue/pc_x_q_reg[14]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1840#9 Warning
RAMB18 async control check  
The RAMB18E1 ptop/u_riscv_top/u_icache/u_tag1/ram_reg has an input control pin ptop/u_riscv_top/u_icache/u_tag1/ram_reg/ADDRARDADDR[11] (net: ptop/u_riscv_top/u_icache/u_tag1/tag_addr_r[7]) which is driven by a register (ptop/u_riscv_top/u_core/u_issue/pc_x_q_reg[15]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1840#10 Warning
RAMB18 async control check  
The RAMB18E1 ptop/u_riscv_top/u_icache/u_tag1/ram_reg has an input control pin ptop/u_riscv_top/u_icache/u_tag1/ram_reg/ADDRARDADDR[11] (net: ptop/u_riscv_top/u_icache/u_tag1/tag_addr_r[7]) which is driven by a register (ptop/u_riscv_top/u_core/u_issue/pc_x_q_reg[17]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1840#11 Warning
RAMB18 async control check  
The RAMB18E1 ptop/u_riscv_top/u_icache/u_tag1/ram_reg has an input control pin ptop/u_riscv_top/u_icache/u_tag1/ram_reg/ADDRARDADDR[11] (net: ptop/u_riscv_top/u_icache/u_tag1/tag_addr_r[7]) which is driven by a register (ptop/u_riscv_top/u_core/u_issue/pc_x_q_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1840#12 Warning
RAMB18 async control check  
The RAMB18E1 ptop/u_riscv_top/u_icache/u_tag1/ram_reg has an input control pin ptop/u_riscv_top/u_icache/u_tag1/ram_reg/ADDRARDADDR[11] (net: ptop/u_riscv_top/u_icache/u_tag1/tag_addr_r[7]) which is driven by a register (ptop/u_riscv_top/u_core/u_issue/pc_x_q_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1840#13 Warning
RAMB18 async control check  
The RAMB18E1 ptop/u_riscv_top/u_icache/u_tag1/ram_reg has an input control pin ptop/u_riscv_top/u_icache/u_tag1/ram_reg/ADDRARDADDR[11] (net: ptop/u_riscv_top/u_icache/u_tag1/tag_addr_r[7]) which is driven by a register (ptop/u_riscv_top/u_core/u_issue/pc_x_q_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1840#14 Warning
RAMB18 async control check  
The RAMB18E1 ptop/u_riscv_top/u_icache/u_tag1/ram_reg has an input control pin ptop/u_riscv_top/u_icache/u_tag1/ram_reg/ADDRARDADDR[11] (net: ptop/u_riscv_top/u_icache/u_tag1/tag_addr_r[7]) which is driven by a register (ptop/u_riscv_top/u_core/u_issue/pc_x_q_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1840#15 Warning
RAMB18 async control check  
The RAMB18E1 ptop/u_riscv_top/u_icache/u_tag1/ram_reg has an input control pin ptop/u_riscv_top/u_icache/u_tag1/ram_reg/ADDRARDADDR[11] (net: ptop/u_riscv_top/u_icache/u_tag1/tag_addr_r[7]) which is driven by a register (ptop/u_riscv_top/u_core/u_issue/pc_x_q_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1840#16 Warning
RAMB18 async control check  
The RAMB18E1 ptop/u_riscv_top/u_icache/u_tag1/ram_reg has an input control pin ptop/u_riscv_top/u_icache/u_tag1/ram_reg/ADDRARDADDR[11] (net: ptop/u_riscv_top/u_icache/u_tag1/tag_addr_r[7]) which is driven by a register (ptop/u_riscv_top/u_core/u_issue/pc_x_q_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1840#17 Warning
RAMB18 async control check  
The RAMB18E1 ptop/u_riscv_top/u_icache/u_tag1/ram_reg has an input control pin ptop/u_riscv_top/u_icache/u_tag1/ram_reg/ADDRARDADDR[11] (net: ptop/u_riscv_top/u_icache/u_tag1/tag_addr_r[7]) which is driven by a register (ptop/u_riscv_top/u_core/u_issue/pc_x_q_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1840#18 Warning
RAMB18 async control check  
The RAMB18E1 ptop/u_riscv_top/u_icache/u_tag1/ram_reg has an input control pin ptop/u_riscv_top/u_icache/u_tag1/ram_reg/ADDRARDADDR[11] (net: ptop/u_riscv_top/u_icache/u_tag1/tag_addr_r[7]) which is driven by a register (ptop/u_riscv_top/u_core/u_issue/pc_x_q_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1840#19 Warning
RAMB18 async control check  
The RAMB18E1 ptop/u_riscv_top/u_icache/u_tag1/ram_reg has an input control pin ptop/u_riscv_top/u_icache/u_tag1/ram_reg/ADDRARDADDR[11] (net: ptop/u_riscv_top/u_icache/u_tag1/tag_addr_r[7]) which is driven by a register (ptop/u_riscv_top/u_icache/flush_addr_q_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>

REQP-1840#20 Warning
RAMB18 async control check  
The RAMB18E1 ptop/u_riscv_top/u_icache/u_tag1/ram_reg has an input control pin ptop/u_riscv_top/u_icache/u_tag1/ram_reg/ADDRARDADDR[11] (net: ptop/u_riscv_top/u_icache/u_tag1/tag_addr_r[7]) which is driven by a register (ptop/u_riscv_top/u_icache/lookup_addr_q_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
Related violations: <none>


