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build_digilent_arty_a7_100t.tclSep 9, 2026, 3:12:13 AM5.10 KiB
clockInfo.txtSep 9, 2026, 3:18:53 AM375 B
digilent_arty_a7_100t.bitSep 9, 2026, 3:20:07 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptSep 9, 2026, 3:19:05 AM23.67 KiB
digilent_arty_a7_control_sets.rptSep 9, 2026, 3:19:04 AM33.64 KiB
digilent_arty_a7_drc.rptSep 9, 2026, 3:19:45 AM17.21 KiB
digilent_arty_a7_io.rptSep 9, 2026, 3:19:04 AM96.81 KiB
digilent_arty_a7_power.rptSep 9, 2026, 3:19:47 AM8.74 KiB
digilent_arty_a7_route_status.rptSep 9, 2026, 3:19:43 AM651 B
digilent_arty_a7_timing.rptSep 9, 2026, 3:19:46 AM22.74 KiB
digilent_arty_a7_utilization_hierarchical_place.rptSep 9, 2026, 3:19:04 AM7.02 KiB
digilent_arty_a7_utilization_place.rptSep 9, 2026, 3:19:04 AM10.78 KiB
LICENSESep 9, 2026, 3:12:06 AM11.09 KiB
processor_ci_defines.vhSep 9, 2026, 3:12:13 AM300 B
README.mdSep 9, 2026, 3:12:06 AM6.30 KiB