Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date         : Sun Aug  2 23:19:54 2026
| Host         : 685a421e500f running 64-bit unknown
| Command      : report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
| Design       : fpga_top
| Device       : xc7a100t
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |   135 |
|    Minimum number of control sets                        |   135 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |   238 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |   135 |
| >= 0 to < 4        |     3 |
| >= 4 to < 6        |     5 |
| >= 6 to < 8        |     2 |
| >= 8 to < 10       |     7 |
| >= 10 to < 12      |     4 |
| >= 12 to < 14      |     3 |
| >= 14 to < 16      |     0 |
| >= 16              |   111 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |               7 |            4 |
| No           | No                    | Yes                    |              73 |           30 |
| No           | Yes                   | No                     |              52 |           27 |
| Yes          | No                    | No                     |             163 |           68 |
| Yes          | No                    | Yes                    |            2524 |         1027 |
| Yes          | Yes                   | No                     |             407 |          110 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+----------------+------------------------------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+
|  Clock Signal  |                                       Enable Signal                                      |                       Set/Reset Signal                       | Slice Load Count | Bel Load Count | Bels / Slice |
+----------------+------------------------------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                                         | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_1_n_0             |                1 |              1 |         1.00 |
|  clk_IBUF_BUFG |                                                                                          |                                                              |                1 |              1 |         1.00 |
|  clk_core      | ptop/Data_mem/FSM_onehot_state[4]_i_1__0_n_0                                             | ptop/u_Controller/Interpreter/AR[0]                          |                1 |              3 |         3.00 |
|  clk_o_BUFG    | ResetBootSystem/counter                                                                  |                                                              |                1 |              4 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_2__0_n_0                               | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_1_n_0      |                1 |              4 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_tx/E[0]                                                    |                                                              |                1 |              4 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_rx/next_bit                                                | ptop/u_Controller/Uart/i_uart_rx/bit_counter[3]_i_1__0_n_0   |                1 |              4 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/return_state                                               | ResetBootSystem/rst_o_reg_0                                  |                1 |              5 |         5.00 |
|  clk_o_BUFG    |                                                                                          |                                                              |                3 |              6 |         2.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_tx/data_to_send[6]_i_1_n_0                                 | ResetBootSystem/rst_o_reg_0                                  |                2 |              7 |         3.50 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/counter                                                    | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/accumulator[7]_i_1_n_0                                     | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/tx_fifo/FSM_sequential_state_write_reg[2][0]                      | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/uart_tx_en                                                        | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_rx/E[0]                                                    | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_rx/recieved_data0                                          | ptop/u_Controller/Uart/i_uart_rx/recieved_data[7]_i_1_n_0    |                2 |              8 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_rx/uart_rx_data[7]_i_1_n_0                                 | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_rx/cycle_counter0                                          | ptop/u_Controller/Uart/i_uart_rx/cycle_counter[9]_i_1__0_n_0 |                3 |             10 |         3.33 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                                         | ResetBootSystem/SR[0]                                        |                3 |             10 |         3.33 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/tx_fifo/read_ptr[2]_i_1_n_0                                       | ResetBootSystem/rst_o_reg_0                                  |                3 |             11 |         3.67 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/rx_fifo/read_ptr0                                                 | ResetBootSystem/rst_o_reg_0                                  |                3 |             11 |         3.67 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/rx_fifo/memory_reg_0_7_0_5_i_1__0_n_0                             |                                                              |                2 |             12 |         6.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address[31]_i_1_n_0                                        |                                                              |                9 |             12 |         1.33 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/tx_fifo/memory_reg_0_7_0_5_i_1_n_0                                |                                                              |                2 |             12 |         6.00 |
|  clk_core      | ptop/u_riscv_top/u_core/u_issue/u_pipe0_ctrl/BRANCH_PREDICTION.btb_pc_q[30][31]_i_2_0[0] | ptop/u_Controller/Interpreter/AR[0]                          |                7 |             16 |         2.29 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/memory_page_number[23]_i_2_n_0                             | ptop/u_Controller/Interpreter/memory_page_number[23]_i_1_n_0 |                7 |             24 |         3.43 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/timeout                                                    | ResetBootSystem/rst_o_reg_0                                  |                8 |             24 |         3.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/accumulator0                                               | ResetBootSystem/rst_o_reg_0                                  |                6 |             24 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/num_of_pages                                               | ResetBootSystem/rst_o_reg_0                                  |                5 |             24 |         4.80 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/num_of_cycles_to_pulse[23]_i_1_n_0                         |                                                              |               11 |             24 |         2.18 |
|  clk_core      | ptop/u_riscv_top/u_icache/u_tag1/FSM_sequential_state_q_reg[0][0]                        | ptop/u_Controller/Interpreter/AR[0]                          |                9 |             27 |         3.00 |
|  clk_core      | ptop/u_riscv_top/u_icache/u_tag1/addr_reg                                                | ptop/u_Controller/Interpreter/AR[0]                          |               11 |             27 |         2.45 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_decode/u_fifo/pc_q[0][31]_i_1_n_0                   | ptop/u_Controller/Interpreter/AR[0]                          |                8 |             29 |         3.62 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_decode/u_fifo/ram_q                                 | ptop/u_Controller/Interpreter/AR[0]                          |                7 |             29 |         4.14 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_fetch/icache_fetch_q0                               | ptop/u_Controller/Interpreter/AR[0]                          |               10 |             29 |         2.90 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[0]_1[0]      | ptop/u_Controller/Interpreter/AR[0]                          |                9 |             30 |         3.33 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[2]_12[0]     | ptop/u_Controller/Interpreter/AR[0]                          |               15 |             30 |         2.00 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[2]_3[0]      | ptop/u_Controller/Interpreter/AR[0]                          |                9 |             30 |         3.33 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[3]_9[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               12 |             30 |         2.50 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[0]_0[0]      | ptop/u_Controller/Interpreter/AR[0]                          |                9 |             30 |         3.33 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[2]_9[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               12 |             30 |         2.50 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[4]_0[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               13 |             30 |         2.31 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[3]_13[0]     | ptop/u_Controller/Interpreter/AR[0]                          |               13 |             30 |         2.31 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[2]_10[0]     | ptop/u_Controller/Interpreter/AR[0]                          |                9 |             30 |         3.33 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[0]_6[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               20 |             30 |         1.50 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[2]_6[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               11 |             30 |         2.73 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[3]_11[0]     | ptop/u_Controller/Interpreter/AR[0]                          |                9 |             30 |         3.33 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[3]_10[0]     | ptop/u_Controller/Interpreter/AR[0]                          |                5 |             30 |         6.00 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[2]_0[0]      | ptop/u_Controller/Interpreter/AR[0]                          |                7 |             30 |         4.29 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[2]_4[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               12 |             30 |         2.50 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[4]_5[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               10 |             30 |         3.00 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[0]_4[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               12 |             30 |         2.50 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[2]_7[0]      | ptop/u_Controller/Interpreter/AR[0]                          |                9 |             30 |         3.33 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[1]_0[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               10 |             30 |         3.00 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[3]_8[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               12 |             30 |         2.50 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[2]_15[0]     | ptop/u_Controller/Interpreter/AR[0]                          |                9 |             30 |         3.33 |
|  clk_core      | ptop/u_riscv_top/u_core/u_issue/u_pipe0_ctrl/lfsr_q_reg[2]_0[0]                          | ptop/u_Controller/Interpreter/AR[0]                          |               10 |             30 |         3.00 |
|  clk_core      | ptop/u_riscv_top/u_core/u_issue/u_pipe0_ctrl/lfsr_q_reg[2]_1[0]                          | ptop/u_Controller/Interpreter/AR[0]                          |               11 |             30 |         2.73 |
|  clk_core      | ptop/u_riscv_top/u_core/u_issue/u_pipe0_ctrl/lfsr_q_reg[3]_0[0]                          | ptop/u_Controller/Interpreter/AR[0]                          |               10 |             30 |         3.00 |
|  clk_core      | ptop/u_riscv_top/u_core/u_issue/u_pipe0_ctrl/lfsr_q_reg[3][0]                            | ptop/u_Controller/Interpreter/AR[0]                          |                8 |             30 |         3.75 |
|  clk_core      | ptop/u_riscv_top/u_core/u_issue/u_pipe0_ctrl/lfsr_q_reg[2][0]                            | ptop/u_Controller/Interpreter/AR[0]                          |               10 |             30 |         3.00 |
|  clk_core      | ptop/u_riscv_top/u_core/u_issue/u_pipe0_ctrl/lfsr_q_reg[1][0]                            | ptop/u_Controller/Interpreter/AR[0]                          |                8 |             30 |         3.75 |
|  clk_core      | ptop/u_riscv_top/u_core/u_issue/u_pipe0_ctrl/lfsr_q_reg[0][0]                            | ptop/u_Controller/Interpreter/AR[0]                          |               14 |             30 |         2.14 |
|  clk_core      | ptop/u_riscv_top/u_core/u_issue/u_pipe0_ctrl/lfsr_q_reg[3]_2[0]                          | ptop/u_Controller/Interpreter/AR[0]                          |               11 |             30 |         2.73 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[2]_16[0]     | ptop/u_Controller/Interpreter/AR[0]                          |               15 |             30 |         2.00 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[3]_14[0]     | ptop/u_Controller/Interpreter/AR[0]                          |               14 |             30 |         2.14 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[4]_1[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               12 |             30 |         2.50 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[0]_7[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               16 |             30 |         1.88 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[3]_16[0]     | ptop/u_Controller/Interpreter/AR[0]                          |               13 |             30 |         2.31 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[2]_14[0]     | ptop/u_Controller/Interpreter/AR[0]                          |               12 |             30 |         2.50 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[3]_15[0]     | ptop/u_Controller/Interpreter/AR[0]                          |               14 |             30 |         2.14 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[3]_17[0]     | ptop/u_Controller/Interpreter/AR[0]                          |               20 |             30 |         1.50 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/E[0]                    | ptop/u_Controller/Interpreter/AR[0]                          |               16 |             30 |         1.88 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[2]_13[0]     | ptop/u_Controller/Interpreter/AR[0]                          |               26 |             30 |         1.15 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[3]_0[0]      | ptop/u_Controller/Interpreter/AR[0]                          |                9 |             30 |         3.33 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[2]_5[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               10 |             30 |         3.00 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[2]_8[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               24 |             30 |         1.25 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[3]_6[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               24 |             30 |         1.25 |
|  clk_core      | ptop/u_riscv_top/u_core/u_issue/u_pipe0_ctrl/lfsr_q_reg[3]_1[0]                          | ptop/u_Controller/Interpreter/AR[0]                          |                9 |             30 |         3.33 |
|  clk_core      | ptop/u_riscv_top/u_core/u_issue/u_pipe0_ctrl/lfsr_q_reg[0]_0[0]                          | ptop/u_Controller/Interpreter/AR[0]                          |                8 |             30 |         3.75 |
|  clk_core      | ptop/u_riscv_top/u_core/u_issue/u_pipe0_ctrl/lfsr_q_reg[4]_0[0]                          | ptop/u_Controller/Interpreter/AR[0]                          |               11 |             30 |         2.73 |
|  clk_core      | ptop/u_riscv_top/u_core/u_issue/u_pipe0_ctrl/lfsr_q_reg[4][0]                            | ptop/u_Controller/Interpreter/AR[0]                          |               13 |             30 |         2.31 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[2]_2[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               10 |             30 |         3.00 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[4]_6[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               23 |             30 |         1.30 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[0]_2[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               12 |             30 |         2.50 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[3]_1[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               10 |             30 |         3.00 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[2]_1[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               10 |             30 |         3.00 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[4]_2[0]      | ptop/u_Controller/Interpreter/AR[0]                          |                8 |             30 |         3.75 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[3]_2[0]      | ptop/u_Controller/Interpreter/AR[0]                          |                7 |             30 |         4.29 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[3]_3[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               16 |             30 |         1.88 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[3]_4[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               11 |             30 |         2.73 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[3]_7[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               14 |             30 |         2.14 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[3]_5[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               26 |             30 |         1.15 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[2]_11[0]     | ptop/u_Controller/Interpreter/AR[0]                          |               18 |             30 |         1.67 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[3]_12[0]     | ptop/u_Controller/Interpreter/AR[0]                          |               25 |             30 |         1.20 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[0]_5[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               11 |             30 |         2.73 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[0]_3[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               13 |             30 |         2.31 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[4]_4[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               15 |             30 |         2.00 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.u_lru/lfsr_q_reg[4]_3[0]      | ptop/u_Controller/Interpreter/AR[0]                          |               21 |             30 |         1.43 |
|  clk_core      | ptop/u_riscv_top/u_core/u_issue/u_pipe0_ctrl/branch_q_reg[0]                             | ptop/u_Controller/Interpreter/AR[0]                          |                7 |             31 |         4.43 |
|  clk_o_BUFG    | ptop/u_Controller/ClkDivider/pulse_counter[0]_i_1_n_0                                    | ResetBootSystem/rst_o_reg_0                                  |                8 |             32 |         4.00 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.ras_stack_q[1][31]_i_1_n_0    | ptop/u_Controller/Interpreter/AR[0]                          |                9 |             32 |         3.56 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.ras_stack_q[0][31]_i_1_n_0    | ptop/u_Controller/Interpreter/AR[0]                          |                9 |             32 |         3.56 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.ras_stack_q[2][31]_i_1_n_0    | ptop/u_Controller/Interpreter/AR[0]                          |               11 |             32 |         2.91 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.ras_stack_q[4][31]_i_1_n_0    | ptop/u_Controller/Interpreter/AR[0]                          |                9 |             32 |         3.56 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.ras_stack_q[6][31]_i_1_n_0    | ptop/u_Controller/Interpreter/AR[0]                          |                9 |             32 |         3.56 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.ras_stack_q[7][31]_i_1_n_0    | ptop/u_Controller/Interpreter/AR[0]                          |               16 |             32 |         2.00 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.ras_stack_q[5][31]_i_1_n_0    | ptop/u_Controller/Interpreter/AR[0]                          |                9 |             32 |         3.56 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_npc/BRANCH_PREDICTION.ras_stack_q[3][31]_i_1_n_0    | ptop/u_Controller/Interpreter/AR[0]                          |               10 |             32 |         3.20 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/read_buffer[31]_i_1_n_0                                    | ResetBootSystem/rst_o_reg_0                                  |               17 |             32 |         1.88 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/communication_write_data[31]_i_1_n_0                       |                                                              |               13 |             32 |         2.46 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/write_data[31]_i_1_n_0                                     |                                                              |               18 |             32 |         1.78 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/timeout_counter                                            | ResetBootSystem/rst_o_reg_0                                  |                7 |             32 |         4.57 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/end_position[31]_i_1_n_0                                   | ResetBootSystem/rst_o_reg_0                                  |               12 |             32 |         2.67 |
|  clk_core      | ptop/u_riscv_top/u_icache/u_tag1/E[0]                                                    | ptop/u_Controller/Interpreter/AR[0]                          |               22 |             32 |         1.45 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/rx_fifo/E[0]                                                      | ResetBootSystem/rst_o_reg_0                                  |                6 |             32 |         5.33 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/communication_buffer[31]_i_1_n_0                           | ResetBootSystem/rst_o_reg_0                                  |                9 |             32 |         3.56 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/tx_fifo/E[0]                                                      | ResetBootSystem/rst_o_reg_0                                  |                5 |             32 |         6.40 |
|  clk_core      | ptop/u_riscv_top/u_core/u_frontend/u_fetch/branch_pc_q[31]_i_1_n_0                       | ptop/u_Controller/Interpreter/AR[0]                          |               14 |             33 |         2.36 |
|  clk_o_BUFG    |                                                                                          | ResetBootSystem/rst_o_reg_0                                  |               27 |             52 |         1.93 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/num_of_positions[23]_i_1_n_0                               |                                                              |               15 |             55 |         3.67 |
|  clk_core      | ptop/u_riscv_top/u_core/u_issue/u_pipe0_ctrl/E[0]                                        | ptop/u_Controller/Interpreter/AR[0]                          |               16 |             60 |         3.75 |
|  clk_core      |                                                                                          | ptop/u_Controller/Interpreter/AR[0]                          |               30 |             73 |         2.43 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/addr_reg_reg[12]_3                                         |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/addr_reg_reg[12]_2                                         |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/addr_reg_reg[12]_1                                         |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/addr_reg_reg[12]                                           |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/addr_reg_reg[12]_0                                         |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/addr_reg_reg[12]_4                                         |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/addr_reg_reg[12]_5                                         |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/addr_reg_reg[12]_6                                         |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/memory_mux_selector_reg_3                                  |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/memory_mux_selector_reg_2                                  |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/memory_mux_selector_reg_4                                  |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/memory_mux_selector_reg_1                                  |                                                              |               32 |            128 |         4.00 |
+----------------+------------------------------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+


