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build_digilent_arty_a7_100t.tclSep 21, 2026, 3:12:10 AM5.10 KiB
clockInfo.txtSep 21, 2026, 3:18:47 AM375 B
digilent_arty_a7_100t.bitSep 21, 2026, 3:20:00 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptSep 21, 2026, 3:18:58 AM23.67 KiB
digilent_arty_a7_control_sets.rptSep 21, 2026, 3:18:57 AM33.64 KiB
digilent_arty_a7_drc.rptSep 21, 2026, 3:19:38 AM16.92 KiB
digilent_arty_a7_io.rptSep 21, 2026, 3:18:57 AM96.81 KiB
digilent_arty_a7_power.rptSep 21, 2026, 3:19:40 AM8.74 KiB
digilent_arty_a7_route_status.rptSep 21, 2026, 3:19:36 AM651 B
digilent_arty_a7_timing.rptSep 21, 2026, 3:19:39 AM22.74 KiB
digilent_arty_a7_utilization_hierarchical_place.rptSep 21, 2026, 3:18:57 AM7.02 KiB
digilent_arty_a7_utilization_place.rptSep 21, 2026, 3:18:57 AM10.78 KiB
LICENSESep 21, 2026, 3:12:04 AM11.09 KiB
processor_ci_defines.vhSep 21, 2026, 3:12:10 AM300 B
README.mdSep 21, 2026, 3:12:04 AM6.30 KiB