Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date         : Mon Jun 29 00:31:55 2026
| Host         : 685a421e500f running 64-bit unknown
| Command      : report_drc -file digilent_arty_a7_drc.rpt
| Design       : fpga_top
| Device       : xc7a100tcsg324-1
| Speed File   : -1
| Design State : Fully Routed
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Report DRC

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: fpga_top
          Floorplan: design_1
      Design limits: <entire design considered>
           Ruledeck: default
             Max violations: <unlimited>
             Violations found: 30
+-------------+----------+-------------------------------------------------------------+------------+
| Rule        | Severity | Description                                                 | Violations |
+-------------+----------+-------------------------------------------------------------+------------+
| CFGBVS-1    | Warning  | Missing CFGBVS and CONFIG_VOLTAGE Design Properties         | 1          |
| DPIP-1      | Warning  | Input pipelining                                            | 5          |
| DPOP-1      | Warning  | PREG Output pipelining                                      | 3          |
| DPOP-2      | Warning  | MREG Output pipelining                                      | 3          |
| PDRC-153    | Warning  | Gated clock check                                           | 10         |
| PLHOLDVIO-2 | Warning  | Non-Optimal connections which could lead to hold violations | 8          |
+-------------+----------+-------------------------------------------------------------+------------+

2. REPORT DETAILS
-----------------
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties  
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
Related violations: <none>

DPIP-1#1 Warning
Input pipelining  
DSP ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result input ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>

DPIP-1#2 Warning
Input pipelining  
DSP ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result input ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>

DPIP-1#3 Warning
Input pipelining  
DSP ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__0 input ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>

DPIP-1#4 Warning
Input pipelining  
DSP ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__0 input ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>

DPIP-1#5 Warning
Input pipelining  
DSP ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__1 input ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>

DPOP-1#1 Warning
PREG Output pipelining  
DSP ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result output ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>

DPOP-1#2 Warning
PREG Output pipelining  
DSP ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__0 output ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>

DPOP-1#3 Warning
PREG Output pipelining  
DSP ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__1 output ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>

DPOP-2#1 Warning
MREG Output pipelining  
DSP ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result multiplier stage ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>

DPOP-2#2 Warning
MREG Output pipelining  
DSP ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__0 multiplier stage ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>

DPOP-2#3 Warning
MREG Output pipelining  
DSP ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__1 multiplier stage ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>

PDRC-153#1 Warning
Gated clock check  
Net ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated is a gated clock net sourced by a combinational pin ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__8/O, cell ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__8. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>

PDRC-153#2 Warning
Gated clock check  
Net ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_0 is a gated clock net sourced by a combinational pin ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__9/O, cell ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__9. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>

PDRC-153#3 Warning
Gated clock check  
Net ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_1 is a gated clock net sourced by a combinational pin ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__10/O, cell ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__10. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>

PDRC-153#4 Warning
Gated clock check  
Net ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_2 is a gated clock net sourced by a combinational pin ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__11/O, cell ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__11. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>

PDRC-153#5 Warning
Gated clock check  
Net ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_3 is a gated clock net sourced by a combinational pin ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_1__107/O, cell ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_1__107. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>

PDRC-153#6 Warning
Gated clock check  
Net ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_4 is a gated clock net sourced by a combinational pin ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__12/O, cell ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__12. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>

PDRC-153#7 Warning
Gated clock check  
Net ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_6 is a gated clock net sourced by a combinational pin ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__15/O, cell ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__15. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>

PDRC-153#8 Warning
Gated clock check  
Net ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_7 is a gated clock net sourced by a combinational pin ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__16/O, cell ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__16. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>

PDRC-153#9 Warning
Gated clock check  
Net ptop/u_Controller/ClkDivider/clk_o_reg_0 is a gated clock net sourced by a combinational pin ptop/u_Controller/ClkDivider/clk_en_reg_i_2__9/O, cell ptop/u_Controller/ClkDivider/clk_en_reg_i_2__9. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>

PDRC-153#10 Warning
Gated clock check  
Net ptop/u_Controller/ClkDivider/clk_o_reg_1 is a gated clock net sourced by a combinational pin ptop/u_Controller/ClkDivider/clk_en_reg_i_1__9/O, cell ptop/u_Controller/ClkDivider/clk_en_reg_i_1__9. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>

PLHOLDVIO-2#1 Warning
Non-Optimal connections which could lead to hold violations  
A LUT ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_1__107 is driving clock pin of 1 cells. This could lead to large hold time violations. Involved cells are:
ptop/cv32e40s_core_i/cs_registers_i/mstateen0_csr_i/gen_hardened.gen_csr_hardened[2].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg
Related violations: <none>

PLHOLDVIO-2#2 Warning
Non-Optimal connections which could lead to hold violations  
A LUT ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__10 is driving clock pin of 19 cells. This could lead to large hold time violations. Involved cells are:
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[11].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[16].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[17].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[18].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[19].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[20].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[21].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[22].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[23].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[24].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[25].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[26].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[27].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[28].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[29].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg
 (the first 15 of 19 listed)
Related violations: <none>

PLHOLDVIO-2#3 Warning
Non-Optimal connections which could lead to hold violations  
A LUT ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__11 is driving clock pin of 9 cells. This could lead to large hold time violations. Involved cells are:
ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.gen_csr_hardened[0].gen_unmasked_hardened.gen_rv1.sffs_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.gen_csr_hardened[16].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.gen_csr_hardened[17].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.gen_csr_hardened[18].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.gen_csr_hardened[19].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.gen_csr_hardened[1].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.gen_csr_hardened[2].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.gen_csr_hardened[3].gen_unmasked_hardened.gen_rv1.sffs_rdatareg/q_o_reg
ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.gen_csr_hardened[4].gen_unmasked_hardened.gen_rv1.sffs_rdatareg/q_o_reg
Related violations: <none>

PLHOLDVIO-2#4 Warning
Non-Optimal connections which could lead to hold violations  
A LUT ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__12 is driving clock pin of 26 cells. This could lead to large hold time violations. Involved cells are:
ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[10].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[11].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[12].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[13].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[14].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[15].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[16].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[17].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[18].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[19].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[20].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[21].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[22].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[23].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[24].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg
 (the first 15 of 26 listed)
Related violations: <none>

PLHOLDVIO-2#5 Warning
Non-Optimal connections which could lead to hold violations  
A LUT ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__15 is driving clock pin of 6 cells. This could lead to large hold time violations. Involved cells are:
ptop/cv32e40s_core_i/cs_registers_i/mstatus_csr_i/gen_hardened.gen_csr_hardened[11].gen_unmasked_hardened.gen_rv1.sffs_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/mstatus_csr_i/gen_hardened.gen_csr_hardened[12].gen_unmasked_hardened.gen_rv1.sffs_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/mstatus_csr_i/gen_hardened.gen_csr_hardened[17].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/mstatus_csr_i/gen_hardened.gen_csr_hardened[21].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/mstatus_csr_i/gen_hardened.gen_csr_hardened[3].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg
ptop/cv32e40s_core_i/cs_registers_i/mstatus_csr_i/gen_hardened.gen_csr_hardened[7].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg
Related violations: <none>

PLHOLDVIO-2#6 Warning
Non-Optimal connections which could lead to hold violations  
A LUT ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__16 is driving clock pin of 2 cells. This could lead to large hold time violations. Involved cells are:
ptop/cv32e40s_core_i/cs_registers_i/privlvl_user.priv_lvl_i/gen_hardened.gen_csr_hardened[0].gen_unmasked_hardened.gen_rv1.sffs_rdatareg/q_o_reg
ptop/cv32e40s_core_i/cs_registers_i/privlvl_user.priv_lvl_i/gen_hardened.gen_csr_hardened[1].gen_unmasked_hardened.gen_rv1.sffs_rdatareg/q_o_reg
Related violations: <none>

PLHOLDVIO-2#7 Warning
Non-Optimal connections which could lead to hold violations  
A LUT ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__8 is driving clock pin of 12 cells. This could lead to large hold time violations. Involved cells are:
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[0].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[10].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[1].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[2].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[31].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[3].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[4].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[5].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[6].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[7].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[8].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[9].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg
Related violations: <none>

PLHOLDVIO-2#8 Warning
Non-Optimal connections which could lead to hold violations  
A LUT ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__9 is driving clock pin of 26 cells. This could lead to large hold time violations. Involved cells are:
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[0].gen_unmasked_hardened.gen_rv1.sffs_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[10].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[11].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[12].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[13].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[14].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[15].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[16].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[17].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[18].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[19].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[20].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[21].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[22].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg,
ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[23].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg
 (the first 15 of 26 listed)
Related violations: <none>


