Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date         : Fri Jul 10 00:31:15 2026
| Host         : 685a421e500f running 64-bit unknown
| Command      : report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
| Design       : fpga_top
| Device       : xc7a100t
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |   144 |
|    Minimum number of control sets                        |   144 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |   247 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |   144 |
| >= 0 to < 4        |     7 |
| >= 4 to < 6        |    14 |
| >= 6 to < 8        |     5 |
| >= 8 to < 10       |    10 |
| >= 10 to < 12      |     5 |
| >= 12 to < 14      |     5 |
| >= 14 to < 16      |     1 |
| >= 16              |    97 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |              51 |           21 |
| No           | No                    | Yes                    |             247 |          149 |
| No           | Yes                   | No                     |             150 |           54 |
| Yes          | No                    | No                     |             165 |           60 |
| Yes          | No                    | Yes                    |            2262 |          918 |
| Yes          | Yes                   | No                     |             406 |          107 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+
|                                    Clock Signal                                    |                                              Enable Signal                                              |                       Set/Reset Signal                       | Slice Load Count | Bel Load Count | Bels / Slice |
+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+
|  ptop/u_Controller/ClkDivider/clk_o_reg_1                                          |                                                                                                         |                                                              |                1 |              1 |         1.00 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Interpreter/memory_page_number[23]_i_2_n_0                                            |                                                              |                1 |              1 |         1.00 |
|  ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_3      |                                                                                                         | ptop/u_Controller/Interpreter/rst_core                       |                1 |              1 |         1.00 |
|  clk_IBUF_BUFG                                                                     |                                                                                                         |                                                              |                1 |              1 |         1.00 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                                                        | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_1_n_0             |                1 |              1 |         1.00 |
|  ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_7      |                                                                                                         | ptop/u_Controller/Interpreter/rst_core                       |                1 |              2 |         2.00 |
|  u_Controller/ClkDivider/clk_o_pulse                                               |                                                                                                         | ptop/u_Controller/Interpreter/rst_core                       |                2 |              2 |         1.00 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[instr_valid]_2[0]                                      | ptop/u_Controller/Interpreter/rst_core                       |                4 |              4 |         1.00 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Uart/i_uart_rx/next_bit                                                               | ptop/u_Controller/Uart/i_uart_rx/bit_counter[3]_i_1_n_0      |                1 |              4 |         4.00 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/if_stage_i/prefetch_unit_i/alignment_buffer_i/FSM_sequential_ctrl_fsm_cs_reg[1][0] | ptop/u_Controller/Interpreter/rst_core                       |                2 |              4 |         2.00 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/load_store_unit_i/mpu_i/p_0_in[0]                                                  | ptop/u_Controller/Interpreter/rst_core                       |                1 |              4 |         4.00 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_2__0_n_0                                              | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_1__0_n_0   |                2 |              4 |         2.00 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Uart/tx_fifo/E[0]                                                                     |                                                              |                1 |              4 |         4.00 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/if_stage_i/if_id_pipe_o_reg[instr][bus_resp][rdata][4]_0[0]                        | ptop/u_Controller/Interpreter/rst_core                       |                4 |              4 |         1.00 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/div.div_i/state                                                         | ptop/u_Controller/Interpreter/rst_core                       |                1 |              4 |         4.00 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Interpreter/return_state                                                              | ResetBootSystem/rst_o_reg_0                                  |                2 |              5 |         2.50 |
|  clk_o_BUFG                                                                        |                                                                                                         |                                                              |                3 |              5 |         1.67 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/if_stage_i/if_id_pipe_o_reg[instr][bus_resp][rdata][14]_0[0]                       | ptop/u_Controller/Interpreter/rst_core                       |                5 |              5 |         1.00 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/id_stage_i/id_ex_pipe_o_reg[rf_we]_0[0]                                            | ptop/u_Controller/Interpreter/rst_core                       |                2 |              5 |         2.50 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/if_stage_i/if_id_pipe_o_reg[illegal_c_insn]_0[0]                                   | ptop/u_Controller/Interpreter/rst_core                       |                1 |              5 |         5.00 |
|  clk_o_BUFG                                                                        | ResetBootSystem/counter                                                                                 |                                                              |                2 |              5 |         2.50 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/div.div_i/cnt_q                                                         | ptop/u_Controller/Interpreter/rst_core                       |                2 |              6 |         3.00 |
|  ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_6      |                                                                                                         | ptop/u_Controller/Interpreter/rst_core                       |                3 |              6 |         2.00 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/load_store_unit_i/mpu_i/E[0]                                                       | ptop/u_Controller/Interpreter/rst_core                       |                4 |              6 |         1.50 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/q_o_reg_28[0]                                                           | ptop/u_Controller/Interpreter/rst_core                       |                3 |              7 |         2.33 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Uart/i_uart_tx/data_to_send[6]_i_1_n_0                                                | ResetBootSystem/rst_o_reg_0                                  |                2 |              7 |         3.50 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Uart/uart_tx_en                                                                       | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Interpreter/counter                                                                   | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Interpreter/accumulator[7]_i_1_n_0                                                    | ResetBootSystem/rst_o_reg_0                                  |                3 |              8 |         2.67 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Uart/tx_fifo/counter_write_reg[2][0]                                                  | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/if_stage_i/if_id_pipe_o_reg[instr_valid]_0                                         | ptop/u_Controller/Interpreter/rst_core                       |                4 |              8 |         2.00 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Uart/i_uart_rx/E[0]                                                                   | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/id_stage_i/id_ex_pipe_o_reg[sys_en]_0                                              | ptop/u_Controller/Interpreter/rst_core                       |                4 |              8 |         2.00 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Uart/i_uart_rx/uart_rx_data[7]_i_1_n_0                                                | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Uart/i_uart_rx/recieved_data0                                                         | ptop/u_Controller/Uart/i_uart_rx/recieved_data[7]_i_1_n_0    |                2 |              8 |         4.00 |
|  ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_2      |                                                                                                         | ptop/u_Controller/Interpreter/rst_core                       |                5 |              9 |         1.80 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                                                        | ResetBootSystem/SR[0]                                        |                3 |             10 |         3.33 |
|  ptop/u_Controller/ClkDivider/clk_o_reg_0                                          |                                                                                                         |                                                              |                4 |             10 |         2.50 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Uart/i_uart_rx/cycle_counter0                                                         | ptop/u_Controller/Uart/i_uart_rx/cycle_counter[9]_i_1_n_0    |                4 |             10 |         2.50 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Uart/rx_fifo/read_ptr0                                                                | ResetBootSystem/rst_o_reg_0                                  |                3 |             11 |         3.67 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Uart/tx_fifo/read_ptr[2]_i_1_n_0                                                      | ResetBootSystem/rst_o_reg_0                                  |                3 |             11 |         3.67 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Uart/tx_fifo/memory_reg_0_7_0_5_i_1_n_0                                               |                                                              |                2 |             12 |         6.00 |
|  ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated        |                                                                                                         | ptop/u_Controller/Interpreter/rst_core                       |                8 |             12 |         1.50 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Interpreter/address[31]_i_1_n_0                                                       |                                                              |                6 |             12 |         2.00 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Uart/rx_fifo/memory_reg_0_7_0_5_i_1__0_n_0                                            |                                                              |                2 |             12 |         6.00 |
|  cv32e40s_core_i/clk                                                               | ptop/if_id_pipe_o[instr][bus_resp][err]_i_1_n_0                                                         | ptop/u_Controller/Interpreter/rst_core                       |                4 |             13 |         3.25 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/gen_triggers.tdata1_we_int                                              | ptop/u_Controller/Interpreter/rst_core                       |                6 |             14 |         2.33 |
|  ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_1      |                                                                                                         | ptop/u_Controller/Interpreter/rst_core                       |               13 |             19 |         1.46 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Interpreter/memory_page_number[23]_i_2_n_0                                            | ptop/u_Controller/Interpreter/memory_page_number[23]_i_1_n_0 |                6 |             23 |         3.83 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Interpreter/timeout                                                                   | ResetBootSystem/rst_o_reg_0                                  |                5 |             24 |         4.80 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Interpreter/num_of_pages                                                              | ResetBootSystem/rst_o_reg_0                                  |                5 |             24 |         4.80 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Interpreter/accumulator0                                                              | ResetBootSystem/rst_o_reg_0                                  |                5 |             24 |         4.80 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Interpreter/num_of_cycles_to_pulse[23]_i_1_n_0                                        |                                                              |                8 |             24 |         3.00 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/load_store_unit_i/rdata_q0                                                         | ptop/u_Controller/Interpreter/rst_core                       |               21 |             25 |         1.19 |
|  ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_0      |                                                                                                         | ptop/u_Controller/Interpreter/rst_core                       |               19 |             26 |         1.37 |
|  ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_4      |                                                                                                         | ptop/u_Controller/Interpreter/rst_core                       |                8 |             26 |         3.25 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/if_stage_i/prefetch_unit_i/prefetcher_i/instr_ack_reg[0]                           | ptop/u_Controller/Interpreter/rst_core                       |               14 |             30 |         2.14 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/if_stage_i/prefetch_unit_i/alignment_buffer_i/is_tbljmp_ptr_q_reg_9[0]             | ptop/u_Controller/Interpreter/rst_core                       |               11 |             31 |         2.82 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/if_stage_i/if_id_pipe_o_reg[illegal_c_insn]_2[0]                                   | ptop/u_Controller/Interpreter/rst_core                       |                8 |             31 |         3.88 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/is_tbljmp_ptr_q_reg_1[0]                                                | ptop/u_Controller/Interpreter/rst_core                       |               10 |             31 |         3.10 |
|  ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_5_BUFG |                                                                                                         | ptop/u_Controller/Interpreter/rst_core                       |               22 |             31 |         1.41 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Interpreter/communication_write_data[31]_i_1_n_0                                      |                                                              |               12 |             32 |         2.67 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_27[0]                                     | ptop/u_Controller/Interpreter/rst_core                       |                7 |             32 |         4.57 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_16[0]                                     | ptop/u_Controller/Interpreter/rst_core                       |               15 |             32 |         2.13 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_12[0]                                     | ptop/u_Controller/Interpreter/rst_core                       |               12 |             32 |         2.67 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Interpreter/core_clk_enable_reg_0                                                     | ResetBootSystem/rst_o_reg_0                                  |                8 |             32 |         4.00 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Interpreter/timeout_counter                                                           | ResetBootSystem/rst_o_reg_0                                  |                8 |             32 |         4.00 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_15[0]                                     | ptop/u_Controller/Interpreter/rst_core                       |                8 |             32 |         4.00 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_21[0]                                     | ptop/u_Controller/Interpreter/rst_core                       |               11 |             32 |         2.91 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Interpreter/read_buffer                                                               | ResetBootSystem/rst_o_reg_0                                  |               18 |             32 |         1.78 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_14[0]                                     | ptop/u_Controller/Interpreter/rst_core                       |               12 |             32 |         2.67 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_20[0]                                     | ptop/u_Controller/Interpreter/rst_core                       |                9 |             32 |         3.56 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_18[0]                                     | ptop/u_Controller/Interpreter/rst_core                       |               10 |             32 |         3.20 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_13[0]                                     | ptop/u_Controller/Interpreter/rst_core                       |               11 |             32 |         2.91 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_19[0]                                     | ptop/u_Controller/Interpreter/rst_core                       |               13 |             32 |         2.46 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_31[0]                                     | ptop/u_Controller/Interpreter/rst_core                       |               15 |             32 |         2.13 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_10[0]                                     | ptop/u_Controller/Interpreter/rst_core                       |                8 |             32 |         4.00 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_11[0]                                     | ptop/u_Controller/Interpreter/rst_core                       |                8 |             32 |         4.00 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_30[0]                                     | ptop/u_Controller/Interpreter/rst_core                       |               19 |             32 |         1.68 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Interpreter/write_data[31]_i_1_n_0                                                    |                                                              |               18 |             32 |         1.78 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Interpreter/end_position[31]_i_1_n_0                                                  | ResetBootSystem/rst_o_reg_0                                  |               10 |             32 |         3.20 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_17[0]                                     | ptop/u_Controller/Interpreter/rst_core                       |               11 |             32 |         2.91 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Interpreter/communication_buffer[31]_i_1_n_0                                          | ResetBootSystem/rst_o_reg_0                                  |                8 |             32 |         4.00 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Uart/rx_fifo/E[0]                                                                     | ResetBootSystem/rst_o_reg_0                                  |                5 |             32 |         6.40 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_26[0]                                     | ptop/u_Controller/Interpreter/rst_core                       |               10 |             32 |         3.20 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_28[0]                                     | ptop/u_Controller/Interpreter/rst_core                       |               11 |             32 |         2.91 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_29[0]                                     | ptop/u_Controller/Interpreter/rst_core                       |               15 |             32 |         2.13 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/div.div_i/remainder_q                                                   | ptop/u_Controller/Interpreter/rst_core                       |                8 |             32 |         4.00 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/div.div_i/divisor_q                                                     | ptop/u_Controller/Interpreter/rst_core                       |                8 |             32 |         4.00 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/id_stage_i/id_ex_pipe_o_reg[lsu_en]_0[0]                                           | ptop/u_Controller/Interpreter/rst_core                       |               23 |             32 |         1.39 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/mcountinhibit_q_reg[0]_0[1]                                             | ptop/u_Controller/Interpreter/rst_core                       |               13 |             32 |         2.46 |
|  u_Controller/ClkDivider/clk_o_pulse                                               |                                                                                                         | ptop/instr_data[31]_i_1_n_0                                  |                9 |             32 |         3.56 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Uart/tx_fifo/FSM_sequential_state_write_reg[2][0]                                     | ResetBootSystem/rst_o_reg_0                                  |                5 |             32 |         6.40 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/div.div_i/quotient_q                                                    | ptop/u_Controller/Interpreter/rst_core                       |               10 |             32 |         3.20 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_24[0]                                     | ptop/u_Controller/Interpreter/rst_core                       |               16 |             32 |         2.00 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/mcountinhibit_q_reg[2][1]                                               | ptop/u_Controller/Interpreter/rst_core                       |               13 |             32 |         2.46 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/mcountinhibit_q_reg[2][0]                                               | ptop/u_Controller/Interpreter/rst_core                       |               13 |             32 |         2.46 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_23[0]                                     | ptop/u_Controller/Interpreter/rst_core                       |               22 |             32 |         1.45 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_22[0]                                     | ptop/u_Controller/Interpreter/rst_core                       |                9 |             32 |         3.56 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_3[0]                                      | ptop/u_Controller/Interpreter/rst_core                       |               11 |             32 |         2.91 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_2[0]                                      | ptop/u_Controller/Interpreter/rst_core                       |                9 |             32 |         3.56 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_1[0]                                      | ptop/u_Controller/Interpreter/rst_core                       |               14 |             32 |         2.29 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_5[0]                                      | ptop/u_Controller/Interpreter/rst_core                       |               13 |             32 |         2.46 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_6[0]                                      | ptop/u_Controller/Interpreter/rst_core                       |                8 |             32 |         4.00 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_7[0]                                      | ptop/u_Controller/Interpreter/rst_core                       |               15 |             32 |         2.13 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_8[0]                                      | ptop/u_Controller/Interpreter/rst_core                       |               10 |             32 |         3.20 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_9[0]                                      | ptop/u_Controller/Interpreter/rst_core                       |               10 |             32 |         3.20 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_0[0]                                      | ptop/u_Controller/Interpreter/rst_core                       |               17 |             32 |         1.88 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_25[0]                                     | ptop/u_Controller/Interpreter/rst_core                       |               10 |             32 |         3.20 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/if_stage_i/if_id_pipe_o_reg[instr][bus_resp][rdata][4]_1[0]                        | ptop/u_Controller/Interpreter/rst_core                       |                8 |             32 |         4.00 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/if_stage_i/prefetch_unit_i/alignment_buffer_i/addr_q[12]                           | ptop/u_Controller/Interpreter/rst_core                       |                9 |             32 |         3.56 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/if_stage_i/secure_ctrl_flow.multi_op_cnt_reg[0]_0[0]                               | ptop/u_Controller/Interpreter/rst_core                       |               19 |             32 |         1.68 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/tdata2_we13_out                                                         | ptop/u_Controller/Interpreter/rst_core                       |               10 |             32 |         3.20 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/if_stage_i/secure_ctrl_flow.multi_op_cnt_reg[0][0]                                 | ptop/u_Controller/Interpreter/rst_core                       |               14 |             32 |         2.29 |
|  cv32e40s_core_i/cs_registers_i/mscratch_csr_i/gen_hardened.clk_gated              |                                                                                                         | ptop/u_Controller/Interpreter/rst_core                       |               19 |             32 |         1.68 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/ex_wb_pipe_o_reg[rf_waddr][1]_4[0]                                      | ptop/u_Controller/Interpreter/rst_core                       |                9 |             32 |         3.56 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/mcountinhibit_q_reg[0]_0[0]                                             | ptop/u_Controller/Interpreter/rst_core                       |               10 |             32 |         3.20 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/controller_i/controller_fsm_i/E[0]                                                 | ptop/u_Controller/Interpreter/rst_core                       |               16 |             34 |         2.12 |
|  u_Controller/ClkDivider/clk_o_pulse                                               |                                                                                                         |                                                              |               12 |             34 |         2.83 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/id_stage_i/id_ex_pipe_o_reg[instr_valid]_2[0]                                      | ptop/u_Controller/Interpreter/rst_core                       |                9 |             35 |         3.89 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/if_stage_i/prefetch_unit_i/alignment_buffer_i/resp_q[1][bus_resp][rchk][4]_i_1_n_0 | ptop/u_Controller/Interpreter/rst_core                       |               24 |             42 |         1.75 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/if_stage_i/prefetch_unit_i/alignment_buffer_i/resp_q[2][bus_resp][rchk][4]_i_1_n_0 | ptop/u_Controller/Interpreter/rst_core                       |               19 |             42 |         2.21 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/if_stage_i/prefetch_unit_i/alignment_buffer_i/resp_q[0][bus_resp][rchk][4]_i_1_n_0 | ptop/u_Controller/Interpreter/rst_core                       |               24 |             42 |         1.75 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/id_stage_i/id_ex_pipe_o_reg[csr_en]_0[0]                                           | ptop/u_Controller/Interpreter/rst_core                       |               22 |             47 |         2.14 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/id_stage_i/p_12_out                                                                | ptop/u_Controller/Interpreter/rst_core                       |               26 |             49 |         1.88 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/if_stage_i/p_13_in                                                                 | ptop/u_Controller/Interpreter/rst_core                       |               21 |             52 |         2.48 |
|  clk_o_BUFG                                                                        | ptop/u_Controller/Interpreter/num_of_positions[23]_i_1_n_0                                              |                                                              |               12 |             55 |         4.58 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/if_stage_i/if_id_pipe_o_reg[instr_valid]_1[0]                                      | ptop/u_Controller/Interpreter/rst_core                       |               25 |             64 |         2.56 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/if_stage_i/if_id_pipe_o_reg[instr_valid]_2[0]                                      | ptop/u_Controller/Interpreter/rst_core                       |               39 |             64 |         1.64 |
|  cv32e40s_core_i/clk                                                               | ptop/cv32e40s_core_i/ex_stage_i/is_tbljmp_ptr_q_reg                                                     | ptop/u_Controller/Interpreter/rst_core                       |               38 |             74 |         1.95 |
|  cv32e40s_core_i/clk                                                               |                                                                                                         | ptop/u_Controller/Interpreter/rst_core                       |               48 |             81 |         1.69 |
|  clk_o_BUFG                                                                        |                                                                                                         | ResetBootSystem/rst_o_reg_0                                  |               45 |            118 |         2.62 |
|  clk_o_BUFG                                                                        | ptop/cv32e40s_core_i/if_stage_i/instruction_obi_i/memory_mux_selector_reg_6                             |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                        | ptop/cv32e40s_core_i/if_stage_i/instruction_obi_i/memory_mux_selector_reg                               |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                        | ptop/cv32e40s_core_i/if_stage_i/instruction_obi_i/memory_mux_selector_reg_2                             |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                        | ptop/cv32e40s_core_i/if_stage_i/instruction_obi_i/memory_mux_selector_reg_3                             |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                        | ptop/cv32e40s_core_i/if_stage_i/instruction_obi_i/memory_mux_selector_reg_0                             |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                        | ptop/cv32e40s_core_i/if_stage_i/instruction_obi_i/memory_mux_selector_reg_5                             |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                        | ptop/cv32e40s_core_i/if_stage_i/instruction_obi_i/memory_mux_selector_reg_1                             |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                        | ptop/cv32e40s_core_i/if_stage_i/instruction_obi_i/memory_mux_selector_reg_4                             |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                        | ptop/cv32e40s_core_i/id_stage_i/split_q_reg_3                                                           |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                        | ptop/cv32e40s_core_i/id_stage_i/bus_cnt_q_reg[1]                                                        |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                        | ptop/cv32e40s_core_i/id_stage_i/split_q_reg_4                                                           |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                                                                        | ptop/cv32e40s_core_i/id_stage_i/bus_cnt_q_reg[1]_0                                                      |                                                              |               32 |            128 |         4.00 |
+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+


