Started by timer [Pipeline] Start of Pipeline [Pipeline] node Still waiting to schedule task Waiting for next available executor Running on Jenkins in /var/jenkins_home/workspace/cv32e40s [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -rf test_results_1775881951.5023232.xml [Pipeline] sh + rm -rf cv32e40s [Pipeline] sh + git clone --recursive --depth=1 https://github.com/openhwgroup/cv32e40s cv32e40s Cloning into 'cv32e40s'... [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Simulation) [Pipeline] dir Running in /var/jenkins_home/workspace/cv32e40s/cv32e40s [Pipeline] { [Pipeline] echo FPGA > Simulation [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Utilities) [Pipeline] dir Running in /var/jenkins_home/workspace/cv32e40s/cv32e40s [Pipeline] { [Pipeline] sh + pwd + python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/cv32e40s/cv32e40s -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels Trying to read file: /var/jenkins_home/workspace/cv32e40s/cv32e40s/bhv/cv32e40s_sim_clock_gate.sv Trying to read file: /var/jenkins_home/workspace/cv32e40s/cv32e40s/bhv/cv32e40s_sim_clock_gate.sv Trying to read file: /var/jenkins_home/workspace/cv32e40s/cv32e40s/bhv/cv32e40s_sim_sffr.sv Trying to read file: /var/jenkins_home/workspace/cv32e40s/cv32e40s/bhv/cv32e40s_sim_sffs.sv Trying to read file: /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv Cache-related signals in cv32e40s_ex_stage.sv Cache-related signals in cv32e40s_controller_fsm.sv Cache-related signals in cv32e40s_lsu_response_filter.sv Cache-related signals in cv32e40s_div.sv Cache-related signals in cv32e40s_alignment_buffer.sv Cache-related signals in cv32e40s_clic_int_controller.sv Cache-related signals in cv32e40s_sequencer.sv Cache-related signals in cv32e40s_wb_stage.sv Cache-related signals in cv32e40s_prefetcher.sv Cache-related signals in cv32e40s_pc_check.sv Cache-related signals in cv32e40s_core.sv Cache-related signals in cv32e40s_if_stage.sv Cache-related signals in cv32e40s_controller.sv Cache-related signals in cv32e40s_prefetch_unit.sv Cache-related signals in cv32e40s_mult.sv Cache-related signals in cv32e40s_id_stage.sv Cache-related signals in cv32e40s_register_file.sv Cache-related signals in cv32e40s_load_store_unit.sv Cache-related signals in cv32e40s_obi_integrity_fifo.sv Cache-related signals in cv32e40s_cs_registers.sv Cache-related signals in cv32e40s_pkg.sv Cache-related signals in cv32e40s_prefetcher_sva.sv Cache-related signals in cv32e40s_if_stage_sva.sv Cache-related signals in cv32e40s_controller_fsm_sva.sv Cache-related signals in cv32e40s_id_stage_sva.sv Cache-related signals in cv32e40s_data_obi_interface_sva.sv Cache-related signals in cv32e40s_rvfi_sva.sv Cache-related signals in cv32e40s_load_store_unit_sva.sv Cache-related signals in cv32e40s_sequencer_sva.sv Cache-related signals in cv32e40s_mult_sva.sv Cache-related signals in cv32e40s_core_sva.sv Cache-related signals in cv32e40s_instr_obi_interface_sva.sv Cache-related signals in cv32e40s_ex_stage_sva.sv Cache-related signals in cv32e40s_wb_stage_sva.sv Cache-related signals in cv32e40s_alignment_buffer_sva.sv Cache-related signals in cv32e40s_mpu_sva.sv Cache-related signals in cv32e40s_rvfi_instr_obi.sv Cache-related signals in cv32e40s_rvfi_data_obi.sv Cache-related signals in cv32e40s_rvfi.sv Results saved to /jenkins/processor_ci_utils/labels/cv32e40s.json [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Build Pipeline) [Pipeline] parallel [Pipeline] { (Branch: digilent_arty_a7_100t) [Pipeline] stage [Pipeline] { (digilent_arty_a7_100t) [Pipeline] lock Trying to acquire lock on [Resource: digilent_arty_a7_100t] The resource [digilent_arty_a7_100t] is locked by build pulpino #420 #420 since Apr 12, 2026, 4:25 AM. [Resource: digilent_arty_a7_100t] is not free, waiting for execution ... [Required resources: [digilent_arty_a7_100t]] added into queue at position 0 Lock acquired on [Resource: digilent_arty_a7_100t] [Pipeline] { [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] dir Running in /var/jenkins_home/workspace/cv32e40s/cv32e40s [Pipeline] { [Pipeline] echo Starting synthesis for FPGA digilent_arty_a7_100t. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p cv32e40s -b digilent_arty_a7_100t [LOCK] Criado: run.lock File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'. Final configuration file generated at /var/jenkins_home/workspace/cv32e40s/cv32e40s/build_digilent_arty_a7_100t.tcl [LOCK] Removido: run.lock Makefile executed successfully. Makefile output: Building the Design... /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source /var/jenkins_home/workspace/cv32e40s/cv32e40s/build_digilent_arty_a7_100t.tcl ****** Vivado v2023.2 (64-bit) **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source /var/jenkins_home/workspace/cv32e40s/cv32e40s/build_digilent_arty_a7_100t.tcl # read_verilog -sv /eda/processor_ci/rtl/cv32e40s.sv read_verilog: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1319.996 ; gain = 0.023 ; free physical = 4452 ; free virtual = 27136 # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/bhv/cv32e40s_sim_clock_gate.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/bhv/cv32e40s_sim_sffr.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/bhv/cv32e40s_sim_sffs.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_alert.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_alignment_buffer.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_alu.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_alu_b_cpop.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_b_decoder.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_clic_int_controller.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_compressed_decoder.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_controller.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_controller_bypass.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_controller_fsm.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_core.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_cs_registers.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_data_obi_interface.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_debug_triggers.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_decoder.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_div.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_dummy_instr.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_ex_stage.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_ff_one.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_i_decoder.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_id_stage.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_if_c_obi.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_if_stage.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_instr_obi_interface.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_int_controller.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_lfsr.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_load_store_unit.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_lsu_response_filter.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_m_decoder.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_mpu.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_mult.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_obi_integrity_fifo.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_pc_check.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_pc_target.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_pma.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_pmp.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_popcnt.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_prefetch_unit.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_prefetcher.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_rchk_check.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_register_file.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_register_file_ecc.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_register_file_wrapper.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_sequencer.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_sleep_unit.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_wb_stage.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_wpt.sv # read_verilog -sv /var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_write_buffer.sv # read_verilog -sv /eda/processor-ci-controller/modules/uart.sv # read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v # read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v # read_verilog -sv /eda/processor_ci/internal/ahblite_to_wishbone.sv # read_verilog -sv /eda/processor_ci/internal/axi4_to_wishbone.sv # read_verilog -sv /eda/processor_ci/internal/axi4lite_to_wishbone.sv # read_verilog -sv /eda/processor-ci-controller/rtl/fifo.sv # read_verilog -sv /eda/processor-ci-controller/rtl/reset.sv # read_verilog -sv /eda/processor-ci-controller/rtl/clk_divider.sv # read_verilog -sv /eda/processor-ci-controller/rtl/memory.sv # read_verilog -sv /eda/processor-ci-controller/rtl/interpreter.sv # read_verilog -sv /eda/processor-ci-controller/rtl/controller.sv # read_verilog -sv /eda/processor-ci-controller/rtl/timer.sv # read_verilog -sv /eda/processor_ci/internal/fpga_top.sv # set_param general.maxThreads 16 # read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc" # set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] # synth_design -top "fpga_top" -part "xc7a100tcsg324-1" Command: synth_design -top fpga_top -part xc7a100tcsg324-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Device 21-403] Loading part xc7a100tcsg324-1 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 1613514 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2032.781 ; gain = 402.746 ; free physical = 3491 ; free virtual = 26175 --------------------------------------------------------------------------------- WARNING: [Synth 8-11067] parameter 'ALU_OP_WIDTH' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:63] WARNING: [Synth 8-11067] parameter 'MUL_OP_WIDTH' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:148] WARNING: [Synth 8-11067] parameter 'DIV_OP_WIDTH' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:156] WARNING: [Synth 8-11067] parameter 'HAVERESET_INDEX' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:175] WARNING: [Synth 8-11067] parameter 'RUNNING_INDEX' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:176] WARNING: [Synth 8-11067] parameter 'HALTED_INDEX' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:177] WARNING: [Synth 8-11067] parameter 'CSR_JVT_MASK' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:467] WARNING: [Synth 8-11067] parameter 'CSR_DCSR_MASK' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:468] WARNING: [Synth 8-11067] parameter 'CSR_MEPC_MASK' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:469] WARNING: [Synth 8-11067] parameter 'CSR_DPC_MASK' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:470] WARNING: [Synth 8-11067] parameter 'CSR_MSTATUS_MASK' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:472] WARNING: [Synth 8-11067] parameter 'CSR_MINTSTATUS_MASK' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:473] WARNING: [Synth 8-11067] parameter 'CSR_MSCRATCH_MASK' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:474] WARNING: [Synth 8-11067] parameter 'CSR_CPUCTRL_MASK' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:475] WARNING: [Synth 8-11067] parameter 'CSR_PMPNCFG_MASK' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:476] WARNING: [Synth 8-11067] parameter 'CSR_PMPADDR_MASK' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:477] WARNING: [Synth 8-11067] parameter 'CSR_MSECCFG_MASK' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:478] WARNING: [Synth 8-11067] parameter 'CSR_PRV_LVL_MASK' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:479] WARNING: [Synth 8-11067] parameter 'CSR_MSTATEEN0_MASK' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:480] WARNING: [Synth 8-11067] parameter 'CSR_DSCRATCH0_MASK' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:481] WARNING: [Synth 8-11067] parameter 'CSR_DSCRATCH1_MASK' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:482] WARNING: [Synth 8-11067] parameter 'CSR_MINTTHRESH_MASK' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:483] WARNING: [Synth 8-11067] parameter 'CSR_CLIC_MCAUSE_MASK' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:484] WARNING: [Synth 8-11067] parameter 'CSR_BASIC_MCAUSE_MASK' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:485] WARNING: [Synth 8-11067] parameter 'CSR_CLIC_MTVEC_MASK' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:486] WARNING: [Synth 8-11067] parameter 'CSR_BASIC_MTVEC_MASK' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:487] WARNING: [Synth 8-11067] parameter 'CSR_OP_WIDTH' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:492] WARNING: [Synth 8-11067] parameter 'CSR_MSIX_BIT' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:503] WARNING: [Synth 8-11067] parameter 'CSR_MTIX_BIT' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:504] WARNING: [Synth 8-11067] parameter 'CSR_MEIX_BIT' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:505] WARNING: [Synth 8-11067] parameter 'CSR_MFIX_BIT_LOW' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:506] WARNING: [Synth 8-11067] parameter 'CSR_MFIX_BIT_HIGH' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:507] WARNING: [Synth 8-11067] parameter 'CPUCTRL_RESET_VAL' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:521] WARNING: [Synth 8-11067] parameter 'MVENDORID_OFFSET' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:552] WARNING: [Synth 8-11067] parameter 'MVENDORID_BANK' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:553] WARNING: [Synth 8-11067] parameter 'MARCHID' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:556] WARNING: [Synth 8-11067] parameter 'MIMPID_MAJOR' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:559] WARNING: [Synth 8-11067] parameter 'MIMPID_MINOR' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:560] WARNING: [Synth 8-11067] parameter 'MTVEC_MODE_BASIC' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:562] WARNING: [Synth 8-11067] parameter 'MTVEC_MODE_CLIC' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:563] WARNING: [Synth 8-11067] parameter 'NUM_HPM_EVENTS' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:564] WARNING: [Synth 8-11067] parameter 'MSTATUS_MIE_BIT' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:566] WARNING: [Synth 8-11067] parameter 'MSTATUS_MPIE_BIT' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:567] WARNING: [Synth 8-11067] parameter 'MSTATUS_MPP_BIT_LOW' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:568] WARNING: [Synth 8-11067] parameter 'MSTATUS_MPP_BIT_HIGH' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:569] WARNING: [Synth 8-11067] parameter 'MSTATUS_MPRV_BIT' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:570] WARNING: [Synth 8-11067] parameter 'MSTATUS_TW_BIT' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:571] WARNING: [Synth 8-11067] parameter 'MCAUSE_MPIE_BIT' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:573] WARNING: [Synth 8-11067] parameter 'MCAUSE_MPP_BIT_LOW' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:574] WARNING: [Synth 8-11067] parameter 'MCAUSE_MPP_BIT_HIGH' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:575] WARNING: [Synth 8-11067] parameter 'MTVEC_MODE_BIT_HIGH' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:577] WARNING: [Synth 8-11067] parameter 'MTVEC_MODE_BIT_LOW' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:578] WARNING: [Synth 8-11067] parameter 'DCSR_EBREAKU_BIT' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:580] WARNING: [Synth 8-11067] parameter 'DCSR_PRV_BIT_HIGH' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:581] WARNING: [Synth 8-11067] parameter 'DCSR_PRV_BIT_LOW' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:582] WARNING: [Synth 8-11067] parameter 'MXL' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:586] WARNING: [Synth 8-11067] parameter 'JVT_ADDR_WIDTH' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:595] WARNING: [Synth 8-11067] parameter 'DBG_CAUSE_NONE' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:629] WARNING: [Synth 8-11067] parameter 'DBG_CAUSE_EBREAK' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:630] WARNING: [Synth 8-11067] parameter 'DBG_CAUSE_TRIGGER' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:631] WARNING: [Synth 8-11067] parameter 'DBG_CAUSE_HALTREQ' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:632] WARNING: [Synth 8-11067] parameter 'DBG_CAUSE_STEP' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:633] WARNING: [Synth 8-11067] parameter 'DBG_CAUSE_RSTHALTREQ' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:634] WARNING: [Synth 8-11067] parameter 'DCSR_RESET_VAL' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:702] WARNING: [Synth 8-11067] parameter 'MTVEC_BASIC_RESET_VAL' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:710] WARNING: [Synth 8-11067] parameter 'MTVEC_CLIC_RESET_VAL' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:716] WARNING: [Synth 8-11067] parameter 'MTVT_RESET_VAL' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:722] WARNING: [Synth 8-11067] parameter 'MINTSTATUS_RESET_VAL' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:726] WARNING: [Synth 8-11067] parameter 'MSTATUS_RESET_VAL' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:732] WARNING: [Synth 8-11067] parameter 'MCAUSE_CLIC_RESET_VAL' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:744] WARNING: [Synth 8-11067] parameter 'MCAUSE_BASIC_RESET_VAL' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:748] WARNING: [Synth 8-11067] parameter 'JVT_RESET_VAL' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:751] WARNING: [Synth 8-11067] parameter 'MSCRATCH_RESET_VAL' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:752] WARNING: [Synth 8-11067] parameter 'MEPC_RESET_VAL' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:753] WARNING: [Synth 8-11067] parameter 'DPC_RESET_VAL' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:754] WARNING: [Synth 8-11067] parameter 'DSCRATCH0_RESET_VAL' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:755] WARNING: [Synth 8-11067] parameter 'DSCRATCH1_RESET_VAL' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:756] WARNING: [Synth 8-11067] parameter 'MINTTHRESH_RESET_VAL' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:757] WARNING: [Synth 8-11067] parameter 'MIE_BASIC_RESET_VAL' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:758] WARNING: [Synth 8-11067] parameter 'MSTATEEN0_RESET_VAL' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:759] WARNING: [Synth 8-11067] parameter 'TDATA1_RST_VAL' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:761] WARNING: [Synth 8-11067] parameter 'MCONTROL_6_UNCERTAIN' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:781] WARNING: [Synth 8-11067] parameter 'MCONTROL_6_HIT1' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:782] WARNING: [Synth 8-11067] parameter 'MCONTROL_6_HIT0' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:783] WARNING: [Synth 8-11067] parameter 'MCONTROL2_6_MATCH_HIGH' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:784] WARNING: [Synth 8-11067] parameter 'MCONTROL2_6_MATCH_LOW' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:785] WARNING: [Synth 8-11067] parameter 'MCONTROL2_6_M' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:786] WARNING: [Synth 8-11067] parameter 'MCONTROL_6_UNCERTAINEN' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:787] WARNING: [Synth 8-11067] parameter 'MCONTROL2_6_U' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:788] WARNING: [Synth 8-11067] parameter 'MCONTROL2_6_EXECUTE' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:789] WARNING: [Synth 8-11067] parameter 'MCONTROL2_6_STORE' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:790] WARNING: [Synth 8-11067] parameter 'MCONTROL2_6_LOAD' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:791] WARNING: [Synth 8-11067] parameter 'ETRIGGER_M' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:794] WARNING: [Synth 8-11067] parameter 'ETRIGGER_U' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:795] WARNING: [Synth 8-11067] parameter 'TDATA1_TTYPE_HIGH' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:798] WARNING: [Synth 8-11067] parameter 'TDATA1_TTYPE_LOW' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:799] WARNING: [Synth 8-11067] parameter 'SECURE' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:822] WARNING: [Synth 8-11067] parameter 'USER' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:825] WARNING: [Synth 8-11067] parameter 'PRIV_LVL_LOWEST' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:828] WARNING: [Synth 8-11067] parameter 'REGFILE_NUM_WRITE_PORTS' declared inside package 'cv32e40s_pkg' shall be treated as localparam [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:831] INFO: [Common 17-14] Message 'Synth 8-11067' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-11241] undeclared symbol 'sys_wfe_unqual_id', assumed default net type 'wire' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_controller_bypass.sv:133] INFO: [Synth 8-11241] undeclared symbol 'mscratchcsw_q', assumed default net type 'wire' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_cs_registers.sv:2092] INFO: [Synth 8-11241] undeclared symbol 'mscratchcswl_q', assumed default net type 'wire' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_cs_registers.sv:2094] INFO: [Synth 8-11241] undeclared symbol 'tdata1_n', assumed default net type 'wire' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_debug_triggers.sv:530] INFO: [Synth 8-11241] undeclared symbol 'clic_ptr_valid', assumed default net type 'wire' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_ex_stage.sv:476] INFO: [Synth 8-11241] undeclared symbol 'mret_ptr_valid', assumed default net type 'wire' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_ex_stage.sv:477] WARNING: [Synth 8-6901] identifier 'wstrb' is used before its declaration [/eda/processor_ci/internal/ahblite_to_wishbone.sv:79] WARNING: [Synth 8-6901] identifier 'timer_data_out' is used before its declaration [/eda/processor-ci-controller/rtl/controller.sv:149] WARNING: [Synth 8-9535] ignoring re-definition of command line macro 'SYNTHESIS' [/eda/processor_ci/internal/fpga_top.sv:7] WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:16] WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:16] INFO: [Synth 8-6157] synthesizing module 'fpga_top' [/eda/processor_ci/internal/fpga_top.sv:8] INFO: [Synth 8-6157] synthesizing module 'processorci_top' [/eda/processor_ci/rtl/cv32e40s.sv:9] INFO: [Synth 8-6157] synthesizing module 'Controller' [/eda/processor-ci-controller/rtl/controller.sv:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer Parameter BUFFER_SIZE bound to: 8 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer Parameter BUS_WIDTH bound to: 32 - type: integer Parameter WORD_SIZE_BY bound to: 4 - type: integer Parameter ID bound to: 1095914585 - type: integer Parameter RESET_CLK_CYCLES bound to: 20 - type: integer Parameter MEMORY_FILE bound to: (null) - type: string Parameter MEMORY_SIZE bound to: 8192 - type: integer INFO: [Synth 8-6157] synthesizing module 'ClkDivider' [/eda/processor-ci-controller/rtl/clk_divider.sv:1] Parameter COUNTER_BITS bound to: 32 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ClkDivider' (0#1) [/eda/processor-ci-controller/rtl/clk_divider.sv:1] INFO: [Synth 8-6157] synthesizing module 'Interpreter' [/eda/processor-ci-controller/rtl/interpreter.sv:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer Parameter BUS_WIDTH bound to: 32 - type: integer Parameter ID bound to: 1095914585 - type: integer Parameter RESET_CLK_CYCLES bound to: 20 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Interpreter' (0#1) [/eda/processor-ci-controller/rtl/interpreter.sv:1] INFO: [Synth 8-6157] synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.sv:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer Parameter BUFFER_SIZE bound to: 8 - type: integer Parameter WORD_SIZE_BY bound to: 4 - type: integer INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:66] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:125] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:199] INFO: [Synth 8-226] default block is never used [/eda/processor-ci-controller/modules/uart.sv:199] INFO: [Synth 8-6157] synthesizing module 'FIFO' [/eda/processor-ci-controller/rtl/fifo.sv:1] Parameter DEPTH bound to: 8 - type: integer Parameter WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/eda/processor-ci-controller/rtl/fifo.sv:1] INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9] INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10] INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/eda/processor-ci-controller/modules/uart.sv:1] INFO: [Synth 8-6157] synthesizing module 'Memory' [/eda/processor-ci-controller/rtl/memory.sv:1] Parameter MEMORY_FILE bound to: (null) - type: string Parameter MEMORY_SIZE bound to: 8192 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/eda/processor-ci-controller/rtl/memory.sv:1] INFO: [Synth 8-6157] synthesizing module 'Timer' [/eda/processor-ci-controller/rtl/timer.sv:1] INFO: [Synth 8-6155] done synthesizing module 'Timer' (0#1) [/eda/processor-ci-controller/rtl/timer.sv:1] INFO: [Synth 8-6157] synthesizing module 'Memory__parameterized0' [/eda/processor-ci-controller/rtl/memory.sv:1] Parameter MEMORY_SIZE bound to: 4096 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Memory__parameterized0' (0#1) [/eda/processor-ci-controller/rtl/memory.sv:1] INFO: [Synth 8-6155] done synthesizing module 'Controller' (0#1) [/eda/processor-ci-controller/rtl/controller.sv:1] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_core' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_core.sv:32] Parameter LIB bound to: 0 - type: integer Parameter DEBUG bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'cv32e40s_int_controller' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_int_controller.sv:24] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_int_controller' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_int_controller.sv:24] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_if_c_obi' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_if_c_obi.sv:27] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_if_c_obi' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_if_c_obi.sv:27] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_if_c_obi' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_if_c_obi.sv:27] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_if_c_obi' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_if_c_obi.sv:27] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_sleep_unit' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_sleep_unit.sv:43] Parameter LIB bound to: 0 - type: integer INFO: [Synth 8-6157] synthesizing module 'cv32e40s_clock_gate' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/bhv/cv32e40s_sim_clock_gate.sv:15] Parameter LIB bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_clock_gate' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/bhv/cv32e40s_sim_clock_gate.sv:15] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_sleep_unit' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_sleep_unit.sv:43] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_alert' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_alert.sv:33] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_alert' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_alert.sv:33] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_if_stage' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_if_stage.sv:29] Parameter RV32 bound to: 1'b0 Parameter B_EXT bound to: 2'b00 Parameter PMA_NUM_REGIONS bound to: 32'sb00000000000000000000000000000000 Parameter PMA_CFG bound to: 136'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter PMP_GRANULARITY bound to: 32'b00000000000000000000000000000000 Parameter PMP_NUM_REGIONS bound to: 32'sb00000000000000000000000000000000 Parameter DUMMY_INSTRUCTIONS bound to: 1'b1 Parameter MTVT_ADDR_WIDTH bound to: 32'b00000000000000000000000000011001 Parameter CLIC bound to: 1'b0 Parameter CLIC_ID_WIDTH bound to: 32'b00000000000000000000000000000101 Parameter ZC_EXT bound to: 1'b1 Parameter M_EXT bound to: 2'b01 Parameter DEBUG bound to: 1'b0 Parameter DM_REGION_START bound to: -268435456 - type: integer Parameter DM_REGION_END bound to: -268419073 - type: integer INFO: [Synth 8-6157] synthesizing module 'cv32e40s_sequencer' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_sequencer.sv:34] Parameter RV32 bound to: 1'b0 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_sequencer.sv:165] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/include/cv32e40s_pkg.sv:1823] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_sequencer.sv:279] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_sequencer' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_sequencer.sv:34] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_dummy_instr' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_dummy_instr.sv:33] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_dummy_instr.sv:128] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_dummy_instr' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_dummy_instr.sv:33] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_if_stage.sv:198] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_prefetch_unit' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_prefetch_unit.sv:29] Parameter CLIC bound to: 1'b0 Parameter ALBUF_DEPTH bound to: 32'b00000000000000000000000000000011 Parameter ALBUF_CNT_WIDTH bound to: 32'b00000000000000000000000000000010 Parameter MAX_OUTSTANDING bound to: 32'b00000000000000000000000000000010 INFO: [Synth 8-6157] synthesizing module 'cv32e40s_prefetcher' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_prefetcher.sv:40] Parameter CLIC bound to: 1'b0 INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_prefetcher.sv:91] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_prefetcher' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_prefetcher.sv:40] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_alignment_buffer' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_alignment_buffer.sv:24] Parameter ALBUF_DEPTH bound to: 32'b00000000000000000000000000000011 Parameter ALBUF_CNT_WIDTH bound to: 32'b00000000000000000000000000000010 Parameter MAX_OUTSTANDING bound to: 32'b00000000000000000000000000000010 INFO: [Synth 8-6157] synthesizing module 'cv32e40s_rchk_check' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_rchk_check.sv:35] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_rchk_check' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_rchk_check.sv:35] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_alignment_buffer.sv:470] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_alignment_buffer' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_alignment_buffer.sv:24] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_prefetch_unit' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_prefetch_unit.sv:29] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_mpu' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_mpu.sv:26] Parameter IF_STAGE bound to: 1'b1 Parameter PMP_GRANULARITY bound to: 32'b00000000000000000000000000000000 Parameter PMP_NUM_REGIONS bound to: 32'sb00000000000000000000000000000000 Parameter PMA_NUM_REGIONS bound to: 32'sb00000000000000000000000000000000 Parameter PMA_CFG bound to: 136'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DEBUG bound to: 1'b0 Parameter DM_REGION_START bound to: -268435456 - type: integer Parameter DM_REGION_END bound to: -268419073 - type: integer INFO: [Synth 8-6157] synthesizing module 'cv32e40s_pmp' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_pmp.sv:31] Parameter PMP_GRANULARITY bound to: 32'b00000000000000000000000000000000 Parameter PMP_NUM_REGIONS bound to: 32'sb00000000000000000000000000000000 INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_pmp' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_pmp.sv:31] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_pma' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_pma.sv:26] Parameter PMA_NUM_REGIONS bound to: 32'sb00000000000000000000000000000000 Parameter PMA_CFG bound to: 136'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_pma' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_pma.sv:26] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_mpu' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_mpu.sv:26] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_instr_obi_interface' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_instr_obi_interface.sv:38] Parameter MAX_OUTSTANDING bound to: 32'b00000000000000000000000000000010 INFO: [Synth 8-6157] synthesizing module 'cv32e40s_obi_integrity_fifo' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_obi_integrity_fifo.sv:33] Parameter MAX_OUTSTANDING bound to: 32'b00000000000000000000000000000010 INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_obi_integrity_fifo.sv:101] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_obi_integrity_fifo' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_obi_integrity_fifo.sv:33] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_instr_obi_interface.sv:119] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_instr_obi_interface' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_instr_obi_interface.sv:38] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_pc_check' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_pc_check.sv:33] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_pc_check' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_pc_check.sv:33] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_compressed_decoder' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_compressed_decoder.sv:27] Parameter ZC_EXT bound to: 1'b1 Parameter B_EXT bound to: 2'b00 Parameter M_EXT bound to: 2'b01 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_compressed_decoder.sv:66] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_compressed_decoder.sv:69] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_compressed_decoder.sv:69] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_compressed_decoder.sv:91] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_compressed_decoder.sv:142] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_compressed_decoder.sv:142] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_compressed_decoder.sv:184] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_compressed_decoder.sv:184] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_compressed_decoder.sv:209] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_compressed_decoder.sv:209] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_compressed_decoder.sv:242] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_compressed_decoder.sv:313] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_compressed_decoder.sv:313] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_compressed_decoder' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_compressed_decoder.sv:27] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_if_stage' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_if_stage.sv:29] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_id_stage' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_id_stage.sv:33] Parameter RV32 bound to: 1'b0 Parameter B_EXT bound to: 2'b00 Parameter M_EXT bound to: 2'b01 Parameter REGFILE_NUM_READ_PORTS bound to: 32'b00000000000000000000000000000010 Parameter CLIC bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'cv32e40s_pc_target' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_pc_target.sv:26] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_pc_target.sv:50] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_pc_target.sv:50] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_pc_target' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_pc_target.sv:26] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_id_stage.sv:303] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_id_stage.sv:303] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_id_stage.sv:312] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_id_stage.sv:322] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_id_stage.sv:340] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_id_stage.sv:340] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_id_stage.sv:360] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_decoder' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_decoder.sv:28] Parameter RV32 bound to: 1'b0 Parameter REGFILE_NUM_READ_PORTS bound to: 32'b00000000000000000000000000000010 Parameter B_EXT bound to: 2'b00 Parameter M_EXT bound to: 2'b01 Parameter CLIC bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'cv32e40s_m_decoder' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_m_decoder.sv:29] Parameter M_EXT bound to: 2'b01 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_m_decoder.sv:46] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_m_decoder.sv:61] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_m_decoder' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_m_decoder.sv:29] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_i_decoder' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_i_decoder.sv:30] Parameter CLIC bound to: 1'b0 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_i_decoder.sv:54] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_i_decoder.sv:108] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_i_decoder.sv:207] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_i_decoder.sv:207] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_i_decoder.sv:249] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_i_decoder.sv:279] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_i_decoder.sv:301] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_i_decoder.sv:392] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_i_decoder' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_i_decoder.sv:30] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_decoder.sv:221] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_decoder' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_decoder.sv:28] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_id_stage' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_id_stage.sv:33] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_ex_stage' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_ex_stage.sv:33] Parameter B_EXT bound to: 2'b00 Parameter M_EXT bound to: 2'b01 INFO: [Synth 8-6157] synthesizing module 'cv32e40s_div' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_div.sv:28] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_div.sv:120] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_div.sv:231] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_div' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_div.sv:28] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_mult' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_mult.sv:27] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_mult.sv:123] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_mult' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_mult.sv:27] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_ex_stage.sv:152] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_alu' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_alu.sv:50] Parameter B_EXT bound to: 2'b00 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_alu.sv:153] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_alu.sv:236] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_ff_one' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_ff_one.sv:25] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_ff_one' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_ff_one.sv:25] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_alu_b_cpop' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_alu_b_cpop.sv:30] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_alu_b_cpop' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_alu_b_cpop.sv:30] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_alu.sv:345] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_alu' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_alu.sv:50] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_ex_stage' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_ex_stage.sv:33] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_load_store_unit' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_load_store_unit.sv:28] Parameter PMP_GRANULARITY bound to: 32'b00000000000000000000000000000000 Parameter PMP_NUM_REGIONS bound to: 32'sb00000000000000000000000000000000 Parameter PMA_NUM_REGIONS bound to: 32'sb00000000000000000000000000000000 Parameter PMA_CFG bound to: 136'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DBG_NUM_TRIGGERS bound to: 32'sb00000000000000000000000000000001 Parameter DEBUG bound to: 1'b0 Parameter DM_REGION_START bound to: -268435456 - type: integer Parameter DM_REGION_END bound to: -268419073 - type: integer INFO: [Synth 8-6157] synthesizing module 'cv32e40s_wpt' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_wpt.sv:31] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_wpt' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_wpt.sv:31] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_load_store_unit.sv:215] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_load_store_unit.sv:227] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_load_store_unit.sv:244] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_load_store_unit.sv:254] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_load_store_unit.sv:271] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_load_store_unit.sv:521] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_mpu__parameterized0' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_mpu.sv:26] Parameter IF_STAGE bound to: 1'b0 Parameter PMP_GRANULARITY bound to: 32'b00000000000000000000000000000000 Parameter PMP_NUM_REGIONS bound to: 32'sb00000000000000000000000000000000 Parameter PMA_NUM_REGIONS bound to: 32'sb00000000000000000000000000000000 Parameter PMA_CFG bound to: 136'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DEBUG bound to: 1'b0 Parameter DM_REGION_START bound to: -268435456 - type: integer Parameter DM_REGION_END bound to: -268419073 - type: integer INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_mpu__parameterized0' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_mpu.sv:26] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_lsu_response_filter' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_lsu_response_filter.sv:33] Parameter DEPTH bound to: 2 - type: integer Parameter OUTSTND_CNT_WIDTH bound to: 2 - type: integer INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_lsu_response_filter' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_lsu_response_filter.sv:33] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_write_buffer' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_write_buffer.sv:32] Parameter PMA_NUM_REGIONS bound to: 32'sb00000000000000000000000000000000 Parameter PMA_CFG bound to: 136'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_write_buffer.sv:76] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_write_buffer' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_write_buffer.sv:32] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_data_obi_interface' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_data_obi_interface.sv:38] Parameter MAX_OUTSTANDING bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'cv32e40s_obi_integrity_fifo__parameterized0' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_obi_integrity_fifo.sv:33] Parameter MAX_OUTSTANDING bound to: 2 - type: integer INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_obi_integrity_fifo.sv:101] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_rchk_check__parameterized0' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_rchk_check.sv:35] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_rchk_check__parameterized0' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_rchk_check.sv:35] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_obi_integrity_fifo__parameterized0' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_obi_integrity_fifo.sv:33] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_data_obi_interface' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_data_obi_interface.sv:38] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_load_store_unit' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_load_store_unit.sv:28] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_wb_stage' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_wb_stage.sv:37] Parameter DEBUG bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_wb_stage' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_wb_stage.sv:37] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_cs_registers' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_cs_registers.sv:34] Parameter LIB bound to: 0 - type: integer Parameter RV32 bound to: 1'b0 Parameter M_EXT bound to: 2'b01 Parameter ZC_EXT bound to: 1'b1 Parameter CLIC bound to: 1'b0 Parameter CLIC_ID_WIDTH bound to: 32'b00000000000000000000000000000101 Parameter NUM_MHPMCOUNTERS bound to: 32'b00000000000000000000000000000000 Parameter PMP_NUM_REGIONS bound to: 32'sb00000000000000000000000000000000 Parameter PMP_GRANULARITY bound to: 32'b00000000000000000000000000000000 Parameter PMP_PMPNCFG_RV bound to: 16'b0000000000000000 Parameter PMP_PMPADDR_RV bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter PMP_MSECCFG_RV[zero0] bound to: 29'b00000000000000000000000000000 Parameter PMP_MSECCFG_RV[rlb] bound to: 1'b0 Parameter PMP_MSECCFG_RV[mmwp] bound to: 1'b0 Parameter PMP_MSECCFG_RV[mml] bound to: 1'b0 Parameter LFSR0_CFG[coeffs] bound to: 32'b00000000000000000000000000000000 Parameter LFSR0_CFG[default_seed] bound to: 32'b00000000000000000000000000000000 Parameter LFSR1_CFG[coeffs] bound to: 32'b00000000000000000000000000000000 Parameter LFSR1_CFG[default_seed] bound to: 32'b00000000000000000000000000000000 Parameter LFSR2_CFG[coeffs] bound to: 32'b00000000000000000000000000000000 Parameter LFSR2_CFG[default_seed] bound to: 32'b00000000000000000000000000000000 Parameter DEBUG bound to: 1'b0 Parameter DBG_NUM_TRIGGERS bound to: 32'sb00000000000000000000000000000001 Parameter MTVT_ADDR_WIDTH bound to: 32'b00000000000000000000000000011001 INFO: [Synth 8-6157] synthesizing module 'cv32e40s_csr' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] Parameter LIB bound to: 0 - type: integer Parameter WIDTH bound to: 32'b00000000000000000000000000100000 Parameter SHADOWCOPY bound to: 1'b1 Parameter RESETVALUE bound to: 32'b00000000000000000000000000000000 Parameter MASK bound to: -2147481601 - type: integer INFO: [Synth 8-6157] synthesizing module 'cv32e40s_sffr' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/bhv/cv32e40s_sim_sffr.sv:32] Parameter LIB bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_sffr' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/bhv/cv32e40s_sim_sffr.sv:32] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_sffs' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/bhv/cv32e40s_sim_sffs.sv:32] Parameter LIB bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_sffs' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/bhv/cv32e40s_sim_sffs.sv:32] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_csr' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_csr__parameterized0' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] Parameter LIB bound to: 0 - type: integer Parameter WIDTH bound to: 32'b00000000000000000000000000100000 Parameter SHADOWCOPY bound to: 1'b1 Parameter RESETVALUE bound to: 32'b00000000000000000000000000000001 Parameter MASK bound to: -127 - type: integer INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_csr__parameterized0' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_csr__parameterized1' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] Parameter LIB bound to: 0 - type: integer Parameter WIDTH bound to: 32'b00000000000000000000000000100000 Parameter SHADOWCOPY bound to: 1'b1 Parameter RESETVALUE bound to: 0 - type: integer Parameter MASK bound to: -63352 - type: integer INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_csr__parameterized1' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_csr__parameterized2' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] Parameter LIB bound to: 0 - type: integer Parameter WIDTH bound to: 32'b00000000000000000000000000100000 Parameter SHADOWCOPY bound to: 1'b1 Parameter RESETVALUE bound to: 32'b00000000000000000000000000011001 Parameter MASK bound to: 983071 - type: integer INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_csr__parameterized2' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_lfsr' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_lfsr.sv:32] Parameter LFSR_CFG[coeffs] bound to: 32'b00000000000000000000000000000000 Parameter LFSR_CFG[default_seed] bound to: 32'b00000000000000000000000000000000 INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_lfsr' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_lfsr.sv:32] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_csr__parameterized3' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] Parameter LIB bound to: 0 - type: integer Parameter WIDTH bound to: 32'b00000000000000000000000000000010 Parameter SHADOWCOPY bound to: 1'b1 Parameter RESETVALUE bound to: 2'b11 Parameter MASK bound to: 2'b11 INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_csr__parameterized3' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_cs_registers.sv:1579] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_cs_registers.sv:1719] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_csr__parameterized4' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] Parameter LIB bound to: 0 - type: integer Parameter WIDTH bound to: 32'b00000000000000000000000000100000 Parameter SHADOWCOPY bound to: 1'b1 Parameter RESETVALUE bound to: 0 - type: integer Parameter MASK bound to: 4 - type: integer INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_csr__parameterized4' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_csr__parameterized5' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] Parameter LIB bound to: 0 - type: integer Parameter WIDTH bound to: 32'b00000000000000000000000000100000 Parameter SHADOWCOPY bound to: 1'b1 Parameter RESETVALUE bound to: 0 - type: integer Parameter MASK bound to: -64 - type: integer INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_csr__parameterized5' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_csr__parameterized6' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] Parameter LIB bound to: 0 - type: integer Parameter WIDTH bound to: 32'b00000000000000000000000000100000 Parameter SHADOWCOPY bound to: 1'b1 Parameter RESETVALUE bound to: 0 - type: integer Parameter MASK bound to: -2 - type: integer INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_csr__parameterized6' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_csr__parameterized7' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] Parameter LIB bound to: 0 - type: integer Parameter WIDTH bound to: 32'b00000000000000000000000000100000 Parameter SHADOWCOPY bound to: 1'b1 Parameter RESETVALUE bound to: 0 - type: integer Parameter MASK bound to: -1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_csr__parameterized7' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_csr__parameterized8' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] Parameter LIB bound to: 0 - type: integer Parameter WIDTH bound to: 32'b00000000000000000000000000100000 Parameter SHADOWCOPY bound to: 1'b1 Parameter RESETVALUE bound to: 32'b00000000000000000001100000000000 Parameter MASK bound to: 2234504 - type: integer INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_csr__parameterized8' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_debug_triggers' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_debug_triggers.sv:32] Parameter LIB bound to: 0 - type: integer Parameter DBG_NUM_TRIGGERS bound to: 32'sb00000000000000000000000000000001 INFO: [Synth 8-6157] synthesizing module 'cv32e40s_csr__parameterized9' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] Parameter LIB bound to: 0 - type: integer Parameter WIDTH bound to: 32'b00000000000000000000000000100000 Parameter SHADOWCOPY bound to: 1'b0 Parameter RESETVALUE bound to: 32'b00101000000000000001000000000000 INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_csr__parameterized9' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_csr__parameterized10' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] Parameter LIB bound to: 0 - type: integer Parameter WIDTH bound to: 32'b00000000000000000000000000100000 Parameter SHADOWCOPY bound to: 1'b0 Parameter RESETVALUE bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_csr__parameterized10' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_csr.sv:10] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_debug_triggers' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_debug_triggers.sv:32] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_cs_registers' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_cs_registers.sv:34] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_controller' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_controller.sv:32] Parameter REGFILE_NUM_READ_PORTS bound to: 32'b00000000000000000000000000000010 Parameter CLIC bound to: 1'b0 Parameter CLIC_ID_WIDTH bound to: 32'b00000000000000000000000000000101 Parameter RV32 bound to: 1'b0 Parameter DEBUG bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'cv32e40s_controller_fsm' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_controller_fsm.sv:32] Parameter DEBUG bound to: 1'b0 Parameter CLIC bound to: 1'b0 Parameter CLIC_ID_WIDTH bound to: 32'b00000000000000000000000000000101 Parameter RV32 bound to: 1'b0 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_controller_fsm.sv:627] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_controller_fsm.sv:627] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_controller_fsm.sv:740] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_controller_fsm.sv:740] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_controller_fsm' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_controller_fsm.sv:32] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_controller_bypass' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_controller_bypass.sv:33] Parameter REGFILE_NUM_READ_PORTS bound to: 32'b00000000000000000000000000000010 INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_controller_bypass' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_controller_bypass.sv:33] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_controller' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_controller.sv:32] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_register_file_wrapper' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_register_file_wrapper.sv:32] Parameter REGFILE_NUM_READ_PORTS bound to: 32'b00000000000000000000000000000010 Parameter RV32 bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'cv32e40s_register_file_ecc' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_register_file_ecc.sv:79] Parameter REGFILE_NUM_READ_PORTS bound to: 32'b00000000000000000000000000000010 INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_register_file_ecc' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_register_file_ecc.sv:79] INFO: [Synth 8-6157] synthesizing module 'cv32e40s_register_file' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_register_file.sv:29] Parameter REGFILE_NUM_READ_PORTS bound to: 32'b00000000000000000000000000000010 Parameter RV32 bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_register_file' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_register_file.sv:29] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_register_file_wrapper' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_register_file_wrapper.sv:32] INFO: [Synth 8-6155] done synthesizing module 'cv32e40s_core' (0#1) [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_core.sv:32] WARNING: [Synth 8-7071] port 'scan_cg_en_i' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'dm_exception_addr_i' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'mhartid_i' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'mimpid_patch_i' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'mtvec_addr_i' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'instr_memtype_o' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'instr_prot_o' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'instr_dbg_o' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'instr_err_i' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'instr_reqpar_o' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'instr_gntpar_i' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'instr_rvalidpar_i' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'instr_achk_o' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'instr_rchk_i' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'data_memtype_o' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'data_prot_o' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'data_dbg_o' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'data_err_i' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'data_reqpar_o' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'data_gntpar_i' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'data_rvalidpar_i' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'data_achk_o' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'data_rchk_i' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'mcycle_o' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'wu_wfe_i' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'clic_irq_i' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'clic_irq_id_i' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'clic_irq_level_i' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'clic_irq_priv_i' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'clic_irq_shv_i' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'fencei_flush_req_o' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'fencei_flush_ack_i' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'alert_minor_o' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'alert_major_o' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'debug_pc_valid_o' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7071] port 'debug_pc_o' of module 'cv32e40s_core' is unconnected for instance 'cv32e40s_core_i' [/eda/processor_ci/rtl/cv32e40s.sv:156] WARNING: [Synth 8-7023] instance 'cv32e40s_core_i' of module 'cv32e40s_core' has 60 connections declared, but only 24 given [/eda/processor_ci/rtl/cv32e40s.sv:156] INFO: [Synth 8-6155] done synthesizing module 'processorci_top' (0#1) [/eda/processor_ci/rtl/cv32e40s.sv:9] INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/rtl/reset.sv:1] Parameter CYCLES bound to: 32'sb00000000000000000000000000010100 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/rtl/reset.sv:32] INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/eda/processor-ci-controller/rtl/reset.sv:1] WARNING: [Synth 8-7071] port 'start' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/internal/fpga_top.sv:98] WARNING: [Synth 8-7071] port 'rst_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/internal/fpga_top.sv:98] WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 4 connections declared, but only 2 given [/eda/processor_ci/internal/fpga_top.sv:98] INFO: [Synth 8-6155] done synthesizing module 'fpga_top' (0#1) [/eda/processor_ci/internal/fpga_top.sv:8] WARNING: [Synth 8-3848] Net intr_o in module/entity Controller does not have driver. [/eda/processor-ci-controller/rtl/controller.sv:25] WARNING: [Synth 8-3936] Found unconnected internal register 'shifter_tmp_reg' and it is trimmed from '64' to '32' bits. [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_alu.sv:173] WARNING: [Synth 8-6014] Unused sequential element last_q_reg was removed. [/var/jenkins_home/workspace/cv32e40s/cv32e40s/rtl/cv32e40s_load_store_unit.sv:289] WARNING: [Synth 8-3848] Net miso in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/cv32e40s.sv:22] WARNING: [Synth 8-7129] Port clk in module cv32e40s_register_file_ecc is either unconnected or has no load WARNING: [Synth 8-7129] Port rst_n in module cv32e40s_register_file_ecc is either unconnected or has no load WARNING: [Synth 8-7129] Port waddr_i[0][4] in module cv32e40s_register_file_ecc is either unconnected or has no load WARNING: [Synth 8-7129] Port waddr_i[0][3] in module cv32e40s_register_file_ecc is either unconnected or has no load WARNING: [Synth 8-7129] Port waddr_i[0][2] in module cv32e40s_register_file_ecc is either unconnected or has no load WARNING: [Synth 8-7129] Port waddr_i[0][1] in module cv32e40s_register_file_ecc is either unconnected or has no load WARNING: [Synth 8-7129] Port waddr_i[0][0] in module cv32e40s_register_file_ecc is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_i[0][4] in module cv32e40s_register_file_ecc is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_i[0][3] in module cv32e40s_register_file_ecc is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_i[0][2] in module cv32e40s_register_file_ecc is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_i[0][1] in module cv32e40s_register_file_ecc is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_i[0][0] in module cv32e40s_register_file_ecc is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_i[1][4] in module cv32e40s_register_file_ecc is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_i[1][3] in module cv32e40s_register_file_ecc is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_i[1][2] in module cv32e40s_register_file_ecc is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_i[1][1] in module cv32e40s_register_file_ecc is either unconnected or has no load WARNING: [Synth 8-7129] Port raddr_i[1][0] in module cv32e40s_register_file_ecc is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][31] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][30] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][29] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][28] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][27] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][26] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][25] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][24] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][23] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][22] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][21] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][20] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][19] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][18] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][17] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][16] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][15] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][14] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][13] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][12] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][11] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][10] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][9] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][8] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][7] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][6] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][5] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][4] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][3] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][2] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][1] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rdata][0] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rchk][4] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rchk][3] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rchk][2] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rchk][1] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][rchk][0] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr][bus_resp][integrity] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr_meta][compressed] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[instr_meta][pushpop] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][31] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][30] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][29] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][28] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][27] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][26] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][25] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][24] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][23] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][22] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][21] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][20] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][19] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][18] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][17] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][16] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][15] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][14] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][13] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][12] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][11] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][10] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][9] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][8] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][7] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][6] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][5] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][4] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][3] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][2] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][1] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[pc][0] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[compressed_instr][15] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[compressed_instr][14] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[compressed_instr][13] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[compressed_instr][12] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[compressed_instr][11] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[compressed_instr][10] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[compressed_instr][9] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[compressed_instr][8] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[compressed_instr][7] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[compressed_instr][6] in module cv32e40s_controller_bypass is either unconnected or has no load WARNING: [Synth 8-7129] Port if_id_pipe_i[compressed_instr][5] in module cv32e40s_controller_bypass is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2210.719 ; gain = 580.684 ; free physical = 3288 ; free virtual = 25975 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2222.594 ; gain = 592.559 ; free physical = 3287 ; free virtual = 25974 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2222.594 ; gain = 592.559 ; free physical = 3287 ; free virtual = 25974 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2222.594 ; gain = 0.000 ; free physical = 3288 ; free virtual = 25975 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2360.344 ; gain = 0.000 ; free physical = 3266 ; free virtual = 25953 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2360.379 ; gain = 0.000 ; free physical = 3269 ; free virtual = 25956 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 2360.379 ; gain = 730.344 ; free physical = 3257 ; free virtual = 25945 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a100tcsg324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 2360.379 ; gain = 730.344 ; free physical = 3259 ; free virtual = 25946 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 2360.379 ; gain = 730.344 ; free physical = 3259 ; free virtual = 25946 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_rx' INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tx' INFO: [Synth 8-802] inferred FSM for state register 'state_read_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'state_write_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'tx_read_fifo_state_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'seq_state_q_reg' in module 'cv32e40s_sequencer' INFO: [Synth 8-802] inferred FSM for state register 'state_q_reg' in module 'cv32e40s_mpu' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'cv32e40s_div' INFO: [Synth 8-802] inferred FSM for state register 'state_q_reg' in module 'cv32e40s_wpt' INFO: [Synth 8-802] inferred FSM for state register 'state_q_reg' in module 'cv32e40s_mpu__parameterized0' INFO: [Synth 8-802] inferred FSM for state register 'ctrl_fsm_cs_reg' in module 'cv32e40s_controller_fsm' INFO: [Synth 8-802] inferred FSM for state register 'debug_fsm_cs_reg' in module 'cv32e40s_controller_fsm' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_RECV | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_rx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_SEND | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 0000 READ | 001 | 0001 COPY_READ_BUFFER | 010 | 0100 WB | 011 | 0010 FINISH | 100 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_read_reg' using encoding 'sequential' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 0000 COPY_WRITE_BUFFER | 001 | 0100 WRITE | 010 | 0101 WB | 011 | 0010 FINISH | 100 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_write_reg' using encoding 'sequential' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- TX_FIFO_IDLE | 0001 | 00 TX_FIFO_READ_FIFO | 0010 | 01 TX_FIFO_WRITE_TX | 0100 | 10 TX_FIFO_WAIT | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'tx_read_fifo_state_reg' using encoding 'one-hot' in module 'UART' WARNING: [Synth 8-327] inferring latch for variable 'clk_en_reg' [/var/jenkins_home/workspace/cv32e40s/cv32e40s/bhv/cv32e40s_sim_clock_gate.sv:31] --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- S_IDLE | 000 | 0000 S_POP | 001 | 0010 S_PUSH | 010 | 0001 S_RA | 011 | 0100 S_SP | 100 | 0101 S_A0 | 101 | 0110 S_RET | 110 | 0111 S_DMOVE | 111 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'seq_state_q_reg' using encoding 'sequential' in module 'cv32e40s_sequencer' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 00 | 000 iSTATE2 | 01 | 010 iSTATE3 | 10 | 001 iSTATE1 | 11 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_q_reg' using encoding 'sequential' in module 'cv32e40s_mpu' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- DIV_IDLE | 0001 | 00 DIV_DIVIDE | 0010 | 01 DIV_DUMMY | 0100 | 10 DIV_FINISH | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'cv32e40s_div' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WPT_IDLE | 001 | 00 WPT_MATCH_WAIT | 010 | 01 WPT_MATCH_RESP | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_q_reg' using encoding 'one-hot' in module 'cv32e40s_wpt' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 000 | 000 iSTATE0 | 001 | 100 iSTATE2 | 010 | 010 iSTATE3 | 011 | 001 iSTATE1 | 100 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_q_reg' using encoding 'sequential' in module 'cv32e40s_mpu__parameterized0' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RESET | 11 | 00 FUNCTIONAL | 01 | 01 DEBUG_TAKEN | 00 | 11 SLEEP | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'ctrl_fsm_cs_reg' using encoding 'sequential' in module 'cv32e40s_controller_fsm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * HAVERESET | 001 | 001 RUNNING | 010 | 010 HALTED | 100 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3898] No Re-encoding of one hot register 'debug_fsm_cs_reg' in module 'cv32e40s_controller_fsm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- INIT | 001 | 00 RESET_COUNTER | 010 | 01 IDLE | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'ResetBootSystem' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:26 ; elapsed = 00:00:26 . Memory (MB): peak = 2360.379 ; gain = 730.344 ; free physical = 3260 ; free virtual = 25950 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 64 Bit Adders := 4 2 Input 34 Bit Adders := 1 2 Input 33 Bit Adders := 1 2 Input 32 Bit Adders := 13 3 Input 32 Bit Adders := 1 2 Input 24 Bit Adders := 2 3 Input 12 Bit Adders := 1 2 Input 10 Bit Adders := 2 2 Input 8 Bit Adders := 2 2 Input 7 Bit Adders := 1 2 Input 6 Bit Adders := 3 32 Input 6 Bit Adders := 1 3 Input 5 Bit Adders := 1 2 Input 5 Bit Adders := 2 2 Input 4 Bit Adders := 5 3 Input 4 Bit Adders := 1 2 Input 3 Bit Adders := 6 4 Input 3 Bit Adders := 1 2 Input 2 Bit Adders := 12 3 Input 2 Bit Adders := 2 +---XORs : 2 Input 32 Bit XORs := 2 2 Input 6 Bit XORs := 3 2 Input 1 Bit XORs := 2 +---XORs : 38 Bit Wide XORs := 12 32 Bit Wide XORs := 6 8 Bit Wide XORs := 28 5 Bit Wide XORs := 3 3 Bit Wide XORs := 1 1 Bit Wide XORs := 2 +---Registers : 64 Bit Registers := 4 38 Bit Registers := 32 33 Bit Registers := 1 32 Bit Registers := 50 24 Bit Registers := 4 16 Bit Registers := 1 13 Bit Registers := 2 12 Bit Registers := 1 10 Bit Registers := 2 8 Bit Registers := 11 7 Bit Registers := 1 6 Bit Registers := 3 5 Bit Registers := 8 4 Bit Registers := 5 3 Bit Registers := 7 2 Bit Registers := 32 1 Bit Registers := 621 +---Multipliers : 32x32 Multipliers := 1 +---RAMs : 64K Bit (2048 X 32 bit) RAMs := 1 32K Bit (1024 X 32 bit) RAMs := 1 64 Bit (8 X 8 bit) RAMs := 2 +---Muxes : 4 Input 64 Bit Muxes := 1 2 Input 64 Bit Muxes := 15 48 Input 64 Bit Muxes := 2 2 Input 38 Bit Muxes := 1 2 Input 33 Bit Muxes := 2 4 Input 33 Bit Muxes := 1 5 Input 32 Bit Muxes := 2 2 Input 32 Bit Muxes := 125 8 Input 32 Bit Muxes := 1 4 Input 32 Bit Muxes := 18 3 Input 32 Bit Muxes := 7 6 Input 32 Bit Muxes := 1 20 Input 32 Bit Muxes := 1 23 Input 32 Bit Muxes := 1 2 Input 25 Bit Muxes := 1 48 Input 24 Bit Muxes := 1 2 Input 17 Bit Muxes := 4 4 Input 17 Bit Muxes := 2 3 Input 16 Bit Muxes := 1 2 Input 13 Bit Muxes := 3 2 Input 12 Bit Muxes := 2 3 Input 12 Bit Muxes := 2 4 Input 11 Bit Muxes := 2 2 Input 11 Bit Muxes := 1 2 Input 10 Bit Muxes := 6 4 Input 10 Bit Muxes := 2 48 Input 8 Bit Muxes := 2 2 Input 8 Bit Muxes := 7 3 Input 8 Bit Muxes := 1 4 Input 8 Bit Muxes := 2 24 Input 7 Bit Muxes := 1 2 Input 7 Bit Muxes := 4 5 Input 7 Bit Muxes := 1 4 Input 7 Bit Muxes := 1 3 Input 6 Bit Muxes := 2 2 Input 6 Bit Muxes := 7 2 Input 5 Bit Muxes := 22 19 Input 5 Bit Muxes := 1 3 Input 5 Bit Muxes := 3 8 Input 5 Bit Muxes := 2 7 Input 5 Bit Muxes := 1 10 Input 5 Bit Muxes := 1 12 Input 5 Bit Muxes := 1 6 Input 5 Bit Muxes := 1 9 Input 5 Bit Muxes := 1 23 Input 5 Bit Muxes := 1 57 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 11 7 Input 4 Bit Muxes := 1 9 Input 4 Bit Muxes := 1 4 Input 4 Bit Muxes := 2 10 Input 4 Bit Muxes := 1 3 Input 4 Bit Muxes := 1 8 Input 4 Bit Muxes := 1 5 Input 3 Bit Muxes := 6 2 Input 3 Bit Muxes := 26 3 Input 3 Bit Muxes := 6 4 Input 3 Bit Muxes := 7 18 Input 3 Bit Muxes := 1 12 Input 3 Bit Muxes := 1 6 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 143 48 Input 2 Bit Muxes := 1 4 Input 2 Bit Muxes := 24 3 Input 2 Bit Muxes := 10 5 Input 2 Bit Muxes := 4 8 Input 2 Bit Muxes := 4 7 Input 2 Bit Muxes := 5 10 Input 2 Bit Muxes := 2 12 Input 2 Bit Muxes := 9 6 Input 2 Bit Muxes := 1 11 Input 2 Bit Muxes := 1 14 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 326 48 Input 1 Bit Muxes := 22 3 Input 1 Bit Muxes := 52 4 Input 1 Bit Muxes := 78 5 Input 1 Bit Muxes := 18 8 Input 1 Bit Muxes := 11 14 Input 1 Bit Muxes := 1 7 Input 1 Bit Muxes := 5 6 Input 1 Bit Muxes := 2 10 Input 1 Bit Muxes := 5 12 Input 1 Bit Muxes := 20 9 Input 1 Bit Muxes := 2 57 Input 1 Bit Muxes := 2 47 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 240 (col length:80) BRAMs: 270 (col length: RAMB18 80 RAMB36 40) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met DSP Report: Generating DSP int_result, operation Mode is: A*B. DSP Report: operator int_result is absorbed into DSP int_result. DSP Report: operator int_result is absorbed into DSP int_result. DSP Report: Generating DSP int_result, operation Mode is: (PCIN>>17)+A*B. DSP Report: operator int_result is absorbed into DSP int_result. DSP Report: operator int_result is absorbed into DSP int_result. DSP Report: Generating DSP int_result, operation Mode is: A*B. DSP Report: operator int_result is absorbed into DSP int_result. DSP Report: operator int_result is absorbed into DSP int_result. DSP Report: Generating DSP int_result, operation Mode is: (PCIN>>17)+A*B. DSP Report: operator int_result is absorbed into DSP int_result. DSP Report: operator int_result is absorbed into DSP int_result. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:02:10 ; elapsed = 00:02:10 . Memory (MB): peak = 2360.379 ; gain = 730.344 ; free physical = 3178 ; free virtual = 25888 --------------------------------------------------------------------------------- Sort Area is int_result_0 : 0 0 : 3101 5754 : Used 1 time 0 Sort Area is int_result_0 : 0 1 : 2653 5754 : Used 1 time 0 Sort Area is int_result_3 : 0 0 : 2634 5119 : Used 1 time 0 Sort Area is int_result_3 : 0 1 : 2485 5119 : Used 1 time 0 --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- ROM: Preliminary Mapping Report +------------+---------------------+---------------+----------------+ |Module Name | RTL Object | Depth x Width | Implemented As | +------------+---------------------+---------------+----------------+ |Interpreter | memory_mux_selector | 256x1 | LUT | |Interpreter | memory_mux_selector | 256x1 | LUT | +------------+---------------------+---------------+----------------+ Distributed RAM: Preliminary Mapping Report (see note below) +------------+-----------------------------------------------+-----------+----------------------+------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+-----------------------------------------------+-----------+----------------------+------------------+ |fpga_top | ptop/u_Controller/Uart/tx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |fpga_top | ptop/u_Controller/Uart/rx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |fpga_top | ptop/u_Controller/Core_Memory/memory_reg | Implied | 2 K x 32 | RAM256X1S x 256 | |fpga_top | ptop/u_Controller/Core_Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | +------------+-----------------------------------------------+-----------+----------------------+------------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set) +--------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | +--------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |cv32e40s_mult | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |cv32e40s_mult | (PCIN>>17)+A*B | 15 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |cv32e40s_mult | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |cv32e40s_mult | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +--------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:02:16 ; elapsed = 00:02:17 . Memory (MB): peak = 2360.379 ; gain = 730.344 ; free physical = 3192 ; free virtual = 25902 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:02:25 ; elapsed = 00:02:26 . Memory (MB): peak = 2360.379 ; gain = 730.344 ; free physical = 3176 ; free virtual = 25887 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Distributed RAM: Final Mapping Report +------------+-----------------------------------------------+-----------+----------------------+------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+-----------------------------------------------+-----------+----------------------+------------------+ |fpga_top | ptop/u_Controller/Uart/tx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |fpga_top | ptop/u_Controller/Uart/rx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |fpga_top | ptop/u_Controller/Core_Memory/memory_reg | Implied | 2 K x 32 | RAM256X1S x 256 | |fpga_top | ptop/u_Controller/Core_Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | +------------+-----------------------------------------------+-----------+----------------------+------------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:02:31 ; elapsed = 00:02:32 . Memory (MB): peak = 2423.328 ; gain = 793.293 ; free physical = 3056 ; free virtual = 25767 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:02:35 ; elapsed = 00:02:36 . Memory (MB): peak = 2423.328 ; gain = 793.293 ; free physical = 3055 ; free virtual = 25766 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:02:35 ; elapsed = 00:02:36 . Memory (MB): peak = 2423.328 ; gain = 793.293 ; free physical = 3054 ; free virtual = 25765 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:36 ; elapsed = 00:02:37 . Memory (MB): peak = 2423.328 ; gain = 793.293 ; free physical = 3053 ; free virtual = 25764 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:02:36 ; elapsed = 00:02:37 . Memory (MB): peak = 2423.328 ; gain = 793.293 ; free physical = 3053 ; free virtual = 25764 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:02:36 ; elapsed = 00:02:38 . Memory (MB): peak = 2423.328 ; gain = 793.293 ; free physical = 3053 ; free virtual = 25764 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:02:36 ; elapsed = 00:02:38 . Memory (MB): peak = 2423.328 ; gain = 793.293 ; free physical = 3053 ; free virtual = 25764 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- DSP Final Report (the ' indicates corresponding REG is set) +--------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | +--------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |cv32e40s_mult | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |cv32e40s_mult | A*B | 17 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |cv32e40s_mult | PCIN>>17+A*B | 0 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +--------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+----------+------+ | |Cell |Count | +------+----------+------+ |1 |BUFG | 5| |2 |CARRY4 | 251| |3 |DSP48E1 | 3| |4 |LUT1 | 38| |5 |LUT2 | 620| |6 |LUT3 | 1005| |7 |LUT4 | 683| |8 |LUT5 | 960| |9 |LUT6 | 2923| |10 |MUXF7 | 367| |11 |MUXF8 | 60| |12 |RAM256X1S | 384| |13 |RAM32M | 2| |14 |RAM32X1D | 4| |15 |FDCE | 2476| |16 |FDPE | 33| |17 |FDRE | 756| |18 |FDSE | 5| |19 |LD | 11| |20 |IBUF | 2| |21 |OBUF | 1| |22 |OBUFT | 2| +------+----------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:02:37 ; elapsed = 00:02:38 . Memory (MB): peak = 2423.328 ; gain = 793.293 ; free physical = 3053 ; free virtual = 25764 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 10868 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:02:32 ; elapsed = 00:02:34 . Memory (MB): peak = 2423.328 ; gain = 655.508 ; free physical = 3053 ; free virtual = 25764 Synthesis Optimization Complete : Time (s): cpu = 00:02:37 ; elapsed = 00:02:38 . Memory (MB): peak = 2423.336 ; gain = 793.293 ; free physical = 3053 ; free virtual = 25764 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2423.336 ; gain = 0.000 ; free physical = 3332 ; free virtual = 26043 INFO: [Netlist 29-17] Analyzing 1082 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2519.375 ; gain = 0.000 ; free physical = 3336 ; free virtual = 26047 INFO: [Project 1-111] Unisim Transformation Summary: A total of 401 instances were transformed. LD => LDCE: 11 instances RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 384 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances Synth Design complete | Checksum: 62ddcb0b INFO: [Common 17-83] Releasing license: Synthesis 271 Infos, 253 Warnings, 2 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:02:47 ; elapsed = 00:02:46 . Memory (MB): peak = 2519.410 ; gain = 1199.414 ; free physical = 3335 ; free virtual = 26046 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2251.684; main = 1963.682; forked = 430.584 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3403.684; main = 2519.379; forked = 982.352 # opt_design Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.71 . Memory (MB): peak = 2583.406 ; gain = 63.996 ; free physical = 3327 ; free virtual = 26038 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 1e3bba8ae Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2599.414 ; gain = 16.008 ; free physical = 3402 ; free virtual = 26114 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 1e3bba8ae Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2775.414 ; gain = 0.000 ; free physical = 3177 ; free virtual = 25888 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1e3bba8ae Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2775.414 ; gain = 0.000 ; free physical = 3177 ; free virtual = 25888 Phase 1 Initialization | Checksum: 1e3bba8ae Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2775.414 ; gain = 0.000 ; free physical = 3177 ; free virtual = 25888 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update Phase 2.1 Timer Update | Checksum: 1e3bba8ae Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2775.414 ; gain = 0.000 ; free physical = 3177 ; free virtual = 25888 Phase 2.2 Timing Data Collection Phase 2.2 Timing Data Collection | Checksum: 1e3bba8ae Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2775.414 ; gain = 0.000 ; free physical = 3175 ; free virtual = 25886 Phase 2 Timer Update And Timing Data Collection | Checksum: 1e3bba8ae Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2775.414 ; gain = 0.000 ; free physical = 3175 ; free virtual = 25886 Phase 3 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 1e3bba8ae Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2775.414 ; gain = 0.000 ; free physical = 3175 ; free virtual = 25886 Retarget | Checksum: 1e3bba8ae INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 269c0bc9b Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.4 . Memory (MB): peak = 2775.414 ; gain = 0.000 ; free physical = 3175 ; free virtual = 25886 Constant propagation | Checksum: 269c0bc9b INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep Phase 5 Sweep | Checksum: 279a407c8 Time (s): cpu = 00:00:00.9 ; elapsed = 00:00:00.52 . Memory (MB): peak = 2775.414 ; gain = 0.000 ; free physical = 3175 ; free virtual = 25886 Sweep | Checksum: 279a407c8 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells Phase 6 BUFG optimization INFO: [Opt 31-194] Inserted BUFG ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_5_BUFG_inst to drive 31 load(s) on clock net ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_5_BUFG INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets Phase 6 BUFG optimization | Checksum: 1dd3c7964 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2807.430 ; gain = 32.016 ; free physical = 3174 ; free virtual = 25885 BUFG optimization | Checksum: 1dd3c7964 INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 1dd3c7964 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.63 . Memory (MB): peak = 2807.430 ; gain = 32.016 ; free physical = 3174 ; free virtual = 25885 Shift Register Optimization | Checksum: 1dd3c7964 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 1dd3c7964 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.66 . Memory (MB): peak = 2807.430 ; gain = 32.016 ; free physical = 3174 ; free virtual = 25885 Post Processing Netlist | Checksum: 1dd3c7964 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1bd5eedf8 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.79 . Memory (MB): peak = 2807.430 ; gain = 32.016 ; free physical = 3167 ; free virtual = 25878 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2807.430 ; gain = 0.000 ; free physical = 3172 ; free virtual = 25883 Phase 9.2 Verifying Netlist Connectivity | Checksum: 1bd5eedf8 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2807.430 ; gain = 32.016 ; free physical = 3172 ; free virtual = 25883 Phase 9 Finalization | Checksum: 1bd5eedf8 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2807.430 ; gain = 32.016 ; free physical = 3172 ; free virtual = 25883 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 0 | 0 | 0 | | Constant propagation | 0 | 0 | 0 | | Sweep | 0 | 0 | 0 | | BUFG optimization | 1 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 1bd5eedf8 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2807.430 ; gain = 32.016 ; free physical = 3172 ; free virtual = 25883 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2807.430 ; gain = 0.000 ; free physical = 3172 ; free virtual = 25883 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. Ending Power Optimization Task | Checksum: 1bd5eedf8 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2807.430 ; gain = 0.000 ; free physical = 3169 ; free virtual = 25880 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: 1bd5eedf8 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2807.430 ; gain = 0.000 ; free physical = 3169 ; free virtual = 25880 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2807.430 ; gain = 0.000 ; free physical = 3168 ; free virtual = 25879 Ending Netlist Obfuscation Task | Checksum: 1bd5eedf8 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2807.430 ; gain = 0.000 ; free physical = 3168 ; free virtual = 25879 INFO: [Common 17-83] Releasing license: Implementation 20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 2807.430 ; gain = 288.020 ; free physical = 3168 ; free virtual = 25879 # place_design Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-83] Releasing license: Implementation INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2839.445 ; gain = 0.000 ; free physical = 3164 ; free virtual = 25875 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 18d943343 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2839.445 ; gain = 0.000 ; free physical = 3164 ; free virtual = 25875 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2839.445 ; gain = 0.000 ; free physical = 3163 ; free virtual = 25874 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Place 30-568] A LUT 'ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__11' is driving clock pin of 9 registers. This could lead to large hold time violations. First few involved registers are: ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.gen_csr_hardened[0].gen_unmasked_hardened.gen_rv1.sffs_rdatareg/q_o_reg {FDPE} ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.gen_csr_hardened[16].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.gen_csr_hardened[18].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.gen_csr_hardened[17].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.gen_csr_hardened[3].gen_unmasked_hardened.gen_rv1.sffs_rdatareg/q_o_reg {FDPE} WARNING: [Place 30-568] A LUT 'ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__15' is driving clock pin of 6 registers. This could lead to large hold time violations. First few involved registers are: ptop/cv32e40s_core_i/cs_registers_i/mstatus_csr_i/gen_hardened.gen_csr_hardened[12].gen_unmasked_hardened.gen_rv1.sffs_rdatareg/q_o_reg {FDPE} ptop/cv32e40s_core_i/cs_registers_i/mstatus_csr_i/gen_hardened.gen_csr_hardened[17].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} ptop/cv32e40s_core_i/cs_registers_i/mstatus_csr_i/gen_hardened.gen_csr_hardened[21].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} ptop/cv32e40s_core_i/cs_registers_i/mstatus_csr_i/gen_hardened.gen_csr_hardened[3].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} ptop/cv32e40s_core_i/cs_registers_i/mstatus_csr_i/gen_hardened.gen_csr_hardened[7].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} WARNING: [Place 30-568] A LUT 'ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__8' is driving clock pin of 12 registers. This could lead to large hold time violations. First few involved registers are: ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[4].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[5].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[6].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[0].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[10].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} WARNING: [Place 30-568] A LUT 'ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__9' is driving clock pin of 26 registers. This could lead to large hold time violations. First few involved registers are: ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[9].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[8].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[7].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[31].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[30].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} WARNING: [Place 30-568] A LUT 'ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__12' is driving clock pin of 26 registers. This could lead to large hold time violations. First few involved registers are: ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[28].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[9].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[8].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[7].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[6].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} WARNING: [Place 30-568] A LUT 'ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__10' is driving clock pin of 19 registers. This could lead to large hold time violations. First few involved registers are: ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[24].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[25].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[26].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[27].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[28].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} WARNING: [Place 30-568] A LUT 'ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_1__107' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: ptop/cv32e40s_core_i/cs_registers_i/mstateen0_csr_i/gen_hardened.gen_csr_hardened[2].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg {FDCE} WARNING: [Place 30-568] A LUT 'ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__16' is driving clock pin of 2 registers. This could lead to large hold time violations. First few involved registers are: ptop/cv32e40s_core_i/cs_registers_i/privlvl_user.priv_lvl_i/gen_hardened.gen_csr_hardened[0].gen_unmasked_hardened.gen_rv1.sffs_rdatareg/q_o_reg {FDPE} ptop/cv32e40s_core_i/cs_registers_i/privlvl_user.priv_lvl_i/gen_hardened.gen_csr_hardened[1].gen_unmasked_hardened.gen_rv1.sffs_rdatareg/q_o_reg {FDPE} Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 101a79568 Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.445 ; gain = 0.000 ; free physical = 3164 ; free virtual = 25875 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1a91488d2 Time (s): cpu = 00:00:10 ; elapsed = 00:00:04 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3157 ; free virtual = 25868 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1a91488d2 Time (s): cpu = 00:00:10 ; elapsed = 00:00:04 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3157 ; free virtual = 25868 Phase 1 Placer Initialization | Checksum: 1a91488d2 Time (s): cpu = 00:00:10 ; elapsed = 00:00:04 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3157 ; free virtual = 25868 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 160d5e59f Time (s): cpu = 00:00:10 ; elapsed = 00:00:04 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3153 ; free virtual = 25864 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1df802e60 Time (s): cpu = 00:00:10 ; elapsed = 00:00:04 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3153 ; free virtual = 25864 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 1df802e60 Time (s): cpu = 00:00:10 ; elapsed = 00:00:04 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3153 ; free virtual = 25864 Phase 2.4 Global Placement Core Phase 2.4.1 UpdateTiming Before Physical Synthesis Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1d053f3e2 Time (s): cpu = 00:00:22 ; elapsed = 00:00:08 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3135 ; free virtual = 25846 Phase 2.4.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 320 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-1138] End 1 Pass. Optimized 119 nets or LUTs. Breaked 0 LUT, combined 119 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2846.473 ; gain = 0.000 ; free physical = 3139 ; free virtual = 25850 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 119 | 119 | 0 | 1 | 00:00:01 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 119 | 119 | 0 | 4 | 00:00:01 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1d28a0ca9 Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3139 ; free virtual = 25850 Phase 2.4 Global Placement Core | Checksum: 1fd13c56b Time (s): cpu = 00:00:25 ; elapsed = 00:00:10 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3140 ; free virtual = 25851 Phase 2 Global Placement | Checksum: 1fd13c56b Time (s): cpu = 00:00:25 ; elapsed = 00:00:10 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3140 ; free virtual = 25851 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 17706f6ad Time (s): cpu = 00:00:25 ; elapsed = 00:00:10 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3139 ; free virtual = 25850 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: fd88123d Time (s): cpu = 00:00:25 ; elapsed = 00:00:10 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3139 ; free virtual = 25850 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: c4453403 Time (s): cpu = 00:00:25 ; elapsed = 00:00:10 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3139 ; free virtual = 25850 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 180f1ff1b Time (s): cpu = 00:00:25 ; elapsed = 00:00:10 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3139 ; free virtual = 25850 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 1eabccb13 Time (s): cpu = 00:00:28 ; elapsed = 00:00:13 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3147 ; free virtual = 25858 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 24676aa74 Time (s): cpu = 00:00:29 ; elapsed = 00:00:13 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3148 ; free virtual = 25859 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1f34d9b7c Time (s): cpu = 00:00:29 ; elapsed = 00:00:13 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3143 ; free virtual = 25855 Phase 3 Detail Placement | Checksum: 1f34d9b7c Time (s): cpu = 00:00:29 ; elapsed = 00:00:13 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3141 ; free virtual = 25852 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 24271c878 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.840 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 1a7bcee3d Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2846.473 ; gain = 0.000 ; free physical = 3141 ; free virtual = 25852 INFO: [Place 46-33] Processed net ptop/u_Controller/Interpreter/rst_core, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 1a7bcee3d Time (s): cpu = 00:00:00.96 ; elapsed = 00:00:00.59 . Memory (MB): peak = 2846.473 ; gain = 0.000 ; free physical = 3137 ; free virtual = 25848 Phase 4.1.1.1 BUFG Insertion | Checksum: 24271c878 Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3137 ; free virtual = 25848 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=8.840. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1dc702644 Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3136 ; free virtual = 25847 Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3136 ; free virtual = 25847 Phase 4.1 Post Commit Optimization | Checksum: 1dc702644 Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3135 ; free virtual = 25847 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1dc702644 Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3134 ; free virtual = 25845 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 2x2| |___________|___________________|___________________| | South| 1x1| 2x2| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 1dc702644 Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3134 ; free virtual = 25845 Phase 4.3 Placer Reporting | Checksum: 1dc702644 Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3134 ; free virtual = 25845 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2846.473 ; gain = 0.000 ; free physical = 3134 ; free virtual = 25845 Time (s): cpu = 00:00:38 ; elapsed = 00:00:17 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3134 ; free virtual = 25845 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2083d79fd Time (s): cpu = 00:00:38 ; elapsed = 00:00:17 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3135 ; free virtual = 25846 Ending Placer Task | Checksum: 1a3bf8741 Time (s): cpu = 00:00:38 ; elapsed = 00:00:17 . Memory (MB): peak = 2846.473 ; gain = 7.027 ; free physical = 3135 ; free virtual = 25846 30 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:40 ; elapsed = 00:00:17 . Memory (MB): peak = 2846.473 ; gain = 39.043 ; free physical = 3135 ; free virtual = 25846 # report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt # report_utilization -file digilent_arty_a7_utilization_place.rpt # report_io -file digilent_arty_a7_io.rpt report_io: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2846.473 ; gain = 0.000 ; free physical = 3135 ; free virtual = 25846 # report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2846.473 ; gain = 0.000 ; free physical = 3135 ; free virtual = 25846 # report_clock_utilization -file digilent_arty_a7_clock_utilization.rpt # route_design Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Build RT Design Checksum: PlaceDB: fe2bef5b ConstDB: 0 ShapeSum: a59397e6 RouteDB: 0 Post Restoration Checksum: NetGraph: c0147470 | NumContArr: e9a60d8f | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 32f0c7739 Time (s): cpu = 00:00:38 ; elapsed = 00:00:26 . Memory (MB): peak = 2902.500 ; gain = 0.000 ; free physical = 3136 ; free virtual = 25847 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 32f0c7739 Time (s): cpu = 00:00:38 ; elapsed = 00:00:26 . Memory (MB): peak = 2902.500 ; gain = 0.000 ; free physical = 3136 ; free virtual = 25847 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 32f0c7739 Time (s): cpu = 00:00:38 ; elapsed = 00:00:26 . Memory (MB): peak = 2902.500 ; gain = 0.000 ; free physical = 3136 ; free virtual = 25847 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 27a0b404b Time (s): cpu = 00:00:49 ; elapsed = 00:00:29 . Memory (MB): peak = 2902.500 ; gain = 0.000 ; free physical = 3147 ; free virtual = 25858 INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.797 | TNS=0.000 | WHS=0.007 | THS=0.000 | Router Utilization Summary Global Vertical Routing Utilization = 0.0421726 % Global Horizontal Routing Utilization = 0.0349531 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 8577 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 8543 Number of Partially Routed Nets = 34 Number of Node Overlaps = 28 Phase 2 Router Initialization | Checksum: 2769765ed Time (s): cpu = 00:00:53 ; elapsed = 00:00:30 . Memory (MB): peak = 2902.500 ; gain = 0.000 ; free physical = 3135 ; free virtual = 25846 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 2769765ed Time (s): cpu = 00:00:53 ; elapsed = 00:00:30 . Memory (MB): peak = 2902.500 ; gain = 0.000 ; free physical = 3134 ; free virtual = 25846 Phase 3.2 Initial Net Routing Phase 3.2 Initial Net Routing | Checksum: 22154dbfa Time (s): cpu = 00:00:57 ; elapsed = 00:00:31 . Memory (MB): peak = 2902.500 ; gain = 0.000 ; free physical = 3132 ; free virtual = 25844 Phase 3 Initial Routing | Checksum: 22154dbfa Time (s): cpu = 00:00:57 ; elapsed = 00:00:31 . Memory (MB): peak = 2902.500 ; gain = 0.000 ; free physical = 3132 ; free virtual = 25844 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 913 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.264 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 22e2be6bd Time (s): cpu = 00:01:04 ; elapsed = 00:00:34 . Memory (MB): peak = 2902.500 ; gain = 0.000 ; free physical = 3129 ; free virtual = 25841 Phase 4 Rip-up And Reroute | Checksum: 22e2be6bd Time (s): cpu = 00:01:04 ; elapsed = 00:00:34 . Memory (MB): peak = 2902.500 ; gain = 0.000 ; free physical = 3129 ; free virtual = 25841 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 22e2be6bd Time (s): cpu = 00:01:04 ; elapsed = 00:00:34 . Memory (MB): peak = 2902.500 ; gain = 0.000 ; free physical = 3129 ; free virtual = 25841 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 22e2be6bd Time (s): cpu = 00:01:04 ; elapsed = 00:00:34 . Memory (MB): peak = 2902.500 ; gain = 0.000 ; free physical = 3129 ; free virtual = 25841 Phase 5 Delay and Skew Optimization | Checksum: 22e2be6bd Time (s): cpu = 00:01:04 ; elapsed = 00:00:34 . Memory (MB): peak = 2902.500 ; gain = 0.000 ; free physical = 3129 ; free virtual = 25841 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 1d2ae8c81 Time (s): cpu = 00:01:05 ; elapsed = 00:00:34 . Memory (MB): peak = 2902.500 ; gain = 0.000 ; free physical = 3130 ; free virtual = 25841 INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.361 | TNS=0.000 | WHS=0.514 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 1d2ae8c81 Time (s): cpu = 00:01:05 ; elapsed = 00:00:34 . Memory (MB): peak = 2902.500 ; gain = 0.000 ; free physical = 3130 ; free virtual = 25841 Phase 6 Post Hold Fix | Checksum: 1d2ae8c81 Time (s): cpu = 00:01:05 ; elapsed = 00:00:34 . Memory (MB): peak = 2902.500 ; gain = 0.000 ; free physical = 3130 ; free virtual = 25841 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 1.99125 % Global Horizontal Routing Utilization = 2.60827 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 1d2ae8c81 Time (s): cpu = 00:01:05 ; elapsed = 00:00:34 . Memory (MB): peak = 2902.500 ; gain = 0.000 ; free physical = 3130 ; free virtual = 25841 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1d2ae8c81 Time (s): cpu = 00:01:05 ; elapsed = 00:00:34 . Memory (MB): peak = 2902.500 ; gain = 0.000 ; free physical = 3130 ; free virtual = 25841 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1e4d00f40 Time (s): cpu = 00:01:07 ; elapsed = 00:00:35 . Memory (MB): peak = 2902.500 ; gain = 0.000 ; free physical = 3130 ; free virtual = 25841 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=8.361 | TNS=0.000 | WHS=0.514 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: 1e4d00f40 Time (s): cpu = 00:01:07 ; elapsed = 00:00:35 . Memory (MB): peak = 2902.500 ; gain = 0.000 ; free physical = 3130 ; free virtual = 25841 INFO: [Route 35-16] Router Completed Successfully Phase 11 Post-Route Event Processing Phase 11 Post-Route Event Processing | Checksum: 1a7c26d0f Time (s): cpu = 00:01:08 ; elapsed = 00:00:35 . Memory (MB): peak = 2902.500 ; gain = 0.000 ; free physical = 3130 ; free virtual = 25841 Ending Routing Task | Checksum: 1a7c26d0f Time (s): cpu = 00:01:08 ; elapsed = 00:00:35 . Memory (MB): peak = 2902.500 ; gain = 0.000 ; free physical = 3128 ; free virtual = 25839 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:01:10 ; elapsed = 00:00:37 . Memory (MB): peak = 2902.500 ; gain = 0.000 ; free physical = 3116 ; free virtual = 25827 # report_timing_summary -no_header -no_detailed_paths INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Inter-SLR Compensation : Conservative Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes ------------------------------------------------------------------------------------------------ | Report Methodology | ------------------ ------------------------------------------------------------------------------------------------ No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. check_timing report Table of Contents ----------------- 1. checking no_clock (89217) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (24653) 5. checking no_input_delay (1) 6. checking no_output_delay (1) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (1) 1. checking no_clock (89217) ---------------------------- There are 4840 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH) There are 12 register/latch pins with no clock driven by root clock pin: ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.core_clock_gate_i/clk_en_reg/Q (HIGH) There are 19 register/latch pins with no clock driven by root clock pin: ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.core_clock_gate_i/clk_en_reg/Q (HIGH) There are 26 register/latch pins with no clock driven by root clock pin: ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.core_clock_gate_i/clk_en_reg/Q (HIGH) There are 26 register/latch pins with no clock driven by root clock pin: ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.core_clock_gate_i/clk_en_reg/Q (HIGH) There are 31 register/latch pins with no clock driven by root clock pin: ptop/cv32e40s_core_i/cs_registers_i/mepc_csr_i/gen_hardened.core_clock_gate_i/clk_en_reg/Q (HIGH) There are 32 register/latch pins with no clock driven by root clock pin: ptop/cv32e40s_core_i/cs_registers_i/mscratch_csr_i/gen_hardened.core_clock_gate_i/clk_en_reg/Q (HIGH) There is 1 register/latch pin with no clock driven by root clock pin: ptop/cv32e40s_core_i/cs_registers_i/mstateen0_csr_i/gen_hardened.core_clock_gate_i/clk_en_reg/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ptop/cv32e40s_core_i/cs_registers_i/mstatus_csr_i/gen_hardened.core_clock_gate_i/clk_en_reg/Q (HIGH) There are 2 register/latch pins with no clock driven by root clock pin: ptop/cv32e40s_core_i/cs_registers_i/privlvl_user.priv_lvl_i/gen_hardened.core_clock_gate_i/clk_en_reg/Q (HIGH) There are 9 register/latch pins with no clock driven by root clock pin: ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.core_clock_gate_i/clk_en_reg/Q (HIGH) There are 2485 register/latch pins with no clock driven by root clock pin: ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/clk_en_reg/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[0]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[10]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[11]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[12]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[13]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[14]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[15]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[16]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[17]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[18]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[19]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[1]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[20]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[21]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[22]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[23]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[24]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[25]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[26]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[27]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[28]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[29]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[2]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[30]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[31]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[3]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[4]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[5]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[6]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[7]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[8]/Q (HIGH) There are 2554 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[9]/Q (HIGH) 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (24653) ---------------------------------------------------- There are 24653 pins that are not constrained for maximum delay. (HIGH) There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (1) ------------------------------ There is 1 input port with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay (1) ------------------------------- There is 1 port with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (1) ---------------------------- There is 1 combinational latch loop in the design through latch input (HIGH) ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 8.385 0.000 0 1 0.530 0.000 0 1 4.500 0.000 0 2 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- sck {0.000 50.000} 100.000 10.000 sys_clk_pin {0.000 5.000} 10.000 100.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- sys_clk_pin 8.385 0.000 0 1 0.530 0.000 0 1 4.500 0.000 0 2 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- # report_route_status -file digilent_arty_a7_route_status.rpt # report_drc -file digilent_arty_a7_drc.rpt Command: report_drc -file digilent_arty_a7_drc.rpt INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'. INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/jenkins_home/workspace/cv32e40s/cv32e40s/digilent_arty_a7_drc.rpt. report_drc completed successfully # report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs # report_power -file digilent_arty_a7_power.rpt Command: report_power -file digilent_arty_a7_power.rpt Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully # write_bitstream -force "digilent_arty_a7_100t.bit" Command: write_bitstream -force digilent_arty_a7_100t.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. WARNING: [DRC DPIP-1] Input pipelining: DSP ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result input ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result input ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__0 input ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__0 input ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__1 input ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result output ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__0 output ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__1 output ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result multiplier stage ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__0 multiplier stage ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__1 multiplier stage ptop/cv32e40s_core_i/ex_stage_i/mul.mult_i/int_result__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC PDRC-153] Gated clock check: Net ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated is a gated clock net sourced by a combinational pin ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__8/O, cell ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__8. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_0 is a gated clock net sourced by a combinational pin ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__9/O, cell ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__9. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_1 is a gated clock net sourced by a combinational pin ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__10/O, cell ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__10. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_2 is a gated clock net sourced by a combinational pin ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__11/O, cell ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__11. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_3 is a gated clock net sourced by a combinational pin ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_1__107/O, cell ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_1__107. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_4 is a gated clock net sourced by a combinational pin ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__12/O, cell ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__12. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_6 is a gated clock net sourced by a combinational pin ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__15/O, cell ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__15. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/gen_hardened.clk_gated_7 is a gated clock net sourced by a combinational pin ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__16/O, cell ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__16. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ptop/u_Controller/ClkDivider/clk_o_reg_0 is a gated clock net sourced by a combinational pin ptop/u_Controller/ClkDivider/clk_en_reg_i_2__9/O, cell ptop/u_Controller/ClkDivider/clk_en_reg_i_2__9. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ptop/u_Controller/ClkDivider/clk_o_reg_1 is a gated clock net sourced by a combinational pin ptop/u_Controller/ClkDivider/clk_en_reg_i_1__9/O, cell ptop/u_Controller/ClkDivider/clk_en_reg_i_1__9. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_1__107 is driving clock pin of 1 cells. This could lead to large hold time violations. Involved cells are: ptop/cv32e40s_core_i/cs_registers_i/mstateen0_csr_i/gen_hardened.gen_csr_hardened[2].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__10 is driving clock pin of 19 cells. This could lead to large hold time violations. Involved cells are: ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[11].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[16].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[17].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[18].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[19].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[20].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[21].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[22].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[23].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[24].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[25].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[26].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[27].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[28].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mie_csr_i/gen_hardened.gen_csr_hardened[29].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg... and (the first 15 of 19 listed) WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__11 is driving clock pin of 9 cells. This could lead to large hold time violations. Involved cells are: ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.gen_csr_hardened[0].gen_unmasked_hardened.gen_rv1.sffs_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.gen_csr_hardened[16].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.gen_csr_hardened[17].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.gen_csr_hardened[18].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.gen_csr_hardened[19].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.gen_csr_hardened[1].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.gen_csr_hardened[2].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.gen_csr_hardened[3].gen_unmasked_hardened.gen_rv1.sffs_rdatareg/q_o_reg, and ptop/cv32e40s_core_i/cs_registers_i/xsecure.cpuctrl_csr_i/gen_hardened.gen_csr_hardened[4].gen_unmasked_hardened.gen_rv1.sffs_rdatareg/q_o_reg WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__12 is driving clock pin of 26 cells. This could lead to large hold time violations. Involved cells are: ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[10].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[11].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[12].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[13].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[14].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[15].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[16].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[17].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[18].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[19].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[20].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[21].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[22].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[23].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/jvt_csr_i/gen_hardened.gen_csr_hardened[24].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg... and (the first 15 of 26 listed) WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__15 is driving clock pin of 6 cells. This could lead to large hold time violations. Involved cells are: ptop/cv32e40s_core_i/cs_registers_i/mstatus_csr_i/gen_hardened.gen_csr_hardened[11].gen_unmasked_hardened.gen_rv1.sffs_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/mstatus_csr_i/gen_hardened.gen_csr_hardened[12].gen_unmasked_hardened.gen_rv1.sffs_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/mstatus_csr_i/gen_hardened.gen_csr_hardened[17].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/mstatus_csr_i/gen_hardened.gen_csr_hardened[21].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/mstatus_csr_i/gen_hardened.gen_csr_hardened[3].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, and ptop/cv32e40s_core_i/cs_registers_i/mstatus_csr_i/gen_hardened.gen_csr_hardened[7].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__16 is driving clock pin of 2 cells. This could lead to large hold time violations. Involved cells are: ptop/cv32e40s_core_i/cs_registers_i/privlvl_user.priv_lvl_i/gen_hardened.gen_csr_hardened[0].gen_unmasked_hardened.gen_rv1.sffs_rdatareg/q_o_reg, and ptop/cv32e40s_core_i/cs_registers_i/privlvl_user.priv_lvl_i/gen_hardened.gen_csr_hardened[1].gen_unmasked_hardened.gen_rv1.sffs_rdatareg/q_o_reg WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__8 is driving clock pin of 12 cells. This could lead to large hold time violations. Involved cells are: ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[0].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[10].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[1].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[2].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[31].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[3].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[4].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[5].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[6].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[7].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[8].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, and ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mcause_csr_i/gen_hardened.gen_csr_hardened[9].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT ptop/cv32e40s_core_i/sleep_unit_i/core_clock_gate_i/q_o_i_2__9 is driving clock pin of 26 cells. This could lead to large hold time violations. Involved cells are: ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[0].gen_unmasked_hardened.gen_rv1.sffs_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[10].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[11].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[12].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[13].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[14].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[15].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[16].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[17].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[18].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[19].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[20].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[21].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[22].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg, ptop/cv32e40s_core_i/cs_registers_i/basic_mode_csrs.mtvec_csr_i/gen_hardened.gen_csr_hardened[23].gen_unmasked_hardened.gen_rv0.sffr_rdatareg/q_o_reg... and (the first 15 of 26 listed) INFO: [Vivado 12-3199] DRC finished with 0 Errors, 30 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./digilent_arty_a7_100t.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-83] Releasing license: Implementation 9 Infos, 30 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:15 . Memory (MB): peak = 3196.871 ; gain = 241.066 ; free physical = 2784 ; free virtual = 25499 # exit INFO: [Common 17-206] Exiting Vivado at Sun Apr 12 00:32:04 2026... [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash digilent_arty_a7_100t) [Pipeline] dir Running in /var/jenkins_home/workspace/cv32e40s/cv32e40s [Pipeline] { [Pipeline] echo Flashing FPGA digilent_arty_a7_100t. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p cv32e40s -b digilent_arty_a7_100t -l Makefile executed successfully. Makefile output: Flashing the FPGA... /eda/oss-cad-suite/bin/openFPGALoader -b arty_a7_100t digilent_arty_a7_100t.bit empty Jtag frequency : requested 10.00MHz -> real 10.00MHz Open file DONE Parse file DONE load program Load SRAM: [================ ] 31.00% Load SRAM: [================================ ] 63.00% Load SRAM: [================================================ ] 95.00% Load SRAM: [===================================================] 100.00% Done Shift IR 35 ir: 1 isc_done 1 isc_ena 0 init 1 done 1 [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test digilent_arty_a7_100t) [Pipeline] echo Testing FPGA digilent_arty_a7_100t. [Pipeline] sh + echo Test for FPGA in /dev/ttyUSB1 Test for FPGA in /dev/ttyUSB1 [Pipeline] sh + python3 /eda/processor_ci_tests/main.py -b 115200 -s 2 -c /eda/processor_ci_tests/config.json --p /dev/ttyUSB1 -m rv32i -k 0x41525459 -ctm 32 Connected to FPGA with ID: b'ARTY' Checking for sync keyword... Sync keyword matched. Testsuite configurated. Running tests: RV32I in /eda/processor_ci_tests/tests/RV32I Running basic tests in /eda/processor_ci_tests/tests/RV32I/basic, with breakpoint 60 Running test: 000-addi.hex Running test: 001-sw.hex Running test: 002-slti.hex Running test: 003-sltiu.hex Running test: 004-xori.hex Running test: 005-ori.hex Running test: 006-andi.hex Running test: 007-slli.hex Running test: 008-srli.hex Running test: 009-srai.hex Running test: 010-lui.hex Running test: 011-auipc.hex Running test: 012-jal.hex Running test: 013-jalr.hex Running test: 014-beq.hex Running test: 015-bne.hex Running test: 016-blt.hex Running test: 017-bge.hex Running test: 018-bltu.hex Running test: 019-bgeu.hex Running test: 020-lb.hex Running test: 021-lh.hex Running test: 022-lw.hex Running test: 023-lbu.hex Running test: 024-lhu.hex Running test: 025-sb.hex Running test: 026-sh.hex Running test: 027-add.hex Running test: 028-sub.hex Running test: 029-sll.hex Running test: 030-slt.hex Running test: 031-sltu.hex Running test: 032-xor.hex Running test: 033-srl.hex Running test: 034-sra.hex Running test: 035-or.hex Running test: 036-and.hex Running test: 037-fence.hex Running test: 038-ecall.hex Running test: 039-ebreak.hex Running test: 040-timeout.hex Running test: 041-forwarding.hex Running test: 042-forwarding-lw.hex JUnit XML report generated: test_results_1775968336.4541771.xml All tests finished. [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: digilent_arty_a7_100t] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Declarative: Post Actions) [Pipeline] junit Recording test results [Checks API] No suitable checks publisher found. [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline Finished: UNSTABLE