read_verilog -sv /eda/processor_ci/rtl/cva5.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/memory_sub_units/avalon_master.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/memory_sub_units/axi_master.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/memory_sub_units/local_mem_sub_unit.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/memory_sub_units/wishbone_master.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/types_and_interfaces/csr_types.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/types_and_interfaces/cva5_config.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/types_and_interfaces/cva5_types.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/types_and_interfaces/external_interfaces.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/types_and_interfaces/fpu_types.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/types_and_interfaces/internal_interfaces.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/types_and_interfaces/opcodes.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/types_and_interfaces/riscv_types.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/decode_and_issue.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/fp_writeback.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/instruction_metadata_and_id_management.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/l1_arbiter.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/mmu.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/register_file.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/register_free_list.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/renamer.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/tlb_lut_ram.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/writeback.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/common_components/byte_en_bram.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/common_components/clz.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/common_components/cva5_fifo.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/common_components/cycler.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/common_components/dual_port_bram.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/common_components/lfsr.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/common_components/lutram_1w_1r.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/common_components/lutram_1w_mr.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/common_components/one_hot_to_integer.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/common_components/priority_encoder.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/common_components/set_clr_reg_with_rst.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/common_components/toggle_memory.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/common_components/toggle_memory_set.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/common_components/vendor_support/intel/intel_byte_enable_ram.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/common_components/vendor_support/xilinx/cva5_wrapper_xilinx.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/common_components/vendor_support/xilinx/xilinx_byte_enable_ram.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/alu_unit.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/barrel_shifter.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/branch_comparator.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/branch_unit.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/csr_unit.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/custom_unit.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/div_core.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/div_unit.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/gc_unit.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/mul_unit.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/fp_unit/fp_add.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/fp_unit/fp_div.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/fp_unit/fp_div_sqrt_wrapper.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/fp_unit/fp_madd_wrapper.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/fp_unit/fp_mul.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/fp_unit/fp_normalize_rounding_top.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/fp_unit/fp_prenormalize.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/fp_unit/fp_preprocessing.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/fp_unit/fp_roundup.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/fp_unit/fp_rs_preprocess.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/fp_unit/fp_special_case_detection.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/fp_unit/fp_sqrt.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/fp_unit/fp_sqrt_core.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/fp_unit/fp_sticky_tracking.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/fp_unit/fp_wb2fp_misc.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/fp_unit/fp_wb2int_misc.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/fp_unit/fpu_top.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/fp_unit/divider/carry_save_shift.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/fp_unit/divider/fp_div_core.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/fp_unit/divider/on_the_fly.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/fp_unit/divider/q_lookup.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/load_store_unit/addr_hash.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/load_store_unit/amo_alu.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/load_store_unit/dcache.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/load_store_unit/dcache_tag_banks.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/load_store_unit/load_store_queue.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/load_store_unit/load_store_unit.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/execution_units/load_store_unit/store_queue.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/fetch_stage/branch_predictor.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/fetch_stage/fetch.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/fetch_stage/icache.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/fetch_stage/icache_tag_banks.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/fetch_stage/ras.sv
read_verilog -sv /var/jenkins_home/workspace/cva5/cva5/core/cva5.sv
read_verilog -sv /eda/processor-ci-controller/modules/uart.sv
read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v

#read_verilog -sv /eda/processor-ci-controller/modules/spi.sv;
#read_verilog -sv /eda/processor-ci-controller/modules/SPI-Slave/rtl/spi_slave.sv;

read_verilog -sv /eda/processor_ci/internal/ahblite_to_wishbone.sv
read_verilog -sv /eda/processor_ci/internal/axi4_to_wishbone.sv
read_verilog -sv /eda/processor_ci/internal/axi4lite_to_wishbone.sv
read_verilog -sv /eda/processor-ci-controller/rtl/fifo.sv
read_verilog -sv /eda/processor-ci-controller/rtl/reset.sv
read_verilog -sv /eda/processor-ci-controller/rtl/clk_divider.sv
read_verilog -sv /eda/processor-ci-controller/rtl/memory.sv
read_verilog -sv /eda/processor-ci-controller/rtl/interpreter.sv
read_verilog -sv /eda/processor-ci-controller/rtl/controller.sv
read_verilog -sv /eda/processor-ci-controller/rtl/timer.sv
read_verilog -sv /eda/processor_ci/internal/fpga_top.sv

set_param general.maxThreads 16

read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc"
set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]

# synth
synth_design -top "fpga_top" -part "xc7a100tcsg324-1"

# place and route
opt_design
place_design

report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt
report_utilization               -file digilent_arty_a7_utilization_place.rpt
report_io                        -file digilent_arty_a7_io.rpt
report_control_sets -verbose     -file digilent_arty_a7_control_sets.rpt
report_clock_utilization         -file digilent_arty_a7_clock_utilization.rpt


route_design

report_timing_summary -no_header -no_detailed_paths
report_route_status                            -file digilent_arty_a7_route_status.rpt
report_drc                                     -file digilent_arty_a7_drc.rpt
report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt
report_power                                   -file digilent_arty_a7_power.rpt


# write bitstream
write_bitstream -force "digilent_arty_a7_100t.bit"

exit