# CSR access test
# Generated by gen_csr_test.py (part of riscv-dv)
# Manual edits to fit with BSP and enhance debug
#include "corev_uvmt.h"
.include "user_define.h"
.section .text.start
.globl _start
.section .text
#.include "user_init.s"
.type _start, @function

_start:
    j _start_main

.globl _start_main
.section .text
_start_main:

	#define EXP_MISA 0x40001104

###############################################################################
# Generated code starts...
###############################################################################
_start0:
	# mcycle
	li x7, 0xa5a5a5a5
	csrrw x12, 2816, x7
	li x7, 0x00000000
	bne x7, x12, csr_fail
	li x7, 0x5a5a5a5a
	csrrw x12, 2816, x7
	li x7, 0xa5a5a5a5
	bne x7, x12, csr_fail
	li x7, 0xd5583a6b
	csrrw x12, 2816, x7
	li x7, 0x5a5a5a5a
	bne x7, x12, csr_fail
	li x7, 0xa5a5a5a5
	csrrs x12, 2816, x7
	li x7, 0xd5583a6b
	bne x7, x12, csr_fail
	li x7, 0x5a5a5a5a
	csrrs x12, 2816, x7
	li x7, 0xf5fdbfef
	bne x7, x12, csr_fail
	li x7, 0x1ac809f1
	csrrs x12, 2816, x7
	li x7, 0xffffffff
	bne x7, x12, csr_fail
	li x7, 0xa5a5a5a5
	csrrc x12, 2816, x7
	li x7, 0xffffffff
	bne x7, x12, csr_fail
	li x7, 0x5a5a5a5a
	csrrc x12, 2816, x7
	li x7, 0x5a5a5a5a
	bne x7, x12, csr_fail
	li x7, 0xe34ffa80
	csrrc x12, 2816, x7
	li x7, 0x00000000
	bne x7, x12, csr_fail
	csrrwi x12, 2816, 0b00101
	li x7, 0x00000000
	bne x7, x12, csr_fail
	csrrwi x12, 2816, 0b11010
	li x7, 0x00000005
	bne x7, x12, csr_fail
	csrrwi x12, 2816, 0b01111
	li x7, 0x0000001a
	bne x7, x12, csr_fail
	csrrsi x12, 2816, 0b00101
	li x7, 0x0000000f
	bne x7, x12, csr_fail
	csrrsi x12, 2816, 0b11010
	li x7, 0x0000000f
	bne x7, x12, csr_fail
	csrrsi x12, 2816, 0b01100
	li x7, 0x0000001f
	bne x7, x12, csr_fail
	csrrci x12, 2816, 0b00101
	li x7, 0x0000001f
	bne x7, x12, csr_fail
	csrrci x12, 2816, 0b11010
	li x7, 0x0000001a
	bne x7, x12, csr_fail
	csrrci x12, 2816, 0b11001
	li x7, 0x00000000
	bne x7, x12, csr_fail

################################################################################
# Generated code ends...
################################################################################
# Hit those coverage holes with manually generated code...
################################################################################

  # Various rd/rs holes, especially rs1==x0
  li  x1, 0xFFFFFFFF
  add x2, x0, x4         # hole: rs1==x0
  add x2, x0, x1
  and x2, x25, x26       # hole: rs1==x25

  lw  x2, 0(x0)          # hole: load/store with rs1==x0
  lw  x3, 4(x0)
  add x2, x0, x3
  sw  x2, 0(x0)
  lw  x1, 0(x0)          # hole: load/store with rs1==x0
  bne x2, x1, csr_fail

  li  x1, 0xFFFFFFFF
  li  x2, 0xFFFFFFFF
  li  x3, 0xFFFFFFFF
  lb  x2, 0(x0)          # hole: load/store with rs1==x0
  lb  x3, 4(x0)
  add x2, x0, x3
  sb  x2, 0(x0)
  lb  x1, 0(x0)          # hole: load/store with rs1==x0
  bne x2, x1, csr_fail

  li  x1, 0xFFFFFFFF
  li  x2, 0xFFFFFFFF
  li  x3, 0xFFFFFFFF
  lbu x2, 0(x0)          # hole: load/store with rs1==x0
  lbu x3, 4(x0)
  add x2, x0, x3
  sb  x2, 0(x0)
  lbu x1, 0(x0)          # hole: load/store with rs1==x0
  bne x2, x1, csr_fail

  li  x1, 0xFFFFFFFF
  li  x2, 0xFFFFFFFF
  li  x3, 0xFFFFFFFF
  lh  x2, 0(x0)          # hole: load/store with rs1==x0
  lh  x3, 4(x0)
  add x2, x0, x3
  sh  x2, 0(x0)
  lh  x1, 0(x0)          # hole: load/store with rs1==x0
  bne x2, x1, csr_fail

  li  x1, 0xFFFFFFFF
  li  x2, 0xFFFFFFFF
  li  x3, 0xFFFFFFFF
  lhu x2, 0(x0)          # hole: load/store with rs1==x0
  lhu x3, 4(x0)
  add x2, x0, x3
  sh  x2, 0(x0)
  lhu x1, 0(x0)          # hole: load/store with rs1==x0
  bne x2, x1, csr_fail

  lw  x3, 4(x0)
  add x3, x0, x4         # hole: rs1==x0
  sw  x2, 0(x0)
  sw  x2, 4(x0)

  # cross coverage with c.jal
  # TODO: how to handle EBREAK, ECALL, WFI, MRET, DRET, C_EBREAK
crosses:
  add x3, x2, x1
  c.jal next1
next1:
  addi x3, x2, 1
  c.jal next2
next2:
  and x3, x2, x1
  c.jal next3
next3:
  andi x3, x2, 1
  c.jal next4
next4:
  auipc x3, 1
  c.jal next5
next5:
  li x1, 1
  li x2, 2
  beq x1, x2, crosses
  c.jal next6
next6:
  bge x2, x1, crosses
  c.jal next7
next7:
  bgeu x2, x1, crosses
  c.jal next8
next8:
  blt x1, x2, crosses
  c.jal next9
next9:
  bltu x1, x2, crosses
  c.jal next10
next10:
  li  x1, 1
  li  x2, 1
  bne x1, x2, crosses
  c.jal next11
next11:
  fence
  c.jal next12
next12:
  fence.i
  c.jal next13
next13:
  jal next14
next14:
  c.jal next14.1 # whoops!
next14.1:
  lla x2, next15
  jalr x2
next15:
  c.jal next16
next16:
  lb x2, 2(x0)
  c.jal next17
next17:
  lbu x2, 2(x0)
  c.jal next18
next18:
  lhu x2, 2(x0)
  c.jal next19
next19:
  lh x2, 2(x0)
  c.jal next20
next20:
  lui x2, 5
  c.jal next21
next21:
  lw  x2, 2(x0)
  c.jal next22
next22:
  or  x2, x3, x4
  c.jal next23
next23:
  ori  x2, x3, 5
  c.jal next24
next24:
  sb   x2, 2(x0)
  c.jal next25
next25:
  sh   x2, 2(x0)
  c.jal next26
next26:
  sll  x2, x3, x4
  c.jal next27
next27:
  slli x2, x3, 5
  c.jal next28
next28:
  slt   x2, x3, x4
  c.jal next29
next29:
  slti  x2, x3, 4
  c.jal next30
next30:
  sltiu x2, x3, 4
  c.jal next31
next31:
  sltu  x2, x3, x4
  c.jal next32
next32:
  sra   x2, x3, x4
  c.jal next33
next33:
  srai  x2, x3, 4
  c.jal next34
next34:
  srl  x2, x3, x4
  c.jal next35
next35:
  srli x2, x3, 4
  c.jal next36
next36:
  sub  x2, x3, x4
  c.jal next37
next37:
  sw   x2, 2(x0)
  c.jal next38
next38:
  xor  x2, x3, x4
  c.jal next39
next39:
  xori x2, x3, 4
  c.jal next40
next40:
  mul    x2, x3, x4
  c.jal next41
next41:
  mulh   x2, x3, x4
  c.jal next42
next42:
  mulhu  x2, x3, x4
  c.jal next43
next43:
  mulhsu x2, x3, x4
  c.jal next44
next44:
  div   x2, x3, x4
  c.jal next45
next45:
  rem   x2, x3, x4
  c.jal next46
next46:
  divu  x2, x3, x4
  c.jal next47
next47:
  remu  x2, x3, x4
  c.jal next48
next48:
  csrrw x7, 0x340, x12 #mscratch
  c.jal next49
next49:
  csrrc x7, 0x340, x12
  c.jal next50
next50:
  csrrs x7, 0x340, x12
  c.jal next51
next51:
  csrrwi x7, 0x340, 12 #mscratch
  c.jal next52
next52:
  csrrci x7, 0x340, 12
  c.jal next53
next53:
  csrrsi x7, 0x340, 12
  c.jal next54
next54:
  c.lwsp x4, 0(x2)
  c.jal next55
next55:
  c.swsp x4, 0(x2)
  c.jal next56
next56:
  c.lw   a2, 8(a0)
  c.jal next57
next57:
  c.sw   a2, 8(a0)
  c.jal next58
next58:
  li  a2, 1
  li  a4, 0
  c.beqz a2, crosses
  c.jal next59
next59:
  c.bnez a4, crosses
  c.jal next60
next60:
  c.j next61
next61:
  c.jal next62
next62:
  lla x2, next63
  c.jr x2
next63:
  c.jal next64
next64:
  c.jal next65
next65:
  lla x2, next66
  c.jalr x2
next66:
  c.jal next67
next67:
  c.li x2, 0
  c.jal next68
next68:
  c.lui x4, 2
  c.jal next69
next69:
  c.addi      x2, 0
  c.jal next70
next70:
  c.addi16sp  sp, -16
  c.jal next71
next71:
  c.addi4spn  a2, sp,  4
  c.jal next72
next72:
  c.mv        x4, x3
  c.jal next73
next73:
  c.slli  x2, 2
  c.jal next74
next74:
  c.srli  a2, 2
  c.jal next75
next75:
  c.srai  a2, 2
  c.jal next76
next76:
  c.andi  a2, 4
  c.jal next77
next77:
  c.add   x2, x4
  c.jal next78
next78:
  c.and a2, a4
  c.jal next79
next79:
  c.or  a2, a4
  c.jal next80
next80:
  c.xor a2, a4
  c.jal next81
next81:
  c.sub a2, a4
  c.jal next82
next82:

  # negative branch
  li x1, 0xFFFFFFFF
holes:
  beq x0, x1, test_lui0
  li x1, 0x00000000
  srli x2, x0, 0b000100  # hole: rd is never x2
  beq x0, x7, holes      # hole: negative branch
  li x4, 0x00000002
  jalr    x0, x4, 0      # jump to the second nop
  nop
  nop
  nop

test_lui0:
  #first, load gprs with non-zero values
  lui x0,  0x0FFFF
  lui x1,  0xF0FFF
  lui x2,  0xFF0FF
  lui x3,  0xFFF0F
  lui x4,  0xFFFF0
  lui x5,  0xFFF0F
  lui x6,  0xFF0FF
  lui x7,  0xF0FFF
  lui x8,  0x0FFFF
  lui x9,  0xF0FFF
  lui x10, 0xFF0FF
  lui x11, 0xFFF0F
  lui x12, 0xFFFF0
  lui x13, 0xFFF0F
  lui x14, 0xFF0FF
  lui x15, 0xF0FFF
  lui x16, 0x0FFFF
  lui x17, 0xF0FFF
  lui x18, 0xFF0FF
  lui x19, 0xFFFFF
  lui x20, 0xFFF0F
  lui x21, 0xFFFF0
  lui x22, 0xFFF0F
  lui x23, 0xFF0FF
  lui x24, 0xF0FFF
  lui x25, 0x0FFFF
  lui x26, 0xF0FFF
  lui x27, 0xFF0FF
  lui x28, 0xFFF0F
  lui x29, 0xFFFF0
  lui x30, 0xFFF0F
  lui x31, 0xFF0FF

  # The infamous load-unsigned-immediate with imm==0
  lui x0,  0
  addi x0, x0, 0
  bne x0, x0, test_fail
  lui x1,  0
  bne x1, x0, test_fail
  lui x2,  0
  bne x2, x0, test_fail
  lui x3,  0
  bne x3, x0, test_fail
  lui x4,  0
  bne x4, x0, test_fail
  lui x5,  0
  bne x5, x0, test_fail
  lui x6,  0
  bne x6, x0, test_fail
  lui x7,  0
  bne x7, x0, test_fail
  lui x8,  0
  bne x8, x0, test_fail
  lui x9,  0
  bne x9, x0, test_fail
  lui x10, 0
  bne x10, x0, test_fail
  lui x11, 0
  bne x0, x11, test_fail
  lui x12, 0
  bne x0, x12, test_fail
  lui x13, 0
  bne x0, x13, test_fail
  lui x14, 0
  bne x0, x14, test_fail
  lui x15, 0
  bne x0, x15, test_fail
  lui x16, 0
  bne x0, x16, test_fail
  lui x17, 0
  bne x0, x17, test_fail
  lui x18, 0
  bne x0, x18, test_fail
  lui x19, 0
  bne x0, x19, test_fail
  lui x20, 0
  bne x0, x20, test_fail
  lui x21, 0
  bne x21, x0, test_fail
  lui x22, 0
  bne x0, x22, test_fail
  lui x23, 0
  bne x23, x0, test_fail
  lui x24, 0
  bne x0, x24, test_fail
  lui x25, 0
  bne x25, x0, test_fail
  lui x26, 0
  bne x0, x26, test_fail
  lui x27, 0
  bne x27, x0, test_fail
  lui x28, 6
  beq x0, x28, test_fail # just to see if you're paying attention
  lui x29, 0
  bne x29, x0, test_fail
  lui x30, 0
  bne x0, x30, test_fail
  lui x31, 0
  bne x31, x0, test_fail
  lui x28, 0
  bne x0, x28, test_fail # we skipped lui x28, 0

test_done:
    lui a0,print_port>>12
    addi a1,zero,'\n'
    sw a1,0(a0)
    addi a1,zero,'C'
    sw a1,0(a0)
    addi a1,zero,'V'
    sw a1,0(a0)
    addi a1,zero,'3'
    sw a1,0(a0)
    addi a1,zero,'2'
    sw a1,0(a0)
    addi a1,zero,' '
    sw a1,0(a0)
    addi a1,zero,'D'
    sw a1,0(a0)
    addi a1,zero,'O'
    sw a1,0(a0)
    addi a1,zero,'N'
    sw a1,0(a0)
    addi a1,zero,'E'
    sw a1,0(a0)
    addi a1,zero,'\n'
    sw a1,0(a0)
    sw a1,0(a0)

csr_pass:
    li x18, 123456789
    li x17, CV_VP_STATUS_FLAGS_BASE
    sw x18,0(x17)
    wfi

csr_fail:
test_fail:
    lui a0,print_port>>12
    addi a1,zero,'\n'
    sw a1,0(a0)
    addi a1,zero,'C'
    sw a1,0(a0)
    addi a1,zero,'V'
    sw a1,0(a0)
    addi a1,zero,'3'
    sw a1,0(a0)
    addi a1,zero,'2'
    sw a1,0(a0)
    addi a1,zero,' '
    sw a1,0(a0)
    addi a1,zero,'F'
    sw a1,0(a0)
    addi a1,zero,'A'
    sw a1,0(a0)
    addi a1,zero,'I'
    sw a1,0(a0)
    addi a1,zero,'L'
    sw a1,0(a0)
    addi a1,zero,'\n'
    sw a1,0(a0)
    sw a1,0(a0)

    li x18, 1
    li x17, CV_VP_STATUS_FLAGS_BASE
    sw x18,0(x17)
    wfi
#
# end
#
