//## 2.3 Immediate Encoding Variants
//### Figure 2.3
//RISC-V base instruction formats showing immediate variants.

[wavedrom, ,svg]
....
{reg: [
  {bits: 7,  name: 'opcode'},
  {bits: 5,  name: 'rd'},
  {bits: 3,  name: 'funct3'},
  {bits: 5,  name: 'rs1'},
  {bits: 5,  name: 'rs2'},
  {bits: 7,  name: 'funct7'}
], config: {label: {right: 'R-Type'}}}
....

[wavedrom, ,svg]
....
{reg: [
  {bits: 7,  name: 'opcode'},
  {bits: 5,  name: 'rd'},
  {bits: 3,  name: 'funct3'},
  {bits: 5,  name: 'rs1'},
  {bits: 12, name: 'imm[11:0]'},
], config: {label: {right: 'I-Type'}}}
....

[wavedrom, ,svg]
....
{reg: [
  {bits: 7,  name: 'opcode'},
  {bits: 5,  name: 'imm[4:0]'},
  {bits: 3,  name: 'funct3'},
  {bits: 5,  name: 'rs1'},
  {bits: 5,  name: 'rs2'},
  {bits: 7,  name: 'imm[11:5]'}
], config: {label: {right: 'S-Type'}}}
....

[wavedrom, ,svg]
....
{reg: [
  {bits: 7,  name: 'opcode'},
  {bits: 1,  name: '[11]'},
  {bits: 4,  name: 'imm[4:1]'},
  {bits: 3,  name: 'funct3'},
  {bits: 5,  name: 'rs1'},
  {bits: 5,  name: 'rs2'},
  {bits: 6,  name: 'imm[10:5]'},
  {bits: 1,  name: '[12]'}
], config: {fontsize: 12, label: {right: 'B-Type'}}}
....

[wavedrom, ,svg]
....
{reg: [
  {bits: 7,  name: 'opcode'},
  {bits: 5,  name: 'rd'},
  {bits: 20, name: 'imm[31:12]'}
], config: {label: {right: 'U-Type'}}}
....

[wavedrom, ,svg]
....
{reg: [
  {bits: 7,  name: 'opcode'},
  {bits: 5,  name: 'rd'},
  {bits: 8,  name: 'imm[19:12]'},
  {bits: 1,  name: '[11]'},
  {bits: 10, name: 'imm[10:1]'},
  {bits: 1,  name: '[20]'}
], config: {fontsize: 12, label: {right: 'J-Type'}}}
....


