component:
  '@xmlns:ipxact': http://www.accellera.org/XMLSchema/IPXACT/1685-2014
  vendor: OpenHW
  library: cva6
  name: CV32A6_CSR
  version: CV32A60X
  busInterfaces:
    busInterface:
      name: Other
      busType:
        '@library': cv32a6
        '@name': cva6
        '@vendor': OpenHW
        '@version': '1.0'
      abstractionTypes:
        abstractionType:
          abstractionRef:
            '@library': cv32a6
            '@name': cva6
            '@vendor': OpenHW
            '@version': '1.0'
      slave:
        memoryMapRef:
          '@memoryMapRef': Other
      bitsInLau: '32'
  memoryMaps:
    memoryMap:
      name: Other
      addressBlock:
        name: address_block
        baseAddress: "'h0"
        range: "'h4000"
        width: '32'
        usage: register
        register:
        - name: fflags
          displayName: Floating-Point Accrued Exceptions
          description: The fields within the ``fcsr`` can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field ``frm`` and copies it into the least-significant three bits of integer register *rd*, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register *rd*, and then writing a new value obtained from the three least-significant bits of integer register *rs1* into ``frm``. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field ``fflags``.
          addressOffset: "'h1"
          size: '32'
          access: read-write
          field:
          - name: NV
            displayName: Invalid Operation
            description: The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
            bitOffset: '4'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: DZ
            displayName: Divide by Zero
            description: The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
            bitOffset: '3'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: OF
            displayName: Overflow
            description: The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
            bitOffset: '2'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: UF
            displayName: Underflow
            description: The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
            bitOffset: '1'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: NX
            displayName: Inexact
            description: The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          vendorExtensions:
            privilege_mode: U
        - name: frm
          displayName: Floating-Point Dynamic Rounding Mode
          description: The fields within the ``fcsr`` can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field ``frm`` and copies it into the least-significant three bits of integer register *rd*, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register *rd*, and then writing a new value obtained from the three least-significant bits of integer register *rs1* into ``frm``. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field ``fflags``.
          addressOffset: "'h2"
          size: '32'
          access: read-write
          field:
            name: FRM
            displayName: Floating-Point Rounding Mode
            description: "Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in ``frm``. Rounding modes are encoded as shown in the enumerated value. A value of 111 in\nthe instruction’s *rm* field selects the dynamic rounding mode held in ``frm``. If ``frm`` is set to an invalid value (101–111), any subsequent attempt to execute a floating-point operation with a dynamic rounding mode will raise an illegal instruction exception. Some instructions, including widening conversions, have the *rm* field but are nevertheless unaffected by the rounding mode; software should set their *rm* field to RNE (000)."
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0x7'
            bitWidth: '3'
            access: read-write
            enumeratedValues:
              enumeratedValue:
              - '@usage': read-write
                name: RNE
                description: Round to Nearest, ties to Even
                value: '0'
              - '@usage': read-write
                name: RTZ
                description: Round towards Zero
                value: '1'
              - '@usage': read-write
                name: RDN
                description: Round Down
                value: '2'
              - '@usage': read-write
                name: RUP
                description: Round Up
                value: '3'
              - '@usage': read-write
                name: RMM
                description: Round to Nearest, ties to Max Magnitude
                value: '4'
              - '@usage': read-write
                name: INVALID_5
                description: '*Reserved for future use.*'
                value: '5'
              - '@usage': read-write
                name: INVALID_6
                description: '*Reserved for future use.*'
                value: '6'
              - '@usage': read-write
                name: DYN
                description: "In instruction’s *rm* field, selects dynamic rounding mode;\nIn Rounding Mode register, *Invalid*."
                value: '7'
          vendorExtensions:
            privilege_mode: U
        - name: fcsr
          displayName: Floating-Point Control and Status Register
          description: "The floating-point control and status register, ``fcsr``, is a RISC-V control and status register (CSR). It is a read/write register that selects the dynamic rounding mode for floating-point arithmetic operations and holds the accrued exception flags.\n\nThe ``fcsr`` register can be read and written with the FRCSR and FSCSR instructions, which are assembler pseudoinstructions built on the underlying CSR access instructions. FRCSR reads ``fcsr`` by copying it into integer register *rd*. FSCSR swaps the value in ``fcsr`` by copying the original value into integer register *rd*, and then writing a new value obtained from integer register *rs1* into ``fcsr``.\n\nThe fields within the ``fcsr`` can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field ``frm`` and copies it into the least-significant three bits of integer register *rd*, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register *rd*, and then writing a new value obtained from the three least-significant bits of integer register *rs1* into ``frm``. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field ``fflags``."
          addressOffset: "'h3"
          size: '32'
          access: read-write
          field:
          - name: FRM
            displayName: Floating-Point Rounding Mode
            description: "Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in ``frm``. Rounding modes are encoded as shown in the enumerated value. A value of 111 in\nthe instruction’s *rm* field selects the dynamic rounding mode held in ``frm``. If ``frm`` is set to an invalid value (101–111), any subsequent attempt to execute a floating-point operation with a dynamic rounding mode will raise an illegal instruction exception. Some instructions, including widening conversions, have the *rm* field but are nevertheless unaffected by the rounding mode; software should set their *rm* field to RNE (000)."
            bitOffset: '5'
            resets:
              reset:
                value: '0x0'
                mask: '0x7'
            bitWidth: '3'
            access: read-write
            enumeratedValues:
              enumeratedValue:
              - '@usage': read-write
                name: RNE
                description: Round to Nearest, ties to Even
                value: '0'
              - '@usage': read-write
                name: RTZ
                description: Round towards Zero
                value: '1'
              - '@usage': read-write
                name: RDN
                description: Round Down
                value: '2'
              - '@usage': read-write
                name: RUP
                description: Round Up
                value: '3'
              - '@usage': read-write
                name: RMM
                description: Round to Nearest, ties to Max Magnitude
                value: '4'
              - '@usage': read-write
                name: INVALID_5
                description: '*Reserved for future use.*'
                value: '5'
              - '@usage': read-write
                name: INVALID_6
                description: '*Reserved for future use.*'
                value: '6'
              - '@usage': read-write
                name: DYN
                description: "In instruction’s *rm* field, selects dynamic rounding mode;\nIn Rounding Mode register, *Invalid*."
                value: '7'
          - name: NV
            displayName: Invalid Operation
            description: The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
            bitOffset: '4'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: DZ
            displayName: Divide by Zero
            description: The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
            bitOffset: '3'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: OF
            displayName: Overflow
            description: The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
            bitOffset: '2'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: UF
            displayName: Underflow
            description: The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
            bitOffset: '1'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: NX
            displayName: Inexact
            description: The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          vendorExtensions:
            privilege_mode: U
        - name: sstatus
          displayName: Supervisor Status
          description: "The ``sstatus`` register keeps track of the processor’s current operating state.\n\nThe ``sstatus`` register is a subset of the ``mstatus`` register."
          addressOffset: "'h100"
          size: '32'
          volatile: 'true'
          access: read-write
          field:
          - name: SD
            displayName: State Dirty
            description: The SD bit is a read-only bit that summarizes whether either the FS, VS, or XS fields signal the presence of some dirty state that will require saving extended user context to memory. If FS, XS, and VS are all read-only zero, then SD is also always zero.
            bitOffset: '31'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            volatile: 'true'
            access: read-only
          - name: MXR
            displayName: Make eXecutable Readable
            description: The MXR bit modifies the privilege with which loads access virtual memory. When MXR=0, only loads from pages marked readable will succeed. When MXR=1, loads from pages marked either readable or executable (R=1 or X=1) will succeed. MXR has no effect when page-based virtual memory is not in effect.
            bitOffset: '19'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: SUM
            displayName: Supervisor User Memory
            description: The SUM (permit Supervisor User Memory access) bit modifies the privilege with which S-mode loads and stores access virtual memory. When SUM=0, S-mode memory accesses to pages that are accessible by U-mode will fault. When SUM=1, these accesses are permitted. SUM has no effect when page-based virtual memory is not in effect. Note that, while SUM is ordinarily ignored when not executing in S-mode, it *is* in effect when MPRV=1 and MPP=S. SUM is read-only 0 if S-mode is not supported or if ``satp``.MODE is read-only 0.
            bitOffset: '18'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: XS
            displayName: Extension State
            description: "The XS field is used to reduce the cost of context save and restore by setting and tracking the current state of the user-mode extensions. The XS field encodes the status of the additional user-mode extensions and associated state.\n\nThis field can be checked by a context switch routine to quickly determine whether a state save or restore is required. If a save or restore is required, additional instructions and CSRs are typically required to effect and optimize the process."
            bitOffset: '15'
            resets:
              reset:
                value: '0x0'
                mask: '0x3'
            bitWidth: '2'
            volatile: 'true'
            access: read-only
            enumeratedValues:
              enumeratedValue:
              - '@usage': read
                name: Off
                description: All off
                value: '0'
              - '@usage': read
                name: Initial
                description: None dirty or clean, some on
                value: '1'
              - '@usage': read
                name: Clean
                description: None dirty, some clean
                value: '2'
              - '@usage': read
                name: Dirty
                description: Some dirty
                value: '3'
          - name: FS
            displayName: Floating-point unit State
            description: "The FS field is used to reduce the cost of context save and restore by setting and tracking the current state of the floating-point unit. The FS field encodes the status of the floating-point unit state, including the floating-point registers ``f0–f31`` and the CSRs ``fcsr``, ``frm``, and ``fflags``.\n\nThis field can be checked by a context switch routine to quickly determine whether a state save or restore is required. If a save or restore is required, additional instructions and CSRs are typically required to effect and optimize the process."
            bitOffset: '13'
            resets:
              reset:
                value: '0x0'
                mask: '0x3'
            bitWidth: '2'
            access: read-write
            enumeratedValues:
              enumeratedValue:
              - '@usage': read-write
                name: Off
                value: '0'
              - '@usage': read-write
                name: Initial
                value: '1'
              - '@usage': read-write
                name: Clean
                value: '2'
              - '@usage': read-write
                name: Dirty
                value: '3'
            vendorExtensions:
              RISCV_behavior: WARL
          - name: SPP
            displayName: Supervisor mode Prior Privilege
            description: SPP bit indicates the privilege level at which a hart was executing before entering supervisor mode. When a trap is taken, SPP is set to 0 if the trap originated from user mode, or 1 otherwise. When an SRET instruction is executed to return from the trap handler, the privilege level is set to user mode if the SPP bit is 0, or supervisor mode if the SPP bit is 1; SPP is then set to 0.
            bitOffset: '8'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: SPIE
            displayName: Supervisor mode Prior Interrupt Enable
            description: "The SPIE bit indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode. When a trap is taken into supervisor mode, SPIE is set to SIE, and SIE is set to 0. When\nan SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1."
            bitOffset: '5'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: UPIE
            description: When a URET instruction is executed, UIE is set to UPIE, and UPIE is set to 1.
            bitOffset: '4'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: SIE
            displayName: Supervisor mode Interrupt Enable
            description: The SIE bit enables or disables all interrupts in supervisor mode. When SIE is clear, interrupts are not taken while in supervisor mode. When the hart is running in user-mode, the value in SIE is ignored, and supervisor-level interrupts are enabled. The supervisor can disable individual interrupt sources using the ``sie`` CSR.
            bitOffset: '1'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: UIE
            description: The UIE bit enables or disables user-mode interrupts.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          vendorExtensions:
            privilege_mode: S
        - name: sie
          displayName: Supervisor Interrupt Enable
          description: The ``sie`` is the register containing supervisor interrupt enable bits.
          addressOffset: "'h104"
          size: '32'
          access: read-write
          field:
          - name: Reserved_10
            displayName: Reserved
            description: Reserved.``Legal Values:``0.
            bitOffset: '10'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '5'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: SEIE
            displayName: Supervisor-level External Interrupt Enable
            description: SEIE is the interrupt-enable bit for supervisor-level external interrupts.
            bitOffset: '9'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: UEIE
            description: User-level external interrupts are disabled when the UEIE bit in the sie register is clear.``Legal Values:``0.
            bitOffset: '8'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: Reserved_6
            displayName: Reserved
            description: Reserved.``Legal Values:``0.
            bitOffset: '6'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '2'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: STIE
            displayName: Supervisor-level Timer Interrupt Enable
            description: STIE is the interrupt-enable bit for supervisor-level timer interrupts.
            bitOffset: '5'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: UTIE
            description: User-level timer interrupts are disabled when the UTIE bit in the sie register is clear.``Legal Values:``0.
            bitOffset: '4'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: Reserved_2
            displayName: Reserved
            description: Reserved.``Legal Values:``0.
            bitOffset: '2'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '2'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: SSIE
            displayName: Supervisor-level Software Interrupt Enable
            description: SSIE is the interrupt-enable bit for supervisor-level software interrupts.
            bitOffset: '1'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: USIE
            description: User-level software interrupts are disabled when the USIE bit in the sie register is clear.``Legal Values:``0.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          vendorExtensions:
            privilege_mode: S
        - name: stvec
          displayName: Supervisor Trap Vector Base Address
          description: The ``stvec`` register holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE).
          addressOffset: "'h105"
          size: '32'
          access: read-write
          field:
          - name: BASE
            description: 'The BASE field in stvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: when MODE=Direct the address must be 4-byte aligned, and when MODE=Vectored the address must be 256-byte aligned.'
            bitOffset: '2'
            resets:
              reset:
                value: '0x0'
                mask: '0x3fffffff'
            bitWidth: '30'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: MODE
            description: When MODE=Direct, all traps into supervisor mode cause the ``pc`` to be set to the address in the BASE field. When MODE=Vectored, all synchronous exceptions into supervisor mode cause the ``pc`` to be set to the address in the BASE field, whereas interrupts cause the ``pc`` to be set to the address in the BASE field plus four times the interrupt cause number.``Legal Values :``0,1.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0x3'
            bitWidth: '2'
            access: read-write
            enumeratedValues:
              enumeratedValue:
              - '@usage': read-write
                name: Direct
                description: All exceptions set ``pc`` to BASE.
                value: '0'
              - '@usage': read-write
                name: Vectored
                description: Asynchronous interrupts set pc to BASE+4×cause.
                value: '1'
              - '@usage': read-write
                name: Reserved_2
                description: '*Reserved*'
                value: '2'
              - '@usage': read-write
                name: Reserved_3
                description: '*Reserved*'
                value: '3'
            vendorExtensions:
              RISCV_behavior: WARL
          vendorExtensions:
            privilege_mode: S
        - name: scounteren
          displayName: Supervisor Counter Enable
          description: The counter-enable register ``scounteren`` controls the availability of the hardware performance monitoring counters to U-mode.
          addressOffset: "'h106"
          size: '32'
          access: read-write
          field:
          - name: HPMn
            displayName: Hpmcountern
            description: When HPMn is clear, attempts to read the ``hpmcountern`` register while executing in U-mode will cause an illegal instruction exception. When this bit is set, access to the corresponding register is permitted.
            bitOffset: '3'
            resets:
              reset:
                value: '0x0'
                mask: '0x1fffffff'
            bitWidth: '29'
            access: read-write
          - name: IR
            displayName: Instret
            description: When IR is clear, attempts to read the ``instret`` register while executing in U-mode will cause an illegal instruction exception. When this bit is set, access to the corresponding register is permitted.
            bitOffset: '2'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: TM
            displayName: Time
            description: When TM is clear, attempts to read the ``time`` register while executing in U-mode will cause an illegal instruction exception. When this bit is set, access to the corresponding register is permitted.
            bitOffset: '1'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: CY
            displayName: Cycle
            description: When CY is clear, attempts to read the ``cycle`` register while executing in U-mode will cause an illegal instruction exception. When this bit is set, access to the corresponding register is permitted.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          vendorExtensions:
            privilege_mode: S
        - name: sscratch
          displayName: Supervisor Scratch
          description: The ``sscratch`` register is dedicated for use by the supervisor.
          addressOffset: "'h140"
          size: '32'
          access: read-write
          field:
            name: SSCRATCH
            displayName: Supervisor Scratch
            description: Typically, ``sscratch`` is used to hold a pointer to the hart-local supervisor context while the hart is executing user code. At the beginning of a trap handler, ``sscratch`` is swapped with a user register to provide an initial working register.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: S
        - name: sepc
          displayName: Supervisor Exception Program Counter
          description: When a trap is taken into S-mode, ``sepc`` is written with the virtual address of the instruction that was interrupted or that encountered the exception. Otherwise, ``sepc`` is never written by the implementation, though it may be explicitly written by software.
          addressOffset: "'h141"
          size: '32'
          access: read-write
          field:
            name: SEPC
            displayName: Supervisor Exception Program Counter
            description: The low bit of SEPC (SEPC[0]) is always zero. On implementations that support only IALIGN=32, the two low bits (SEPC[1:0]) are always zero.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          vendorExtensions:
            privilege_mode: S
        - name: scause
          displayName: Supervisor Cause
          description: "When a trap is taken into S-mode, ``scause`` is written with a code indicating the event that caused the trap. Otherwise, ``scause`` is never written by the implementation, though it may be explicitly written by software.\n\nSupervisor cause register (``scause``) values after trap are shown in the following table. =========  ==============  ==============================\nInterrupt  Exception Code Description =========  ==============  ==============================\n        1               0  *Reserved*\n        1               1  Supervisor software interrupt\n        1             2-4  *Reserved*\n        1               5  Supervisor timer interrupt\n        1             6-8  *Reserved*\n        1               9  Supervisor external interrupt\n        1           10-15  *Reserved*\n        1             ≥16  *Designated for platform use*\n        0               0  Instruction address misaligned\n        0               1  Instruction access fault\n        0               2  Illegal instruction\n        0               3  Breakpoint\n        0               4  Load address misaligned\n        0               5  Load access fault\n        0               6  Store/AMO address misaligned\n        0               7  Store/AMO access fault\n        0               8  Environment call from U-mode\n        0               9  Environment call from S-mode\n        0           10-11  *Reserved*\n        0              12  Instruction page fault\n        0              13  Load page fault\n        0              14  *Reserved*\n        0              15  Store/AMO page fault\n        0           16-23  *Reserved*\n        0           24-31  *Designated for custom use*\n        0           32-47  *Reserved*\n        0           48-63  *Designated for custom use*\n        0             ≥64 *Reserved* =========  ==============  =============================="
          addressOffset: "'h142"
          size: '32'
          access: read-write
          field:
          - name: Interrupt
            description: The Interrupt bit in the ``scause`` register is set if the trap was caused by an interrupt.
            bitOffset: '31'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: Exception_Code
            displayName: Exception Code
            description: The Exception Code field contains a code identifying the last exception or interrupt.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0x7fffffff'
            bitWidth: '31'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WLRL
          vendorExtensions:
            privilege_mode: S
        - name: stval
          displayName: Supervisor Trap Value
          description: When a trap is taken into S-mode, ``stval`` is written with exception-specific information to assist software in handling the trap. Otherwise, ``stval`` is never written by the implementation, though it may be explicitly written by software. The hardware platform will specify which exceptions must set ``stval`` informatively and which may unconditionally set it to zero.
          addressOffset: "'h143"
          size: '32'
          access: read-write
          field:
            name: STVAL
            displayName: Supervisor Trap Value
            description: "If ``stval`` is written with a nonzero value when a breakpoint, address-misaligned, access-fault, or page-fault exception occurs on an instruction fetch, load, or store, then ``stval`` will contain the faulting virtual address.\n\nIf ``stval`` is written with a nonzero value when a misaligned load or store causes an access-fault or page-fault exception, then ``stval`` will contain the virtual address of the portion of the access that caused the fault.\n\nIf ``stval`` is written with a nonzero value when an instruction access-fault or page-fault exception occurs on a system with variable-length instructions, then ``stval`` will contain the virtual address of the portion of the instruction that caused the fault, while ``sepc`` will point to the beginning of the instruction.\n\nThe ``stval`` register can optionally also be used to return the faulting instruction bits on an illegal instruction exception (``sepc`` points to the faulting instruction in memory). If ``stval`` is written with a nonzero value when an illegal-instruction exception occurs, then ``stval`` will contain the shortest of:\n\n* the actual faulting instruction\n* the first ILEN bits of the faulting instruction\n* the first SXLEN bits of the faulting instruction\n\nThe value loaded into ``stval`` on an illegal-instruction exception is right-justified and all unused upper bits are cleared to zero. For other traps, ``stval`` is set to zero, but a future standard may redefine ``stval’s`` setting for other traps."
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          vendorExtensions:
            privilege_mode: S
        - name: sip
          displayName: Supervisor Interrupt Pending
          description: The ``sip`` register contains information on pending interrupts.
          addressOffset: "'h144"
          size: '32'
          volatile: 'true'
          access: read-write
          field:
          - name: Reserved_10
            displayName: Reserved
            description: Reserved.``Legal Values:``0.
            bitOffset: '10'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '5'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: SEIP
            displayName: Supervisor-level External Interrupt Pending
            description: SEIP is the interrupt-pending bit for supervisor-level external interrupts.
            bitOffset: '9'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            volatile: 'true'
            access: read-only
            vendorExtensions:
              RISCV_behavior: WARL
          - name: UEIP
            description: UEIP may be written by S-mode software to indicate to U-mode that an external interrupt is pending.``Legal Values:``0.
            bitOffset: '8'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: Reserved_6
            displayName: Reserved
            description: Reserved.``Legal Values:``0.
            bitOffset: '6'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '2'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: STIP
            displayName: Supervisor-level Timer Interrupt Pending
            description: SEIP is the interrupt-pending bit for supervisor-level timer interrupts.
            bitOffset: '5'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            volatile: 'true'
            access: read-only
            vendorExtensions:
              RISCV_behavior: WARL
          - name: UTIP
            description: A user-level timer interrupt is pending if the UTIP bit in the sip register is set.``Legal Values:``0.
            bitOffset: '4'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: Reserved_2
            displayName: Reserved
            description: Reserved.``Legal Values:``0.
            bitOffset: '2'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '2'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: SSIP
            displayName: Supervisor-level Software Interrupt Pending
            description: SSIP is the interrupt-pending bit for supervisor-level software interrupts.
            bitOffset: '1'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            volatile: 'true'
            access: read-only
            vendorExtensions:
              RISCV_behavior: WARL
          - name: USIP
            description: A user-level software interrupt is triggered on the current hart by writing 1 to its user software interrupt-pending (USIP) bit.``Legal Values:``0.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          vendorExtensions:
            privilege_mode: S
        - name: satp
          displayName: Supervisor Address Translation and Protection
          description: "The ``satp`` register controls supervisor-mode address translation and protection.\n\nThe ``satp`` register is considered active when the effective privilege mode is S-mode or U-mode. Executions of the address-translation algorithm may only begin using a given value of ``satp`` when ``satp`` is active.\n\n.. note::\n  Writing ``satp`` does not imply any ordering constraints between page-table updates and subsequent address translations, nor does it imply any invalidation of address-translation caches. If the new address space’s page tables have been modified, or if an ASID is reused, it may be necessary to execute an SFENCE.VMA instruction after, or in some cases before, writing ``satp``."
          addressOffset: "'h180"
          size: '32'
          access: read-write
          field:
          - name: MODE
            displayName: Mode
            description: "This bitfield selects the current address-translation scheme.\n\nWhen MODE=Bare, supervisor virtual addresses are equal to supervisor physical addresses, and there is no additional memory protection beyond the physical memory protection scheme.\n\nTo select MODE=Bare, software must write zero to the remaining fields of ``satp`` (bits 30–0). Attempting to select MODE=Bare with a nonzero pattern in the remaining fields has an ``unspecified`` effect on the value that the remaining fields assume and an ``unspecified`` effect on address translation and protection behavior."
            bitOffset: '31'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            enumeratedValues:
              enumeratedValue:
              - '@usage': read-write
                name: Bare
                description: No translation or protection.
                value: '0'
              - '@usage': read-write
                name: Sv32
                description: Page-based 32-bit virtual addressing.
                value: '1'
            vendorExtensions:
              RISCV_behavior: WARL
          - name: ASID
            displayName: Address Space Identifier
            description: This bitfield facilitates address-translation fences on a per-address-space basis.
            bitOffset: '22'
            resets:
              reset:
                value: '0x0'
                mask: '0x1ff'
            bitWidth: '9'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: PPN
            displayName: Physical Page Number
            description: This bitfield holds the root page table, i.e., its supervisor physical address divided by 4 KiB.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0x3fffff'
            bitWidth: '22'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          vendorExtensions:
            privilege_mode: S
        - name: mstatus
          displayName: Machine Status
          description: The ``mstatus`` register keeps track of and controls the hart’s current operating state.
          addressOffset: "'h300"
          size: '32'
          volatile: 'true'
          access: read-write
          field:
          - name: SD
            displayName: State Dirty
            description: The SD bit is a read-only bit that summarizes whether either the FS, VS, or XS fields signal the presence of some dirty state that will require saving extended user context to memory. If FS, XS, and VS are all read-only zero, then SD is also always zero.
            bitOffset: '31'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            volatile: 'true'
            access: read-only
          - name: WPRI3
            displayName: Reserved Writes Preserve Values, Reads Ignore Value
            description: Reserved Writes Preserve Values, Reads Ignore Value
            bitOffset: '23'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '8'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WPRI
          - name: TSR
            displayName: Trap SRET
            description: The TSR bit supports intercepting the supervisor exception return instruction, SRET. When TSR=1, attempts to execute SRET while executing in S-mode will raise an illegal instruction exception. When TSR=0, this operation is permitted in S-mode.
            bitOffset: '22'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: TW
            displayName: Timeout Wait
            description: The TW bit supports intercepting the WFI instruction. When TW=0, the WFI instruction may execute in lower privilege modes when not prevented for some other reason. When TW=1, then if WFI is executed in any less-privileged mode, and it does not complete within an implementation-specific, bounded time limit, the WFI instruction causes an illegal instruction exception. The time limit may always be 0, in which case WFI always causes an illegal instruction exception in less-privileged modes when TW=1.
            bitOffset: '21'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: TVM
            displayName: Trap Virtual Memory
            description: The TVM bit supports intercepting supervisor virtual-memory management operations. When TVM=1, attempts to read or write the ``satp`` CSR or execute an SFENCE.VMA or SINVAL.VMA instruction while executing in S-mode will raise an illegal instruction exception. When TVM=0, these operations are permitted in S-mode.
            bitOffset: '20'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: MXR
            displayName: Make eXecutable Readable
            description: The MXR bit modifies the privilege with which loads access virtual memory. When MXR=0, only loads from pages marked readable will succeed. When MXR=1, loads from pages marked either readable or executable (R=1 or X=1) will succeed. MXR has no effect when page-based virtual memory is not in effect.
            bitOffset: '19'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: SUM
            displayName: Supervisor User Memory
            description: The SUM (permit Supervisor User Memory access) bit modifies the privilege with which S-mode loads and stores access virtual memory. When SUM=0, S-mode memory accesses to pages that are accessible by U-mode will fault. When SUM=1, these accesses are permitted. SUM has no effect when page-based virtual memory is not in effect. Note that, while SUM is ordinarily ignored when not executing in S-mode, it is in effect when MPRV=1 and MPP=S.
            bitOffset: '18'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: MPRV
            displayName: Modify Privilege
            description: The MPRV (Modify PRiVilege) bit modifies the effective privilege mode, i.e., the privilege level at which loads and stores execute. When MPRV=0, loads and stores behave as normal, using the translation and protection mechanisms of the current privilege mode. When MPRV=1, load and store memory addresses are translated and protected, and endianness is applied, as though the current privilege mode were set to MPP. Instruction address-translation and protection are unaffected by the setting of MPRV.
            bitOffset: '17'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: XS
            displayName: Extension State
            description: "The XS field is used to reduce the cost of context save and restore by setting and tracking the current state of the user-mode extensions. The XS field encodes the status of the additional user-mode extensions and associated state.\n\nThis field can be checked by a context switch routine to quickly determine whether a state save or restore is required. If a save or restore is required, additional instructions and CSRs are typically required to effect and optimize the process."
            bitOffset: '15'
            resets:
              reset:
                value: '0x0'
                mask: '0x3'
            bitWidth: '2'
            volatile: 'true'
            access: read-only
            enumeratedValues:
              enumeratedValue:
              - '@usage': read
                name: Off
                description: All off
                value: '0'
              - '@usage': read
                name: Initial
                description: None dirty or clean, some on
                value: '1'
              - '@usage': read
                name: Clean
                description: None dirty, some clean
                value: '2'
              - '@usage': read
                name: Dirty
                description: Some dirty
                value: '3'
          - name: FS
            displayName: Floating-point unit State
            description: "The FS field is used to reduce the cost of context save and restore by setting and tracking the current state of the floating-point unit. The FS field encodes the status of the floating-point unit state, including the floating-point registers ``f0–f31`` and the CSRs ``fcsr``, ``frm``, and ``fflags``.\n\nThis field can be checked by a context switch routine to quickly determine whether a state save or restore is required. If a save or restore is required, additional instructions and CSRs are typically required to effect and optimize the process."
            bitOffset: '13'
            resets:
              reset:
                value: '0x0'
                mask: '0x3'
            bitWidth: '2'
            access: read-write
            enumeratedValues:
              enumeratedValue:
              - '@usage': read-write
                name: Off
                value: '0'
              - '@usage': read-write
                name: Initial
                value: '1'
              - '@usage': read-write
                name: Clean
                value: '2'
              - '@usage': read-write
                name: Dirty
                value: '3'
            vendorExtensions:
              RISCV_behavior: WARL
          - name: MPP
            displayName: Machine mode Prior Privilege
            description: Holds the previous privilege mode for machine mode.
            bitOffset: '11'
            resets:
              reset:
                value: '0x0'
                mask: '0x3'
            bitWidth: '2'
            access: read-write
          - name: VS
            displayName: Vector extension State
            description: V extension is not supported VS=0.
            bitOffset: '9'
            resets:
              reset:
                value: '0x0'
                mask: '0x3'
            bitWidth: '2'
            access: read-only
            vendorExtensions:
              RISCV_behavior: WARL
          - name: SPP
            displayName: Supervisor mode Prior Privilege
            description: Holds the previous privilege mode for supervisor mode.
            bitOffset: '8'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: MPIE
            displayName: Machine mode Prior Interrupt Enable
            description: Indicates whether machine interrupts were enabled prior to trapping into machine mode.
            bitOffset: '7'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: UBE
            displayName: User Breakpoint Enable
            description: UBE controls whether explicit load and store memory accesses made from U-mode are little-endian (UBE=0) or big-endian (UBE=1).
            bitOffset: '6'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: SPIE
            displayName: Supervisor mode Prior Interrupt Enable
            description: Indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode.
            bitOffset: '5'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: WPRI2
            displayName: Reserved Writes Preserve Values, Reads Ignore Value
            description: Reserved Writes Preserve Values, Reads Ignore Value
            bitOffset: '4'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WPRI
          - name: MIE
            displayName: Machine mode Interrupt Enable
            description: Global interrupt-enable bit for Machine mode.
            bitOffset: '3'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: WPRI1
            displayName: Reserved Writes Preserve Values, Reads Ignore Value
            description: Reserved Writes Preserve Values, Reads Ignore Value
            bitOffset: '2'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WPRI
          - name: SIE
            displayName: Supervisor mode Interrupt Enable
            description: Global interrupt-enable bit for Supervisor mode.
            bitOffset: '1'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: WPRI0
            displayName: Reserved Writes Preserve Values, Reads Ignore Value
            description: Reserved Writes Preserve Values, Reads Ignore Value
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WPRI
          vendorExtensions:
            privilege_mode: M
        - name: misa
          displayName: Machine ISA
          description: The misa CSR is reporting the ISA supported by the hart.
          addressOffset: "'h301"
          size: '32'
          access: read-write
          field:
          - name: MXL
            displayName: Machine XLEN
            description: The MXL field encodes the native base integer ISA width.
            bitOffset: '30'
            resets:
              reset:
                value: '0x1'
                mask: '0x3'
            bitWidth: '2'
            access: read-write
            enumeratedValues:
              enumeratedValue:
              - '@usage': read-write
                name: XLEN_32
                value: '1'
              - '@usage': read-write
                name: XLEN_64
                value: '2'
              - '@usage': read-write
                name: XLEN_128
                value: '3'
            vendorExtensions:
              RISCV_behavior: WARL
          - name: Extensions
            displayName: Extensions
            description: The Extensions field encodes the presence of the standard extensions, with a single bit per letter of the alphabet.
            bitOffset: '0'
            resets:
              reset:
                value: '0x141104'
                mask: '0x3ffffff'
            bitWidth: '26'
            access: read-write
            enumeratedValues:
              enumeratedValue:
              - '@usage': read-write
                name: A
                description: Atomic extension.
                value: '1'
              - '@usage': read-write
                name: B
                description: '*Tentatively reserved for Bit-Manipulation extension.*'
                value: '2'
              - '@usage': read-write
                name: C
                description: Compressed extension.
                value: '4'
              - '@usage': read-write
                name: D
                description: Double-precision floating-point extension.
                value: '8'
              - '@usage': read-write
                name: E
                description: RV32E base ISA.
                value: '16'
              - '@usage': read-write
                name: F
                description: Single-precision floating-point extension.
                value: '32'
              - '@usage': read-write
                name: G
                description: '*Reserved.*'
                value: '64'
              - '@usage': read-write
                name: H
                description: Hypervisor extension.
                value: '128'
              - '@usage': read-write
                name: I
                description: RV32I/64I/128I base ISA.
                value: '256'
              - '@usage': read-write
                name: J
                description: '*Tentatively reserved for Dynamically Translated Languages extension.*'
                value: '512'
              - '@usage': read-write
                name: K
                description: '*Reserved.*'
                value: '1024'
              - '@usage': read-write
                name: L
                description: '*Reserved.*'
                value: '2048'
              - '@usage': read-write
                name: M
                description: Integer Multiply/Divide extension.
                value: '4096'
              - '@usage': read-write
                name: N
                description: '*Tentatively reserved for User-Level Interrupts extension.*'
                value: '8192'
              - '@usage': read-write
                name: O
                description: '*Reserved.*'
                value: '16384'
              - '@usage': read-write
                name: P
                description: '*Tentatively reserved for Packed-SIMD extension.*'
                value: '32768'
              - '@usage': read-write
                name: Q
                description: Quad-precision floating-point extension.
                value: '65536'
              - '@usage': read-write
                name: R
                description: '*Reserved.*'
                value: '131072'
              - '@usage': read-write
                name: S
                description: Supervisor mode implemented.
                value: '262144'
              - '@usage': read-write
                name: T
                description: '*Reserved.*'
                value: '524288'
              - '@usage': read-write
                name: U
                description: User mode implemented.
                value: '1048576'
              - '@usage': read-write
                name: V
                description: '*Tentatively reserved for Vector extension.*'
                value: '2097152'
              - '@usage': read-write
                name: W
                description: '*Reserved.*'
                value: '4194304'
              - '@usage': read-write
                name: X
                description: Non-standard extensions present.
                value: '8388608'
              - '@usage': read-write
                name: Y
                description: '*Reserved.*'
                value: '16777216'
              - '@usage': read-write
                name: Z
                description: '*Reserved.*'
                value: '33554432'
            vendorExtensions:
              RISCV_behavior: WARL
          vendorExtensions:
            privilege_mode: M
        - name: medeleg
          displayName: Machine Exception Delegation
          description: Provides individual read/write bits to indicate that certain exceptions should be processed directly by a lower privilege level.
          addressOffset: "'h302"
          size: '32'
          access: read-write
          field:
            name: Synchronous_Exceptions
            displayName: Synchronous Exceptions
            description: "There is a bit position allocated for every synchronous exception,\nwith the index of the bit position equal to the value returned in the ``mcause`` register."
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          vendorExtensions:
            privilege_mode: M
        - name: mideleg
          displayName: Machine Interrupt Delegation
          description: Provides individual read/write bits to indicate that certain interrupts should be processed directly by a lower privilege level.
          addressOffset: "'h303"
          size: '32'
          access: read-write
          field:
            name: Interrupts
            displayName: Interrupts
            description: This bitfield holds trap delegation bits for individual interrupts, with the layout of bits matching those in the ``mip`` register.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: mie
          displayName: Machine Interrupt Enable
          description: This register contains machine interrupt enable bits.
          addressOffset: "'h304"
          size: '32'
          access: read-write
          field:
          - name: Reserved_12
            displayName: Reserved
            description: Reserved.``Legal Values:``0.
            bitOffset: '12'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '4'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: MEIE
            displayName: M-mode External Interrupt Enable
            description: Enables machine mode external interrupts.
            bitOffset: '11'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: Reserved_10
            displayName: Reserved
            description: Reserved.``Legal Values:``0.
            bitOffset: '10'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: SEIE
            displayName: S-mode External Interrupt Enable
            description: Enables supervisor mode external interrupts.
            bitOffset: '9'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: UEIE
            description: enables U-mode external interrupts.``Legal Values:``0.
            bitOffset: '8'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: MTIE
            displayName: M-mode Timer Interrupt Enable
            description: Enables machine mode timer interrupts.
            bitOffset: '7'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: Reserved_6
            displayName: Reserved
            description: Reserved.``Legal Values:``0.
            bitOffset: '6'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: STIE
            displayName: S-mode Timer Interrupt Enable
            description: Enables supervisor mode timer interrupts.
            bitOffset: '5'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: UTIE
            description: timer interrupt-enable bit for U-mode.``Legal Values:``0.
            bitOffset: '4'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: MSIE
            displayName: M-mode Software Interrupt Enable
            description: Enables machine mode software interrupts.
            bitOffset: '3'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: Reserved_2
            displayName: Reserved
            description: Reserved.``Legal Values:``0.
            bitOffset: '2'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: SSIE
            displayName: S-mode Software Interrupt Enable
            description: Enables supervisor mode software interrupts.
            bitOffset: '1'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: USIE
            description: enable U-mode software interrrupts.``Legal Values:``0.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          vendorExtensions:
            privilege_mode: M
        - name: mtvec
          displayName: Machine Trap Vector
          description: This register holds trap vector configuration, consisting of a vector base address and a vector mode.
          addressOffset: "'h305"
          size: '32'
          access: read-write
          field:
          - name: BASE
            description: 'The BASE field in mtvec is a WARL field that can hold any valid virtual or physical address, subject to the following alignment constraints: when MODE=Direct the address must be 4-byte aligned, and when MODE=Vectored the address must be 256-byte aligned.'
            bitOffset: '2'
            resets:
              reset:
                value: '0x0'
                mask: '0x3fffffff'
            bitWidth: '30'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: MODE
            description: Imposes additional alignment constraints on the value in the BASE field.``Legal Values :``0,1.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0x3'
            bitWidth: '2'
            access: read-write
            enumeratedValues:
              enumeratedValue:
              - '@usage': read-write
                name: Direct
                description: All exceptions set ``pc`` to BASE.
                value: '0'
              - '@usage': read-write
                name: Vectored
                description: Asynchronous interrupts set ``pc`` to BASE+4×cause.
                value: '1'
              - '@usage': read-write
                name: Reserved_2
                description: '*Reserved.*'
                value: '2'
              - '@usage': read-write
                name: Reserved_3
                description: '*Reserved.*'
                value: '3'
            vendorExtensions:
              RISCV_behavior: WARL
          vendorExtensions:
            privilege_mode: M
        - name: mcountern
          displayName: Machine Counter Enable
          description: This register controls the availability of the hardware performance-monitoring counters to the next-lowest privileged mode.
          addressOffset: "'h306"
          size: '32'
          access: read-write
          field:
          - name: HPMn
            displayName: Hpmcountern
            description: When HPMn is clear, attempts to read the ``hpmcountern`` register while executing in S-mode or U-mode will cause an illegal instruction exception. When this bit is set, access to the corresponding register is permitted in the next implemented privilege mode.
            bitOffset: '3'
            resets:
              reset:
                value: '0x0'
                mask: '0x1fffffff'
            bitWidth: '29'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: IR
            displayName: Instret
            description: When IR is clear, attempts to read the ``instret`` register while executing in S-mode or U-mode will cause an illegal instruction exception. When this bit is set, access to the corresponding register is permitted in the next implemented privilege mode.
            bitOffset: '2'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: TM
            displayName: Time
            description: When TM is clear, attempts to read the ``time`` register while executing in S-mode or U-mode will cause an illegal instruction exception. When this bit is set, access to the corresponding register is permitted in the next implemented privilege mode.
            bitOffset: '1'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: CY
            displayName: Cycle
            description: When CY is clear, attempts to read the ``cycle`` register while executing in S-mode or U-mode will cause an illegal instruction exception. When this bit is set, access to the corresponding register is permitted in the next implemented privilege mode.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: hpmevent
          displayName: Hardware Performance-Monitoring Event Selector
          description: This register controls which event causes the corresponding counter to increment.
          dim: '6'
          addressOffset: "'h323"
          size: '32'
          access: read-write
          field:
            name: mhpmevent
            description: event selector CSRs
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0x1f'
            bitWidth: '5'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          vendorExtensions:
            privilege_mode: M
        - name: mscratch
          displayName: Machine Scratch
          description: This register is used to hold a value dedicated to Machine mode. Attempts to access without Machine mode level raise illegal instruction exception.
          addressOffset: "'h340"
          size: '32'
          access: read-write
          field:
            name: mscratch
            displayName: Machine Scratch
            description: Holds a value dedicated to Machine mode.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: mepc
          displayName: Machine Exception Program Counter
          description: This register must be able to hold all valid virtual addresses.
          addressOffset: "'h341"
          size: '32'
          access: read-write
          field:
            name: mepc
            displayName: Machine Exception Program Counter
            description: When a trap is taken into M-mode, ``mepc`` is written with the virtual address of the instruction that was interrupted or that encountered the exception.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          vendorExtensions:
            privilege_mode: M
        - name: mcause
          displayName: Machine Cause
          description: "When a trap is taken into M-mode, mcause is written with a code indicating the event that caused the trap.\n\nMachine cause register (``mcause``) values after trap are shown in the following table. =========  ==============  ==============================\nInterrupt  Exception Code Description =========  ==============  ==============================\n        1               0  *Reserved*\n        1               1  Supervisor software interrupt\n        1             2-4  *Reserved*\n        1               5  Supervisor timer interrupt\n        1             6-8  *Reserved*\n        1               9  Supervisor external interrupt\n        1           10-15  *Reserved*\n        1             ≥16  *Designated for platform use*\n        0               0  Instruction address misaligned\n        0               1  Instruction access fault\n        0               2  Illegal instruction\n        0               3  Breakpoint\n        0               4  Load address misaligned\n        0               5  Load access fault\n        0               6  Store/AMO address misaligned\n        0               7  Store/AMO access fault\n        0               8  Environment call from U-mode\n        0               9  Environment call from S-mode\n        0           10-11  *Reserved*\n        0              12  Instruction page fault\n        0              13  Load page fault\n        0              14  *Reserved*\n        0              15  Store/AMO page fault\n        0           16-23  *Reserved*\n        0           24-31  *Designated for custom use*\n        0           32-47  *Reserved*\n        0           48-63  *Designated for custom use*\n        0             ≥64 *Reserved* =========  ==============  =============================="
          addressOffset: "'h342"
          size: '32'
          access: read-write
          field:
          - name: Interrupt
            displayName: Interrupt
            description: This bit is set if the trap was caused by an interrupt.
            bitOffset: '31'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: exception_code
            displayName: Exception Code
            description: This field contains a code identifying the last exception or interrupt.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0x7fffffff'
            bitWidth: '31'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WLRL
          vendorExtensions:
            privilege_mode: M
        - name: mtval
          displayName: Machine Trap Value
          description: When a trap is taken into M-mode, mtval is either set to zero or written with exception-specific information to assist software in handling the trap.
          addressOffset: "'h343"
          size: '32'
          access: read-write
          field:
            name: mtval
            displayName: Machine Trap Value
            description: "If ``mtval`` is written with a nonzero value when a breakpoint, address-misaligned, access-fault, or page-fault exception occurs on an instruction fetch, load, or store, then mtval will contain the faulting virtual address.\n\nIf ``mtval`` is written with a nonzero value when a misaligned load or store causes an access-fault or page-fault exception, then ``mtval`` will contain the virtual address of the portion of the access that caused the fault.\n\nIf ``mtval`` is written with a nonzero value when an instruction access-fault or page-fault exception occurs on a system with variable-length instructions, then ``mtval`` will contain the virtual address of the portion of the instruction that caused the fault, while ``mepc`` will point to the beginning of the instruction."
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          vendorExtensions:
            privilege_mode: M
        - name: mip
          displayName: Machine Interrupt Pending
          description: This register contains machine interrupt pending bits.
          addressOffset: "'h344"
          size: '32'
          volatile: 'true'
          access: read-write
          field:
          - name: Reserved_12
            displayName: Reserved
            description: Reserved.``Legal Values:``0.
            bitOffset: '12'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '4'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: MEIP
            displayName: M-mode External Interrupt Pending
            description: The interrupt-pending bit for machine-level external interrupts.
            bitOffset: '11'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            volatile: 'true'
            access: read-only
          - name: Reserved_10
            displayName: Reserved
            description: Reserved.``Legal Values:``0.
            bitOffset: '10'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: SEIP
            displayName: S-mode External Interrupt Pending
            description: The interrupt-pending bit for supervisor-level external interrupts.
            bitOffset: '9'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: UEIP
            description: enables external interrupts.``Legal Values:``0.
            bitOffset: '8'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: MTIP
            displayName: M-mode Timer Interrupt Pending
            description: The interrupt-pending bit for machine-level timer interrupts.
            bitOffset: '7'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            volatile: 'true'
            access: read-only
          - name: Reserved_6
            displayName: Reserved
            description: Reserved.``Legal Values:``0.
            bitOffset: '6'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: STIP
            displayName: S-mode Timer Interrupt Pending
            description: The interrupt-pending bit for supervisor-level timer interrupts.
            bitOffset: '5'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: UTIP
            description: Correspond to timer interrupt-pending bits for user interrupt.``Legal Values:``0.
            bitOffset: '4'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: MSIP
            displayName: M-mode Software Interrupt Pending
            description: The interrupt-pending bit for machine-level software interrupts.
            bitOffset: '3'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            volatile: 'true'
            access: read-only
          - name: Reserved_2
            displayName: Reserved
            description: Reserved.``Legal Values:``0.
            bitOffset: '2'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          - name: SSIP
            displayName: S-mode Software Interrupt Pending
            description: The interrupt-pending bit for supervisor-level software interrupts.
            bitOffset: '1'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: USIP
            description: A hart to directly write its own USIP bits when running in the appropriate mode.``Legal Values:``0.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: pmpcfg0
          displayName: Physical Memory Protection Config 0
          description: Holds configuration 0-3.
          addressOffset: "'h3A0"
          size: '32'
          access: read-write
          field:
          - name: pmp3cfg
            displayName: Physical Memory Protection 3 Config
            description: Holds the configuration.
            bitOffset: '24'
            resets:
              reset:
                value: '0x0'
                mask: '0xff'
            bitWidth: '8'
            access: read-write
          - name: pmp2cfg
            displayName: Physical Memory Protection 2 Config
            description: Holds the configuration.
            bitOffset: '16'
            resets:
              reset:
                value: '0x0'
                mask: '0xff'
            bitWidth: '8'
            access: read-write
          - name: pmp1cfg
            displayName: Physical Memory Protection 1 Config
            description: Holds the configuration.
            bitOffset: '8'
            resets:
              reset:
                value: '0x0'
                mask: '0xff'
            bitWidth: '8'
            access: read-write
          - name: pmp0cfg
            displayName: Physical Memory Protection 0 Config
            description: Holds the configuration.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xff'
            bitWidth: '8'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: pmpcfg1
          displayName: Physical Memory Protection Config 1
          description: Holds configuration 4-7.
          addressOffset: "'h3A1"
          size: '32'
          access: read-write
          field:
          - name: pmp7cfg
            displayName: Physical Memory Protection 7 Config
            description: Holds the configuration.
            bitOffset: '24'
            resets:
              reset:
                value: '0x0'
                mask: '0xff'
            bitWidth: '8'
            access: read-write
          - name: pmp6cfg
            displayName: Physical Memory Protection 6 Config
            description: Holds the configuration.
            bitOffset: '16'
            resets:
              reset:
                value: '0x0'
                mask: '0xff'
            bitWidth: '8'
            access: read-write
          - name: pmp5cfg
            displayName: Physical Memory Protection 5 Config
            description: Holds the configuration.
            bitOffset: '8'
            resets:
              reset:
                value: '0x0'
                mask: '0xff'
            bitWidth: '8'
            access: read-write
          - name: pmp4cfg
            displayName: Physical Memory Protection 4 Config
            description: Holds the configuration.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xff'
            bitWidth: '8'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: pmpcfg2
          displayName: Physical Memory Protection Config 2
          description: Holds configuration 8-11.
          addressOffset: "'h3A2"
          size: '32'
          access: read-write
          field:
          - name: pmp11cfg
            displayName: Physical Memory Protection 11 Config
            description: Holds the configuration.
            bitOffset: '24'
            resets:
              reset:
                value: '0x0'
                mask: '0xff'
            bitWidth: '8'
            access: read-write
          - name: pmp10cfg
            displayName: Physical Memory Protection 10 Config
            description: Holds the configuration.
            bitOffset: '16'
            resets:
              reset:
                value: '0x0'
                mask: '0xff'
            bitWidth: '8'
            access: read-write
          - name: pmp9cfg
            displayName: Physical Memory Protection 9 Config
            description: Holds the configuration.
            bitOffset: '8'
            resets:
              reset:
                value: '0x0'
                mask: '0xff'
            bitWidth: '8'
            access: read-write
          - name: pmp8cfg
            displayName: Physical Memory Protection 8 Config
            description: Holds the configuration.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xff'
            bitWidth: '8'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: pmpcfg3
          displayName: Physical Memory Protection Config 3
          description: Holds configuration 12-15.
          addressOffset: "'h3A3"
          size: '32'
          access: read-write
          field:
          - name: pmp15cfg
            displayName: Physical Memory Protection 15 Config
            description: Holds the configuration.
            bitOffset: '24'
            resets:
              reset:
                value: '0x0'
                mask: '0xff'
            bitWidth: '8'
            access: read-write
          - name: pmp14cfg
            displayName: Physical Memory Protection 14 Config
            description: Holds the configuration.
            bitOffset: '16'
            resets:
              reset:
                value: '0x0'
                mask: '0xff'
            bitWidth: '8'
            access: read-write
          - name: pmp13cfg
            displayName: Physical Memory Protection 13 Config
            description: Holds the configuration.
            bitOffset: '8'
            resets:
              reset:
                value: '0x0'
                mask: '0xff'
            bitWidth: '8'
            access: read-write
          - name: pmp12cfg
            displayName: Physical Memory Protection 12 Config
            description: Holds the configuration.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xff'
            bitWidth: '8'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: pmpaddr
          displayName: Physical Memory Protection Address
          description: Address register for Physical Memory Protection.
          dim: '16'
          addressOffset: "'h3B0"
          size: '32'
          access: read-write
          field:
            name: address
            displayName: Address
            description: Encodes bits 33-2 of a 34-bit physical address.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
            vendorExtensions:
              RISCV_behavior: WARL
          vendorExtensions:
            privilege_mode: M
        - name: icache
          displayName: Instruction Cache
          description: Custom Register to enable/disable for Icache [bit 0]
          addressOffset: "'h7C0"
          size: '32'
          access: read-write
          field:
            name: icache
            displayName: Instruction Cache
            description: Custom Register
            bitOffset: '0'
            resets:
              reset:
                value: '0x1'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: dcache
          displayName: Data Cache
          description: Custom Register to enable/disable for Dcache [bit 0]
          addressOffset: "'h7C1"
          size: '32'
          access: read-write
          field:
            name: dcache
            displayName: Data Cache
            description: Custom Register
            bitOffset: '0'
            resets:
              reset:
                value: '0x1'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: tselect
          displayName: Trigger Select
          description: This register determines which trigger is accessible through the other trigger registers.
          addressOffset: "'h7A0"
          size: '32'
          access: read-write
          field:
            name: index
            displayName: Index
            description: "The set of accessible triggers must start at 0, and be contiguous.\n\nWrites of values greater than or equal to the number of supported triggers may result in a different value in this register than what was written. To verify that what they wrote is a valid index, debuggers can read back the value and check that ``tselect`` holds what they wrote.\n\nSince triggers can be used both by Debug Mode and M-mode, the debugger must restore this register if it modifies it."
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: D
        - name: tdata1
          displayName: Trigger Data 1
          description: Trigger-specific data.
          addressOffset: "'h7A1"
          size: '32'
          access: read-write
          field:
          - name: type
            displayName: Type
            description: Type of trigger.
            bitOffset: '28'
            resets:
              reset:
                value: '0x0'
                mask: '0xf'
            bitWidth: '4'
            access: read-write
            enumeratedValues:
              enumeratedValue:
              - '@usage': read-write
                name: no_trigger
                description: There is no trigger at this ``tselect``.
                value: '0'
              - '@usage': read-write
                name: legacy_address_match_trigger
                description: The trigger is a legacy SiFive address match trigger. These should not be implemented and aren’t further documented here.
                value: '1'
              - '@usage': read-write
                name: address_data_match_trigger
                description: The trigger is an address/data match trigger. The remaining bits in this register act as described in ``mcontrol``.
                value: '2'
              - '@usage': read-write
                name: instruction_count_trigger
                description: The trigger is an instruction count trigger. The remaining bits in this register act as described in ``icount``.
                value: '3'
              - '@usage': read-write
                name: interrupt_trigger
                description: The trigger is an interrupt trigger. The remaining bits in this register act as described in ``itrigger``.
                value: '4'
              - '@usage': read-write
                name: exception_trigger
                description: The trigger is an exception trigger. The remaining bits in this register act as described in ``etrigger``.
                value: '5'
              - '@usage': read-write
                name: Reserved_6
                description: '*Reserved.*'
                value: '6'
              - '@usage': read-write
                name: Reserved_7
                description: '*Reserved.*'
                value: '7'
              - '@usage': read-write
                name: Reserved_8
                description: '*Reserved.*'
                value: '8'
              - '@usage': read-write
                name: Reserved_9
                description: '*Reserved.*'
                value: '9'
              - '@usage': read-write
                name: Reserved_10
                description: '*Reserved.*'
                value: '10'
              - '@usage': read-write
                name: Reserved_11
                description: '*Reserved.*'
                value: '11'
              - '@usage': read-write
                name: Reserved_12
                description: '*Reserved.*'
                value: '12'
              - '@usage': read-write
                name: Reserved_13
                description: '*Reserved.*'
                value: '13'
              - '@usage': read-write
                name: Reserved_14
                description: '*Reserved.*'
                value: '14'
              - '@usage': read-write
                name: trigger_exists
                description: This trigger exists (so enumeration shouldn’t terminate), but is not currently available.
                value: '15'
          - name: dmode
            displayName: Debug Mode
            description: This bit is only writable from Debug Mode.
            bitOffset: '27'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            enumeratedValues:
              enumeratedValue:
              - '@usage': read-write
                name: D_and_M_mode
                description: Both Debug and M-mode can write the ``tdata`` registers at the selected ``tselect``.
                value: '0'
              - '@usage': read-write
                name: M_mode_only
                description: Only Debug Mode can write the ``tdata`` registers at the selected ``tselect``. Writes from other modes are ignored.
                value: '1'
          - name: data
            displayName: Data
            description: Trigger-specific data.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0x7ffffff'
            bitWidth: '27'
            access: read-write
          vendorExtensions:
            privilege_mode: D
        - name: tdata2
          displayName: Trigger Data 2
          description: Trigger-specific data.
          addressOffset: "'h7A2"
          size: '32'
          access: read-write
          field:
            name: data
            displayName: Data
            description: Trigger-specific data.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: D
        - name: tdata3
          displayName: Trigger Data 3
          description: Trigger-specific data.
          addressOffset: "'h7A3"
          size: '32'
          access: read-write
          field:
            name: data
            displayName: Data
            description: Trigger-specific data.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: D
        - name: tinfo
          displayName: Trigger Info
          description: Shows trigger information.
          addressOffset: "'h7A4"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: info
            displayName: Info
            description: "One bit for each possible ``type`` enumerated in ``tdata1``. Bit N corresponds to type N. If the bit is set, then that type is supported by the currently selected trigger.\n\nIf the currently selected trigger doesn’t exist, this field contains 1.\n\nIf ``type`` is not writable, this register may be unimplemented, in which case reading it causes an illegal instruction exception. In this case the debugger can read the only supported type from ``tdata1``."
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffff'
            bitWidth: '16'
            volatile: 'true'
            access: read-only
          vendorExtensions:
            privilege_mode: D
        - name: dcsr
          displayName: Debug Control and Status
          description: Debug ontrol and status register.
          addressOffset: "'h7B0"
          size: '32'
          volatile: 'true'
          access: read-write
          field:
          - name: xdebugver
            displayName: Debug Version
            description: Shows the version of the debug support.
            bitOffset: '28'
            resets:
              reset:
                value: '0x0'
                mask: '0xf'
            bitWidth: '4'
            volatile: 'true'
            access: read-only
            enumeratedValues:
              enumeratedValue:
              - '@usage': read
                name: no_ext_debug
                description: There is no external debug support.
                value: '0'
              - '@usage': read
                name: ext_debug_spec
                description: External debug support exists as it is described in the riscv-debug-release document.
                value: '4'
              - '@usage': read
                name: ext_debug_no_spec
                description: There is external debug support, but it does not conform to any available version of the riscv-debug-release spec.
                value: '15'
          - name: ebreakm
            displayName: Environment Breakpoint M-mode
            description: Shows the behvior of the ``ebreak`` instruction in machine mode.
            bitOffset: '15'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            enumeratedValues:
              enumeratedValue:
              - '@usage': read-write
                name: break_as_spec
                description: '``ebreak`` instructions in M-mode behave as described in the Privileged Spec.'
                value: '0'
              - '@usage': read-write
                name: break_to_debug
                description: '``ebreak`` instructions in M-mode enter Debug Mode.'
                value: '1'
          - name: ebreaks
            displayName: Environment Breakpoint S-mode
            description: Shows the behvior of the ``ebreak`` instruction in supervisor mode.
            bitOffset: '13'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            enumeratedValues:
              enumeratedValue:
              - '@usage': read-write
                name: break_as_spec
                description: '``ebreak`` instructions in S-mode behave as described in the Privileged Spec.'
                value: '0'
              - '@usage': read-write
                name: break_to_debug
                description: '``ebreak`` instructions in S-mode enter Debug Mode.'
                value: '1'
          - name: ebreaku
            displayName: Environment Breakpoint U-mode
            description: Shows the behvior of the ``ebreak`` instruction in user mode.
            bitOffset: '12'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            enumeratedValues:
              enumeratedValue:
              - '@usage': read-write
                name: break_as_spec
                description: '``ebreak`` instructions in U-mode behave as described in the Privileged Spec.'
                value: '0'
              - '@usage': read-write
                name: break_to_debug
                description: '``ebreak`` instructions in U-mode enter Debug Mode.'
                value: '1'
          - name: stepie
            displayName: Stepping Interrupt Enable
            description: "Enables/disables interrupts for single stepping.\n\nThe debugger must not change the value of this bit while the hart is running."
            bitOffset: '11'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            enumeratedValues:
              enumeratedValue:
              - '@usage': read-write
                name: disabled
                description: Interrupts are disabled during single stepping.
                value: '0'
              - '@usage': read-write
                name: enabled
                description: Interrupts are enabled during single stepping.
                value: '1'
            vendorExtensions:
              RISCV_behavior: WARL
          - name: stopcount
            displayName: Stop Counters
            description: Starts/stops incrementing counters in debug mode.
            bitOffset: '10'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            enumeratedValues:
              enumeratedValue:
              - '@usage': read-write
                name: increment_counters
                description: Increment counters as usual.
                value: '0'
              - '@usage': read-write
                name: dont_increment_counters
                description: Don’t increment any counters while in Debug Mode or on ``ebreak`` instructions that cause entry into Debug Mode.
                value: '1'
            vendorExtensions:
              RISCV_behavior: WARL
          - name: stoptime
            displayName: Stop Timers
            description: Starts/stops incrementing timers in debug mode.
            bitOffset: '9'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            enumeratedValues:
              enumeratedValue:
              - '@usage': read-write
                name: increment_timers
                description: Increment timers as usual.
                value: '0'
              - '@usage': read-write
                name: dont_increment_timers
                description: Don’t increment any hart-local timers while in Debug Mode.
                value: '1'
            vendorExtensions:
              RISCV_behavior: WARL
          - name: cause
            displayName: Cause
            description: "Explains why Debug Mode was entered.\n\nWhen there are multiple reasons to enter Debug Mode in a single cycle, hardware sets ``cause`` to the cause with the highest priority."
            bitOffset: '6'
            resets:
              reset:
                value: '0x0'
                mask: '0x7'
            bitWidth: '3'
            access: read-write
            enumeratedValues:
              enumeratedValue:
              - '@usage': read-write
                name: ebreak_instruction
                description: An ``ebreak`` instruction was executed. (priority 3)
                value: '1'
              - '@usage': read-write
                name: trigger_module
                description: The Trigger Module caused a breakpoint exception. (priority 4, highest)
                value: '2'
              - '@usage': read-write
                name: debugger_request
                description: The debugger requested entry to Debug Mode using ``haltreq``. (priority 1)
                value: '3'
              - '@usage': read-write
                name: single_step
                description: The hart single stepped because ``step`` was set. (priority 0, lowest)
                value: '4'
              - '@usage': read-write
                name: reset_halt
                description: The hart halted directly out of reset due to ``resethaltreq``. It is also acceptable to report 3 when this happens. (priority 2)
                value: '5'
          - name: mprven
            displayName: Modify Privilege Enable
            description: Enables/disables the modify privilege setting in debug mode.
            bitOffset: '4'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
            enumeratedValues:
              enumeratedValue:
              - '@usage': read-write
                name: disable_mprv
                description: MPRV in ``mstatus`` is ignored in Debug Mode.
                value: '0'
              - '@usage': read-write
                name: enable_mprv
                description: MPRV in ``mstatus`` takes effect in Debug Mode.
                value: '1'
            vendorExtensions:
              RISCV_behavior: WARL
          - name: nmip
            displayName: Non-Maskable Interrupt Pending
            description: When set, there is a Non-Maskable-Interrupt (NMI) pending for the hart.
            bitOffset: '3'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            volatile: 'true'
            access: read-only
          - name: step
            displayName: Step
            description: When set and not in Debug Mode, the hart will only execute a single instruction and then enter Debug Mode. If the instruction does not complete due to an exception, the hart will immediately enter Debug Mode before executing the trap handler, with appropriate exception registers set. The debugger must not change the value of this bit while the hart is running.
            bitOffset: '2'
            resets:
              reset:
                value: '0x0'
                mask: '0x1'
            bitWidth: '1'
            access: read-write
          - name: prv
            displayName: Privilege level
            description: Contains the privilege level the hart was operating in when Debug Mode was entered. A debugger can change this value to change the hart’s privilege level when exiting Debug Mode.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0x3'
            bitWidth: '2'
            access: read-write
            enumeratedValues:
              enumeratedValue:
              - '@usage': read-write
                name: User
                value: '0'
              - '@usage': read-write
                name: Supervisor
                value: '1'
              - '@usage': read-write
                name: Machine
                value: '3'
          vendorExtensions:
            privilege_mode: D
        - name: dpc
          displayName: Debug PC
          description: "Upon entry to debug mode, ``dpc`` is updated with the virtual address of the next instruction to be executed.\n\nWhen resuming, the hart’s PC is updated to the virtual address stored in ``dpc``. A debugger may write ``dpc`` to change where the hart resumes."
          addressOffset: "'h7B1"
          size: '32'
          access: read-write
          field:
            name: dpc
            description: "The ``dpc`` behavior is described in more detail in the table below.\n\n.. csv-table::\n  :header: \"Cause\", \"Virtual Address in DPC\"\n\n  \"``ebreak``\", \"Address of the ``ebreak`` instruction.\"\n  \"single step\", \"Address of the instruction that would be executed next if no debugging was going on. Ie. pc + 4 for 32-bit instructions that don’t change program flow, the destination PC on taken jumps/branches, etc.\"\n  \"trigger module\", \"If ``timing`` is 0, the address of the instruction which caused the trigger to fire. If ``timing`` is 1, the address of the next instruction to be executed at the time that debug mode was entered.\"\n  \"halt request\", \"Address of the next instruction to be executed at the time that debug mode was entered.\""
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: D
        - name: dscratch
          displayName: Debug Scratch Register
          description: Optional scratch register. A debugger must not write to this register unless ``hartinfo`` explicitly mentions it.
          dim: '2'
          addressOffset: "'h7B2"
          size: '32'
          access: read-write
          field:
            name: dscratch
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: D
        - name: ftran
          description: Floating Point Custom CSR
          addressOffset: "'h800"
          size: '32'
          access: read-write
          field:
            name: ftran
            description: Floating Point Custom CSR
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0x7f'
            bitWidth: '7'
            access: read-write
          vendorExtensions:
            privilege_mode: U
        - name: mcycle
          displayName: M-mode Cycle counter
          description: Counts the number of clock cycles executed by the processor core on which the hart is running.
          addressOffset: "'hB00"
          size: '32'
          access: read-write
          field:
            name: count
            displayName: Count
            description: Counts the number of clock cycles executed by the processor core.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: minstret
          displayName: Machine Instruction Retired counter
          description: Counts the number of instructions the hart has retired.
          addressOffset: "'hB02"
          size: '32'
          access: read-write
          field:
            name: count
            displayName: Count
            description: Counts the number of instructions the hart has retired.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: ml1_icache_miss
          displayName: L1 Inst Cache Miss
          description: Hardware performance event counter.
          addressOffset: "'hB03"
          size: '32'
          access: read-write
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: ml1_dcache_miss
          displayName: L1 Data Cache Miss
          description: Hardware performance event counter.
          addressOffset: "'hB04"
          size: '32'
          access: read-write
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: mitlb_miss
          displayName: ITLB Miss
          description: Hardware performance event counter.
          addressOffset: "'hB05"
          size: '32'
          access: read-write
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: mdtlb_miss
          displayName: DTLB Miss
          description: Hardware performance event counter.
          addressOffset: "'hB06"
          size: '32'
          access: read-write
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: mload
          displayName: Loads
          description: Hardware performance event counter.
          addressOffset: "'hB07"
          size: '32'
          access: read-write
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: mstore
          displayName: Stores
          description: Hardware performance event counter.
          addressOffset: "'hB08"
          size: '32'
          access: read-write
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: mexception
          displayName: Taken Exceptions
          description: Hardware performance event counter.
          addressOffset: "'hB09"
          size: '32'
          access: read-write
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: mexception_ret
          displayName: Exception Return
          description: Hardware performance event counter.
          addressOffset: "'hB0A"
          size: '32'
          access: read-write
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: mbranch_jump
          displayName: Software Change of PC
          description: Hardware performance event counter.
          addressOffset: "'hB0B"
          size: '32'
          access: read-write
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: mcall
          displayName: Procedure Call
          description: Hardware performance event counter.
          addressOffset: "'hB0C"
          size: '32'
          access: read-write
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: mret
          displayName: Procedure Return
          description: Hardware performance event counter.
          addressOffset: "'hB0D"
          size: '32'
          access: read-write
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: mmis_predict
          displayName: Branch mis-predicted
          description: Hardware performance event counter.
          addressOffset: "'hB0E"
          size: '32'
          access: read-write
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: msb_full
          displayName: Scoreboard Full
          description: Hardware performance event counter.
          addressOffset: "'hB0F"
          size: '32'
          access: read-write
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: mif_empty
          displayName: Instruction Fetch Queue Empty
          description: Hardware performance event counter.
          addressOffset: "'hB10"
          size: '32'
          access: read-write
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: mcycleh
          displayName: Upper 32-bits of M-mode Cycle counter
          description: Counts the number of clock cycles executed by the processor core on which the hart is running.
          addressOffset: "'hB80"
          size: '32'
          access: read-write
          field:
            name: count
            displayName: Count
            description: Counts the number of clock cycles executed by the processor core.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: minstreth
          displayName: Upper 32-bits of Machine Instruction Retired counter
          description: Counts the number of instructions the hart has retired.
          addressOffset: "'hB82"
          size: '32'
          access: read-write
          field:
            name: count
            displayName: Count
            description: Counts the number of instructions the hart has retired.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: mhpmcounterh
          displayName: Upper 32-bits of Machine Hardware Performance Monitoring Counter
          description: Hardware performance event counter.
          dim: '6'
          addressOffset: "'hB83"
          size: '32'
          access: read-write
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            access: read-write
          vendorExtensions:
            privilege_mode: M
        - name: cycle
          displayName: Cycle counter
          description: Cycle counter for RDCYCLE instruction.
          addressOffset: "'hC00"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            volatile: 'true'
            access: read-only
          vendorExtensions:
            privilege_mode: U
        - name: time
          displayName: Timer
          description: Timer for RDTIME instruction.
          addressOffset: "'hC01"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            volatile: 'true'
            access: read-only
        - name: instret
          displayName: Instruction Retired counter
          description: Instructions-retired counter for RDINSTRET instruction
          addressOffset: "'hC02"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            volatile: 'true'
            access: read-only
          vendorExtensions:
            privilege_mode: U
        - name: l1_icache_miss
          displayName: L1 Inst Cache Miss
          description: Hardware performance event counter.
          addressOffset: "'hC03"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            volatile: 'true'
            access: read-only
          vendorExtensions:
            privilege_mode: M
        - name: l1_dcache_miss
          displayName: L1 Data Cache Miss
          description: Hardware performance event counter.
          addressOffset: "'hC04"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            volatile: 'true'
            access: read-only
          vendorExtensions:
            privilege_mode: M
        - name: itlb_miss
          displayName: ITLB Miss
          description: Hardware performance event counter.
          addressOffset: "'hC05"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            volatile: 'true'
            access: read-only
          vendorExtensions:
            privilege_mode: M
        - name: dtlb_miss
          displayName: DTLB Miss
          description: Hardware performance event counter.
          addressOffset: "'hC06"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            volatile: 'true'
            access: read-only
          vendorExtensions:
            privilege_mode: M
        - name: load
          displayName: Loads
          description: Hardware performance event counter.
          addressOffset: "'hC07"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            volatile: 'true'
            access: read-only
          vendorExtensions:
            privilege_mode: M
        - name: store
          displayName: Stores
          description: Hardware performance event counter.
          addressOffset: "'hC08"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            volatile: 'true'
            access: read-only
          vendorExtensions:
            privilege_mode: M
        - name: exception
          displayName: Taken Exceptions
          description: Hardware performance event counter.
          addressOffset: "'hC09"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            volatile: 'true'
            access: read-only
          vendorExtensions:
            privilege_mode: M
        - name: exception_ret
          displayName: Exception Return
          description: Hardware performance event counter.
          addressOffset: "'hC0A"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            volatile: 'true'
            access: read-only
          vendorExtensions:
            privilege_mode: M
        - name: branch_jump
          displayName: Software Change of PC
          description: Hardware performance event counter.
          addressOffset: "'hC0B"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            volatile: 'true'
            access: read-only
          vendorExtensions:
            privilege_mode: M
        - name: call
          displayName: Procedure Call
          description: Hardware performance event counter.
          addressOffset: "'hC0C"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            volatile: 'true'
            access: read-only
          vendorExtensions:
            privilege_mode: M
        - name: ret
          displayName: Procedure Return
          description: Hardware performance event counter.
          addressOffset: "'hC0D"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            volatile: 'true'
            access: read-only
          vendorExtensions:
            privilege_mode: M
        - name: mis_predict
          displayName: Branch mis-predicted
          description: Hardware performance event counter.
          addressOffset: "'hC0E"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            volatile: 'true'
            access: read-only
          vendorExtensions:
            privilege_mode: M
        - name: sb_full
          displayName: Scoreboard Full
          description: Hardware performance event counter.
          addressOffset: "'hC0F"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            volatile: 'true'
            access: read-only
          vendorExtensions:
            privilege_mode: M
        - name: if_empty
          displayName: Instruction Fetch Queue Empty
          description: Hardware performance event counter.
          addressOffset: "'hC10"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            volatile: 'true'
            access: read-only
          vendorExtensions:
            privilege_mode: M
        - name: cycleh
          displayName: Upper 32-bits of Cycle counter
          description: Cycle counter for RDCYCLE instruction.
          addressOffset: "'hC80"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            volatile: 'true'
            access: read-only
          vendorExtensions:
            privilege_mode: U
        - name: timeh
          displayName: Upper 32-bit of Timer
          description: Timer for RDTIME instruction.
          addressOffset: "'hC81"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            volatile: 'true'
            access: read-only
        - name: instreth
          displayName: Upper 32-bits of Instruction Retired counter
          description: Instructions-retired counter for RDINSTRET instruction
          addressOffset: "'hC82"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: count
            displayName: Count
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            volatile: 'true'
            access: read-only
          vendorExtensions:
            privilege_mode: U
        - name: mvendorid
          displayName: Machine Vendor ID
          description: This register provids the JEDEC manufacturer ID of the provider of the core.
          addressOffset: "'hF11"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
          - name: bank
            displayName: Bank
            description: Contain encoding for number of one-byte continuation codes discarding the parity bit.
            bitOffset: '7'
            resets:
              reset:
                value: '0x0'
                mask: '0x1ffffff'
            bitWidth: '25'
            volatile: 'true'
            access: read-only
          - name: offset
            displayName: Offset
            description: Contain encording for the final byte discarding the parity bit.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0x7f'
            bitWidth: '7'
            volatile: 'true'
            access: read-only
          vendorExtensions:
            privilege_mode: M
        - name: marchid
          displayName: Machine Architecture ID
          description: This register encodes the base microarchitecture of the hart.
          addressOffset: "'hF12"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: architecture_id
            displayName: Architecture ID
            description: Provide Encoding the base microarchitecture of the hart.
            bitOffset: '0'
            resets:
              reset:
                value: '0x3'
                mask: '0xffffffff'
            bitWidth: '32'
            volatile: 'true'
            access: read-only
          vendorExtensions:
            privilege_mode: M
        - name: mimpid
          displayName: Machine Implementation ID
          description: Provides a unique encoding of the version of the processor implementation.
          addressOffset: "'hF13"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: implementation
            displayName: Implementation
            description: Provides unique encoding of the version of the processor implementation.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            volatile: 'true'
            access: read-only
          vendorExtensions:
            privilege_mode: M
        - name: mhartid
          displayName: Machine Hardware Thread ID
          description: This register contains the integer ID of the hardware thread running the code.
          addressOffset: "'hF14"
          size: '32'
          volatile: 'true'
          access: read-only
          field:
            name: hart_id
            displayName: Hart ID
            description: Contains the integer ID of the hardware thread running the code.
            bitOffset: '0'
            resets:
              reset:
                value: '0x0'
                mask: '0xffffffff'
            bitWidth: '32'
            volatile: 'true'
            access: read-only
          vendorExtensions:
            privilege_mode: M
      addressUnitBits: '32'
