// Copyright (c) 2025 PlanV Technologies
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
/dts-v1/;

/ {
  #address-cells = <1>;
  #size-cells = <1>;
  compatible = "eth,ariane-bare-dev";
  model = "eth,ariane-bare";
  chosen {
    stdout-path = "/soc/uart@10000000:UART_BITRATE";
  };
  cpus {
    #address-cells = <1>;
    #size-cells = <0>;
    timebase-frequency = <HALF_CLOCK_FREQUENCY>;
    CPU0: cpu@0 {
      clock-frequency = <CLOCK_FREQUENCY>;
      device_type = "cpu";
      reg = <0>;
      status = "okay";
      compatible = "eth, ariane", "riscv";
      riscv,isa = "rv32ima";
      mmu-type = "riscv,sv32";
      tlb-split;
      // HLIC - hart local interrupt controller
      CPU0_intc: interrupt-controller {
        #interrupt-cells = <1>;
        interrupt-controller;
        compatible = "riscv,cpu-intc";
      };
    };
  };
  memory@80000000 {
    device_type = "memory";
    reg = <0x80000000 DRAM_SIZE_32>;
  };
  L26: soc {
    #address-cells = <1>;
    #size-cells = <1>;
    compatible = "eth,ariane-bare-soc", "simple-bus";
    ranges;
    clint@2000000 {
      compatible = "riscv,clint0";
      interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7>;
      reg = <0x2000000 0xc0000>;
      reg-names = "control";
    };
    PLIC0: interrupt-controller@c000000 {
      #address-cells = <0>;
      #interrupt-cells = <1>;
      compatible = "riscv,plic0";
      interrupt-controller;
      interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
      reg = <0xc000000 0x4000000>;
      riscv,max-priority = <7>;
      riscv,ndev = <30>;
    };
    // Specifying the interrupt controller in the devicetree is not necessary.
    // Furthermore, the IRQ 65535 will cause a `hwirq 0xffff is too large` during
    // Linux boot (occured with mainline linux 5.14.0).
    // debug-controller@0 {
    //   compatible = "riscv,debug-013";
    //   interrupts-extended = <&CPU0_intc 65535>;
    //   reg = <0x0 0x1000>;
    //   reg-names = "control";
    // };
    uart@10000000 {
      compatible = "ns16550a";
      reg = < 0x10000000 0x1000>;
      clock-frequency = <CLOCK_FREQUENCY>;
      current-speed = <UART_BITRATE>;
      interrupt-parent = <&PLIC0>;
      interrupts = <1>;
      reg-shift = <0>; // regs are spaced on 32 bit boundary
      reg-io-width = <1>; // only 32-bit access are supported
    };
    timer@18000000 {
      compatible = "pulp,apb_timer";
      interrupts = <0x00000004 0x00000005 0x00000006 0x00000007>;
      reg = <0x18000000 0x00001000>;
      interrupt-parent = <&PLIC0>;
      reg-names = "control";
    };
    sysmgr: sysmgr@ffd12000 {
			compatible = "altr,sys-mgr-s10","altr,sys-mgr";
			reg = <0xffd12000 0x500>;
		};
    mmc: mmc@ff808000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "altr,socfpga-dw-mshc";
			reg = <0xff808000 0x1000>;
			fifo-depth = <0x400>;
			altr,sysmgr-syscon = <&sysmgr 0x28 4>;
			status = "disabled";
		};
  };
};
// delete ethernet device if disabled
/delete-node/ &eth; // DELETE_ETH
