// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Register Top module auto-generated by `reggen`


`include "common_cells/assertions.svh"

module gpio_reg_top #(
  parameter type reg_req_t = logic,
  parameter type reg_rsp_t = logic,
  parameter int AW = 11
) (
  input logic clk_i,
  input logic rst_ni,
  input  reg_req_t reg_req_i,
  output reg_rsp_t reg_rsp_o,
  // To HW
  output gpio_reg_pkg::gpio_reg2hw_t reg2hw, // Write
  input  gpio_reg_pkg::gpio_hw2reg_t hw2reg, // Read


  // Config
  input devmode_i // If 1, explicit error return for unmapped register access
);

  import gpio_reg_pkg::* ;

  localparam int DW = 32;
  localparam int DBW = DW/8;                    // Byte Width

  // register signals
  logic           reg_we;
  logic           reg_re;
  logic [AW-1:0]  reg_addr;
  logic [DW-1:0]  reg_wdata;
  logic [DBW-1:0] reg_be;
  logic [DW-1:0]  reg_rdata;
  logic           reg_error;

  logic          addrmiss, wr_err;

  logic [DW-1:0] reg_rdata_next;

  // Below register interface can be changed
  reg_req_t  reg_intf_req;
  reg_rsp_t  reg_intf_rsp;


  assign reg_intf_req = reg_req_i;
  assign reg_rsp_o = reg_intf_rsp;


  assign reg_we = reg_intf_req.valid & reg_intf_req.write;
  assign reg_re = reg_intf_req.valid & ~reg_intf_req.write;
  assign reg_addr = reg_intf_req.addr;
  assign reg_wdata = reg_intf_req.wdata;
  assign reg_be = reg_intf_req.wstrb;
  assign reg_intf_rsp.rdata = reg_rdata;
  assign reg_intf_rsp.error = reg_error;
  assign reg_intf_rsp.ready = 1'b1;

  assign reg_rdata = reg_rdata_next ;
  assign reg_error = (devmode_i & addrmiss) | wr_err;


  // Define SW related signals
  // Format: <reg>_<field>_{wd|we|qs}
  //        or <reg>_{wd|we|qs} if field == 1 or 0
  logic [9:0] info_gpio_cnt_qs;
  logic info_gpio_cnt_re;
  logic [9:0] info_version_qs;
  logic info_version_re;
  logic cfg_glbl_intrpt_mode_qs;
  logic cfg_glbl_intrpt_mode_wd;
  logic cfg_glbl_intrpt_mode_we;
  logic cfg_pin_lvl_intrpt_mode_qs;
  logic cfg_pin_lvl_intrpt_mode_wd;
  logic cfg_pin_lvl_intrpt_mode_we;
  logic [1:0] gpio_mode_0_mode_0_qs;
  logic [1:0] gpio_mode_0_mode_0_wd;
  logic gpio_mode_0_mode_0_we;
  logic [1:0] gpio_mode_0_mode_1_qs;
  logic [1:0] gpio_mode_0_mode_1_wd;
  logic gpio_mode_0_mode_1_we;
  logic [1:0] gpio_mode_0_mode_2_qs;
  logic [1:0] gpio_mode_0_mode_2_wd;
  logic gpio_mode_0_mode_2_we;
  logic [1:0] gpio_mode_0_mode_3_qs;
  logic [1:0] gpio_mode_0_mode_3_wd;
  logic gpio_mode_0_mode_3_we;
  logic [1:0] gpio_mode_0_mode_4_qs;
  logic [1:0] gpio_mode_0_mode_4_wd;
  logic gpio_mode_0_mode_4_we;
  logic [1:0] gpio_mode_0_mode_5_qs;
  logic [1:0] gpio_mode_0_mode_5_wd;
  logic gpio_mode_0_mode_5_we;
  logic [1:0] gpio_mode_0_mode_6_qs;
  logic [1:0] gpio_mode_0_mode_6_wd;
  logic gpio_mode_0_mode_6_we;
  logic [1:0] gpio_mode_0_mode_7_qs;
  logic [1:0] gpio_mode_0_mode_7_wd;
  logic gpio_mode_0_mode_7_we;
  logic [1:0] gpio_mode_0_mode_8_qs;
  logic [1:0] gpio_mode_0_mode_8_wd;
  logic gpio_mode_0_mode_8_we;
  logic [1:0] gpio_mode_0_mode_9_qs;
  logic [1:0] gpio_mode_0_mode_9_wd;
  logic gpio_mode_0_mode_9_we;
  logic [1:0] gpio_mode_0_mode_10_qs;
  logic [1:0] gpio_mode_0_mode_10_wd;
  logic gpio_mode_0_mode_10_we;
  logic [1:0] gpio_mode_0_mode_11_qs;
  logic [1:0] gpio_mode_0_mode_11_wd;
  logic gpio_mode_0_mode_11_we;
  logic [1:0] gpio_mode_0_mode_12_qs;
  logic [1:0] gpio_mode_0_mode_12_wd;
  logic gpio_mode_0_mode_12_we;
  logic [1:0] gpio_mode_0_mode_13_qs;
  logic [1:0] gpio_mode_0_mode_13_wd;
  logic gpio_mode_0_mode_13_we;
  logic [1:0] gpio_mode_0_mode_14_qs;
  logic [1:0] gpio_mode_0_mode_14_wd;
  logic gpio_mode_0_mode_14_we;
  logic [1:0] gpio_mode_0_mode_15_qs;
  logic [1:0] gpio_mode_0_mode_15_wd;
  logic gpio_mode_0_mode_15_we;
  logic [1:0] gpio_mode_1_mode_16_qs;
  logic [1:0] gpio_mode_1_mode_16_wd;
  logic gpio_mode_1_mode_16_we;
  logic [1:0] gpio_mode_1_mode_17_qs;
  logic [1:0] gpio_mode_1_mode_17_wd;
  logic gpio_mode_1_mode_17_we;
  logic [1:0] gpio_mode_1_mode_18_qs;
  logic [1:0] gpio_mode_1_mode_18_wd;
  logic gpio_mode_1_mode_18_we;
  logic [1:0] gpio_mode_1_mode_19_qs;
  logic [1:0] gpio_mode_1_mode_19_wd;
  logic gpio_mode_1_mode_19_we;
  logic [1:0] gpio_mode_1_mode_20_qs;
  logic [1:0] gpio_mode_1_mode_20_wd;
  logic gpio_mode_1_mode_20_we;
  logic [1:0] gpio_mode_1_mode_21_qs;
  logic [1:0] gpio_mode_1_mode_21_wd;
  logic gpio_mode_1_mode_21_we;
  logic [1:0] gpio_mode_1_mode_22_qs;
  logic [1:0] gpio_mode_1_mode_22_wd;
  logic gpio_mode_1_mode_22_we;
  logic [1:0] gpio_mode_1_mode_23_qs;
  logic [1:0] gpio_mode_1_mode_23_wd;
  logic gpio_mode_1_mode_23_we;
  logic [1:0] gpio_mode_1_mode_24_qs;
  logic [1:0] gpio_mode_1_mode_24_wd;
  logic gpio_mode_1_mode_24_we;
  logic [1:0] gpio_mode_1_mode_25_qs;
  logic [1:0] gpio_mode_1_mode_25_wd;
  logic gpio_mode_1_mode_25_we;
  logic [1:0] gpio_mode_1_mode_26_qs;
  logic [1:0] gpio_mode_1_mode_26_wd;
  logic gpio_mode_1_mode_26_we;
  logic [1:0] gpio_mode_1_mode_27_qs;
  logic [1:0] gpio_mode_1_mode_27_wd;
  logic gpio_mode_1_mode_27_we;
  logic [1:0] gpio_mode_1_mode_28_qs;
  logic [1:0] gpio_mode_1_mode_28_wd;
  logic gpio_mode_1_mode_28_we;
  logic [1:0] gpio_mode_1_mode_29_qs;
  logic [1:0] gpio_mode_1_mode_29_wd;
  logic gpio_mode_1_mode_29_we;
  logic [1:0] gpio_mode_1_mode_30_qs;
  logic [1:0] gpio_mode_1_mode_30_wd;
  logic gpio_mode_1_mode_30_we;
  logic [1:0] gpio_mode_1_mode_31_qs;
  logic [1:0] gpio_mode_1_mode_31_wd;
  logic gpio_mode_1_mode_31_we;
  logic gpio_en_gpio_en_0_qs;
  logic gpio_en_gpio_en_0_wd;
  logic gpio_en_gpio_en_0_we;
  logic gpio_en_gpio_en_1_qs;
  logic gpio_en_gpio_en_1_wd;
  logic gpio_en_gpio_en_1_we;
  logic gpio_en_gpio_en_2_qs;
  logic gpio_en_gpio_en_2_wd;
  logic gpio_en_gpio_en_2_we;
  logic gpio_en_gpio_en_3_qs;
  logic gpio_en_gpio_en_3_wd;
  logic gpio_en_gpio_en_3_we;
  logic gpio_en_gpio_en_4_qs;
  logic gpio_en_gpio_en_4_wd;
  logic gpio_en_gpio_en_4_we;
  logic gpio_en_gpio_en_5_qs;
  logic gpio_en_gpio_en_5_wd;
  logic gpio_en_gpio_en_5_we;
  logic gpio_en_gpio_en_6_qs;
  logic gpio_en_gpio_en_6_wd;
  logic gpio_en_gpio_en_6_we;
  logic gpio_en_gpio_en_7_qs;
  logic gpio_en_gpio_en_7_wd;
  logic gpio_en_gpio_en_7_we;
  logic gpio_en_gpio_en_8_qs;
  logic gpio_en_gpio_en_8_wd;
  logic gpio_en_gpio_en_8_we;
  logic gpio_en_gpio_en_9_qs;
  logic gpio_en_gpio_en_9_wd;
  logic gpio_en_gpio_en_9_we;
  logic gpio_en_gpio_en_10_qs;
  logic gpio_en_gpio_en_10_wd;
  logic gpio_en_gpio_en_10_we;
  logic gpio_en_gpio_en_11_qs;
  logic gpio_en_gpio_en_11_wd;
  logic gpio_en_gpio_en_11_we;
  logic gpio_en_gpio_en_12_qs;
  logic gpio_en_gpio_en_12_wd;
  logic gpio_en_gpio_en_12_we;
  logic gpio_en_gpio_en_13_qs;
  logic gpio_en_gpio_en_13_wd;
  logic gpio_en_gpio_en_13_we;
  logic gpio_en_gpio_en_14_qs;
  logic gpio_en_gpio_en_14_wd;
  logic gpio_en_gpio_en_14_we;
  logic gpio_en_gpio_en_15_qs;
  logic gpio_en_gpio_en_15_wd;
  logic gpio_en_gpio_en_15_we;
  logic gpio_en_gpio_en_16_qs;
  logic gpio_en_gpio_en_16_wd;
  logic gpio_en_gpio_en_16_we;
  logic gpio_en_gpio_en_17_qs;
  logic gpio_en_gpio_en_17_wd;
  logic gpio_en_gpio_en_17_we;
  logic gpio_en_gpio_en_18_qs;
  logic gpio_en_gpio_en_18_wd;
  logic gpio_en_gpio_en_18_we;
  logic gpio_en_gpio_en_19_qs;
  logic gpio_en_gpio_en_19_wd;
  logic gpio_en_gpio_en_19_we;
  logic gpio_en_gpio_en_20_qs;
  logic gpio_en_gpio_en_20_wd;
  logic gpio_en_gpio_en_20_we;
  logic gpio_en_gpio_en_21_qs;
  logic gpio_en_gpio_en_21_wd;
  logic gpio_en_gpio_en_21_we;
  logic gpio_en_gpio_en_22_qs;
  logic gpio_en_gpio_en_22_wd;
  logic gpio_en_gpio_en_22_we;
  logic gpio_en_gpio_en_23_qs;
  logic gpio_en_gpio_en_23_wd;
  logic gpio_en_gpio_en_23_we;
  logic gpio_en_gpio_en_24_qs;
  logic gpio_en_gpio_en_24_wd;
  logic gpio_en_gpio_en_24_we;
  logic gpio_en_gpio_en_25_qs;
  logic gpio_en_gpio_en_25_wd;
  logic gpio_en_gpio_en_25_we;
  logic gpio_en_gpio_en_26_qs;
  logic gpio_en_gpio_en_26_wd;
  logic gpio_en_gpio_en_26_we;
  logic gpio_en_gpio_en_27_qs;
  logic gpio_en_gpio_en_27_wd;
  logic gpio_en_gpio_en_27_we;
  logic gpio_en_gpio_en_28_qs;
  logic gpio_en_gpio_en_28_wd;
  logic gpio_en_gpio_en_28_we;
  logic gpio_en_gpio_en_29_qs;
  logic gpio_en_gpio_en_29_wd;
  logic gpio_en_gpio_en_29_we;
  logic gpio_en_gpio_en_30_qs;
  logic gpio_en_gpio_en_30_wd;
  logic gpio_en_gpio_en_30_we;
  logic gpio_en_gpio_en_31_qs;
  logic gpio_en_gpio_en_31_wd;
  logic gpio_en_gpio_en_31_we;
  logic gpio_in_gpio_in_0_qs;
  logic gpio_in_gpio_in_0_re;
  logic gpio_in_gpio_in_1_qs;
  logic gpio_in_gpio_in_1_re;
  logic gpio_in_gpio_in_2_qs;
  logic gpio_in_gpio_in_2_re;
  logic gpio_in_gpio_in_3_qs;
  logic gpio_in_gpio_in_3_re;
  logic gpio_in_gpio_in_4_qs;
  logic gpio_in_gpio_in_4_re;
  logic gpio_in_gpio_in_5_qs;
  logic gpio_in_gpio_in_5_re;
  logic gpio_in_gpio_in_6_qs;
  logic gpio_in_gpio_in_6_re;
  logic gpio_in_gpio_in_7_qs;
  logic gpio_in_gpio_in_7_re;
  logic gpio_in_gpio_in_8_qs;
  logic gpio_in_gpio_in_8_re;
  logic gpio_in_gpio_in_9_qs;
  logic gpio_in_gpio_in_9_re;
  logic gpio_in_gpio_in_10_qs;
  logic gpio_in_gpio_in_10_re;
  logic gpio_in_gpio_in_11_qs;
  logic gpio_in_gpio_in_11_re;
  logic gpio_in_gpio_in_12_qs;
  logic gpio_in_gpio_in_12_re;
  logic gpio_in_gpio_in_13_qs;
  logic gpio_in_gpio_in_13_re;
  logic gpio_in_gpio_in_14_qs;
  logic gpio_in_gpio_in_14_re;
  logic gpio_in_gpio_in_15_qs;
  logic gpio_in_gpio_in_15_re;
  logic gpio_in_gpio_in_16_qs;
  logic gpio_in_gpio_in_16_re;
  logic gpio_in_gpio_in_17_qs;
  logic gpio_in_gpio_in_17_re;
  logic gpio_in_gpio_in_18_qs;
  logic gpio_in_gpio_in_18_re;
  logic gpio_in_gpio_in_19_qs;
  logic gpio_in_gpio_in_19_re;
  logic gpio_in_gpio_in_20_qs;
  logic gpio_in_gpio_in_20_re;
  logic gpio_in_gpio_in_21_qs;
  logic gpio_in_gpio_in_21_re;
  logic gpio_in_gpio_in_22_qs;
  logic gpio_in_gpio_in_22_re;
  logic gpio_in_gpio_in_23_qs;
  logic gpio_in_gpio_in_23_re;
  logic gpio_in_gpio_in_24_qs;
  logic gpio_in_gpio_in_24_re;
  logic gpio_in_gpio_in_25_qs;
  logic gpio_in_gpio_in_25_re;
  logic gpio_in_gpio_in_26_qs;
  logic gpio_in_gpio_in_26_re;
  logic gpio_in_gpio_in_27_qs;
  logic gpio_in_gpio_in_27_re;
  logic gpio_in_gpio_in_28_qs;
  logic gpio_in_gpio_in_28_re;
  logic gpio_in_gpio_in_29_qs;
  logic gpio_in_gpio_in_29_re;
  logic gpio_in_gpio_in_30_qs;
  logic gpio_in_gpio_in_30_re;
  logic gpio_in_gpio_in_31_qs;
  logic gpio_in_gpio_in_31_re;
  logic gpio_out_gpio_out_0_qs;
  logic gpio_out_gpio_out_0_wd;
  logic gpio_out_gpio_out_0_we;
  logic gpio_out_gpio_out_1_qs;
  logic gpio_out_gpio_out_1_wd;
  logic gpio_out_gpio_out_1_we;
  logic gpio_out_gpio_out_2_qs;
  logic gpio_out_gpio_out_2_wd;
  logic gpio_out_gpio_out_2_we;
  logic gpio_out_gpio_out_3_qs;
  logic gpio_out_gpio_out_3_wd;
  logic gpio_out_gpio_out_3_we;
  logic gpio_out_gpio_out_4_qs;
  logic gpio_out_gpio_out_4_wd;
  logic gpio_out_gpio_out_4_we;
  logic gpio_out_gpio_out_5_qs;
  logic gpio_out_gpio_out_5_wd;
  logic gpio_out_gpio_out_5_we;
  logic gpio_out_gpio_out_6_qs;
  logic gpio_out_gpio_out_6_wd;
  logic gpio_out_gpio_out_6_we;
  logic gpio_out_gpio_out_7_qs;
  logic gpio_out_gpio_out_7_wd;
  logic gpio_out_gpio_out_7_we;
  logic gpio_out_gpio_out_8_qs;
  logic gpio_out_gpio_out_8_wd;
  logic gpio_out_gpio_out_8_we;
  logic gpio_out_gpio_out_9_qs;
  logic gpio_out_gpio_out_9_wd;
  logic gpio_out_gpio_out_9_we;
  logic gpio_out_gpio_out_10_qs;
  logic gpio_out_gpio_out_10_wd;
  logic gpio_out_gpio_out_10_we;
  logic gpio_out_gpio_out_11_qs;
  logic gpio_out_gpio_out_11_wd;
  logic gpio_out_gpio_out_11_we;
  logic gpio_out_gpio_out_12_qs;
  logic gpio_out_gpio_out_12_wd;
  logic gpio_out_gpio_out_12_we;
  logic gpio_out_gpio_out_13_qs;
  logic gpio_out_gpio_out_13_wd;
  logic gpio_out_gpio_out_13_we;
  logic gpio_out_gpio_out_14_qs;
  logic gpio_out_gpio_out_14_wd;
  logic gpio_out_gpio_out_14_we;
  logic gpio_out_gpio_out_15_qs;
  logic gpio_out_gpio_out_15_wd;
  logic gpio_out_gpio_out_15_we;
  logic gpio_out_gpio_out_16_qs;
  logic gpio_out_gpio_out_16_wd;
  logic gpio_out_gpio_out_16_we;
  logic gpio_out_gpio_out_17_qs;
  logic gpio_out_gpio_out_17_wd;
  logic gpio_out_gpio_out_17_we;
  logic gpio_out_gpio_out_18_qs;
  logic gpio_out_gpio_out_18_wd;
  logic gpio_out_gpio_out_18_we;
  logic gpio_out_gpio_out_19_qs;
  logic gpio_out_gpio_out_19_wd;
  logic gpio_out_gpio_out_19_we;
  logic gpio_out_gpio_out_20_qs;
  logic gpio_out_gpio_out_20_wd;
  logic gpio_out_gpio_out_20_we;
  logic gpio_out_gpio_out_21_qs;
  logic gpio_out_gpio_out_21_wd;
  logic gpio_out_gpio_out_21_we;
  logic gpio_out_gpio_out_22_qs;
  logic gpio_out_gpio_out_22_wd;
  logic gpio_out_gpio_out_22_we;
  logic gpio_out_gpio_out_23_qs;
  logic gpio_out_gpio_out_23_wd;
  logic gpio_out_gpio_out_23_we;
  logic gpio_out_gpio_out_24_qs;
  logic gpio_out_gpio_out_24_wd;
  logic gpio_out_gpio_out_24_we;
  logic gpio_out_gpio_out_25_qs;
  logic gpio_out_gpio_out_25_wd;
  logic gpio_out_gpio_out_25_we;
  logic gpio_out_gpio_out_26_qs;
  logic gpio_out_gpio_out_26_wd;
  logic gpio_out_gpio_out_26_we;
  logic gpio_out_gpio_out_27_qs;
  logic gpio_out_gpio_out_27_wd;
  logic gpio_out_gpio_out_27_we;
  logic gpio_out_gpio_out_28_qs;
  logic gpio_out_gpio_out_28_wd;
  logic gpio_out_gpio_out_28_we;
  logic gpio_out_gpio_out_29_qs;
  logic gpio_out_gpio_out_29_wd;
  logic gpio_out_gpio_out_29_we;
  logic gpio_out_gpio_out_30_qs;
  logic gpio_out_gpio_out_30_wd;
  logic gpio_out_gpio_out_30_we;
  logic gpio_out_gpio_out_31_qs;
  logic gpio_out_gpio_out_31_wd;
  logic gpio_out_gpio_out_31_we;
  logic gpio_set_gpio_set_0_wd;
  logic gpio_set_gpio_set_0_we;
  logic gpio_set_gpio_set_1_wd;
  logic gpio_set_gpio_set_1_we;
  logic gpio_set_gpio_set_2_wd;
  logic gpio_set_gpio_set_2_we;
  logic gpio_set_gpio_set_3_wd;
  logic gpio_set_gpio_set_3_we;
  logic gpio_set_gpio_set_4_wd;
  logic gpio_set_gpio_set_4_we;
  logic gpio_set_gpio_set_5_wd;
  logic gpio_set_gpio_set_5_we;
  logic gpio_set_gpio_set_6_wd;
  logic gpio_set_gpio_set_6_we;
  logic gpio_set_gpio_set_7_wd;
  logic gpio_set_gpio_set_7_we;
  logic gpio_set_gpio_set_8_wd;
  logic gpio_set_gpio_set_8_we;
  logic gpio_set_gpio_set_9_wd;
  logic gpio_set_gpio_set_9_we;
  logic gpio_set_gpio_set_10_wd;
  logic gpio_set_gpio_set_10_we;
  logic gpio_set_gpio_set_11_wd;
  logic gpio_set_gpio_set_11_we;
  logic gpio_set_gpio_set_12_wd;
  logic gpio_set_gpio_set_12_we;
  logic gpio_set_gpio_set_13_wd;
  logic gpio_set_gpio_set_13_we;
  logic gpio_set_gpio_set_14_wd;
  logic gpio_set_gpio_set_14_we;
  logic gpio_set_gpio_set_15_wd;
  logic gpio_set_gpio_set_15_we;
  logic gpio_set_gpio_set_16_wd;
  logic gpio_set_gpio_set_16_we;
  logic gpio_set_gpio_set_17_wd;
  logic gpio_set_gpio_set_17_we;
  logic gpio_set_gpio_set_18_wd;
  logic gpio_set_gpio_set_18_we;
  logic gpio_set_gpio_set_19_wd;
  logic gpio_set_gpio_set_19_we;
  logic gpio_set_gpio_set_20_wd;
  logic gpio_set_gpio_set_20_we;
  logic gpio_set_gpio_set_21_wd;
  logic gpio_set_gpio_set_21_we;
  logic gpio_set_gpio_set_22_wd;
  logic gpio_set_gpio_set_22_we;
  logic gpio_set_gpio_set_23_wd;
  logic gpio_set_gpio_set_23_we;
  logic gpio_set_gpio_set_24_wd;
  logic gpio_set_gpio_set_24_we;
  logic gpio_set_gpio_set_25_wd;
  logic gpio_set_gpio_set_25_we;
  logic gpio_set_gpio_set_26_wd;
  logic gpio_set_gpio_set_26_we;
  logic gpio_set_gpio_set_27_wd;
  logic gpio_set_gpio_set_27_we;
  logic gpio_set_gpio_set_28_wd;
  logic gpio_set_gpio_set_28_we;
  logic gpio_set_gpio_set_29_wd;
  logic gpio_set_gpio_set_29_we;
  logic gpio_set_gpio_set_30_wd;
  logic gpio_set_gpio_set_30_we;
  logic gpio_set_gpio_set_31_wd;
  logic gpio_set_gpio_set_31_we;
  logic gpio_clear_gpio_clear_0_wd;
  logic gpio_clear_gpio_clear_0_we;
  logic gpio_clear_gpio_clear_1_wd;
  logic gpio_clear_gpio_clear_1_we;
  logic gpio_clear_gpio_clear_2_wd;
  logic gpio_clear_gpio_clear_2_we;
  logic gpio_clear_gpio_clear_3_wd;
  logic gpio_clear_gpio_clear_3_we;
  logic gpio_clear_gpio_clear_4_wd;
  logic gpio_clear_gpio_clear_4_we;
  logic gpio_clear_gpio_clear_5_wd;
  logic gpio_clear_gpio_clear_5_we;
  logic gpio_clear_gpio_clear_6_wd;
  logic gpio_clear_gpio_clear_6_we;
  logic gpio_clear_gpio_clear_7_wd;
  logic gpio_clear_gpio_clear_7_we;
  logic gpio_clear_gpio_clear_8_wd;
  logic gpio_clear_gpio_clear_8_we;
  logic gpio_clear_gpio_clear_9_wd;
  logic gpio_clear_gpio_clear_9_we;
  logic gpio_clear_gpio_clear_10_wd;
  logic gpio_clear_gpio_clear_10_we;
  logic gpio_clear_gpio_clear_11_wd;
  logic gpio_clear_gpio_clear_11_we;
  logic gpio_clear_gpio_clear_12_wd;
  logic gpio_clear_gpio_clear_12_we;
  logic gpio_clear_gpio_clear_13_wd;
  logic gpio_clear_gpio_clear_13_we;
  logic gpio_clear_gpio_clear_14_wd;
  logic gpio_clear_gpio_clear_14_we;
  logic gpio_clear_gpio_clear_15_wd;
  logic gpio_clear_gpio_clear_15_we;
  logic gpio_clear_gpio_clear_16_wd;
  logic gpio_clear_gpio_clear_16_we;
  logic gpio_clear_gpio_clear_17_wd;
  logic gpio_clear_gpio_clear_17_we;
  logic gpio_clear_gpio_clear_18_wd;
  logic gpio_clear_gpio_clear_18_we;
  logic gpio_clear_gpio_clear_19_wd;
  logic gpio_clear_gpio_clear_19_we;
  logic gpio_clear_gpio_clear_20_wd;
  logic gpio_clear_gpio_clear_20_we;
  logic gpio_clear_gpio_clear_21_wd;
  logic gpio_clear_gpio_clear_21_we;
  logic gpio_clear_gpio_clear_22_wd;
  logic gpio_clear_gpio_clear_22_we;
  logic gpio_clear_gpio_clear_23_wd;
  logic gpio_clear_gpio_clear_23_we;
  logic gpio_clear_gpio_clear_24_wd;
  logic gpio_clear_gpio_clear_24_we;
  logic gpio_clear_gpio_clear_25_wd;
  logic gpio_clear_gpio_clear_25_we;
  logic gpio_clear_gpio_clear_26_wd;
  logic gpio_clear_gpio_clear_26_we;
  logic gpio_clear_gpio_clear_27_wd;
  logic gpio_clear_gpio_clear_27_we;
  logic gpio_clear_gpio_clear_28_wd;
  logic gpio_clear_gpio_clear_28_we;
  logic gpio_clear_gpio_clear_29_wd;
  logic gpio_clear_gpio_clear_29_we;
  logic gpio_clear_gpio_clear_30_wd;
  logic gpio_clear_gpio_clear_30_we;
  logic gpio_clear_gpio_clear_31_wd;
  logic gpio_clear_gpio_clear_31_we;
  logic gpio_toggle_gpio_toggle_0_wd;
  logic gpio_toggle_gpio_toggle_0_we;
  logic gpio_toggle_gpio_toggle_1_wd;
  logic gpio_toggle_gpio_toggle_1_we;
  logic gpio_toggle_gpio_toggle_2_wd;
  logic gpio_toggle_gpio_toggle_2_we;
  logic gpio_toggle_gpio_toggle_3_wd;
  logic gpio_toggle_gpio_toggle_3_we;
  logic gpio_toggle_gpio_toggle_4_wd;
  logic gpio_toggle_gpio_toggle_4_we;
  logic gpio_toggle_gpio_toggle_5_wd;
  logic gpio_toggle_gpio_toggle_5_we;
  logic gpio_toggle_gpio_toggle_6_wd;
  logic gpio_toggle_gpio_toggle_6_we;
  logic gpio_toggle_gpio_toggle_7_wd;
  logic gpio_toggle_gpio_toggle_7_we;
  logic gpio_toggle_gpio_toggle_8_wd;
  logic gpio_toggle_gpio_toggle_8_we;
  logic gpio_toggle_gpio_toggle_9_wd;
  logic gpio_toggle_gpio_toggle_9_we;
  logic gpio_toggle_gpio_toggle_10_wd;
  logic gpio_toggle_gpio_toggle_10_we;
  logic gpio_toggle_gpio_toggle_11_wd;
  logic gpio_toggle_gpio_toggle_11_we;
  logic gpio_toggle_gpio_toggle_12_wd;
  logic gpio_toggle_gpio_toggle_12_we;
  logic gpio_toggle_gpio_toggle_13_wd;
  logic gpio_toggle_gpio_toggle_13_we;
  logic gpio_toggle_gpio_toggle_14_wd;
  logic gpio_toggle_gpio_toggle_14_we;
  logic gpio_toggle_gpio_toggle_15_wd;
  logic gpio_toggle_gpio_toggle_15_we;
  logic gpio_toggle_gpio_toggle_16_wd;
  logic gpio_toggle_gpio_toggle_16_we;
  logic gpio_toggle_gpio_toggle_17_wd;
  logic gpio_toggle_gpio_toggle_17_we;
  logic gpio_toggle_gpio_toggle_18_wd;
  logic gpio_toggle_gpio_toggle_18_we;
  logic gpio_toggle_gpio_toggle_19_wd;
  logic gpio_toggle_gpio_toggle_19_we;
  logic gpio_toggle_gpio_toggle_20_wd;
  logic gpio_toggle_gpio_toggle_20_we;
  logic gpio_toggle_gpio_toggle_21_wd;
  logic gpio_toggle_gpio_toggle_21_we;
  logic gpio_toggle_gpio_toggle_22_wd;
  logic gpio_toggle_gpio_toggle_22_we;
  logic gpio_toggle_gpio_toggle_23_wd;
  logic gpio_toggle_gpio_toggle_23_we;
  logic gpio_toggle_gpio_toggle_24_wd;
  logic gpio_toggle_gpio_toggle_24_we;
  logic gpio_toggle_gpio_toggle_25_wd;
  logic gpio_toggle_gpio_toggle_25_we;
  logic gpio_toggle_gpio_toggle_26_wd;
  logic gpio_toggle_gpio_toggle_26_we;
  logic gpio_toggle_gpio_toggle_27_wd;
  logic gpio_toggle_gpio_toggle_27_we;
  logic gpio_toggle_gpio_toggle_28_wd;
  logic gpio_toggle_gpio_toggle_28_we;
  logic gpio_toggle_gpio_toggle_29_wd;
  logic gpio_toggle_gpio_toggle_29_we;
  logic gpio_toggle_gpio_toggle_30_wd;
  logic gpio_toggle_gpio_toggle_30_we;
  logic gpio_toggle_gpio_toggle_31_wd;
  logic gpio_toggle_gpio_toggle_31_we;
  logic intrpt_rise_en_intrpt_rise_en_0_qs;
  logic intrpt_rise_en_intrpt_rise_en_0_wd;
  logic intrpt_rise_en_intrpt_rise_en_0_we;
  logic intrpt_rise_en_intrpt_rise_en_1_qs;
  logic intrpt_rise_en_intrpt_rise_en_1_wd;
  logic intrpt_rise_en_intrpt_rise_en_1_we;
  logic intrpt_rise_en_intrpt_rise_en_2_qs;
  logic intrpt_rise_en_intrpt_rise_en_2_wd;
  logic intrpt_rise_en_intrpt_rise_en_2_we;
  logic intrpt_rise_en_intrpt_rise_en_3_qs;
  logic intrpt_rise_en_intrpt_rise_en_3_wd;
  logic intrpt_rise_en_intrpt_rise_en_3_we;
  logic intrpt_rise_en_intrpt_rise_en_4_qs;
  logic intrpt_rise_en_intrpt_rise_en_4_wd;
  logic intrpt_rise_en_intrpt_rise_en_4_we;
  logic intrpt_rise_en_intrpt_rise_en_5_qs;
  logic intrpt_rise_en_intrpt_rise_en_5_wd;
  logic intrpt_rise_en_intrpt_rise_en_5_we;
  logic intrpt_rise_en_intrpt_rise_en_6_qs;
  logic intrpt_rise_en_intrpt_rise_en_6_wd;
  logic intrpt_rise_en_intrpt_rise_en_6_we;
  logic intrpt_rise_en_intrpt_rise_en_7_qs;
  logic intrpt_rise_en_intrpt_rise_en_7_wd;
  logic intrpt_rise_en_intrpt_rise_en_7_we;
  logic intrpt_rise_en_intrpt_rise_en_8_qs;
  logic intrpt_rise_en_intrpt_rise_en_8_wd;
  logic intrpt_rise_en_intrpt_rise_en_8_we;
  logic intrpt_rise_en_intrpt_rise_en_9_qs;
  logic intrpt_rise_en_intrpt_rise_en_9_wd;
  logic intrpt_rise_en_intrpt_rise_en_9_we;
  logic intrpt_rise_en_intrpt_rise_en_10_qs;
  logic intrpt_rise_en_intrpt_rise_en_10_wd;
  logic intrpt_rise_en_intrpt_rise_en_10_we;
  logic intrpt_rise_en_intrpt_rise_en_11_qs;
  logic intrpt_rise_en_intrpt_rise_en_11_wd;
  logic intrpt_rise_en_intrpt_rise_en_11_we;
  logic intrpt_rise_en_intrpt_rise_en_12_qs;
  logic intrpt_rise_en_intrpt_rise_en_12_wd;
  logic intrpt_rise_en_intrpt_rise_en_12_we;
  logic intrpt_rise_en_intrpt_rise_en_13_qs;
  logic intrpt_rise_en_intrpt_rise_en_13_wd;
  logic intrpt_rise_en_intrpt_rise_en_13_we;
  logic intrpt_rise_en_intrpt_rise_en_14_qs;
  logic intrpt_rise_en_intrpt_rise_en_14_wd;
  logic intrpt_rise_en_intrpt_rise_en_14_we;
  logic intrpt_rise_en_intrpt_rise_en_15_qs;
  logic intrpt_rise_en_intrpt_rise_en_15_wd;
  logic intrpt_rise_en_intrpt_rise_en_15_we;
  logic intrpt_rise_en_intrpt_rise_en_16_qs;
  logic intrpt_rise_en_intrpt_rise_en_16_wd;
  logic intrpt_rise_en_intrpt_rise_en_16_we;
  logic intrpt_rise_en_intrpt_rise_en_17_qs;
  logic intrpt_rise_en_intrpt_rise_en_17_wd;
  logic intrpt_rise_en_intrpt_rise_en_17_we;
  logic intrpt_rise_en_intrpt_rise_en_18_qs;
  logic intrpt_rise_en_intrpt_rise_en_18_wd;
  logic intrpt_rise_en_intrpt_rise_en_18_we;
  logic intrpt_rise_en_intrpt_rise_en_19_qs;
  logic intrpt_rise_en_intrpt_rise_en_19_wd;
  logic intrpt_rise_en_intrpt_rise_en_19_we;
  logic intrpt_rise_en_intrpt_rise_en_20_qs;
  logic intrpt_rise_en_intrpt_rise_en_20_wd;
  logic intrpt_rise_en_intrpt_rise_en_20_we;
  logic intrpt_rise_en_intrpt_rise_en_21_qs;
  logic intrpt_rise_en_intrpt_rise_en_21_wd;
  logic intrpt_rise_en_intrpt_rise_en_21_we;
  logic intrpt_rise_en_intrpt_rise_en_22_qs;
  logic intrpt_rise_en_intrpt_rise_en_22_wd;
  logic intrpt_rise_en_intrpt_rise_en_22_we;
  logic intrpt_rise_en_intrpt_rise_en_23_qs;
  logic intrpt_rise_en_intrpt_rise_en_23_wd;
  logic intrpt_rise_en_intrpt_rise_en_23_we;
  logic intrpt_rise_en_intrpt_rise_en_24_qs;
  logic intrpt_rise_en_intrpt_rise_en_24_wd;
  logic intrpt_rise_en_intrpt_rise_en_24_we;
  logic intrpt_rise_en_intrpt_rise_en_25_qs;
  logic intrpt_rise_en_intrpt_rise_en_25_wd;
  logic intrpt_rise_en_intrpt_rise_en_25_we;
  logic intrpt_rise_en_intrpt_rise_en_26_qs;
  logic intrpt_rise_en_intrpt_rise_en_26_wd;
  logic intrpt_rise_en_intrpt_rise_en_26_we;
  logic intrpt_rise_en_intrpt_rise_en_27_qs;
  logic intrpt_rise_en_intrpt_rise_en_27_wd;
  logic intrpt_rise_en_intrpt_rise_en_27_we;
  logic intrpt_rise_en_intrpt_rise_en_28_qs;
  logic intrpt_rise_en_intrpt_rise_en_28_wd;
  logic intrpt_rise_en_intrpt_rise_en_28_we;
  logic intrpt_rise_en_intrpt_rise_en_29_qs;
  logic intrpt_rise_en_intrpt_rise_en_29_wd;
  logic intrpt_rise_en_intrpt_rise_en_29_we;
  logic intrpt_rise_en_intrpt_rise_en_30_qs;
  logic intrpt_rise_en_intrpt_rise_en_30_wd;
  logic intrpt_rise_en_intrpt_rise_en_30_we;
  logic intrpt_rise_en_intrpt_rise_en_31_qs;
  logic intrpt_rise_en_intrpt_rise_en_31_wd;
  logic intrpt_rise_en_intrpt_rise_en_31_we;
  logic intrpt_fall_en_intrpt_fall_en_0_qs;
  logic intrpt_fall_en_intrpt_fall_en_0_wd;
  logic intrpt_fall_en_intrpt_fall_en_0_we;
  logic intrpt_fall_en_intrpt_fall_en_1_qs;
  logic intrpt_fall_en_intrpt_fall_en_1_wd;
  logic intrpt_fall_en_intrpt_fall_en_1_we;
  logic intrpt_fall_en_intrpt_fall_en_2_qs;
  logic intrpt_fall_en_intrpt_fall_en_2_wd;
  logic intrpt_fall_en_intrpt_fall_en_2_we;
  logic intrpt_fall_en_intrpt_fall_en_3_qs;
  logic intrpt_fall_en_intrpt_fall_en_3_wd;
  logic intrpt_fall_en_intrpt_fall_en_3_we;
  logic intrpt_fall_en_intrpt_fall_en_4_qs;
  logic intrpt_fall_en_intrpt_fall_en_4_wd;
  logic intrpt_fall_en_intrpt_fall_en_4_we;
  logic intrpt_fall_en_intrpt_fall_en_5_qs;
  logic intrpt_fall_en_intrpt_fall_en_5_wd;
  logic intrpt_fall_en_intrpt_fall_en_5_we;
  logic intrpt_fall_en_intrpt_fall_en_6_qs;
  logic intrpt_fall_en_intrpt_fall_en_6_wd;
  logic intrpt_fall_en_intrpt_fall_en_6_we;
  logic intrpt_fall_en_intrpt_fall_en_7_qs;
  logic intrpt_fall_en_intrpt_fall_en_7_wd;
  logic intrpt_fall_en_intrpt_fall_en_7_we;
  logic intrpt_fall_en_intrpt_fall_en_8_qs;
  logic intrpt_fall_en_intrpt_fall_en_8_wd;
  logic intrpt_fall_en_intrpt_fall_en_8_we;
  logic intrpt_fall_en_intrpt_fall_en_9_qs;
  logic intrpt_fall_en_intrpt_fall_en_9_wd;
  logic intrpt_fall_en_intrpt_fall_en_9_we;
  logic intrpt_fall_en_intrpt_fall_en_10_qs;
  logic intrpt_fall_en_intrpt_fall_en_10_wd;
  logic intrpt_fall_en_intrpt_fall_en_10_we;
  logic intrpt_fall_en_intrpt_fall_en_11_qs;
  logic intrpt_fall_en_intrpt_fall_en_11_wd;
  logic intrpt_fall_en_intrpt_fall_en_11_we;
  logic intrpt_fall_en_intrpt_fall_en_12_qs;
  logic intrpt_fall_en_intrpt_fall_en_12_wd;
  logic intrpt_fall_en_intrpt_fall_en_12_we;
  logic intrpt_fall_en_intrpt_fall_en_13_qs;
  logic intrpt_fall_en_intrpt_fall_en_13_wd;
  logic intrpt_fall_en_intrpt_fall_en_13_we;
  logic intrpt_fall_en_intrpt_fall_en_14_qs;
  logic intrpt_fall_en_intrpt_fall_en_14_wd;
  logic intrpt_fall_en_intrpt_fall_en_14_we;
  logic intrpt_fall_en_intrpt_fall_en_15_qs;
  logic intrpt_fall_en_intrpt_fall_en_15_wd;
  logic intrpt_fall_en_intrpt_fall_en_15_we;
  logic intrpt_fall_en_intrpt_fall_en_16_qs;
  logic intrpt_fall_en_intrpt_fall_en_16_wd;
  logic intrpt_fall_en_intrpt_fall_en_16_we;
  logic intrpt_fall_en_intrpt_fall_en_17_qs;
  logic intrpt_fall_en_intrpt_fall_en_17_wd;
  logic intrpt_fall_en_intrpt_fall_en_17_we;
  logic intrpt_fall_en_intrpt_fall_en_18_qs;
  logic intrpt_fall_en_intrpt_fall_en_18_wd;
  logic intrpt_fall_en_intrpt_fall_en_18_we;
  logic intrpt_fall_en_intrpt_fall_en_19_qs;
  logic intrpt_fall_en_intrpt_fall_en_19_wd;
  logic intrpt_fall_en_intrpt_fall_en_19_we;
  logic intrpt_fall_en_intrpt_fall_en_20_qs;
  logic intrpt_fall_en_intrpt_fall_en_20_wd;
  logic intrpt_fall_en_intrpt_fall_en_20_we;
  logic intrpt_fall_en_intrpt_fall_en_21_qs;
  logic intrpt_fall_en_intrpt_fall_en_21_wd;
  logic intrpt_fall_en_intrpt_fall_en_21_we;
  logic intrpt_fall_en_intrpt_fall_en_22_qs;
  logic intrpt_fall_en_intrpt_fall_en_22_wd;
  logic intrpt_fall_en_intrpt_fall_en_22_we;
  logic intrpt_fall_en_intrpt_fall_en_23_qs;
  logic intrpt_fall_en_intrpt_fall_en_23_wd;
  logic intrpt_fall_en_intrpt_fall_en_23_we;
  logic intrpt_fall_en_intrpt_fall_en_24_qs;
  logic intrpt_fall_en_intrpt_fall_en_24_wd;
  logic intrpt_fall_en_intrpt_fall_en_24_we;
  logic intrpt_fall_en_intrpt_fall_en_25_qs;
  logic intrpt_fall_en_intrpt_fall_en_25_wd;
  logic intrpt_fall_en_intrpt_fall_en_25_we;
  logic intrpt_fall_en_intrpt_fall_en_26_qs;
  logic intrpt_fall_en_intrpt_fall_en_26_wd;
  logic intrpt_fall_en_intrpt_fall_en_26_we;
  logic intrpt_fall_en_intrpt_fall_en_27_qs;
  logic intrpt_fall_en_intrpt_fall_en_27_wd;
  logic intrpt_fall_en_intrpt_fall_en_27_we;
  logic intrpt_fall_en_intrpt_fall_en_28_qs;
  logic intrpt_fall_en_intrpt_fall_en_28_wd;
  logic intrpt_fall_en_intrpt_fall_en_28_we;
  logic intrpt_fall_en_intrpt_fall_en_29_qs;
  logic intrpt_fall_en_intrpt_fall_en_29_wd;
  logic intrpt_fall_en_intrpt_fall_en_29_we;
  logic intrpt_fall_en_intrpt_fall_en_30_qs;
  logic intrpt_fall_en_intrpt_fall_en_30_wd;
  logic intrpt_fall_en_intrpt_fall_en_30_we;
  logic intrpt_fall_en_intrpt_fall_en_31_qs;
  logic intrpt_fall_en_intrpt_fall_en_31_wd;
  logic intrpt_fall_en_intrpt_fall_en_31_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_0_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_0_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_0_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_1_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_1_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_1_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_2_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_2_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_2_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_3_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_3_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_3_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_4_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_4_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_4_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_5_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_5_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_5_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_6_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_6_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_6_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_7_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_7_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_7_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_8_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_8_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_8_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_9_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_9_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_9_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_10_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_10_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_10_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_11_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_11_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_11_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_12_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_12_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_12_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_13_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_13_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_13_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_14_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_14_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_14_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_15_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_15_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_15_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_16_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_16_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_16_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_17_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_17_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_17_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_18_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_18_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_18_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_19_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_19_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_19_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_20_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_20_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_20_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_21_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_21_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_21_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_22_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_22_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_22_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_23_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_23_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_23_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_24_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_24_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_24_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_25_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_25_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_25_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_26_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_26_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_26_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_27_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_27_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_27_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_28_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_28_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_28_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_29_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_29_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_29_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_30_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_30_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_30_we;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_31_qs;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_31_wd;
  logic intrpt_lvl_high_en_intrpt_lvl_high_en_31_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_0_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_0_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_0_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_1_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_1_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_1_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_2_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_2_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_2_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_3_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_3_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_3_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_4_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_4_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_4_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_5_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_5_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_5_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_6_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_6_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_6_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_7_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_7_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_7_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_8_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_8_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_8_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_9_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_9_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_9_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_10_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_10_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_10_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_11_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_11_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_11_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_12_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_12_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_12_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_13_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_13_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_13_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_14_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_14_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_14_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_15_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_15_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_15_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_16_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_16_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_16_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_17_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_17_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_17_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_18_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_18_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_18_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_19_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_19_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_19_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_20_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_20_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_20_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_21_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_21_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_21_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_22_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_22_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_22_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_23_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_23_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_23_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_24_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_24_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_24_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_25_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_25_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_25_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_26_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_26_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_26_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_27_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_27_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_27_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_28_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_28_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_28_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_29_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_29_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_29_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_30_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_30_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_30_we;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_31_qs;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_31_wd;
  logic intrpt_lvl_low_en_intrpt_lvl_low_en_31_we;
  logic intrpt_status_intrpt_status_0_qs;
  logic intrpt_status_intrpt_status_0_wd;
  logic intrpt_status_intrpt_status_0_we;
  logic intrpt_status_intrpt_status_0_re;
  logic intrpt_status_intrpt_status_1_qs;
  logic intrpt_status_intrpt_status_1_wd;
  logic intrpt_status_intrpt_status_1_we;
  logic intrpt_status_intrpt_status_1_re;
  logic intrpt_status_intrpt_status_2_qs;
  logic intrpt_status_intrpt_status_2_wd;
  logic intrpt_status_intrpt_status_2_we;
  logic intrpt_status_intrpt_status_2_re;
  logic intrpt_status_intrpt_status_3_qs;
  logic intrpt_status_intrpt_status_3_wd;
  logic intrpt_status_intrpt_status_3_we;
  logic intrpt_status_intrpt_status_3_re;
  logic intrpt_status_intrpt_status_4_qs;
  logic intrpt_status_intrpt_status_4_wd;
  logic intrpt_status_intrpt_status_4_we;
  logic intrpt_status_intrpt_status_4_re;
  logic intrpt_status_intrpt_status_5_qs;
  logic intrpt_status_intrpt_status_5_wd;
  logic intrpt_status_intrpt_status_5_we;
  logic intrpt_status_intrpt_status_5_re;
  logic intrpt_status_intrpt_status_6_qs;
  logic intrpt_status_intrpt_status_6_wd;
  logic intrpt_status_intrpt_status_6_we;
  logic intrpt_status_intrpt_status_6_re;
  logic intrpt_status_intrpt_status_7_qs;
  logic intrpt_status_intrpt_status_7_wd;
  logic intrpt_status_intrpt_status_7_we;
  logic intrpt_status_intrpt_status_7_re;
  logic intrpt_status_intrpt_status_8_qs;
  logic intrpt_status_intrpt_status_8_wd;
  logic intrpt_status_intrpt_status_8_we;
  logic intrpt_status_intrpt_status_8_re;
  logic intrpt_status_intrpt_status_9_qs;
  logic intrpt_status_intrpt_status_9_wd;
  logic intrpt_status_intrpt_status_9_we;
  logic intrpt_status_intrpt_status_9_re;
  logic intrpt_status_intrpt_status_10_qs;
  logic intrpt_status_intrpt_status_10_wd;
  logic intrpt_status_intrpt_status_10_we;
  logic intrpt_status_intrpt_status_10_re;
  logic intrpt_status_intrpt_status_11_qs;
  logic intrpt_status_intrpt_status_11_wd;
  logic intrpt_status_intrpt_status_11_we;
  logic intrpt_status_intrpt_status_11_re;
  logic intrpt_status_intrpt_status_12_qs;
  logic intrpt_status_intrpt_status_12_wd;
  logic intrpt_status_intrpt_status_12_we;
  logic intrpt_status_intrpt_status_12_re;
  logic intrpt_status_intrpt_status_13_qs;
  logic intrpt_status_intrpt_status_13_wd;
  logic intrpt_status_intrpt_status_13_we;
  logic intrpt_status_intrpt_status_13_re;
  logic intrpt_status_intrpt_status_14_qs;
  logic intrpt_status_intrpt_status_14_wd;
  logic intrpt_status_intrpt_status_14_we;
  logic intrpt_status_intrpt_status_14_re;
  logic intrpt_status_intrpt_status_15_qs;
  logic intrpt_status_intrpt_status_15_wd;
  logic intrpt_status_intrpt_status_15_we;
  logic intrpt_status_intrpt_status_15_re;
  logic intrpt_status_intrpt_status_16_qs;
  logic intrpt_status_intrpt_status_16_wd;
  logic intrpt_status_intrpt_status_16_we;
  logic intrpt_status_intrpt_status_16_re;
  logic intrpt_status_intrpt_status_17_qs;
  logic intrpt_status_intrpt_status_17_wd;
  logic intrpt_status_intrpt_status_17_we;
  logic intrpt_status_intrpt_status_17_re;
  logic intrpt_status_intrpt_status_18_qs;
  logic intrpt_status_intrpt_status_18_wd;
  logic intrpt_status_intrpt_status_18_we;
  logic intrpt_status_intrpt_status_18_re;
  logic intrpt_status_intrpt_status_19_qs;
  logic intrpt_status_intrpt_status_19_wd;
  logic intrpt_status_intrpt_status_19_we;
  logic intrpt_status_intrpt_status_19_re;
  logic intrpt_status_intrpt_status_20_qs;
  logic intrpt_status_intrpt_status_20_wd;
  logic intrpt_status_intrpt_status_20_we;
  logic intrpt_status_intrpt_status_20_re;
  logic intrpt_status_intrpt_status_21_qs;
  logic intrpt_status_intrpt_status_21_wd;
  logic intrpt_status_intrpt_status_21_we;
  logic intrpt_status_intrpt_status_21_re;
  logic intrpt_status_intrpt_status_22_qs;
  logic intrpt_status_intrpt_status_22_wd;
  logic intrpt_status_intrpt_status_22_we;
  logic intrpt_status_intrpt_status_22_re;
  logic intrpt_status_intrpt_status_23_qs;
  logic intrpt_status_intrpt_status_23_wd;
  logic intrpt_status_intrpt_status_23_we;
  logic intrpt_status_intrpt_status_23_re;
  logic intrpt_status_intrpt_status_24_qs;
  logic intrpt_status_intrpt_status_24_wd;
  logic intrpt_status_intrpt_status_24_we;
  logic intrpt_status_intrpt_status_24_re;
  logic intrpt_status_intrpt_status_25_qs;
  logic intrpt_status_intrpt_status_25_wd;
  logic intrpt_status_intrpt_status_25_we;
  logic intrpt_status_intrpt_status_25_re;
  logic intrpt_status_intrpt_status_26_qs;
  logic intrpt_status_intrpt_status_26_wd;
  logic intrpt_status_intrpt_status_26_we;
  logic intrpt_status_intrpt_status_26_re;
  logic intrpt_status_intrpt_status_27_qs;
  logic intrpt_status_intrpt_status_27_wd;
  logic intrpt_status_intrpt_status_27_we;
  logic intrpt_status_intrpt_status_27_re;
  logic intrpt_status_intrpt_status_28_qs;
  logic intrpt_status_intrpt_status_28_wd;
  logic intrpt_status_intrpt_status_28_we;
  logic intrpt_status_intrpt_status_28_re;
  logic intrpt_status_intrpt_status_29_qs;
  logic intrpt_status_intrpt_status_29_wd;
  logic intrpt_status_intrpt_status_29_we;
  logic intrpt_status_intrpt_status_29_re;
  logic intrpt_status_intrpt_status_30_qs;
  logic intrpt_status_intrpt_status_30_wd;
  logic intrpt_status_intrpt_status_30_we;
  logic intrpt_status_intrpt_status_30_re;
  logic intrpt_status_intrpt_status_31_qs;
  logic intrpt_status_intrpt_status_31_wd;
  logic intrpt_status_intrpt_status_31_we;
  logic intrpt_status_intrpt_status_31_re;
  logic intrpt_rise_status_intrpt_rise_status_0_qs;
  logic intrpt_rise_status_intrpt_rise_status_0_wd;
  logic intrpt_rise_status_intrpt_rise_status_0_we;
  logic intrpt_rise_status_intrpt_rise_status_1_qs;
  logic intrpt_rise_status_intrpt_rise_status_1_wd;
  logic intrpt_rise_status_intrpt_rise_status_1_we;
  logic intrpt_rise_status_intrpt_rise_status_2_qs;
  logic intrpt_rise_status_intrpt_rise_status_2_wd;
  logic intrpt_rise_status_intrpt_rise_status_2_we;
  logic intrpt_rise_status_intrpt_rise_status_3_qs;
  logic intrpt_rise_status_intrpt_rise_status_3_wd;
  logic intrpt_rise_status_intrpt_rise_status_3_we;
  logic intrpt_rise_status_intrpt_rise_status_4_qs;
  logic intrpt_rise_status_intrpt_rise_status_4_wd;
  logic intrpt_rise_status_intrpt_rise_status_4_we;
  logic intrpt_rise_status_intrpt_rise_status_5_qs;
  logic intrpt_rise_status_intrpt_rise_status_5_wd;
  logic intrpt_rise_status_intrpt_rise_status_5_we;
  logic intrpt_rise_status_intrpt_rise_status_6_qs;
  logic intrpt_rise_status_intrpt_rise_status_6_wd;
  logic intrpt_rise_status_intrpt_rise_status_6_we;
  logic intrpt_rise_status_intrpt_rise_status_7_qs;
  logic intrpt_rise_status_intrpt_rise_status_7_wd;
  logic intrpt_rise_status_intrpt_rise_status_7_we;
  logic intrpt_rise_status_intrpt_rise_status_8_qs;
  logic intrpt_rise_status_intrpt_rise_status_8_wd;
  logic intrpt_rise_status_intrpt_rise_status_8_we;
  logic intrpt_rise_status_intrpt_rise_status_9_qs;
  logic intrpt_rise_status_intrpt_rise_status_9_wd;
  logic intrpt_rise_status_intrpt_rise_status_9_we;
  logic intrpt_rise_status_intrpt_rise_status_10_qs;
  logic intrpt_rise_status_intrpt_rise_status_10_wd;
  logic intrpt_rise_status_intrpt_rise_status_10_we;
  logic intrpt_rise_status_intrpt_rise_status_11_qs;
  logic intrpt_rise_status_intrpt_rise_status_11_wd;
  logic intrpt_rise_status_intrpt_rise_status_11_we;
  logic intrpt_rise_status_intrpt_rise_status_12_qs;
  logic intrpt_rise_status_intrpt_rise_status_12_wd;
  logic intrpt_rise_status_intrpt_rise_status_12_we;
  logic intrpt_rise_status_intrpt_rise_status_13_qs;
  logic intrpt_rise_status_intrpt_rise_status_13_wd;
  logic intrpt_rise_status_intrpt_rise_status_13_we;
  logic intrpt_rise_status_intrpt_rise_status_14_qs;
  logic intrpt_rise_status_intrpt_rise_status_14_wd;
  logic intrpt_rise_status_intrpt_rise_status_14_we;
  logic intrpt_rise_status_intrpt_rise_status_15_qs;
  logic intrpt_rise_status_intrpt_rise_status_15_wd;
  logic intrpt_rise_status_intrpt_rise_status_15_we;
  logic intrpt_rise_status_intrpt_rise_status_16_qs;
  logic intrpt_rise_status_intrpt_rise_status_16_wd;
  logic intrpt_rise_status_intrpt_rise_status_16_we;
  logic intrpt_rise_status_intrpt_rise_status_17_qs;
  logic intrpt_rise_status_intrpt_rise_status_17_wd;
  logic intrpt_rise_status_intrpt_rise_status_17_we;
  logic intrpt_rise_status_intrpt_rise_status_18_qs;
  logic intrpt_rise_status_intrpt_rise_status_18_wd;
  logic intrpt_rise_status_intrpt_rise_status_18_we;
  logic intrpt_rise_status_intrpt_rise_status_19_qs;
  logic intrpt_rise_status_intrpt_rise_status_19_wd;
  logic intrpt_rise_status_intrpt_rise_status_19_we;
  logic intrpt_rise_status_intrpt_rise_status_20_qs;
  logic intrpt_rise_status_intrpt_rise_status_20_wd;
  logic intrpt_rise_status_intrpt_rise_status_20_we;
  logic intrpt_rise_status_intrpt_rise_status_21_qs;
  logic intrpt_rise_status_intrpt_rise_status_21_wd;
  logic intrpt_rise_status_intrpt_rise_status_21_we;
  logic intrpt_rise_status_intrpt_rise_status_22_qs;
  logic intrpt_rise_status_intrpt_rise_status_22_wd;
  logic intrpt_rise_status_intrpt_rise_status_22_we;
  logic intrpt_rise_status_intrpt_rise_status_23_qs;
  logic intrpt_rise_status_intrpt_rise_status_23_wd;
  logic intrpt_rise_status_intrpt_rise_status_23_we;
  logic intrpt_rise_status_intrpt_rise_status_24_qs;
  logic intrpt_rise_status_intrpt_rise_status_24_wd;
  logic intrpt_rise_status_intrpt_rise_status_24_we;
  logic intrpt_rise_status_intrpt_rise_status_25_qs;
  logic intrpt_rise_status_intrpt_rise_status_25_wd;
  logic intrpt_rise_status_intrpt_rise_status_25_we;
  logic intrpt_rise_status_intrpt_rise_status_26_qs;
  logic intrpt_rise_status_intrpt_rise_status_26_wd;
  logic intrpt_rise_status_intrpt_rise_status_26_we;
  logic intrpt_rise_status_intrpt_rise_status_27_qs;
  logic intrpt_rise_status_intrpt_rise_status_27_wd;
  logic intrpt_rise_status_intrpt_rise_status_27_we;
  logic intrpt_rise_status_intrpt_rise_status_28_qs;
  logic intrpt_rise_status_intrpt_rise_status_28_wd;
  logic intrpt_rise_status_intrpt_rise_status_28_we;
  logic intrpt_rise_status_intrpt_rise_status_29_qs;
  logic intrpt_rise_status_intrpt_rise_status_29_wd;
  logic intrpt_rise_status_intrpt_rise_status_29_we;
  logic intrpt_rise_status_intrpt_rise_status_30_qs;
  logic intrpt_rise_status_intrpt_rise_status_30_wd;
  logic intrpt_rise_status_intrpt_rise_status_30_we;
  logic intrpt_rise_status_intrpt_rise_status_31_qs;
  logic intrpt_rise_status_intrpt_rise_status_31_wd;
  logic intrpt_rise_status_intrpt_rise_status_31_we;
  logic intrpt_fall_status_intrpt_fall_status_0_qs;
  logic intrpt_fall_status_intrpt_fall_status_0_wd;
  logic intrpt_fall_status_intrpt_fall_status_0_we;
  logic intrpt_fall_status_intrpt_fall_status_1_qs;
  logic intrpt_fall_status_intrpt_fall_status_1_wd;
  logic intrpt_fall_status_intrpt_fall_status_1_we;
  logic intrpt_fall_status_intrpt_fall_status_2_qs;
  logic intrpt_fall_status_intrpt_fall_status_2_wd;
  logic intrpt_fall_status_intrpt_fall_status_2_we;
  logic intrpt_fall_status_intrpt_fall_status_3_qs;
  logic intrpt_fall_status_intrpt_fall_status_3_wd;
  logic intrpt_fall_status_intrpt_fall_status_3_we;
  logic intrpt_fall_status_intrpt_fall_status_4_qs;
  logic intrpt_fall_status_intrpt_fall_status_4_wd;
  logic intrpt_fall_status_intrpt_fall_status_4_we;
  logic intrpt_fall_status_intrpt_fall_status_5_qs;
  logic intrpt_fall_status_intrpt_fall_status_5_wd;
  logic intrpt_fall_status_intrpt_fall_status_5_we;
  logic intrpt_fall_status_intrpt_fall_status_6_qs;
  logic intrpt_fall_status_intrpt_fall_status_6_wd;
  logic intrpt_fall_status_intrpt_fall_status_6_we;
  logic intrpt_fall_status_intrpt_fall_status_7_qs;
  logic intrpt_fall_status_intrpt_fall_status_7_wd;
  logic intrpt_fall_status_intrpt_fall_status_7_we;
  logic intrpt_fall_status_intrpt_fall_status_8_qs;
  logic intrpt_fall_status_intrpt_fall_status_8_wd;
  logic intrpt_fall_status_intrpt_fall_status_8_we;
  logic intrpt_fall_status_intrpt_fall_status_9_qs;
  logic intrpt_fall_status_intrpt_fall_status_9_wd;
  logic intrpt_fall_status_intrpt_fall_status_9_we;
  logic intrpt_fall_status_intrpt_fall_status_10_qs;
  logic intrpt_fall_status_intrpt_fall_status_10_wd;
  logic intrpt_fall_status_intrpt_fall_status_10_we;
  logic intrpt_fall_status_intrpt_fall_status_11_qs;
  logic intrpt_fall_status_intrpt_fall_status_11_wd;
  logic intrpt_fall_status_intrpt_fall_status_11_we;
  logic intrpt_fall_status_intrpt_fall_status_12_qs;
  logic intrpt_fall_status_intrpt_fall_status_12_wd;
  logic intrpt_fall_status_intrpt_fall_status_12_we;
  logic intrpt_fall_status_intrpt_fall_status_13_qs;
  logic intrpt_fall_status_intrpt_fall_status_13_wd;
  logic intrpt_fall_status_intrpt_fall_status_13_we;
  logic intrpt_fall_status_intrpt_fall_status_14_qs;
  logic intrpt_fall_status_intrpt_fall_status_14_wd;
  logic intrpt_fall_status_intrpt_fall_status_14_we;
  logic intrpt_fall_status_intrpt_fall_status_15_qs;
  logic intrpt_fall_status_intrpt_fall_status_15_wd;
  logic intrpt_fall_status_intrpt_fall_status_15_we;
  logic intrpt_fall_status_intrpt_fall_status_16_qs;
  logic intrpt_fall_status_intrpt_fall_status_16_wd;
  logic intrpt_fall_status_intrpt_fall_status_16_we;
  logic intrpt_fall_status_intrpt_fall_status_17_qs;
  logic intrpt_fall_status_intrpt_fall_status_17_wd;
  logic intrpt_fall_status_intrpt_fall_status_17_we;
  logic intrpt_fall_status_intrpt_fall_status_18_qs;
  logic intrpt_fall_status_intrpt_fall_status_18_wd;
  logic intrpt_fall_status_intrpt_fall_status_18_we;
  logic intrpt_fall_status_intrpt_fall_status_19_qs;
  logic intrpt_fall_status_intrpt_fall_status_19_wd;
  logic intrpt_fall_status_intrpt_fall_status_19_we;
  logic intrpt_fall_status_intrpt_fall_status_20_qs;
  logic intrpt_fall_status_intrpt_fall_status_20_wd;
  logic intrpt_fall_status_intrpt_fall_status_20_we;
  logic intrpt_fall_status_intrpt_fall_status_21_qs;
  logic intrpt_fall_status_intrpt_fall_status_21_wd;
  logic intrpt_fall_status_intrpt_fall_status_21_we;
  logic intrpt_fall_status_intrpt_fall_status_22_qs;
  logic intrpt_fall_status_intrpt_fall_status_22_wd;
  logic intrpt_fall_status_intrpt_fall_status_22_we;
  logic intrpt_fall_status_intrpt_fall_status_23_qs;
  logic intrpt_fall_status_intrpt_fall_status_23_wd;
  logic intrpt_fall_status_intrpt_fall_status_23_we;
  logic intrpt_fall_status_intrpt_fall_status_24_qs;
  logic intrpt_fall_status_intrpt_fall_status_24_wd;
  logic intrpt_fall_status_intrpt_fall_status_24_we;
  logic intrpt_fall_status_intrpt_fall_status_25_qs;
  logic intrpt_fall_status_intrpt_fall_status_25_wd;
  logic intrpt_fall_status_intrpt_fall_status_25_we;
  logic intrpt_fall_status_intrpt_fall_status_26_qs;
  logic intrpt_fall_status_intrpt_fall_status_26_wd;
  logic intrpt_fall_status_intrpt_fall_status_26_we;
  logic intrpt_fall_status_intrpt_fall_status_27_qs;
  logic intrpt_fall_status_intrpt_fall_status_27_wd;
  logic intrpt_fall_status_intrpt_fall_status_27_we;
  logic intrpt_fall_status_intrpt_fall_status_28_qs;
  logic intrpt_fall_status_intrpt_fall_status_28_wd;
  logic intrpt_fall_status_intrpt_fall_status_28_we;
  logic intrpt_fall_status_intrpt_fall_status_29_qs;
  logic intrpt_fall_status_intrpt_fall_status_29_wd;
  logic intrpt_fall_status_intrpt_fall_status_29_we;
  logic intrpt_fall_status_intrpt_fall_status_30_qs;
  logic intrpt_fall_status_intrpt_fall_status_30_wd;
  logic intrpt_fall_status_intrpt_fall_status_30_we;
  logic intrpt_fall_status_intrpt_fall_status_31_qs;
  logic intrpt_fall_status_intrpt_fall_status_31_wd;
  logic intrpt_fall_status_intrpt_fall_status_31_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_0_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_0_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_0_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_1_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_1_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_1_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_2_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_2_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_2_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_3_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_3_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_3_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_4_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_4_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_4_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_5_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_5_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_5_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_6_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_6_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_6_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_7_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_7_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_7_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_8_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_8_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_8_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_9_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_9_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_9_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_10_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_10_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_10_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_11_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_11_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_11_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_12_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_12_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_12_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_13_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_13_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_13_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_14_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_14_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_14_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_15_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_15_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_15_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_16_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_16_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_16_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_17_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_17_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_17_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_18_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_18_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_18_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_19_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_19_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_19_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_20_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_20_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_20_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_21_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_21_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_21_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_22_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_22_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_22_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_23_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_23_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_23_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_24_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_24_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_24_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_25_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_25_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_25_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_26_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_26_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_26_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_27_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_27_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_27_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_28_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_28_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_28_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_29_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_29_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_29_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_30_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_30_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_30_we;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_31_qs;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_31_wd;
  logic intrpt_lvl_high_status_intrpt_lvl_high_status_31_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_0_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_0_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_0_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_1_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_1_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_1_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_2_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_2_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_2_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_3_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_3_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_3_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_4_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_4_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_4_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_5_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_5_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_5_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_6_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_6_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_6_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_7_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_7_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_7_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_8_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_8_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_8_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_9_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_9_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_9_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_10_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_10_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_10_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_11_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_11_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_11_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_12_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_12_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_12_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_13_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_13_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_13_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_14_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_14_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_14_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_15_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_15_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_15_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_16_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_16_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_16_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_17_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_17_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_17_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_18_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_18_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_18_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_19_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_19_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_19_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_20_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_20_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_20_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_21_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_21_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_21_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_22_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_22_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_22_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_23_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_23_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_23_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_24_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_24_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_24_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_25_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_25_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_25_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_26_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_26_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_26_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_27_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_27_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_27_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_28_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_28_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_28_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_29_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_29_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_29_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_30_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_30_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_30_we;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_31_qs;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_31_wd;
  logic intrpt_lvl_low_status_intrpt_lvl_low_status_31_we;

  // Register instances
  // R[info]: V(True)

  //   F[gpio_cnt]: 9:0
  prim_subreg_ext #(
    .DW    (10)
  ) u_info_gpio_cnt (
    .re     (info_gpio_cnt_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.info.gpio_cnt.d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (info_gpio_cnt_qs)
  );


  //   F[version]: 19:10
  prim_subreg_ext #(
    .DW    (10)
  ) u_info_version (
    .re     (info_version_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.info.version.d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (info_version_qs)
  );


  // R[cfg]: V(False)

  //   F[glbl_intrpt_mode]: 0:0
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_cfg_glbl_intrpt_mode (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (cfg_glbl_intrpt_mode_we),
    .wd     (cfg_glbl_intrpt_mode_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cfg.glbl_intrpt_mode.q ),

    // to register interface (read)
    .qs     (cfg_glbl_intrpt_mode_qs)
  );


  //   F[pin_lvl_intrpt_mode]: 1:1
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_cfg_pin_lvl_intrpt_mode (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (cfg_pin_lvl_intrpt_mode_we),
    .wd     (cfg_pin_lvl_intrpt_mode_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.cfg.pin_lvl_intrpt_mode.q ),

    // to register interface (read)
    .qs     (cfg_pin_lvl_intrpt_mode_qs)
  );



  // Subregister 0 of Multireg gpio_mode
  // R[gpio_mode_0]: V(False)

  // F[mode_0]: 1:0
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_0_mode_0 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_0_mode_0_we),
    .wd     (gpio_mode_0_mode_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[0].q ),

    // to register interface (read)
    .qs     (gpio_mode_0_mode_0_qs)
  );


  // F[mode_1]: 3:2
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_0_mode_1 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_0_mode_1_we),
    .wd     (gpio_mode_0_mode_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[1].q ),

    // to register interface (read)
    .qs     (gpio_mode_0_mode_1_qs)
  );


  // F[mode_2]: 5:4
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_0_mode_2 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_0_mode_2_we),
    .wd     (gpio_mode_0_mode_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[2].q ),

    // to register interface (read)
    .qs     (gpio_mode_0_mode_2_qs)
  );


  // F[mode_3]: 7:6
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_0_mode_3 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_0_mode_3_we),
    .wd     (gpio_mode_0_mode_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[3].q ),

    // to register interface (read)
    .qs     (gpio_mode_0_mode_3_qs)
  );


  // F[mode_4]: 9:8
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_0_mode_4 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_0_mode_4_we),
    .wd     (gpio_mode_0_mode_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[4].q ),

    // to register interface (read)
    .qs     (gpio_mode_0_mode_4_qs)
  );


  // F[mode_5]: 11:10
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_0_mode_5 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_0_mode_5_we),
    .wd     (gpio_mode_0_mode_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[5].q ),

    // to register interface (read)
    .qs     (gpio_mode_0_mode_5_qs)
  );


  // F[mode_6]: 13:12
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_0_mode_6 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_0_mode_6_we),
    .wd     (gpio_mode_0_mode_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[6].q ),

    // to register interface (read)
    .qs     (gpio_mode_0_mode_6_qs)
  );


  // F[mode_7]: 15:14
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_0_mode_7 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_0_mode_7_we),
    .wd     (gpio_mode_0_mode_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[7].q ),

    // to register interface (read)
    .qs     (gpio_mode_0_mode_7_qs)
  );


  // F[mode_8]: 17:16
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_0_mode_8 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_0_mode_8_we),
    .wd     (gpio_mode_0_mode_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[8].q ),

    // to register interface (read)
    .qs     (gpio_mode_0_mode_8_qs)
  );


  // F[mode_9]: 19:18
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_0_mode_9 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_0_mode_9_we),
    .wd     (gpio_mode_0_mode_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[9].q ),

    // to register interface (read)
    .qs     (gpio_mode_0_mode_9_qs)
  );


  // F[mode_10]: 21:20
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_0_mode_10 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_0_mode_10_we),
    .wd     (gpio_mode_0_mode_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[10].q ),

    // to register interface (read)
    .qs     (gpio_mode_0_mode_10_qs)
  );


  // F[mode_11]: 23:22
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_0_mode_11 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_0_mode_11_we),
    .wd     (gpio_mode_0_mode_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[11].q ),

    // to register interface (read)
    .qs     (gpio_mode_0_mode_11_qs)
  );


  // F[mode_12]: 25:24
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_0_mode_12 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_0_mode_12_we),
    .wd     (gpio_mode_0_mode_12_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[12].q ),

    // to register interface (read)
    .qs     (gpio_mode_0_mode_12_qs)
  );


  // F[mode_13]: 27:26
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_0_mode_13 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_0_mode_13_we),
    .wd     (gpio_mode_0_mode_13_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[13].q ),

    // to register interface (read)
    .qs     (gpio_mode_0_mode_13_qs)
  );


  // F[mode_14]: 29:28
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_0_mode_14 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_0_mode_14_we),
    .wd     (gpio_mode_0_mode_14_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[14].q ),

    // to register interface (read)
    .qs     (gpio_mode_0_mode_14_qs)
  );


  // F[mode_15]: 31:30
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_0_mode_15 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_0_mode_15_we),
    .wd     (gpio_mode_0_mode_15_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[15].q ),

    // to register interface (read)
    .qs     (gpio_mode_0_mode_15_qs)
  );


  // Subregister 16 of Multireg gpio_mode
  // R[gpio_mode_1]: V(False)

  // F[mode_16]: 1:0
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_1_mode_16 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_1_mode_16_we),
    .wd     (gpio_mode_1_mode_16_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[16].q ),

    // to register interface (read)
    .qs     (gpio_mode_1_mode_16_qs)
  );


  // F[mode_17]: 3:2
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_1_mode_17 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_1_mode_17_we),
    .wd     (gpio_mode_1_mode_17_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[17].q ),

    // to register interface (read)
    .qs     (gpio_mode_1_mode_17_qs)
  );


  // F[mode_18]: 5:4
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_1_mode_18 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_1_mode_18_we),
    .wd     (gpio_mode_1_mode_18_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[18].q ),

    // to register interface (read)
    .qs     (gpio_mode_1_mode_18_qs)
  );


  // F[mode_19]: 7:6
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_1_mode_19 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_1_mode_19_we),
    .wd     (gpio_mode_1_mode_19_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[19].q ),

    // to register interface (read)
    .qs     (gpio_mode_1_mode_19_qs)
  );


  // F[mode_20]: 9:8
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_1_mode_20 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_1_mode_20_we),
    .wd     (gpio_mode_1_mode_20_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[20].q ),

    // to register interface (read)
    .qs     (gpio_mode_1_mode_20_qs)
  );


  // F[mode_21]: 11:10
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_1_mode_21 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_1_mode_21_we),
    .wd     (gpio_mode_1_mode_21_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[21].q ),

    // to register interface (read)
    .qs     (gpio_mode_1_mode_21_qs)
  );


  // F[mode_22]: 13:12
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_1_mode_22 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_1_mode_22_we),
    .wd     (gpio_mode_1_mode_22_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[22].q ),

    // to register interface (read)
    .qs     (gpio_mode_1_mode_22_qs)
  );


  // F[mode_23]: 15:14
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_1_mode_23 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_1_mode_23_we),
    .wd     (gpio_mode_1_mode_23_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[23].q ),

    // to register interface (read)
    .qs     (gpio_mode_1_mode_23_qs)
  );


  // F[mode_24]: 17:16
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_1_mode_24 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_1_mode_24_we),
    .wd     (gpio_mode_1_mode_24_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[24].q ),

    // to register interface (read)
    .qs     (gpio_mode_1_mode_24_qs)
  );


  // F[mode_25]: 19:18
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_1_mode_25 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_1_mode_25_we),
    .wd     (gpio_mode_1_mode_25_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[25].q ),

    // to register interface (read)
    .qs     (gpio_mode_1_mode_25_qs)
  );


  // F[mode_26]: 21:20
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_1_mode_26 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_1_mode_26_we),
    .wd     (gpio_mode_1_mode_26_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[26].q ),

    // to register interface (read)
    .qs     (gpio_mode_1_mode_26_qs)
  );


  // F[mode_27]: 23:22
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_1_mode_27 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_1_mode_27_we),
    .wd     (gpio_mode_1_mode_27_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[27].q ),

    // to register interface (read)
    .qs     (gpio_mode_1_mode_27_qs)
  );


  // F[mode_28]: 25:24
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_1_mode_28 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_1_mode_28_we),
    .wd     (gpio_mode_1_mode_28_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[28].q ),

    // to register interface (read)
    .qs     (gpio_mode_1_mode_28_qs)
  );


  // F[mode_29]: 27:26
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_1_mode_29 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_1_mode_29_we),
    .wd     (gpio_mode_1_mode_29_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[29].q ),

    // to register interface (read)
    .qs     (gpio_mode_1_mode_29_qs)
  );


  // F[mode_30]: 29:28
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_1_mode_30 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_1_mode_30_we),
    .wd     (gpio_mode_1_mode_30_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[30].q ),

    // to register interface (read)
    .qs     (gpio_mode_1_mode_30_qs)
  );


  // F[mode_31]: 31:30
  prim_subreg #(
    .DW      (2),
    .SWACCESS("RW"),
    .RESVAL  (2'h0)
  ) u_gpio_mode_1_mode_31 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_mode_1_mode_31_we),
    .wd     (gpio_mode_1_mode_31_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_mode[31].q ),

    // to register interface (read)
    .qs     (gpio_mode_1_mode_31_qs)
  );




  // Subregister 0 of Multireg gpio_en
  // R[gpio_en]: V(False)

  // F[gpio_en_0]: 0:0
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_0 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_0_we),
    .wd     (gpio_en_gpio_en_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[0].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_0_qs)
  );


  // F[gpio_en_1]: 1:1
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_1 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_1_we),
    .wd     (gpio_en_gpio_en_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[1].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_1_qs)
  );


  // F[gpio_en_2]: 2:2
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_2 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_2_we),
    .wd     (gpio_en_gpio_en_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[2].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_2_qs)
  );


  // F[gpio_en_3]: 3:3
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_3 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_3_we),
    .wd     (gpio_en_gpio_en_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[3].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_3_qs)
  );


  // F[gpio_en_4]: 4:4
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_4 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_4_we),
    .wd     (gpio_en_gpio_en_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[4].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_4_qs)
  );


  // F[gpio_en_5]: 5:5
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_5 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_5_we),
    .wd     (gpio_en_gpio_en_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[5].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_5_qs)
  );


  // F[gpio_en_6]: 6:6
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_6 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_6_we),
    .wd     (gpio_en_gpio_en_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[6].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_6_qs)
  );


  // F[gpio_en_7]: 7:7
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_7 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_7_we),
    .wd     (gpio_en_gpio_en_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[7].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_7_qs)
  );


  // F[gpio_en_8]: 8:8
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_8 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_8_we),
    .wd     (gpio_en_gpio_en_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[8].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_8_qs)
  );


  // F[gpio_en_9]: 9:9
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_9 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_9_we),
    .wd     (gpio_en_gpio_en_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[9].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_9_qs)
  );


  // F[gpio_en_10]: 10:10
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_10 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_10_we),
    .wd     (gpio_en_gpio_en_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[10].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_10_qs)
  );


  // F[gpio_en_11]: 11:11
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_11 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_11_we),
    .wd     (gpio_en_gpio_en_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[11].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_11_qs)
  );


  // F[gpio_en_12]: 12:12
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_12 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_12_we),
    .wd     (gpio_en_gpio_en_12_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[12].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_12_qs)
  );


  // F[gpio_en_13]: 13:13
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_13 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_13_we),
    .wd     (gpio_en_gpio_en_13_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[13].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_13_qs)
  );


  // F[gpio_en_14]: 14:14
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_14 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_14_we),
    .wd     (gpio_en_gpio_en_14_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[14].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_14_qs)
  );


  // F[gpio_en_15]: 15:15
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_15 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_15_we),
    .wd     (gpio_en_gpio_en_15_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[15].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_15_qs)
  );


  // F[gpio_en_16]: 16:16
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_16 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_16_we),
    .wd     (gpio_en_gpio_en_16_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[16].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_16_qs)
  );


  // F[gpio_en_17]: 17:17
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_17 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_17_we),
    .wd     (gpio_en_gpio_en_17_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[17].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_17_qs)
  );


  // F[gpio_en_18]: 18:18
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_18 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_18_we),
    .wd     (gpio_en_gpio_en_18_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[18].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_18_qs)
  );


  // F[gpio_en_19]: 19:19
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_19 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_19_we),
    .wd     (gpio_en_gpio_en_19_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[19].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_19_qs)
  );


  // F[gpio_en_20]: 20:20
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_20 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_20_we),
    .wd     (gpio_en_gpio_en_20_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[20].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_20_qs)
  );


  // F[gpio_en_21]: 21:21
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_21 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_21_we),
    .wd     (gpio_en_gpio_en_21_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[21].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_21_qs)
  );


  // F[gpio_en_22]: 22:22
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_22 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_22_we),
    .wd     (gpio_en_gpio_en_22_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[22].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_22_qs)
  );


  // F[gpio_en_23]: 23:23
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_23 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_23_we),
    .wd     (gpio_en_gpio_en_23_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[23].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_23_qs)
  );


  // F[gpio_en_24]: 24:24
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_24 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_24_we),
    .wd     (gpio_en_gpio_en_24_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[24].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_24_qs)
  );


  // F[gpio_en_25]: 25:25
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_25 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_25_we),
    .wd     (gpio_en_gpio_en_25_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[25].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_25_qs)
  );


  // F[gpio_en_26]: 26:26
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_26 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_26_we),
    .wd     (gpio_en_gpio_en_26_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[26].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_26_qs)
  );


  // F[gpio_en_27]: 27:27
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_27 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_27_we),
    .wd     (gpio_en_gpio_en_27_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[27].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_27_qs)
  );


  // F[gpio_en_28]: 28:28
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_28 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_28_we),
    .wd     (gpio_en_gpio_en_28_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[28].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_28_qs)
  );


  // F[gpio_en_29]: 29:29
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_29 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_29_we),
    .wd     (gpio_en_gpio_en_29_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[29].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_29_qs)
  );


  // F[gpio_en_30]: 30:30
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_30 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_30_we),
    .wd     (gpio_en_gpio_en_30_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[30].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_30_qs)
  );


  // F[gpio_en_31]: 31:31
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_en_gpio_en_31 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_en_gpio_en_31_we),
    .wd     (gpio_en_gpio_en_31_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_en[31].q ),

    // to register interface (read)
    .qs     (gpio_en_gpio_en_31_qs)
  );




  // Subregister 0 of Multireg gpio_in
  // R[gpio_in]: V(True)

  // F[gpio_in_0]: 0:0
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_0 (
    .re     (gpio_in_gpio_in_0_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[0].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_0_qs)
  );


  // F[gpio_in_1]: 1:1
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_1 (
    .re     (gpio_in_gpio_in_1_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[1].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_1_qs)
  );


  // F[gpio_in_2]: 2:2
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_2 (
    .re     (gpio_in_gpio_in_2_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[2].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_2_qs)
  );


  // F[gpio_in_3]: 3:3
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_3 (
    .re     (gpio_in_gpio_in_3_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[3].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_3_qs)
  );


  // F[gpio_in_4]: 4:4
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_4 (
    .re     (gpio_in_gpio_in_4_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[4].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_4_qs)
  );


  // F[gpio_in_5]: 5:5
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_5 (
    .re     (gpio_in_gpio_in_5_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[5].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_5_qs)
  );


  // F[gpio_in_6]: 6:6
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_6 (
    .re     (gpio_in_gpio_in_6_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[6].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_6_qs)
  );


  // F[gpio_in_7]: 7:7
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_7 (
    .re     (gpio_in_gpio_in_7_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[7].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_7_qs)
  );


  // F[gpio_in_8]: 8:8
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_8 (
    .re     (gpio_in_gpio_in_8_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[8].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_8_qs)
  );


  // F[gpio_in_9]: 9:9
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_9 (
    .re     (gpio_in_gpio_in_9_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[9].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_9_qs)
  );


  // F[gpio_in_10]: 10:10
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_10 (
    .re     (gpio_in_gpio_in_10_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[10].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_10_qs)
  );


  // F[gpio_in_11]: 11:11
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_11 (
    .re     (gpio_in_gpio_in_11_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[11].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_11_qs)
  );


  // F[gpio_in_12]: 12:12
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_12 (
    .re     (gpio_in_gpio_in_12_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[12].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_12_qs)
  );


  // F[gpio_in_13]: 13:13
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_13 (
    .re     (gpio_in_gpio_in_13_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[13].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_13_qs)
  );


  // F[gpio_in_14]: 14:14
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_14 (
    .re     (gpio_in_gpio_in_14_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[14].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_14_qs)
  );


  // F[gpio_in_15]: 15:15
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_15 (
    .re     (gpio_in_gpio_in_15_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[15].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_15_qs)
  );


  // F[gpio_in_16]: 16:16
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_16 (
    .re     (gpio_in_gpio_in_16_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[16].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_16_qs)
  );


  // F[gpio_in_17]: 17:17
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_17 (
    .re     (gpio_in_gpio_in_17_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[17].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_17_qs)
  );


  // F[gpio_in_18]: 18:18
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_18 (
    .re     (gpio_in_gpio_in_18_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[18].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_18_qs)
  );


  // F[gpio_in_19]: 19:19
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_19 (
    .re     (gpio_in_gpio_in_19_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[19].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_19_qs)
  );


  // F[gpio_in_20]: 20:20
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_20 (
    .re     (gpio_in_gpio_in_20_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[20].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_20_qs)
  );


  // F[gpio_in_21]: 21:21
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_21 (
    .re     (gpio_in_gpio_in_21_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[21].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_21_qs)
  );


  // F[gpio_in_22]: 22:22
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_22 (
    .re     (gpio_in_gpio_in_22_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[22].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_22_qs)
  );


  // F[gpio_in_23]: 23:23
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_23 (
    .re     (gpio_in_gpio_in_23_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[23].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_23_qs)
  );


  // F[gpio_in_24]: 24:24
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_24 (
    .re     (gpio_in_gpio_in_24_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[24].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_24_qs)
  );


  // F[gpio_in_25]: 25:25
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_25 (
    .re     (gpio_in_gpio_in_25_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[25].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_25_qs)
  );


  // F[gpio_in_26]: 26:26
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_26 (
    .re     (gpio_in_gpio_in_26_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[26].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_26_qs)
  );


  // F[gpio_in_27]: 27:27
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_27 (
    .re     (gpio_in_gpio_in_27_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[27].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_27_qs)
  );


  // F[gpio_in_28]: 28:28
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_28 (
    .re     (gpio_in_gpio_in_28_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[28].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_28_qs)
  );


  // F[gpio_in_29]: 29:29
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_29 (
    .re     (gpio_in_gpio_in_29_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[29].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_29_qs)
  );


  // F[gpio_in_30]: 30:30
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_30 (
    .re     (gpio_in_gpio_in_30_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[30].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_30_qs)
  );


  // F[gpio_in_31]: 31:31
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_in_gpio_in_31 (
    .re     (gpio_in_gpio_in_31_re),
    .we     (1'b0),
    .wd     ('0),
    .d      (hw2reg.gpio_in[31].d),
    .qre    (),
    .qe     (),
    .q      (),
    .qs     (gpio_in_gpio_in_31_qs)
  );




  // Subregister 0 of Multireg gpio_out
  // R[gpio_out]: V(False)

  // F[gpio_out_0]: 0:0
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_0 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_0_we),
    .wd     (gpio_out_gpio_out_0_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[0].de),
    .d      (hw2reg.gpio_out[0].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[0].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_0_qs)
  );


  // F[gpio_out_1]: 1:1
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_1 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_1_we),
    .wd     (gpio_out_gpio_out_1_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[1].de),
    .d      (hw2reg.gpio_out[1].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[1].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_1_qs)
  );


  // F[gpio_out_2]: 2:2
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_2 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_2_we),
    .wd     (gpio_out_gpio_out_2_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[2].de),
    .d      (hw2reg.gpio_out[2].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[2].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_2_qs)
  );


  // F[gpio_out_3]: 3:3
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_3 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_3_we),
    .wd     (gpio_out_gpio_out_3_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[3].de),
    .d      (hw2reg.gpio_out[3].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[3].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_3_qs)
  );


  // F[gpio_out_4]: 4:4
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_4 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_4_we),
    .wd     (gpio_out_gpio_out_4_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[4].de),
    .d      (hw2reg.gpio_out[4].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[4].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_4_qs)
  );


  // F[gpio_out_5]: 5:5
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_5 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_5_we),
    .wd     (gpio_out_gpio_out_5_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[5].de),
    .d      (hw2reg.gpio_out[5].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[5].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_5_qs)
  );


  // F[gpio_out_6]: 6:6
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_6 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_6_we),
    .wd     (gpio_out_gpio_out_6_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[6].de),
    .d      (hw2reg.gpio_out[6].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[6].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_6_qs)
  );


  // F[gpio_out_7]: 7:7
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_7 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_7_we),
    .wd     (gpio_out_gpio_out_7_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[7].de),
    .d      (hw2reg.gpio_out[7].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[7].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_7_qs)
  );


  // F[gpio_out_8]: 8:8
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_8 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_8_we),
    .wd     (gpio_out_gpio_out_8_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[8].de),
    .d      (hw2reg.gpio_out[8].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[8].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_8_qs)
  );


  // F[gpio_out_9]: 9:9
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_9 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_9_we),
    .wd     (gpio_out_gpio_out_9_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[9].de),
    .d      (hw2reg.gpio_out[9].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[9].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_9_qs)
  );


  // F[gpio_out_10]: 10:10
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_10 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_10_we),
    .wd     (gpio_out_gpio_out_10_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[10].de),
    .d      (hw2reg.gpio_out[10].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[10].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_10_qs)
  );


  // F[gpio_out_11]: 11:11
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_11 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_11_we),
    .wd     (gpio_out_gpio_out_11_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[11].de),
    .d      (hw2reg.gpio_out[11].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[11].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_11_qs)
  );


  // F[gpio_out_12]: 12:12
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_12 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_12_we),
    .wd     (gpio_out_gpio_out_12_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[12].de),
    .d      (hw2reg.gpio_out[12].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[12].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_12_qs)
  );


  // F[gpio_out_13]: 13:13
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_13 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_13_we),
    .wd     (gpio_out_gpio_out_13_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[13].de),
    .d      (hw2reg.gpio_out[13].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[13].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_13_qs)
  );


  // F[gpio_out_14]: 14:14
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_14 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_14_we),
    .wd     (gpio_out_gpio_out_14_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[14].de),
    .d      (hw2reg.gpio_out[14].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[14].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_14_qs)
  );


  // F[gpio_out_15]: 15:15
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_15 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_15_we),
    .wd     (gpio_out_gpio_out_15_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[15].de),
    .d      (hw2reg.gpio_out[15].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[15].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_15_qs)
  );


  // F[gpio_out_16]: 16:16
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_16 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_16_we),
    .wd     (gpio_out_gpio_out_16_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[16].de),
    .d      (hw2reg.gpio_out[16].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[16].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_16_qs)
  );


  // F[gpio_out_17]: 17:17
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_17 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_17_we),
    .wd     (gpio_out_gpio_out_17_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[17].de),
    .d      (hw2reg.gpio_out[17].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[17].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_17_qs)
  );


  // F[gpio_out_18]: 18:18
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_18 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_18_we),
    .wd     (gpio_out_gpio_out_18_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[18].de),
    .d      (hw2reg.gpio_out[18].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[18].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_18_qs)
  );


  // F[gpio_out_19]: 19:19
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_19 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_19_we),
    .wd     (gpio_out_gpio_out_19_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[19].de),
    .d      (hw2reg.gpio_out[19].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[19].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_19_qs)
  );


  // F[gpio_out_20]: 20:20
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_20 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_20_we),
    .wd     (gpio_out_gpio_out_20_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[20].de),
    .d      (hw2reg.gpio_out[20].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[20].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_20_qs)
  );


  // F[gpio_out_21]: 21:21
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_21 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_21_we),
    .wd     (gpio_out_gpio_out_21_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[21].de),
    .d      (hw2reg.gpio_out[21].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[21].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_21_qs)
  );


  // F[gpio_out_22]: 22:22
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_22 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_22_we),
    .wd     (gpio_out_gpio_out_22_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[22].de),
    .d      (hw2reg.gpio_out[22].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[22].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_22_qs)
  );


  // F[gpio_out_23]: 23:23
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_23 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_23_we),
    .wd     (gpio_out_gpio_out_23_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[23].de),
    .d      (hw2reg.gpio_out[23].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[23].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_23_qs)
  );


  // F[gpio_out_24]: 24:24
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_24 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_24_we),
    .wd     (gpio_out_gpio_out_24_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[24].de),
    .d      (hw2reg.gpio_out[24].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[24].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_24_qs)
  );


  // F[gpio_out_25]: 25:25
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_25 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_25_we),
    .wd     (gpio_out_gpio_out_25_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[25].de),
    .d      (hw2reg.gpio_out[25].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[25].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_25_qs)
  );


  // F[gpio_out_26]: 26:26
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_26 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_26_we),
    .wd     (gpio_out_gpio_out_26_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[26].de),
    .d      (hw2reg.gpio_out[26].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[26].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_26_qs)
  );


  // F[gpio_out_27]: 27:27
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_27 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_27_we),
    .wd     (gpio_out_gpio_out_27_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[27].de),
    .d      (hw2reg.gpio_out[27].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[27].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_27_qs)
  );


  // F[gpio_out_28]: 28:28
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_28 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_28_we),
    .wd     (gpio_out_gpio_out_28_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[28].de),
    .d      (hw2reg.gpio_out[28].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[28].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_28_qs)
  );


  // F[gpio_out_29]: 29:29
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_29 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_29_we),
    .wd     (gpio_out_gpio_out_29_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[29].de),
    .d      (hw2reg.gpio_out[29].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[29].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_29_qs)
  );


  // F[gpio_out_30]: 30:30
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_30 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_30_we),
    .wd     (gpio_out_gpio_out_30_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[30].de),
    .d      (hw2reg.gpio_out[30].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[30].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_30_qs)
  );


  // F[gpio_out_31]: 31:31
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_gpio_out_gpio_out_31 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (gpio_out_gpio_out_31_we),
    .wd     (gpio_out_gpio_out_31_wd),

    // from internal hardware
    .de     (hw2reg.gpio_out[31].de),
    .d      (hw2reg.gpio_out[31].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.gpio_out[31].q ),

    // to register interface (read)
    .qs     (gpio_out_gpio_out_31_qs)
  );




  // Subregister 0 of Multireg gpio_set
  // R[gpio_set]: V(True)

  // F[gpio_set_0]: 0:0
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_0 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_0_we),
    .wd     (gpio_set_gpio_set_0_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[0].qe),
    .q      (reg2hw.gpio_set[0].q ),
    .qs     ()
  );


  // F[gpio_set_1]: 1:1
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_1 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_1_we),
    .wd     (gpio_set_gpio_set_1_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[1].qe),
    .q      (reg2hw.gpio_set[1].q ),
    .qs     ()
  );


  // F[gpio_set_2]: 2:2
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_2 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_2_we),
    .wd     (gpio_set_gpio_set_2_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[2].qe),
    .q      (reg2hw.gpio_set[2].q ),
    .qs     ()
  );


  // F[gpio_set_3]: 3:3
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_3 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_3_we),
    .wd     (gpio_set_gpio_set_3_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[3].qe),
    .q      (reg2hw.gpio_set[3].q ),
    .qs     ()
  );


  // F[gpio_set_4]: 4:4
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_4 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_4_we),
    .wd     (gpio_set_gpio_set_4_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[4].qe),
    .q      (reg2hw.gpio_set[4].q ),
    .qs     ()
  );


  // F[gpio_set_5]: 5:5
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_5 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_5_we),
    .wd     (gpio_set_gpio_set_5_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[5].qe),
    .q      (reg2hw.gpio_set[5].q ),
    .qs     ()
  );


  // F[gpio_set_6]: 6:6
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_6 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_6_we),
    .wd     (gpio_set_gpio_set_6_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[6].qe),
    .q      (reg2hw.gpio_set[6].q ),
    .qs     ()
  );


  // F[gpio_set_7]: 7:7
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_7 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_7_we),
    .wd     (gpio_set_gpio_set_7_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[7].qe),
    .q      (reg2hw.gpio_set[7].q ),
    .qs     ()
  );


  // F[gpio_set_8]: 8:8
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_8 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_8_we),
    .wd     (gpio_set_gpio_set_8_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[8].qe),
    .q      (reg2hw.gpio_set[8].q ),
    .qs     ()
  );


  // F[gpio_set_9]: 9:9
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_9 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_9_we),
    .wd     (gpio_set_gpio_set_9_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[9].qe),
    .q      (reg2hw.gpio_set[9].q ),
    .qs     ()
  );


  // F[gpio_set_10]: 10:10
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_10 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_10_we),
    .wd     (gpio_set_gpio_set_10_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[10].qe),
    .q      (reg2hw.gpio_set[10].q ),
    .qs     ()
  );


  // F[gpio_set_11]: 11:11
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_11 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_11_we),
    .wd     (gpio_set_gpio_set_11_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[11].qe),
    .q      (reg2hw.gpio_set[11].q ),
    .qs     ()
  );


  // F[gpio_set_12]: 12:12
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_12 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_12_we),
    .wd     (gpio_set_gpio_set_12_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[12].qe),
    .q      (reg2hw.gpio_set[12].q ),
    .qs     ()
  );


  // F[gpio_set_13]: 13:13
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_13 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_13_we),
    .wd     (gpio_set_gpio_set_13_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[13].qe),
    .q      (reg2hw.gpio_set[13].q ),
    .qs     ()
  );


  // F[gpio_set_14]: 14:14
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_14 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_14_we),
    .wd     (gpio_set_gpio_set_14_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[14].qe),
    .q      (reg2hw.gpio_set[14].q ),
    .qs     ()
  );


  // F[gpio_set_15]: 15:15
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_15 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_15_we),
    .wd     (gpio_set_gpio_set_15_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[15].qe),
    .q      (reg2hw.gpio_set[15].q ),
    .qs     ()
  );


  // F[gpio_set_16]: 16:16
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_16 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_16_we),
    .wd     (gpio_set_gpio_set_16_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[16].qe),
    .q      (reg2hw.gpio_set[16].q ),
    .qs     ()
  );


  // F[gpio_set_17]: 17:17
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_17 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_17_we),
    .wd     (gpio_set_gpio_set_17_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[17].qe),
    .q      (reg2hw.gpio_set[17].q ),
    .qs     ()
  );


  // F[gpio_set_18]: 18:18
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_18 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_18_we),
    .wd     (gpio_set_gpio_set_18_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[18].qe),
    .q      (reg2hw.gpio_set[18].q ),
    .qs     ()
  );


  // F[gpio_set_19]: 19:19
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_19 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_19_we),
    .wd     (gpio_set_gpio_set_19_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[19].qe),
    .q      (reg2hw.gpio_set[19].q ),
    .qs     ()
  );


  // F[gpio_set_20]: 20:20
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_20 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_20_we),
    .wd     (gpio_set_gpio_set_20_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[20].qe),
    .q      (reg2hw.gpio_set[20].q ),
    .qs     ()
  );


  // F[gpio_set_21]: 21:21
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_21 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_21_we),
    .wd     (gpio_set_gpio_set_21_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[21].qe),
    .q      (reg2hw.gpio_set[21].q ),
    .qs     ()
  );


  // F[gpio_set_22]: 22:22
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_22 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_22_we),
    .wd     (gpio_set_gpio_set_22_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[22].qe),
    .q      (reg2hw.gpio_set[22].q ),
    .qs     ()
  );


  // F[gpio_set_23]: 23:23
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_23 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_23_we),
    .wd     (gpio_set_gpio_set_23_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[23].qe),
    .q      (reg2hw.gpio_set[23].q ),
    .qs     ()
  );


  // F[gpio_set_24]: 24:24
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_24 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_24_we),
    .wd     (gpio_set_gpio_set_24_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[24].qe),
    .q      (reg2hw.gpio_set[24].q ),
    .qs     ()
  );


  // F[gpio_set_25]: 25:25
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_25 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_25_we),
    .wd     (gpio_set_gpio_set_25_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[25].qe),
    .q      (reg2hw.gpio_set[25].q ),
    .qs     ()
  );


  // F[gpio_set_26]: 26:26
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_26 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_26_we),
    .wd     (gpio_set_gpio_set_26_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[26].qe),
    .q      (reg2hw.gpio_set[26].q ),
    .qs     ()
  );


  // F[gpio_set_27]: 27:27
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_27 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_27_we),
    .wd     (gpio_set_gpio_set_27_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[27].qe),
    .q      (reg2hw.gpio_set[27].q ),
    .qs     ()
  );


  // F[gpio_set_28]: 28:28
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_28 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_28_we),
    .wd     (gpio_set_gpio_set_28_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[28].qe),
    .q      (reg2hw.gpio_set[28].q ),
    .qs     ()
  );


  // F[gpio_set_29]: 29:29
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_29 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_29_we),
    .wd     (gpio_set_gpio_set_29_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[29].qe),
    .q      (reg2hw.gpio_set[29].q ),
    .qs     ()
  );


  // F[gpio_set_30]: 30:30
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_30 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_30_we),
    .wd     (gpio_set_gpio_set_30_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[30].qe),
    .q      (reg2hw.gpio_set[30].q ),
    .qs     ()
  );


  // F[gpio_set_31]: 31:31
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_set_gpio_set_31 (
    .re     (1'b0),
    .we     (gpio_set_gpio_set_31_we),
    .wd     (gpio_set_gpio_set_31_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_set[31].qe),
    .q      (reg2hw.gpio_set[31].q ),
    .qs     ()
  );




  // Subregister 0 of Multireg gpio_clear
  // R[gpio_clear]: V(True)

  // F[gpio_clear_0]: 0:0
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_0 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_0_we),
    .wd     (gpio_clear_gpio_clear_0_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[0].qe),
    .q      (reg2hw.gpio_clear[0].q ),
    .qs     ()
  );


  // F[gpio_clear_1]: 1:1
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_1 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_1_we),
    .wd     (gpio_clear_gpio_clear_1_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[1].qe),
    .q      (reg2hw.gpio_clear[1].q ),
    .qs     ()
  );


  // F[gpio_clear_2]: 2:2
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_2 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_2_we),
    .wd     (gpio_clear_gpio_clear_2_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[2].qe),
    .q      (reg2hw.gpio_clear[2].q ),
    .qs     ()
  );


  // F[gpio_clear_3]: 3:3
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_3 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_3_we),
    .wd     (gpio_clear_gpio_clear_3_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[3].qe),
    .q      (reg2hw.gpio_clear[3].q ),
    .qs     ()
  );


  // F[gpio_clear_4]: 4:4
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_4 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_4_we),
    .wd     (gpio_clear_gpio_clear_4_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[4].qe),
    .q      (reg2hw.gpio_clear[4].q ),
    .qs     ()
  );


  // F[gpio_clear_5]: 5:5
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_5 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_5_we),
    .wd     (gpio_clear_gpio_clear_5_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[5].qe),
    .q      (reg2hw.gpio_clear[5].q ),
    .qs     ()
  );


  // F[gpio_clear_6]: 6:6
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_6 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_6_we),
    .wd     (gpio_clear_gpio_clear_6_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[6].qe),
    .q      (reg2hw.gpio_clear[6].q ),
    .qs     ()
  );


  // F[gpio_clear_7]: 7:7
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_7 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_7_we),
    .wd     (gpio_clear_gpio_clear_7_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[7].qe),
    .q      (reg2hw.gpio_clear[7].q ),
    .qs     ()
  );


  // F[gpio_clear_8]: 8:8
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_8 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_8_we),
    .wd     (gpio_clear_gpio_clear_8_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[8].qe),
    .q      (reg2hw.gpio_clear[8].q ),
    .qs     ()
  );


  // F[gpio_clear_9]: 9:9
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_9 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_9_we),
    .wd     (gpio_clear_gpio_clear_9_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[9].qe),
    .q      (reg2hw.gpio_clear[9].q ),
    .qs     ()
  );


  // F[gpio_clear_10]: 10:10
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_10 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_10_we),
    .wd     (gpio_clear_gpio_clear_10_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[10].qe),
    .q      (reg2hw.gpio_clear[10].q ),
    .qs     ()
  );


  // F[gpio_clear_11]: 11:11
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_11 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_11_we),
    .wd     (gpio_clear_gpio_clear_11_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[11].qe),
    .q      (reg2hw.gpio_clear[11].q ),
    .qs     ()
  );


  // F[gpio_clear_12]: 12:12
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_12 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_12_we),
    .wd     (gpio_clear_gpio_clear_12_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[12].qe),
    .q      (reg2hw.gpio_clear[12].q ),
    .qs     ()
  );


  // F[gpio_clear_13]: 13:13
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_13 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_13_we),
    .wd     (gpio_clear_gpio_clear_13_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[13].qe),
    .q      (reg2hw.gpio_clear[13].q ),
    .qs     ()
  );


  // F[gpio_clear_14]: 14:14
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_14 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_14_we),
    .wd     (gpio_clear_gpio_clear_14_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[14].qe),
    .q      (reg2hw.gpio_clear[14].q ),
    .qs     ()
  );


  // F[gpio_clear_15]: 15:15
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_15 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_15_we),
    .wd     (gpio_clear_gpio_clear_15_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[15].qe),
    .q      (reg2hw.gpio_clear[15].q ),
    .qs     ()
  );


  // F[gpio_clear_16]: 16:16
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_16 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_16_we),
    .wd     (gpio_clear_gpio_clear_16_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[16].qe),
    .q      (reg2hw.gpio_clear[16].q ),
    .qs     ()
  );


  // F[gpio_clear_17]: 17:17
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_17 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_17_we),
    .wd     (gpio_clear_gpio_clear_17_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[17].qe),
    .q      (reg2hw.gpio_clear[17].q ),
    .qs     ()
  );


  // F[gpio_clear_18]: 18:18
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_18 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_18_we),
    .wd     (gpio_clear_gpio_clear_18_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[18].qe),
    .q      (reg2hw.gpio_clear[18].q ),
    .qs     ()
  );


  // F[gpio_clear_19]: 19:19
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_19 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_19_we),
    .wd     (gpio_clear_gpio_clear_19_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[19].qe),
    .q      (reg2hw.gpio_clear[19].q ),
    .qs     ()
  );


  // F[gpio_clear_20]: 20:20
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_20 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_20_we),
    .wd     (gpio_clear_gpio_clear_20_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[20].qe),
    .q      (reg2hw.gpio_clear[20].q ),
    .qs     ()
  );


  // F[gpio_clear_21]: 21:21
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_21 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_21_we),
    .wd     (gpio_clear_gpio_clear_21_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[21].qe),
    .q      (reg2hw.gpio_clear[21].q ),
    .qs     ()
  );


  // F[gpio_clear_22]: 22:22
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_22 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_22_we),
    .wd     (gpio_clear_gpio_clear_22_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[22].qe),
    .q      (reg2hw.gpio_clear[22].q ),
    .qs     ()
  );


  // F[gpio_clear_23]: 23:23
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_23 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_23_we),
    .wd     (gpio_clear_gpio_clear_23_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[23].qe),
    .q      (reg2hw.gpio_clear[23].q ),
    .qs     ()
  );


  // F[gpio_clear_24]: 24:24
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_24 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_24_we),
    .wd     (gpio_clear_gpio_clear_24_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[24].qe),
    .q      (reg2hw.gpio_clear[24].q ),
    .qs     ()
  );


  // F[gpio_clear_25]: 25:25
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_25 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_25_we),
    .wd     (gpio_clear_gpio_clear_25_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[25].qe),
    .q      (reg2hw.gpio_clear[25].q ),
    .qs     ()
  );


  // F[gpio_clear_26]: 26:26
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_26 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_26_we),
    .wd     (gpio_clear_gpio_clear_26_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[26].qe),
    .q      (reg2hw.gpio_clear[26].q ),
    .qs     ()
  );


  // F[gpio_clear_27]: 27:27
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_27 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_27_we),
    .wd     (gpio_clear_gpio_clear_27_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[27].qe),
    .q      (reg2hw.gpio_clear[27].q ),
    .qs     ()
  );


  // F[gpio_clear_28]: 28:28
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_28 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_28_we),
    .wd     (gpio_clear_gpio_clear_28_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[28].qe),
    .q      (reg2hw.gpio_clear[28].q ),
    .qs     ()
  );


  // F[gpio_clear_29]: 29:29
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_29 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_29_we),
    .wd     (gpio_clear_gpio_clear_29_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[29].qe),
    .q      (reg2hw.gpio_clear[29].q ),
    .qs     ()
  );


  // F[gpio_clear_30]: 30:30
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_30 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_30_we),
    .wd     (gpio_clear_gpio_clear_30_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[30].qe),
    .q      (reg2hw.gpio_clear[30].q ),
    .qs     ()
  );


  // F[gpio_clear_31]: 31:31
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_clear_gpio_clear_31 (
    .re     (1'b0),
    .we     (gpio_clear_gpio_clear_31_we),
    .wd     (gpio_clear_gpio_clear_31_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_clear[31].qe),
    .q      (reg2hw.gpio_clear[31].q ),
    .qs     ()
  );




  // Subregister 0 of Multireg gpio_toggle
  // R[gpio_toggle]: V(True)

  // F[gpio_toggle_0]: 0:0
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_0 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_0_we),
    .wd     (gpio_toggle_gpio_toggle_0_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[0].qe),
    .q      (reg2hw.gpio_toggle[0].q ),
    .qs     ()
  );


  // F[gpio_toggle_1]: 1:1
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_1 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_1_we),
    .wd     (gpio_toggle_gpio_toggle_1_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[1].qe),
    .q      (reg2hw.gpio_toggle[1].q ),
    .qs     ()
  );


  // F[gpio_toggle_2]: 2:2
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_2 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_2_we),
    .wd     (gpio_toggle_gpio_toggle_2_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[2].qe),
    .q      (reg2hw.gpio_toggle[2].q ),
    .qs     ()
  );


  // F[gpio_toggle_3]: 3:3
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_3 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_3_we),
    .wd     (gpio_toggle_gpio_toggle_3_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[3].qe),
    .q      (reg2hw.gpio_toggle[3].q ),
    .qs     ()
  );


  // F[gpio_toggle_4]: 4:4
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_4 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_4_we),
    .wd     (gpio_toggle_gpio_toggle_4_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[4].qe),
    .q      (reg2hw.gpio_toggle[4].q ),
    .qs     ()
  );


  // F[gpio_toggle_5]: 5:5
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_5 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_5_we),
    .wd     (gpio_toggle_gpio_toggle_5_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[5].qe),
    .q      (reg2hw.gpio_toggle[5].q ),
    .qs     ()
  );


  // F[gpio_toggle_6]: 6:6
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_6 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_6_we),
    .wd     (gpio_toggle_gpio_toggle_6_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[6].qe),
    .q      (reg2hw.gpio_toggle[6].q ),
    .qs     ()
  );


  // F[gpio_toggle_7]: 7:7
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_7 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_7_we),
    .wd     (gpio_toggle_gpio_toggle_7_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[7].qe),
    .q      (reg2hw.gpio_toggle[7].q ),
    .qs     ()
  );


  // F[gpio_toggle_8]: 8:8
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_8 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_8_we),
    .wd     (gpio_toggle_gpio_toggle_8_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[8].qe),
    .q      (reg2hw.gpio_toggle[8].q ),
    .qs     ()
  );


  // F[gpio_toggle_9]: 9:9
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_9 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_9_we),
    .wd     (gpio_toggle_gpio_toggle_9_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[9].qe),
    .q      (reg2hw.gpio_toggle[9].q ),
    .qs     ()
  );


  // F[gpio_toggle_10]: 10:10
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_10 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_10_we),
    .wd     (gpio_toggle_gpio_toggle_10_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[10].qe),
    .q      (reg2hw.gpio_toggle[10].q ),
    .qs     ()
  );


  // F[gpio_toggle_11]: 11:11
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_11 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_11_we),
    .wd     (gpio_toggle_gpio_toggle_11_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[11].qe),
    .q      (reg2hw.gpio_toggle[11].q ),
    .qs     ()
  );


  // F[gpio_toggle_12]: 12:12
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_12 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_12_we),
    .wd     (gpio_toggle_gpio_toggle_12_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[12].qe),
    .q      (reg2hw.gpio_toggle[12].q ),
    .qs     ()
  );


  // F[gpio_toggle_13]: 13:13
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_13 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_13_we),
    .wd     (gpio_toggle_gpio_toggle_13_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[13].qe),
    .q      (reg2hw.gpio_toggle[13].q ),
    .qs     ()
  );


  // F[gpio_toggle_14]: 14:14
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_14 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_14_we),
    .wd     (gpio_toggle_gpio_toggle_14_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[14].qe),
    .q      (reg2hw.gpio_toggle[14].q ),
    .qs     ()
  );


  // F[gpio_toggle_15]: 15:15
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_15 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_15_we),
    .wd     (gpio_toggle_gpio_toggle_15_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[15].qe),
    .q      (reg2hw.gpio_toggle[15].q ),
    .qs     ()
  );


  // F[gpio_toggle_16]: 16:16
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_16 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_16_we),
    .wd     (gpio_toggle_gpio_toggle_16_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[16].qe),
    .q      (reg2hw.gpio_toggle[16].q ),
    .qs     ()
  );


  // F[gpio_toggle_17]: 17:17
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_17 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_17_we),
    .wd     (gpio_toggle_gpio_toggle_17_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[17].qe),
    .q      (reg2hw.gpio_toggle[17].q ),
    .qs     ()
  );


  // F[gpio_toggle_18]: 18:18
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_18 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_18_we),
    .wd     (gpio_toggle_gpio_toggle_18_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[18].qe),
    .q      (reg2hw.gpio_toggle[18].q ),
    .qs     ()
  );


  // F[gpio_toggle_19]: 19:19
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_19 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_19_we),
    .wd     (gpio_toggle_gpio_toggle_19_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[19].qe),
    .q      (reg2hw.gpio_toggle[19].q ),
    .qs     ()
  );


  // F[gpio_toggle_20]: 20:20
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_20 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_20_we),
    .wd     (gpio_toggle_gpio_toggle_20_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[20].qe),
    .q      (reg2hw.gpio_toggle[20].q ),
    .qs     ()
  );


  // F[gpio_toggle_21]: 21:21
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_21 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_21_we),
    .wd     (gpio_toggle_gpio_toggle_21_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[21].qe),
    .q      (reg2hw.gpio_toggle[21].q ),
    .qs     ()
  );


  // F[gpio_toggle_22]: 22:22
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_22 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_22_we),
    .wd     (gpio_toggle_gpio_toggle_22_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[22].qe),
    .q      (reg2hw.gpio_toggle[22].q ),
    .qs     ()
  );


  // F[gpio_toggle_23]: 23:23
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_23 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_23_we),
    .wd     (gpio_toggle_gpio_toggle_23_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[23].qe),
    .q      (reg2hw.gpio_toggle[23].q ),
    .qs     ()
  );


  // F[gpio_toggle_24]: 24:24
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_24 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_24_we),
    .wd     (gpio_toggle_gpio_toggle_24_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[24].qe),
    .q      (reg2hw.gpio_toggle[24].q ),
    .qs     ()
  );


  // F[gpio_toggle_25]: 25:25
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_25 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_25_we),
    .wd     (gpio_toggle_gpio_toggle_25_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[25].qe),
    .q      (reg2hw.gpio_toggle[25].q ),
    .qs     ()
  );


  // F[gpio_toggle_26]: 26:26
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_26 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_26_we),
    .wd     (gpio_toggle_gpio_toggle_26_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[26].qe),
    .q      (reg2hw.gpio_toggle[26].q ),
    .qs     ()
  );


  // F[gpio_toggle_27]: 27:27
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_27 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_27_we),
    .wd     (gpio_toggle_gpio_toggle_27_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[27].qe),
    .q      (reg2hw.gpio_toggle[27].q ),
    .qs     ()
  );


  // F[gpio_toggle_28]: 28:28
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_28 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_28_we),
    .wd     (gpio_toggle_gpio_toggle_28_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[28].qe),
    .q      (reg2hw.gpio_toggle[28].q ),
    .qs     ()
  );


  // F[gpio_toggle_29]: 29:29
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_29 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_29_we),
    .wd     (gpio_toggle_gpio_toggle_29_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[29].qe),
    .q      (reg2hw.gpio_toggle[29].q ),
    .qs     ()
  );


  // F[gpio_toggle_30]: 30:30
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_30 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_30_we),
    .wd     (gpio_toggle_gpio_toggle_30_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[30].qe),
    .q      (reg2hw.gpio_toggle[30].q ),
    .qs     ()
  );


  // F[gpio_toggle_31]: 31:31
  prim_subreg_ext #(
    .DW    (1)
  ) u_gpio_toggle_gpio_toggle_31 (
    .re     (1'b0),
    .we     (gpio_toggle_gpio_toggle_31_we),
    .wd     (gpio_toggle_gpio_toggle_31_wd),
    .d      ('0),
    .qre    (),
    .qe     (reg2hw.gpio_toggle[31].qe),
    .q      (reg2hw.gpio_toggle[31].q ),
    .qs     ()
  );




  // Subregister 0 of Multireg intrpt_rise_en
  // R[intrpt_rise_en]: V(False)

  // F[intrpt_rise_en_0]: 0:0
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_0 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_0_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[0].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_0_qs)
  );


  // F[intrpt_rise_en_1]: 1:1
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_1 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_1_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[1].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_1_qs)
  );


  // F[intrpt_rise_en_2]: 2:2
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_2 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_2_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[2].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_2_qs)
  );


  // F[intrpt_rise_en_3]: 3:3
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_3 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_3_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[3].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_3_qs)
  );


  // F[intrpt_rise_en_4]: 4:4
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_4 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_4_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[4].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_4_qs)
  );


  // F[intrpt_rise_en_5]: 5:5
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_5 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_5_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[5].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_5_qs)
  );


  // F[intrpt_rise_en_6]: 6:6
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_6 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_6_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[6].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_6_qs)
  );


  // F[intrpt_rise_en_7]: 7:7
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_7 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_7_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[7].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_7_qs)
  );


  // F[intrpt_rise_en_8]: 8:8
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_8 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_8_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[8].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_8_qs)
  );


  // F[intrpt_rise_en_9]: 9:9
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_9 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_9_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[9].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_9_qs)
  );


  // F[intrpt_rise_en_10]: 10:10
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_10 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_10_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[10].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_10_qs)
  );


  // F[intrpt_rise_en_11]: 11:11
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_11 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_11_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[11].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_11_qs)
  );


  // F[intrpt_rise_en_12]: 12:12
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_12 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_12_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_12_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[12].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_12_qs)
  );


  // F[intrpt_rise_en_13]: 13:13
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_13 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_13_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_13_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[13].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_13_qs)
  );


  // F[intrpt_rise_en_14]: 14:14
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_14 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_14_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_14_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[14].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_14_qs)
  );


  // F[intrpt_rise_en_15]: 15:15
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_15 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_15_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_15_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[15].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_15_qs)
  );


  // F[intrpt_rise_en_16]: 16:16
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_16 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_16_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_16_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[16].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_16_qs)
  );


  // F[intrpt_rise_en_17]: 17:17
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_17 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_17_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_17_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[17].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_17_qs)
  );


  // F[intrpt_rise_en_18]: 18:18
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_18 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_18_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_18_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[18].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_18_qs)
  );


  // F[intrpt_rise_en_19]: 19:19
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_19 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_19_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_19_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[19].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_19_qs)
  );


  // F[intrpt_rise_en_20]: 20:20
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_20 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_20_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_20_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[20].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_20_qs)
  );


  // F[intrpt_rise_en_21]: 21:21
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_21 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_21_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_21_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[21].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_21_qs)
  );


  // F[intrpt_rise_en_22]: 22:22
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_22 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_22_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_22_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[22].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_22_qs)
  );


  // F[intrpt_rise_en_23]: 23:23
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_23 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_23_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_23_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[23].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_23_qs)
  );


  // F[intrpt_rise_en_24]: 24:24
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_24 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_24_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_24_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[24].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_24_qs)
  );


  // F[intrpt_rise_en_25]: 25:25
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_25 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_25_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_25_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[25].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_25_qs)
  );


  // F[intrpt_rise_en_26]: 26:26
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_26 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_26_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_26_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[26].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_26_qs)
  );


  // F[intrpt_rise_en_27]: 27:27
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_27 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_27_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_27_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[27].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_27_qs)
  );


  // F[intrpt_rise_en_28]: 28:28
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_28 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_28_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_28_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[28].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_28_qs)
  );


  // F[intrpt_rise_en_29]: 29:29
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_29 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_29_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_29_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[29].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_29_qs)
  );


  // F[intrpt_rise_en_30]: 30:30
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_30 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_30_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_30_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[30].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_30_qs)
  );


  // F[intrpt_rise_en_31]: 31:31
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_en_intrpt_rise_en_31 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_en_intrpt_rise_en_31_we),
    .wd     (intrpt_rise_en_intrpt_rise_en_31_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_en[31].q ),

    // to register interface (read)
    .qs     (intrpt_rise_en_intrpt_rise_en_31_qs)
  );




  // Subregister 0 of Multireg intrpt_fall_en
  // R[intrpt_fall_en]: V(False)

  // F[intrpt_fall_en_0]: 0:0
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_0 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_0_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[0].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_0_qs)
  );


  // F[intrpt_fall_en_1]: 1:1
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_1 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_1_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[1].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_1_qs)
  );


  // F[intrpt_fall_en_2]: 2:2
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_2 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_2_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[2].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_2_qs)
  );


  // F[intrpt_fall_en_3]: 3:3
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_3 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_3_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[3].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_3_qs)
  );


  // F[intrpt_fall_en_4]: 4:4
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_4 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_4_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[4].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_4_qs)
  );


  // F[intrpt_fall_en_5]: 5:5
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_5 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_5_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[5].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_5_qs)
  );


  // F[intrpt_fall_en_6]: 6:6
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_6 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_6_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[6].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_6_qs)
  );


  // F[intrpt_fall_en_7]: 7:7
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_7 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_7_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[7].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_7_qs)
  );


  // F[intrpt_fall_en_8]: 8:8
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_8 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_8_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[8].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_8_qs)
  );


  // F[intrpt_fall_en_9]: 9:9
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_9 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_9_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[9].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_9_qs)
  );


  // F[intrpt_fall_en_10]: 10:10
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_10 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_10_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[10].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_10_qs)
  );


  // F[intrpt_fall_en_11]: 11:11
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_11 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_11_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[11].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_11_qs)
  );


  // F[intrpt_fall_en_12]: 12:12
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_12 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_12_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_12_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[12].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_12_qs)
  );


  // F[intrpt_fall_en_13]: 13:13
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_13 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_13_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_13_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[13].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_13_qs)
  );


  // F[intrpt_fall_en_14]: 14:14
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_14 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_14_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_14_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[14].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_14_qs)
  );


  // F[intrpt_fall_en_15]: 15:15
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_15 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_15_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_15_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[15].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_15_qs)
  );


  // F[intrpt_fall_en_16]: 16:16
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_16 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_16_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_16_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[16].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_16_qs)
  );


  // F[intrpt_fall_en_17]: 17:17
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_17 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_17_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_17_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[17].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_17_qs)
  );


  // F[intrpt_fall_en_18]: 18:18
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_18 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_18_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_18_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[18].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_18_qs)
  );


  // F[intrpt_fall_en_19]: 19:19
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_19 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_19_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_19_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[19].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_19_qs)
  );


  // F[intrpt_fall_en_20]: 20:20
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_20 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_20_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_20_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[20].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_20_qs)
  );


  // F[intrpt_fall_en_21]: 21:21
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_21 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_21_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_21_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[21].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_21_qs)
  );


  // F[intrpt_fall_en_22]: 22:22
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_22 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_22_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_22_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[22].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_22_qs)
  );


  // F[intrpt_fall_en_23]: 23:23
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_23 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_23_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_23_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[23].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_23_qs)
  );


  // F[intrpt_fall_en_24]: 24:24
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_24 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_24_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_24_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[24].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_24_qs)
  );


  // F[intrpt_fall_en_25]: 25:25
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_25 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_25_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_25_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[25].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_25_qs)
  );


  // F[intrpt_fall_en_26]: 26:26
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_26 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_26_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_26_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[26].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_26_qs)
  );


  // F[intrpt_fall_en_27]: 27:27
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_27 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_27_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_27_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[27].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_27_qs)
  );


  // F[intrpt_fall_en_28]: 28:28
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_28 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_28_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_28_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[28].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_28_qs)
  );


  // F[intrpt_fall_en_29]: 29:29
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_29 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_29_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_29_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[29].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_29_qs)
  );


  // F[intrpt_fall_en_30]: 30:30
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_30 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_30_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_30_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[30].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_30_qs)
  );


  // F[intrpt_fall_en_31]: 31:31
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_en_intrpt_fall_en_31 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_en_intrpt_fall_en_31_we),
    .wd     (intrpt_fall_en_intrpt_fall_en_31_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_en[31].q ),

    // to register interface (read)
    .qs     (intrpt_fall_en_intrpt_fall_en_31_qs)
  );




  // Subregister 0 of Multireg intrpt_lvl_high_en
  // R[intrpt_lvl_high_en]: V(False)

  // F[intrpt_lvl_high_en_0]: 0:0
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_0 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_0_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[0].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_0_qs)
  );


  // F[intrpt_lvl_high_en_1]: 1:1
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_1 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_1_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[1].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_1_qs)
  );


  // F[intrpt_lvl_high_en_2]: 2:2
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_2 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_2_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[2].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_2_qs)
  );


  // F[intrpt_lvl_high_en_3]: 3:3
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_3 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_3_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[3].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_3_qs)
  );


  // F[intrpt_lvl_high_en_4]: 4:4
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_4 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_4_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[4].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_4_qs)
  );


  // F[intrpt_lvl_high_en_5]: 5:5
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_5 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_5_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[5].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_5_qs)
  );


  // F[intrpt_lvl_high_en_6]: 6:6
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_6 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_6_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[6].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_6_qs)
  );


  // F[intrpt_lvl_high_en_7]: 7:7
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_7 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_7_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[7].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_7_qs)
  );


  // F[intrpt_lvl_high_en_8]: 8:8
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_8 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_8_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[8].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_8_qs)
  );


  // F[intrpt_lvl_high_en_9]: 9:9
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_9 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_9_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[9].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_9_qs)
  );


  // F[intrpt_lvl_high_en_10]: 10:10
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_10 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_10_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[10].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_10_qs)
  );


  // F[intrpt_lvl_high_en_11]: 11:11
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_11 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_11_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[11].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_11_qs)
  );


  // F[intrpt_lvl_high_en_12]: 12:12
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_12 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_12_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_12_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[12].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_12_qs)
  );


  // F[intrpt_lvl_high_en_13]: 13:13
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_13 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_13_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_13_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[13].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_13_qs)
  );


  // F[intrpt_lvl_high_en_14]: 14:14
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_14 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_14_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_14_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[14].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_14_qs)
  );


  // F[intrpt_lvl_high_en_15]: 15:15
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_15 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_15_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_15_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[15].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_15_qs)
  );


  // F[intrpt_lvl_high_en_16]: 16:16
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_16 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_16_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_16_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[16].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_16_qs)
  );


  // F[intrpt_lvl_high_en_17]: 17:17
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_17 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_17_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_17_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[17].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_17_qs)
  );


  // F[intrpt_lvl_high_en_18]: 18:18
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_18 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_18_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_18_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[18].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_18_qs)
  );


  // F[intrpt_lvl_high_en_19]: 19:19
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_19 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_19_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_19_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[19].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_19_qs)
  );


  // F[intrpt_lvl_high_en_20]: 20:20
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_20 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_20_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_20_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[20].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_20_qs)
  );


  // F[intrpt_lvl_high_en_21]: 21:21
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_21 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_21_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_21_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[21].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_21_qs)
  );


  // F[intrpt_lvl_high_en_22]: 22:22
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_22 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_22_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_22_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[22].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_22_qs)
  );


  // F[intrpt_lvl_high_en_23]: 23:23
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_23 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_23_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_23_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[23].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_23_qs)
  );


  // F[intrpt_lvl_high_en_24]: 24:24
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_24 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_24_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_24_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[24].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_24_qs)
  );


  // F[intrpt_lvl_high_en_25]: 25:25
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_25 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_25_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_25_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[25].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_25_qs)
  );


  // F[intrpt_lvl_high_en_26]: 26:26
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_26 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_26_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_26_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[26].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_26_qs)
  );


  // F[intrpt_lvl_high_en_27]: 27:27
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_27 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_27_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_27_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[27].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_27_qs)
  );


  // F[intrpt_lvl_high_en_28]: 28:28
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_28 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_28_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_28_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[28].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_28_qs)
  );


  // F[intrpt_lvl_high_en_29]: 29:29
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_29 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_29_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_29_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[29].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_29_qs)
  );


  // F[intrpt_lvl_high_en_30]: 30:30
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_30 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_30_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_30_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[30].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_30_qs)
  );


  // F[intrpt_lvl_high_en_31]: 31:31
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_31 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_en_intrpt_lvl_high_en_31_we),
    .wd     (intrpt_lvl_high_en_intrpt_lvl_high_en_31_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_en[31].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_en_intrpt_lvl_high_en_31_qs)
  );




  // Subregister 0 of Multireg intrpt_lvl_low_en
  // R[intrpt_lvl_low_en]: V(False)

  // F[intrpt_lvl_low_en_0]: 0:0
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_0 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_0_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_0_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[0].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_0_qs)
  );


  // F[intrpt_lvl_low_en_1]: 1:1
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_1 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_1_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_1_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[1].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_1_qs)
  );


  // F[intrpt_lvl_low_en_2]: 2:2
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_2 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_2_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_2_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[2].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_2_qs)
  );


  // F[intrpt_lvl_low_en_3]: 3:3
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_3 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_3_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_3_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[3].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_3_qs)
  );


  // F[intrpt_lvl_low_en_4]: 4:4
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_4 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_4_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_4_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[4].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_4_qs)
  );


  // F[intrpt_lvl_low_en_5]: 5:5
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_5 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_5_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_5_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[5].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_5_qs)
  );


  // F[intrpt_lvl_low_en_6]: 6:6
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_6 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_6_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_6_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[6].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_6_qs)
  );


  // F[intrpt_lvl_low_en_7]: 7:7
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_7 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_7_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_7_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[7].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_7_qs)
  );


  // F[intrpt_lvl_low_en_8]: 8:8
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_8 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_8_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_8_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[8].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_8_qs)
  );


  // F[intrpt_lvl_low_en_9]: 9:9
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_9 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_9_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_9_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[9].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_9_qs)
  );


  // F[intrpt_lvl_low_en_10]: 10:10
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_10 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_10_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_10_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[10].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_10_qs)
  );


  // F[intrpt_lvl_low_en_11]: 11:11
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_11 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_11_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_11_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[11].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_11_qs)
  );


  // F[intrpt_lvl_low_en_12]: 12:12
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_12 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_12_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_12_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[12].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_12_qs)
  );


  // F[intrpt_lvl_low_en_13]: 13:13
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_13 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_13_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_13_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[13].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_13_qs)
  );


  // F[intrpt_lvl_low_en_14]: 14:14
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_14 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_14_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_14_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[14].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_14_qs)
  );


  // F[intrpt_lvl_low_en_15]: 15:15
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_15 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_15_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_15_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[15].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_15_qs)
  );


  // F[intrpt_lvl_low_en_16]: 16:16
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_16 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_16_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_16_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[16].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_16_qs)
  );


  // F[intrpt_lvl_low_en_17]: 17:17
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_17 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_17_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_17_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[17].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_17_qs)
  );


  // F[intrpt_lvl_low_en_18]: 18:18
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_18 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_18_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_18_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[18].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_18_qs)
  );


  // F[intrpt_lvl_low_en_19]: 19:19
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_19 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_19_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_19_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[19].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_19_qs)
  );


  // F[intrpt_lvl_low_en_20]: 20:20
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_20 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_20_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_20_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[20].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_20_qs)
  );


  // F[intrpt_lvl_low_en_21]: 21:21
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_21 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_21_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_21_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[21].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_21_qs)
  );


  // F[intrpt_lvl_low_en_22]: 22:22
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_22 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_22_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_22_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[22].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_22_qs)
  );


  // F[intrpt_lvl_low_en_23]: 23:23
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_23 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_23_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_23_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[23].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_23_qs)
  );


  // F[intrpt_lvl_low_en_24]: 24:24
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_24 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_24_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_24_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[24].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_24_qs)
  );


  // F[intrpt_lvl_low_en_25]: 25:25
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_25 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_25_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_25_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[25].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_25_qs)
  );


  // F[intrpt_lvl_low_en_26]: 26:26
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_26 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_26_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_26_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[26].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_26_qs)
  );


  // F[intrpt_lvl_low_en_27]: 27:27
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_27 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_27_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_27_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[27].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_27_qs)
  );


  // F[intrpt_lvl_low_en_28]: 28:28
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_28 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_28_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_28_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[28].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_28_qs)
  );


  // F[intrpt_lvl_low_en_29]: 29:29
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_29 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_29_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_29_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[29].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_29_qs)
  );


  // F[intrpt_lvl_low_en_30]: 30:30
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_30 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_30_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_30_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[30].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_30_qs)
  );


  // F[intrpt_lvl_low_en_31]: 31:31
  prim_subreg #(
    .DW      (1),
    .SWACCESS("RW"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_31 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_en_intrpt_lvl_low_en_31_we),
    .wd     (intrpt_lvl_low_en_intrpt_lvl_low_en_31_wd),

    // from internal hardware
    .de     (1'b0),
    .d      ('0  ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_en[31].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_en_intrpt_lvl_low_en_31_qs)
  );




  // Subregister 0 of Multireg intrpt_status
  // R[intrpt_status]: V(True)

  // F[intrpt_status_0]: 0:0
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_0 (
    .re     (intrpt_status_intrpt_status_0_re),
    .we     (intrpt_status_intrpt_status_0_we),
    .wd     (intrpt_status_intrpt_status_0_wd),
    .d      (hw2reg.intrpt_status[0].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[0].qe),
    .q      (reg2hw.intrpt_status[0].q ),
    .qs     (intrpt_status_intrpt_status_0_qs)
  );


  // F[intrpt_status_1]: 1:1
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_1 (
    .re     (intrpt_status_intrpt_status_1_re),
    .we     (intrpt_status_intrpt_status_1_we),
    .wd     (intrpt_status_intrpt_status_1_wd),
    .d      (hw2reg.intrpt_status[1].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[1].qe),
    .q      (reg2hw.intrpt_status[1].q ),
    .qs     (intrpt_status_intrpt_status_1_qs)
  );


  // F[intrpt_status_2]: 2:2
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_2 (
    .re     (intrpt_status_intrpt_status_2_re),
    .we     (intrpt_status_intrpt_status_2_we),
    .wd     (intrpt_status_intrpt_status_2_wd),
    .d      (hw2reg.intrpt_status[2].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[2].qe),
    .q      (reg2hw.intrpt_status[2].q ),
    .qs     (intrpt_status_intrpt_status_2_qs)
  );


  // F[intrpt_status_3]: 3:3
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_3 (
    .re     (intrpt_status_intrpt_status_3_re),
    .we     (intrpt_status_intrpt_status_3_we),
    .wd     (intrpt_status_intrpt_status_3_wd),
    .d      (hw2reg.intrpt_status[3].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[3].qe),
    .q      (reg2hw.intrpt_status[3].q ),
    .qs     (intrpt_status_intrpt_status_3_qs)
  );


  // F[intrpt_status_4]: 4:4
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_4 (
    .re     (intrpt_status_intrpt_status_4_re),
    .we     (intrpt_status_intrpt_status_4_we),
    .wd     (intrpt_status_intrpt_status_4_wd),
    .d      (hw2reg.intrpt_status[4].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[4].qe),
    .q      (reg2hw.intrpt_status[4].q ),
    .qs     (intrpt_status_intrpt_status_4_qs)
  );


  // F[intrpt_status_5]: 5:5
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_5 (
    .re     (intrpt_status_intrpt_status_5_re),
    .we     (intrpt_status_intrpt_status_5_we),
    .wd     (intrpt_status_intrpt_status_5_wd),
    .d      (hw2reg.intrpt_status[5].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[5].qe),
    .q      (reg2hw.intrpt_status[5].q ),
    .qs     (intrpt_status_intrpt_status_5_qs)
  );


  // F[intrpt_status_6]: 6:6
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_6 (
    .re     (intrpt_status_intrpt_status_6_re),
    .we     (intrpt_status_intrpt_status_6_we),
    .wd     (intrpt_status_intrpt_status_6_wd),
    .d      (hw2reg.intrpt_status[6].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[6].qe),
    .q      (reg2hw.intrpt_status[6].q ),
    .qs     (intrpt_status_intrpt_status_6_qs)
  );


  // F[intrpt_status_7]: 7:7
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_7 (
    .re     (intrpt_status_intrpt_status_7_re),
    .we     (intrpt_status_intrpt_status_7_we),
    .wd     (intrpt_status_intrpt_status_7_wd),
    .d      (hw2reg.intrpt_status[7].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[7].qe),
    .q      (reg2hw.intrpt_status[7].q ),
    .qs     (intrpt_status_intrpt_status_7_qs)
  );


  // F[intrpt_status_8]: 8:8
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_8 (
    .re     (intrpt_status_intrpt_status_8_re),
    .we     (intrpt_status_intrpt_status_8_we),
    .wd     (intrpt_status_intrpt_status_8_wd),
    .d      (hw2reg.intrpt_status[8].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[8].qe),
    .q      (reg2hw.intrpt_status[8].q ),
    .qs     (intrpt_status_intrpt_status_8_qs)
  );


  // F[intrpt_status_9]: 9:9
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_9 (
    .re     (intrpt_status_intrpt_status_9_re),
    .we     (intrpt_status_intrpt_status_9_we),
    .wd     (intrpt_status_intrpt_status_9_wd),
    .d      (hw2reg.intrpt_status[9].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[9].qe),
    .q      (reg2hw.intrpt_status[9].q ),
    .qs     (intrpt_status_intrpt_status_9_qs)
  );


  // F[intrpt_status_10]: 10:10
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_10 (
    .re     (intrpt_status_intrpt_status_10_re),
    .we     (intrpt_status_intrpt_status_10_we),
    .wd     (intrpt_status_intrpt_status_10_wd),
    .d      (hw2reg.intrpt_status[10].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[10].qe),
    .q      (reg2hw.intrpt_status[10].q ),
    .qs     (intrpt_status_intrpt_status_10_qs)
  );


  // F[intrpt_status_11]: 11:11
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_11 (
    .re     (intrpt_status_intrpt_status_11_re),
    .we     (intrpt_status_intrpt_status_11_we),
    .wd     (intrpt_status_intrpt_status_11_wd),
    .d      (hw2reg.intrpt_status[11].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[11].qe),
    .q      (reg2hw.intrpt_status[11].q ),
    .qs     (intrpt_status_intrpt_status_11_qs)
  );


  // F[intrpt_status_12]: 12:12
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_12 (
    .re     (intrpt_status_intrpt_status_12_re),
    .we     (intrpt_status_intrpt_status_12_we),
    .wd     (intrpt_status_intrpt_status_12_wd),
    .d      (hw2reg.intrpt_status[12].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[12].qe),
    .q      (reg2hw.intrpt_status[12].q ),
    .qs     (intrpt_status_intrpt_status_12_qs)
  );


  // F[intrpt_status_13]: 13:13
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_13 (
    .re     (intrpt_status_intrpt_status_13_re),
    .we     (intrpt_status_intrpt_status_13_we),
    .wd     (intrpt_status_intrpt_status_13_wd),
    .d      (hw2reg.intrpt_status[13].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[13].qe),
    .q      (reg2hw.intrpt_status[13].q ),
    .qs     (intrpt_status_intrpt_status_13_qs)
  );


  // F[intrpt_status_14]: 14:14
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_14 (
    .re     (intrpt_status_intrpt_status_14_re),
    .we     (intrpt_status_intrpt_status_14_we),
    .wd     (intrpt_status_intrpt_status_14_wd),
    .d      (hw2reg.intrpt_status[14].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[14].qe),
    .q      (reg2hw.intrpt_status[14].q ),
    .qs     (intrpt_status_intrpt_status_14_qs)
  );


  // F[intrpt_status_15]: 15:15
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_15 (
    .re     (intrpt_status_intrpt_status_15_re),
    .we     (intrpt_status_intrpt_status_15_we),
    .wd     (intrpt_status_intrpt_status_15_wd),
    .d      (hw2reg.intrpt_status[15].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[15].qe),
    .q      (reg2hw.intrpt_status[15].q ),
    .qs     (intrpt_status_intrpt_status_15_qs)
  );


  // F[intrpt_status_16]: 16:16
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_16 (
    .re     (intrpt_status_intrpt_status_16_re),
    .we     (intrpt_status_intrpt_status_16_we),
    .wd     (intrpt_status_intrpt_status_16_wd),
    .d      (hw2reg.intrpt_status[16].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[16].qe),
    .q      (reg2hw.intrpt_status[16].q ),
    .qs     (intrpt_status_intrpt_status_16_qs)
  );


  // F[intrpt_status_17]: 17:17
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_17 (
    .re     (intrpt_status_intrpt_status_17_re),
    .we     (intrpt_status_intrpt_status_17_we),
    .wd     (intrpt_status_intrpt_status_17_wd),
    .d      (hw2reg.intrpt_status[17].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[17].qe),
    .q      (reg2hw.intrpt_status[17].q ),
    .qs     (intrpt_status_intrpt_status_17_qs)
  );


  // F[intrpt_status_18]: 18:18
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_18 (
    .re     (intrpt_status_intrpt_status_18_re),
    .we     (intrpt_status_intrpt_status_18_we),
    .wd     (intrpt_status_intrpt_status_18_wd),
    .d      (hw2reg.intrpt_status[18].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[18].qe),
    .q      (reg2hw.intrpt_status[18].q ),
    .qs     (intrpt_status_intrpt_status_18_qs)
  );


  // F[intrpt_status_19]: 19:19
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_19 (
    .re     (intrpt_status_intrpt_status_19_re),
    .we     (intrpt_status_intrpt_status_19_we),
    .wd     (intrpt_status_intrpt_status_19_wd),
    .d      (hw2reg.intrpt_status[19].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[19].qe),
    .q      (reg2hw.intrpt_status[19].q ),
    .qs     (intrpt_status_intrpt_status_19_qs)
  );


  // F[intrpt_status_20]: 20:20
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_20 (
    .re     (intrpt_status_intrpt_status_20_re),
    .we     (intrpt_status_intrpt_status_20_we),
    .wd     (intrpt_status_intrpt_status_20_wd),
    .d      (hw2reg.intrpt_status[20].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[20].qe),
    .q      (reg2hw.intrpt_status[20].q ),
    .qs     (intrpt_status_intrpt_status_20_qs)
  );


  // F[intrpt_status_21]: 21:21
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_21 (
    .re     (intrpt_status_intrpt_status_21_re),
    .we     (intrpt_status_intrpt_status_21_we),
    .wd     (intrpt_status_intrpt_status_21_wd),
    .d      (hw2reg.intrpt_status[21].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[21].qe),
    .q      (reg2hw.intrpt_status[21].q ),
    .qs     (intrpt_status_intrpt_status_21_qs)
  );


  // F[intrpt_status_22]: 22:22
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_22 (
    .re     (intrpt_status_intrpt_status_22_re),
    .we     (intrpt_status_intrpt_status_22_we),
    .wd     (intrpt_status_intrpt_status_22_wd),
    .d      (hw2reg.intrpt_status[22].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[22].qe),
    .q      (reg2hw.intrpt_status[22].q ),
    .qs     (intrpt_status_intrpt_status_22_qs)
  );


  // F[intrpt_status_23]: 23:23
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_23 (
    .re     (intrpt_status_intrpt_status_23_re),
    .we     (intrpt_status_intrpt_status_23_we),
    .wd     (intrpt_status_intrpt_status_23_wd),
    .d      (hw2reg.intrpt_status[23].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[23].qe),
    .q      (reg2hw.intrpt_status[23].q ),
    .qs     (intrpt_status_intrpt_status_23_qs)
  );


  // F[intrpt_status_24]: 24:24
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_24 (
    .re     (intrpt_status_intrpt_status_24_re),
    .we     (intrpt_status_intrpt_status_24_we),
    .wd     (intrpt_status_intrpt_status_24_wd),
    .d      (hw2reg.intrpt_status[24].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[24].qe),
    .q      (reg2hw.intrpt_status[24].q ),
    .qs     (intrpt_status_intrpt_status_24_qs)
  );


  // F[intrpt_status_25]: 25:25
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_25 (
    .re     (intrpt_status_intrpt_status_25_re),
    .we     (intrpt_status_intrpt_status_25_we),
    .wd     (intrpt_status_intrpt_status_25_wd),
    .d      (hw2reg.intrpt_status[25].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[25].qe),
    .q      (reg2hw.intrpt_status[25].q ),
    .qs     (intrpt_status_intrpt_status_25_qs)
  );


  // F[intrpt_status_26]: 26:26
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_26 (
    .re     (intrpt_status_intrpt_status_26_re),
    .we     (intrpt_status_intrpt_status_26_we),
    .wd     (intrpt_status_intrpt_status_26_wd),
    .d      (hw2reg.intrpt_status[26].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[26].qe),
    .q      (reg2hw.intrpt_status[26].q ),
    .qs     (intrpt_status_intrpt_status_26_qs)
  );


  // F[intrpt_status_27]: 27:27
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_27 (
    .re     (intrpt_status_intrpt_status_27_re),
    .we     (intrpt_status_intrpt_status_27_we),
    .wd     (intrpt_status_intrpt_status_27_wd),
    .d      (hw2reg.intrpt_status[27].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[27].qe),
    .q      (reg2hw.intrpt_status[27].q ),
    .qs     (intrpt_status_intrpt_status_27_qs)
  );


  // F[intrpt_status_28]: 28:28
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_28 (
    .re     (intrpt_status_intrpt_status_28_re),
    .we     (intrpt_status_intrpt_status_28_we),
    .wd     (intrpt_status_intrpt_status_28_wd),
    .d      (hw2reg.intrpt_status[28].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[28].qe),
    .q      (reg2hw.intrpt_status[28].q ),
    .qs     (intrpt_status_intrpt_status_28_qs)
  );


  // F[intrpt_status_29]: 29:29
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_29 (
    .re     (intrpt_status_intrpt_status_29_re),
    .we     (intrpt_status_intrpt_status_29_we),
    .wd     (intrpt_status_intrpt_status_29_wd),
    .d      (hw2reg.intrpt_status[29].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[29].qe),
    .q      (reg2hw.intrpt_status[29].q ),
    .qs     (intrpt_status_intrpt_status_29_qs)
  );


  // F[intrpt_status_30]: 30:30
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_30 (
    .re     (intrpt_status_intrpt_status_30_re),
    .we     (intrpt_status_intrpt_status_30_we),
    .wd     (intrpt_status_intrpt_status_30_wd),
    .d      (hw2reg.intrpt_status[30].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[30].qe),
    .q      (reg2hw.intrpt_status[30].q ),
    .qs     (intrpt_status_intrpt_status_30_qs)
  );


  // F[intrpt_status_31]: 31:31
  prim_subreg_ext #(
    .DW    (1)
  ) u_intrpt_status_intrpt_status_31 (
    .re     (intrpt_status_intrpt_status_31_re),
    .we     (intrpt_status_intrpt_status_31_we),
    .wd     (intrpt_status_intrpt_status_31_wd),
    .d      (hw2reg.intrpt_status[31].d),
    .qre    (),
    .qe     (reg2hw.intrpt_status[31].qe),
    .q      (reg2hw.intrpt_status[31].q ),
    .qs     (intrpt_status_intrpt_status_31_qs)
  );




  // Subregister 0 of Multireg intrpt_rise_status
  // R[intrpt_rise_status]: V(False)

  // F[intrpt_rise_status_0]: 0:0
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_0 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_0_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_0_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[0].de),
    .d      (hw2reg.intrpt_rise_status[0].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[0].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_0_qs)
  );


  // F[intrpt_rise_status_1]: 1:1
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_1 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_1_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_1_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[1].de),
    .d      (hw2reg.intrpt_rise_status[1].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[1].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_1_qs)
  );


  // F[intrpt_rise_status_2]: 2:2
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_2 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_2_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_2_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[2].de),
    .d      (hw2reg.intrpt_rise_status[2].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[2].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_2_qs)
  );


  // F[intrpt_rise_status_3]: 3:3
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_3 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_3_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_3_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[3].de),
    .d      (hw2reg.intrpt_rise_status[3].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[3].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_3_qs)
  );


  // F[intrpt_rise_status_4]: 4:4
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_4 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_4_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_4_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[4].de),
    .d      (hw2reg.intrpt_rise_status[4].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[4].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_4_qs)
  );


  // F[intrpt_rise_status_5]: 5:5
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_5 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_5_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_5_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[5].de),
    .d      (hw2reg.intrpt_rise_status[5].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[5].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_5_qs)
  );


  // F[intrpt_rise_status_6]: 6:6
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_6 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_6_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_6_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[6].de),
    .d      (hw2reg.intrpt_rise_status[6].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[6].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_6_qs)
  );


  // F[intrpt_rise_status_7]: 7:7
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_7 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_7_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_7_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[7].de),
    .d      (hw2reg.intrpt_rise_status[7].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[7].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_7_qs)
  );


  // F[intrpt_rise_status_8]: 8:8
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_8 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_8_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_8_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[8].de),
    .d      (hw2reg.intrpt_rise_status[8].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[8].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_8_qs)
  );


  // F[intrpt_rise_status_9]: 9:9
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_9 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_9_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_9_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[9].de),
    .d      (hw2reg.intrpt_rise_status[9].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[9].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_9_qs)
  );


  // F[intrpt_rise_status_10]: 10:10
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_10 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_10_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_10_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[10].de),
    .d      (hw2reg.intrpt_rise_status[10].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[10].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_10_qs)
  );


  // F[intrpt_rise_status_11]: 11:11
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_11 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_11_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_11_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[11].de),
    .d      (hw2reg.intrpt_rise_status[11].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[11].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_11_qs)
  );


  // F[intrpt_rise_status_12]: 12:12
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_12 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_12_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_12_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[12].de),
    .d      (hw2reg.intrpt_rise_status[12].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[12].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_12_qs)
  );


  // F[intrpt_rise_status_13]: 13:13
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_13 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_13_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_13_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[13].de),
    .d      (hw2reg.intrpt_rise_status[13].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[13].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_13_qs)
  );


  // F[intrpt_rise_status_14]: 14:14
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_14 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_14_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_14_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[14].de),
    .d      (hw2reg.intrpt_rise_status[14].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[14].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_14_qs)
  );


  // F[intrpt_rise_status_15]: 15:15
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_15 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_15_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_15_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[15].de),
    .d      (hw2reg.intrpt_rise_status[15].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[15].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_15_qs)
  );


  // F[intrpt_rise_status_16]: 16:16
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_16 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_16_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_16_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[16].de),
    .d      (hw2reg.intrpt_rise_status[16].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[16].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_16_qs)
  );


  // F[intrpt_rise_status_17]: 17:17
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_17 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_17_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_17_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[17].de),
    .d      (hw2reg.intrpt_rise_status[17].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[17].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_17_qs)
  );


  // F[intrpt_rise_status_18]: 18:18
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_18 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_18_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_18_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[18].de),
    .d      (hw2reg.intrpt_rise_status[18].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[18].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_18_qs)
  );


  // F[intrpt_rise_status_19]: 19:19
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_19 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_19_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_19_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[19].de),
    .d      (hw2reg.intrpt_rise_status[19].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[19].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_19_qs)
  );


  // F[intrpt_rise_status_20]: 20:20
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_20 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_20_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_20_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[20].de),
    .d      (hw2reg.intrpt_rise_status[20].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[20].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_20_qs)
  );


  // F[intrpt_rise_status_21]: 21:21
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_21 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_21_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_21_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[21].de),
    .d      (hw2reg.intrpt_rise_status[21].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[21].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_21_qs)
  );


  // F[intrpt_rise_status_22]: 22:22
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_22 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_22_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_22_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[22].de),
    .d      (hw2reg.intrpt_rise_status[22].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[22].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_22_qs)
  );


  // F[intrpt_rise_status_23]: 23:23
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_23 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_23_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_23_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[23].de),
    .d      (hw2reg.intrpt_rise_status[23].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[23].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_23_qs)
  );


  // F[intrpt_rise_status_24]: 24:24
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_24 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_24_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_24_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[24].de),
    .d      (hw2reg.intrpt_rise_status[24].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[24].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_24_qs)
  );


  // F[intrpt_rise_status_25]: 25:25
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_25 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_25_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_25_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[25].de),
    .d      (hw2reg.intrpt_rise_status[25].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[25].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_25_qs)
  );


  // F[intrpt_rise_status_26]: 26:26
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_26 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_26_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_26_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[26].de),
    .d      (hw2reg.intrpt_rise_status[26].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[26].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_26_qs)
  );


  // F[intrpt_rise_status_27]: 27:27
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_27 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_27_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_27_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[27].de),
    .d      (hw2reg.intrpt_rise_status[27].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[27].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_27_qs)
  );


  // F[intrpt_rise_status_28]: 28:28
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_28 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_28_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_28_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[28].de),
    .d      (hw2reg.intrpt_rise_status[28].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[28].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_28_qs)
  );


  // F[intrpt_rise_status_29]: 29:29
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_29 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_29_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_29_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[29].de),
    .d      (hw2reg.intrpt_rise_status[29].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[29].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_29_qs)
  );


  // F[intrpt_rise_status_30]: 30:30
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_30 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_30_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_30_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[30].de),
    .d      (hw2reg.intrpt_rise_status[30].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[30].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_30_qs)
  );


  // F[intrpt_rise_status_31]: 31:31
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_rise_status_intrpt_rise_status_31 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_rise_status_intrpt_rise_status_31_we),
    .wd     (intrpt_rise_status_intrpt_rise_status_31_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_rise_status[31].de),
    .d      (hw2reg.intrpt_rise_status[31].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_rise_status[31].q ),

    // to register interface (read)
    .qs     (intrpt_rise_status_intrpt_rise_status_31_qs)
  );




  // Subregister 0 of Multireg intrpt_fall_status
  // R[intrpt_fall_status]: V(False)

  // F[intrpt_fall_status_0]: 0:0
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_0 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_0_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_0_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[0].de),
    .d      (hw2reg.intrpt_fall_status[0].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[0].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_0_qs)
  );


  // F[intrpt_fall_status_1]: 1:1
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_1 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_1_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_1_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[1].de),
    .d      (hw2reg.intrpt_fall_status[1].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[1].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_1_qs)
  );


  // F[intrpt_fall_status_2]: 2:2
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_2 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_2_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_2_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[2].de),
    .d      (hw2reg.intrpt_fall_status[2].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[2].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_2_qs)
  );


  // F[intrpt_fall_status_3]: 3:3
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_3 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_3_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_3_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[3].de),
    .d      (hw2reg.intrpt_fall_status[3].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[3].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_3_qs)
  );


  // F[intrpt_fall_status_4]: 4:4
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_4 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_4_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_4_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[4].de),
    .d      (hw2reg.intrpt_fall_status[4].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[4].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_4_qs)
  );


  // F[intrpt_fall_status_5]: 5:5
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_5 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_5_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_5_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[5].de),
    .d      (hw2reg.intrpt_fall_status[5].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[5].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_5_qs)
  );


  // F[intrpt_fall_status_6]: 6:6
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_6 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_6_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_6_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[6].de),
    .d      (hw2reg.intrpt_fall_status[6].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[6].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_6_qs)
  );


  // F[intrpt_fall_status_7]: 7:7
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_7 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_7_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_7_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[7].de),
    .d      (hw2reg.intrpt_fall_status[7].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[7].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_7_qs)
  );


  // F[intrpt_fall_status_8]: 8:8
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_8 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_8_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_8_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[8].de),
    .d      (hw2reg.intrpt_fall_status[8].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[8].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_8_qs)
  );


  // F[intrpt_fall_status_9]: 9:9
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_9 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_9_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_9_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[9].de),
    .d      (hw2reg.intrpt_fall_status[9].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[9].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_9_qs)
  );


  // F[intrpt_fall_status_10]: 10:10
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_10 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_10_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_10_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[10].de),
    .d      (hw2reg.intrpt_fall_status[10].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[10].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_10_qs)
  );


  // F[intrpt_fall_status_11]: 11:11
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_11 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_11_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_11_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[11].de),
    .d      (hw2reg.intrpt_fall_status[11].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[11].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_11_qs)
  );


  // F[intrpt_fall_status_12]: 12:12
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_12 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_12_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_12_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[12].de),
    .d      (hw2reg.intrpt_fall_status[12].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[12].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_12_qs)
  );


  // F[intrpt_fall_status_13]: 13:13
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_13 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_13_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_13_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[13].de),
    .d      (hw2reg.intrpt_fall_status[13].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[13].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_13_qs)
  );


  // F[intrpt_fall_status_14]: 14:14
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_14 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_14_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_14_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[14].de),
    .d      (hw2reg.intrpt_fall_status[14].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[14].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_14_qs)
  );


  // F[intrpt_fall_status_15]: 15:15
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_15 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_15_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_15_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[15].de),
    .d      (hw2reg.intrpt_fall_status[15].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[15].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_15_qs)
  );


  // F[intrpt_fall_status_16]: 16:16
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_16 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_16_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_16_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[16].de),
    .d      (hw2reg.intrpt_fall_status[16].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[16].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_16_qs)
  );


  // F[intrpt_fall_status_17]: 17:17
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_17 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_17_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_17_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[17].de),
    .d      (hw2reg.intrpt_fall_status[17].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[17].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_17_qs)
  );


  // F[intrpt_fall_status_18]: 18:18
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_18 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_18_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_18_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[18].de),
    .d      (hw2reg.intrpt_fall_status[18].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[18].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_18_qs)
  );


  // F[intrpt_fall_status_19]: 19:19
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_19 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_19_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_19_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[19].de),
    .d      (hw2reg.intrpt_fall_status[19].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[19].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_19_qs)
  );


  // F[intrpt_fall_status_20]: 20:20
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_20 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_20_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_20_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[20].de),
    .d      (hw2reg.intrpt_fall_status[20].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[20].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_20_qs)
  );


  // F[intrpt_fall_status_21]: 21:21
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_21 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_21_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_21_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[21].de),
    .d      (hw2reg.intrpt_fall_status[21].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[21].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_21_qs)
  );


  // F[intrpt_fall_status_22]: 22:22
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_22 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_22_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_22_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[22].de),
    .d      (hw2reg.intrpt_fall_status[22].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[22].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_22_qs)
  );


  // F[intrpt_fall_status_23]: 23:23
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_23 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_23_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_23_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[23].de),
    .d      (hw2reg.intrpt_fall_status[23].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[23].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_23_qs)
  );


  // F[intrpt_fall_status_24]: 24:24
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_24 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_24_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_24_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[24].de),
    .d      (hw2reg.intrpt_fall_status[24].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[24].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_24_qs)
  );


  // F[intrpt_fall_status_25]: 25:25
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_25 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_25_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_25_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[25].de),
    .d      (hw2reg.intrpt_fall_status[25].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[25].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_25_qs)
  );


  // F[intrpt_fall_status_26]: 26:26
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_26 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_26_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_26_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[26].de),
    .d      (hw2reg.intrpt_fall_status[26].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[26].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_26_qs)
  );


  // F[intrpt_fall_status_27]: 27:27
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_27 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_27_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_27_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[27].de),
    .d      (hw2reg.intrpt_fall_status[27].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[27].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_27_qs)
  );


  // F[intrpt_fall_status_28]: 28:28
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_28 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_28_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_28_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[28].de),
    .d      (hw2reg.intrpt_fall_status[28].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[28].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_28_qs)
  );


  // F[intrpt_fall_status_29]: 29:29
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_29 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_29_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_29_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[29].de),
    .d      (hw2reg.intrpt_fall_status[29].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[29].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_29_qs)
  );


  // F[intrpt_fall_status_30]: 30:30
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_30 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_30_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_30_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[30].de),
    .d      (hw2reg.intrpt_fall_status[30].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[30].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_30_qs)
  );


  // F[intrpt_fall_status_31]: 31:31
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_fall_status_intrpt_fall_status_31 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_fall_status_intrpt_fall_status_31_we),
    .wd     (intrpt_fall_status_intrpt_fall_status_31_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_fall_status[31].de),
    .d      (hw2reg.intrpt_fall_status[31].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_fall_status[31].q ),

    // to register interface (read)
    .qs     (intrpt_fall_status_intrpt_fall_status_31_qs)
  );




  // Subregister 0 of Multireg intrpt_lvl_high_status
  // R[intrpt_lvl_high_status]: V(False)

  // F[intrpt_lvl_high_status_0]: 0:0
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_0 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_0_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_0_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[0].de),
    .d      (hw2reg.intrpt_lvl_high_status[0].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[0].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_0_qs)
  );


  // F[intrpt_lvl_high_status_1]: 1:1
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_1 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_1_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_1_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[1].de),
    .d      (hw2reg.intrpt_lvl_high_status[1].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[1].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_1_qs)
  );


  // F[intrpt_lvl_high_status_2]: 2:2
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_2 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_2_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_2_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[2].de),
    .d      (hw2reg.intrpt_lvl_high_status[2].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[2].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_2_qs)
  );


  // F[intrpt_lvl_high_status_3]: 3:3
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_3 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_3_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_3_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[3].de),
    .d      (hw2reg.intrpt_lvl_high_status[3].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[3].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_3_qs)
  );


  // F[intrpt_lvl_high_status_4]: 4:4
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_4 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_4_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_4_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[4].de),
    .d      (hw2reg.intrpt_lvl_high_status[4].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[4].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_4_qs)
  );


  // F[intrpt_lvl_high_status_5]: 5:5
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_5 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_5_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_5_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[5].de),
    .d      (hw2reg.intrpt_lvl_high_status[5].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[5].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_5_qs)
  );


  // F[intrpt_lvl_high_status_6]: 6:6
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_6 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_6_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_6_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[6].de),
    .d      (hw2reg.intrpt_lvl_high_status[6].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[6].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_6_qs)
  );


  // F[intrpt_lvl_high_status_7]: 7:7
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_7 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_7_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_7_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[7].de),
    .d      (hw2reg.intrpt_lvl_high_status[7].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[7].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_7_qs)
  );


  // F[intrpt_lvl_high_status_8]: 8:8
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_8 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_8_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_8_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[8].de),
    .d      (hw2reg.intrpt_lvl_high_status[8].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[8].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_8_qs)
  );


  // F[intrpt_lvl_high_status_9]: 9:9
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_9 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_9_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_9_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[9].de),
    .d      (hw2reg.intrpt_lvl_high_status[9].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[9].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_9_qs)
  );


  // F[intrpt_lvl_high_status_10]: 10:10
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_10 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_10_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_10_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[10].de),
    .d      (hw2reg.intrpt_lvl_high_status[10].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[10].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_10_qs)
  );


  // F[intrpt_lvl_high_status_11]: 11:11
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_11 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_11_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_11_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[11].de),
    .d      (hw2reg.intrpt_lvl_high_status[11].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[11].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_11_qs)
  );


  // F[intrpt_lvl_high_status_12]: 12:12
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_12 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_12_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_12_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[12].de),
    .d      (hw2reg.intrpt_lvl_high_status[12].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[12].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_12_qs)
  );


  // F[intrpt_lvl_high_status_13]: 13:13
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_13 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_13_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_13_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[13].de),
    .d      (hw2reg.intrpt_lvl_high_status[13].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[13].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_13_qs)
  );


  // F[intrpt_lvl_high_status_14]: 14:14
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_14 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_14_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_14_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[14].de),
    .d      (hw2reg.intrpt_lvl_high_status[14].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[14].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_14_qs)
  );


  // F[intrpt_lvl_high_status_15]: 15:15
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_15 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_15_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_15_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[15].de),
    .d      (hw2reg.intrpt_lvl_high_status[15].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[15].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_15_qs)
  );


  // F[intrpt_lvl_high_status_16]: 16:16
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_16 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_16_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_16_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[16].de),
    .d      (hw2reg.intrpt_lvl_high_status[16].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[16].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_16_qs)
  );


  // F[intrpt_lvl_high_status_17]: 17:17
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_17 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_17_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_17_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[17].de),
    .d      (hw2reg.intrpt_lvl_high_status[17].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[17].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_17_qs)
  );


  // F[intrpt_lvl_high_status_18]: 18:18
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_18 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_18_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_18_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[18].de),
    .d      (hw2reg.intrpt_lvl_high_status[18].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[18].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_18_qs)
  );


  // F[intrpt_lvl_high_status_19]: 19:19
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_19 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_19_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_19_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[19].de),
    .d      (hw2reg.intrpt_lvl_high_status[19].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[19].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_19_qs)
  );


  // F[intrpt_lvl_high_status_20]: 20:20
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_20 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_20_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_20_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[20].de),
    .d      (hw2reg.intrpt_lvl_high_status[20].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[20].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_20_qs)
  );


  // F[intrpt_lvl_high_status_21]: 21:21
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_21 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_21_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_21_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[21].de),
    .d      (hw2reg.intrpt_lvl_high_status[21].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[21].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_21_qs)
  );


  // F[intrpt_lvl_high_status_22]: 22:22
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_22 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_22_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_22_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[22].de),
    .d      (hw2reg.intrpt_lvl_high_status[22].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[22].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_22_qs)
  );


  // F[intrpt_lvl_high_status_23]: 23:23
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_23 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_23_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_23_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[23].de),
    .d      (hw2reg.intrpt_lvl_high_status[23].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[23].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_23_qs)
  );


  // F[intrpt_lvl_high_status_24]: 24:24
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_24 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_24_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_24_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[24].de),
    .d      (hw2reg.intrpt_lvl_high_status[24].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[24].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_24_qs)
  );


  // F[intrpt_lvl_high_status_25]: 25:25
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_25 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_25_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_25_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[25].de),
    .d      (hw2reg.intrpt_lvl_high_status[25].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[25].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_25_qs)
  );


  // F[intrpt_lvl_high_status_26]: 26:26
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_26 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_26_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_26_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[26].de),
    .d      (hw2reg.intrpt_lvl_high_status[26].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[26].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_26_qs)
  );


  // F[intrpt_lvl_high_status_27]: 27:27
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_27 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_27_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_27_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[27].de),
    .d      (hw2reg.intrpt_lvl_high_status[27].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[27].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_27_qs)
  );


  // F[intrpt_lvl_high_status_28]: 28:28
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_28 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_28_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_28_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[28].de),
    .d      (hw2reg.intrpt_lvl_high_status[28].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[28].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_28_qs)
  );


  // F[intrpt_lvl_high_status_29]: 29:29
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_29 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_29_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_29_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[29].de),
    .d      (hw2reg.intrpt_lvl_high_status[29].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[29].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_29_qs)
  );


  // F[intrpt_lvl_high_status_30]: 30:30
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_30 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_30_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_30_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[30].de),
    .d      (hw2reg.intrpt_lvl_high_status[30].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[30].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_30_qs)
  );


  // F[intrpt_lvl_high_status_31]: 31:31
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_31 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_high_status_intrpt_lvl_high_status_31_we),
    .wd     (intrpt_lvl_high_status_intrpt_lvl_high_status_31_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_high_status[31].de),
    .d      (hw2reg.intrpt_lvl_high_status[31].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_high_status[31].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_high_status_intrpt_lvl_high_status_31_qs)
  );




  // Subregister 0 of Multireg intrpt_lvl_low_status
  // R[intrpt_lvl_low_status]: V(False)

  // F[intrpt_lvl_low_status_0]: 0:0
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_0 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_0_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_0_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[0].de),
    .d      (hw2reg.intrpt_lvl_low_status[0].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[0].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_0_qs)
  );


  // F[intrpt_lvl_low_status_1]: 1:1
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_1 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_1_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_1_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[1].de),
    .d      (hw2reg.intrpt_lvl_low_status[1].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[1].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_1_qs)
  );


  // F[intrpt_lvl_low_status_2]: 2:2
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_2 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_2_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_2_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[2].de),
    .d      (hw2reg.intrpt_lvl_low_status[2].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[2].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_2_qs)
  );


  // F[intrpt_lvl_low_status_3]: 3:3
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_3 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_3_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_3_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[3].de),
    .d      (hw2reg.intrpt_lvl_low_status[3].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[3].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_3_qs)
  );


  // F[intrpt_lvl_low_status_4]: 4:4
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_4 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_4_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_4_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[4].de),
    .d      (hw2reg.intrpt_lvl_low_status[4].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[4].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_4_qs)
  );


  // F[intrpt_lvl_low_status_5]: 5:5
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_5 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_5_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_5_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[5].de),
    .d      (hw2reg.intrpt_lvl_low_status[5].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[5].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_5_qs)
  );


  // F[intrpt_lvl_low_status_6]: 6:6
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_6 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_6_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_6_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[6].de),
    .d      (hw2reg.intrpt_lvl_low_status[6].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[6].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_6_qs)
  );


  // F[intrpt_lvl_low_status_7]: 7:7
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_7 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_7_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_7_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[7].de),
    .d      (hw2reg.intrpt_lvl_low_status[7].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[7].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_7_qs)
  );


  // F[intrpt_lvl_low_status_8]: 8:8
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_8 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_8_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_8_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[8].de),
    .d      (hw2reg.intrpt_lvl_low_status[8].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[8].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_8_qs)
  );


  // F[intrpt_lvl_low_status_9]: 9:9
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_9 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_9_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_9_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[9].de),
    .d      (hw2reg.intrpt_lvl_low_status[9].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[9].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_9_qs)
  );


  // F[intrpt_lvl_low_status_10]: 10:10
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_10 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_10_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_10_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[10].de),
    .d      (hw2reg.intrpt_lvl_low_status[10].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[10].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_10_qs)
  );


  // F[intrpt_lvl_low_status_11]: 11:11
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_11 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_11_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_11_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[11].de),
    .d      (hw2reg.intrpt_lvl_low_status[11].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[11].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_11_qs)
  );


  // F[intrpt_lvl_low_status_12]: 12:12
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_12 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_12_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_12_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[12].de),
    .d      (hw2reg.intrpt_lvl_low_status[12].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[12].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_12_qs)
  );


  // F[intrpt_lvl_low_status_13]: 13:13
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_13 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_13_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_13_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[13].de),
    .d      (hw2reg.intrpt_lvl_low_status[13].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[13].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_13_qs)
  );


  // F[intrpt_lvl_low_status_14]: 14:14
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_14 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_14_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_14_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[14].de),
    .d      (hw2reg.intrpt_lvl_low_status[14].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[14].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_14_qs)
  );


  // F[intrpt_lvl_low_status_15]: 15:15
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_15 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_15_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_15_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[15].de),
    .d      (hw2reg.intrpt_lvl_low_status[15].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[15].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_15_qs)
  );


  // F[intrpt_lvl_low_status_16]: 16:16
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_16 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_16_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_16_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[16].de),
    .d      (hw2reg.intrpt_lvl_low_status[16].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[16].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_16_qs)
  );


  // F[intrpt_lvl_low_status_17]: 17:17
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_17 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_17_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_17_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[17].de),
    .d      (hw2reg.intrpt_lvl_low_status[17].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[17].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_17_qs)
  );


  // F[intrpt_lvl_low_status_18]: 18:18
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_18 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_18_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_18_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[18].de),
    .d      (hw2reg.intrpt_lvl_low_status[18].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[18].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_18_qs)
  );


  // F[intrpt_lvl_low_status_19]: 19:19
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_19 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_19_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_19_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[19].de),
    .d      (hw2reg.intrpt_lvl_low_status[19].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[19].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_19_qs)
  );


  // F[intrpt_lvl_low_status_20]: 20:20
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_20 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_20_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_20_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[20].de),
    .d      (hw2reg.intrpt_lvl_low_status[20].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[20].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_20_qs)
  );


  // F[intrpt_lvl_low_status_21]: 21:21
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_21 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_21_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_21_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[21].de),
    .d      (hw2reg.intrpt_lvl_low_status[21].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[21].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_21_qs)
  );


  // F[intrpt_lvl_low_status_22]: 22:22
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_22 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_22_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_22_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[22].de),
    .d      (hw2reg.intrpt_lvl_low_status[22].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[22].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_22_qs)
  );


  // F[intrpt_lvl_low_status_23]: 23:23
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_23 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_23_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_23_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[23].de),
    .d      (hw2reg.intrpt_lvl_low_status[23].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[23].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_23_qs)
  );


  // F[intrpt_lvl_low_status_24]: 24:24
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_24 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_24_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_24_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[24].de),
    .d      (hw2reg.intrpt_lvl_low_status[24].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[24].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_24_qs)
  );


  // F[intrpt_lvl_low_status_25]: 25:25
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_25 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_25_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_25_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[25].de),
    .d      (hw2reg.intrpt_lvl_low_status[25].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[25].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_25_qs)
  );


  // F[intrpt_lvl_low_status_26]: 26:26
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_26 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_26_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_26_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[26].de),
    .d      (hw2reg.intrpt_lvl_low_status[26].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[26].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_26_qs)
  );


  // F[intrpt_lvl_low_status_27]: 27:27
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_27 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_27_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_27_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[27].de),
    .d      (hw2reg.intrpt_lvl_low_status[27].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[27].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_27_qs)
  );


  // F[intrpt_lvl_low_status_28]: 28:28
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_28 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_28_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_28_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[28].de),
    .d      (hw2reg.intrpt_lvl_low_status[28].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[28].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_28_qs)
  );


  // F[intrpt_lvl_low_status_29]: 29:29
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_29 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_29_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_29_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[29].de),
    .d      (hw2reg.intrpt_lvl_low_status[29].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[29].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_29_qs)
  );


  // F[intrpt_lvl_low_status_30]: 30:30
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_30 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_30_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_30_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[30].de),
    .d      (hw2reg.intrpt_lvl_low_status[30].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[30].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_30_qs)
  );


  // F[intrpt_lvl_low_status_31]: 31:31
  prim_subreg #(
    .DW      (1),
    .SWACCESS("W1C"),
    .RESVAL  (1'h0)
  ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_31 (
    .clk_i   (clk_i    ),
    .rst_ni  (rst_ni  ),

    // from register interface
    .we     (intrpt_lvl_low_status_intrpt_lvl_low_status_31_we),
    .wd     (intrpt_lvl_low_status_intrpt_lvl_low_status_31_wd),

    // from internal hardware
    .de     (hw2reg.intrpt_lvl_low_status[31].de),
    .d      (hw2reg.intrpt_lvl_low_status[31].d ),

    // to internal hardware
    .qe     (),
    .q      (reg2hw.intrpt_lvl_low_status[31].q ),

    // to register interface (read)
    .qs     (intrpt_lvl_low_status_intrpt_lvl_low_status_31_qs)
  );





  logic [18:0] addr_hit;
  always_comb begin
    addr_hit = '0;
    addr_hit[ 0] = (reg_addr == GPIO_INFO_OFFSET);
    addr_hit[ 1] = (reg_addr == GPIO_CFG_OFFSET);
    addr_hit[ 2] = (reg_addr == GPIO_GPIO_MODE_0_OFFSET);
    addr_hit[ 3] = (reg_addr == GPIO_GPIO_MODE_1_OFFSET);
    addr_hit[ 4] = (reg_addr == GPIO_GPIO_EN_OFFSET);
    addr_hit[ 5] = (reg_addr == GPIO_GPIO_IN_OFFSET);
    addr_hit[ 6] = (reg_addr == GPIO_GPIO_OUT_OFFSET);
    addr_hit[ 7] = (reg_addr == GPIO_GPIO_SET_OFFSET);
    addr_hit[ 8] = (reg_addr == GPIO_GPIO_CLEAR_OFFSET);
    addr_hit[ 9] = (reg_addr == GPIO_GPIO_TOGGLE_OFFSET);
    addr_hit[10] = (reg_addr == GPIO_INTRPT_RISE_EN_OFFSET);
    addr_hit[11] = (reg_addr == GPIO_INTRPT_FALL_EN_OFFSET);
    addr_hit[12] = (reg_addr == GPIO_INTRPT_LVL_HIGH_EN_OFFSET);
    addr_hit[13] = (reg_addr == GPIO_INTRPT_LVL_LOW_EN_OFFSET);
    addr_hit[14] = (reg_addr == GPIO_INTRPT_STATUS_OFFSET);
    addr_hit[15] = (reg_addr == GPIO_INTRPT_RISE_STATUS_OFFSET);
    addr_hit[16] = (reg_addr == GPIO_INTRPT_FALL_STATUS_OFFSET);
    addr_hit[17] = (reg_addr == GPIO_INTRPT_LVL_HIGH_STATUS_OFFSET);
    addr_hit[18] = (reg_addr == GPIO_INTRPT_LVL_LOW_STATUS_OFFSET);
  end

  assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;

  // Check sub-word write is permitted
  always_comb begin
    wr_err = (reg_we &
              ((addr_hit[ 0] & (|(GPIO_PERMIT[ 0] & ~reg_be))) |
               (addr_hit[ 1] & (|(GPIO_PERMIT[ 1] & ~reg_be))) |
               (addr_hit[ 2] & (|(GPIO_PERMIT[ 2] & ~reg_be))) |
               (addr_hit[ 3] & (|(GPIO_PERMIT[ 3] & ~reg_be))) |
               (addr_hit[ 4] & (|(GPIO_PERMIT[ 4] & ~reg_be))) |
               (addr_hit[ 5] & (|(GPIO_PERMIT[ 5] & ~reg_be))) |
               (addr_hit[ 6] & (|(GPIO_PERMIT[ 6] & ~reg_be))) |
               (addr_hit[ 7] & (|(GPIO_PERMIT[ 7] & ~reg_be))) |
               (addr_hit[ 8] & (|(GPIO_PERMIT[ 8] & ~reg_be))) |
               (addr_hit[ 9] & (|(GPIO_PERMIT[ 9] & ~reg_be))) |
               (addr_hit[10] & (|(GPIO_PERMIT[10] & ~reg_be))) |
               (addr_hit[11] & (|(GPIO_PERMIT[11] & ~reg_be))) |
               (addr_hit[12] & (|(GPIO_PERMIT[12] & ~reg_be))) |
               (addr_hit[13] & (|(GPIO_PERMIT[13] & ~reg_be))) |
               (addr_hit[14] & (|(GPIO_PERMIT[14] & ~reg_be))) |
               (addr_hit[15] & (|(GPIO_PERMIT[15] & ~reg_be))) |
               (addr_hit[16] & (|(GPIO_PERMIT[16] & ~reg_be))) |
               (addr_hit[17] & (|(GPIO_PERMIT[17] & ~reg_be))) |
               (addr_hit[18] & (|(GPIO_PERMIT[18] & ~reg_be)))));
  end

  assign info_gpio_cnt_re = addr_hit[0] & reg_re & !reg_error;

  assign info_version_re = addr_hit[0] & reg_re & !reg_error;

  assign cfg_glbl_intrpt_mode_we = addr_hit[1] & reg_we & !reg_error;
  assign cfg_glbl_intrpt_mode_wd = reg_wdata[0];

  assign cfg_pin_lvl_intrpt_mode_we = addr_hit[1] & reg_we & !reg_error;
  assign cfg_pin_lvl_intrpt_mode_wd = reg_wdata[1];

  assign gpio_mode_0_mode_0_we = addr_hit[2] & reg_we & !reg_error;
  assign gpio_mode_0_mode_0_wd = reg_wdata[1:0];

  assign gpio_mode_0_mode_1_we = addr_hit[2] & reg_we & !reg_error;
  assign gpio_mode_0_mode_1_wd = reg_wdata[3:2];

  assign gpio_mode_0_mode_2_we = addr_hit[2] & reg_we & !reg_error;
  assign gpio_mode_0_mode_2_wd = reg_wdata[5:4];

  assign gpio_mode_0_mode_3_we = addr_hit[2] & reg_we & !reg_error;
  assign gpio_mode_0_mode_3_wd = reg_wdata[7:6];

  assign gpio_mode_0_mode_4_we = addr_hit[2] & reg_we & !reg_error;
  assign gpio_mode_0_mode_4_wd = reg_wdata[9:8];

  assign gpio_mode_0_mode_5_we = addr_hit[2] & reg_we & !reg_error;
  assign gpio_mode_0_mode_5_wd = reg_wdata[11:10];

  assign gpio_mode_0_mode_6_we = addr_hit[2] & reg_we & !reg_error;
  assign gpio_mode_0_mode_6_wd = reg_wdata[13:12];

  assign gpio_mode_0_mode_7_we = addr_hit[2] & reg_we & !reg_error;
  assign gpio_mode_0_mode_7_wd = reg_wdata[15:14];

  assign gpio_mode_0_mode_8_we = addr_hit[2] & reg_we & !reg_error;
  assign gpio_mode_0_mode_8_wd = reg_wdata[17:16];

  assign gpio_mode_0_mode_9_we = addr_hit[2] & reg_we & !reg_error;
  assign gpio_mode_0_mode_9_wd = reg_wdata[19:18];

  assign gpio_mode_0_mode_10_we = addr_hit[2] & reg_we & !reg_error;
  assign gpio_mode_0_mode_10_wd = reg_wdata[21:20];

  assign gpio_mode_0_mode_11_we = addr_hit[2] & reg_we & !reg_error;
  assign gpio_mode_0_mode_11_wd = reg_wdata[23:22];

  assign gpio_mode_0_mode_12_we = addr_hit[2] & reg_we & !reg_error;
  assign gpio_mode_0_mode_12_wd = reg_wdata[25:24];

  assign gpio_mode_0_mode_13_we = addr_hit[2] & reg_we & !reg_error;
  assign gpio_mode_0_mode_13_wd = reg_wdata[27:26];

  assign gpio_mode_0_mode_14_we = addr_hit[2] & reg_we & !reg_error;
  assign gpio_mode_0_mode_14_wd = reg_wdata[29:28];

  assign gpio_mode_0_mode_15_we = addr_hit[2] & reg_we & !reg_error;
  assign gpio_mode_0_mode_15_wd = reg_wdata[31:30];

  assign gpio_mode_1_mode_16_we = addr_hit[3] & reg_we & !reg_error;
  assign gpio_mode_1_mode_16_wd = reg_wdata[1:0];

  assign gpio_mode_1_mode_17_we = addr_hit[3] & reg_we & !reg_error;
  assign gpio_mode_1_mode_17_wd = reg_wdata[3:2];

  assign gpio_mode_1_mode_18_we = addr_hit[3] & reg_we & !reg_error;
  assign gpio_mode_1_mode_18_wd = reg_wdata[5:4];

  assign gpio_mode_1_mode_19_we = addr_hit[3] & reg_we & !reg_error;
  assign gpio_mode_1_mode_19_wd = reg_wdata[7:6];

  assign gpio_mode_1_mode_20_we = addr_hit[3] & reg_we & !reg_error;
  assign gpio_mode_1_mode_20_wd = reg_wdata[9:8];

  assign gpio_mode_1_mode_21_we = addr_hit[3] & reg_we & !reg_error;
  assign gpio_mode_1_mode_21_wd = reg_wdata[11:10];

  assign gpio_mode_1_mode_22_we = addr_hit[3] & reg_we & !reg_error;
  assign gpio_mode_1_mode_22_wd = reg_wdata[13:12];

  assign gpio_mode_1_mode_23_we = addr_hit[3] & reg_we & !reg_error;
  assign gpio_mode_1_mode_23_wd = reg_wdata[15:14];

  assign gpio_mode_1_mode_24_we = addr_hit[3] & reg_we & !reg_error;
  assign gpio_mode_1_mode_24_wd = reg_wdata[17:16];

  assign gpio_mode_1_mode_25_we = addr_hit[3] & reg_we & !reg_error;
  assign gpio_mode_1_mode_25_wd = reg_wdata[19:18];

  assign gpio_mode_1_mode_26_we = addr_hit[3] & reg_we & !reg_error;
  assign gpio_mode_1_mode_26_wd = reg_wdata[21:20];

  assign gpio_mode_1_mode_27_we = addr_hit[3] & reg_we & !reg_error;
  assign gpio_mode_1_mode_27_wd = reg_wdata[23:22];

  assign gpio_mode_1_mode_28_we = addr_hit[3] & reg_we & !reg_error;
  assign gpio_mode_1_mode_28_wd = reg_wdata[25:24];

  assign gpio_mode_1_mode_29_we = addr_hit[3] & reg_we & !reg_error;
  assign gpio_mode_1_mode_29_wd = reg_wdata[27:26];

  assign gpio_mode_1_mode_30_we = addr_hit[3] & reg_we & !reg_error;
  assign gpio_mode_1_mode_30_wd = reg_wdata[29:28];

  assign gpio_mode_1_mode_31_we = addr_hit[3] & reg_we & !reg_error;
  assign gpio_mode_1_mode_31_wd = reg_wdata[31:30];

  assign gpio_en_gpio_en_0_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_0_wd = reg_wdata[0];

  assign gpio_en_gpio_en_1_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_1_wd = reg_wdata[1];

  assign gpio_en_gpio_en_2_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_2_wd = reg_wdata[2];

  assign gpio_en_gpio_en_3_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_3_wd = reg_wdata[3];

  assign gpio_en_gpio_en_4_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_4_wd = reg_wdata[4];

  assign gpio_en_gpio_en_5_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_5_wd = reg_wdata[5];

  assign gpio_en_gpio_en_6_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_6_wd = reg_wdata[6];

  assign gpio_en_gpio_en_7_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_7_wd = reg_wdata[7];

  assign gpio_en_gpio_en_8_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_8_wd = reg_wdata[8];

  assign gpio_en_gpio_en_9_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_9_wd = reg_wdata[9];

  assign gpio_en_gpio_en_10_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_10_wd = reg_wdata[10];

  assign gpio_en_gpio_en_11_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_11_wd = reg_wdata[11];

  assign gpio_en_gpio_en_12_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_12_wd = reg_wdata[12];

  assign gpio_en_gpio_en_13_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_13_wd = reg_wdata[13];

  assign gpio_en_gpio_en_14_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_14_wd = reg_wdata[14];

  assign gpio_en_gpio_en_15_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_15_wd = reg_wdata[15];

  assign gpio_en_gpio_en_16_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_16_wd = reg_wdata[16];

  assign gpio_en_gpio_en_17_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_17_wd = reg_wdata[17];

  assign gpio_en_gpio_en_18_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_18_wd = reg_wdata[18];

  assign gpio_en_gpio_en_19_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_19_wd = reg_wdata[19];

  assign gpio_en_gpio_en_20_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_20_wd = reg_wdata[20];

  assign gpio_en_gpio_en_21_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_21_wd = reg_wdata[21];

  assign gpio_en_gpio_en_22_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_22_wd = reg_wdata[22];

  assign gpio_en_gpio_en_23_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_23_wd = reg_wdata[23];

  assign gpio_en_gpio_en_24_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_24_wd = reg_wdata[24];

  assign gpio_en_gpio_en_25_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_25_wd = reg_wdata[25];

  assign gpio_en_gpio_en_26_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_26_wd = reg_wdata[26];

  assign gpio_en_gpio_en_27_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_27_wd = reg_wdata[27];

  assign gpio_en_gpio_en_28_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_28_wd = reg_wdata[28];

  assign gpio_en_gpio_en_29_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_29_wd = reg_wdata[29];

  assign gpio_en_gpio_en_30_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_30_wd = reg_wdata[30];

  assign gpio_en_gpio_en_31_we = addr_hit[4] & reg_we & !reg_error;
  assign gpio_en_gpio_en_31_wd = reg_wdata[31];

  assign gpio_in_gpio_in_0_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_1_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_2_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_3_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_4_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_5_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_6_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_7_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_8_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_9_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_10_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_11_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_12_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_13_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_14_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_15_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_16_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_17_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_18_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_19_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_20_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_21_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_22_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_23_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_24_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_25_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_26_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_27_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_28_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_29_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_30_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_in_gpio_in_31_re = addr_hit[5] & reg_re & !reg_error;

  assign gpio_out_gpio_out_0_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_0_wd = reg_wdata[0];

  assign gpio_out_gpio_out_1_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_1_wd = reg_wdata[1];

  assign gpio_out_gpio_out_2_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_2_wd = reg_wdata[2];

  assign gpio_out_gpio_out_3_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_3_wd = reg_wdata[3];

  assign gpio_out_gpio_out_4_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_4_wd = reg_wdata[4];

  assign gpio_out_gpio_out_5_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_5_wd = reg_wdata[5];

  assign gpio_out_gpio_out_6_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_6_wd = reg_wdata[6];

  assign gpio_out_gpio_out_7_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_7_wd = reg_wdata[7];

  assign gpio_out_gpio_out_8_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_8_wd = reg_wdata[8];

  assign gpio_out_gpio_out_9_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_9_wd = reg_wdata[9];

  assign gpio_out_gpio_out_10_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_10_wd = reg_wdata[10];

  assign gpio_out_gpio_out_11_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_11_wd = reg_wdata[11];

  assign gpio_out_gpio_out_12_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_12_wd = reg_wdata[12];

  assign gpio_out_gpio_out_13_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_13_wd = reg_wdata[13];

  assign gpio_out_gpio_out_14_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_14_wd = reg_wdata[14];

  assign gpio_out_gpio_out_15_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_15_wd = reg_wdata[15];

  assign gpio_out_gpio_out_16_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_16_wd = reg_wdata[16];

  assign gpio_out_gpio_out_17_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_17_wd = reg_wdata[17];

  assign gpio_out_gpio_out_18_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_18_wd = reg_wdata[18];

  assign gpio_out_gpio_out_19_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_19_wd = reg_wdata[19];

  assign gpio_out_gpio_out_20_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_20_wd = reg_wdata[20];

  assign gpio_out_gpio_out_21_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_21_wd = reg_wdata[21];

  assign gpio_out_gpio_out_22_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_22_wd = reg_wdata[22];

  assign gpio_out_gpio_out_23_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_23_wd = reg_wdata[23];

  assign gpio_out_gpio_out_24_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_24_wd = reg_wdata[24];

  assign gpio_out_gpio_out_25_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_25_wd = reg_wdata[25];

  assign gpio_out_gpio_out_26_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_26_wd = reg_wdata[26];

  assign gpio_out_gpio_out_27_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_27_wd = reg_wdata[27];

  assign gpio_out_gpio_out_28_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_28_wd = reg_wdata[28];

  assign gpio_out_gpio_out_29_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_29_wd = reg_wdata[29];

  assign gpio_out_gpio_out_30_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_30_wd = reg_wdata[30];

  assign gpio_out_gpio_out_31_we = addr_hit[6] & reg_we & !reg_error;
  assign gpio_out_gpio_out_31_wd = reg_wdata[31];

  assign gpio_set_gpio_set_0_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_0_wd = reg_wdata[0];

  assign gpio_set_gpio_set_1_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_1_wd = reg_wdata[1];

  assign gpio_set_gpio_set_2_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_2_wd = reg_wdata[2];

  assign gpio_set_gpio_set_3_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_3_wd = reg_wdata[3];

  assign gpio_set_gpio_set_4_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_4_wd = reg_wdata[4];

  assign gpio_set_gpio_set_5_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_5_wd = reg_wdata[5];

  assign gpio_set_gpio_set_6_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_6_wd = reg_wdata[6];

  assign gpio_set_gpio_set_7_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_7_wd = reg_wdata[7];

  assign gpio_set_gpio_set_8_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_8_wd = reg_wdata[8];

  assign gpio_set_gpio_set_9_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_9_wd = reg_wdata[9];

  assign gpio_set_gpio_set_10_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_10_wd = reg_wdata[10];

  assign gpio_set_gpio_set_11_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_11_wd = reg_wdata[11];

  assign gpio_set_gpio_set_12_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_12_wd = reg_wdata[12];

  assign gpio_set_gpio_set_13_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_13_wd = reg_wdata[13];

  assign gpio_set_gpio_set_14_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_14_wd = reg_wdata[14];

  assign gpio_set_gpio_set_15_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_15_wd = reg_wdata[15];

  assign gpio_set_gpio_set_16_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_16_wd = reg_wdata[16];

  assign gpio_set_gpio_set_17_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_17_wd = reg_wdata[17];

  assign gpio_set_gpio_set_18_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_18_wd = reg_wdata[18];

  assign gpio_set_gpio_set_19_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_19_wd = reg_wdata[19];

  assign gpio_set_gpio_set_20_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_20_wd = reg_wdata[20];

  assign gpio_set_gpio_set_21_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_21_wd = reg_wdata[21];

  assign gpio_set_gpio_set_22_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_22_wd = reg_wdata[22];

  assign gpio_set_gpio_set_23_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_23_wd = reg_wdata[23];

  assign gpio_set_gpio_set_24_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_24_wd = reg_wdata[24];

  assign gpio_set_gpio_set_25_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_25_wd = reg_wdata[25];

  assign gpio_set_gpio_set_26_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_26_wd = reg_wdata[26];

  assign gpio_set_gpio_set_27_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_27_wd = reg_wdata[27];

  assign gpio_set_gpio_set_28_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_28_wd = reg_wdata[28];

  assign gpio_set_gpio_set_29_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_29_wd = reg_wdata[29];

  assign gpio_set_gpio_set_30_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_30_wd = reg_wdata[30];

  assign gpio_set_gpio_set_31_we = addr_hit[7] & reg_we & !reg_error;
  assign gpio_set_gpio_set_31_wd = reg_wdata[31];

  assign gpio_clear_gpio_clear_0_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_0_wd = reg_wdata[0];

  assign gpio_clear_gpio_clear_1_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_1_wd = reg_wdata[1];

  assign gpio_clear_gpio_clear_2_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_2_wd = reg_wdata[2];

  assign gpio_clear_gpio_clear_3_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_3_wd = reg_wdata[3];

  assign gpio_clear_gpio_clear_4_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_4_wd = reg_wdata[4];

  assign gpio_clear_gpio_clear_5_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_5_wd = reg_wdata[5];

  assign gpio_clear_gpio_clear_6_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_6_wd = reg_wdata[6];

  assign gpio_clear_gpio_clear_7_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_7_wd = reg_wdata[7];

  assign gpio_clear_gpio_clear_8_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_8_wd = reg_wdata[8];

  assign gpio_clear_gpio_clear_9_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_9_wd = reg_wdata[9];

  assign gpio_clear_gpio_clear_10_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_10_wd = reg_wdata[10];

  assign gpio_clear_gpio_clear_11_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_11_wd = reg_wdata[11];

  assign gpio_clear_gpio_clear_12_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_12_wd = reg_wdata[12];

  assign gpio_clear_gpio_clear_13_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_13_wd = reg_wdata[13];

  assign gpio_clear_gpio_clear_14_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_14_wd = reg_wdata[14];

  assign gpio_clear_gpio_clear_15_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_15_wd = reg_wdata[15];

  assign gpio_clear_gpio_clear_16_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_16_wd = reg_wdata[16];

  assign gpio_clear_gpio_clear_17_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_17_wd = reg_wdata[17];

  assign gpio_clear_gpio_clear_18_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_18_wd = reg_wdata[18];

  assign gpio_clear_gpio_clear_19_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_19_wd = reg_wdata[19];

  assign gpio_clear_gpio_clear_20_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_20_wd = reg_wdata[20];

  assign gpio_clear_gpio_clear_21_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_21_wd = reg_wdata[21];

  assign gpio_clear_gpio_clear_22_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_22_wd = reg_wdata[22];

  assign gpio_clear_gpio_clear_23_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_23_wd = reg_wdata[23];

  assign gpio_clear_gpio_clear_24_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_24_wd = reg_wdata[24];

  assign gpio_clear_gpio_clear_25_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_25_wd = reg_wdata[25];

  assign gpio_clear_gpio_clear_26_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_26_wd = reg_wdata[26];

  assign gpio_clear_gpio_clear_27_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_27_wd = reg_wdata[27];

  assign gpio_clear_gpio_clear_28_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_28_wd = reg_wdata[28];

  assign gpio_clear_gpio_clear_29_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_29_wd = reg_wdata[29];

  assign gpio_clear_gpio_clear_30_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_30_wd = reg_wdata[30];

  assign gpio_clear_gpio_clear_31_we = addr_hit[8] & reg_we & !reg_error;
  assign gpio_clear_gpio_clear_31_wd = reg_wdata[31];

  assign gpio_toggle_gpio_toggle_0_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_0_wd = reg_wdata[0];

  assign gpio_toggle_gpio_toggle_1_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_1_wd = reg_wdata[1];

  assign gpio_toggle_gpio_toggle_2_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_2_wd = reg_wdata[2];

  assign gpio_toggle_gpio_toggle_3_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_3_wd = reg_wdata[3];

  assign gpio_toggle_gpio_toggle_4_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_4_wd = reg_wdata[4];

  assign gpio_toggle_gpio_toggle_5_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_5_wd = reg_wdata[5];

  assign gpio_toggle_gpio_toggle_6_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_6_wd = reg_wdata[6];

  assign gpio_toggle_gpio_toggle_7_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_7_wd = reg_wdata[7];

  assign gpio_toggle_gpio_toggle_8_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_8_wd = reg_wdata[8];

  assign gpio_toggle_gpio_toggle_9_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_9_wd = reg_wdata[9];

  assign gpio_toggle_gpio_toggle_10_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_10_wd = reg_wdata[10];

  assign gpio_toggle_gpio_toggle_11_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_11_wd = reg_wdata[11];

  assign gpio_toggle_gpio_toggle_12_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_12_wd = reg_wdata[12];

  assign gpio_toggle_gpio_toggle_13_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_13_wd = reg_wdata[13];

  assign gpio_toggle_gpio_toggle_14_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_14_wd = reg_wdata[14];

  assign gpio_toggle_gpio_toggle_15_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_15_wd = reg_wdata[15];

  assign gpio_toggle_gpio_toggle_16_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_16_wd = reg_wdata[16];

  assign gpio_toggle_gpio_toggle_17_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_17_wd = reg_wdata[17];

  assign gpio_toggle_gpio_toggle_18_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_18_wd = reg_wdata[18];

  assign gpio_toggle_gpio_toggle_19_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_19_wd = reg_wdata[19];

  assign gpio_toggle_gpio_toggle_20_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_20_wd = reg_wdata[20];

  assign gpio_toggle_gpio_toggle_21_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_21_wd = reg_wdata[21];

  assign gpio_toggle_gpio_toggle_22_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_22_wd = reg_wdata[22];

  assign gpio_toggle_gpio_toggle_23_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_23_wd = reg_wdata[23];

  assign gpio_toggle_gpio_toggle_24_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_24_wd = reg_wdata[24];

  assign gpio_toggle_gpio_toggle_25_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_25_wd = reg_wdata[25];

  assign gpio_toggle_gpio_toggle_26_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_26_wd = reg_wdata[26];

  assign gpio_toggle_gpio_toggle_27_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_27_wd = reg_wdata[27];

  assign gpio_toggle_gpio_toggle_28_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_28_wd = reg_wdata[28];

  assign gpio_toggle_gpio_toggle_29_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_29_wd = reg_wdata[29];

  assign gpio_toggle_gpio_toggle_30_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_30_wd = reg_wdata[30];

  assign gpio_toggle_gpio_toggle_31_we = addr_hit[9] & reg_we & !reg_error;
  assign gpio_toggle_gpio_toggle_31_wd = reg_wdata[31];

  assign intrpt_rise_en_intrpt_rise_en_0_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_0_wd = reg_wdata[0];

  assign intrpt_rise_en_intrpt_rise_en_1_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_1_wd = reg_wdata[1];

  assign intrpt_rise_en_intrpt_rise_en_2_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_2_wd = reg_wdata[2];

  assign intrpt_rise_en_intrpt_rise_en_3_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_3_wd = reg_wdata[3];

  assign intrpt_rise_en_intrpt_rise_en_4_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_4_wd = reg_wdata[4];

  assign intrpt_rise_en_intrpt_rise_en_5_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_5_wd = reg_wdata[5];

  assign intrpt_rise_en_intrpt_rise_en_6_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_6_wd = reg_wdata[6];

  assign intrpt_rise_en_intrpt_rise_en_7_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_7_wd = reg_wdata[7];

  assign intrpt_rise_en_intrpt_rise_en_8_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_8_wd = reg_wdata[8];

  assign intrpt_rise_en_intrpt_rise_en_9_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_9_wd = reg_wdata[9];

  assign intrpt_rise_en_intrpt_rise_en_10_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_10_wd = reg_wdata[10];

  assign intrpt_rise_en_intrpt_rise_en_11_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_11_wd = reg_wdata[11];

  assign intrpt_rise_en_intrpt_rise_en_12_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_12_wd = reg_wdata[12];

  assign intrpt_rise_en_intrpt_rise_en_13_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_13_wd = reg_wdata[13];

  assign intrpt_rise_en_intrpt_rise_en_14_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_14_wd = reg_wdata[14];

  assign intrpt_rise_en_intrpt_rise_en_15_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_15_wd = reg_wdata[15];

  assign intrpt_rise_en_intrpt_rise_en_16_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_16_wd = reg_wdata[16];

  assign intrpt_rise_en_intrpt_rise_en_17_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_17_wd = reg_wdata[17];

  assign intrpt_rise_en_intrpt_rise_en_18_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_18_wd = reg_wdata[18];

  assign intrpt_rise_en_intrpt_rise_en_19_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_19_wd = reg_wdata[19];

  assign intrpt_rise_en_intrpt_rise_en_20_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_20_wd = reg_wdata[20];

  assign intrpt_rise_en_intrpt_rise_en_21_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_21_wd = reg_wdata[21];

  assign intrpt_rise_en_intrpt_rise_en_22_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_22_wd = reg_wdata[22];

  assign intrpt_rise_en_intrpt_rise_en_23_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_23_wd = reg_wdata[23];

  assign intrpt_rise_en_intrpt_rise_en_24_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_24_wd = reg_wdata[24];

  assign intrpt_rise_en_intrpt_rise_en_25_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_25_wd = reg_wdata[25];

  assign intrpt_rise_en_intrpt_rise_en_26_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_26_wd = reg_wdata[26];

  assign intrpt_rise_en_intrpt_rise_en_27_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_27_wd = reg_wdata[27];

  assign intrpt_rise_en_intrpt_rise_en_28_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_28_wd = reg_wdata[28];

  assign intrpt_rise_en_intrpt_rise_en_29_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_29_wd = reg_wdata[29];

  assign intrpt_rise_en_intrpt_rise_en_30_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_30_wd = reg_wdata[30];

  assign intrpt_rise_en_intrpt_rise_en_31_we = addr_hit[10] & reg_we & !reg_error;
  assign intrpt_rise_en_intrpt_rise_en_31_wd = reg_wdata[31];

  assign intrpt_fall_en_intrpt_fall_en_0_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_0_wd = reg_wdata[0];

  assign intrpt_fall_en_intrpt_fall_en_1_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_1_wd = reg_wdata[1];

  assign intrpt_fall_en_intrpt_fall_en_2_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_2_wd = reg_wdata[2];

  assign intrpt_fall_en_intrpt_fall_en_3_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_3_wd = reg_wdata[3];

  assign intrpt_fall_en_intrpt_fall_en_4_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_4_wd = reg_wdata[4];

  assign intrpt_fall_en_intrpt_fall_en_5_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_5_wd = reg_wdata[5];

  assign intrpt_fall_en_intrpt_fall_en_6_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_6_wd = reg_wdata[6];

  assign intrpt_fall_en_intrpt_fall_en_7_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_7_wd = reg_wdata[7];

  assign intrpt_fall_en_intrpt_fall_en_8_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_8_wd = reg_wdata[8];

  assign intrpt_fall_en_intrpt_fall_en_9_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_9_wd = reg_wdata[9];

  assign intrpt_fall_en_intrpt_fall_en_10_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_10_wd = reg_wdata[10];

  assign intrpt_fall_en_intrpt_fall_en_11_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_11_wd = reg_wdata[11];

  assign intrpt_fall_en_intrpt_fall_en_12_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_12_wd = reg_wdata[12];

  assign intrpt_fall_en_intrpt_fall_en_13_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_13_wd = reg_wdata[13];

  assign intrpt_fall_en_intrpt_fall_en_14_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_14_wd = reg_wdata[14];

  assign intrpt_fall_en_intrpt_fall_en_15_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_15_wd = reg_wdata[15];

  assign intrpt_fall_en_intrpt_fall_en_16_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_16_wd = reg_wdata[16];

  assign intrpt_fall_en_intrpt_fall_en_17_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_17_wd = reg_wdata[17];

  assign intrpt_fall_en_intrpt_fall_en_18_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_18_wd = reg_wdata[18];

  assign intrpt_fall_en_intrpt_fall_en_19_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_19_wd = reg_wdata[19];

  assign intrpt_fall_en_intrpt_fall_en_20_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_20_wd = reg_wdata[20];

  assign intrpt_fall_en_intrpt_fall_en_21_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_21_wd = reg_wdata[21];

  assign intrpt_fall_en_intrpt_fall_en_22_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_22_wd = reg_wdata[22];

  assign intrpt_fall_en_intrpt_fall_en_23_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_23_wd = reg_wdata[23];

  assign intrpt_fall_en_intrpt_fall_en_24_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_24_wd = reg_wdata[24];

  assign intrpt_fall_en_intrpt_fall_en_25_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_25_wd = reg_wdata[25];

  assign intrpt_fall_en_intrpt_fall_en_26_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_26_wd = reg_wdata[26];

  assign intrpt_fall_en_intrpt_fall_en_27_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_27_wd = reg_wdata[27];

  assign intrpt_fall_en_intrpt_fall_en_28_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_28_wd = reg_wdata[28];

  assign intrpt_fall_en_intrpt_fall_en_29_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_29_wd = reg_wdata[29];

  assign intrpt_fall_en_intrpt_fall_en_30_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_30_wd = reg_wdata[30];

  assign intrpt_fall_en_intrpt_fall_en_31_we = addr_hit[11] & reg_we & !reg_error;
  assign intrpt_fall_en_intrpt_fall_en_31_wd = reg_wdata[31];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_0_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_0_wd = reg_wdata[0];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_1_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_1_wd = reg_wdata[1];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_2_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_2_wd = reg_wdata[2];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_3_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_3_wd = reg_wdata[3];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_4_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_4_wd = reg_wdata[4];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_5_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_5_wd = reg_wdata[5];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_6_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_6_wd = reg_wdata[6];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_7_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_7_wd = reg_wdata[7];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_8_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_8_wd = reg_wdata[8];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_9_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_9_wd = reg_wdata[9];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_10_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_10_wd = reg_wdata[10];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_11_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_11_wd = reg_wdata[11];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_12_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_12_wd = reg_wdata[12];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_13_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_13_wd = reg_wdata[13];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_14_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_14_wd = reg_wdata[14];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_15_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_15_wd = reg_wdata[15];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_16_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_16_wd = reg_wdata[16];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_17_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_17_wd = reg_wdata[17];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_18_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_18_wd = reg_wdata[18];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_19_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_19_wd = reg_wdata[19];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_20_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_20_wd = reg_wdata[20];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_21_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_21_wd = reg_wdata[21];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_22_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_22_wd = reg_wdata[22];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_23_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_23_wd = reg_wdata[23];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_24_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_24_wd = reg_wdata[24];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_25_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_25_wd = reg_wdata[25];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_26_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_26_wd = reg_wdata[26];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_27_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_27_wd = reg_wdata[27];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_28_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_28_wd = reg_wdata[28];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_29_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_29_wd = reg_wdata[29];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_30_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_30_wd = reg_wdata[30];

  assign intrpt_lvl_high_en_intrpt_lvl_high_en_31_we = addr_hit[12] & reg_we & !reg_error;
  assign intrpt_lvl_high_en_intrpt_lvl_high_en_31_wd = reg_wdata[31];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_0_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_0_wd = reg_wdata[0];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_1_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_1_wd = reg_wdata[1];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_2_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_2_wd = reg_wdata[2];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_3_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_3_wd = reg_wdata[3];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_4_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_4_wd = reg_wdata[4];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_5_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_5_wd = reg_wdata[5];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_6_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_6_wd = reg_wdata[6];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_7_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_7_wd = reg_wdata[7];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_8_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_8_wd = reg_wdata[8];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_9_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_9_wd = reg_wdata[9];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_10_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_10_wd = reg_wdata[10];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_11_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_11_wd = reg_wdata[11];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_12_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_12_wd = reg_wdata[12];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_13_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_13_wd = reg_wdata[13];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_14_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_14_wd = reg_wdata[14];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_15_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_15_wd = reg_wdata[15];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_16_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_16_wd = reg_wdata[16];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_17_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_17_wd = reg_wdata[17];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_18_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_18_wd = reg_wdata[18];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_19_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_19_wd = reg_wdata[19];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_20_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_20_wd = reg_wdata[20];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_21_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_21_wd = reg_wdata[21];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_22_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_22_wd = reg_wdata[22];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_23_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_23_wd = reg_wdata[23];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_24_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_24_wd = reg_wdata[24];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_25_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_25_wd = reg_wdata[25];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_26_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_26_wd = reg_wdata[26];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_27_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_27_wd = reg_wdata[27];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_28_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_28_wd = reg_wdata[28];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_29_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_29_wd = reg_wdata[29];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_30_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_30_wd = reg_wdata[30];

  assign intrpt_lvl_low_en_intrpt_lvl_low_en_31_we = addr_hit[13] & reg_we & !reg_error;
  assign intrpt_lvl_low_en_intrpt_lvl_low_en_31_wd = reg_wdata[31];

  assign intrpt_status_intrpt_status_0_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_0_wd = reg_wdata[0];
  assign intrpt_status_intrpt_status_0_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_1_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_1_wd = reg_wdata[1];
  assign intrpt_status_intrpt_status_1_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_2_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_2_wd = reg_wdata[2];
  assign intrpt_status_intrpt_status_2_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_3_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_3_wd = reg_wdata[3];
  assign intrpt_status_intrpt_status_3_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_4_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_4_wd = reg_wdata[4];
  assign intrpt_status_intrpt_status_4_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_5_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_5_wd = reg_wdata[5];
  assign intrpt_status_intrpt_status_5_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_6_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_6_wd = reg_wdata[6];
  assign intrpt_status_intrpt_status_6_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_7_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_7_wd = reg_wdata[7];
  assign intrpt_status_intrpt_status_7_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_8_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_8_wd = reg_wdata[8];
  assign intrpt_status_intrpt_status_8_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_9_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_9_wd = reg_wdata[9];
  assign intrpt_status_intrpt_status_9_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_10_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_10_wd = reg_wdata[10];
  assign intrpt_status_intrpt_status_10_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_11_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_11_wd = reg_wdata[11];
  assign intrpt_status_intrpt_status_11_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_12_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_12_wd = reg_wdata[12];
  assign intrpt_status_intrpt_status_12_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_13_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_13_wd = reg_wdata[13];
  assign intrpt_status_intrpt_status_13_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_14_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_14_wd = reg_wdata[14];
  assign intrpt_status_intrpt_status_14_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_15_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_15_wd = reg_wdata[15];
  assign intrpt_status_intrpt_status_15_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_16_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_16_wd = reg_wdata[16];
  assign intrpt_status_intrpt_status_16_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_17_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_17_wd = reg_wdata[17];
  assign intrpt_status_intrpt_status_17_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_18_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_18_wd = reg_wdata[18];
  assign intrpt_status_intrpt_status_18_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_19_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_19_wd = reg_wdata[19];
  assign intrpt_status_intrpt_status_19_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_20_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_20_wd = reg_wdata[20];
  assign intrpt_status_intrpt_status_20_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_21_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_21_wd = reg_wdata[21];
  assign intrpt_status_intrpt_status_21_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_22_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_22_wd = reg_wdata[22];
  assign intrpt_status_intrpt_status_22_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_23_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_23_wd = reg_wdata[23];
  assign intrpt_status_intrpt_status_23_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_24_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_24_wd = reg_wdata[24];
  assign intrpt_status_intrpt_status_24_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_25_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_25_wd = reg_wdata[25];
  assign intrpt_status_intrpt_status_25_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_26_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_26_wd = reg_wdata[26];
  assign intrpt_status_intrpt_status_26_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_27_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_27_wd = reg_wdata[27];
  assign intrpt_status_intrpt_status_27_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_28_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_28_wd = reg_wdata[28];
  assign intrpt_status_intrpt_status_28_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_29_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_29_wd = reg_wdata[29];
  assign intrpt_status_intrpt_status_29_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_30_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_30_wd = reg_wdata[30];
  assign intrpt_status_intrpt_status_30_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_status_intrpt_status_31_we = addr_hit[14] & reg_we & !reg_error;
  assign intrpt_status_intrpt_status_31_wd = reg_wdata[31];
  assign intrpt_status_intrpt_status_31_re = addr_hit[14] & reg_re & !reg_error;

  assign intrpt_rise_status_intrpt_rise_status_0_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_0_wd = reg_wdata[0];

  assign intrpt_rise_status_intrpt_rise_status_1_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_1_wd = reg_wdata[1];

  assign intrpt_rise_status_intrpt_rise_status_2_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_2_wd = reg_wdata[2];

  assign intrpt_rise_status_intrpt_rise_status_3_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_3_wd = reg_wdata[3];

  assign intrpt_rise_status_intrpt_rise_status_4_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_4_wd = reg_wdata[4];

  assign intrpt_rise_status_intrpt_rise_status_5_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_5_wd = reg_wdata[5];

  assign intrpt_rise_status_intrpt_rise_status_6_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_6_wd = reg_wdata[6];

  assign intrpt_rise_status_intrpt_rise_status_7_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_7_wd = reg_wdata[7];

  assign intrpt_rise_status_intrpt_rise_status_8_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_8_wd = reg_wdata[8];

  assign intrpt_rise_status_intrpt_rise_status_9_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_9_wd = reg_wdata[9];

  assign intrpt_rise_status_intrpt_rise_status_10_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_10_wd = reg_wdata[10];

  assign intrpt_rise_status_intrpt_rise_status_11_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_11_wd = reg_wdata[11];

  assign intrpt_rise_status_intrpt_rise_status_12_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_12_wd = reg_wdata[12];

  assign intrpt_rise_status_intrpt_rise_status_13_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_13_wd = reg_wdata[13];

  assign intrpt_rise_status_intrpt_rise_status_14_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_14_wd = reg_wdata[14];

  assign intrpt_rise_status_intrpt_rise_status_15_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_15_wd = reg_wdata[15];

  assign intrpt_rise_status_intrpt_rise_status_16_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_16_wd = reg_wdata[16];

  assign intrpt_rise_status_intrpt_rise_status_17_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_17_wd = reg_wdata[17];

  assign intrpt_rise_status_intrpt_rise_status_18_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_18_wd = reg_wdata[18];

  assign intrpt_rise_status_intrpt_rise_status_19_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_19_wd = reg_wdata[19];

  assign intrpt_rise_status_intrpt_rise_status_20_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_20_wd = reg_wdata[20];

  assign intrpt_rise_status_intrpt_rise_status_21_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_21_wd = reg_wdata[21];

  assign intrpt_rise_status_intrpt_rise_status_22_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_22_wd = reg_wdata[22];

  assign intrpt_rise_status_intrpt_rise_status_23_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_23_wd = reg_wdata[23];

  assign intrpt_rise_status_intrpt_rise_status_24_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_24_wd = reg_wdata[24];

  assign intrpt_rise_status_intrpt_rise_status_25_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_25_wd = reg_wdata[25];

  assign intrpt_rise_status_intrpt_rise_status_26_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_26_wd = reg_wdata[26];

  assign intrpt_rise_status_intrpt_rise_status_27_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_27_wd = reg_wdata[27];

  assign intrpt_rise_status_intrpt_rise_status_28_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_28_wd = reg_wdata[28];

  assign intrpt_rise_status_intrpt_rise_status_29_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_29_wd = reg_wdata[29];

  assign intrpt_rise_status_intrpt_rise_status_30_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_30_wd = reg_wdata[30];

  assign intrpt_rise_status_intrpt_rise_status_31_we = addr_hit[15] & reg_we & !reg_error;
  assign intrpt_rise_status_intrpt_rise_status_31_wd = reg_wdata[31];

  assign intrpt_fall_status_intrpt_fall_status_0_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_0_wd = reg_wdata[0];

  assign intrpt_fall_status_intrpt_fall_status_1_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_1_wd = reg_wdata[1];

  assign intrpt_fall_status_intrpt_fall_status_2_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_2_wd = reg_wdata[2];

  assign intrpt_fall_status_intrpt_fall_status_3_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_3_wd = reg_wdata[3];

  assign intrpt_fall_status_intrpt_fall_status_4_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_4_wd = reg_wdata[4];

  assign intrpt_fall_status_intrpt_fall_status_5_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_5_wd = reg_wdata[5];

  assign intrpt_fall_status_intrpt_fall_status_6_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_6_wd = reg_wdata[6];

  assign intrpt_fall_status_intrpt_fall_status_7_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_7_wd = reg_wdata[7];

  assign intrpt_fall_status_intrpt_fall_status_8_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_8_wd = reg_wdata[8];

  assign intrpt_fall_status_intrpt_fall_status_9_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_9_wd = reg_wdata[9];

  assign intrpt_fall_status_intrpt_fall_status_10_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_10_wd = reg_wdata[10];

  assign intrpt_fall_status_intrpt_fall_status_11_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_11_wd = reg_wdata[11];

  assign intrpt_fall_status_intrpt_fall_status_12_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_12_wd = reg_wdata[12];

  assign intrpt_fall_status_intrpt_fall_status_13_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_13_wd = reg_wdata[13];

  assign intrpt_fall_status_intrpt_fall_status_14_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_14_wd = reg_wdata[14];

  assign intrpt_fall_status_intrpt_fall_status_15_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_15_wd = reg_wdata[15];

  assign intrpt_fall_status_intrpt_fall_status_16_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_16_wd = reg_wdata[16];

  assign intrpt_fall_status_intrpt_fall_status_17_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_17_wd = reg_wdata[17];

  assign intrpt_fall_status_intrpt_fall_status_18_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_18_wd = reg_wdata[18];

  assign intrpt_fall_status_intrpt_fall_status_19_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_19_wd = reg_wdata[19];

  assign intrpt_fall_status_intrpt_fall_status_20_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_20_wd = reg_wdata[20];

  assign intrpt_fall_status_intrpt_fall_status_21_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_21_wd = reg_wdata[21];

  assign intrpt_fall_status_intrpt_fall_status_22_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_22_wd = reg_wdata[22];

  assign intrpt_fall_status_intrpt_fall_status_23_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_23_wd = reg_wdata[23];

  assign intrpt_fall_status_intrpt_fall_status_24_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_24_wd = reg_wdata[24];

  assign intrpt_fall_status_intrpt_fall_status_25_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_25_wd = reg_wdata[25];

  assign intrpt_fall_status_intrpt_fall_status_26_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_26_wd = reg_wdata[26];

  assign intrpt_fall_status_intrpt_fall_status_27_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_27_wd = reg_wdata[27];

  assign intrpt_fall_status_intrpt_fall_status_28_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_28_wd = reg_wdata[28];

  assign intrpt_fall_status_intrpt_fall_status_29_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_29_wd = reg_wdata[29];

  assign intrpt_fall_status_intrpt_fall_status_30_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_30_wd = reg_wdata[30];

  assign intrpt_fall_status_intrpt_fall_status_31_we = addr_hit[16] & reg_we & !reg_error;
  assign intrpt_fall_status_intrpt_fall_status_31_wd = reg_wdata[31];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_0_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_0_wd = reg_wdata[0];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_1_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_1_wd = reg_wdata[1];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_2_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_2_wd = reg_wdata[2];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_3_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_3_wd = reg_wdata[3];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_4_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_4_wd = reg_wdata[4];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_5_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_5_wd = reg_wdata[5];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_6_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_6_wd = reg_wdata[6];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_7_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_7_wd = reg_wdata[7];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_8_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_8_wd = reg_wdata[8];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_9_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_9_wd = reg_wdata[9];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_10_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_10_wd = reg_wdata[10];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_11_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_11_wd = reg_wdata[11];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_12_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_12_wd = reg_wdata[12];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_13_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_13_wd = reg_wdata[13];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_14_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_14_wd = reg_wdata[14];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_15_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_15_wd = reg_wdata[15];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_16_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_16_wd = reg_wdata[16];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_17_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_17_wd = reg_wdata[17];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_18_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_18_wd = reg_wdata[18];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_19_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_19_wd = reg_wdata[19];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_20_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_20_wd = reg_wdata[20];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_21_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_21_wd = reg_wdata[21];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_22_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_22_wd = reg_wdata[22];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_23_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_23_wd = reg_wdata[23];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_24_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_24_wd = reg_wdata[24];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_25_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_25_wd = reg_wdata[25];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_26_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_26_wd = reg_wdata[26];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_27_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_27_wd = reg_wdata[27];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_28_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_28_wd = reg_wdata[28];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_29_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_29_wd = reg_wdata[29];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_30_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_30_wd = reg_wdata[30];

  assign intrpt_lvl_high_status_intrpt_lvl_high_status_31_we = addr_hit[17] & reg_we & !reg_error;
  assign intrpt_lvl_high_status_intrpt_lvl_high_status_31_wd = reg_wdata[31];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_0_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_0_wd = reg_wdata[0];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_1_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_1_wd = reg_wdata[1];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_2_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_2_wd = reg_wdata[2];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_3_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_3_wd = reg_wdata[3];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_4_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_4_wd = reg_wdata[4];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_5_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_5_wd = reg_wdata[5];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_6_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_6_wd = reg_wdata[6];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_7_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_7_wd = reg_wdata[7];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_8_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_8_wd = reg_wdata[8];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_9_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_9_wd = reg_wdata[9];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_10_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_10_wd = reg_wdata[10];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_11_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_11_wd = reg_wdata[11];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_12_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_12_wd = reg_wdata[12];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_13_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_13_wd = reg_wdata[13];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_14_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_14_wd = reg_wdata[14];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_15_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_15_wd = reg_wdata[15];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_16_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_16_wd = reg_wdata[16];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_17_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_17_wd = reg_wdata[17];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_18_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_18_wd = reg_wdata[18];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_19_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_19_wd = reg_wdata[19];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_20_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_20_wd = reg_wdata[20];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_21_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_21_wd = reg_wdata[21];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_22_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_22_wd = reg_wdata[22];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_23_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_23_wd = reg_wdata[23];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_24_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_24_wd = reg_wdata[24];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_25_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_25_wd = reg_wdata[25];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_26_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_26_wd = reg_wdata[26];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_27_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_27_wd = reg_wdata[27];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_28_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_28_wd = reg_wdata[28];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_29_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_29_wd = reg_wdata[29];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_30_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_30_wd = reg_wdata[30];

  assign intrpt_lvl_low_status_intrpt_lvl_low_status_31_we = addr_hit[18] & reg_we & !reg_error;
  assign intrpt_lvl_low_status_intrpt_lvl_low_status_31_wd = reg_wdata[31];

  // Read data return
  always_comb begin
    reg_rdata_next = '0;
    unique case (1'b1)
      addr_hit[0]: begin
        reg_rdata_next[9:0] = info_gpio_cnt_qs;
        reg_rdata_next[19:10] = info_version_qs;
      end

      addr_hit[1]: begin
        reg_rdata_next[0] = cfg_glbl_intrpt_mode_qs;
        reg_rdata_next[1] = cfg_pin_lvl_intrpt_mode_qs;
      end

      addr_hit[2]: begin
        reg_rdata_next[1:0] = gpio_mode_0_mode_0_qs;
        reg_rdata_next[3:2] = gpio_mode_0_mode_1_qs;
        reg_rdata_next[5:4] = gpio_mode_0_mode_2_qs;
        reg_rdata_next[7:6] = gpio_mode_0_mode_3_qs;
        reg_rdata_next[9:8] = gpio_mode_0_mode_4_qs;
        reg_rdata_next[11:10] = gpio_mode_0_mode_5_qs;
        reg_rdata_next[13:12] = gpio_mode_0_mode_6_qs;
        reg_rdata_next[15:14] = gpio_mode_0_mode_7_qs;
        reg_rdata_next[17:16] = gpio_mode_0_mode_8_qs;
        reg_rdata_next[19:18] = gpio_mode_0_mode_9_qs;
        reg_rdata_next[21:20] = gpio_mode_0_mode_10_qs;
        reg_rdata_next[23:22] = gpio_mode_0_mode_11_qs;
        reg_rdata_next[25:24] = gpio_mode_0_mode_12_qs;
        reg_rdata_next[27:26] = gpio_mode_0_mode_13_qs;
        reg_rdata_next[29:28] = gpio_mode_0_mode_14_qs;
        reg_rdata_next[31:30] = gpio_mode_0_mode_15_qs;
      end

      addr_hit[3]: begin
        reg_rdata_next[1:0] = gpio_mode_1_mode_16_qs;
        reg_rdata_next[3:2] = gpio_mode_1_mode_17_qs;
        reg_rdata_next[5:4] = gpio_mode_1_mode_18_qs;
        reg_rdata_next[7:6] = gpio_mode_1_mode_19_qs;
        reg_rdata_next[9:8] = gpio_mode_1_mode_20_qs;
        reg_rdata_next[11:10] = gpio_mode_1_mode_21_qs;
        reg_rdata_next[13:12] = gpio_mode_1_mode_22_qs;
        reg_rdata_next[15:14] = gpio_mode_1_mode_23_qs;
        reg_rdata_next[17:16] = gpio_mode_1_mode_24_qs;
        reg_rdata_next[19:18] = gpio_mode_1_mode_25_qs;
        reg_rdata_next[21:20] = gpio_mode_1_mode_26_qs;
        reg_rdata_next[23:22] = gpio_mode_1_mode_27_qs;
        reg_rdata_next[25:24] = gpio_mode_1_mode_28_qs;
        reg_rdata_next[27:26] = gpio_mode_1_mode_29_qs;
        reg_rdata_next[29:28] = gpio_mode_1_mode_30_qs;
        reg_rdata_next[31:30] = gpio_mode_1_mode_31_qs;
      end

      addr_hit[4]: begin
        reg_rdata_next[0] = gpio_en_gpio_en_0_qs;
        reg_rdata_next[1] = gpio_en_gpio_en_1_qs;
        reg_rdata_next[2] = gpio_en_gpio_en_2_qs;
        reg_rdata_next[3] = gpio_en_gpio_en_3_qs;
        reg_rdata_next[4] = gpio_en_gpio_en_4_qs;
        reg_rdata_next[5] = gpio_en_gpio_en_5_qs;
        reg_rdata_next[6] = gpio_en_gpio_en_6_qs;
        reg_rdata_next[7] = gpio_en_gpio_en_7_qs;
        reg_rdata_next[8] = gpio_en_gpio_en_8_qs;
        reg_rdata_next[9] = gpio_en_gpio_en_9_qs;
        reg_rdata_next[10] = gpio_en_gpio_en_10_qs;
        reg_rdata_next[11] = gpio_en_gpio_en_11_qs;
        reg_rdata_next[12] = gpio_en_gpio_en_12_qs;
        reg_rdata_next[13] = gpio_en_gpio_en_13_qs;
        reg_rdata_next[14] = gpio_en_gpio_en_14_qs;
        reg_rdata_next[15] = gpio_en_gpio_en_15_qs;
        reg_rdata_next[16] = gpio_en_gpio_en_16_qs;
        reg_rdata_next[17] = gpio_en_gpio_en_17_qs;
        reg_rdata_next[18] = gpio_en_gpio_en_18_qs;
        reg_rdata_next[19] = gpio_en_gpio_en_19_qs;
        reg_rdata_next[20] = gpio_en_gpio_en_20_qs;
        reg_rdata_next[21] = gpio_en_gpio_en_21_qs;
        reg_rdata_next[22] = gpio_en_gpio_en_22_qs;
        reg_rdata_next[23] = gpio_en_gpio_en_23_qs;
        reg_rdata_next[24] = gpio_en_gpio_en_24_qs;
        reg_rdata_next[25] = gpio_en_gpio_en_25_qs;
        reg_rdata_next[26] = gpio_en_gpio_en_26_qs;
        reg_rdata_next[27] = gpio_en_gpio_en_27_qs;
        reg_rdata_next[28] = gpio_en_gpio_en_28_qs;
        reg_rdata_next[29] = gpio_en_gpio_en_29_qs;
        reg_rdata_next[30] = gpio_en_gpio_en_30_qs;
        reg_rdata_next[31] = gpio_en_gpio_en_31_qs;
      end

      addr_hit[5]: begin
        reg_rdata_next[0] = gpio_in_gpio_in_0_qs;
        reg_rdata_next[1] = gpio_in_gpio_in_1_qs;
        reg_rdata_next[2] = gpio_in_gpio_in_2_qs;
        reg_rdata_next[3] = gpio_in_gpio_in_3_qs;
        reg_rdata_next[4] = gpio_in_gpio_in_4_qs;
        reg_rdata_next[5] = gpio_in_gpio_in_5_qs;
        reg_rdata_next[6] = gpio_in_gpio_in_6_qs;
        reg_rdata_next[7] = gpio_in_gpio_in_7_qs;
        reg_rdata_next[8] = gpio_in_gpio_in_8_qs;
        reg_rdata_next[9] = gpio_in_gpio_in_9_qs;
        reg_rdata_next[10] = gpio_in_gpio_in_10_qs;
        reg_rdata_next[11] = gpio_in_gpio_in_11_qs;
        reg_rdata_next[12] = gpio_in_gpio_in_12_qs;
        reg_rdata_next[13] = gpio_in_gpio_in_13_qs;
        reg_rdata_next[14] = gpio_in_gpio_in_14_qs;
        reg_rdata_next[15] = gpio_in_gpio_in_15_qs;
        reg_rdata_next[16] = gpio_in_gpio_in_16_qs;
        reg_rdata_next[17] = gpio_in_gpio_in_17_qs;
        reg_rdata_next[18] = gpio_in_gpio_in_18_qs;
        reg_rdata_next[19] = gpio_in_gpio_in_19_qs;
        reg_rdata_next[20] = gpio_in_gpio_in_20_qs;
        reg_rdata_next[21] = gpio_in_gpio_in_21_qs;
        reg_rdata_next[22] = gpio_in_gpio_in_22_qs;
        reg_rdata_next[23] = gpio_in_gpio_in_23_qs;
        reg_rdata_next[24] = gpio_in_gpio_in_24_qs;
        reg_rdata_next[25] = gpio_in_gpio_in_25_qs;
        reg_rdata_next[26] = gpio_in_gpio_in_26_qs;
        reg_rdata_next[27] = gpio_in_gpio_in_27_qs;
        reg_rdata_next[28] = gpio_in_gpio_in_28_qs;
        reg_rdata_next[29] = gpio_in_gpio_in_29_qs;
        reg_rdata_next[30] = gpio_in_gpio_in_30_qs;
        reg_rdata_next[31] = gpio_in_gpio_in_31_qs;
      end

      addr_hit[6]: begin
        reg_rdata_next[0] = gpio_out_gpio_out_0_qs;
        reg_rdata_next[1] = gpio_out_gpio_out_1_qs;
        reg_rdata_next[2] = gpio_out_gpio_out_2_qs;
        reg_rdata_next[3] = gpio_out_gpio_out_3_qs;
        reg_rdata_next[4] = gpio_out_gpio_out_4_qs;
        reg_rdata_next[5] = gpio_out_gpio_out_5_qs;
        reg_rdata_next[6] = gpio_out_gpio_out_6_qs;
        reg_rdata_next[7] = gpio_out_gpio_out_7_qs;
        reg_rdata_next[8] = gpio_out_gpio_out_8_qs;
        reg_rdata_next[9] = gpio_out_gpio_out_9_qs;
        reg_rdata_next[10] = gpio_out_gpio_out_10_qs;
        reg_rdata_next[11] = gpio_out_gpio_out_11_qs;
        reg_rdata_next[12] = gpio_out_gpio_out_12_qs;
        reg_rdata_next[13] = gpio_out_gpio_out_13_qs;
        reg_rdata_next[14] = gpio_out_gpio_out_14_qs;
        reg_rdata_next[15] = gpio_out_gpio_out_15_qs;
        reg_rdata_next[16] = gpio_out_gpio_out_16_qs;
        reg_rdata_next[17] = gpio_out_gpio_out_17_qs;
        reg_rdata_next[18] = gpio_out_gpio_out_18_qs;
        reg_rdata_next[19] = gpio_out_gpio_out_19_qs;
        reg_rdata_next[20] = gpio_out_gpio_out_20_qs;
        reg_rdata_next[21] = gpio_out_gpio_out_21_qs;
        reg_rdata_next[22] = gpio_out_gpio_out_22_qs;
        reg_rdata_next[23] = gpio_out_gpio_out_23_qs;
        reg_rdata_next[24] = gpio_out_gpio_out_24_qs;
        reg_rdata_next[25] = gpio_out_gpio_out_25_qs;
        reg_rdata_next[26] = gpio_out_gpio_out_26_qs;
        reg_rdata_next[27] = gpio_out_gpio_out_27_qs;
        reg_rdata_next[28] = gpio_out_gpio_out_28_qs;
        reg_rdata_next[29] = gpio_out_gpio_out_29_qs;
        reg_rdata_next[30] = gpio_out_gpio_out_30_qs;
        reg_rdata_next[31] = gpio_out_gpio_out_31_qs;
      end

      addr_hit[7]: begin
        reg_rdata_next[0] = '0;
        reg_rdata_next[1] = '0;
        reg_rdata_next[2] = '0;
        reg_rdata_next[3] = '0;
        reg_rdata_next[4] = '0;
        reg_rdata_next[5] = '0;
        reg_rdata_next[6] = '0;
        reg_rdata_next[7] = '0;
        reg_rdata_next[8] = '0;
        reg_rdata_next[9] = '0;
        reg_rdata_next[10] = '0;
        reg_rdata_next[11] = '0;
        reg_rdata_next[12] = '0;
        reg_rdata_next[13] = '0;
        reg_rdata_next[14] = '0;
        reg_rdata_next[15] = '0;
        reg_rdata_next[16] = '0;
        reg_rdata_next[17] = '0;
        reg_rdata_next[18] = '0;
        reg_rdata_next[19] = '0;
        reg_rdata_next[20] = '0;
        reg_rdata_next[21] = '0;
        reg_rdata_next[22] = '0;
        reg_rdata_next[23] = '0;
        reg_rdata_next[24] = '0;
        reg_rdata_next[25] = '0;
        reg_rdata_next[26] = '0;
        reg_rdata_next[27] = '0;
        reg_rdata_next[28] = '0;
        reg_rdata_next[29] = '0;
        reg_rdata_next[30] = '0;
        reg_rdata_next[31] = '0;
      end

      addr_hit[8]: begin
        reg_rdata_next[0] = '0;
        reg_rdata_next[1] = '0;
        reg_rdata_next[2] = '0;
        reg_rdata_next[3] = '0;
        reg_rdata_next[4] = '0;
        reg_rdata_next[5] = '0;
        reg_rdata_next[6] = '0;
        reg_rdata_next[7] = '0;
        reg_rdata_next[8] = '0;
        reg_rdata_next[9] = '0;
        reg_rdata_next[10] = '0;
        reg_rdata_next[11] = '0;
        reg_rdata_next[12] = '0;
        reg_rdata_next[13] = '0;
        reg_rdata_next[14] = '0;
        reg_rdata_next[15] = '0;
        reg_rdata_next[16] = '0;
        reg_rdata_next[17] = '0;
        reg_rdata_next[18] = '0;
        reg_rdata_next[19] = '0;
        reg_rdata_next[20] = '0;
        reg_rdata_next[21] = '0;
        reg_rdata_next[22] = '0;
        reg_rdata_next[23] = '0;
        reg_rdata_next[24] = '0;
        reg_rdata_next[25] = '0;
        reg_rdata_next[26] = '0;
        reg_rdata_next[27] = '0;
        reg_rdata_next[28] = '0;
        reg_rdata_next[29] = '0;
        reg_rdata_next[30] = '0;
        reg_rdata_next[31] = '0;
      end

      addr_hit[9]: begin
        reg_rdata_next[0] = '0;
        reg_rdata_next[1] = '0;
        reg_rdata_next[2] = '0;
        reg_rdata_next[3] = '0;
        reg_rdata_next[4] = '0;
        reg_rdata_next[5] = '0;
        reg_rdata_next[6] = '0;
        reg_rdata_next[7] = '0;
        reg_rdata_next[8] = '0;
        reg_rdata_next[9] = '0;
        reg_rdata_next[10] = '0;
        reg_rdata_next[11] = '0;
        reg_rdata_next[12] = '0;
        reg_rdata_next[13] = '0;
        reg_rdata_next[14] = '0;
        reg_rdata_next[15] = '0;
        reg_rdata_next[16] = '0;
        reg_rdata_next[17] = '0;
        reg_rdata_next[18] = '0;
        reg_rdata_next[19] = '0;
        reg_rdata_next[20] = '0;
        reg_rdata_next[21] = '0;
        reg_rdata_next[22] = '0;
        reg_rdata_next[23] = '0;
        reg_rdata_next[24] = '0;
        reg_rdata_next[25] = '0;
        reg_rdata_next[26] = '0;
        reg_rdata_next[27] = '0;
        reg_rdata_next[28] = '0;
        reg_rdata_next[29] = '0;
        reg_rdata_next[30] = '0;
        reg_rdata_next[31] = '0;
      end

      addr_hit[10]: begin
        reg_rdata_next[0] = intrpt_rise_en_intrpt_rise_en_0_qs;
        reg_rdata_next[1] = intrpt_rise_en_intrpt_rise_en_1_qs;
        reg_rdata_next[2] = intrpt_rise_en_intrpt_rise_en_2_qs;
        reg_rdata_next[3] = intrpt_rise_en_intrpt_rise_en_3_qs;
        reg_rdata_next[4] = intrpt_rise_en_intrpt_rise_en_4_qs;
        reg_rdata_next[5] = intrpt_rise_en_intrpt_rise_en_5_qs;
        reg_rdata_next[6] = intrpt_rise_en_intrpt_rise_en_6_qs;
        reg_rdata_next[7] = intrpt_rise_en_intrpt_rise_en_7_qs;
        reg_rdata_next[8] = intrpt_rise_en_intrpt_rise_en_8_qs;
        reg_rdata_next[9] = intrpt_rise_en_intrpt_rise_en_9_qs;
        reg_rdata_next[10] = intrpt_rise_en_intrpt_rise_en_10_qs;
        reg_rdata_next[11] = intrpt_rise_en_intrpt_rise_en_11_qs;
        reg_rdata_next[12] = intrpt_rise_en_intrpt_rise_en_12_qs;
        reg_rdata_next[13] = intrpt_rise_en_intrpt_rise_en_13_qs;
        reg_rdata_next[14] = intrpt_rise_en_intrpt_rise_en_14_qs;
        reg_rdata_next[15] = intrpt_rise_en_intrpt_rise_en_15_qs;
        reg_rdata_next[16] = intrpt_rise_en_intrpt_rise_en_16_qs;
        reg_rdata_next[17] = intrpt_rise_en_intrpt_rise_en_17_qs;
        reg_rdata_next[18] = intrpt_rise_en_intrpt_rise_en_18_qs;
        reg_rdata_next[19] = intrpt_rise_en_intrpt_rise_en_19_qs;
        reg_rdata_next[20] = intrpt_rise_en_intrpt_rise_en_20_qs;
        reg_rdata_next[21] = intrpt_rise_en_intrpt_rise_en_21_qs;
        reg_rdata_next[22] = intrpt_rise_en_intrpt_rise_en_22_qs;
        reg_rdata_next[23] = intrpt_rise_en_intrpt_rise_en_23_qs;
        reg_rdata_next[24] = intrpt_rise_en_intrpt_rise_en_24_qs;
        reg_rdata_next[25] = intrpt_rise_en_intrpt_rise_en_25_qs;
        reg_rdata_next[26] = intrpt_rise_en_intrpt_rise_en_26_qs;
        reg_rdata_next[27] = intrpt_rise_en_intrpt_rise_en_27_qs;
        reg_rdata_next[28] = intrpt_rise_en_intrpt_rise_en_28_qs;
        reg_rdata_next[29] = intrpt_rise_en_intrpt_rise_en_29_qs;
        reg_rdata_next[30] = intrpt_rise_en_intrpt_rise_en_30_qs;
        reg_rdata_next[31] = intrpt_rise_en_intrpt_rise_en_31_qs;
      end

      addr_hit[11]: begin
        reg_rdata_next[0] = intrpt_fall_en_intrpt_fall_en_0_qs;
        reg_rdata_next[1] = intrpt_fall_en_intrpt_fall_en_1_qs;
        reg_rdata_next[2] = intrpt_fall_en_intrpt_fall_en_2_qs;
        reg_rdata_next[3] = intrpt_fall_en_intrpt_fall_en_3_qs;
        reg_rdata_next[4] = intrpt_fall_en_intrpt_fall_en_4_qs;
        reg_rdata_next[5] = intrpt_fall_en_intrpt_fall_en_5_qs;
        reg_rdata_next[6] = intrpt_fall_en_intrpt_fall_en_6_qs;
        reg_rdata_next[7] = intrpt_fall_en_intrpt_fall_en_7_qs;
        reg_rdata_next[8] = intrpt_fall_en_intrpt_fall_en_8_qs;
        reg_rdata_next[9] = intrpt_fall_en_intrpt_fall_en_9_qs;
        reg_rdata_next[10] = intrpt_fall_en_intrpt_fall_en_10_qs;
        reg_rdata_next[11] = intrpt_fall_en_intrpt_fall_en_11_qs;
        reg_rdata_next[12] = intrpt_fall_en_intrpt_fall_en_12_qs;
        reg_rdata_next[13] = intrpt_fall_en_intrpt_fall_en_13_qs;
        reg_rdata_next[14] = intrpt_fall_en_intrpt_fall_en_14_qs;
        reg_rdata_next[15] = intrpt_fall_en_intrpt_fall_en_15_qs;
        reg_rdata_next[16] = intrpt_fall_en_intrpt_fall_en_16_qs;
        reg_rdata_next[17] = intrpt_fall_en_intrpt_fall_en_17_qs;
        reg_rdata_next[18] = intrpt_fall_en_intrpt_fall_en_18_qs;
        reg_rdata_next[19] = intrpt_fall_en_intrpt_fall_en_19_qs;
        reg_rdata_next[20] = intrpt_fall_en_intrpt_fall_en_20_qs;
        reg_rdata_next[21] = intrpt_fall_en_intrpt_fall_en_21_qs;
        reg_rdata_next[22] = intrpt_fall_en_intrpt_fall_en_22_qs;
        reg_rdata_next[23] = intrpt_fall_en_intrpt_fall_en_23_qs;
        reg_rdata_next[24] = intrpt_fall_en_intrpt_fall_en_24_qs;
        reg_rdata_next[25] = intrpt_fall_en_intrpt_fall_en_25_qs;
        reg_rdata_next[26] = intrpt_fall_en_intrpt_fall_en_26_qs;
        reg_rdata_next[27] = intrpt_fall_en_intrpt_fall_en_27_qs;
        reg_rdata_next[28] = intrpt_fall_en_intrpt_fall_en_28_qs;
        reg_rdata_next[29] = intrpt_fall_en_intrpt_fall_en_29_qs;
        reg_rdata_next[30] = intrpt_fall_en_intrpt_fall_en_30_qs;
        reg_rdata_next[31] = intrpt_fall_en_intrpt_fall_en_31_qs;
      end

      addr_hit[12]: begin
        reg_rdata_next[0] = intrpt_lvl_high_en_intrpt_lvl_high_en_0_qs;
        reg_rdata_next[1] = intrpt_lvl_high_en_intrpt_lvl_high_en_1_qs;
        reg_rdata_next[2] = intrpt_lvl_high_en_intrpt_lvl_high_en_2_qs;
        reg_rdata_next[3] = intrpt_lvl_high_en_intrpt_lvl_high_en_3_qs;
        reg_rdata_next[4] = intrpt_lvl_high_en_intrpt_lvl_high_en_4_qs;
        reg_rdata_next[5] = intrpt_lvl_high_en_intrpt_lvl_high_en_5_qs;
        reg_rdata_next[6] = intrpt_lvl_high_en_intrpt_lvl_high_en_6_qs;
        reg_rdata_next[7] = intrpt_lvl_high_en_intrpt_lvl_high_en_7_qs;
        reg_rdata_next[8] = intrpt_lvl_high_en_intrpt_lvl_high_en_8_qs;
        reg_rdata_next[9] = intrpt_lvl_high_en_intrpt_lvl_high_en_9_qs;
        reg_rdata_next[10] = intrpt_lvl_high_en_intrpt_lvl_high_en_10_qs;
        reg_rdata_next[11] = intrpt_lvl_high_en_intrpt_lvl_high_en_11_qs;
        reg_rdata_next[12] = intrpt_lvl_high_en_intrpt_lvl_high_en_12_qs;
        reg_rdata_next[13] = intrpt_lvl_high_en_intrpt_lvl_high_en_13_qs;
        reg_rdata_next[14] = intrpt_lvl_high_en_intrpt_lvl_high_en_14_qs;
        reg_rdata_next[15] = intrpt_lvl_high_en_intrpt_lvl_high_en_15_qs;
        reg_rdata_next[16] = intrpt_lvl_high_en_intrpt_lvl_high_en_16_qs;
        reg_rdata_next[17] = intrpt_lvl_high_en_intrpt_lvl_high_en_17_qs;
        reg_rdata_next[18] = intrpt_lvl_high_en_intrpt_lvl_high_en_18_qs;
        reg_rdata_next[19] = intrpt_lvl_high_en_intrpt_lvl_high_en_19_qs;
        reg_rdata_next[20] = intrpt_lvl_high_en_intrpt_lvl_high_en_20_qs;
        reg_rdata_next[21] = intrpt_lvl_high_en_intrpt_lvl_high_en_21_qs;
        reg_rdata_next[22] = intrpt_lvl_high_en_intrpt_lvl_high_en_22_qs;
        reg_rdata_next[23] = intrpt_lvl_high_en_intrpt_lvl_high_en_23_qs;
        reg_rdata_next[24] = intrpt_lvl_high_en_intrpt_lvl_high_en_24_qs;
        reg_rdata_next[25] = intrpt_lvl_high_en_intrpt_lvl_high_en_25_qs;
        reg_rdata_next[26] = intrpt_lvl_high_en_intrpt_lvl_high_en_26_qs;
        reg_rdata_next[27] = intrpt_lvl_high_en_intrpt_lvl_high_en_27_qs;
        reg_rdata_next[28] = intrpt_lvl_high_en_intrpt_lvl_high_en_28_qs;
        reg_rdata_next[29] = intrpt_lvl_high_en_intrpt_lvl_high_en_29_qs;
        reg_rdata_next[30] = intrpt_lvl_high_en_intrpt_lvl_high_en_30_qs;
        reg_rdata_next[31] = intrpt_lvl_high_en_intrpt_lvl_high_en_31_qs;
      end

      addr_hit[13]: begin
        reg_rdata_next[0] = intrpt_lvl_low_en_intrpt_lvl_low_en_0_qs;
        reg_rdata_next[1] = intrpt_lvl_low_en_intrpt_lvl_low_en_1_qs;
        reg_rdata_next[2] = intrpt_lvl_low_en_intrpt_lvl_low_en_2_qs;
        reg_rdata_next[3] = intrpt_lvl_low_en_intrpt_lvl_low_en_3_qs;
        reg_rdata_next[4] = intrpt_lvl_low_en_intrpt_lvl_low_en_4_qs;
        reg_rdata_next[5] = intrpt_lvl_low_en_intrpt_lvl_low_en_5_qs;
        reg_rdata_next[6] = intrpt_lvl_low_en_intrpt_lvl_low_en_6_qs;
        reg_rdata_next[7] = intrpt_lvl_low_en_intrpt_lvl_low_en_7_qs;
        reg_rdata_next[8] = intrpt_lvl_low_en_intrpt_lvl_low_en_8_qs;
        reg_rdata_next[9] = intrpt_lvl_low_en_intrpt_lvl_low_en_9_qs;
        reg_rdata_next[10] = intrpt_lvl_low_en_intrpt_lvl_low_en_10_qs;
        reg_rdata_next[11] = intrpt_lvl_low_en_intrpt_lvl_low_en_11_qs;
        reg_rdata_next[12] = intrpt_lvl_low_en_intrpt_lvl_low_en_12_qs;
        reg_rdata_next[13] = intrpt_lvl_low_en_intrpt_lvl_low_en_13_qs;
        reg_rdata_next[14] = intrpt_lvl_low_en_intrpt_lvl_low_en_14_qs;
        reg_rdata_next[15] = intrpt_lvl_low_en_intrpt_lvl_low_en_15_qs;
        reg_rdata_next[16] = intrpt_lvl_low_en_intrpt_lvl_low_en_16_qs;
        reg_rdata_next[17] = intrpt_lvl_low_en_intrpt_lvl_low_en_17_qs;
        reg_rdata_next[18] = intrpt_lvl_low_en_intrpt_lvl_low_en_18_qs;
        reg_rdata_next[19] = intrpt_lvl_low_en_intrpt_lvl_low_en_19_qs;
        reg_rdata_next[20] = intrpt_lvl_low_en_intrpt_lvl_low_en_20_qs;
        reg_rdata_next[21] = intrpt_lvl_low_en_intrpt_lvl_low_en_21_qs;
        reg_rdata_next[22] = intrpt_lvl_low_en_intrpt_lvl_low_en_22_qs;
        reg_rdata_next[23] = intrpt_lvl_low_en_intrpt_lvl_low_en_23_qs;
        reg_rdata_next[24] = intrpt_lvl_low_en_intrpt_lvl_low_en_24_qs;
        reg_rdata_next[25] = intrpt_lvl_low_en_intrpt_lvl_low_en_25_qs;
        reg_rdata_next[26] = intrpt_lvl_low_en_intrpt_lvl_low_en_26_qs;
        reg_rdata_next[27] = intrpt_lvl_low_en_intrpt_lvl_low_en_27_qs;
        reg_rdata_next[28] = intrpt_lvl_low_en_intrpt_lvl_low_en_28_qs;
        reg_rdata_next[29] = intrpt_lvl_low_en_intrpt_lvl_low_en_29_qs;
        reg_rdata_next[30] = intrpt_lvl_low_en_intrpt_lvl_low_en_30_qs;
        reg_rdata_next[31] = intrpt_lvl_low_en_intrpt_lvl_low_en_31_qs;
      end

      addr_hit[14]: begin
        reg_rdata_next[0] = intrpt_status_intrpt_status_0_qs;
        reg_rdata_next[1] = intrpt_status_intrpt_status_1_qs;
        reg_rdata_next[2] = intrpt_status_intrpt_status_2_qs;
        reg_rdata_next[3] = intrpt_status_intrpt_status_3_qs;
        reg_rdata_next[4] = intrpt_status_intrpt_status_4_qs;
        reg_rdata_next[5] = intrpt_status_intrpt_status_5_qs;
        reg_rdata_next[6] = intrpt_status_intrpt_status_6_qs;
        reg_rdata_next[7] = intrpt_status_intrpt_status_7_qs;
        reg_rdata_next[8] = intrpt_status_intrpt_status_8_qs;
        reg_rdata_next[9] = intrpt_status_intrpt_status_9_qs;
        reg_rdata_next[10] = intrpt_status_intrpt_status_10_qs;
        reg_rdata_next[11] = intrpt_status_intrpt_status_11_qs;
        reg_rdata_next[12] = intrpt_status_intrpt_status_12_qs;
        reg_rdata_next[13] = intrpt_status_intrpt_status_13_qs;
        reg_rdata_next[14] = intrpt_status_intrpt_status_14_qs;
        reg_rdata_next[15] = intrpt_status_intrpt_status_15_qs;
        reg_rdata_next[16] = intrpt_status_intrpt_status_16_qs;
        reg_rdata_next[17] = intrpt_status_intrpt_status_17_qs;
        reg_rdata_next[18] = intrpt_status_intrpt_status_18_qs;
        reg_rdata_next[19] = intrpt_status_intrpt_status_19_qs;
        reg_rdata_next[20] = intrpt_status_intrpt_status_20_qs;
        reg_rdata_next[21] = intrpt_status_intrpt_status_21_qs;
        reg_rdata_next[22] = intrpt_status_intrpt_status_22_qs;
        reg_rdata_next[23] = intrpt_status_intrpt_status_23_qs;
        reg_rdata_next[24] = intrpt_status_intrpt_status_24_qs;
        reg_rdata_next[25] = intrpt_status_intrpt_status_25_qs;
        reg_rdata_next[26] = intrpt_status_intrpt_status_26_qs;
        reg_rdata_next[27] = intrpt_status_intrpt_status_27_qs;
        reg_rdata_next[28] = intrpt_status_intrpt_status_28_qs;
        reg_rdata_next[29] = intrpt_status_intrpt_status_29_qs;
        reg_rdata_next[30] = intrpt_status_intrpt_status_30_qs;
        reg_rdata_next[31] = intrpt_status_intrpt_status_31_qs;
      end

      addr_hit[15]: begin
        reg_rdata_next[0] = intrpt_rise_status_intrpt_rise_status_0_qs;
        reg_rdata_next[1] = intrpt_rise_status_intrpt_rise_status_1_qs;
        reg_rdata_next[2] = intrpt_rise_status_intrpt_rise_status_2_qs;
        reg_rdata_next[3] = intrpt_rise_status_intrpt_rise_status_3_qs;
        reg_rdata_next[4] = intrpt_rise_status_intrpt_rise_status_4_qs;
        reg_rdata_next[5] = intrpt_rise_status_intrpt_rise_status_5_qs;
        reg_rdata_next[6] = intrpt_rise_status_intrpt_rise_status_6_qs;
        reg_rdata_next[7] = intrpt_rise_status_intrpt_rise_status_7_qs;
        reg_rdata_next[8] = intrpt_rise_status_intrpt_rise_status_8_qs;
        reg_rdata_next[9] = intrpt_rise_status_intrpt_rise_status_9_qs;
        reg_rdata_next[10] = intrpt_rise_status_intrpt_rise_status_10_qs;
        reg_rdata_next[11] = intrpt_rise_status_intrpt_rise_status_11_qs;
        reg_rdata_next[12] = intrpt_rise_status_intrpt_rise_status_12_qs;
        reg_rdata_next[13] = intrpt_rise_status_intrpt_rise_status_13_qs;
        reg_rdata_next[14] = intrpt_rise_status_intrpt_rise_status_14_qs;
        reg_rdata_next[15] = intrpt_rise_status_intrpt_rise_status_15_qs;
        reg_rdata_next[16] = intrpt_rise_status_intrpt_rise_status_16_qs;
        reg_rdata_next[17] = intrpt_rise_status_intrpt_rise_status_17_qs;
        reg_rdata_next[18] = intrpt_rise_status_intrpt_rise_status_18_qs;
        reg_rdata_next[19] = intrpt_rise_status_intrpt_rise_status_19_qs;
        reg_rdata_next[20] = intrpt_rise_status_intrpt_rise_status_20_qs;
        reg_rdata_next[21] = intrpt_rise_status_intrpt_rise_status_21_qs;
        reg_rdata_next[22] = intrpt_rise_status_intrpt_rise_status_22_qs;
        reg_rdata_next[23] = intrpt_rise_status_intrpt_rise_status_23_qs;
        reg_rdata_next[24] = intrpt_rise_status_intrpt_rise_status_24_qs;
        reg_rdata_next[25] = intrpt_rise_status_intrpt_rise_status_25_qs;
        reg_rdata_next[26] = intrpt_rise_status_intrpt_rise_status_26_qs;
        reg_rdata_next[27] = intrpt_rise_status_intrpt_rise_status_27_qs;
        reg_rdata_next[28] = intrpt_rise_status_intrpt_rise_status_28_qs;
        reg_rdata_next[29] = intrpt_rise_status_intrpt_rise_status_29_qs;
        reg_rdata_next[30] = intrpt_rise_status_intrpt_rise_status_30_qs;
        reg_rdata_next[31] = intrpt_rise_status_intrpt_rise_status_31_qs;
      end

      addr_hit[16]: begin
        reg_rdata_next[0] = intrpt_fall_status_intrpt_fall_status_0_qs;
        reg_rdata_next[1] = intrpt_fall_status_intrpt_fall_status_1_qs;
        reg_rdata_next[2] = intrpt_fall_status_intrpt_fall_status_2_qs;
        reg_rdata_next[3] = intrpt_fall_status_intrpt_fall_status_3_qs;
        reg_rdata_next[4] = intrpt_fall_status_intrpt_fall_status_4_qs;
        reg_rdata_next[5] = intrpt_fall_status_intrpt_fall_status_5_qs;
        reg_rdata_next[6] = intrpt_fall_status_intrpt_fall_status_6_qs;
        reg_rdata_next[7] = intrpt_fall_status_intrpt_fall_status_7_qs;
        reg_rdata_next[8] = intrpt_fall_status_intrpt_fall_status_8_qs;
        reg_rdata_next[9] = intrpt_fall_status_intrpt_fall_status_9_qs;
        reg_rdata_next[10] = intrpt_fall_status_intrpt_fall_status_10_qs;
        reg_rdata_next[11] = intrpt_fall_status_intrpt_fall_status_11_qs;
        reg_rdata_next[12] = intrpt_fall_status_intrpt_fall_status_12_qs;
        reg_rdata_next[13] = intrpt_fall_status_intrpt_fall_status_13_qs;
        reg_rdata_next[14] = intrpt_fall_status_intrpt_fall_status_14_qs;
        reg_rdata_next[15] = intrpt_fall_status_intrpt_fall_status_15_qs;
        reg_rdata_next[16] = intrpt_fall_status_intrpt_fall_status_16_qs;
        reg_rdata_next[17] = intrpt_fall_status_intrpt_fall_status_17_qs;
        reg_rdata_next[18] = intrpt_fall_status_intrpt_fall_status_18_qs;
        reg_rdata_next[19] = intrpt_fall_status_intrpt_fall_status_19_qs;
        reg_rdata_next[20] = intrpt_fall_status_intrpt_fall_status_20_qs;
        reg_rdata_next[21] = intrpt_fall_status_intrpt_fall_status_21_qs;
        reg_rdata_next[22] = intrpt_fall_status_intrpt_fall_status_22_qs;
        reg_rdata_next[23] = intrpt_fall_status_intrpt_fall_status_23_qs;
        reg_rdata_next[24] = intrpt_fall_status_intrpt_fall_status_24_qs;
        reg_rdata_next[25] = intrpt_fall_status_intrpt_fall_status_25_qs;
        reg_rdata_next[26] = intrpt_fall_status_intrpt_fall_status_26_qs;
        reg_rdata_next[27] = intrpt_fall_status_intrpt_fall_status_27_qs;
        reg_rdata_next[28] = intrpt_fall_status_intrpt_fall_status_28_qs;
        reg_rdata_next[29] = intrpt_fall_status_intrpt_fall_status_29_qs;
        reg_rdata_next[30] = intrpt_fall_status_intrpt_fall_status_30_qs;
        reg_rdata_next[31] = intrpt_fall_status_intrpt_fall_status_31_qs;
      end

      addr_hit[17]: begin
        reg_rdata_next[0] = intrpt_lvl_high_status_intrpt_lvl_high_status_0_qs;
        reg_rdata_next[1] = intrpt_lvl_high_status_intrpt_lvl_high_status_1_qs;
        reg_rdata_next[2] = intrpt_lvl_high_status_intrpt_lvl_high_status_2_qs;
        reg_rdata_next[3] = intrpt_lvl_high_status_intrpt_lvl_high_status_3_qs;
        reg_rdata_next[4] = intrpt_lvl_high_status_intrpt_lvl_high_status_4_qs;
        reg_rdata_next[5] = intrpt_lvl_high_status_intrpt_lvl_high_status_5_qs;
        reg_rdata_next[6] = intrpt_lvl_high_status_intrpt_lvl_high_status_6_qs;
        reg_rdata_next[7] = intrpt_lvl_high_status_intrpt_lvl_high_status_7_qs;
        reg_rdata_next[8] = intrpt_lvl_high_status_intrpt_lvl_high_status_8_qs;
        reg_rdata_next[9] = intrpt_lvl_high_status_intrpt_lvl_high_status_9_qs;
        reg_rdata_next[10] = intrpt_lvl_high_status_intrpt_lvl_high_status_10_qs;
        reg_rdata_next[11] = intrpt_lvl_high_status_intrpt_lvl_high_status_11_qs;
        reg_rdata_next[12] = intrpt_lvl_high_status_intrpt_lvl_high_status_12_qs;
        reg_rdata_next[13] = intrpt_lvl_high_status_intrpt_lvl_high_status_13_qs;
        reg_rdata_next[14] = intrpt_lvl_high_status_intrpt_lvl_high_status_14_qs;
        reg_rdata_next[15] = intrpt_lvl_high_status_intrpt_lvl_high_status_15_qs;
        reg_rdata_next[16] = intrpt_lvl_high_status_intrpt_lvl_high_status_16_qs;
        reg_rdata_next[17] = intrpt_lvl_high_status_intrpt_lvl_high_status_17_qs;
        reg_rdata_next[18] = intrpt_lvl_high_status_intrpt_lvl_high_status_18_qs;
        reg_rdata_next[19] = intrpt_lvl_high_status_intrpt_lvl_high_status_19_qs;
        reg_rdata_next[20] = intrpt_lvl_high_status_intrpt_lvl_high_status_20_qs;
        reg_rdata_next[21] = intrpt_lvl_high_status_intrpt_lvl_high_status_21_qs;
        reg_rdata_next[22] = intrpt_lvl_high_status_intrpt_lvl_high_status_22_qs;
        reg_rdata_next[23] = intrpt_lvl_high_status_intrpt_lvl_high_status_23_qs;
        reg_rdata_next[24] = intrpt_lvl_high_status_intrpt_lvl_high_status_24_qs;
        reg_rdata_next[25] = intrpt_lvl_high_status_intrpt_lvl_high_status_25_qs;
        reg_rdata_next[26] = intrpt_lvl_high_status_intrpt_lvl_high_status_26_qs;
        reg_rdata_next[27] = intrpt_lvl_high_status_intrpt_lvl_high_status_27_qs;
        reg_rdata_next[28] = intrpt_lvl_high_status_intrpt_lvl_high_status_28_qs;
        reg_rdata_next[29] = intrpt_lvl_high_status_intrpt_lvl_high_status_29_qs;
        reg_rdata_next[30] = intrpt_lvl_high_status_intrpt_lvl_high_status_30_qs;
        reg_rdata_next[31] = intrpt_lvl_high_status_intrpt_lvl_high_status_31_qs;
      end

      addr_hit[18]: begin
        reg_rdata_next[0] = intrpt_lvl_low_status_intrpt_lvl_low_status_0_qs;
        reg_rdata_next[1] = intrpt_lvl_low_status_intrpt_lvl_low_status_1_qs;
        reg_rdata_next[2] = intrpt_lvl_low_status_intrpt_lvl_low_status_2_qs;
        reg_rdata_next[3] = intrpt_lvl_low_status_intrpt_lvl_low_status_3_qs;
        reg_rdata_next[4] = intrpt_lvl_low_status_intrpt_lvl_low_status_4_qs;
        reg_rdata_next[5] = intrpt_lvl_low_status_intrpt_lvl_low_status_5_qs;
        reg_rdata_next[6] = intrpt_lvl_low_status_intrpt_lvl_low_status_6_qs;
        reg_rdata_next[7] = intrpt_lvl_low_status_intrpt_lvl_low_status_7_qs;
        reg_rdata_next[8] = intrpt_lvl_low_status_intrpt_lvl_low_status_8_qs;
        reg_rdata_next[9] = intrpt_lvl_low_status_intrpt_lvl_low_status_9_qs;
        reg_rdata_next[10] = intrpt_lvl_low_status_intrpt_lvl_low_status_10_qs;
        reg_rdata_next[11] = intrpt_lvl_low_status_intrpt_lvl_low_status_11_qs;
        reg_rdata_next[12] = intrpt_lvl_low_status_intrpt_lvl_low_status_12_qs;
        reg_rdata_next[13] = intrpt_lvl_low_status_intrpt_lvl_low_status_13_qs;
        reg_rdata_next[14] = intrpt_lvl_low_status_intrpt_lvl_low_status_14_qs;
        reg_rdata_next[15] = intrpt_lvl_low_status_intrpt_lvl_low_status_15_qs;
        reg_rdata_next[16] = intrpt_lvl_low_status_intrpt_lvl_low_status_16_qs;
        reg_rdata_next[17] = intrpt_lvl_low_status_intrpt_lvl_low_status_17_qs;
        reg_rdata_next[18] = intrpt_lvl_low_status_intrpt_lvl_low_status_18_qs;
        reg_rdata_next[19] = intrpt_lvl_low_status_intrpt_lvl_low_status_19_qs;
        reg_rdata_next[20] = intrpt_lvl_low_status_intrpt_lvl_low_status_20_qs;
        reg_rdata_next[21] = intrpt_lvl_low_status_intrpt_lvl_low_status_21_qs;
        reg_rdata_next[22] = intrpt_lvl_low_status_intrpt_lvl_low_status_22_qs;
        reg_rdata_next[23] = intrpt_lvl_low_status_intrpt_lvl_low_status_23_qs;
        reg_rdata_next[24] = intrpt_lvl_low_status_intrpt_lvl_low_status_24_qs;
        reg_rdata_next[25] = intrpt_lvl_low_status_intrpt_lvl_low_status_25_qs;
        reg_rdata_next[26] = intrpt_lvl_low_status_intrpt_lvl_low_status_26_qs;
        reg_rdata_next[27] = intrpt_lvl_low_status_intrpt_lvl_low_status_27_qs;
        reg_rdata_next[28] = intrpt_lvl_low_status_intrpt_lvl_low_status_28_qs;
        reg_rdata_next[29] = intrpt_lvl_low_status_intrpt_lvl_low_status_29_qs;
        reg_rdata_next[30] = intrpt_lvl_low_status_intrpt_lvl_low_status_30_qs;
        reg_rdata_next[31] = intrpt_lvl_low_status_intrpt_lvl_low_status_31_qs;
      end

      default: begin
        reg_rdata_next = '1;
      end
    endcase
  end

  // Unused signal tieoff

  // wdata / byte enable are not always fully used
  // add a blanket unused statement to handle lint waivers
  logic unused_wdata;
  logic unused_be;
  assign unused_wdata = ^reg_wdata;
  assign unused_be = ^reg_be;

  // Assertions for Register Interface
  `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))

endmodule

module gpio_reg_top_intf
#(
  parameter int AW = 11,
  localparam int DW = 32
) (
  input logic clk_i,
  input logic rst_ni,
  REG_BUS.in  regbus_slave,
  // To HW
  output gpio_reg_pkg::gpio_reg2hw_t reg2hw, // Write
  input  gpio_reg_pkg::gpio_hw2reg_t hw2reg, // Read
  // Config
  input devmode_i // If 1, explicit error return for unmapped register access
);
 localparam int unsigned STRB_WIDTH = DW/8;

`include "register_interface/typedef.svh"
`include "register_interface/assign.svh"

  // Define structs for reg_bus
  typedef logic [AW-1:0] addr_t;
  typedef logic [DW-1:0] data_t;
  typedef logic [STRB_WIDTH-1:0] strb_t;
  `REG_BUS_TYPEDEF_ALL(reg_bus, addr_t, data_t, strb_t)

  reg_bus_req_t s_reg_req;
  reg_bus_rsp_t s_reg_rsp;
  
  // Assign SV interface to structs
  `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave)
  `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp)

  

  gpio_reg_top #(
    .reg_req_t(reg_bus_req_t),
    .reg_rsp_t(reg_bus_rsp_t),
    .AW(AW)
  ) i_regs (
    .clk_i,
    .rst_ni,
    .reg_req_i(s_reg_req),
    .reg_rsp_o(s_reg_rsp),
    .reg2hw, // Write
    .hw2reg, // Read
    .devmode_i
  );
  
endmodule


