//## 8.2 Division Operations

[wavedrom, ,svg]
....
{reg: [
  {bits: 7,  name: 'opcode', attr: ['7', 'OP', 'OP-32']},
  {bits: 5,  name: 'rd',     attr: ['5', 'dest', 'dest']},
  {bits: 3,  name: 'funct3',  attr: ['3','DIV[U]/REM[U]', 'DIV[U]W/REM[U]W']},
  {bits: 5,  name: 'rs1',    attr: ['5', 'dividend', 'dividend']},
  {bits: 5,  name: 'rs2',    attr: ['5', 'divisor', 'divisor']},
  {bits: 7,  name: 'funct7', attr: ['7', 'MULDIV', 'MULDIV']},
]}
....

//[wavedrom, ,svg]
//....
//{reg: [
//  {bits: 7,  name: 'opcode', attr: 'OP-32'},
//  {bits: 5,  name: 'rd',     attr: 'dest'},
//  {bits: 3,  name: 'funct3',  attr: ['DIVW', 'DIVUW', 'REMW', 'REMUW']},
//  {bits: 5,  name: 'rs1',    attr: 'dividend'},
//  {bits: 5,  name: 'rs2',    attr: 'divisor'},
//  {bits: 7,  name: 'funct7', attr: 'MULDIV'},
//]}
//....
