[[rv32e]]
== RV32E and RV64E Base Integer Instruction Sets, Version 2.0
This chapter describes a proposal for the RV32E and RV64E base integer
instruction sets, designed for microcontrollers in embedded systems.
RV32E and RV64E are reduced versions of RV32I and RV64I, respectively:
the only change is to reduce the number of integer registers to 16. This
chapter only outlines the differences between RV32E/RV64E and
RV32I/RV64I, and so should be read after <<rv32>> and <<rv64>>.
(((RV32E, design)))
[NOTE]
====
RV32E was designed to provide an even smaller base core for embedded
microcontrollers. There is also interest in RV64E for microcontrollers
within large SoC designs, and to reduce context state for highly
threaded 64-bit processors.

Unless otherwise stated, standard extensions compatible with RV32I and
RV64I are also compatible with RV32E and RV64E, respectively.
====

=== RV32E and RV64E Programmers’ Model
RV32E and RV64E reduce the integer register count to 16 general-purpose
registers, (`x0-x15`), where `x0` is a dedicated zero register.

[NOTE]
====
We have found that in the small RV32I core implementations, the upper 16
registers consume around one quarter of the total area of the core
excluding memories, thus their removal saves around 25% core area with a
corresponding core power reduction.
====

=== RV32E and RV64E Instruction Set Encoding
(((RV32E, difference from RV32I)))
RV32E and RV64E use the same instruction-set encoding as RV32I and RV64I
respectively, except that only registers `x0-x15` are provided. All
encodings specifying the other registers `x16-x31` are reserved.

[NOTE]
====
The previous draft of this chapter made all encodings using the
`x16-x31` registers available as custom. This version takes a more
conservative approach, making these reserved so that they can be
allocated between custom space or new standard encodings at a later
date.
====
