//### Integer Register-Register Operations

[wavedrom, ,svg]
....
{reg: [
  {bits: 7,  name: 'opcode',    attr: ['7', 'OP', 'OP', 'OP', 'OP']},
  {bits: 5,  name: 'rd',        attr: ['5', 'dest', 'dest', 'dest','dest']},
  {bits: 3,  name: 'funct3',     attr: ['3', 'ADD/SLT[U]', 'AND/OR/XOR', 'SLL/SRL', 'SUB/SRA']},
  {bits: 5,  name: 'rs1',       attr: ['5', 'src1', 'src1', 'src1', 'src1']},
  {bits: 5,  name: 'rs2',       attr: ['5', 'src2', 'src2', 'src2', 'src2']},
  {bits: 7,  name: 'funct7', attr: ['7', 0, 0, 0, 32]}
]}
....
