//### Figure 2.2

//RISC-V base instruction formats. Each immediate subfield is labeled with the bit position (imm[x]) in the immediate value being produced, rather than the bit position within the instruction’s immediate field as is usually done.

[wavedrom, ,svg]
....
{reg: [
  {bits: 7,  name: 'opcode'},
  {bits: 5,  name: 'rd'},
  {bits: 3,  name: 'funct3'},
  {bits: 5,  name: 'rs1'},
  {bits: 5,  name: 'rs2'},
  {bits: 7,  name: 'funct7'}
], config: {label: {right: 'R-Type'}}}
....

[wavedrom, ,svg]
....
{reg: [
  {bits: 7,  name: 'opcode'},
  {bits: 5,  name: 'rd'},
  {bits: 3,  name: 'funct3'},
  {bits: 5,  name: 'rs1'},
  {bits: 12, name: 'imm[11:0]'},
], config: {label: {right: 'I-Type'}}}
....

[wavedrom, ,svg]
....
{reg: [
  {bits: 7,  name: 'opcode'},
  {bits: 5,  name: 'imm[4:0]'},
  {bits: 3,  name: 'funct3'},
  {bits: 5,  name: 'rs1'},
  {bits: 5,  name: 'rs2'},
  {bits: 7,  name: 'imm[11:5]'}
], config: {label: {right: 'S-Type'}}}
....

[wavedrom, ,svg]
....
{reg: [
  {bits: 7,  name: 'opcode'},
  {bits: 5,  name: 'rd'},
  {bits: 20,  name: 'imm[31:12]'}
], config: {label: {right: 'U-Type'}}}
....

