//## 13.4 Double-Precision Floating-Point Computational Instructions

[wavedrom, ,svg]
....
{reg: [
  {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP']},
  {bits: 5, name: 'rd',     attr: ['5','dest','dest','dest','dest']},
  {bits: 3, name: 'rm',     attr: ['3','RM','RM','MIN/MAX','RM']},
  {bits: 5, name: 'rs1',    attr: ['5','src1','src1','src1','src']},
  {bits: 5, name: 'rs2',    attr: ['5','src2','src2','src2','0']},
  {bits: 2, name: 'fmt',    attr: ['2','D','D','D','D']},
  {bits: 5, name: 'funct5', attr: ['5','FADD/FSUB', 'FMUL/FDIV', 'FMIN-MAX', 'FSQRT']},
]}
....

[wavedrom, ,svg]
....
{reg: [
  {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB']},
  {bits: 5, name: 'rd',     attr: ['5','dest']},
  {bits: 3, name: 'rm',     attr: ['3','RM']},
  {bits: 5, name: 'rs1',    attr: ['5','src']},
  {bits: 5, name: 'rs2',    attr: ['5','src2']},
  {bits: 2, name: 'fmt',    attr: ['2','D']},
  {bits: 5, name: 'rs3',    attr: ['5','src3']},
]}
....

//[wavedrom, ,]
//....
//{reg: [
//  {bits: 7, name: 'opcode', attr: 'OP-FP'},
//  {bits: 5, name: 'rd',     attr: 'dest'},
//  {bits: 3, name: 'funct3',  attr: ['MIN', 'MAX']},
//  {bits: 5, name: 'rs1',    attr: 'src1'},
//  {bits: 5, name: 'rs2',    attr: 'src2'},
//  {bits: 2, name: 'fmt',    attr: 'D'},
//  {bits: 5, name: 'funct5', attr: 'FMIN-MAX'},
//]}
//....

//[wavedrom, ,]
//....
//{reg: [
//  {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB']},
//  {bits: 5, name: 'rd',     attr: 'dest'},
//  {bits: 3, name: 'funct3',  attr: 'RM'},
//  {bits: 5, name: 'rs1',    attr: 'src1'},
//  {bits: 5, name: 'rs2',    attr: 'src2'},
//  {bits: 2, name: 'fmt',    attr: 'D'},
//  {bits: 5, name: 'rs3',    attr: 'src3'},
//]}
//....

