Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date         : Sun Jul 26 02:07:13 2026
| Host         : 685a421e500f running 64-bit unknown
| Command      : report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
| Design       : fpga_top
| Device       : xc7a100t
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |   137 |
|    Minimum number of control sets                        |   137 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |   107 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |   137 |
| >= 0 to < 4        |     3 |
| >= 4 to < 6        |     6 |
| >= 6 to < 8        |     5 |
| >= 8 to < 10       |    19 |
| >= 10 to < 12      |     4 |
| >= 12 to < 14      |     4 |
| >= 14 to < 16      |     0 |
| >= 16              |    96 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |               9 |            5 |
| No           | No                    | Yes                    |              22 |           16 |
| No           | Yes                   | No                     |             148 |           54 |
| Yes          | No                    | No                     |             163 |           52 |
| Yes          | No                    | Yes                    |            2296 |         1016 |
| Yes          | Yes                   | No                     |             407 |          113 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+--------------------------------------+------------------------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+
|             Clock Signal             |                                    Enable Signal                                   |                       Set/Reset Signal                       | Slice Load Count | Bel Load Count | Bels / Slice |
+--------------------------------------+------------------------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+
|  clk_IBUF_BUFG                       |                                                                                    |                                                              |                1 |              1 |         1.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                                   | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_1_n_0             |                1 |              1 |         1.00 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                                    |                                                              |                2 |              2 |         1.00 |
|  clk_o_BUFG                          | ResetBootSystem/counter                                                            |                                                              |                2 |              4 |         2.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/next_bit                                          | ptop/u_Controller/Uart/i_uart_rx/bit_counter[3]_i_1__0_n_0   |                1 |              4 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/E[0]                                              |                                                              |                1 |              4 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_2__0_n_0                         | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_1_n_0      |                1 |              4 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/id_stage_i/controller_i/ctrl_fsm_ns                             | ptop/u_Controller/Interpreter/rst_core                       |                2 |              4 |         2.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/return_state                                         | ResetBootSystem/rst_o_reg_0                                  |                2 |              5 |         2.50 |
|  clk_o_BUFG                          |                                                                                    |                                                              |                2 |              6 |         3.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/load_store_unit_i/ctrl_update                                   | ptop/u_Controller/Interpreter/rst_core                       |                3 |              6 |         2.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/id_stage_i/controller_i/debug_mode_q_reg_3[0]                   | ptop/u_Controller/Interpreter/rst_core                       |                3 |              6 |         2.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[12]_4[0]                        | ptop/u_Controller/Interpreter/rst_core                       |                5 |              7 |         1.40 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/data_to_send[6]_i_1_n_0                           | ResetBootSystem/rst_o_reg_0                                  |                2 |              7 |         3.50 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/uart_tx_en                                                  | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/E[0]                                              | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/recieved_data0                                    | ptop/u_Controller/Uart/i_uart_rx/recieved_data[7]_i_1_n_0    |                2 |              8 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/branch_set_raw_q_reg[0]                              | ptop/u_Controller/Interpreter/rst_core                       |                4 |              8 |         2.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/FSM_sequential_state_write_reg[2][0]                | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/id_stage_i/controller_i/ctrl_fsm_cs_reg[3]_5                    | ptop/u_Controller/Interpreter/rst_core                       |                4 |              8 |         2.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/uart_rx_data[7]_i_1_n_0                           | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/E[1]                                                 | ptop/u_Controller/Interpreter/rst_core                       |                3 |              8 |         2.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/counter                                              | ResetBootSystem/rst_o_reg_0                                  |                4 |              8 |         2.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/id_stage_i/controller_i/ctrl_fsm_cs_reg[2]_3[0]                 | ptop/u_Controller/Interpreter/rst_core                       |                5 |              8 |         1.60 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/FSM_sequential_ls_fsm_cs_reg[1]_0[1]                 | ptop/u_Controller/Interpreter/rst_core                       |                3 |              8 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_valid_id_q_reg_8[1]                            | ptop/u_Controller/Interpreter/rst_core                       |                3 |              8 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/mcountinhibit_q_reg[12][1]                           | ptop/u_Controller/Interpreter/rst_core                       |                3 |              8 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/FSM_sequential_ls_fsm_cs_reg[1][1]                   | ptop/u_Controller/Interpreter/rst_core                       |                3 |              8 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/mcountinhibit_q_reg[11][1]                           | ptop/u_Controller/Interpreter/rst_core                       |                4 |              8 |         2.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/accumulator[7]_i_1_n_0                               | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/id_fsm_q_reg_1[1]                                    | ptop/u_Controller/Interpreter/rst_core                       |                4 |              8 |         2.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_is_compressed_id_o_reg_0[1]                    | ptop/u_Controller/Interpreter/rst_core                       |                4 |              8 |         2.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/branch_jump_set_done_q_reg[0]                        | ptop/u_Controller/Interpreter/rst_core                       |                5 |              8 |         1.60 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                                   | ResetBootSystem/SR[0]                                        |                3 |             10 |         3.33 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/cycle_counter0                                    | ptop/u_Controller/Uart/i_uart_rx/cycle_counter[9]_i_1__0_n_0 |                3 |             10 |         3.33 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/read_ptr0                                           | ResetBootSystem/rst_o_reg_0                                  |                3 |             11 |         3.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/read_ptr[2]_i_1_n_0                                 | ResetBootSystem/rst_o_reg_0                                  |                3 |             11 |         3.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/memory_reg_0_7_0_5_i_1__0_n_0                       |                                                              |                2 |             12 |         6.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/memory_reg_0_7_0_5_i_1_n_0                          |                                                              |                2 |             12 |         6.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[12]_22[0]                       | ptop/u_Controller/Interpreter/rst_core                       |                7 |             12 |         1.71 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/address[31]_i_1_n_0                                  |                                                              |                9 |             12 |         1.33 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[12]_21[0]                       | ptop/u_Controller/Interpreter/rst_core                       |               14 |             19 |         1.36 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                                    | ptop/u_Controller/Interpreter/rst_core                       |               16 |             22 |         1.38 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/accumulator0                                         | ResetBootSystem/rst_o_reg_0                                  |                6 |             24 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/load_store_unit_i/rdata_q[31]_i_1__6_n_0                        | ptop/u_Controller/Interpreter/rst_core                       |                9 |             24 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[12]_2[0]                        | ptop/u_Controller/Interpreter/rst_core                       |                7 |             24 |         3.43 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/memory_page_number[23]_i_2_n_0                       | ptop/u_Controller/Interpreter/memory_page_number[23]_i_1_n_0 |                7 |             24 |         3.43 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_cycles_to_pulse[23]_i_1_n_0                   |                                                              |                7 |             24 |         3.43 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/timeout                                              | ResetBootSystem/rst_o_reg_0                                  |                8 |             24 |         3.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_pages                                         | ResetBootSystem/rst_o_reg_0                                  |                4 |             24 |         6.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/prefetch_buffer_i/stored_addr_en                     | ptop/u_Controller/Interpreter/rst_core                       |               10 |             30 |         3.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/id_stage_i/controller_i/valid_req_q_reg[0]                      | ptop/u_Controller/Interpreter/rst_core                       |                8 |             30 |         3.75 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/id_stage_i/controller_i/E[0]                                    | ptop/u_Controller/Interpreter/rst_core                       |                8 |             31 |         3.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/ctrl_fsm_cs_reg[2]_0[0]                              | ptop/u_Controller/Interpreter/rst_core                       |               16 |             31 |         1.94 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/ctrl_fsm_cs_reg[3]_1[0]                              | ptop/u_Controller/Interpreter/rst_core                       |               17 |             31 |         1.82 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/communication_buffer[31]_i_1_n_0                     | ResetBootSystem/rst_o_reg_0                                  |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/load_store_unit_i/addr_update                                   | ptop/u_Controller/Interpreter/rst_core                       |                9 |             32 |         3.56 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/rdata_q[31]_i_4__4_0[0]                              | ptop/u_Controller/Interpreter/rst_core                       |               15 |             32 |         2.13 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/E[0]                                                 | ptop/u_Controller/Interpreter/rst_core                       |               11 |             32 |         2.91 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/prefetch_buffer_i/fifo_i/entry_en_2                  | ptop/u_Controller/Interpreter/rst_core                       |                9 |             32 |         3.56 |
|  clk_o_BUFG                          | ptop/u_Controller/ClkDivider/pulse_counter[0]_i_1_n_0                              | ResetBootSystem/rst_o_reg_0                                  |                8 |             32 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[11]_3[0]                        | ptop/u_Controller/Interpreter/rst_core                       |               11 |             32 |         2.91 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[11]_1[0]                        | ptop/u_Controller/Interpreter/rst_core                       |               11 |             32 |         2.91 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[11]_2[0]                        | ptop/u_Controller/Interpreter/rst_core                       |               13 |             32 |         2.46 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/end_position[31]_i_1_n_0                             | ResetBootSystem/rst_o_reg_0                                  |               12 |             32 |         2.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/timeout_counter                                      | ResetBootSystem/rst_o_reg_0                                  |                5 |             32 |         6.40 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/write_data[31]_i_1_n_0                               |                                                              |               14 |             32 |         2.29 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/id_fsm_q_reg_1[0]                                    | ptop/u_Controller/Interpreter/rst_core                       |               17 |             32 |         1.88 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/read_buffer                                          | ResetBootSystem/rst_o_reg_0                                  |               18 |             32 |         1.78 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/communication_write_data[31]_i_1_n_0                 |                                                              |                7 |             32 |         4.57 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/E[0]                                                | ResetBootSystem/rst_o_reg_0                                  |                5 |             32 |         6.40 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/E[0]                                                | ResetBootSystem/rst_o_reg_0                                  |                4 |             32 |         8.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/ex_block_i/gen_multdiv_fast.multdiv_i/op_quotient_q[31]_i_1_n_0 | ptop/u_Controller/Interpreter/rst_core                       |               18 |             32 |         1.78 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[9]_3[0]                         | ptop/u_Controller/Interpreter/rst_core                       |               19 |             32 |         1.68 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[7]_6[0]                         | ptop/u_Controller/Interpreter/rst_core                       |               15 |             32 |         2.13 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[7]_4[0]                         | ptop/u_Controller/Interpreter/rst_core                       |               16 |             32 |         2.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[8]_8[0]                         | ptop/u_Controller/Interpreter/rst_core                       |               16 |             32 |         2.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[8]_4[0]                         | ptop/u_Controller/Interpreter/rst_core                       |               10 |             32 |         3.20 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[8]_3[0]                         | ptop/u_Controller/Interpreter/rst_core                       |               14 |             32 |         2.29 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[9]_1[0]                         | ptop/u_Controller/Interpreter/rst_core                       |               14 |             32 |         2.29 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[7]_0[0]                         | ptop/u_Controller/Interpreter/rst_core                       |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[7]_7[0]                         | ptop/u_Controller/Interpreter/rst_core                       |               24 |             32 |         1.33 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[7]_3[0]                         | ptop/u_Controller/Interpreter/rst_core                       |               22 |             32 |         1.45 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[8]_1[0]                         | ptop/u_Controller/Interpreter/rst_core                       |               10 |             32 |         3.20 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[8]_5[0]                         | ptop/u_Controller/Interpreter/rst_core                       |               10 |             32 |         3.20 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[11]_0[0]                        | ptop/u_Controller/Interpreter/rst_core                       |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/rdata_q[31]_i_3__2_0[0]                              | ptop/u_Controller/Interpreter/rst_core                       |               16 |             32 |         2.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[7]_9[0]                         | ptop/u_Controller/Interpreter/rst_core                       |                9 |             32 |         3.56 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[7]_8[0]                         | ptop/u_Controller/Interpreter/rst_core                       |               14 |             32 |         2.29 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[9]_0[0]                         | ptop/u_Controller/Interpreter/rst_core                       |               10 |             32 |         3.20 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[9]_2[0]                         | ptop/u_Controller/Interpreter/rst_core                       |               21 |             32 |         1.52 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[7]_1[0]                         | ptop/u_Controller/Interpreter/rst_core                       |               11 |             32 |         2.91 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[9]_4[0]                         | ptop/u_Controller/Interpreter/rst_core                       |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[11]_5[0]                        | ptop/u_Controller/Interpreter/rst_core                       |               14 |             32 |         2.29 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[7]_5[0]                         | ptop/u_Controller/Interpreter/rst_core                       |               10 |             32 |         3.20 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[8]_7[0]                         | ptop/u_Controller/Interpreter/rst_core                       |               13 |             32 |         2.46 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_valid_id_q_reg_8[0]                            | ptop/u_Controller/Interpreter/rst_core                       |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/ex_block_i/gen_multdiv_fast.multdiv_i/op_numerator_q            | ptop/u_Controller/Interpreter/rst_core                       |                7 |             32 |         4.57 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[7]_2[0]                         | ptop/u_Controller/Interpreter/rst_core                       |               11 |             32 |         2.91 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[12]_19[0]                       | ptop/u_Controller/Interpreter/rst_core                       |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/mcountinhibit_q_reg[11][0]                           | ptop/u_Controller/Interpreter/rst_core                       |               13 |             32 |         2.46 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/mcountinhibit_q_reg[12][0]                           | ptop/u_Controller/Interpreter/rst_core                       |               11 |             32 |         2.91 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/prefetch_buffer_i/fifo_i/entry_en_0                  | ptop/u_Controller/Interpreter/rst_core                       |                8 |             32 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/prefetch_buffer_i/fifo_i/entry_en_1                  | ptop/u_Controller/Interpreter/rst_core                       |               10 |             32 |         3.20 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/mcountinhibit_q_reg[2][0]                            | ptop/u_Controller/Interpreter/rst_core                       |               13 |             32 |         2.46 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_is_compressed_id_o_reg_0[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/mcountinhibit_q_reg[2][1]                            | ptop/u_Controller/Interpreter/rst_core                       |               13 |             32 |         2.46 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/FSM_sequential_ls_fsm_cs_reg[1]_0[0]                 | ptop/u_Controller/Interpreter/rst_core                       |               13 |             32 |         2.46 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/FSM_sequential_ls_fsm_cs_reg[1][0]                   | ptop/u_Controller/Interpreter/rst_core                       |               14 |             32 |         2.29 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/id_stage_i/controller_i/imd_val_we_ex[1]                        | ptop/u_Controller/Interpreter/rst_core                       |               25 |             32 |         1.28 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/id_stage_i/controller_i/branch_jump_set_done_q_reg[0]           | ptop/u_Controller/Interpreter/rst_core                       |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/id_stage_i/controller_i/branch_set_raw_q_reg[0]                 | ptop/u_Controller/Interpreter/rst_core                       |               19 |             32 |         1.68 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[8]_2[0]                         | ptop/u_Controller/Interpreter/rst_core                       |               11 |             32 |         2.91 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/mcountinhibit_q_reg[0][0]                            | ptop/u_Controller/Interpreter/rst_core                       |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/mcountinhibit_q_reg[0][1]                            | ptop/u_Controller/Interpreter/rst_core                       |               11 |             32 |         2.91 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/ctrl_fsm_cs_reg[3]_0[0]                              | ptop/u_Controller/Interpreter/rst_core                       |               23 |             32 |         1.39 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[11]_4[0]                        | ptop/u_Controller/Interpreter/rst_core                       |               14 |             32 |         2.29 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[10]_0[0]                        | ptop/u_Controller/Interpreter/rst_core                       |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[8]_6[0]                         | ptop/u_Controller/Interpreter/rst_core                       |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/instr_rdata_id_o_reg[8]_0[0]                         | ptop/u_Controller/Interpreter/rst_core                       |               23 |             32 |         1.39 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/id_stage_i/controller_i/imd_val_we_ex[0]                        | ptop/u_Controller/Interpreter/rst_core                       |               21 |             34 |         1.62 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_positions[23]_i_1_n_0                         |                                                              |               12 |             55 |         4.58 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                                    | ptop/instr_data[31]_i_1_n_0                                  |               20 |             64 |         3.20 |
|  clk_o_BUFG                          |                                                                                    | ResetBootSystem/rst_o_reg_0                                  |               34 |             84 |         2.47 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/cve2_top_inst/if_stage_i/prefetch_buffer_i/fifo_i/instr_data_reg[16]          | ptop/u_Controller/Interpreter/rst_core                       |               47 |             87 |         1.85 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/memory_mux_selector_reg_42                           |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/address_reg[10]_0                                    |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/address_reg[11]_0                                    |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/memory_mux_selector_reg_41                           |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/cve2_top_inst/if_stage_i/prefetch_buffer_i/memory_mux_selector_reg_1          |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/cve2_top_inst/if_stage_i/prefetch_buffer_i/memory_mux_selector_reg_2          |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/cve2_top_inst/if_stage_i/prefetch_buffer_i/memory_mux_selector_reg_7          |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/cve2_top_inst/if_stage_i/prefetch_buffer_i/memory_mux_selector_reg_5          |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/cve2_top_inst/if_stage_i/prefetch_buffer_i/memory_mux_selector_reg_8          |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/cve2_top_inst/if_stage_i/prefetch_buffer_i/memory_mux_selector_reg_6          |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/cve2_top_inst/if_stage_i/prefetch_buffer_i/memory_mux_selector_reg_4          |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/cve2_top_inst/if_stage_i/prefetch_buffer_i/memory_mux_selector_reg_3          |                                                              |               32 |            128 |         4.00 |
+--------------------------------------+------------------------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+


