/*
 * Do not edit this file, it was generated by gen_pll.sh
 * 
 *   FPGA kind      : ECP5
 *   Input frequency: 25 MHz
 */

/* verilator lint_off TIMESCALEMOD */
module pll_ref_25MHz #(
        parameter freq = 25
    ) (
        input wire clki,
        output wire clko
    );
    (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
    EHXPLLL pll_i (
                .RST(1'b0),
                .STDBY(1'b0),
                .CLKI(clki),
                .CLKOP(clko),
                .CLKFB(clko),
                .CLKINTFB(),
                .PHASESEL0(1'b0),
                .PHASESEL1(1'b0),
                .PHASEDIR(1'b1),
                .PHASESTEP(1'b1),
                .PHASELOADREG(1'b1),
                .PLLWAKESYNC(1'b0),
                .ENCLKOP(1'b0)
            );
    defparam pll_i.PLLRST_ENA = "DISABLED";
    defparam pll_i.INTFB_WAKE = "DISABLED";
    defparam pll_i.STDBY_ENABLE = "DISABLED";
    defparam pll_i.DPHASE_SOURCE = "DISABLED";
    defparam pll_i.OUTDIVIDER_MUXA = "DIVA";
    defparam pll_i.OUTDIVIDER_MUXB = "DIVB";
    defparam pll_i.OUTDIVIDER_MUXC = "DIVC";
    defparam pll_i.OUTDIVIDER_MUXD = "DIVD";
    defparam pll_i.CLKOP_ENABLE = "ENABLED";
    defparam pll_i.CLKOP_FPHASE = 0;
    defparam pll_i.FEEDBK_PATH = "CLKOP";
    generate
        case(freq)
            16: begin
                defparam pll_i.CLKI_DIV=8;
                defparam pll_i.CLKOP_DIV=38;
                defparam pll_i.CLKOP_CPHASE=18;
                defparam pll_i.CLKFB_DIV=5;
            end
            20: begin
                defparam pll_i.CLKI_DIV=5;
                defparam pll_i.CLKOP_DIV=30;
                defparam pll_i.CLKOP_CPHASE=15;
                defparam pll_i.CLKFB_DIV=4;
            end
            24: begin
                defparam pll_i.CLKI_DIV=1;
                defparam pll_i.CLKOP_DIV=24;
                defparam pll_i.CLKOP_CPHASE=11;
                defparam pll_i.CLKFB_DIV=1;
            end
            25: begin
                defparam pll_i.CLKI_DIV=1;
                defparam pll_i.CLKOP_DIV=24;
                defparam pll_i.CLKOP_CPHASE=11;
                defparam pll_i.CLKFB_DIV=1;
            end
            30: begin
                defparam pll_i.CLKI_DIV=5;
                defparam pll_i.CLKOP_DIV=20;
                defparam pll_i.CLKOP_CPHASE=9;
                defparam pll_i.CLKFB_DIV=6;
            end
            35: begin
                defparam pll_i.CLKI_DIV=5;
                defparam pll_i.CLKOP_DIV=17;
                defparam pll_i.CLKOP_CPHASE=8;
                defparam pll_i.CLKFB_DIV=7;
            end
            40: begin
                defparam pll_i.CLKI_DIV=5;
                defparam pll_i.CLKOP_DIV=15;
                defparam pll_i.CLKOP_CPHASE=7;
                defparam pll_i.CLKFB_DIV=8;
            end
            45: begin
                defparam pll_i.CLKI_DIV=5;
                defparam pll_i.CLKOP_DIV=13;
                defparam pll_i.CLKOP_CPHASE=6;
                defparam pll_i.CLKFB_DIV=9;
            end
            48: begin
                defparam pll_i.CLKI_DIV=8;
                defparam pll_i.CLKOP_DIV=13;
                defparam pll_i.CLKOP_CPHASE=6;
                defparam pll_i.CLKFB_DIV=15;
            end
            50: begin
                defparam pll_i.CLKI_DIV=1;
                defparam pll_i.CLKOP_DIV=12;
                defparam pll_i.CLKOP_CPHASE=5;
                defparam pll_i.CLKFB_DIV=2;
            end
            55: begin
                defparam pll_i.CLKI_DIV=5;
                defparam pll_i.CLKOP_DIV=11;
                defparam pll_i.CLKOP_CPHASE=5;
                defparam pll_i.CLKFB_DIV=11;
            end
            60: begin
                defparam pll_i.CLKI_DIV=5;
                defparam pll_i.CLKOP_DIV=10;
                defparam pll_i.CLKOP_CPHASE=4;
                defparam pll_i.CLKFB_DIV=12;
            end
            65: begin
                defparam pll_i.CLKI_DIV=5;
                defparam pll_i.CLKOP_DIV=9;
                defparam pll_i.CLKOP_CPHASE=4;
                defparam pll_i.CLKFB_DIV=13;
            end
            66: begin
                defparam pll_i.CLKI_DIV=8;
                defparam pll_i.CLKOP_DIV=9;
                defparam pll_i.CLKOP_CPHASE=4;
                defparam pll_i.CLKFB_DIV=21;
            end
            70: begin
                defparam pll_i.CLKI_DIV=5;
                defparam pll_i.CLKOP_DIV=9;
                defparam pll_i.CLKOP_CPHASE=4;
                defparam pll_i.CLKFB_DIV=14;
            end
            75: begin
                defparam pll_i.CLKI_DIV=1;
                defparam pll_i.CLKOP_DIV=8;
                defparam pll_i.CLKOP_CPHASE=4;
                defparam pll_i.CLKFB_DIV=3;
            end
            80: begin
                defparam pll_i.CLKI_DIV=5;
                defparam pll_i.CLKOP_DIV=7;
                defparam pll_i.CLKOP_CPHASE=3;
                defparam pll_i.CLKFB_DIV=16;
            end
            85: begin
                defparam pll_i.CLKI_DIV=5;
                defparam pll_i.CLKOP_DIV=7;
                defparam pll_i.CLKOP_CPHASE=3;
                defparam pll_i.CLKFB_DIV=17;
            end
            90: begin
                defparam pll_i.CLKI_DIV=5;
                defparam pll_i.CLKOP_DIV=7;
                defparam pll_i.CLKOP_CPHASE=3;
                defparam pll_i.CLKFB_DIV=18;
            end
            95: begin
                defparam pll_i.CLKI_DIV=5;
                defparam pll_i.CLKOP_DIV=6;
                defparam pll_i.CLKOP_CPHASE=3;
                defparam pll_i.CLKFB_DIV=19;
            end
            100: begin
                defparam pll_i.CLKI_DIV=1;
                defparam pll_i.CLKOP_DIV=6;
                defparam pll_i.CLKOP_CPHASE=2;
                defparam pll_i.CLKFB_DIV=4;
            end
            105: begin
                defparam pll_i.CLKI_DIV=5;
                defparam pll_i.CLKOP_DIV=6;
                defparam pll_i.CLKOP_CPHASE=2;
                defparam pll_i.CLKFB_DIV=21;
            end
            110: begin
                defparam pll_i.CLKI_DIV=5;
                defparam pll_i.CLKOP_DIV=5;
                defparam pll_i.CLKOP_CPHASE=2;
                defparam pll_i.CLKFB_DIV=22;
            end
            115: begin
                defparam pll_i.CLKI_DIV=5;
                defparam pll_i.CLKOP_DIV=5;
                defparam pll_i.CLKOP_CPHASE=2;
                defparam pll_i.CLKFB_DIV=23;
            end
            120: begin
                defparam pll_i.CLKI_DIV=5;
                defparam pll_i.CLKOP_DIV=5;
                defparam pll_i.CLKOP_CPHASE=2;
                defparam pll_i.CLKFB_DIV=24;
            end
            125: begin
                defparam pll_i.CLKI_DIV=1;
                defparam pll_i.CLKOP_DIV=5;
                defparam pll_i.CLKOP_CPHASE=2;
                defparam pll_i.CLKFB_DIV=5;
            end
            130: begin
                defparam pll_i.CLKI_DIV=5;
                defparam pll_i.CLKOP_DIV=5;
                defparam pll_i.CLKOP_CPHASE=2;
                defparam pll_i.CLKFB_DIV=26;
            end
            135: begin
                defparam pll_i.CLKI_DIV=5;
                defparam pll_i.CLKOP_DIV=4;
                defparam pll_i.CLKOP_CPHASE=2;
                defparam pll_i.CLKFB_DIV=27;
            end
            140: begin
                defparam pll_i.CLKI_DIV=5;
                defparam pll_i.CLKOP_DIV=4;
                defparam pll_i.CLKOP_CPHASE=1;
                defparam pll_i.CLKFB_DIV=28;
            end
            default: UNKNOWN_FREQUENCY unknown_frequency();
        endcase
    endgenerate
endmodule
/* verilator lint_on TIMESCALEMOD */
