Skip to content
[Jenkins]Jenkins
log in

Workspace

/ e200_opensource /
.git
.Xil
boards
doc
fpga
prebuilt_tools
riscv-tools
rtl/e203
sirv-e-sdk
tb
vsim
.gitignoreJun 21, 2026, 4:37:22 AM216 B
book2pic.jpgJun 21, 2026, 4:37:23 AM69.45 KiB
bookpic.jpgJun 21, 2026, 4:37:23 AM71.73 KiB
build_digilent_arty_a7_100t.tclJun 21, 2026, 4:38:00 AM6.48 KiB
clockInfo.txtJun 21, 2026, 4:38:59 AM375 B
digilent_arty_a7_100t.bitJun 21, 2026, 4:39:54 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptJun 21, 2026, 4:39:03 AM16.56 KiB
digilent_arty_a7_control_sets.rptJun 21, 2026, 4:39:03 AM12.95 KiB
digilent_arty_a7_drc.rptJun 21, 2026, 4:39:35 AM2.34 KiB
digilent_arty_a7_io.rptJun 21, 2026, 4:39:03 AM96.81 KiB
digilent_arty_a7_power.rptJun 21, 2026, 4:39:35 AM8.59 KiB
digilent_arty_a7_route_status.rptJun 21, 2026, 4:39:34 AM651 B
digilent_arty_a7_timing.rptJun 21, 2026, 4:39:35 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptJun 21, 2026, 4:39:03 AM3.22 KiB
digilent_arty_a7_utilization_place.rptJun 21, 2026, 4:39:03 AM10.57 KiB
LICENSEJun 21, 2026, 4:37:22 AM11.09 KiB
processor_ci_defines.vhJun 21, 2026, 4:38:00 AM300 B
README.mdJun 21, 2026, 4:37:22 AM8.75 KiB