Skip to content

Workspace

.git
.Xil
boards
doc
fpga
prebuilt_tools
riscv-tools
rtl/e203
sirv-e-sdk
tb
vsim
.gitignoreMay 13, 2026, 4:34:06 AM216 B
book2pic.jpgMay 13, 2026, 4:34:07 AM69.45 KiB
bookpic.jpgMay 13, 2026, 4:34:07 AM71.73 KiB
build_digilent_arty_a7_100t.tclMay 13, 2026, 4:37:52 AM6.48 KiB
clockInfo.txtMay 13, 2026, 4:38:50 AM375 B
digilent_arty_a7_100t.bitMay 13, 2026, 4:39:44 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptMay 13, 2026, 4:38:54 AM16.56 KiB
digilent_arty_a7_control_sets.rptMay 13, 2026, 4:38:54 AM12.95 KiB
digilent_arty_a7_drc.rptMay 13, 2026, 4:39:25 AM2.34 KiB
digilent_arty_a7_io.rptMay 13, 2026, 4:38:54 AM96.81 KiB
digilent_arty_a7_power.rptMay 13, 2026, 4:39:26 AM8.59 KiB
digilent_arty_a7_route_status.rptMay 13, 2026, 4:39:24 AM651 B
digilent_arty_a7_timing.rptMay 13, 2026, 4:39:26 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptMay 13, 2026, 4:38:53 AM3.22 KiB
digilent_arty_a7_utilization_place.rptMay 13, 2026, 4:38:53 AM10.57 KiB
LICENSEMay 13, 2026, 4:34:06 AM11.09 KiB
processor_ci_defines.vhMay 13, 2026, 4:37:52 AM300 B
README.mdMay 13, 2026, 4:34:06 AM8.75 KiB