Skip to content
[Jenkins]Jenkins
log in

Workspace

/ e200_opensource /
.git
.Xil
boards
doc
fpga
prebuilt_tools
riscv-tools
rtl/e203
sirv-e-sdk
tb
vsim
.gitignoreMay 18, 2026, 4:34:02 AM216 B
book2pic.jpgMay 18, 2026, 4:34:03 AM69.45 KiB
bookpic.jpgMay 18, 2026, 4:34:03 AM71.73 KiB
build_digilent_arty_a7_100t.tclMay 18, 2026, 4:37:45 AM6.48 KiB
clockInfo.txtMay 18, 2026, 4:38:43 AM375 B
digilent_arty_a7_100t.bitMay 18, 2026, 4:39:37 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptMay 18, 2026, 4:38:47 AM16.56 KiB
digilent_arty_a7_control_sets.rptMay 18, 2026, 4:38:47 AM12.95 KiB
digilent_arty_a7_drc.rptMay 18, 2026, 4:39:19 AM2.34 KiB
digilent_arty_a7_io.rptMay 18, 2026, 4:38:47 AM96.81 KiB
digilent_arty_a7_power.rptMay 18, 2026, 4:39:19 AM8.59 KiB
digilent_arty_a7_route_status.rptMay 18, 2026, 4:39:18 AM651 B
digilent_arty_a7_timing.rptMay 18, 2026, 4:39:19 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptMay 18, 2026, 4:38:47 AM3.22 KiB
digilent_arty_a7_utilization_place.rptMay 18, 2026, 4:38:47 AM10.57 KiB
LICENSEMay 18, 2026, 4:34:02 AM11.09 KiB
processor_ci_defines.vhMay 18, 2026, 4:37:45 AM300 B
README.mdMay 18, 2026, 4:34:02 AM8.75 KiB