Skip to content
[Jenkins]Jenkins
log in

Workspace

/ e200_opensource /
.git
.Xil
boards
doc
fpga
prebuilt_tools
riscv-tools
rtl/e203
sirv-e-sdk
tb
vsim
.gitignoreSep 27, 2026, 4:33:27 AM216 B
book2pic.jpgSep 27, 2026, 4:33:27 AM69.45 KiB
bookpic.jpgSep 27, 2026, 4:33:27 AM71.73 KiB
build_digilent_arty_a7_100t.tclSep 27, 2026, 4:33:34 AM6.48 KiB
clockInfo.txtSep 27, 2026, 4:34:33 AM375 B
digilent_arty_a7_100t.bitSep 27, 2026, 4:35:28 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptSep 27, 2026, 4:34:37 AM16.56 KiB
digilent_arty_a7_control_sets.rptSep 27, 2026, 4:34:37 AM12.95 KiB
digilent_arty_a7_drc.rptSep 27, 2026, 4:35:09 AM2.34 KiB
digilent_arty_a7_io.rptSep 27, 2026, 4:34:37 AM96.81 KiB
digilent_arty_a7_power.rptSep 27, 2026, 4:35:09 AM8.59 KiB
digilent_arty_a7_route_status.rptSep 27, 2026, 4:35:08 AM651 B
digilent_arty_a7_timing.rptSep 27, 2026, 4:35:09 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptSep 27, 2026, 4:34:37 AM3.22 KiB
digilent_arty_a7_utilization_place.rptSep 27, 2026, 4:34:37 AM10.57 KiB
LICENSESep 27, 2026, 4:33:27 AM11.09 KiB
processor_ci_defines.vhSep 27, 2026, 4:33:34 AM300 B
README.mdSep 27, 2026, 4:33:27 AM8.75 KiB