Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date         : Sun Jun 28 00:38:02 2026
| Host         : 685a421e500f running 64-bit unknown
| Command      : report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
| Design       : fpga_top
| Device       : xc7a100t
---------------------------------------------------------------------------------------------------------------------------------------------

Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |    45 |
|    Minimum number of control sets                        |    45 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |    63 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |    45 |
| >= 0 to < 4        |     2 |
| >= 4 to < 6        |     5 |
| >= 6 to < 8        |     2 |
| >= 8 to < 10       |     7 |
| >= 10 to < 12      |     4 |
| >= 12 to < 14      |     3 |
| >= 14 to < 16      |     0 |
| >= 16              |    22 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |               7 |            4 |
| No           | No                    | Yes                    |               0 |            0 |
| No           | Yes                   | No                     |              48 |           23 |
| Yes          | No                    | No                     |             139 |           47 |
| Yes          | No                    | Yes                    |               0 |            0 |
| Yes          | Yes                   | No                     |             407 |           99 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+----------------+---------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+
|  Clock Signal  |                            Enable Signal                            |                       Set/Reset Signal                       | Slice Load Count | Bel Load Count | Bels / Slice |
+----------------+---------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+
|  clk_IBUF_BUFG |                                                                     |                                                              |                1 |              1 |         1.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                    | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_1_n_0             |                1 |              1 |         1.00 |
|  clk_o_BUFG    | ResetBootSystem/counter                                             |                                                              |                1 |              4 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_rx/next_bit                           | ptop/u_Controller/Uart/i_uart_rx/bit_counter[3]_i_1__0_n_0   |                1 |              4 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_2__0_n_0          | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_1_n_0      |                1 |              4 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_tx/E[0]                               |                                                              |                1 |              4 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/return_state                          | ResetBootSystem/rst_o_reg_0                                  |                2 |              5 |         2.50 |
|  clk_o_BUFG    |                                                                     |                                                              |                3 |              6 |         2.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_tx/data_to_send[6]_i_1_n_0            | ResetBootSystem/rst_o_reg_0                                  |                2 |              7 |         3.50 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/tx_fifo/FSM_sequential_state_write_reg[2][0] | ResetBootSystem/rst_o_reg_0                                  |                3 |              8 |         2.67 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/uart_tx_en                                   | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/counter                               | ResetBootSystem/rst_o_reg_0                                  |                3 |              8 |         2.67 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_rx/recieved_data0                     | ptop/u_Controller/Uart/i_uart_rx/recieved_data[7]_i_1_n_0    |                2 |              8 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_rx/uart_rx_data[7]_i_1_n_0            | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/accumulator[7]_i_1_n_0                | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_rx/E[0]                               | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                    | ResetBootSystem/SR[0]                                        |                3 |             10 |         3.33 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_rx/cycle_counter0                     | ptop/u_Controller/Uart/i_uart_rx/cycle_counter[9]_i_1__0_n_0 |                3 |             10 |         3.33 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/tx_fifo/read_ptr[2]_i_1_n_0                  | ResetBootSystem/rst_o_reg_0                                  |                3 |             11 |         3.67 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/rx_fifo/read_ptr0                            | ResetBootSystem/rst_o_reg_0                                  |                3 |             11 |         3.67 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address[31]_i_1_n_0                   |                                                              |                5 |             12 |         2.40 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/rx_fifo/memory_reg_0_7_0_5_i_1__0_n_0        |                                                              |                2 |             12 |         6.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/tx_fifo/memory_reg_0_7_0_5_i_1_n_0           |                                                              |                2 |             12 |         6.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/timeout                               | ResetBootSystem/rst_o_reg_0                                  |                5 |             24 |         4.80 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/memory_page_number[23]_i_2_n_0        | ptop/u_Controller/Interpreter/memory_page_number[23]_i_1_n_0 |                7 |             24 |         3.43 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/accumulator0                          | ResetBootSystem/rst_o_reg_0                                  |                6 |             24 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/num_of_pages                          | ResetBootSystem/rst_o_reg_0                                  |                5 |             24 |         4.80 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/communication_write_data[31]_i_1_n_0  |                                                              |               11 |             32 |         2.91 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/read_buffer                           | ResetBootSystem/rst_o_reg_0                                  |               15 |             32 |         2.13 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/timeout_counter                       | ResetBootSystem/rst_o_reg_0                                  |                5 |             32 |         6.40 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/communication_buffer[31]_i_1_n_0      | ResetBootSystem/rst_o_reg_0                                  |                8 |             32 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/end_position[31]_i_1_n_0              | ResetBootSystem/rst_o_reg_0                                  |                5 |             32 |         6.40 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/rx_fifo/E[0]                                 | ResetBootSystem/rst_o_reg_0                                  |                6 |             32 |         5.33 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/tx_fifo/E[0]                                 | ResetBootSystem/rst_o_reg_0                                  |                4 |             32 |         8.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/write_data[31]_i_1_n_0                |                                                              |               17 |             32 |         1.88 |
|  clk_o_BUFG    |                                                                     | ResetBootSystem/rst_o_reg_0                                  |               23 |             48 |         2.09 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/num_of_positions[23]_i_1_n_0          |                                                              |               12 |             55 |         4.58 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address_reg[31]_3                     |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address_reg[31]_2                     |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address_reg[31]_7                     |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address_reg[31]_4                     |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address_reg[31]_6                     |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address_reg[31]_0                     |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address_reg[31]_5                     |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address_reg[31]_1                     |                                                              |               32 |            128 |         4.00 |
+----------------+---------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+


