Skip to content

Workspace

.git
.Xil
boards
doc
fpga
prebuilt_tools
riscv-tools
rtl/e203
sirv-e-sdk
tb
vsim
.gitignoreSep 25, 2026, 4:33:43 AM216 B
book2pic.jpgSep 25, 2026, 4:33:43 AM69.45 KiB
bookpic.jpgSep 25, 2026, 4:33:43 AM71.73 KiB
build_digilent_arty_a7_100t.tclSep 25, 2026, 4:37:14 AM6.48 KiB
clockInfo.txtSep 25, 2026, 4:38:13 AM375 B
digilent_arty_a7_100t.bitSep 25, 2026, 4:39:08 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptSep 25, 2026, 4:38:18 AM16.56 KiB
digilent_arty_a7_control_sets.rptSep 25, 2026, 4:38:18 AM12.95 KiB
digilent_arty_a7_drc.rptSep 25, 2026, 4:38:50 AM2.34 KiB
digilent_arty_a7_io.rptSep 25, 2026, 4:38:18 AM96.81 KiB
digilent_arty_a7_power.rptSep 25, 2026, 4:38:50 AM8.59 KiB
digilent_arty_a7_route_status.rptSep 25, 2026, 4:38:49 AM651 B
digilent_arty_a7_timing.rptSep 25, 2026, 4:38:50 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptSep 25, 2026, 4:38:17 AM3.22 KiB
digilent_arty_a7_utilization_place.rptSep 25, 2026, 4:38:18 AM10.57 KiB
LICENSESep 25, 2026, 4:33:43 AM11.09 KiB
processor_ci_defines.vhSep 25, 2026, 4:37:14 AM300 B
README.mdSep 25, 2026, 4:33:43 AM8.75 KiB