Skip to content

Workspace

.git
.Xil
boards
doc
fpga
prebuilt_tools
riscv-tools
rtl/e203
sirv-e-sdk
tb
vsim
.gitignoreJun 22, 2026, 4:34:51 AM216 B
book2pic.jpgJun 22, 2026, 4:34:52 AM69.45 KiB
bookpic.jpgJun 22, 2026, 4:34:52 AM71.73 KiB
build_digilent_arty_a7_100t.tclJun 22, 2026, 4:37:58 AM6.48 KiB
clockInfo.txtJun 22, 2026, 4:38:57 AM375 B
digilent_arty_a7_100t.bitJun 22, 2026, 4:39:51 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptJun 22, 2026, 4:39:01 AM16.56 KiB
digilent_arty_a7_control_sets.rptJun 22, 2026, 4:39:01 AM12.95 KiB
digilent_arty_a7_drc.rptJun 22, 2026, 4:39:32 AM2.34 KiB
digilent_arty_a7_io.rptJun 22, 2026, 4:39:01 AM96.81 KiB
digilent_arty_a7_power.rptJun 22, 2026, 4:39:33 AM8.59 KiB
digilent_arty_a7_route_status.rptJun 22, 2026, 4:39:31 AM651 B
digilent_arty_a7_timing.rptJun 22, 2026, 4:39:33 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptJun 22, 2026, 4:39:01 AM3.22 KiB
digilent_arty_a7_utilization_place.rptJun 22, 2026, 4:39:01 AM10.57 KiB
LICENSEJun 22, 2026, 4:34:51 AM11.09 KiB
processor_ci_defines.vhJun 22, 2026, 4:37:58 AM300 B
README.mdJun 22, 2026, 4:34:51 AM8.75 KiB