Skip to content

Workspace

.git
.Xil
boards
doc
fpga
prebuilt_tools
riscv-tools
rtl/e203
sirv-e-sdk
tb
vsim
.gitignoreAug 2, 2026, 4:34:27 AM216 B
book2pic.jpgAug 2, 2026, 4:34:27 AM69.45 KiB
bookpic.jpgAug 2, 2026, 4:34:27 AM71.73 KiB
build_digilent_arty_a7_100t.tclAug 2, 2026, 4:38:23 AM6.48 KiB
clockInfo.txtAug 2, 2026, 4:39:22 AM375 B
digilent_arty_a7_100t.bitAug 2, 2026, 4:40:18 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptAug 2, 2026, 4:39:27 AM16.56 KiB
digilent_arty_a7_control_sets.rptAug 2, 2026, 4:39:26 AM12.95 KiB
digilent_arty_a7_drc.rptAug 2, 2026, 4:39:59 AM2.34 KiB
digilent_arty_a7_io.rptAug 2, 2026, 4:39:26 AM96.81 KiB
digilent_arty_a7_power.rptAug 2, 2026, 4:40:00 AM8.59 KiB
digilent_arty_a7_route_status.rptAug 2, 2026, 4:39:58 AM651 B
digilent_arty_a7_timing.rptAug 2, 2026, 4:39:59 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptAug 2, 2026, 4:39:26 AM3.22 KiB
digilent_arty_a7_utilization_place.rptAug 2, 2026, 4:39:26 AM10.57 KiB
LICENSEAug 2, 2026, 4:34:27 AM11.09 KiB
processor_ci_defines.vhAug 2, 2026, 4:38:23 AM300 B
README.mdAug 2, 2026, 4:34:27 AM8.75 KiB