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.gitignoreJul 27, 2026, 3:18:10 AM46 B
build_digilent_arty_a7_100t.tclJul 27, 2026, 3:20:27 AM8.34 KiB
clockInfo.txtJul 27, 2026, 3:21:26 AM375 B
digilent_arty_a7_100t.bitJul 27, 2026, 3:22:22 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptJul 27, 2026, 3:21:32 AM16.56 KiB
digilent_arty_a7_control_sets.rptJul 27, 2026, 3:21:32 AM12.95 KiB
digilent_arty_a7_drc.rptJul 27, 2026, 3:22:03 AM2.34 KiB
digilent_arty_a7_io.rptJul 27, 2026, 3:21:31 AM96.81 KiB
digilent_arty_a7_power.rptJul 27, 2026, 3:22:04 AM8.59 KiB
digilent_arty_a7_route_status.rptJul 27, 2026, 3:22:02 AM651 B
digilent_arty_a7_timing.rptJul 27, 2026, 3:22:03 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptJul 27, 2026, 3:21:31 AM3.22 KiB
digilent_arty_a7_utilization_place.rptJul 27, 2026, 3:21:31 AM10.57 KiB
e203_core.coreJul 27, 2026, 3:18:10 AM2.49 KiB
e203_soc.coreJul 27, 2026, 3:18:10 AM4.26 KiB
LICENSEJul 27, 2026, 3:18:10 AM11.09 KiB
processor_ci_defines.vhJul 27, 2026, 3:20:27 AM300 B
README.mdJul 27, 2026, 3:18:10 AM4.58 KiB