CAPI=2:

name : e203_soc

filesets:
  soc:
    files:
      - rtl/e203/perips/apb_i2c/i2c_master_defines.v : {is_include_file : true}
      - rtl/e203/debug/sirv_debug_csr.v
      - rtl/e203/debug/sirv_debug_module.v
      - rtl/e203/debug/sirv_debug_ram.v
      - rtl/e203/debug/sirv_debug_rom.v
      - rtl/e203/debug/sirv_jtag_dtm.v
      - rtl/e203/fab/sirv_icb1to16_bus.v
      - rtl/e203/fab/sirv_icb1to2_bus.v
      - rtl/e203/fab/sirv_icb1to8_bus.v
      - rtl/e203/mems/sirv_mrom_top.v
      - rtl/e203/mems/sirv_mrom.v
      - rtl/e203/perips/apb_adv_timer/adv_timer_apb_if.v
      - rtl/e203/perips/apb_adv_timer/apb_adv_timer.v
      - rtl/e203/perips/apb_adv_timer/comparator.v
      - rtl/e203/perips/apb_adv_timer/input_stage.v
      - rtl/e203/perips/apb_adv_timer/prescaler.v
      - rtl/e203/perips/apb_adv_timer/timer_cntrl.v
      - rtl/e203/perips/apb_adv_timer/timer_module.v
      - rtl/e203/perips/apb_adv_timer/up_down_counter.v
      - rtl/e203/perips/apb_gpio/apb_gpio.v
      - rtl/e203/perips/apb_i2c/apb_i2c.v
      - rtl/e203/perips/apb_i2c/i2c_master_bit_ctrl.v
      - rtl/e203/perips/apb_i2c/i2c_master_byte_ctrl.v
      - rtl/e203/perips/apb_spi_master/apb_spi_master.v
      - rtl/e203/perips/apb_spi_master/spi_master_apb_if.v
      - rtl/e203/perips/apb_spi_master/spi_master_clkgen.v
      - rtl/e203/perips/apb_spi_master/spi_master_controller.v
      - rtl/e203/perips/apb_spi_master/spi_master_fifo.v
      - rtl/e203/perips/apb_spi_master/spi_master_rx.v
      - rtl/e203/perips/apb_spi_master/spi_master_tx.v
      - rtl/e203/perips/apb_uart/apb_uart.v
      - rtl/e203/perips/apb_uart/io_generic_fifo.v
      - rtl/e203/perips/apb_uart/uart_interrupt.v
      - rtl/e203/perips/apb_uart/uart_rx.v
      - rtl/e203/perips/apb_uart/uart_tx.v
      - rtl/e203/perips/sirv_aon_lclkgen_regs.v
      - rtl/e203/perips/sirv_aon_porrst.v
      - rtl/e203/perips/sirv_aon_top.v
      - rtl/e203/perips/sirv_aon.v
      - rtl/e203/perips/sirv_aon_wrapper.v
      - rtl/e203/perips/sirv_AsyncResetReg.v
      - rtl/e203/perips/sirv_AsyncResetRegVec_129.v
      - rtl/e203/perips/sirv_AsyncResetRegVec_1.v
      - rtl/e203/perips/sirv_AsyncResetRegVec_36.v
      - rtl/e203/perips/sirv_AsyncResetRegVec.v
      - rtl/e203/perips/sirv_clint_top.v
      - rtl/e203/perips/sirv_clint.v
      - rtl/e203/perips/sirv_DeglitchShiftRegister.v
      - rtl/e203/perips/sirv_expl_axi_slv.v
      - rtl/e203/perips/sirv_flash_qspi_top.v
      - rtl/e203/perips/sirv_flash_qspi.v
      - rtl/e203/perips/sirv_hclkgen_regs.v
      - rtl/e203/perips/sirv_jtaggpioport.v
      - rtl/e203/perips/sirv_LevelGateway.v
      - rtl/e203/perips/sirv_plic_man.v
      - rtl/e203/perips/sirv_plic_top.v
      - rtl/e203/perips/sirv_pmu_core.v
      - rtl/e203/perips/sirv_pmu.v
      - rtl/e203/perips/sirv_qspi_arbiter.v
      - rtl/e203/perips/sirv_qspi_fifo.v
      - rtl/e203/perips/sirv_qspi_media.v
      - rtl/e203/perips/sirv_qspi_physical.v
      - rtl/e203/perips/sirv_queue_1.v
      - rtl/e203/perips/sirv_queue.v
      - rtl/e203/perips/sirv_repeater_6.v
      - rtl/e203/perips/sirv_ResetCatchAndSync_2.v
      - rtl/e203/perips/sirv_ResetCatchAndSync.v
      - rtl/e203/perips/sirv_rtc.v
      - rtl/e203/perips/sirv_spi_flashmap.v
      - rtl/e203/perips/sirv_tlfragmenter_qspi_1.v
      - rtl/e203/perips/sirv_tl_repeater_5.v
      - rtl/e203/perips/sirv_tlwidthwidget_qspi.v
      - rtl/e203/perips/sirv_wdog.v
      - rtl/e203/soc/e203_soc_top.v
      - rtl/e203/subsys/e203_subsys_clint.v
      - rtl/e203/subsys/e203_subsys_gfcm.v
      - rtl/e203/subsys/e203_subsys_hclkgen_rstsync.v
      - rtl/e203/subsys/e203_subsys_hclkgen.v
      - rtl/e203/subsys/e203_subsys_main.v
      - rtl/e203/subsys/e203_subsys_mems.v
      - rtl/e203/subsys/e203_subsys_perips.v
      - rtl/e203/subsys/e203_subsys_plic.v
      - rtl/e203/subsys/e203_subsys_pllclkdiv.v
      - rtl/e203/subsys/e203_subsys_pll.v
      - rtl/e203/subsys/e203_subsys_top.v
    file_type : verilogSource
    depend : [e203_core]

targets:
  default:
    filesets : [soc]
    parameters : [FPGA_SOURCE]
    toplevel : ["is_toplevel? (e203_soc_top)"]

  lint:
    default_tool : verilator
    filesets : [soc]
    tools:
      verilator:
        mode : lint-only
    toplevel : e203_soc_top

parameters:
  FPGA_SOURCE:
    datatype  : bool
    paramtype : vlogdefine
