Skip to content
[Jenkins]Jenkins
log in

Workspace

/ e203_hbirdv2 /
.git
.github
.Xil
doc
fpga
pics
riscv-tools
rtl/e203
tb
vsim
.gitignoreJul 19, 2026, 3:18:08 AM46 B
build_digilent_arty_a7_100t.tclJul 19, 2026, 3:20:25 AM8.34 KiB
clockInfo.txtJul 19, 2026, 3:21:25 AM375 B
digilent_arty_a7_100t.bitJul 19, 2026, 3:22:19 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptJul 19, 2026, 3:21:29 AM16.56 KiB
digilent_arty_a7_control_sets.rptJul 19, 2026, 3:21:29 AM12.95 KiB
digilent_arty_a7_drc.rptJul 19, 2026, 3:22:00 AM2.34 KiB
digilent_arty_a7_io.rptJul 19, 2026, 3:21:29 AM96.81 KiB
digilent_arty_a7_power.rptJul 19, 2026, 3:22:01 AM8.59 KiB
digilent_arty_a7_route_status.rptJul 19, 2026, 3:21:59 AM651 B
digilent_arty_a7_timing.rptJul 19, 2026, 3:22:01 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptJul 19, 2026, 3:21:28 AM3.22 KiB
digilent_arty_a7_utilization_place.rptJul 19, 2026, 3:21:29 AM10.57 KiB
e203_core.coreJul 19, 2026, 3:18:08 AM2.49 KiB
e203_soc.coreJul 19, 2026, 3:18:08 AM4.26 KiB
LICENSEJul 19, 2026, 3:18:08 AM11.09 KiB
processor_ci_defines.vhJul 19, 2026, 3:20:25 AM300 B
README.mdJul 19, 2026, 3:18:08 AM4.58 KiB