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.gitignoreSep 5, 2026, 3:18:08 AM46 B
build_digilent_arty_a7_100t.tclSep 5, 2026, 3:20:24 AM8.34 KiB
clockInfo.txtSep 5, 2026, 3:21:23 AM375 B
digilent_arty_a7_100t.bitSep 5, 2026, 3:22:17 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptSep 5, 2026, 3:21:27 AM16.56 KiB
digilent_arty_a7_control_sets.rptSep 5, 2026, 3:21:26 AM12.95 KiB
digilent_arty_a7_drc.rptSep 5, 2026, 3:21:58 AM2.34 KiB
digilent_arty_a7_io.rptSep 5, 2026, 3:21:26 AM96.81 KiB
digilent_arty_a7_power.rptSep 5, 2026, 3:21:59 AM8.59 KiB
digilent_arty_a7_route_status.rptSep 5, 2026, 3:21:57 AM651 B
digilent_arty_a7_timing.rptSep 5, 2026, 3:21:58 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptSep 5, 2026, 3:21:26 AM3.22 KiB
digilent_arty_a7_utilization_place.rptSep 5, 2026, 3:21:26 AM10.57 KiB
e203_core.coreSep 5, 2026, 3:18:09 AM2.49 KiB
e203_soc.coreSep 5, 2026, 3:18:09 AM4.26 KiB
LICENSESep 5, 2026, 3:18:08 AM11.09 KiB
processor_ci_defines.vhSep 5, 2026, 3:20:24 AM300 B
README.mdSep 5, 2026, 3:18:08 AM4.58 KiB