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.gitignoreJul 28, 2026, 3:18:10 AM46 B
build_digilent_arty_a7_100t.tclJul 28, 2026, 3:20:32 AM8.34 KiB
clockInfo.txtJul 28, 2026, 3:21:31 AM375 B
digilent_arty_a7_100t.bitJul 28, 2026, 3:22:25 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptJul 28, 2026, 3:21:35 AM16.56 KiB
digilent_arty_a7_control_sets.rptJul 28, 2026, 3:21:34 AM12.95 KiB
digilent_arty_a7_drc.rptJul 28, 2026, 3:22:06 AM2.34 KiB
digilent_arty_a7_io.rptJul 28, 2026, 3:21:34 AM96.81 KiB
digilent_arty_a7_power.rptJul 28, 2026, 3:22:07 AM8.59 KiB
digilent_arty_a7_route_status.rptJul 28, 2026, 3:22:05 AM651 B
digilent_arty_a7_timing.rptJul 28, 2026, 3:22:06 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptJul 28, 2026, 3:21:34 AM3.22 KiB
digilent_arty_a7_utilization_place.rptJul 28, 2026, 3:21:34 AM10.57 KiB
e203_core.coreJul 28, 2026, 3:18:10 AM2.49 KiB
e203_soc.coreJul 28, 2026, 3:18:10 AM4.26 KiB
LICENSEJul 28, 2026, 3:18:10 AM11.09 KiB
processor_ci_defines.vhJul 28, 2026, 3:20:32 AM300 B
README.mdJul 28, 2026, 3:18:10 AM4.58 KiB