Skip to content
[Jenkins]Jenkins
log in

Workspace

/ e203_hbirdv2 /
.git
.github
.Xil
doc
fpga
pics
riscv-tools
rtl/e203
tb
vsim
.gitignoreAug 6, 2026, 3:18:07 AM46 B
build_digilent_arty_a7_100t.tclAug 6, 2026, 3:20:24 AM8.34 KiB
clockInfo.txtAug 6, 2026, 3:21:22 AM375 B
digilent_arty_a7_100t.bitAug 6, 2026, 3:22:17 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptAug 6, 2026, 3:21:27 AM16.56 KiB
digilent_arty_a7_control_sets.rptAug 6, 2026, 3:21:27 AM12.95 KiB
digilent_arty_a7_drc.rptAug 6, 2026, 3:21:58 AM2.34 KiB
digilent_arty_a7_io.rptAug 6, 2026, 3:21:27 AM96.81 KiB
digilent_arty_a7_power.rptAug 6, 2026, 3:21:59 AM8.59 KiB
digilent_arty_a7_route_status.rptAug 6, 2026, 3:21:58 AM651 B
digilent_arty_a7_timing.rptAug 6, 2026, 3:21:59 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptAug 6, 2026, 3:21:26 AM3.22 KiB
digilent_arty_a7_utilization_place.rptAug 6, 2026, 3:21:26 AM10.57 KiB
e203_core.coreAug 6, 2026, 3:18:07 AM2.49 KiB
e203_soc.coreAug 6, 2026, 3:18:07 AM4.26 KiB
LICENSEAug 6, 2026, 3:18:07 AM11.09 KiB
processor_ci_defines.vhAug 6, 2026, 3:20:24 AM300 B
README.mdAug 6, 2026, 3:18:07 AM4.58 KiB