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.gitignoreAug 3, 2026, 3:18:11 AM46 B
build_digilent_arty_a7_100t.tclAug 3, 2026, 3:21:09 AM8.34 KiB
clockInfo.txtAug 3, 2026, 3:22:10 AM375 B
digilent_arty_a7_100t.bitAug 3, 2026, 3:23:12 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptAug 3, 2026, 3:22:17 AM16.56 KiB
digilent_arty_a7_control_sets.rptAug 3, 2026, 3:22:16 AM12.95 KiB
digilent_arty_a7_drc.rptAug 3, 2026, 3:22:52 AM2.34 KiB
digilent_arty_a7_io.rptAug 3, 2026, 3:22:16 AM96.81 KiB
digilent_arty_a7_power.rptAug 3, 2026, 3:22:52 AM8.59 KiB
digilent_arty_a7_route_status.rptAug 3, 2026, 3:22:50 AM651 B
digilent_arty_a7_timing.rptAug 3, 2026, 3:22:52 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptAug 3, 2026, 3:22:16 AM3.22 KiB
digilent_arty_a7_utilization_place.rptAug 3, 2026, 3:22:16 AM10.57 KiB
e203_core.coreAug 3, 2026, 3:18:11 AM2.49 KiB
e203_soc.coreAug 3, 2026, 3:18:11 AM4.26 KiB
LICENSEAug 3, 2026, 3:18:11 AM11.09 KiB
processor_ci_defines.vhAug 3, 2026, 3:21:09 AM300 B
README.mdAug 3, 2026, 3:18:11 AM4.58 KiB