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.gitignoreSep 4, 2026, 3:18:17 AM46 B
build_digilent_arty_a7_100t.tclSep 4, 2026, 3:20:42 AM8.34 KiB
clockInfo.txtSep 4, 2026, 3:21:40 AM375 B
digilent_arty_a7_100t.bitSep 4, 2026, 3:22:36 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptSep 4, 2026, 3:21:45 AM16.56 KiB
digilent_arty_a7_control_sets.rptSep 4, 2026, 3:21:45 AM12.95 KiB
digilent_arty_a7_drc.rptSep 4, 2026, 3:22:18 AM2.34 KiB
digilent_arty_a7_io.rptSep 4, 2026, 3:21:45 AM96.81 KiB
digilent_arty_a7_power.rptSep 4, 2026, 3:22:18 AM8.59 KiB
digilent_arty_a7_route_status.rptSep 4, 2026, 3:22:17 AM651 B
digilent_arty_a7_timing.rptSep 4, 2026, 3:22:18 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptSep 4, 2026, 3:21:45 AM3.22 KiB
digilent_arty_a7_utilization_place.rptSep 4, 2026, 3:21:45 AM10.57 KiB
e203_core.coreSep 4, 2026, 3:18:17 AM2.49 KiB
e203_soc.coreSep 4, 2026, 3:18:17 AM4.26 KiB
LICENSESep 4, 2026, 3:18:17 AM11.09 KiB
processor_ci_defines.vhSep 4, 2026, 3:20:42 AM300 B
README.mdSep 4, 2026, 3:18:17 AM4.58 KiB